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CS6105-Digital Fundamentals and Computer Organization Laboratory Experiment List

The document contains a list of 3 experiments for the course CS6105-Digital Fundamentals and Computer Organization. The first experiment aims to study basic logic gates like NOT, AND, OR, NAND, NOR, XOR and XNOR through hardware and simulation. It involves connecting logic gates to a digital trainer kit and power supply to observe input-output behavior and verify truth tables. The second experiment is on verifying Boolean theorems and axioms using logic gates. The third experiment is on realizing logic gates using universal gates.

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92 views4 pages

CS6105-Digital Fundamentals and Computer Organization Laboratory Experiment List

The document contains a list of 3 experiments for the course CS6105-Digital Fundamentals and Computer Organization. The first experiment aims to study basic logic gates like NOT, AND, OR, NAND, NOR, XOR and XNOR through hardware and simulation. It involves connecting logic gates to a digital trainer kit and power supply to observe input-output behavior and verify truth tables. The second experiment is on verifying Boolean theorems and axioms using logic gates. The third experiment is on realizing logic gates using universal gates.

Uploaded by

Historian Famous
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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CS6105-Digital Fundamentals and Computer Organization

Laboratory experiment list

Record submission date: 20-08-2020

1. Experiment 1: Digital Logic Gates: Verification and Interpretation of Logic Gates.

2. Experiment 2: Verification of Boolean Theorems and Axioms using basic logic

gates.

3. Experiment 3: Realization of Logic gates using Universal gates


Record work sample for your reference

Experiment 1: Digital Logic Gates: Verification and Interpretation of Basic Logic Gates.

Date:21/08/2020

Aim:
To study basic logic gates :NOT,AND,OR,NAND,NOR,XOR,XNOR
Requirements:
Hardware: Digital trainer kit, logic gates / ICs, wires.
Simulator: XILINX

Procedure:Hardware
1. Connect the digital trainer kit to power supply.
2. Connect the inputs of any one logic gate to the power supply and its output to the LED indicator.
3. Apply various input combinations and observe output for each one.
4. Verify the truth table for each input/ output combination.
5. Repeat the process for all other logic gates.
Procedure:Simulator
1. Open Xilinx ISE 13.4 version
2. Create a verilog module, specify the input and output port and then write the verilog module for
the given experiment.
3. Create a RTL Schematic of the given experiment.
4. Create a verilog test bench then write the verilog test module and compile.
5. View the simulation process that depicts timing diagram of the given experiment.

Description:
A logic gate is a physical model of a Boolean function that performs a logical operation on one or more
logic inputs and produces a single logic output. The input combinations of a logic gate are written in a
series, then their corresponding outputs are written by applying the respective Boolean and this input/
output combination is called Truth Table.

AND GATE:

AND gate produces an output as 1, when all its inputs are 1; otherwise the output is 0. This
gate can have minimum 2 inputs but output is always one. Its output is 0 when any input is 0.

IC No.: IC7408
A
Q
Symbolic Representation: B
Pin Diagram and Truth Table:

IC 7408

//all Logic gates


Structural module
module Logic_gates( Q, A, B);
input A,B;
output Q;
and(Q, A, B);
//All logic gates
endmodule

Behavioral module
module Logic_gates_br (Q, A, B);
output Q;
input A,B;
reg F;
always@(A,B)
begin
Q = A &B;
//All logic gates
end
endmodule

Test Bench
module testbench;
wire w1;
reg A, B;
Logic_gates(Q,A,B);
Initial
begin
#100 $finsih ;
end
Initial
begin
#10 A=0 ; B=0;
#10 A=0; B=1;
#10 A=1; B=0;
#10 A=1; B=1;
end
Initial
begin
$monitor(“time=%d A=%b B= % b Q= %b”, $time, A, B, Q);
end
Endmodule

OUTPUT
Screenshot of timing diagram and RTL schematic

Results
Thus the logic gates are verified under hardware and simulator.

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