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Universidad Nacional Mayor de San Marcos: Facultad de Ingenieria Electronica Y Electrica

This document contains VHDL code for several digital circuit problems. It includes code for a 4-bit adder, a 4-input multiplexer, binary addition of 16-bit vectors, and other logic circuits. The code specifies the ports, architecture, components, and logic for each circuit using VHDL syntax and constructs. Test vectors and testbenches are provided to simulate and verify the functionality of the described circuits.

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Jhulian Villafuerte
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39 views11 pages

Universidad Nacional Mayor de San Marcos: Facultad de Ingenieria Electronica Y Electrica

This document contains VHDL code for several digital circuit problems. It includes code for a 4-bit adder, a 4-input multiplexer, binary addition of 16-bit vectors, and other logic circuits. The code specifies the ports, architecture, components, and logic for each circuit using VHDL syntax and constructs. Test vectors and testbenches are provided to simulate and verify the functionality of the described circuits.

Uploaded by

Jhulian Villafuerte
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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UNIVERSIDAD NACIONAL MAYOR

DE SAN MARCOS
Universidad del Perú, DECANA DE AMERICA

FACULTAD DE INGENIERIA ELECTRONICA Y


ELECTRICA
 TEMA: Tarea VHDL-2
 CURSO: Circuitos Digitales
 PROFESOR: Ing. ALARCÓN MATUTTI RUBÉN
 ALUMNO:
 VILLAFUERTE HUAYLINOS, JHULIAN 15190138

2019 – 2
PROBLEMA 1

Codigo VHDL:

LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity problema523 is
port (Cin: in std_logic;
x3,x2,x1,x0 : in std_logic;
y3,y2,y1,y0 : in std_logic;
s3,s2,s1,s0: out std_logic;
Cout : out std_logic);
end problema523;
architecture solucion of problema523 is
signal c1,c2,c3: std_logic;
component fulladd
port (Cin,x,y: in std_logic;
s, Cout:out std_logic);
end component;
begin

stage0: fulladd port map (Cin,x0,y0,s0,c1);


stage1: fulladd port map (c1,x1,y1,s1,c2);
stage2: fulladd port map (c2,x2,y2,s2,c3);
stage3: fulladd port map (
Cin=>c3, Cout=>Cout, x=>x3, y=>y3,s=>s3);
end solucion;

Waveform Editor
LIBRARY work;

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

USE fulladd_package.all ;

ENTITY problema525 IS

PORT ( Cin : IN STD_LOGIC ;

x3, x2, x1, x0 : IN STD_LOGIC ;

y3, y2, y1, y0 : IN STD_LOGIC ;

s3, s2, s1, s0 : OUT STD_LOGIC ;

Cout : OUT STD_LOGIC ) ;

END problema525 ;

ARCHITECTURE Structure OF problema525 IS

SIGNAL c1, c2, c3 : STD_LOGIC ;

BEGIN

stage0: fulladd PORT MAP ( Cin, x0, y0, s0, c1 ) ;


stage1: fulladd PORT MAP ( c1, x1, y1, s1, c2 ) ;

stage2: fulladd PORT MAP ( c2, x2, y2, s2, c3 ) ;

stage3: fulladd PORT MAP (

Cin => c3, Cout => Cout, x => x3, y => y3, s => s3 ) ;

END Structure ;

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

USE ieee.std_logic_signed.all ;

ENTITY problema528 IS

PORT ( Cin : IN STD_LOGIC ;

X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;

S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ;

Cout, Overflow : OUT STD_LOGIC);

END problema528 ;

ARCHITECTURE Behavior OF problema528 IS

SIGNAL Sum : STD_LOGIC_VECTOR(16 DOWNTO 0) ;


BEGIN

Sum <= ('0'& X) + Y + Cin ;

S <= Sum(15 downto 0);

Cout <= Sum(16);

Overflow <= Sum(16) xor x(15) xor y(15) xor sum(15);

end behavior;

LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

USE ieee.std_logic_arith.all ;

ENTITY problema529 IS

PORT ( Cin : IN STD_LOGIC ;

X, Y : IN SIGNED(15 DOWNTO 0) ;

S : OUT SIGNED(15 DOWNTO 0) ;

Cout, Overflow : OUT STD_LOGIC ) ;

END problema529 ;

ARCHITECTURE Behavior OF problema529 IS


SIGNAL Sum : SIGNED(16 DOWNTO 0) ;

BEGIN

Sum <= ('0'& X) + Y + Cin ;

S <= Sum(15 downto 0);

Cout <= sum(16);

overflow <= sum(16) xor x(15) xor y(15) xor sum(15);

end behavior;

PROBLEMA 5.17
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY procinco IS
PORT( Input : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Output : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END procinco;
ARCHITECTURE LogicFunc OF procinco IS
BEGIN
WITH Input select
Output <= "0001" when "0101",
"0010" when "0110",
"0011" when "0111",
"0010" when "1001",
"0100" when "1010",
"0110" when "1011",
"0011" when "1101",
"0110" when "1110",
"1001" when "1111",
"0000" when OTHERS;
END LogicFunc ;

El
5.37 PROBLEMA: Escriba el código VHDL para especificar el circuito de la figura 5.36
LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_unsigned.all;

ENTITY problemita IS

PORT (X,Y: IN STD_LOGIC_VECTOR (3 DOWNTO 0);

S : OUT STD_LOGIC_VECTOR (4 DOWNTO 0));

END problemita ;

ARCHITECTURE Behavior OF problemita IS

SIGNAL Z: STD_LOGIC_VECTOR (4 DOWNTO 0);

SIGNAL Adjust: STD_LOGIC;

BEGIN

Z<= ('0'&X) +Y;

Adjust<= '1' WHEN Z>9 ELSE '0';

S<= Z WHEN Z<10 ELSE Z+6;

end behavior ;
PROBLEMA 5.11
LIBRARY IEEE;

USE IEEE.std_logic_1164.all;

ENTITY example8 is

PORT ( A: IN std_logic_vector (3 downto 0);

B: IN std_logic_vector (3 downto 0);

z, n, v : OUT std_logic );

end example8;

architecture sumador OF example8 IS

signal c : std_logic_vector (3 downto 0);

signal sum : std_logic_vector (3 downto 0);


begin

sum (0) <= A(0) xor not B(0) xor '1';

c(0) <= (A(0) and not B(0)) or ((A(0) xor not B(0)) and '1' );

sum (1) <= A(1) xor not B(1) xor c(0);

c(1) <= (A(1) and not B(1)) or ((A(1) xor not B(1)) and c(0));

sum (2) <= A(2) xor not B(2) xor c(1);

c(2) <= (A(2) and not B(2)) or ((A(2) xor not B(2)) and c(1));

sum (3) <= A(3) xor not B(3) xor c(2);

c(3) <= (A(3) and not B(3)) or ((A(3) xor not B(3)) and c(2));

z<= not(sum(0) or sum(1) or sum(2) or sum(3));

v<= (c(3) xor c(2));

n<=sum(3);

END sumador ;

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