AHDL Vs Graphical Programming

AHDL vs Graphical Programming
Graphical logic design

Advantage
Easier than wiring physical gates
Disadvantage
We still need to know which gates to use and how to connect
them
ADHL design using the Quartus Text Editor
Advantage
We just tell Quartis software how to program our PLD and it
determines the individual connections
Disadvantage
Initial setup cost means it can be more time consuming for
simple designs
VHDL vs AHDL
VHDL (Very-high-speed-integrated-circuit Hardware
Description Language)
• VHDL, which was the first HDL to be created. Unfortunately,
VHDL can get over-complex.
AHDL (Altera Hardware Description Language)
• Because of this, Altera created their own HDL, namely
AHDL. AHDL is aimed squarely at digital systems, which
makes is use simpler, but it is just as powerful. This unit
concentrates on the AHDL aspects.
Note: The textbook provides examples for both AHDL and

VHDL
AHDL vs C?
C is a sequential language and AHDL is a concurrent
language
C describes a series of processes to be performed in
sequence
AHDL describes logical operations which are
performed concurrently
A = B;
A = C;
In C, A is equal to B, then, A is equal to C.
In AHDL A can be equal to B or it can be equal to C;
AHDL Basic Format
The basic format of a subdesign is as follows:
SUBDESIGN designname
(
list of inputs : INPUT;
list of outputs : OUTPUT;
)
VARIABLE
List of variables required;
BEGIN
Description in the form of “C” like code;
END;
AHDL Example 8-bit counter
SUBDESIGN time_cnt
(
enable, clk : INPUT;
time[7..0] : OUTPUT; List of I/O
)
VARIABLE
count[7..0] : DFF; Variable declaration
BEGIN
count[].clk = clk;
time[] = count[].q;
If enable THEN
count[].d = count[].q + 1; Logic
ELSE
count[].d = count[].q;
END IF;
END;
The name of the text file must
SUBDESIGN time_cnt be the same as the subdesign
( name ie. time_cnt.TXT
enable, clk : INPUT; Two single bit inputs
time[7..0] : OUTPUT; One 8 bit output. This is an
) 8 bit register
VARIABLE
count[7..0] : DFF; One 8 bit variable, formed
by 8 D-type flip-flops
BEGIN A DFF has 4 inputs, d, clk,

prn, clrn and one output q
........
……. Start of Logic design
BEGIN
Links the clk (clock) input of every DFF
count[].clk = clk; in count to the input clk
time[] = count[]; Links the time output to the count outputs
If enable THEN Conditional Logic. Ie. If Enable is HIGH
count[].d = count[].q + 1; All the d inputs of count[ ]
are set to all the q outputs of
ELSE count[ ] + 1 Ie. Counter
count[].d = count[].q; increments
END IF; The d inputs of count[ ] are

kept at the previous state
END; End of Logic design
The overall functionality is that when the enable input is HIGH the binary number in count[ ]
increments on every clock pulse. If enable is LOW nothing changes.
1 is not added to every q
count[].d = count[].q + 1; output. The [ ] denotes all
devices in range, Ie. count[7] to
count [0]
All the q outputs are treated as
an 8-bit binary number and 1
is added to the number.
Refers to the individual

count[3].q output of D flip-flip 3
% Comments should be included % “%” will start the comments

% To help the programmer % and another “%” will end
the comments
% remember how the code works %
AHDL Example – The D-latch
Lets see how AHDL can match a low-level

D Q
device (the D latch)
Enable Q Remember the D-latch is similar to a D-flip

flop, however the D-latch is level-triggered
Symbol for a D-latch (Enable) and the D-flip flop is edge-triggered
(Clock)
Step 1: Define the Inputs and Outputs
Subdesign DLatch
(
D, Enable : input; % Declaration of inputs %
Q, NOTQ : output; % Declaration of outputs %
)
AHDL Example – The D-latch
Step 2: Variable Declaration

As this is a simple task no variable declaration is required
Step 3: Logic Design

We need to use AHDL to describe the internal workings of the
devices logic
BEGIN
IF enable THEN % If enable is HIGH %
Q = D; % The output equals input %
ELSE % If enable is not HIGH %
Q = Q; % No change %
END IF;
NOTQ = !Q; % NotQ opposite of Q %
END;
Quartus in SEE202
Quartus Version
There have been issues with using the latest version of Quartus
(v12.1 Service Pack) making it unnecessarily difficult to simulate
our AHDL designs
In order to simplify things it is best if we use Quartus II 9.1 Sp2

Web edition. There is little difference with the latest version except
there is an internal simulator which makes simulation of our digital
circuits very straightforward
Quartus II 9.1 Sp2 Web edition can be downloaded from

https://www.altera.com/download/software/quartus-ii-we
Quartus in SEE202
Quartus Version
Aside from preventing us from pulling our hair out simulating our
AHDL designs, version 9.1 allows you to use the ‘MAX+PLUS II’
look which can be useful to those familiar with MAX+PLUS II or
are referring to the study guides
Simulating our designs in Quartus
The D flip-flop AHDL design and simulation
Lets look at designing a D flip-flop in AHDL and simulating it

using Quartus’ built in simulator
Lets see how AHDL can use an existing device
D Q
Remember the D-flip flop is edge-triggered

Clk Q (Clock)
Symbol for a D-flip flop
We could consider the internal workings of the device as we did

for the D-latch, however we will use the existing DFF device
D flip-flop - AHDL design and simulation
SUBDESIGN DflipFlop
(
D, Clk : INPUT;
Q, NOTQ : OUTPUT;
)
VARIABLE
DFLIPFLOP : DFF;
BEGIN
DFLIPFLOP.clk = Clk;
DFLIPFLOP.d = D;
Q = DFLIPFLOP.q;
NOTQ = !DFLIPFLOP.q;
END;
Now lets look at how to simulate and test our design
First create a new project
Then setup a working directory, project name

and top level design name
Choose the device we will simulate our

AHDL running on
Then press Finish
Create a new AHDL file

Enter the AHDL for the Dflipflop and save the file to the project
directory
NOTE : Make sure the

SUBDESIGN name,
.tdf file name and
project name are the
same.
Compile your project
You should have

‘0 errors’ and
successful compilation
Create a new Vector Waveform file
Save with same name, i.e. dflipflop

Right click and choose to insert node or bus
Then click node finder

Click ‘List’ to show the inputs and outputs of our design

Click ‘>’ to bring the selected inputs and outputs into the
simulation and then press OK and OK again
The selected I/O are now in the vector waveform file and we are
close to being able to simulate
Assign a clock signal to Clk
Choose suitable parameters

Set other inputs to appropriate values, i.e. a 1 at D for the time

shown
Now we can simulate the design!

We can now see the simulated output for the inputs we specified!
Why doesn’t Q change to D exactly at the rising edge of Clk?
Because of propagation delay time!

AHDL design and simulation
Now that we know how to simulate lets look at more AHDL design
Using the JKFF primitive and write the subdesign in AHDL

SUBDESIGN JKFFSimple
(
j, k, clock, prn, clrn : INPUT;
q, notq : OUTPUT;
)
VARIABLE
JK : JKFF;
BEGIN
JK.clk = clock;
jk.j = j;
jk.k = k;
jk.prn = prn;
jk.clrn = clrn;
q = jk.q;
notq = !jk.q;
END;
Lets consider the AND gate
Without using the AND primitive write the subdesign in AHDL

SUBDESIGN and_gate
(
a,b : INPUT;
y : OUTPUT;
)
BEGIN
y = a & b;
END;
Write the AHDL for an 8-bit shift register

SUBDESIGN shift_reg
(
clk, ser_in : INPUT;
q[7..0] : OUTPUT;
)
VARIABLE
ff[7..0] : DFF;
BEGIN
ff[].clk=clk;
ff[7..0].d=(ser_in, ff[7..1].q);
q[]=ff[];
END;

AHDL Vs Graphical Programming

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AHDL vs Graphical Programming

Graphical logic design

Note: The textbook provides examples for both AHDL and

BEGIN A DFF has 4 inputs, d, clk,

END IF; The d inputs of count[ ] are

Refers to the individual

% Comments should be included % “%” will start the comments

Lets see how AHDL can match a low-level

Enable Q Remember the D-latch is similar to a D-flip

Step 1: Define the Inputs and Outputs

Step 2: Variable Declaration

Step 3: Logic Design

In order to simplify things it is best if we use Quartus II 9.1 Sp2

Quartus II 9.1 Sp2 Web edition can be downloaded from

The D flip-flop AHDL design and simulation

Lets look at designing a D flip-flop in AHDL and simulating it

Remember the D-flip flop is edge-triggered

Symbol for a D-flip flop

We could consider the internal workings of the device as we did

Now lets look at how to simulate and test our design

First create a new project

Then setup a working directory, project name

Choose the device we will simulate our

Then press Finish

Create a new AHDL file

NOTE : Make sure the

Compile your project

You should have

Create a new Vector Waveform file

Save with same name, i.e. dflipflop

Right click and choose to insert node or bus

Then click node finder

Click ‘List’ to show the inputs and outputs of our design

Assign a clock signal to Clk

Choose suitable parameters

Set other inputs to appropriate values, i.e. a 1 at D for the time

Now we can simulate the design!

Why doesn’t Q change to D exactly at the rising edge of Clk?

Because of propagation delay time!

Using the JKFF primitive and write the subdesign in AHDL

Lets consider the AND gate

Without using the AND primitive write the subdesign in AHDL

Write the AHDL for an 8-bit shift register

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