FDS6612A Single N-Channel, Logic-Level, PowerTrench MOSFET

April 2007

FDS6612A
tm
Single N-Channel, Logic-Level, PowerTrench MOSFET
General Description Features
This N-Channel Logic Level MOSFET is produced • 8.4 A, 30 V. RDS(ON) = 22 mΩ @ VGS = 10 V
using Fairchild Semiconductor’s advanced
PowerTrench process that has been especially tailored RDS(ON) = 30 mΩ @ VGS = 4.5 V
to minimize the on-state resistance and yet maintain
superior switching performance. • Fast switching speed

These devices are well suited for low voltage and • Low gate charge
battery powered applications where low in-line power
loss and fast switching are required. • High performance trench technology for extremely
low RDS(ON)

• High power and current handling capability

DD 5 4
DD
DD 6 3
DD
7 2
SO-8 G
SS G 8 1
S
Pin 1 SO-8 SS S

Absolute Maximum Ratings TA=25oC unless otherwise noted

Symbol Parameter Ratings Units

VDSS Drain-Source Voltage 30 V
VGSS Gate-Source Voltage ±20 V
ID Drain Current – Continuous (Note 1a) 8.4 A
– Pulsed 40
PD Power Dissipation for Single Operation (Note 1a) 2.5 W
(Note 1b) 1.0
EAS Single Pulse Avalanche Energy (Note 3) 24 mJ
TJ, TSTG Operating and Storage Junction Temperature Range –55 to +150 °C

Thermal Characteristics
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 50 °C/W
RθJA Thermal Resistance, Junction-to-Ambient (Note 1b) 125
RθJC Thermal Resistance, Junction-to-Case (Note 1) 25

Package Marking and Ordering Information

Device Marking Device Reel Size Tape width Quantity
FDS6612A FDS6612A 13’’ 12mm 2500 units

2007 Fairchild Semiconductor Corporation FDS6612A Rev D1 (W)

 FDS6612A Single N-Channel, Logic-Level, PowerTrench MOSFET
Electrical Characteristics TA = 25°C unless otherwise noted

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics
BVDSS Drain–Source Breakdown Voltage VGS = 0 V, ID = 250 µA 30 V
∆BVDSS Breakdown Voltage Temperature
ID = 250 µA, Referenced to 25°C 26 mV/°C
∆TJ Coefficient
IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V 1 µA
VDS = 24 V, VGS = 0 V, TJ=55°C 10 µA
IGSS Gate–Body Leakage VGS = ±20 V, VDS = 0 V ±100 nA

On Characteristics (Note 2)
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA 1 1.9 3 V
∆VGS(th) Gate Threshold Voltage ID = 250 µA, Referenced to 25°C
–4.4 mV/°C
∆TJ Temperature Coefficient
RDS(on) Static Drain–Source VGS = 10 V, ID = 8.4 A 19 22 mΩ
On–Resistance VGS = 4.5 V, ID = 7.2 A 24 30
VGS= 10 V, ID = 8.4 A, TJ=125°C 25 37
ID(on) On–State Drain Current VGS = 10 V, VDS = 5 V 20 A
gFS Forward Transconductance VDS = 15 V, ID = 8.4 A 30 S
Dynamic Characteristics
Ciss Input Capacitance VDS = 15 V, V GS = 0 V, 560 pF
Coss Output Capacitance f = 1.0 MHz 140 pF
Crss Reverse Transfer Capacitance 55 pF
RG Gate Resistance VGS = 15 mV, f = 1.0 MHz 2.5 Ω
Switching Characteristics (Note 2)

td(on) Turn–On Delay Time VDD = 15 V, ID = 1 A, 7 14 ns

tr Turn–On Rise Time VGS = 10 V, RGEN = 6 Ω 5 10 ns
td(off) Turn–Off Delay Time 22 35 ns
tf Turn–Off Fall Time 3 6 ns
Qg Total Gate Charge VDS = 15 V, ID = 8.4 A, 5.4 7.6 nC
Qgs Gate–Source Charge VGS = 5 V 1.7 nC
Qgd Gate–Drain Charge 1.9 nC
Drain–Source Diode Characteristics and Maximum Ratings
IS Maximum Continuous Drain–Source Diode Forward Current 2.1 A
Drain–Source Diode Forward
VSD VGS = 0 V, IS = 2.1 A (Note 2) 0.77 1.2 V
Voltage
trr Diode Reverse Recovery Time 19 nS
IF = 8.4 A, diF/dt = 100 A/µs
Qrr Diode Reverse Recovery Charge 9 nC

Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. RθJC is guaranteed by design while RθCA is determined by the user'
s board design.

a) 50°C/W when mounted b) 125°C/W when mounted on a

on a 1in2 pad of 2 oz minimum pad.
copper

Scale 1 : 1 on letter size paper

2 Test: Pulse Width < 300µs, Duty Cycle < 2.0%

3 Starting TJ = 25°C, L = 1mH, IAS = 7A, VDD = 27V, VGS = 10V

FDS6612A Rev D1 (W)

 FDS6612A Single N-Channel, Logic-Level, PowerTrench MOSFET
Typical Characteristics

40 2
VGS = 10V 4.5V VGS = 3.5V

DRAIN-SOURCE ON-RESISTANCE
4.0V 1.8
30 6.0V
ID, DRAIN CURRENT (A)

RDS(ON), NORMALIZED
1.6

4.0V
20 1.4
3.5V 4.5V
5.0V
1.2
6.0V
10
10V
1
3.0V

0 0.8
0 0.5 1 1.5 2 2.5 3 0 10 20 30 40
VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)

Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with

Drain Current and Gate Voltage.

1.6 0.1
ID = 8.4A
ID = 4.2A
VGS = 10V
DRAIN-SOURCE ON-RESISTANCE

RDS(ON), ON-RESISTANCE (OHM)

1.4 0.08
RDS(ON), NORMALIZED

1.2 0.06

TA = 125oC
1 0.04

TA = 25oC
0.8 0.02

0.6 0
-50 -25 0 25 50 75 100 125 150 2 4 6 8 10
TJ, JUNCTION TEMPERATURE (oC) VGS, GATE TO SOURCE VOLTAGE (V)

Figure 3. On-Resistance Variation with Figure 4. On-Resistance Variation with

Temperature. Gate-to-Source Voltage.

40 100
VGS = 0V
VDS = 5V
IS, REVERSE DRAIN CURRENT (A)

10
30
ID, DRAIN CURRENT (A)

1
TA = 125oC

20 0.1
25oC
TA = 125oC

-55oC 0.01
-55oC
10
0.001

25oC
0 0.0001
1.5 2 2.5 3 3.5 4 4.5 0 0.2 0.4 0.6 0.8 1 1.2
VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)

Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation

with Source Current and Temperature.

FDS6612A Rev D1 (W)

 FDS6612A Single N-Channel, Logic-Level, PowerTrench MOSFET
Typical Characteristics

10 800
f = 1 MHz
ID = 8.4A
VGS = 0 V
VGS, GATE-SOURCE VOLTAGE (V)

8
VDS = 10V 600
20V

CAPACITANCE (pF)
6 Ciss
15V 400

Coss
200
2

Crss
0 0
0 2 4 6 8 10 12 0 5 10 15 20 25 30
Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)

Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics.

100
100
100µs
RDS(ON) LIMIT 1ms
IAS, AVALANCHE CURRENT (A)

10
ID, DRAIN CURRENT (A)

10ms
100ms
1s
10s
1 10
DC
25

VGS = 10V
0.1
SINGLE PULSE 125
RθJA = 125oC/W
o
TA = 25 C
1
0.01
0.001 0.01 0.1 1 10 100
0.01 0.1 1 10 100
tAV, TIME IN AVALANCHE (mS)
VDS, DRAIN-SOURCE VOLTAGE (V)

Figure 9. Maximum Safe Operating Area. Figure 10. Unclamped Inductive Switching
Capability

50

40 SINGLE PULSE
P(pk),PEAK TRANSIENT POWER (W)

RθJA = 125oC/W
TA = 25oC
30

20

10

0
0.001 0.01 0.1 1 10 100

t 1, TIME (sec)

Figure 11. Single Pulse Maximum Power Dissipation.

FDS6612A Rev D1 (W)

 FDS6612A Single N-Channel, Logic-Level, PowerTrench MOSFET
Typical Characteristics
TRANSIENT THERMAL RESISTANCE
1
r(t), NORMALIZED EFFECTIVE

D = 0.5

RθJA(t) = r(t) * RθJA

0.2
o
0.1 RθJA = 125 C/W
0.1
0.05
P(pk)
0.02
0.01 t1
0.01 t2
TJ - T A = P * RθJA(t)
SINGLE PULSE Duty Cycle, D = t1 / t2

0.001
0.0001 0.001 0.01 0.1 1 10 100 1000
t1, TIME (sec)

Figure 12. Transient Thermal Response Curve.

Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.

FDS6612A Rev D1 (W)

 FDS6612A Single N-Channel, Logic-Level, PowerTrench MOSFET
PSPICE Electrical Model N-Channel
.SUBCKT FDS6612A 2 1 3
*NOM TEMP=25 DEG C
*REV A - JULY 2003

CA 12 8 1E-9
CB 15 14 4.0E-10
CIN 6 8 5.1E-10
LDRAIN
DPLCAP 5 DRAIN
DBODY 7 5 DBODYMOD 2
DBREAK 5 11 DBREAKMOD 10
DPLCAP 10 5 DPLCAPMOD RLDRAIN
RSLC1
51 DBREAK
EBREAK 11 7 17 18 34.2 RSLC2
+
EDS 14 8 5 8 1 5 ESLC
51 11
EGS 13 8 6 8 1 -
ESG 6 10 6 8 1 50 +
-
EVTHRES 6 21 19 8 1 6 RDRAIN 17 DBODY
EVTEMP 20 6 18 22 1 ESG EBREAK 18
8
EVTHRES -
+ 16
+ 19 - 21
IT 8 17 1 MWEAK
LGATE EVTEMP 8
GATE RGATE + 6
LGATE 1 9 3.84E-9 18 -
1 MMED
LDRAIN 2 5 1.00E-9 9 20 22
RLGATE MSTRO
LSOURCE 3 7 4E-9
LSOURCE
CIN SOURC E
8
RLGATE 1 9 38.4 7
3
RLDRAIN 2 5 10 RSOURCE
RLSOURCE 3 7 40 RLSOURCE
S1A S2A
12 RBREAK
MMED 16 6 8 8 MMEDMOD 13 14 15
17 18
MSTRO 16 6 8 8 MSTROMOD 8 13
MWEAK 16 21 8 8 MWEAKMOD S1 B S2B RVTEMP
13 CB 19
RBREAK 17 18 RBREAKMOD 1 CA
14 IT -
+ +
RDRAIN 50 16 RDRAINMOD 8E-3 VBAT
RGATE 9 20 4.2 6 5
EGS EDS +
8 8
- - 8
RSLC1 5 51 RSLCMOD 1E-6 22
RSLC2 5 50 1E3 RVTHRES
RSOURCE 8 7 RSOURCEMOD 7.5E-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1E-6*105),3))}

.MODEL DBODYMOD D (IS=7E-15 RS=6.1E-3 N=0.84 TRS1=1.7E-3 TRS2=1.0E-6

+ CJO=3.2E-10 TT=10E-9 M=0.5 IKF=0.3 XTI=3.0)
.MODEL DBREAKMOD D (RS=1E-1 TRS1=1.12E-3 TRS2=1.25E-6)
.MODEL DPLCAPMOD D (CJO=14E-11 IS=1E-30 N=10 M=0.34)
.MODEL MWEAKMOD NMOS (VTO=1.82 KP=0.05 IS=1E-30 N=10 TOX=1 L=1U W=1U RG=42 RS=.1)
.MODEL MMEDMOD NMOS (VTO=2.1 KP=6 IS=1E-30 N=10 TOX=1 L=1U W=1U RG=4.2)
.MODEL MSTROMOD NMOS (VTO=2.55 KP=50 IS=1E-30 N=10 TOX=1 L=1U W=1U)
.MODEL RBREAKMOD RES (TC1=0.83E-3 TC2=1E-7)
.MODEL RDRAINMOD RES (TC1=6E-3 TC2=5E-6)
.MODEL RSLCMOD RES (TC1=2.5E-3 TC2=4.5E-6)
.MODEL RSOURCEMOD RES (TC1=1.0E-3 TC2=1E-6)
.MODEL RVTHRESMOD RES (TC1=-2.013E-3 TC2=-7E-6)
.MODEL RVTEMPMOD RES (TC1=-1.5E-3 TC2=1E-6)

.MODEL S1AMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-4 VOFF=-3)

.MODEL S1BMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-3 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-1.3 VOFF=-0.5)
.MODEL S2BMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-0.5 VOFF=-1.3)

.ENDS

Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

FDS6612A Rev D1 (W)

 FDS6612A Single N-Channel, Logic-Level, PowerTrench MOSFET
SPICE Thermal Model

.SUBCKT FDS6612A_THERM TH TL th JUNCTION

*THERMAL MODEL SUBCIRCUIT
*REV A - JULY 2003
*MIN PAD RJA
RTHERM1 CTHERM1
CTHERM1 TH 8 0.005
CTHERM2 8 7 0.05 8

CTHERM3 7 6 0.10
RTHERM2 CTHERM2
CTHERM4 6 5 0.35
CTHERM5 5 4 0.45
7
CTHERM6 4 3 0.50
CTHERM7 3 2 0.55
RTHERM3 CTHERM3
CTHERM8 2 TL 3.00
6
RTHERM1 TH 8 5.000
RTHERM2 8 7 6.250
RTHERM4 CTHERM4
RTHERM3 7 6 7.500
RTHERM4 6 5 8.750 5
RTHERM5 5 4 10.625
RTHERM6 4 3 11.875 RTHERM5 CTHERM5
RTHERM7 3 2 31.250
RTHERM8 2 TL 43.750 4

.ENDS RTHERM6 CTHERM6

RTHERM7 CTHERM7

RTHERM8 CTHERM8

tl AMBIENT

FDS6612A Rev D1 (W)

 tm

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PRODUCT STATUS DEFINITIONS

Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In Design This datasheet contains the design specifications for product
development. Specifications may change in any manner
without notice.

Preliminary First Production This datasheet contains preliminary data; supplementary data will
be published at a later date. Fairchild Semiconductor reserves the
right to make changes at any time without notice to improve
design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at any time
without notice to improve design.

Obsolete Not In Production This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor.The datasheet is printed
for reference information only.

Rev. I26

©2007 Fairchild Semiconductor Corporation www.fairchildsemi.com