EEE 270

Advanced Topics In Logic Design

Control and Sequencing: Hardwired

and Microprogrammed Control

References:
Chapter s 4,5 from textbook
Chapter 7 of M.M. Mano and C.R. Kime, Logic and Computer
Design Fundamentals, Pearson Prentice-Hall, 2008.
Cris Ababei, Marquette University
Overview

 Control and Sequencing

• Algorithmic State Machine (ASM) Chart of
Multiplier
• Hardwired control
• Microprogrammed control

2
 Multiplier Example
 Example: (101 x 011)

 Partial products are:

1 0 1
101 x 0, 101 x 1, and 101 x 1 x 0 1 1
1 0 1
1 0 1
0 0 0
0 0 1 1 1 1

3
Example (1 0 1) x (0 1 1) again
 Reorganizing to follow hardware algorithm:
1 0 1 Multiplicand (B)
x 0 1 1 Multiplier (Q)
0 0 0 0 Clear C || A (Carry and register A)
+ 1 0 1 Multiplier0 = 1 => Add B
0 1 0 1 Addition
0 0 1 0 1 Shift Right (Zero-fill C)
+ 1 0 1 Multiplier1 = 1 => Add B
0 1 1 1 1 Addition
0 0 1 1 1 1 Shift Right
0 0 0 1 1 1 1 Multiplier2 = 0 => No Add, Shift
Right
Multiplier Example: Block Diagram
n- 1 IN
n
Multiplicand

Counter P Register B

log 2 n n

Zero detect
G (Go) C
out Parallel adder

Z n n
Control Qo Multiplier
unit
0 C Shift register A Shift register Q

4
n

Control signals Product

OUT
 Multiplier Example: Operation

1. The multiplicand is loaded into register B.

2. The multiplier is loaded into register Q.
3. When G becomes 1, register C|| A is initialized to 0.
4. Down Counter P is initialized to n – 1 (n = number of bits in
multiplier)
5. The partial products are formed in register C||A||Q.
6. Each multiplier (Q) bit, beginning with the LSB, is processed (if bit is
1, B is added to partial product of A; if bit is 0, do nothing)
7. C||A||Q is shifted right using the shift register
• Partial product bits fill vacant locations in Q as multiplier is shifted out
• If overflow during addition, the outgoing carry is recovered from C
during the right shift
8. Steps 6 and 7 are repeated until P = 0 as detected by Zero detect.
Multiplier Example: ASM Chart
IDLE

MUL0

0 1
G
0 1
Q0
C ← 0, A ← 0
P ←n – 1
A ← A + B,
C ← Cout

MUL1
C ← 0, C || A || Q ← sr C || A || Q,
P← P–1

0 1
Z
7
 Multiplier Example: ASM Chart (Contd.)

 Three states are necessary to implement

multiplier
• IDLE state:
 Input G is used as the condition for starting the multiplication
 C, A, and P are initialized
• MUL0 state: conditional addition is performed based
on the value of Q0.
• MUL1 state:
 Right shift is performed to capture the partial product and
position the next bit of the multiplier in Q0
 Down counter P = P - 1
 P=0 is used to sense completion or continuation of the
multiplication.
Control and sequencing

 The ASM chart provides information about

• Control of the microoperations (control word)
• Sequencing of these operations
 The design can be split up in two parts:
• Control signals
• Sequencing

9
 Control signals for multiplier
n- 1 IN
n
Multiplicand
Initialize
Load_B
Shift_dec Counter P Register B

log2 n n

Zero detect
G (Go) C
out Parallel adder

Z n Load n
Control Qo Multiplier
unit Load_Q
0 C Shift register A Shift register Q

4
n
Clear_C
Initialize Product
Control signals Shift_dec
OUT
10
Multiplier Example: Control Signal Table
Control Signals for Binary Multiplier

Block diagram Microoperation Control Control signal

module signal name expression

Register A: A←0 Initialize IDLE · G

A← A + B Load MUL0 Q0
C || A || Q ← sr C || A || Q ·Shift_dec MUL1
Register B: B ← IN Load_B LOADB
Flip-Flop C: C ←0 Clear_C IDLE · G + MUL1
C ← C out Load —
Register Q: Q ← IN Load_Q LOADQ
C || A || Q ← sr C || A || Q Shift_dec —
Counter P: P← n–1 Initialize —
P ←P–1 Shift_dec —

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Multiplier Example: Control Signal Table (Contd.)

 Signals are defined on a register basis

 LOAD_Q and LOAD_B: external signals controlled from

the system using the multiplier and will not be
considered a part of this design

 Some control signals are “reused” for different registers.

• Four control signals are the “outputs” of the control unit:
initialize, load, shift_dec, clear_c

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Multiplier Example – Sequencing part of ASM

 With the outputs IDLE 00

represented by the
table, they can be
removed from the 0 1
G
ASM making the
ASM to represent MUL0 01
only the sequencing
(next state) behavior
 Simplified ASM
MUL1 10
chart. Similar to a
state diagram/graph
but without outputs
specified. 0
Z
1

13
Overview

 Control and Sequencing

• Algorithmic State Machine (ASM) Chart of
Multiplier
• Hardwired control
• Microprogrammed control

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 Control

 Hardwired Control
• Implemented using gates and flip-flops
• Faster, less flexible, limited complexity
 Microprogram Control
• Control Store
 Memory storing control signals and next state info
 Controller sequences through memory
• Slower, more flexible, greater complexity

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 Hardwired control

 Control Design Methods

• (1) Sequential circuit techniques; studied earlier in
this course
• Procedure specializations that use a single signal to
represent each state
 (2) Sequence Register and Decoder
• Sequence register with encoded states, e.g., 00, 01, 10, 11.
• Decoder outputs produce “state” signals, e.g., 0001, 0010,
0100, 1000.
 (3) One Flip-Flop per State
• Flip-flop outputs as “state” signals, e. g., 0001, 0010, 0100,
1000.

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(2) Sequencer (sequence register) and Decoder

 Use a register to represent the states and a decoder to

generate an output signal corresponding to each state
 Use the State Table to find the input logic

Input Logic

17
Multiplier Example: Sequencer and Decoder
Design - Specification
 Define:
• States: IDLE, MUL0, MUL1
• Input Signals: G, Z, Q0 (Q0 affects outputs, not next state)
• Output Signals: Initialize, Load, Shift_Dec, Clear_C
• State Transition Diagram (Use Sequencing ASM)
• Output Function: Use Control Signal Table
• Decide on type of flip-flops to use
 Find: State M1 M0
• State Assignments IDLE 0 0
• Use two state bits to encode MUL0 0 1
the three states IDLE, MUL0,
and MUL1. MUL1 1 0
Unused 1 1
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Multiplier Example: Sequencer and Decoder
Design - Formulation

 Assuming that state variables M1 and M0 are decoded into states,

the next state part of the State Table is:

Current State Input Next State Current State Input Next State
G Z M1 M0 G Z M1 M0

IDLE 0 0 0 0 MUL1 0 0 0 1
IDLE 0 1 0 0 MUL1 0 1 0 0
IDLE 1 0 0 1 MUL1 1 0 0 1
IDLE 1 1 0 1 MUL1 1 1 0 0
MUL0 0 0 1 0 Unused 0 0 d d
MUL0 0 1 1 0 Unused 0 1 d d
MUL0 1 0 1 0 Unused 1 0 d d
MUL0 1 1 1 0 Unused 1 1 d d

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State Table with Decoder Outputs

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Multiplier Example: Sequencer and Decoder
Design - Equations Derivation/Optimization
 Finding the equations for M1 and M0 using decoded states:
M1 = MUL0
M0 = IDLE · G + MUL1 · Z
 The output equations using the decoded states:
Initialize = IDLE · G
Load = MUL0 · Q0
Clear_C = IDLE · G + MUL1
Shift_dec = MUL1
 Doing multiple level optimization, extract IDLE·G:
START = IDLE · G
M1 = MUL0
M0 = START + MUL1 · Z
Initialize = START
Load = MUL0 · Q0
Clear_C = START + MUL1
Shift_dec = MUL1
 The resulting circuit using flip-flops, a decoder, and the above
equations is given on the next slide.

21
Multiplier Example: Sequencer and Decoder
Design - Implementation

START
Initialize
G M0
D Clear_C
Z C DECODER
IDLE
A0 0
1 MUL0
2 MUL1 Shift_dec
A1 3
M1
D

Load
Q0

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--Binary multiplier with n=4
library ieee; VHDL code: behavioral datapath_func : process (CLK)
use ieee.std_logic_unsigned.all; variable CA : std_logic_vector (4 downto 0);
3 processes begin
entity binary_multiplier is
port(CLK, RESET, G, LOADB, LOADQ : in std_logic; if (CLK'event and CLK='1') then
MULT_IN : in std_logic_vector (3 downto 0); if LOADB='1' then
MULT_OUT : out std_logic_vector (7 downto 0)); B <= MULT_IN;
end binary_multiplier; end if;
if LOADQ = '1' then
architecture behavior_4 of binary_multiplier is
type state_type is (IDLE, MUL0, MUL1); Q <= MULT_IN;
variable P :=3; end if;
signal state, next_state : state_type;
signal A, B, Q : std_logic_vector(3 downto 0); case state is
signal C, Z : std_logic;
when IDLE =>
begin
Z <= P(1) NOR P(0); if G = '1' then
MULT_OUT <= A & Q; C <= '0';
A <= "0000";
state_register : process (CLK, RESET) P <= "11";
begin
end if;
if (RESET = '1') then
state <= IDLE; when MUL0 =>
elsif (CLK'event and CLK='1') then if Q(0) ='1' then
state <= next_state; CA := ('0' & A) + ('0' & B);
endif; else
end process;
CA := C & A;
next_state_func : process (G, Z, state) end if;
begin C <= CA(4);
case state is A <= CA(3 downto 0);
when IDLE => when MUL1 =>
if G='1' then next_state <= MUL0;
C <= '0';
else next_state <= IDLE;
end if; A <= C & A(3 downto 1);
when MUL0 => Q <= A(0) & Q(3 downto 1);
next_state <= MUL1; P <= P - "01";
when MUL1 => end case;
if Z='1' then next_state <= IDLE;
end if;
else next_state <= MUL0;
end if; end process;
end case; 23
end process; end behavior_4;
(3) One Flip-Flop per State

 This method uses one flip-flop per state and a simple

set of transformation rules to implement the circuit.
 The design starts with the ASM chart, and replaces
1. State Boxes with flip-flops,
2. Scalar Decision Boxes with a demultiplexer with 2 outputs,
3. Vector Decision Boxes with a (partial) demultiplexer,
4. Junctions with an OR gate, and
5. Conditional Outputs with AND gates.
 More flip-flops needed than in previous method

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State box and Scalar decision box transformations
 Vector decision box transformation

 Each Decision box transforms to a Demultiplexer

 Entry point is Enable inputs
 The Conditions are the Select inputs
 Demultiplexer Outputs are the Exit points

(Binary Vector Values) (Binary Vector Values) DEMUX

Entry EN D0 Exit 0
00 (Vector of Input 10
Conditions) X1 A1 D1 Exit 1
01 X0 A0 D2 Exit2
X1, X0
D3 Exit 3
Junction transformation, Conditional output box
transformation
Logic Diagram
Overview

 Control and Sequencing

• Algorithmic State Machine (ASM) Chart of
Multiplier
• Hardwired control
• Microprogrammed control
 Datapath + Control unit/path

 Datapath - performs data transfer and processing operations

 Control unit/path - determines the enabling and sequencing of the
operations

Describe properties of
the state of the datapath

Status signals

Control Control Control signals

inputs Datapath
unit
Data
outputs
Control Data
outputs inputs
Datapath + Control unit/path

 Datapath:
• Registers
• MUXes, ALUs, Shifters, Combinational Circuits and Buses
• Implements microoperations (under control of the control
unit)
 Control unit:
• Selects the microoperation
• Determines the sequence (based on status and input
signals)
• Design:
 State diagram or ASM
 Microoperations
 Sequence
Multiplier Example
 Microprogrammed Control

 Is a control unit whose control words are

stored in memory, called control memory.
 A control word contains a microinstruction
that specifies one or more microoperations.
 A sequence of microinstructions is called a
microprogram.
 A microprogram is stored in ROM (thus fixed)
or in RAM (called writable control memory).
Control Unit Organization
 Microprogrammed Control
 The Control Data Register (CDR) is optional:
• Allows higher clock frequencies (pipelining)
• Makes the sequencing more complicated for decisions based on
status bits
 If the CDR is omitted:
• The only register in the control unit is the Control Address
Register (CAR)
• The memory and next-address generator are combinational
• Thus the state of the control unit is given by the contents of the
CAR
• New control data will appear at the output of the memory as long
as the address is applied
 Microprogrammed Control
 The next address (determining the next instruction of the
new state) is function of the next-address bits and the
STATUS signals/bits.
 The way we designed the control unit, the status bits can
only affect the next address (thus next state).
[note: status bits do not control the datapath directly]
 Thus status bits cannot directly affect the output or cause
a register transfer operation (except by affecting the
address).
 This means that the sequential circuit of the control unit
must be a Moore type.
 ASM of the Control Unit

 Moore type circuit:

• No conditional output boxes allowed
• Replace the conditional output boxes by states
• Additional states are required for the same
hardware algorithm
• Also, only one decision box between states
preferred (for simple next address generation)
ASM of the Control Unit

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 ASM of the Control Unit

 Two additional states:

INIT, ADD
 Total of 5 states
needed
 Design of the Control Unit

 To design the (micro)sequencer for the

multiplier and the microprogram we need to
determine:
• The bits in the control word
• The size of the Control memory (ROM)
• The size of the Control Address Register (CAR)
• Next-address generator structure
 Control word
 Sequencer
 Control Signals and Datapath
 Use the same Datapath: n- 1
n
IN

Multiplicand
Load_B
Counter P Register B

log2 n n

Zero detect
C Parallel adder
out
 We need four control
signals: Z n Load n

• Initialize Qo Multiplier
Load_Q
• Load 0 C Shift register A Shift register Q

• Clear_C
•
n
Clear_C
Shift_Dec Initialize Product
 Status bits: Qo, Z Shift_dec
OUT

41
 Control Signals and Register Transfers

 From the datapath and ASM one finds the

register transfers initiated by the control signals.
 From the ASM one finds the states in which the
signals are active

42
 Control Signals, Control Word Format
 Four control signals needed.
 We can use these signals as is or encode them to reduce the
number of bits needed in the control word.
 If we do not encode these: 4 bits needed
• Initialize 0001
• Load 0010
• ClearC 0100
• Shift/Dec 1000

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 Sequencer

 The sequencing is determined by the ASM chart

 First, determine the sequencing requirements:
• IDLE: next state function of G
• MUL0: next state function of Qo
• MUL1: next state function of Z
 We need a pair of addresses to direct to the next
state depending on the values of the status or
input signals
 SEL determines which next address to use

44
Control Sequences for the micro operations based
on decision boxes in the ASM chart:

45
SEL Field definition and Code in the Control Word

46
Design of Control Unit

 ROM size:
• Word length: 12 bits (control word)
• Size: 5 storage location, one for each state
 Address bits:
• 3 bits to address 5 locations
• CAR is 3 bits wide
 The address loaded in the CAR:
• Comes from the next-address info in the
microinstruction: NXTADD0 or NXTADD1
Microprogrammed Control Unit

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 Register Transfer Description of the
Microprogram

 Each memory location contains a microinstruction,

to be executed in the corresponding state. The
register transfer statements are:
 Symbolic Microprogram

 The above Register Transfer Operation can be

translated into a symbolic microprogram (control
words):
 Example:
address IDLE: G: CAR ← INIT, G’: CAR ← IDLE
Can be written as:

50
Symbolic Microprogram

51
Binary Microprogram

 Similar for the other instructions:

52
 Summary
 Interaction between datapaths and control units
 Two types of control units:
• Non-programmed
• Programmed
 Two implementation approaches for Hardwired Control
(non-programmed):
• Sequence Register and Decoder
• One Flip-Flop per state
 Use of ASM to specify control functions:
• Microoperations
• Sequence of operations
 Microprogrammed control is a more structured approach
for complex systems
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Appendix A: Speeding Up the Multiplier

 In processing each bit of the multiplier, the

circuit visits states MUL0 and MUL1 in
sequence.

 By redesigning the multiplier, is it possible to

visit only a single state per bit processed?

54
 Speeding Up Multiply (Contd.)

 The operations in MUL0 and MUL1:

• In MUL0, a conditional add of B
• In MUL1, a right shift of C || A || Q in a shift register, the
decrementing of P, and a test for P = 0 (on the old value of P)

 Any solution that uses one state must combine all of

the operations listed into one state
• The operations involving P are already done in a single state,
so not a problem.
• The right shift, however, depends on the result of the
conditional addition. So these two operations must be
combined!

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 Speeding Up Multiply (Contd.)
 By replacing the shift
register with a
IDLE
combinational shifter
and combining the
adder and shifter,
0 1
the states can be merged. G

A 0
P n –1
 The C-bit is no longer needed.
MUL

 In this case, Z and Q0 P P–1

A || Q sr Cout || (A + 0) || Q A || Q sr Cout || (A + 0) || Q
have been made into
a vector. 00 10
01 Z || Q0 11

A || Q sr Cout || (A +B) || Q A || Q sr Cout || (A+B) || Q

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