IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO.

4, APRIL 2011 1237

Closed-Loop Analysis and Cascade Control of a

Nonminimum Phase Boost Converter
Zengshi Chen, Wenzhong Gao, Jiangang Hu, and Xiao Ye

Abstract—In this paper, a cascade controller is designed and ana- buck and boost converters with an incomplete analysis of the
lyzed for a boost converter. The fast inner current loop uses sliding- closed-loop system stability [12]. As a primitive-control method
mode control. The slow outer voltage loop uses the proportional– for variable structure systems, hysteresis control is still popu-
integral (PI) control. Stability analysis and selection of PI gains are
based on the nonlinear closed-loop error dynamics. It is proven lar for converters or inverters. A hysteretic current-mode con-
that the closed-loop system has a nonminimum phase behavior. trol is applied to a buck converter with low-voltage micro-
The voltage transients and reference voltage are predictable. The processor loads [13]. A simple, self-adjusting analog predic-
current ripple and system sensitivity are studied. The controller tion of the hysteresis band is added to the phase-locked-loop
is validated by a simulation circuit with nonideal circuit parame- control to ensure constant switching frequency of three-phase
ters, different circuit parameters, and various maximum switching
frequencies. The simulation results show that the reference output voltage-source inverters [14]. Hysteresis and delta-modulation
voltage is well tracked under parametric changes, system uncer- controls are implemented for a buck converter by using sen-
tainties, or external disturbances with fast dynamic transients, con- sorless current mode, reporting voltage-source characteristics,
firming the validity of the proposed controller. excellent open-loop tracking, and near-ideal source rejection
Index Terms—Boost converter, closed-loop, error dynamics, [15].
nonminimum phase, proportional–integral (PI), sliding-mode con- The researchers have made efforts to improve dynamic re-
trol (SMC), transient. sponse, transients and voltage ripples for dc–dc converters. Song
and Chung [8] claim that boundary control can improve fast
I. INTRODUCTION dynamic response. Through sensitivity analysis, they conclude
that the steady state switching frequency decreases or the hys-
HE BOOST converter is a typical power-conditioning
T component due to its simple structure and practical func-
tionality of amplifying the input voltage [1]. Its research is
teresis band increases as the equivalent series resistance (ESR)
for the capacitor increases. In [16], the transients caused by
the discontinuity in transition between buck and boost modes
mainly focused on topology, control, and safety [2]. The conven- can be reduced by compensating the discontinuity and nonlin-
tional small signal-based pulsewidth modulation (PWM) con- earity between the output voltage and the effective duty cycle.
trollers are often used although they operate optimally only In [2], focusing on compact-boost converters and intrinsically
for specific operating points [3]–[6]. The in-depth studies have safe switching power supplies, the energy-transfer modes and
been applied to various nonlinear controls for dc–dc convert- output voltage ripple of a boost converter are analyzed within
ers [7]–[9]. They are feedback state linearization, input–output the given range of the input voltage and load. The relationship
linearization, flatness, passivity-based control, dynamic feed- between the maximum output voltage ripple and the element
back control by input–output linearization, exact tracking, error parameters of the converter is deduced, and the minimum in-
passivity feedback, and boundary control. Implementations of ductance to guarantee the maximum output voltage ripple to be
them require PWM modulators. Five recent techniques from the lowest is obtained.
hybrid and optimal controls are evaluated on buck and boost Sliding-mode control (SMC) has gained popularity in con-
converters [10]. These methods display high performances, verters and inverters [17]. The earliest application of SMC to
while respecting circuit constraints. One-cycle control is ap- dc–dc converters was reported in 1983 [18] and 1985 [19].
plied to Cuk Converter [11]. Synergetic control is applied to The detailed SMC design theory is found in [17]. Mainly, the
SMC offers several advantages, namely, large signal stability,
robustness, good dynamic response, system order reduction,
Manuscript received January 4, 2010; revised July 6, 2010; accepted August
18, 2010. Date of current version June 10, 2011. Recommended for publication and simple implementation [20]. The SMC can be naturally im-
by Associate Editor F. Blaabjerg. plemented in converter control [21], since two discrete switch-
Z. Chen is with the Manufacturing Research Center, Tennessee Tech Univer- ing values can directly act as gating signals to semiconductor
sity, Cookeville, TN 38501 USA (e-mail: [email protected]).
J. Hu is with the Rockwell Automation, Milwaukee, WI 53092 USA (e-mail: switching devices in power circuits. In [22], the various aspects
[email protected]). concerning the application of SMC are discussed. It shows that
W. Gao is with the Department of Electrical and Computer Engineering, Uni- the SMC generates more consistent transient responses for a
versity of Denver, Denver, CO, USA (email: [email protected])
X. Ye is with the School of Electric Machinery and Electric Apparatus, wide operating range as compared with the conventional linear
Hefei University of Technology, Hefei 230009, China (e-mail: yexiao1234@ controls.
163.com). With phase portraits, extended linearization is proposed for
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. the systematic solution of sliding mode controller design in
Digital Object Identifier 10.1109/TPEL.2010.2070808 boost and buck–boost converters [23]. In [7] and [17], open-loop

0885-8993/$26.00 © 2011 IEEE

1238 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 4, APRIL 2011

SMC is applied to various dc–dc converters. The indirect control

of the current on a switching manifold is used for output volt-
age regulation. Unfortunately, open-loop SMC lacks robustness
against system uncertainties and disturbances. In [24], a PWM-
based sliding-mode voltage controller is designed for basic dc–
dc converters in continuous conduction mode. It is limited to
a lower bandwidth application. In [25] and [26], sliding mode
controllers with dynamic sliding manifolds allow direct control
of the voltages of buck, boost, and buck–boost converters. How-
ever, the output voltage tracking error has to converge to zero
Fig. 1. Boost converter.
asymptotically in sliding mode. In [27], the SMC is applied to
a buck converter with an assumption of the zero value of the
average capacitor current. It is difficult to extend this method
to more complicated converters or converters with other mod-
eling methods. In [28], the SMC analog integrated circuit for
switching dc–dc converters is developed. The experimental re-
sults validate the high-speed functionality of the proposed im-
plementation. A small-signal model of dc–dc converters with
SMC allows evaluation of closed-loop performances like audio-
susceptibility, output and input impedances, and reference to
output transfer function [20]. The approach is validated on a
boost converter. Fig. 2. Boost converter at u = 1.
As a practical control method with a deep industrial root, PID
control is widely applied to converters or inverters either in con-
ventional manner or in combination with the SMC. Closed-loop
analysis of such systems with a resultant guideline for selecting
PID gains has a demand from practicing engineers and corpo-
rations [29]. However, some researchers suspect the availability
of the analytic approaches for obtaining PID gains when the
PID control and SMC are combined [8]. Some simulation re-
sults are successfully generated for a boost converter under a PI
and sliding mode cascade control through trials and errors for
PI gains [30]. The semiglobal asymptotic stabilizing properties
Fig. 3. Boost converter at u = 0.
of classic PI control in the indirect regulation of average mod-
els of dc–dc converters are established [31]. A PID auxiliary
dynamics is designed for a buck converter under SMC [32]. Simulation results are reported in Section VI. Conclusion is in
In [33], generalized PI controllers are applied to buck, boost, Section VII.
and buck–boost converters based on integral reconstructors of
the unmeasured observable state variables. However, the system
robustness with respect to input voltage variation or disturbances II. BOOST-CONVERTER MODEL
is not studied, and extremely large load variation renders loss The boost converter is shown in Fig. 1. When the control
of feedback for the controller. A double-integral term of the signal u is 1, the circuit is shown in Fig. 2. The inductor L
controlled variables is added to alleviate the regulation error of is being charged by the input voltage E, and the capacitor C
the dc–dc converter [34]. is being discharged through the resistor R. When u is 0, the
In this paper, a PI and sliding mode cascade controller is circuit is shown in Fig. 3. E and L charge C. Let v be the output
designed and analyzed for a boost converter. This control struc- (load) voltage and i be the inductor current. As shown in [7],
ture was proposed 15 years ago but its analytical solution has the ordinary differential equations for the boost converter is
never been seen in the existing literature [17]. Through theoret- represented as
ical study and circuit simulation, this paper shows a few merits
of this controller: it embraces a solid theoretical foundation; it 1 E
i = −(1 − u) v + (1)
can easily be designed, simulated, and implemented; the closed- L L
loop system is stable and robust; and the transients and reference 1 1
voltage are predictable. This paper is organized as follows. The v  = (1 − u) i − v (2)
C CR
boost converter model is developed in Section II. The controller
is designed and the closed-loop system is analyzed in Section where  means the first derivative. Equations (1) and (2) have
III. System robustness is analyzed in Section IV. Parameter se- the typical state space format with the discontinuous right-hand
lection and circuit implementation are discussed in Section V. side. The control and the state variables have a bilinear relation.
CHEN et al.: CLOSED-LOOP ANALYSIS AND CASCADE CONTROL OF A NONMINIMUM PHASE BOOST CONVERTER 1239

such a function for the system represented by (1) and (2) be

V = 0.5S 2 > 0, ifS = 0. (9)
Differentiating (7) yields
1 E
S  = i − i∗  = −(1 − u) v + − i∗  . (10)
Fig. 4. Cascade controller of the boost converter. L L
With (10), the derivative of V is
III. CLOSED-LOOP CONTROL AND ANALYSIS 1
V  = SS  = S(2E − 2Li∗ − v) − |S|v)
A. Cascade Control 2L
1
In this section, based on the nominal parameters, the current ≤ |S|(|2E − 2Li∗ − v| − v). (11)
2L
and voltage controllers are designed, and the nonlinear closed-
loop error dynamics is analyzed. The control goal is to track a Therefore, the sufficient condition for V  < 0 is
constant reference voltage despite disturbances or uncertainties. |2E − 2Li∗ − v| − v < 0. (12)
The control structure for the converter is shown in Fig. 4, where
i∗ is the feedback reference current, vd is the reference voltage, The inequality 12 leads to
E, v, i, and u are defined previously, and e is the error between
vd and v, i is a positive feedback signal due to the structure of 0 < E − Li∗ < v. (13)
the sliding mode controller as shown in (8). Both v and i are With the initial conditions of i(0) ≥ 0 and v(0) ≥ 0, the
measured. boost converter will go through the reaching phase and reach
1) Outer Voltage Loop: The equilibrium point of the boost the sliding mode. After sliding mode is reached, S ≈ 0 and S ≈
converter corresponding to a constant value of the average con- 0 [17]. Consequently, i∗ ≈ id and i∗ ≈ id = 0. Since L is very
trol input is obtained by letting the right-hand side of (1) and (2) small, then 2Li∗ ≈ 0. Due to E > 0, v must be positive to
be zero while the control variable is set to be u = U, where U is guarantee the inequality 13 that defines an attraction domain
a constant [7], [17]. The equations for the equilibrium inductor of the sliding manifold. Because the control in (8) contains
current id and the equilibrium voltage that also equals vd are no control gains to be adjusted, the domain of attraction (the
given by inequality 13) is predetermined by the system architecture. In
1−U E the steady state, the inequality 13 is fulfilled by the definition of
− vd + =0 (3) a boost converter. The derivation of (11) implicitly validates (8)
L L
1−U 1 since it results in a stable system.
id − vd = 0. (4) 3) Closed-Loop Analysis: In sliding mode, the equivalent
C CR
control method can be explored [17]. Once the system is in
Eliminating U in (3) and (4) renders id in terms of vd as sliding mode, S = 0 and S = 0 hold. The discontinuous control
vd2 u in S = 0 can be replaced by a continuous equivalent control
id = . (5) ueq , and S = 0 is solved for ueq . After sliding mode occurs,
RE
one has i = i∗ and
Equation (5) provides a relation between i and v when the
1 E
converter is in the steady state. id is also the feed-forward input S  = −(1 − ueq ) v + − i∗ = 0. (14)
current for the converter as shown in Fig. 4. With e = vd − v, L L
t
the current generated by a PI controller is ic = Kp e + Ki 0 edt Solving (14) for ueq renders
where Kp and Ki are the proportional and integral gains, re-
spectively. The overall reference current for the current loop v − E + Li∗
ueq = . (15)
is v
To show that ueq takes the values only from 0 to 1 in the
i∗ = id + ic . (6) sliding mode, the inequality 13 is solved as
2) Inner Current Loop with SMC: The switching manifold
−v < −E + Li∗ < 0. (16)
for sliding mode current control is designed as
Adding v to both sides of the inequality 16 renders
S = i − i∗ . (7)
0 < v − E + Li∗ < v. (17)
For the boost converter, the control scheme is
u = 0.5(1 − sign(S)) = 1, if S < 0 or 0 if S > 0. (8) Dividing the inequality 17 by v renders 0 < ueq < 1.
Equation (15) contains the current dynamics represented by (1).
This control structure will be verified when the current loop In the sliding mode, current dynamics is controlled. It is natural
stability is analyzed. The existence condition of sliding mode to drop (1) from the original system, leaving only the voltage
can be derived with the candidate Lyapunov function [14]. Let dynamics (2) for study. Plugging i = i∗ and ueq in (15) into (2)
1240 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 4, APRIL 2011

yields TABLE I:
NOMINAL PARAMETERS
(CRv  + v)v
Ri∗ = (18)
E − Li∗
i∗ contains the integral term of the voltage error. It is incon-
venient to analyze a dynamics system with integral terms. The
practical way is to rearrange the dynamics equations and elimi-
nate the integral term by differentiation. Both sides of (18) are
derived with respect to time, resulting in
Ri∗ (E − Li∗ )2 = ((CRv  + v  )v
0) will be evaluated. The trajectories of a second-order nonlin-
+ (CRv  + v)v  )(E − Li∗ ) + L(CRv  + v)vi∗ (19) ear system in a small neighborhood of an equilibrium point is
expected to be close to the trajectories of its linearization about
where  means the second derivative. With e = vd − v and vd that point if the origin of the linearized state equation is a hy-
as a constant, v = vd − e, v  = −e , and v  = −e . The first and perbolic equilibrium point [35]. Proper PI gains guarantee that
second derivatives of (6) are the equilibrium point (0, 0) is hyperbolic. The Jacobian matrix
i∗ = Kp e + Ki e (20) of (24) and (25) around (0, 0) is
 
i∗  = Kp e + Ki e . (21) A1 =
a11 a12
(29)
a21 a22
Let two state variables be x1 = e and x2 = e . Then, one has
RE 2 Ki
x1 = f1 (x1 , x2 ) = x2 and x2 = e . Substituting e, e , e , v, v  , where a11 = 0, a12 = 1, a21 = L v d2 K p −C R E v d
, and a22 =
v  , i∗ and i∗ into (19) yields R E 2 K p −L v d2 K i +2v d E
L v d2 K p −C R E v d
. Let the desired eigenvalues of the closed-
A1 = (A2 x2 + A3 )A4 + A5 x2 + A6 (22) loop system be λ∗1 and λ∗2 . The pole placement renders
where A1 = R(Kp x2 + Ki x1 )(E − LKp x2 − LKi x1 )2 , [ Kp Ki ]T = B −1 D (30)
A2 = CR(x1 − vd ), A3 = x2 (x1 − vd ) + x2 (CRx2 + x1 −
where
vd ), A4 = E − L(Kp x2 + Ki x1 ), A5 = LKp (CRx2 + x1 −  
vd )(x1 − vd ), and A6 = LKi (CRx2 + x1 − vd )(x1 − vd )x2 . RE 2 − Lvd2 (λ∗1 + λ∗2 ) −Lvd2
Solving (22) for x2 renders B= ,
Lvd2 λ∗1 λ∗2
RE 2
A1 − A6 − A3 A4  
x2 = f2 (x1 , x2 ) = . (23) −2vd E − CREvd (λ∗1 + λ∗2 )
A5 + A2 A4 D= ,
CREvd λ∗1 λ∗2
The nonlinear state space equations for the closed-loop error
dynamics in sliding mode is and T is transpose. Now, Kp and Ki are fixed. The Jacobian
matrix of (24) and (25) around (E/(LKi ), 0) is
x1 = f1 (x1 , x2 ) (24) ⎡ ⎤
0 1
x2 = f2 (x1 , x2 ). (25)
A2 = ⎣ Ki ⎦ . (31)
0 −
Any equilibrium point (p1 , p2 ) of (24) and (25) is worth Kp
attention. In the equilibrium state, one has p1 = 0 and p2 = 0
A2 has an eigenvalue on the imaginary axis. The qualitative
with
behavior of the nonlinear system near (E/(LKi ), 0) could be
f1 (p1 , p2 ) = 0 (26) quite distinct from that of the relevant linear system [35].
f2 (p1 , p2 ) = 0. (27) B. Phase Portrait of Error Dynamics
Solving (26) renders p2 = 0 with which one easily finds out Numerical construction of a global phase portrait for (24) and
A3 (p1, 0) = 0 and A6 (p1, 0) = 0. Hence, in order to satisfy (27), (25) will uncover the features of the equilibrium points (0, 0) and
A1 (p1, 0) = 0 must equal 0. Consequently (E/(LKi ), 0). Equation (23) tells that (24) and (25) have two
R(Kp ∗ 0 + Ki p1 )(E − L(Kp ∗ 0 + Ki p1 ))2 = 0. (28) discontinuous subspaces due to A5 + (A2 A4 ) = 0. They are
(vd , x2 ) and ((LKp vd − CRE)/(LKp − LKi CR), x2 ) where
Solving (28) renders p1 = 0 and p2 = E/(LKi ). Therefore, x2 can be any real value. In this design, the nominal parameters
there exist two equilibrium points (0, 0) and (E/(LKi ), 0) for for constructing a phase portrait are shown in Table I (how Kp
the closed-loop error system. The system trajectory shall be con- and Ki will be explained in Section V). The two discontinuous
fined to the equilibrium point (0, 0) since the other point leads subspaces are (50, x2 ) and (49.7423, x2 ). The two equilibrium
to a voltage tracking error and is dangerously close to the two points are (E/(LKi ), 0) = (48.3807, 0) and (0, 0). Fig. 5 shows
discontinuous subspaces to be shown later. After Kp and Ki are these points and subspaces. If the parameters vary, then they shift
obtained through linearizing the system around (0, 0), they are on the x1 axis, qualitatively providing the picture of a workable
plugged into (24) and (25) and the characteristics of (E/(LKi ), initial or transient condition. Let the initial conditions of (24)
CHEN et al.: CLOSED-LOOP ANALYSIS AND CASCADE CONTROL OF A NONMINIMUM PHASE BOOST CONVERTER 1241

v successfully tracks vd , v will also be too close to E. Then,

the inequality 13 could be easily violated due to a transient
(e.g., nonzero initial error) since it has been proven that it is
more ideal for v to be a larger value. Since Kp is very small,
variation of vd hardly affects (E/(LKi ), 0), or ((LKp vd −
CRE)/(LKp − LKi CR), x2 ). Smaller vd significantly shifts
(vd , x2 ) to the vicinity of (0, 0). Thus, the system will more
likely experience discontinuous solutions before it converges to
(0, 0). Second, vd shall be less than its nominal value vd0 for the
controller design. Otherwise, with v(0) = 0, the initial voltage
error e(0) = vd (0) − v(0) will get closer to or cross (vd , x2 ).
Again, the system will be attracted to (E/(LKi ), 0) or have
Fig. 5. Equilibrium points and the discontinuous subspaces. discontinuous solutions. Hence, for the proposed controller, the
workable reference voltage is roughly from 20 to 50 V. A larger
nominal value of the reference voltage shall be used for the
controller design as shown in Section III-A3 if a larger operating
range of the reference voltage is desired. For example, if the
nominal value of the reference voltage 100 V is selected for
the controller design, the boost converter will be able to track
the voltage roughly from 20 to 100 V. Since (vd , x2 ) is the
discontinuous subspace that the error dynamics should avoid, the
actual reference voltage shall be less than vd0 . The operational
range of the reference voltage is recommended to be: 1.1E ≤
vd ≤ 0.9vd0 .

D. Nonminimum Phase Voltage Output

Consider a stable and strictly proper system (i.e., the number
of zeros are less than the number of poles). The step response of
Fig. 6. Phase portrait around the equilibrium point (0,0). the system is said to have an “undershoot” behavior if it initially
“starts off in the wrong direction” [36]. This is the nonminimum
phase phenomenon. Such a system is in the nonminimum phase
and (25) be on the circle around (0, 0) with the radius of 48 as if and only if its transfer function has an odd number of real
shown in Fig. 5. The phase portrait around (0, 0) is shown in right-half plane zeros. The boost converter with the proposed
Fig. 6. Since the magnitude on the x2 axis is too large, it is hard cascade controller has a nonminimum phase voltage output.
to distinguish some initial points. However, it is indeed seen that Since this paper does not simulate the case with feed-forward
(0, 0) is a stable node. For all the initial conditions on the circle, current, dropping id from i∗ and rewriting (20) and (21) in terms
the trajectories converge to (0, 0). Clearly, (0, 0) has a large of vd , v, v  , vd , v  , and vd render
attraction domain. Actually, with any initial condition starting
at [x1 (0), x2 (0)] roughly with x1 (0) ≤ 48 V and any value of i∗ = Kp vd − Kp v  + Ki vd − Kp v (32)
∗  
x2 (0), the trajectories of (24) and (25) always converge to (0, 0). i = Kp vd − K p v + Ki vd 
− Kp v . (33)
Therefore, it is concluded that the closed-loop error dynamics
around the equilibrium point (0, 0) is at least semiglobally stable Plugging (32) and (33) into (19) renders
(stable on the left-hand half phase plane and some part of the R(Kp v̇d − Kp v̇ + Ki vd − Ki v)(E − LKp v̇d + LKp v̇
right-hand half phase plane) with a large attraction domain,
and the equilibrium point (0, 0) is a stable node. The aforesaid − LKi vd + LKi v)2 = ((CRv  + v  )v
phase portrait is for S = 0 with an infinite switching frequency. + (CRv  + v)v  )(E − LKp v̇d + LKp v̇ − LKi vd + LKi v)
However, in general, the switching frequency is finite and S
is less than or equal to Δ that, as the boundary layer width, + L(CRv  + v)v(Kp v̈d − Kp v̈ + Ki v̇d − Ki v̇). (34)
is inversely proportional to the switching frequency [17]. The
Let ve be the equilibrium point of vd and v. Let vδ and vdδ
output voltage will converge to a boundary layer around the
be the perturbations of v and vd . One has v = vδ + ve , vd =
reference voltage. Consequently, the voltage error converges to
vdδ + ve , v  = vδ , vd = vdδ

, v  = vδ , and vd = vdδ

. Plugging
a boundary layer around 0. The origin (0, 0) in Fig. 6 is a pair of
them into (34) and dropping the high orders of vδ , vdδ , vδ , vdδ 
,
average values around which the error state variables oscillate.  
vδ , vdδ , and any product of some of them render

C. Operational Range of Reference Voltage a2 vδ + a1 vδ + a0 vδ = b2 v̈dδ

 
+ b1 v̇dδ + b0 vdδ (35)
It is noticed that the reference voltage is in a certain range. where a0 = RE 2 Ki , a1 = RE 2 Kp + 2Eve − Lve2 Ki , a2 =
First, vd must be greater than E. If vd is too close to E and CREve − Lve2 Kp , b0 = RE 2 Ki , b1 = −Lve2 Ki + RE 2 Kp ,
1242 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 4, APRIL 2011

Fig. 7. Trajectory of the zeros of F(s), and the step responses of v δ /v d δ (s) Fig. 8. Trajectory of the zeros of F(s), and the step responses of v δ /v d δ (s)
and F(s) under v e = 35 V, K p = −0.0087, and K i = 10.3347. and F(s) under v e = 35 V, K p = 0.001, and K i = 10.

and b2 = −Lve2 Kp . The transfer function of (35) is the following two conditions must be satisfied:

vδ (s) b2 s2 + b1 s + b0 b2 ((b0 /b2 ) − (a0 /a2 )) > 0 and ((b1 /b2 ) − (a1 /a2 ) > 0 (37)
= = + F (s) (36)
vdδ (s) a2 s2 + a1 s + a0 a2
((b0 /b2 ) − (a0 /a2 )) < 0 and ((b1 /b2 ) − (a1 /a2 )) < 0. (38)
where F (s) = b2 [((b1 /b2) − (a1 /a2 ))s + (b0 /b2) −
(a0 /a2 )]/(a2 s2 + a1 s + a0 ). With the nominal parame- The inequality (37) has no solution. Solving the in-
ters in Table I, the zeros of F(s) as ve increases from 20 to equality (38) renders Kp > 0 and Ki < Kp (CR2 E 3 +
50 V are plotted in the top pane of Fig. 7. All the zeros are 2LEve2 )/(L2 ve3 ). Therefore, to have a negative zero for
positive. F(s) is a stable and strictly proper system. Thus, F(s) and guarantee the system stability, the inequal-
F(s) is has a nonminimum phase behavior. Since b2 /a2 only ities of 0 < Kp < CRE/(Lve ), 0 < Ki < Kp (CR2 E 2 +
affects the initial value of the response of the vδ (s)/vdδ (s), 2Lve2 )/(LCRve2 ) and 0 < Ki < (CR2 E 3 + 2LEve2 )/(L2 ve3 )
due to F(s), vδ (s)/vdδ (s) always displays a nonminimum must hold. Then, b2 /a2 < 0 since b2 < 0 and a2 > 0. With
phase behavior. For example, ve = 35 V renders F (s) = E, R, L, C, and ve from Table I, it is inferred that 0 < Kp <
(−1243.6s + 34296)/(0.54 s2 + 753.8449 s + 165 360) and 0.0023, 0 < Ki < 12827Kp and 0 < Ki < 29.3178. Appar-
b2 /a2 = 0.7926. The zero of F(s) is 27.5769 and is in the ently, Kp = 0.001 and Ki = 10 are appropriate. Then, the zeros
right-half phase plane. For a unit step input, the response of of F(s) as ve increases from 20 to 50 V are plotted in the top
vδ (s)/vdδ (s) shown in the second pane of Fig. 7 starts from pane of Fig. 8. All the zeros are negative. F(s) is in the min-
b2 /a2 = 0.7926 and reaches the minimal value −0.468 before imum phase. To predict the transient for the closed-loop sys-
it converges to 1. In the bottom pane of Fig. 7, the response tem with Kp = 0.001 and Ki = 10, the unit step responses
of F(s) starts off in the wrong direction from 0 and reaches of vδ (s)/vdδ (s) = −0.78 + F (s) and F (s) = (246.2222s +
the minimal value −1.26 before it converges to 0.208. Hence, 2 84 444)/(0.063s2 + 926s + 1 60 000) with a negative zero of
the output voltage of the boost converter under the proposed −1155.2 for ve = 35 V are plotted in the mid and bottom panes
cascade controller has a nonminimum phase phenomenon when of Fig. 8, respectively. The response of vδ (s)/vdδ (s) starts from
the reference voltage experiences a step change. b2 /a2 = −0.78 and converges to 1. The response of F(s) starts
Next, it will be shown that with a negative zero for from 0 and converges to 1.78. The mid pane shows that the
F(s), F(s) has a minimum phase but vδ (s)/vdδ (s) still dis- output voltage still starts out in the wrong direction in a tran-
plays a kind of nonminimum phase behavior due to nega- sient, displaying a nonminimum phase phenomenon. However,
tive b2 /a2 . The stability evaluation and the PI gain selec- this is not classic nonminimum phase. In this case, the transient
tion can be based on (36). According to Ruth–Hurwitz sta- directly increases from a nonzero initial value on the side of 0
bility theorem, the sufficient and necessary stability condi- farther from the steady state value and then converges to the
tion for (36) is a0 > 0, a1 > 0, and a2 > 0. Solving these steady state value. For a classic nonminimum phase behavior as
inequalities for Kp and Ki renders Kp <CRE/(Lve ) and 0 < shown in Fig. 7, the transient starts from a nonzero initial value,
Ki < (CR2 E 3 + 2LEve2 )/(L2 ve3 ). The zero of F (s) is z = goes farther from the steady state value, reaches a peak, then
−((b0 /b2 ) − (a0 /a2 ))/(b1 /b2 ) − (a1 /a2 )). For z < 0, one of gets closer to the steady state value again until it converges to it.
CHEN et al.: CLOSED-LOOP ANALYSIS AND CASCADE CONTROL OF A NONMINIMUM PHASE BOOST CONVERTER 1243

The step responses of Figs. 7 and 8 are based on the two neg-
ative and real poles of (36). If the two poles of (36) are complex
conjugated with a negative real part, the undershoot behavior
will experience an oscillation. In conclusion, the boost con-
verter under the proposed controller has a nonminimum phase
behavior when the reference voltage experiences a step change
regardless of PI gains.

E. Transients with Step Changes of Input Voltage

and Load Resistance
When the reference voltage is a constant value, the transients
of the output voltage can still happen if there is a step change
for a parameter such as the input voltage, the resistance, the in-
ductance, or the capacitance. It is useful to predict the transients
resulting from step changes of input voltage or load resistance
because such variation is common in practice.
First, the transient due to step change of input voltage is Fig. 9. Output voltage transients for a unit step change of input voltage.
studied. Let E = Ed + Eδ where Ed is the operating point of E
and Eδ is the perturbation of E from Ed . Let v = vd + vδ where
and converges back to 0 V. The transient lasts about 0.025 s.
vd is the operating point of v, and vδ is the perturbation of v
Similarly, the bottom pane of Fig. 9 shows the output voltage
from vd . Apparently, vδ = v − vd = −e and vδ = −e . Then,
transient for a negative unit step change of Eδ . It is symmetrical
(20) and (21) become
to the transient in the top pane of Fig. 9.
i∗ = −Kp vδ − Ki vδ (39) Second, the transient due to the step change of load resistance
i∗ = −Kp vδ − Ki vδ . (40) is studied. Let Rd be the operating point of R and let Rδ be the
∗
perturbation of R from Rd . vd and vδ are defined previously.
E, i , and v are variables to be considered and all the other R, i∗ , and v are variables to be considered and all the other are
are assumed to be constants. Differentiating (18) renders assumed to be constants. Rearranging (18) renders
Rir (E − Lir )2 = ((CRv  + v  )v + (CRv  + v)v  )(E − ir ) (CRv  + v)v
  i∗ = . (46)
− (CRv + v)v(E − Lir ). (41) R(E − Li∗ )
Plugging E = Ed + Eδ , v = vd + vδ , (39) and (40) into (41), Differentiating (46) renders
and dropping the high orders of vδ , vδ , vδ , Eδ , and Eδ and any
product of some of them render i∗ R2 (E − Li∗ )2 = [(CR v  + CRv  + v  )v

e3 vδ + e2 vδ + e1 vδ = e0 Eδ (42) + (CRv  + v)v  ]R(E − Li∗ )

where e0 = vd2 , e1 = Ed2 RKi , e2 = 2Ed vd − Lvd2 Ki + − (CRv  + v)v[(E  − Li∗  )R + (E − Li∗ )R ]. (47)
REd Kp , and e3 = CRvd Ed − Lvd2 Kp . The transfer function Plugging R = Rd + Rδ , v = vd + vδ , (39) and (40) into (47),
of (42) is and dropping the high orders of vδ , vδ , vδ , Rδ , and Rδ and any
vδ (s) e0 s product of some of them render
F1 (s) = = 2
. (43)
Eδ (s) e3 s + e2 s + e1
g3 vδ + g2 vδ + g1 vδ = g0 Rδ (48)
For a unit step perturbation Eδ (s) = 1/s, the final value the-
orem shows that vδ converges to 0 where g0 = Evd2 , g1 = Rd2 E 2 Ki , g2 = 2ERd vd −
  LRd vd Ki + Rd E Kp , and g3 = CRd2 vd E − Rd Lvd2 Kp .
2 2 2
e0 s The transfer function of (48) is
lim vδ (t) = lim svδ (s) = lim = 0. (44)
t→∞ s→0 s→0 e3 s2 + e2 s + e1
vδ (s) g0 s
Equation (44) shows that the output voltage transient even- F2 (s) = = 2
. (49)
Rδ (s) g3 s + g2 s + g1
tually dies out and the reference voltage is tracked again after
a transient. Next, the transient trajectory is shown to be pre- Similarly, the final value theorem shows limt→∞ vδ (t) → 0.
dictable. For example, with the nominal parameters in Table I, Hence, for a step change of load resistance, the output voltage
(44) becomes transient eventually dies out and the reference voltage is tracked
1225s again after a transient. Next, the transient trajectory is shown
F1 (s) = . (45) to be predictable. For example, with the nominal parameters in
0.8887s2 + 951.8685s + 142190
Table I, (49) becomes
The top pane of Fig. 9 shows the output voltage transient for
a positive unit step change of Eδ . It is seen that the voltage tran- 24500s
F2 (s) = . (50)
sient becomes positive, reaches the maximum value of 1.032 V 35.547s2 + 28 438s + 56 87 500
1244 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 4, APRIL 2011

Fig. 10. Output voltage transients for a unit step change of load resistance.
Fig. 11. Frequency response of the open-loop system with respect to the
angular frequency under v e = 35 V.
The top pane of Fig. 10 shows the output voltage transient
for a positive unit step change of Rδ . It is seen that the volt- Plugging (51) into (18) results in
age transient becomes positive, reaches the maximum value of  
0.6339 V and converges back to 0 V. The transient lasts about 1 2L
vd2 E− vd vd = (CRv  + v)v. (52)
0.025 s. The bottom pane of Fig. 10 shows the output voltage E RE
transient for a negative unit step change of Rδ . It is symmetrical
Let ve be the equilibrium point of vd and v. Let vδ and vdδ
to the transient in the top pane of Fig. 10.
be the perturbations of v and vd . Consequently, v = vδ + ve ,
According to the definition of nonminimum phase in
vd = vdδ + ve , v  = vδ , and v  = vdδ

. Plugging these variables
Section III-D, an odd number of real right-half plane zeros for
into (52), and dropping the high orders of vδ , vdδ , vδ , and vdδ

a transfer function is the sufficient and necessary condition for
and any product of some of them render
a linear system represented by that transfer function to have a
non-minimum phase behavior. Equations (45) and (50) do not 2Lve2 
have any real right-half plane zero. Therefore, they do not have 2vdδ − v = CRvδ + 2vδ . (53)
RE 2 dδ
a nonminimum phase structure and the output voltage will not
The transfer function of (53) is
display a nonminimum phase behavior under a step change of

the input voltage or load resistance. The preceding work shows vδ (s) −(2Lve2 RE 2 )s + 2
that the system output voltage experiences an undershoot be- H(s) = = . (54)
vdδ (s) CRs + 2
havior when the input voltage or load resistance has a negative
step change and an overshoot behavior when one of them has a With the nominal parameters from Table I, (54) becomes
positive step change. The amplitude of the undershoot or over- H(s) = (−0.006125s + 2)/(0.00016s + 2) whose frequency
shoot is roughly the product of the magnitude of the step change response is shown in Fig. 11. This open-loop system passes the
and the transient amplitude caused by a unit step change. These low-frequency signals and amplifies the high-frequency signals
predictions are to be verified by the foregoing simulation. substantially. The open-loop system has the undesirable positive
gain margin. Thus, the system is sensitive to disturbances or
parametric uncertainties.
IV. SYSTEM ROBUSTNESS
In this section, the frequency responses of the open-loop and B. Frequency Response of Closed-Loop System
closed-loop boost converter systems are studied. The open-loop With the nominal parameters from Table I, the frequency
system is vulnerable to noises. The generous gain and phase response of (36) is studied. The top and bottom panes of Fig. 12
margins of the closed-loop system confirms its robustness. show the gain and phase responses of the closed-loop system
over the frequency spectrum, respectively. The gain margin is
−1.35 dB. The phase margin is close to 180◦ . They are very
A. Frequency Response of Open-Loop System
generous margins (a converter system has decent robustness if
Under the open loop control, ic is equal to 0 and (6) becomes its phase margin is about 52◦ and its gain margin is less than −0.5
[3]). The closed-loop system passes the low-frequency signals
vd2 and filters the high-frequency signals. The closed-loop system
i∗ = id = . (51) with such gain and phase margins will tolerate large disturbances
RE
CHEN et al.: CLOSED-LOOP ANALYSIS AND CASCADE CONTROL OF A NONMINIMUM PHASE BOOST CONVERTER 1245

of Section III-B mainly focuses on system stability and location

of a zero, but the roles of the poles in affecting the system
performances are not elaborated. In general, a pair of complex
poles with a negative and real part leads to an underdamped
system; two equal and negative poles render a critically damped
system; two unequal and negative poles result in an overdamped
system. Two equal and negative poles are desired for a boost
converter since damping is just enough for preventing oscillation
in the transient response to a step input. As long as the two equal
and negative poles are used, the stability of the power converter
is guaranteed. When the poles are closer to zero, the system will
be better for passing low-frequency signals and rejecting noises,
but the system response is slower. Furthermore, disturbances
or uncertainties can easily bring the system to instability if
the poles are close to zero. For example, if two equal poles
of −10 are used, it takes about 4 s for the output voltage to
converge to its reference value. As the poles diverge from zero,
Fig. 12. Frequency response of the closed-loop system with respect to the
the system response gets faster and the system stability is better.
angular frequency under v e = 35 V. For example, if two equal poles of −700 are used, it takes about
0.01 s for the output voltage to converge to its reference value.
Nevertheless, fast system response is achieved with a cost. If the
and system uncertainties, and hence, embrace strong robustness, poles are far from zero, the magnification of noise at the output
which is to be confirmed by simulation. will be very large. The choice of pole location is the compromise
of noise suppression and the other system performances. The
V. CIRCUIT PARAMETERIZATION AND IMPLEMENTATION detail of using bode plots for such analyses can be found in [37].
A. Selection of E, R, L, C, and vd As a compromise and for the demo purpose, two equal poles of
−400 are used in this paper. The resultant system settling time
Resistance R is selected according to the output power equa-
is about 0.02 s. Then, with the nominal parameters from Table I
tion of P = vd2 /R where P is power. One of the advantages of
and (30), Kp = −0.0087 and Ki = 10.3347 are obtained. The
high-frequency switching power electronics is reduction of the
poles shall be selected according to the expectation for system
circuit volume. In practice, inductance should be as small as
performances. As for zeros, a negative zero will increase the
possible. Large capacitance is preferred if its physical volume is
overshoot if it is within a factor four of the real pole; a positive
not an issue. Input voltage shall be less than the output voltage.
zero will depress the overshoot and may cause the step response
The operational reference voltage vd shall be greater than the
to start out in the wrong direction as shown in Section III-B [36].
input voltage E and less than the nominal reference voltage vd0
for the controller design.
Any of these parameters such as the input voltage, the load re- C. Validation Circuit
sistance, the inductance, the capacitance, the reference voltage,
A closed-loop simulation circuit for the boost converter is
and the PI gains will affect a0 , a1 , a2 , b0 , b1 , and b2 as shown
constructed with SimPowerSystems of Simulink Toolbox as
in (36) that is a typical second-order system. From the system
shown in Fig. 13. The nonideal circuit factors are taken into ac-
and control point of view, variation of any of these parameters
count although they are ignored when the controller is designed.
may affect time constant (L/R or RC), rising time, settling time,
The ESR of the capacitor C is selected to be RC = 0.02 Ω,
oscillation cycle, overshoot amplitude, stability (poles are in
and the series resistance of the inductor L is selected to be
the right- or left-hand plane), robustness (e.g., gain margin and
RL = 0.01 Ω. Through ideal switches, a voltage source E1
phase margin of frequency response), minimal or nonminimum
is used to create step changes of the input voltage; a resistor
phase (zeros are in the right- or left-hand plane), damping type
R1 = 120 Ω is used to create step changes of the load resis-
(overdamping, underdamping, or critical damping), and even
tance. The forward voltage drops and internal resistances of
the reaching phase time of sliding mode. Analytical and com-
the MOSFET switch and freewheeling diode are considered.
putational techniques for these criteria of a second-order system
They are modeled with Off-the-Shelf device parameters. The
are mature [36]. They will not be repeated in this paper.
MOSFET (IRFP2907) is from International Rectifier. The free-
For the demo purpose, the nominal parameters of E, R, L, and
wheeling diode (MUR1510) is from ON Semi. The parameters
C in Table I used in this simulation are inherited from a boost
for the MOSFET and its internal antiparallel diode d are: 1)
converter in [17].
MOSFET On resistance: 4.5 mΩ; 2) MOSFET forward current:
90 A (Package limitation); 3) diode d resistance: 0.036 Ω; 4)
B. PI Gain Selection
diode d forward voltage: 1.3 V; and 5) diode d forward current:
As demonstrated in Section III-A3, Kp and Ki are obtained 90 A (Package limitation). The parameters for the freewheel-
through pole placement. Discussion on Kp and Ki in the late part ing diode D are: 1) On resistance: 0.33 Ω; 2) forward voltage:
1246 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 4, APRIL 2011

Fig. 13. Simulation circuit with nonideal power devices.

1.05 V; and 3) forward current: 15 A. The current rating of yond the interest of this paper. The simulation fixed-step size is
the MOSFET switch guarantees its safety even if a continuous 1 μs. Since this paper deals with only simulation without A/D
current goes through it for a long time. converters, 1 μs is also the sampling period. Hence, the mini-
mum sliding mode pulse width is 1 μs or the maximum sliding
D. Controller Implementation mode switching frequency is 1 MHz. A lower maximum switch-
ing frequency of 10 –100 kHz can be used if a larger voltage
To implement the controller, one should assess the require-
tracking error is permitted [7], [38]. There are many advanced
ment for the system performances via analysis and computation
methods for reducing or eliminating chattering [17]. However,
as shown in this paper and classic control books for a second-
to pursue them is beyond the scope of this paper. If the switching
order system, select the appropriate boost-converter parameters,
frequency is less than 10 kHz, the proposed controller will fail
plug them into (30) to obtain the PI gains, use a reference volt-
to function. This is due to the larger switching boundary layer. A
age between the input voltage and the nominal reference voltage
system on such boundary layers is almost under open-loop con-
for the controller design and code (6), (7), and (8).
trol and, hence, diverges. As the switching frequency increases,
the switching boundary layer decreases, and the analysis and
VI. SIMULATION its prediction are more accurate. With the maximum switching
A. Simulation Summary frequency that is not less than 20 kHz, the simulation results
faithfully represent the analysis. The initial conditions of i(0) =
The system responses under the following conditions are re-
0 and v(0) = 0 are used for all the simulations.
ported: 1) the input voltage, inductance, capacitance, and resis-
tance have uncertainties; 2) the input voltage has a step change;
3) the load resistance has a step change; 4) the input voltage has B. System Uncertainties
disturbances; 5) the reference voltage has a step change; 6) cur-
In this simulation, modeling uncertainties are considered.
rent ripple with practical circuit parameters; and 7) sensitivity
The new parameters are E = 75%E0 = 15 V, L = 20%L0 =
analysis. In the first four cases, the reference voltage is constant.
8 mH, C = 200%C0 = 8 μF and R = 500%R0 = 200 Ω. The
The fifth case is to test the ability of the controller for track-
output voltage is to track vd = 35 V. The top pane of Fig. 14
ing a reference voltage with step changes. The sixth case is to
shows that the inductor current i converges to id = vd2 /(RE) =
demonstrate that the proposed controller can generate a practical
0.41 A. The current ripple is slightly visible. The second pane
current ripple with practical circuit parameters and much lower
shows that the output voltage v converges to vd = 35 V. The
maximum switching frequency. The last case is to compare the
bottom pane shows 0 or 1 SMC signal. In the first 1 ms,
system performances between the ideal and practical circuits. To
MOSFET is OFF since u = 0. The relevant circuit is shown
control the presentation volume, only the overall traveling direc-
in Fig. 3. Ignoring nonideal circuit factors, plugging u = 0 into
tion of a transient of the output voltage (undershoot, overshoot,
(1) and (2), and eliminating i render
or nonminimum phase) is analyzed. The specifics regarding ris-
ing time, overshoot amplitude, and settling time of a transient L 
are not studied. The analytic approaches can be equally applied LCv  + v + v = E. (55)
R
to inductor current transients but a detailed exploration is be-
CHEN et al.: CLOSED-LOOP ANALYSIS AND CASCADE CONTROL OF A NONMINIMUM PHASE BOOST CONVERTER 1247

Fig. 14. Inductor current, the output voltage, and the sliding-mode control Fig. 15. Inductor current, the output voltage, and sliding-mode control signal
signal for system uncertainties. for the step changes of the input voltage.

With E = 15 V, L = 8 mH, C = 8 μF, and R = 200 Ω, the 0. The relevant circuit is shown in Fig. 3. With L = 40 mH, C =
two complex conjugated poles of (55) are −313 + 3940j. In the 4 μF, and R = 40 Ω, the two poles of (55) are −1250 and −5000
first 1 ms, the output voltage rises to about 25 V but before it and the output voltage is underdamped. In the first 2.5 ms, the
shows an oscillatory behavior, MOSFET starts to turn ON and output voltage rises to about 17.7 V. Afterward, MOSFET starts
OFF alternately due to SMC. Starting from the time point of to turn ON and OFF alternately due to SMC. Starting from the
1 ms, the output voltage has an undershoot and then converges time point of 2.5 ms, the output voltage displays an undershoot
to vd = 35 V through an oscillation. As proven in Section III-D, behavior and then converges to vd = 35 V without an oscilla-
the undershoot behavior is due to the nonminimum phase struc- tion. As proven in Section III-D, the undershoot behavior is due
ture. The oscillation is due to the complex poles of (36) after to the nonminimum phase structure. The underdamping is due
sliding mode occurs. With E = 15 V, R = 200 Ω, L = 8 mH, C = to the two real and negative poles of (36) after sliding mode
8 μF, and vd = 35, the poles of (36) are −300 ± 642j. Hence, an occurs. With the nominal parameters from Table I, the poles of
oscillation is expected. The steady-state inductor current track- (36) are −273 and −1123. The output voltage converges without
ing error is within ±0.05 A. The steady-state output voltage an overshoot.
tracking error is within ±0.5 V. In this simulation, despite the
large variations of all the circuit parameters, the output voltage D. Step Change of Load Resistance
is still convergent, the inductor current is limited, and the boost In this simulation, step changes of the load resistance are
converter still operates in continuous mode. The closed-loop considered. In the first 0.03 s, R is 40 Ω. At the time point of
system under the proposed controller is robust against system 0.03 s, R becomes 30 Ω. At the time point of 0.06 s, R becomes
uncertainties. 40 Ω again. The top pane of Fig. 16 shows that i converges to
id = 1.53 A in the first 0.03 s, id = 2.14 A in the second 0.03 s
C. Step Change of Input Voltage Source and id = 1.53 A in the remaining time. The mid pane shows
that v converges to vd = 35 V without an overshoot in the first
In this simulation, step changes of the input voltage are con-
0.03 s. At the time point of 0.03 s, R steps down from 40 to 30 Ω
sidered. In the first 0.03 s, E is 20 V. At the time point of
and v experiences an undershoot. At the time point of 0.06 s, R
0.03 s, E becomes 15 V. At the time point of 0.06 s, E becomes
steps up from 30 to 40 Ω and v experiences an overshoot. These
20 V again. The top pane of Fig. 15 shows that i converges to
transients are predicted in Section III-E. The switching signal is
id = 1.53 A in the first 0.03 s, id = 2.14 A in the second 0.03 s
shown in the bottom pane. Since the parametric conditions are
and id = 1.53 A in the remaining time. The mid pane shows
the same, the transient and its analysis for the first 2.5 ms are
that v converges to vd = 35 V without an overshoot in the first
the same as the ones in Section V-C and they are not repeated
0.03 s since the system is critically damped. At the time point
here. The steady-state inductor current tracking error is within
of 0.03 s, E steps down from 20 to 15 V and v experiences
±0.03 A. The steady-state output voltage tracking error is within
an undershoot. At the time point of 0.06 s, E steps up from 15
±0.5 V.
to 20 V and v experiences an overshoot. These transients are
predicted in Section III-E. The switching signal is shown in the
E. Input Voltage Source with Disturbance
bottom pane. The steady-state inductor current tracking error is
within ±0.03 A. The steady-state output voltage tracking error In this simulation, the input voltage source is mixed with a
is within ±0.5 V. In the first 2.5 ms, MOSFET is OFF since u = Gaussian distributed random signal with the 0 mean and the
1248 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 4, APRIL 2011

Fig. 18. Inductor current, the output voltage, and the sliding-mode control
Fig. 16. Inductor current, the output voltage, and sliding-mode control signal signal for the step change of the reference voltage.
for the step changes of the load resistance.

F. Step Change of Reference Voltage

In this simulation, step changes of the reference voltage are
considered. The reference voltage is 35 V in the first 0.03 s,
40 V in the second 0.03 s, and 35 V in the remaining time. The
top pane of Fig. 18 shows that i converges to id = 1.53 A in the
first 0.03 s, id = 2.08 A in the second 0.03 s, and id = 1.53 A
in the remaining time. The mid pane shows that v converges to
vd = 35 V without an overshoot in the first 0.03 s. At the time
point of 0.03 s, it converges to vd = 40 V after going in the
right direction first and experiencing an undershoot afterward.
At the time point of 0.06 s, it converges to vd = 35 V after
going in the right direction first and experiencing an overshoot
afterward. The switching signal is shown in the bottom pane.
Since the parametric conditions are the same, the transient and
its analysis for the first 2.5 ms are the same as the ones in Section
V-C and they are not repeated here. The steady-state inductor
current tracking error is within ±0.03 A. The steady-state output
voltage tracking error is within ±0.5 V.
The top and third panes of Fig. 19 show the details of the
transient of the output voltage and the switching signal around
Fig. 17. Inductor current, the output voltage, and the sliding-mode control for the time points of 0.03 s. The output voltage goes in the right
the input voltage mixed Gaussian disturbance. direction for about 27 μs during which it rises to about 39 V
and the switching signal is 0. The relevant circuit is shown in
Fig. 3 but the perturbation of (55) is preferred for analysis. Let
vδ and Eδ be the perturbations of v and E. One has v = vδ + ve
2 variance. These noisy signals are shown in the first pane and E = Eδ + Ee where ve and Ee are the equilibrium points
of Fig. 17. The inductor current, the output voltage, and the of the output voltage and input voltage, respectively. Then, (55)
SMC are shown in the next three panes. The inductor cur- becomes
rent converges to id = 1.59 A and the output voltage con-
L 
verges to vd = 35 V. The closed-loop system under the pro- LCvδ + v + v δ = Eδ . (56)
posed controller is robust against disturbances and can filter R δ
high-frequency noise signals. Since the parametric conditions
are the same, the transient and its analysis for the first 2.5 ms With L = 40 mH, C = 4 μF, and R = 40 Ω, the two poles
are the same as the ones in Section V-C and they are not re- of (56) are −1250 and −5000 and the output voltage is un-
peated here. The steady-state inductor current tracking error is derdamped. The output voltage rises from 35 to 39 V. However,
within ±0.03 A. The steady-state output voltage tracking error before it converges to 40 V, MOSFET starts to turn ON and OFF
is within ±0.5 V. alternately due to SMC. After the time point of 0.030027 s, the
CHEN et al.: CLOSED-LOOP ANALYSIS AND CASCADE CONTROL OF A NONMINIMUM PHASE BOOST CONVERTER 1249

Fig. 20. Current ripple with practical parameters.

Fig. 19. Output voltage and the sliding-mode control signal around the tran-
sient time points of 0.03 and 0.06 s for the step changes of the reference voltage.
G. Ripple Current with Practical Parameters
output voltage experiences an undershoot and then converges to In this simulation, the nominal circuit parameters of E0 =
vd = 40 V without an oscillation. As proven in Section III-D, 20 V, R0 = 200 Ω, L0 = 16 mH, C0 = 20 μF, and vd0 = 50 V
the undershoot behavior is due to the nonminimum phase struc- are used. Following the procedure described in Section V-D and
ture. The underdamping without oscillation is due to the two with the two poles of −400, the PI gains become Kp = 0.0071
real and negative poles of (36) after sliding mode occurs. With and Ki = 5.8333. The actual circuit parameters are assumed
vd = 40 V and the other nominal parameters in Table I, the poles to be E = 20 V, R = 200 Ω, L = 16 mH, and C = 20 μF.
of (36) are −269 and −893. The Off-the-Shelf switches, RC = 0.02 Ω and RL = 0.01Ω are
The second and fourth panes of Fig. 19 show the details of the considered. The circuit tracks the reference voltage vd = 35 V.
transient of the output voltage and the switching signal around The simulation step size is 50 μs. Thus, the maximum switching
the time points of 0.06 s. The output voltage goes in the right frequency is 20 kHz. The top pane of Fig. 20 shows the classic
direction in the first 20 μs during which it falls to about 35.3 V inductor current ripple that is often seen in experiments. The
and the switching signal is 1. The relevant circuit is shown in mid pane shows the output voltage. The bottom pane shows the
Fig. 2. Ignoring nonideal circuit factors and plugging u = 1 into SMC signal. The steady-state inductor current is 0.3 A and its
(2) render tracking error is within ±0.1 A. The steady-state output voltage
CRv  + v = 0. (57) is 35 V and its tracking error is within ±1 V. In the first 0.25 ms,
the switching signal is 1 and the output voltage is 0. The circuit
Equation (57) is a first-order differential equation. Its solution is shown in Fig. 2. The capacitor is not charged. Due to the zero
is initial voltage of the capacitor and according to (58), the output
1 voltage is equal to 0. In the next 1.35 ms, the switching signal
v = v0 e C R (t−t 0 ) . (58)
is 0. The circuit is shown in Fig. 3. With E = 20 V, R = 200 Ω,
where v0 and t0 are the initial voltage and initial time. Plugging L = 16 mH, and C = 20 μF, the two complex conjugated poles
v0 = 35 V, t − t0 = 20 μs, R = 40 Ω, and C = 4 μF into (58) of (55) are −156± 1970j. For a underdamped second-order
renders v = 35.3 V. Hence, the output voltage decays to 35.3 V system with the Laplace transform of the characteristic equation
through an exponential trajectory. However, before it decays to such as a2 s2 + a1 s + a0 = a2 (s2 + 2ζwn s + wn2 ) where ζ is
35 V, MOSFET starts to turn ON and OFF alternately due to the damping coefficient and w n is the natural frequency, the
SMC. After the time point of 0.03002 s, the output voltage goes oscillation period is wn = 2π/ a0 /a2  [36]. Thus, the output
in the wrong direction and then converges back to vd = 35 V voltage oscillation period for (55) is 2π/ 1/(LC) = 0.0032s.
without an oscillation. As proven in Section III-D, the wrong Theoretically, at the time point of 1.6 ms, the output voltage
direction (overshoot) is due to the nonminimum phase structure. should have been about 33.76 V. Since the nonideal factors are
The underdamping without an oscillation is due to the two real considered in the circuit, the output voltage actually reaches
and negative poles of (36) after sliding mode occurs. With vd = 35.25 V at this time point at which MOSFET starts to turn ON
35 V and the other nominal parameters in Table I, the poles of and OFF alternately due to SMC. Starting from the time point of
(36) are −273 and −1123. 1.55 ms, the output voltage experiences an undershoot and then
The steady-state inductor current tracking error is within converges to vd = 35 V through an oscillation. As proven in
±0.03 A. The steady-state output voltage tracking error is within Section III-D, the boost converter under the proposed controller
±0.5 V. still has an undershoot behavior even if the proportional gain is
1250 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 4, APRIL 2011

positive and the zero of F(s) in (36) is negative. The oscillation

is due to the complex poles of (36) after sliding mode occurs.
With E = 20 V, R = 200 Ω, L = 16 mH, and C = 20 μF, the two
complex conjugated poles of (55) are −441±167j. However,
the oscillation amplitude is so small that it is invisible in the plot
(actually, for a unit step response, the overshoot of (36) with
the parameters used in this simulation is 0.4 mV). Meanwhile,
the nonideal factors of the circuit has reshaped the undershoot
behavior to be a classic one.
In summary, the proposed controller can easily be applied
to a boost converter with practical circuit parameters, lower
maximum switching frequencies and very high voltage track-
ing accuracy; the analytic theories developed in this paper can
equally be extended to such a practical converter.

H. Sensitivity Analysis
Fig. 21. Inductor currents, load currents, and output voltages for both ideal
In this simulation, the nominal circuit parameters of E0 = and nonideal circuits.
20 V, R0 = 200 Ω, L0 = 16 mH, C0 = 20 μF, and vd0 = 50 V
are used. Following the procedure described in Section V-D and
with the two poles of −400, the PI gains become Kp = 0.0071
and Ki = 5.8333. The actual circuit parameters are assumed to
be E = 20 V, R = 200 Ω, L = 16 mH and C = 20 μF. The
Off-the-Shelf switch devices, RC = 5 Ω and RL = 5 Ω (larger
dc resistances make the sharper differences) are considered. The
reference voltage vd = 35 V is tracked. The simulation step size
is 10 ms. Thus, the maximum switching frequency is 100 kHz.
First, the simulation is carried out with the ideal switch de-
vices, the ideal capacitor without equivalent series resistance
and the ideal inductor without series resistance. The inductor
current ii , the load current Ioi , and the output voltage vi are
obtained. Afterward, the simulation is carried out with the Off-
the-Shelf switch devices, RC = 5 Ω and RL = 5 Ω. The induc-
tor current ia , the load current Ioa , and the output voltage va
are obtained. ia and ii are plotted in the top pane of Fig. 21 and
their error Δi = ia − ii is plotted in the top pane of Fig. 22. Fig. 22. Inductor current error, load current error, and output voltage error for
Ioa and Ioi are plotted in the mid pane of Fig. 21 and their both ideal and nonideal circuits.
error ΔIo = Ioa − Ioi is plotted in the mid pane of Fig. 22.
va and vi are plotted in the bottom pane of Fig. 21 and their words, the steady state inductor current is sensitive to the non-
error Δv = va − vi is plotted in the bottom pane of Fig. 22. In ideal circuit factors; the steady state load current, and voltages
Fig. 21, the variables from the ideal circuit are in solid line and are insensitive to the nonideal factors due to the closed-loop
blue color; the variables from the nonideal circuit are in dotted control.
line and red color. The following conclusion is drawn.
The average value of the steady state inductor current error
Δi is greater than 0. The average values of the steady state VII. CONCLUSION
load current and output voltage are 0. The steady state inductor This paper deals with the cascade controller with PI and SMC
current ripple, the steady state load current tracking error, and for a boost converter. A scientific guideline for the design and
the steady state output voltage tracking error for the ideal cir- analysis of such a cascade controller has been provided. The PI
cuit are less than their counterparts for the nonideal circuit. The gains are selected based on the rigorous analysis of the at least
closed-loop controller has generated more steady state induc- semiglobally stable nonlinear closed-loop system. The stabil-
tor current to compensate voltage drops caused by the nonideal ity and robustness of the closed-loop system are analyzed and
circuit components. The closed-loop controller has guaranteed demonstrated through the pole placement, the phase portrait and
the same average values of the steady state load current and frequency response. The two equilibrium points and two discon-
output voltage for both circuits. The proposed controller is ca- tinuous subspaces of the closed-loop system are discovered and
pable of working with a boost converter taking into account the analyzed. The operational range of the reference voltage is stud-
Off-the-Shelf switch devices, the equivalent series resistance for ied. The nonminimum phase behaviors of the boost converter
the capacitor, and the series resistance for the inductor. In other are analyzed and simulated for various cases. The transient
CHEN et al.: CLOSED-LOOP ANALYSIS AND CASCADE CONTROL OF A NONMINIMUM PHASE BOOST CONVERTER 1251

behaviors for step changes of the input voltage and load re- [16] Y. J. Lee, A. Khaligh, and A. Emadi, “A compensation technique for
sistance are modeled and analyzed. The average load current smooth transitions in a non-inverting buck–boost converter,” IEEE Trans.
Power Electron., vol. 24, no. 4, pp. 608–614, Apr. 2009.
and voltage are shown to be insensitive to the nonideal circuit [17] V. I. Utkin, J. Guldner, and J. X. Shi, Sliding Mode Control in Electrome-
parameters. A variety of operating conditions are simulated. chanical Systems. London, UK: Taylor & Francis, 2008.
The system has robust performances under step changes of in- [18] F. Bilalovic, O. Music, and A. Sabanovic, “Buck converter regulator op-
erating in the sliding mode,” in Proc. 7th International PCI Conf. Rec.,
put voltage, load resistance and reference voltage. The system 1983, pp. 331–340.
rejects disturbances of input voltage, modeling uncertainties, [19] R. Venkataramanan, A. Sabanovic, and S. Cuk, “Sliding mode control of
and unmodeled parameters. dc-dc converters,” IEEE Trans. on Power Electron., vol. 55, no. 3, Mar.
2008.
The future work includes extension of the method to other [20] P. Mattavelli, L. Rossetto, and G. Spiazzi, “Small-signal analysis of DC-
SISO and MIMO dc–dc converters and digital implementation DC converters with sliding mode control,” IEEE Trans. Power Electron.,
of the controller with a microcontroller on a boost converter. vol. 12, no. 1, pp. 96–102, Jan. 1997.
[21] V. I. Utkin, “Sliding mode control design principles and applications to
The performances of this controller and the other controllers electric drives,” IEEE Trans. Ind. Electron., vol. 40, no. 1, pp. 23–36,
regarding robustness, stability, tracking error, switching effi- Feb. 1993.
ciency, reduction of harmonics, current ripple, voltage ripple, [22] S. C. Tan, Y. M. Lai, and C. K. Tse, “General design issues of sliding-mode
controllers in DC-DC converters,” IEEE Trans. Ind. Electron., vol. 55,
etc., would be compared in the future research through a scien- no. 3, pp. 1160–1173, Mar. 2008.
tific and systematic approach. [23] H. Sira-Ramirez and M. Rios-Bolivar, “Sliding mode control of DC-to-
DC power converters via extended linearization,” IEEE Trans. Circuits
Syst., vol. 41, no. 10, pp. 652–661, Oct. 1994.
ACKNOWLEDGMENT [24] S. C. Tan, Y. M. Lai, and C. K. Tse, “A unified approach to the design of
PWM-based sliding-mode voltage controllers for basic DC-DC converters
Z. Chen would like to thank Prof. V. Utkin at The Ohio State in continuous conduction mode,” IEEE Trans. Circuits Syst., vol. 53, no. 8,
University and J. Shi for their discussion on the closed-loop pp. 1816–1827, Aug. 2006.
[25] B. S. Yuri, A. S. I. Zinober, and I. A. Shkolnikov, “Boost and buck-
system analysis and control of power converters. boost power converters control via sliding modes using dynamic sliding
manifold,” in Proc. 41st IEEE Conf. Decis. Control, Dec. 2002, vol. 3,
pp. 2456–2461.
REFERENCES [26] S. Baev and Y. Sheessel, “Causal output tracking in nonminimum phase
boost DC/DC converter using sliding mode techniques,” in Proc. Amer.
[1] R. S. Weissbach and K. M. Torres, “A non-inverting buck-boost con-
Control Conf., Jun. 2009, pp. 77–82.
verter with reduced components using a microcontroller,” in Proc. IEEE
[27] Y. He and F. L. Luo, “Study of sliding mode control for DC-DC convert-
Southeast Conf., Aug. 2002, pp. 79–84.
ers,” in Proc. Power Syst. Technol.-Powercon, Nov. 2004, pp. 1969–1974.
[2] S. L. Liu, J. Liu, H. Mao, and Y. Q. Zhang, “Analysis of operating modes
[28] E. Alarcon, A. Poveda, S. Porta, and L. Martinez-Salamero, “Sliding-mode
and output voltage ripple of boost dc–dc converters and its design consid-
control analog integrated circuit for switching DC-DC power converter,”
erations,” IEEE Trans. Power Electron., vol. 23, no. 4, pp. 1813–1821,
in Proc. IEEE Int. Symp. Circuits and Syst., May 2001, vol. 1, pp. 500–503.
Jul. 2008.
[29] A. Visioli, Practical PID Control. London, UK: Springer, 2006.
[3] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics.
[30] H. Guldemir, “Sliding mode control of DC-DC boost converter,” J. Appl.
Boston, USA: Kluwer Academic Publishers, 2004.
Sciences, vol. 5, no. 3, pp. 588–592, 2005.
[4] D. Xu, C. Zhao, and H. Fan, “A PWM plus phase shift control bidirectional
[31] A. Ramirez and E. Perez, “Stability of current-mode control of DC-DC
dc-dc converter,” IEEE Trans. Power Electron., vol. 19, no. 13, pp. 666–
power converters,” Syst. and Control Letters, vol. 45, pp. 113–119, May
675, May 2004.
2002.
[5] D. M. Mitchell, DC-DC Switching Regulator Analysis. New York, USA:
[32] K. Al-Hosani, A. Malinin, and V. I. Utkin, “Sliding mode PID control of
McGraw-Hill, 1998.
buck converters,” in Proc. Eur. Control Conf.(ECC), Aug. 2009.
[6] A. J. Forsyth and S. V. Mollow, “Modeling and control of dc-dc convert-
[33] H. Sira-Ramirez, “On the generalized PI sliding mode control of DC-
ers,” Power Eng. J., vol. 12, no. 5, pp. 229–236, Aug. 1998.
to-DC power converters: A tutorial,” Int. J. Control, vol. 76, no. 9/10,
[7] H. Sira-Ramirez and R. Silva-Origoza, Control Design Techniques in
pp. 1018–1033, Sep./Oct. 2003.
Power Electronics Devices. New Mexico City, USA: Springer, 2006.
[34] S. C. Tan, Y. M. Lai, and C. K. Tse, “Indirect sliding mode control of
[8] T. T. Song and H. S. Chung, “Boundary control of boost converters using
power converters via double integral sliding surface,” IEEE Trans. Power
state-energy plane,” IEEE Trans. Power Electron., vol. 23, no. 2, pp. 551–
Electron., vol. 23, no. 2, pp. 600–611, Mar. 2008.
563, Mar. 2008.
[35] H. K. Knalil, Nonlinear Systems. Upper Saddle River, NJ: Prentice-Hall,
[9] G. Chu, C. K. Tse, S. C. Wong, and S. X. Tan, “A unified approach for
2002.
the derivation of robust control for boost PFC converters,” IEEE Trans.
[36] G. F. Franklin, J. D. Powell, and E. N. Abbas, Feedback Control of Dy-
Power Electron., vol. 24, no. 1, pp. 2531–2544, Nov. 2009.
namic Systems. New York City, USA: Addison Wesley, 1991.
[10] S. Mariethoz, S. Almer, M. Beja, et al., “Comparison of hybrid control
[37] Z. S. Chen, W. Z. Gao, and X. Ye, “Frequency domain closed-loop analysis
techniques for buck and boost DC-DC converters,” IEEE Trans. Control
and sliding mode control of a nonminimum phase buck-boost converter,”
Syst. Technol., vol. 18, no. 5, pp. 1126–1145, Sep. 2010.
Control and Intell. Syst., vol. 38, no. 4, pp. 246–255, Nov. 2010.
[11] K. M. Smedley and S. Cuk, “One-cycle control of switching converters,”
[38] W. G. Yan, J. G. Hu, V. I. Utkin, and L. Y. Xu, “Sliding mode pulsewidth
IEEE Trans. Power Electron., vol. 10, no. 6, pp. 625–633, Nov. 1995.
modulation,” IEEE Trans. Power Electron., vol. 23, no. 2, pp. 619–626,
[12] T. Y. Jiang and R. Dougal, “Synergetic control of power converters for
Mar. 2008.
pulse current charging of advanced batteries from a fuel cell power
source,” IEEE Trans. Power Electron., vol. 19, no. 4, pp. 1140–1150,
Jul. 2004. Zengshi Chen received the Ph.D. degree in sys-
[13] B. Arbetter and D. Maksimovic, “DC-DC converter with fast transient tems and controls from The Ohio State University,
response and high efficiency for low-voltage microprocessor loads,” in Columbus, in 2006.
Proc. IEEE Appl. Power Electron., Feb. 1998, vol. 1, pp. 156–162. He is a Research Scientist for some universities
[14] L. Malesani, P. Mattavelli, and P. Tomasin, “Improved constant-frequency and corporations. His current research interests in-
hysteresis current control of VSI inverters with simple feedforward band- clude variable structure systems, sliding-mode con-
width prediction,” IEEE Trans. Ind. Appl., vol. 33, no. 5, pp. 1194–1202, trol, nonlinear control and their applications to power
Sep./Oct. 1997. converters, inverters and renewable energy machines.
[15] J. W. Kimball, P. T. Krein, and Y. X. Chen, “Hysteresis and delta modu-
lation control of converters using sensorless current mode,” IEEE Trans.
Power Electron., vol. 21, no. 4, pp. 1154–1158, Jul. 2006.
1252 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 4, APRIL 2011

Wenzhong Gao received the M.S. degree and Ph.D. Xiao Ye is currently pursuing the M.S. degree from
degrees in electrical and computer engineering spe- the School of Electric Machinery and Electric Appa-
cializing in electric power engineering from Georgia ratus, Hefei University of Technology, Hefei, China.
Institute of Technology, Atlanta, in 1999 and 2002, Her current research interests include dc–dc power
respectively. converters and sliding-mode control.
He is an Assistant Professor in the Depart-
ment of Electrical and Computer Engineering, Uni-
versity of Denver, Denver, CO. His current teach-
ing and research interests include renewable energy
and distributed generation, power-electronics appli-
cation, power-system protection, power-system mod-
eling and simulation, hybrid electric propulsion systems.

Jiangang Hu received the B.Eng. and M.Eng. de-

grees in electrical engineering from the Huazhong
University of Science and Technology, Wuhan,
China, in 1997 and 2000, respectively, and the Ph.D.
degree in electrical engineering from The Ohio State
University, Columbus, in 2007.
Since 2007, he has been a Senior Development
Engineer with Kinetix Motion Control, Rockwell Au-
tomation, Milwaukee, WI. His current research inter-
ests include high-performance motion control, sen-
sorless control for variable-speed ac drive system,
high-speed integrated starter and generator system, sliding-mode control, and
power-converter design.