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SRL NVQ Tech Test

This document contains a common written examination for Mechatronics Technology at the NVQ Level 5 semester 1. It consists of 20 multiple choice questions in Part A testing concepts in applied electronics and 10 questions in Part B requiring longer explanations on topics including semiconductors, diodes, transistors, operational amplifiers, logic gates, and flip flops. Students are instructed to answer all questions in Part A and 4 out of the 5 questions in Part B. The exam is 3 hours long and tests knowledge at an advanced vocational level in mechatronics and applied electronics.

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230 views4 pages

SRL NVQ Tech Test

This document contains a common written examination for Mechatronics Technology at the NVQ Level 5 semester 1. It consists of 20 multiple choice questions in Part A testing concepts in applied electronics and 10 questions in Part B requiring longer explanations on topics including semiconductors, diodes, transistors, operational amplifiers, logic gates, and flip flops. Students are instructed to answer all questions in Part A and 4 out of the 5 questions in Part B. The exam is 3 hours long and tests knowledge at an advanced vocational level in mechatronics and applied electronics.

Uploaded by

Shohan Taylor
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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TERTIARY AND VOCATIONAL EDUCATION COMMISSION

COMMON WRITTEN EXAMINATION – 2018

Mechatronics Technology
NVQ Level 5 Semester l Examination

APPLIED ELECTRONICS - D33C001M03


Instructions to Candidates:
1. Answer all questions in Part A and any four (04) in Part B
2. Commence to answer each question on a fresh page.
Time: 03 hours Total Marks: 10

PART A
1. Define Knee Voltage
2. What is rectification
3. What kind of biasing will be required to the Base-Emitter and Base-Collector junctions
when a transistor is used as an amplifier?
4. Give the relation between α and β.
5. Calculate IC,IE and β for a transistor that has α=0.98 and IB=100µA
6. List two (2) characteristics of an ideal op amp.
7. What is the advantage of Digital representation over a analog
8. Convert (BCDE)16 = (………….)2
9. The inputs to a two-input AND gate have the following values for equal periods of time. (A,
B)=(O,O),(1, 1),(0, 1), (0,0),(1,0),(1, 1),(0,0). Draw the timing diagrams showing the
waveforms for the inputs A and B and the output Y.
10. List the binary outputs at the normal output (Q) of the RS flip-flop shown in fig 01.

fig 01

(20 Marks)

1|Page
PART B

Q 01

1. Give two differences between intrinsic and extrinsic semiconductors. (4 Marks)


2. Explain the operation of P-N junction diode under forward and reverse bias conditions with
the help of V-I characteristic curve. (8 Marks)
3. With a neat circuit diagram, explain the working of half wave rectifier along with relevant
waveforms. (6 Marks)
4. What is the need for capacitive filter? Explain. (2 Marks)
(20 Marks)
Q 02

1. Distinguish between avalanche and zener breakdown (6 Marks)


2. Explain with neat diagram how zener diode can be used as voltage regulator (6 Marks)
3. In the zener diode circuit shown in fig 02, find the current flowing in the zener diode and the
power dissipated in the zener diode. (8 marks)
(20 Marks)

fig 02

Q 03
1. Why transistor is called as current controlled device? (2 Marks)
2. The figure 03 shows Si BJTs with β 1 = 100 and β 2 = 50, determine the currents through
the Transistors and Collector – Emitter Voltages of each transistors.

(12 Marks)

470 Ω

Fig 03

2|Page
3. Design the circuit for the fig 04 (i.e., find RS and RD) in order to get ID = 0.25 mA and VD =
0 and VTH = 1 V (6 Marks)

fig 04

(20 Marks)

Q 04
1. Draw the circuit of non-inverting op amp and derive the expression for the voltage gain.
(4 Marks)
2. With neat circuit and necessary equations, explain the voltage follower circuit using
operational amplifier. Mention its important properties. (8 Marks)
3. Find the output voltage for the following fig 05, when V1 =50 mV and V2 =30 mV.
(8 marks)

fig 05

(20 Marks)

3|Page
Q 05

1. Realize Y = AB + CD + E using NAND gates. (4 Marks)

2. Minimize the following Boolean function using K-Maps then draw the logic circuit
diagram:

F (A, B, C, D) =∑ (1, 3, 4, 5, 10, 11, 12, 13, 14, 15) (12 Marks)

3. With the help of logic diagram and truth table explain the working of RS Flip Flop.
(4 Marks)
(20 Marks)

4|Page

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