Tips For Simulation Debug

ATPG Pattern Validation

December 2015
 How and where to start?

• It’s not unusual to have to debug failing ATPG patterns

• Issues could vary from differences in models used in ATPG vs.
Simulation to timing related issues not masked in ATPG

• As a starting point, investigate the TetraMAX ATPG log

– Review run_build step warnings to see if they could be a cause
– Review DRC S and C type warnings S18,S29,S22,C12,C39 etc
– Review ATPG banner warning message that warns about violations that
could lead to failing patterns
– Review run_atpg messages
– Review the write_patterns step to see if any M type message warn about
possibility of pattern failure

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 Are they timing related failures?

• Use VCS switches with purpose

– Understand what each one is doing and if it makes sense to use it with
pattern validation
• Try +delay_mode_zero, +tetramax to eliminate timing issues
• Spend some time understanding the different `define for timing modes
used in the libraries and what should be used with ATPG patterns
• With SDF investigate any SDF annotation warnings or errors
• Try all timing corners to narrow down the issue
• Are the chain test patterns failing ?
– This is an important question. You need to understand if the integrity of the
chain is compromised. Can you safely shift in a sequence of 1s and 0s and
then shift them out as expected?

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 Chain test vs Capture

• Why this question?

– Need to understand if you are debugging a hold time issue on your shift
path or your capture path
– Shift path issues would result in chain test failing
– Capture path issues would mean that chain test passes and failures are
seen later in patterns that exercise a clock with scan enable inactive
– Chain test issues are independent of any capture issues
– Usually C type DRC warnings would not impact chain test
– Before looking into chain test failures investigate STA results
– Run chain test in mode with shortest length chains to speed up debug
– Adjust chain test patterns using set_atpg –chain_test 10C (or 1000)
to have a leading 1 followed by 0s shifted through the chains for easier
debug

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 Report Scan Cell

report_scan_cell -all -verbose

chain cell type edge inv gate# clocks instance_name (type)
------- ---- ------- ---- --- ------ ------- -------------------------
c1 0 MASTER LE NN 29 + clk1 flop7 (FD1S)
c1 1 MASTER LE NN 28 + clk1 flop6 (FD1S)
c1 2 MASTER LE NN 27 + clk1 flop5 (FD1S)
c1 3 MASTER LE NN 26 + clk2 flop4 (FD2S)
c1 4 MASTER LE NN 25 + clk2 flop3 (FD1S)
c1 5 MASTER LE NN 24 + clk2 flop2 (FD1S)
SHADOW LE NN 30 + clk2 nonscan_flop (FD1)
c1 6 MASTER LE NN 23 + clk2 flop1 (FD1S)

• Check that scan chain matches what was expected by user

• Check clock crossing, polarity, lockups and shadows

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 Top Question that should be asked
• Have you performed STA in Test_Mode for capture and shift?

#after run_build,run_drc
source tmax2pt.tcl
write_timing_constraints cap.tcl -mode capture -replace
write_timing_constraints shift.tcl –mode shift -replace

In PrimeTime:
Verify any other exceptions read in and used

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 Double Check STA Reports
• Use remove_generated_clock for any leftover functional clocks

pt_shell> report_timing -from ipdet_dp_clk13m0_reg/Q -to ipdet_dp_cnt_reg_0_/SI -delay min

Startpoint: ipdet_dp_clk13m0_reg/Q
Wrong clock is picked up
(clock source 'clk_13m0')
Endpoint: ipdet_dp_cnt_reg_0_
(rising edge-triggered flip-flop clocked by SCLK)
Path Group: SCLK
Path Type: min
Point Incr Path
---------------------------------------------------------------
clock clk_13m0 (fall edge) 612.00 612.00
clock source latency 0.00 612.00
Wrong edge for TEST

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 Sanity check for patterns

• If you see only capture failures then validating the patterns in

TetraMAX would be worthwhile.
set_patterns -external save_atpg_patterns
run_simulation

• If run_simulation fails, then investigating failing pattern in TetraMAX

could lead to a modeling issue or some ATPG setting
• Find out if failures are a few or massive
– How many patterns fail?
– Do they share a common clock?
• Use report_pattern –all –type to dig into clock use

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 Pattern Report Information

report_pattern –all Pattern Label

Pattern 0 (basic_scan-chain_test)
Time 0: load c1 = 0011001 Scan Chain load
Time 1: force_all_pis = 010001
Time 2: measure_all_pos = Z0 Scan chain unload

Time 3: unload c1 = 0011001

Pattern 1 (basic_scan)
Time 0: load c1 = 0100011
Time 1: force_all_pis = 100010
Capture Clock name and id
Time 2: measure_all_pos = Z0
Time 3: pulse clocks clk2 (3) X for masked bit

Time 4: unload c1 = 0101X01

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 Options in Pattern Generation Flow

• Inspect original pattern generations script for commands that could

affect pattern simulation results

set_simulation -xclock_gives_xout
set_simulation –bidi_fill
set_rule C12 –nomask
set_rule S18 warning

• Check log file for any other S22 and S29 violations, and any C
violations that might not be masked
• If failure is seen in parallel only check number of serial shifts being
used in TestBench

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 Patterns and Testbenchs

• Run both types of patterns serial and parallel, to narrow down which
one fails
• Testbench used should be “MAX Testbench”
• Recommended to do a subset of serial patterns to ensure full
simulation of the shift path as well as complete exercise of all
compression logic
• Rest of patterns can be done in parallel mode.
– With compression this mode bypasses simulation through CODEC
– Understand scan cells are measured and loaded
– Understand if Shadow cells need serial shifts to load correctly
– Understand any issues with S29 and lockups on trailing edge flops
– Investigate memory models with wrapper chains

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 Understand Timing specified in SPF

• Period , clock and strobe timing used in SPF is what translates to

timing used in testbench
Length of tester cycle for shift and
• Timing {
WaveformTable _default_WFT_ { capture
Period '100ns';
Waveforms { Inputs applied without delay at start of
_default_In_Timing_ { 0 { '0ns' D; } } cycle
_default_In_Timing_ { 1 { '0ns' U; } }
_default_In_Timing_ { Z { '0ns' Z; } } Clock rise and fall time
_default_In_Timing_ { N { '0ns' N; } }
_default_Clk0_Timing_ { P { '0ns' D; '50ns' U; '80ns' D; } }
_default_Clk1_Timing_ { P { '0ns' U; '50ns' D; '80ns' U; } }
_default_Out_Timing_ { X { '0ns' X; } }
_default_Out_Timing_ { H { '0ns' X; '40ns' H; } }
_default_Out_Timing_ { T { '0ns' X; '40ns' T; } }
_default_Out_Timing_ { L { '0ns' X; '40ns' L; } }
}
} Measure time for outputs and scan
} cells
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 Force Release and Strobe Timing in Parallel
Load Simulation

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 Force/release for parallel sims

• There are tags in the MAXTestbench you can display in waves to see
force/strobe/release times for parallel testbench

Strobe/force

release

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 Run time options for simulation

• To turn on wave dumping for verdi use +define+tmax_fsdb

• To get verbose messages while simulation is run use
+define+tmax_msg=4
• To control number of patterns simulated use
+define+tmax_n_pattern_sim=100
• To control if serial or parallel is used, use +define+tmax_serial or
+define+tmax_parallel
• To control created of a file for diagnosis +define+tmax_diag=1
• To match parallel reported timing to serial sims use
+define+tmax_serial_timing
• To use a new data file in simulation use
+define+tmax_test_data_file="myfile.dat"

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 Failures Due to load_unload timing

Procedures {
"load_unload" {
W "_default_WFT_";
C { "test_si2"=Z;
"test_si1"=Z; "test_so2"=X;
"test_so1"=X; "clk2"=0;
"clk1"=0; "clk3"=0; "reset"=1; Changing C to V
"SCAN_EN"=1; "reset"=1; will add an extra
} test_cycle that
Shift { might be needed
W "_default_WFT_"; with long scan_en
V { "_si"=##; "_so"=##; insertion delay
"clk2"=P; "clk1"=P; }
}
}

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 Failures Due to Clock LE_TE timing

Timing {
WaveformTable "_default_WFT_" {
Period '100ns';
Waveforms { Having clock edge
too late in the
"clk2" { P { '0ns' D; '45ns' U; '55ns' D; cycle effects
} } parallel testbench
"clk1" { P { '0ns' D; ‘85ns' U; ‘95ns' D; with SDF max
} } timing

Due to insertion delay falling edge flops will get their clock edge too late
causing failures in Parallel Testbench only due to broadside load issues.
Serial sims will pass. Release of SI is done before clock edge reaches flop

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 Hold Time Issue

D E

Same bit gets loaded into B C F

and C in the same clock cycle
Shoot-through
B G

A H

0011 pattern comes

SI SO Out too early

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 Timing Violation

The Flop UDP has a notifier that produces X on violations

$setup(TI, posedge CP &&& TE, TI_SETUP$, notifier);
$hold(posedge CP, TI &&& TE, TI_HOLD$, notifier);

D E

C F

B G

A H

SI SO Exp 1 got X

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 Only one way to debug

• Need to compare waveforms of failing flops in simulation vs.

TetraMAX expected value using analyze_simulation_data
command

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 Compare capture period in waves vs. tmax

Can see flop captures

A 0 instead of 1

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