DEVICES AND COMMUNICATION

BUSES FOR DEVICES NETWORK–

Lesson-6: Parallel port at devices

Chapter-3 L06: "Embedded Systems - " , Raj Kamal,

2008 1
Publs.: McGraw-Hill Education
 Parallel Port

λ 8-bit IOs
λ Short distances, generally within a
circuit board or IC or nearby external
devices

Chapter-3 L06: "Embedded Systems - " , Raj Kamal,

2008 2
Publs.: McGraw-Hill Education
 Parallel port in the devices
• Advantage− Number of 8 bits over the
wires in parallel.
• High data transfer rate
• Disadvantage− More number of wires
• Capacitive effect in parallel wires reduces
the length up to which communication in
parallel can take place.
• High capacitance results in delay for the
bits at the other end undergoing transition
from 0 to 1 or 1 to 0.
Chapter-3 L06: "Embedded Systems - " , Raj Kamal,
2008 3
Publs.: McGraw-Hill Education
 Parallel port in the devices
• Disadvantage− High capacitance can
also result in noise and cross talk
(induced signals) between the wires.

Chapter-3 L06: "Embedded Systems - " , Raj Kamal,

2008 4
Publs.: McGraw-Hill Education
 Port Interfacing
λ IO device interfacing-circuit with the
processor and system buses and connections
to external peripherals/systems
λ Parallel port inputs I0 to I7 may be from a
keypad controller.
λ Parallel port outputs O0 to O7 may be
output bits to LCD display output
controller.
λ Bri and Bro buffers may be provided at bi-
directional I/O port
Chapter-3 L06: "Embedded Systems - " , Raj Kamal,
2008 5
Publs.: McGraw-Hill Education
Parallel port interfacings for keypad, LCD display and modem
CS-Port Select
BRi-Buffer Register
for Input
BRo-Buffer Register An Input Port
for Output CS BRi
I0-I7
Key Pad

IORD
Ai-Aj

Port
Addresses An Output Port
Decoder BRo
CS O0-O7
Processor LCD Display

IOWR
An I/O Port

BRi
IO0-IO7

IORD Modem
BRo
Messages
Note:
A Port can have 1 or 2 IOWR
or more Addresses
Allotted for it and Address Bus Inputs also (a)
Chapter-3 L06: "Embedded Systems - " , Raj Kamal,
2008 6
Publs.: McGraw-Hill Education
 Handshaking signals to and from an external
peripheral device for input at port
λ Device makes a strobe request to port,
STROBE after it is ready to send the
byte and
λ System I/O port sends the
acknowledgement, PORT READY.
λ System I/O port receives data in buffer
and then issues an interrupt signal, INT
to processor to enable an ISR
execution
Chapter-3 L06: "Embedded Systems - " , Raj Kamal,
2008 7
Publs.: McGraw-Hill Education
 Handshaking signals to and from an external
device for output at port
λ Device sends the message
ACKNOWLEDGE when and the I/O
device port ends the BUFFER FULL
signal to inform that the is buffer full.
λ The processor is sent the INTERRUPT
REQUEST message, when the
transmitting-buffer is empty (available
for next write)
Chapter-3 L06: "Embedded Systems - " , Raj Kamal,
2008 8
Publs.: McGraw-Hill Education
 Port Interrupt to processor

λ When receiving-buffer is full

(available for next read)
λ When transmitting-buffer is empty
(available for next write)

Chapter-3 L06: "Embedded Systems - " , Raj Kamal,

2008 9
Publs.: McGraw-Hill Education
 Bidirectional Port Handshaking signals

λ STROBE
λ PORT READY
λ BUFFER-FULL
λ ACKNOWLEDGE
λ INTERRUPT REQUEST

Chapter-3 L06: "Embedded Systems - " , Raj Kamal,

2008 10
Publs.: McGraw-Hill Education
 Parallel IO port handshaking and Interfacing

1
CS
Strobe Request
Control Input
IORD
Signals 2
IOWR Port Ready
4 0
1
D0-D7 Buffer Full
Data Bus
output
2
Acknowledge

3
Interrupt
Request
(b)
Chapter-3 L06: "Embedded Systems - " , Raj Kamal,
2008 11
Publs.: McGraw-Hill Education
Parallel port at IBM PC using 25 pins connector

λ 8 I/O pins
λ 8 ground pins− (pins at 0 V)
λ Status pins and control pins −for handshaking
λ 5 input pins for status signals (four active high
S3 to S6, one active low S7) from external
device (for example, printing device)
λ 4 output pins for control signals (one active
high C2 and three active low C0, C1 and C3

Chapter-3 L06: "Embedded Systems - " , Raj Kamal,

2008 12
Publs.: McGraw-Hill Education
 Intel 8255 programmable peripheral interface
(PPI)
λ Four addresses for the PPI port, three for the
ports and one for the control word.
λ Three 8-bit ports− port A, B and C.
λ Port C programmable to function in bit set-
reset mode.
λ Each bit of port C can be set to 1 or reset to 0
by an appropriate control word.
λ Alternatively, the ports can be grouped as
Group A (Port A and Port C upper four bits) or
Group B (Port B and Port C lower four bits).

Chapter-3 L06: "Embedded Systems - " , Raj Kamal,

2008 13
Publs.: McGraw-Hill Education
 Mode 0 Groups A and B Programming
λ In mode 0 programming for a group
such that the group does not use
handshaking signals.
λ Group A mode 0, Port A input or
output and PC.7-PC.4 input or output
λ Group B mode 0, Port B input or
output and PC.0-PC.3 input or output

Chapter-3 L06: "Embedded Systems - " , Raj Kamal,

2008 14
Publs.: McGraw-Hill Education
 Mode 2 Group A Programming
λ Mode 2 programming is for port A as
bidirectional as input as well as output.
λ Handshaking signals at Port C−
STROBE, PORT READY, BUFFER
FULL, ACK and INTERRUPT when port
A functions as bi-directional I/O port.

Chapter-3 L06: "Embedded Systems - " , Raj Kamal,

2008 15
Publs.: McGraw-Hill Education
 Mode 1 programming for Groups A and B

λ Port as either input or as output with

handshake
λ Group A or B, port A or B use at an
instance only one of the two handshaking
signal pairs, either (STROBE, PORT
READY) or (BUFFER FULL, ACK) plus
one INTERRUPT signal at Port C pins.

Chapter-3 L06: "Embedded Systems - " , Raj Kamal,

2008 16
Publs.: McGraw-Hill Education
 Port Multiple features

λ A port may have provision for multiplexed

output to connect to multiple systems or
units.
λ Port may have provision for de-multiplexed
inputs from the multiple systems or units
λ Special functionalities
λ Alternative use− External address, data and
control buses

Chapter-3 L06: "Embedded Systems - " , Raj Kamal,

2008 17
Publs.: McGraw-Hill Education
 External Address and data buses

λ 8051-family two ports− abbreviate as

P0 and P2.
λ Alternate function (AD0-AD7 and A8-
A15) to bring out when needed, the
internal multiplexed buses
λ For the external program and
memories whenever the internal
memory is insufficient.
Chapter-3 L06: "Embedded Systems - " , Raj Kamal,
2008 18
Publs.: McGraw-Hill Education
 External Address and data buses

λ 68HC11 ports B and C alternative uses

of for the port pins − bring out the
internal address and data buses,
respectively

Chapter-3 L06: "Embedded Systems - " , Raj Kamal,

2008 19
Publs.: McGraw-Hill Education
 Special functionalities
•A device or port may have multi-byte data input
buffer(s) and data output buffer(s).
• Eight-byte buffer in 80196 microcontroller port
can generate three interrupts, one on receiving a
byte, one on receiving the fourth byte and one on
when the buffer full.
• Deadline increases for servicing these
interrupts up to eight times compared to the case
when then there is a single byte register instead
of 8-bit buffer with buffer-full interrupt
Chapter-3 L06: "Embedded Systems - " , Raj Kamal,
2008 20
Publs.: McGraw-Hill Education
 Special functionalities
•A port may be with a DDR (Data Direction
Register) (for example, in 68HC11
microcontroller).
• Advantage 1 − Each bit of the port is now
programmable. It can be set as input or
output.
• Advantage 2 − Same Port pin can be used
by changing direction of bits transfer when
sending signals as master or receive signals
as slave
Chapter-3 L06: "Embedded Systems - " , Raj Kamal,
2008 21
Publs.: McGraw-Hill Education
 Port driving and loading capabilities

λ Port LSTTL driving capability

λ Port loading capability are important
characteristics.

Chapter-3 L06: "Embedded Systems - " , Raj Kamal,

2008 22
Publs.: McGraw-Hill Education
 Parallel Port special functionalities
λ Quasi bi-directional port (for example,
in 80196)− port limited driving
capability for a period of one or a few
clock cycles and for one or a few
LSTTL gates only.
λ When the port connects to more than
one LSTTL then an appropriate pull-up
circuit will be required for each port
pin.
Chapter-3 L06: "Embedded Systems - " , Raj Kamal,
2008 23
Publs.: McGraw-Hill Education
 Parallel Port special functionalities

•Port may be an O.D. (open drain) port−

zero driving capability unless the drain
connects +ve supply voltage. If the given
port has the O.D. gates, appropriate pull-up
resistance or transistor is connected to each
port pin to provide the driving capability.
The drain or collector connects to the supply
voltage to provide the pull-up.
Chapter-3 L06: "Embedded Systems - " , Raj Kamal,
2008 24
Publs.: McGraw-Hill Education
 Multiple or alternate functionality for analog
inputs in the port pins
λ 80196 input port pins. Each pin of P2
has alternative use as a multi-channel
analog input facility for 8 analog
inputs.

Chapter-3 L06: "Embedded Systems - " , Raj Kamal,

2008 25
Publs.: McGraw-Hill Education
 Multiple or alternate functionality for PWM
output
λ A port pin can alternatively be PWM
output to enable DAC operation
λ PWM connects to integrator and
integrator provides analog output

Chapter-3 L06: "Embedded Systems - " , Raj Kamal,

2008 26
Publs.: McGraw-Hill Education
 Multiple or alternate functionality for Time
capture inputs
λ A port pin can alternatively be a time-
capture input to enable the internal timing
device to load the time (counts) at the
captured instance

Chapter-3 L06: "Embedded Systems - " , Raj Kamal,

2008 27
Publs.: McGraw-Hill Education
 Multiple or alternate functionality for Time
compare outputs
λ A port pin can alternatively be a time-
compare output to enable the internal timing
device to compared preload time (counts)
with the present counts to enable sending
output at the instance of their equality
λ For alarm like action from timing device

Chapter-3 L06: "Embedded Systems - " , Raj Kamal,

2008 28
Publs.: McGraw-Hill Education
 Multiple or alternate functionality in the port
pins
λ 8051 each pin of P3 in, has the
alternative multiple uses− during the
serial communication, timer/counter
signals, interrupt-signals, and RD and
WR control signals for external
memories.

Chapter-3 L06: "Embedded Systems - " , Raj Kamal,

2008 29
Publs.: McGraw-Hill Education
 Summary

Chapter-3 L06: "Embedded Systems - " , Raj Kamal,

2008 30
Publs.: McGraw-Hill Education
We learnt
• Parallel port in IBM PC
• Programmable Peripheral Interface −PPI
8255
• Multiple functionalities at port pins
• Data direction register− DDR
• Multiplexed/de-multiplexed outputs and
inputs at the ports
• Handshaking signals.
• Several alternate uses of port pins
Chapter-3 L06: "Embedded Systems - " , Raj Kamal,
2008 31
Publs.: McGraw-Hill Education
 End of Lesson 6 of Chapter 3

Chapter-3 L06: "Embedded Systems - " , Raj Kamal,

2008 32
Publs.: McGraw-Hill Education