Unit I - Boolean Algebra and Combinational Circuits Boolean Variables & Truth Tables
Unit I - Boolean Algebra and Combinational Circuits Boolean Variables & Truth Tables
com 2013
UNIT I – BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS
Boolean algebra differs in a major way from ordinary algebra in that Boolean
constants and variables are allowed to have only two possible values, 0 or 1.
Boolean 0 and 1 do not represent actual numbers but instead represent the state of a
voltage variable, or what is called its logic level.
In Boolean algebra, there are three basic logic operations: AND ,OR, and NOT.
These logic gates are digital circuits constructed from diodes, transistors, and resistors
connected in such a way that the circuit output is the result of a basic logic operation
(OR, AND, NOT) performed on the inputs.
Truth Table
A truth table is a means for describing how a logic circuit's output depends on the
logic levels present at the circuit's inputs.
In the following two-input logic circuit, the table lists all possible combinations of
logic levels present at inputs A and B along with the corresponding output level X.
When either input A OR B is 1, the output X is 1. Therefore the "?" in the box is an
OR gate.
OR Operation
The expression X = A + B reads as "X equals A OR B". The + sign stands for the OR
operation, not for ordinary addition.
The OR operation produces a result of 0 only when all the input variables are 0.
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AND Operation
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An example of three input AND gate and its truth table is as follows:
NOT Operation
The NOT operation is unlike the OR and AND operations in that it can be performed
on a single input variable. For example, if the variable A is subjected to the NOT
operation, the result x can be expressed as x = A' where the prime (') represents the
NOT operation. This expression is read as:
x equals NOT A
x equals the inverse of A
x equals the complement of A
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Each of these is in common usage and all indicate that the logic value of x = A' is o
pposite to the logic value of A. The truth table of the NOT operation is as follows:
NOR Operation
NOR and NAND gates are used extensively in digital circuitry. These gates combine
the basic operations AND, OR and NOT, which make it relatively easy to describe
then using Boolean algebra.
NOR gate symbol is the same as the OR gate symbol except that it has a small circle
on the output. This small circle represents the inversion operation. Therefore the
output expression of the two input NOR gate is:
X = (A + B)'
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An example of three inputs OR gate can be constructed by a NOR gate plus a NOT
gate:
NAND Operation
NAND gate symbol is the same as the AND gate symbol except that it has a small
circle on the output. This small circle represents the inversion operation. Therefore
the output expression of the two input NAND gate is:
X = (AB)'
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Describing Logic Circuits Algebraically
Any logic circuit, no matter how complex, may be completely described using the
Boolean operations, because the OR gate, AND gate, and NOT circuit are the basic
building blocks of digital systems.
If an expression contains both AND and OR operations, the AND operations are
performed first (X=AB+C: AB is performed first), unless there are parentheses in the
expression, in which case the operation inside the parentheses is to be performed first
(X= (A+B) +C: A+B is performed first).
Once the Boolean expression for a circuit output has been obtained, the output logic
level can be determined for any set of input levels.
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X = A'BC (A+D)'
= 0'*1*1* (0+1)'
= 1 *1*1* (1)'
= 1 *1*1* 0
=0
X = [D+ ((A+B)C)'] * E
= [1 + ((0+0)1 )'] * 1
= [1 + (0*1)'] * 1
= [1+ 0'] *1
= [1+ 1 ] * 1
=1
In general, the following rules must always be followed when evaluating a Boolean
expression:
The output logic level for given input levels can also be determined directly from the
circuit diagram without using the Boolean expression.
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Each OR-gate input is an AND product term, which means that an AND gate with
appropriate inputs can be used to generate each of these terms. Note the use of
INVERTERs to produce the A' and C' terms required in the expression.
Boolean Theorems
Investigating the various Boolean theorems (rules) can help us to simplify logic
expressions and logic circuits.
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Multivariable Theorems
Proof of (14)
x + xy = x (1+y)
= x * 1 [using theorem (6)]
= x [using theorem (2)]
DeMorgan's Theorem
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DeMorgan's theorems are extremely useful in simplifying expressions in which a
product or sum of variables is inverted. The two theorems are:
Theorem (16) says that when the OR sum of two variables is inverted,
this is the same as inverting each variable individually and then
ANDing these inverted variables.
Theorem (17) says that when the AND product of two variables is inverted,
this is the same as inverting each variable individually and then ORing them.
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Example
X = [(A'+C) * (B+D')]'
= (A'+C)' + (B+D')' [by theorem (17)]
= (A''*C') + (B'+D'') [by theorem (16)]
= AC' + B'D
It is possible to implement any logic expression using only NAND gates and no other
type of gate. This is because NAND gates, in the proper combination, can be used to
perform each of the Boolean operations OR, AND, and INVERT.
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In a similar manner, it can be shown that NOR gates can be arranged to implement
any of the Boolean operations.
The left side of the illustration shows the standard symbol for each logic gate, and the
right side shows the alternate symbol. The alternate symbol for each gate is obtained
from the standard symbol by doing the following:
1. Invert each input and output of the standard symbol. This is done by adding
bubbles (small circles) on input and output lines that do not have bubbles, and
by removing bubbles that are already there.
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2. Change the operation symbol from AND to OR, or from OR to AND. (In
the special case of the INVERTER, the operation symbol is not changed.)
1. The equivalences are valid for gates with any number of inputs.
2. None of the standard symbols have bubbles on their inputs, and all the
alternate symbols do.
3. The standard and alternate symbols for each gate represent the same
physical circuit: there is no difference in the circuits represented by the two
symbols.
4. NAND and NOR gates are inverting gates, and so both the standard and
alternate symbols for each will have a bubble on either the input or the output.
AND and OR gates are noninverting gates, and so the alternate symbols for
each will have bubbles on both inputs and output.
When an input or output line on a logic circuit symbol has no bubble on it, that line is
said to be active-HIGH. When an input or output line does have a bubble on it, that
line is said to be active-LOW. The presence or absence of a bubble, then, determines
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the active-HIGH/active-LOW status of a circuit's inputs and output, and is used to
interpret the circuit operation.
Boolean Function
Operator Precedence
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Boolean function can be represented by truth table as well.If the function has n
variables, its truth table will have 2n rows
e.g. f = x • y + x • z’
f has 3 variables so 23 combinations
f is 1 when the expression is evaluated to 1 otherwise it is 0.
Minterm
In a Boolean function, a binary variable (x) may appear either in its normal form (x)
or in its complement form (x’).Consider 2 binary variables x and y and an AND
operation, there are 4 and only 4 possible combinations: x’•y’, x’•y, x•y’ & x•y
Each of the 4 product terms is called a MINTERM or STANDARD PRODUCT
By definition, a Minterm is a product which consists of all the variables in the normal
form or the complement form but NOT BOTH.
e.g. for a function with 2 variables x and y:
x•y’ is a minterm but x’ is NOT a minterm
e.g. for a function with 3 variables x, y andz:
x’yz’ is a minterm but xy’ is NOT a minterm
Maxterm
Consider 2 binary variables x and y and an OR operation, there are 4 and only 4
possible combinations: x’+y’, x’+y, x+y’, x+y.Each of the 4 sum terms is called a
MAXTERM or STANDARD SUM.By definition, a Maxterm is a sum in which each
variable appears once and only once either in its normal form or its complement
form but NOT BOTH.
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Literal
If product terms in a Boolean function are not minterms, they can be converted to
minterms
e.g. f(a,b,c) = a’ + bc’ + ab’c
Function f has 3 variables, therefore, each minterm must have 3 literals
Neither a’ nor bc’ are minterms.They can be converted to minterm.ab’c is a
minterm
Conversion to Minterms
QUINE-McCLUSKEY MINIMIZATION
Minimization Technique
The expression is represented in the canonical SOP form if not already in that form.
The function is converted into numeric notation.
The numbers are converted into binary form.
The minterms are arranged in a column divided into groups.
Begin with the minimization procedure.
Each minterm of one group is compared with each minterm in the group immediately
below.
Each time a number is found in one group which is the same as a number in the group
below except for one digit, the numbers pair is ticked and a new composite is created.
This composite number has the same number of digits as the numbers in the pair
except the digit different which is replaced by an "x".
The above procedure is repeated on the second column to generate a third column.
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The next step is to identify the essential prime implicants, which can be done using a
prime implicant chart.
Where a prime implicant covers a minterm, the intersection of the corresponding row
and column is marked with a cross.
Those columns with only one cross identify the essential prime implicants. -> These
prime implicants must be in the final answer.
The single crosses on a column are circled and all the crosses on the same row are
also circled, indicating that these crosses are covered by the prime implicants
selected.
Once one cross on a column is circled, all the crosses on that column can be circled
since the minterm is now covered.
If any non-essential prime implicant has all its crosses circled, the prime implicant is
redundant and need not be considered further.
Next, a selection must be made from the remaining nonessential prime implicants, by
considering how the non-circled crosses can be covered best.
One generally would take those prime implicants which cover the greatest number of
crosses on their row.
If all the crosses in one row also occur on another row which includes further crosses,
then the latter is said to dominate the former and can be selected.
The dominated prime implicant can then be deleted.
Example
Firstly these minterms are represented in the binary form as shown in the table below.
The above binary representations are grouped into a number of sections in terms of
the number of 1's as shown in the table below.
Minterms U V W X
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
14 1 1 1 0
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15 1 1 1 1
No of 1's Minterms U V W X
1 1 0 0 0 1
1 2 0 0 1 0
1 8 1 0 0 0
2 3 0 0 1 1
2 9 1 0 0 1
2 10 1 0 1 0
3 7 0 1 1 1
3 11 1 0 1 1
3 14 1 1 1 0
4 15 1 1 1 1
Any two numbers in these groups which differ from each other by only one variable
can be chosen and combined, to get 2-cell combination, as shown in the table below.
2-Cell combinations
Combinations U V W X
(1,3) 0 0 - 1
(1,9) - 0 0 1
(2,3) 0 0 1 -
(2,10) - 0 1 0
(8,9) 1 0 0 -
(8,10) 1 0 - 0
(3,7) 0 - 1 1
(3,11) - 0 1 1
(9,11) 1 0 - 1
(10,11) 1 0 1 -
(10,14) 1 - 1 0
(7,15) - 1 1 1
(11,15) 1 - 1 1
(14,15) 1 1 1 -
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From the 2-cell combinations, one variable and dash in the same position can be
combined to form 4-cell combinations as shown in the figure below.
Combinations U V W X
(1,3,9,11) - 0 - 1
(2,3,10,11) - 0 1 -
(8,9,10,11) 1 0 - -
(3,7,11,15) - - 1 1
(10,11,14,15) 1 - 1 -
The cells (1,3) and (9,11) form the same 4-cell combination as the cells (1,9) and
(3,11). The order in which the cells are placed in a combination does not have any
effect. Thus the (1,3,9,11) combination could be written as (1,9,3,11).
From above 4-cell combination table, the prime implicants table can be plotted as
shown in table below.
Prime
1 2 3 7 8 9 10 11 14 15
Implicants
(1,3,9,11) X - X - - X - X - -
(2,3,10,11) - X X - - - X X - -
(8,9,10,11) - - - - X X X X - -
(3,7,11,15) - - - - - - X X X X
- X X - X X - - - X -
The columns having only one cross mark correspond to essential prime implicants. A
yellow cross is used against every essential prime implicant. The prime implicants
sum gives the function in its minimal SOP form.
Logic
Combinational logic blocks have the outputs depending on the combinations of the
current inputs. Sequential logic blocks have the outputs depending on the current
inputs as well as any previous inputs.
Binary Adder
Binary Adder is for binary number addition
Logic Circuit to be discussed:
Half Adder
Full Adder
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Ripple Adder
Carry Look Ahead Adder
Half Adder
Binary Addition
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To complete a full addition, the adder needs to take in 3 inputs: a, b and the carry
from the previous bit.
Full Adder
To carry the addition, an adder with 3 inputs is required. A Full Adder takes in 3
inputs (a, b and ci) and produces 2 outputs (s, co) a & b are the 2 bits to be added, ci
is the carry input (carry over from the previous bit) and co is the carry output (to the
next bit)
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s = a b ci
co = ab + bci + aci
Full Adder
The below implementation shows implementing the full adder with AND-OR gates,
instead of using XOR gates. The basis of the circuit below is from the above Kmap.
Circuit-SUM
Circuit-CARRY
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Carry-Look-Ahead Adder
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The delay generated by an N-bit adder is proportional to the length N of the two
numbers X and Y that are added because the carry signals have to propagate from one
full-adder to the next. For large values of N, the delay becomes unacceptably large so
that a special solution needs to be adopted to accelerate the calculation of the carry
bits. This solution involves a "look-ahead carry generator" which is a block that
simultaneously calculates all the carry bits involved. Once these bits are available to
the rest of the circuit, each individual three-bit addition (Xi+Yi+carry-ini) is
implemented by a simple 3-input XOR gate. The design of the look-ahead carry
generator involves two Boolean functions named Generate and Propagate. For each
input bits pair these functions are defined as:
Gi = Xi . Yi
Pi = Xi + Yi
The carry bit c-out(i) generated when adding two bits Xi and Yi is '1' if the
corresponding function Gi is '1' or if the c-out(i-1)='1' and the function Pi = '1'
simultaneously. In the first case, the carry bit is activated by the local conditions (the
values of Xi and Yi). In the second, the carry bit is received from the less significant
elementary addition and is propagated further to the more significant elementary
addition. Therefore, the carry_out bit corresponding to a pair of bits Xi and Yi is
calculated according to the equation:
carry_out(i) = Gi + Pi.carry_in(i-1)
carry_out0 = G0 + P0 . carry_in0
The set of equations above are implemented by the circuit below and a complete
adder with a look-ahead carry generator is next. The input signals need to propagate
through a maximum of 4 logic gate in such an adder as opposed to 8 and 12 logic
gates in its counterparts illustrated earlier.
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With Pi and Gi, we obtain the sum & carry for the full adder:
Ci+1= Gi + PiCi
C1 = G0 + P0C0
C2 = G1 + P1C1
= G1 + P1(G0 + P0C0)
= G1 + P1G0 + P1P0C0
C3 = G2 + P2C2
= G2 + P2(G1 + P1G0 + P1P0C0)
= G2 + P2G1 + P2P1G0 + P2P1P0C0
Carry no longer depend on its previous stage
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Sums can be calculated from the following equations, where carryout is taken from
the carry calculated in the above circuit.
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sum_out0 = X 0 Y0 carry_out0
sum_out1 = X 1 Y1 carry_out1
sum_out2 = X 2 Y2 carry_out2
sum_out3 = X 3 Y3 carry_out3
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MSI Adder
Adders are available in Medium Scale Integration (MSI) devices
Both TTL and CMOS are available, e.g.
74183: TTL 1-bit Full Adder
7482: TTL 4-bit Carry-Look-Ahead Adder
4008: CMOS 4-bit Carry-Look-Ahead Adder
74182: 4-bit Look-Ahead Carry Generator
4-bit Addition
8-bit Addition
Subtractor
Subtractor circuits take two binary numbers as input and subtract one binary number
input from the other binary number input. Similar to adders, it gives out two outputs,
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difference and borrow (carry-in the case of Adder). There are two types of
subtractors.
Half Subtractor
Full Subtractor
Half Subtractor
Symbol
Truth Table
X Y D B
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
From the above table we can draw the Kmap as shown below for "difference" and "
borrow". The boolean expression for the difference and Borrow can be written.
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From the equation we can draw the half-subtractor as shown in the figure below.
Full Subtractor
Symbol
Truth Table
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X Y Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
From above table we can draw the Kmap as shown below for "difference" and
"borrow".
= (X Y)'Bin + (X Y)Bin'
=X Y Bin
From the equation we can draw the full-subtractor as shown in figure below.
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Below is the block level representation of a 4-bit parallel binary subtractor, which
subtracts 4-bit Y3Y2Y1Y0 from 4-bit X3X2X1X0. It has 4-bit difference output
D3D2D1D0 with borrow output Bout.
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A serial subtractor can be obtained by converting the serial adder using the 2's
complement system. The subtrahend is stored in the Y register and must be 2's
complemented before it is added to the minuend stored in the X register.
The circuit for a 4-bit serial subtractor using full-adder is shown in the figure below.
Comparator
Comparator compares binary numbers.
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Magnitude Comparator
Comparator compares binary numbers
4-bit Magnitude Comparator:
Inputs: A3A2A1A0 & B3B2B1B0
Outputs: Y A>B, Y A<B, Y A=B
For each bit, let:
Si = AiBi + Ai’Bi’ = (AiBi’ + Ai’Bi)’
Si is true when Ai = Bi
For A = B, we must have:
A3=B3 and A2=B2 and A1=B1 and A0=B0
Hence, Y A=B = S3•S2•S1•S0 136
Logic For A > B
For A > B, there are 4 cases:
1. A3B3 is 10 and A2A1A0 & B2B1B0 can be anything:
A=1xxx, B=0xxx
2. A3=B3 and A2B2 is 10 and A1A0 & B1B0 can be
anything: A=11xx, B=10xx or A=01xx, B=00xx
3. A3=B3 and A2=B2 and A1B1=10 and A0B0 is xx: e.g.
A=011x, B=010x
4. A3=B3 and A2=B2 and A1=B1 and A0B0 is 10: e.g.
A=1011, B=1010
Y A>B=A3B3’+S3A2B2’+S3S2A1B1’+S3S2S1A0B0’
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Decoder
A binary decoder has n inputs and 2n outputs. Only one output is active at any one
time, corresponding to the input value. Figure below shows a representation of Binary
n-to-2n decoder
3-to-8 Decoder
Function Table
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Suitable when a circuit has many outputs, and each output function is expressed with
few minterms.
S(x, y, z) = (1,2,4,7)
C(x, y, z) = (3,5,6,7)
Truth Table
X Y Z C S
0 0 0 0 0
0 0 1 0 1
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0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
Fr 1 0 1 1 0
o 1 1 0 1 0
m
th 1 1 1 1 1
e truth table we know the values for which the sum (s) is active and also the carry (c)
is active. Thus we have the equation as shown above and a circuit can be drawn as
shown below from the equation derived.
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MSI Decoders
1. 2-to-4 Decoder
2. 3-to-8 Decoder
3. 4-to-16 Decoder
4. BCD-to-Decimal Decoder
5. BCD-to-Seven-Segment Decoder
e.g. Low Power Schottky TTL:
74LS138 3-to-8 Decoder where G1, G2A and G2B are enable pins
Logic Symbol
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4-to-16 Decoder
Binary Encoders
The simplest encoder is a 2n-to-n binary encoder, where it has only one of 2n inputs =
1 and the output is the n-bit binary number corresponding to the active input. It can be
built from OR gates
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Octal-to-Binary Encoder
Octal-to-Binary take 8 inputs and provides 3 outputs, thus doing the opposite of what
the 3-to-8 decoder does. At any one time, only one input line has a value of 1. The
figure below shows the truth table of an Octal-to-binary encoder.
Truth Table
I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
For an 8-to-3 binary encoder with inputs I0-I7 the logic expressions of the outputs
Y0-Y2 are:
Y0 = I1 + I3 + I5 + I7
Y1= I2 + I3 + I6 + I7
Y2 = I4 + I5 + I6 +I7
Based on the above equations, we can draw the circuit as shown below
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Priority Encoder
If more then two inputs are active simultaneously, the output is unpredictable or
rather it is not what we expect it to be.This ambiguity is resolved if priority is
established so that only one input is encoded, no matter how many inputs are active at
a given point of time. The priority encoder includes a priority function. The operation
of the priority encoder is such that if two or more inputs are active at the same time,
the input having the highest priority will take precedence.
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Cascade two 74148 8-to-3 priority encoders. The Input 15 has highest priority
Multiplexer
A multiplexer (MUX) is a digital switch which connects data from one of n sources to
the output. A number of select inputs determine which data source is connected to the
output. The block diagram of MUX with n data sources of b bits wide and s bits wide
select line is shown in below figure.
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MUX acts like a digitally controlled multi-position switch where the binary code
applied to the select inputs controls the input source that will be switched on to the
output as shown in the figure below. At any given point of time only one input gets
selected and is connected to output, based on the select input signal.
2x1 MUX
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To derive the gate level implementation of 2:1 mux we need to have truth table as s
hown in figure. And once we have the truth table, we can draw the K-map as
shown in figure for all the cases when Y is equal to '1'.
Combining the two 1' as shown in figure, we can drive the output y as shown below
Y = A.S’ + B.S
Truth Table
B A S Y
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 0 1
1 1 1 1
Kmap
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Circuit
MSI MUX
74150: 16-to-1
74153: Dual 4-to-1
74157: Quad 2-to-1
74151: 8-to-1
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16-to-1 MUX
Larger Multiplexers
Larger multiplexers can be constructed from smaller ones. An 8-to-1 multiplexer can
be constructed from smaller multiplexers as shown below.
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Determine multiplexer input line i values by comparing the remaining input variable
and the function F for the corresponding selection lines value i.
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Implement the function F(X,Y,Z) = S(1,3,5,6) using an 8-to-1 mux. Connect the input
variables X, Y, Z to mux select lines. Mux data input lines 1, 3, 5, 6 that correspond
to the function minterms are connected to 1. The remaining mux data input lines 0, 2,
4, 7 are connected to 0.
Implement the function F(X,Y,Z) = S(0,1,3,6) using a single 4-to-1 mux and an
inverter. We choose the two most significant inputs X, Y as mux select lines.
Truth Table
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when XY=00 the function F is 1 (for both Z=0, Z=1) thus mux input0 = 1
when XY=01 the function F is Z thus mux input1 = Z
when XY=10 the function F is 0 (for both Z=0, Z=1) thus mux input2 = 0
when XY=11 the function F is Z' thus mux input3 = Z'
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De-multiplexers
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They are digital switches which connect data from one input source to one of n
outputs.Usually implemented by using n-to-2n binary decoders where the decoder
enable line is used for data input of the de-multiplexer.The figure below shows a de-
multiplexer block diagram which has got s-bits-wide select input, one b-bits-wide
data input and n b-bits-wide outputs.
1-to-4 De-multiplexer
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Truth Table
S1 S0 F0 F1 F2 F3
0 0 D 0 0 0
0 1 0 D 0 0
1 0 0 0 D 0
1 1 0 0 0 D
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