Microsystem Technologies

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TECHNICAL PAPER

A design approach of higher oscillation VCO made of CS amplifier

with varying active load
Suraj Kumar Saw1 • Sandeep Kumar Yadav1 • Madhusudan Maiti1 • Abir Jyoti Mondal1 • Alak Majumder1

Received: 5 May 2019 / Accepted: 22 May 2019

 Springer-Verlag GmbH Germany, part of Springer Nature 2019

Abstract
This article proposes a design approach of common source (CS) amplifier based Voltage Controlled Oscillator (VCO) to
derive higher oscillation frequency. The working feature is such that, the active load of CS amplifier is varied to modulate
the flow of current based on a bias circuit steered by an external controlled voltage (Vctrl), which controls the delay of each
stage and thereby regulates the oscillation frequency. The circuit is designed and analyzed on Cadence Virtuoso platform at
a supply voltage of 1.2 V for 90 nm CMOS to read a device footprint of 0.105 mm2, which offers a power burn and
frequency of 2.092 mW and 9.21 GHz respectively with a phase noise and output noise of - 137.9 dBc/Hz and
- 168.40 dB at 1 MHz offset frequency. To justify the reliability of the circuit we have conducted worst case analysis by
considering effect of power delivery network (PDN) and corner variation along with 500 runs of Monte Carlo. The design
is also introduced under 28 nm UMC to validate its scalability with technology trends.

1 Introduction frequency tuning (Alioto and Palumbo 2001; Tiebout

2006). However, it fails to derive very high frequency at
The control system of PLL generates an output oscillation the output. The general mathematical equation of fre-
generally used as clock and the prime element of that quency of oscillation and tuning range (T) for an N-stage
system helping to oscillate is the voltage controlled oscil- VCO may be written as;
lator (VCO) (Razavi 1997). Even in modern CPUs, as the 1
on chip crystal clock (BCLK) ranges between 100 to fOSC ¼ ; ð1Þ
2Ntdelay
133 MHz, PLL takes the responsibility to convert BCLK to
a higher frequency clock (GHz) needed in high end pro- fHigh  fLow
T¼ ; ð2Þ
cessors (Intel CoreTM 2010). The advent in technology is fHigh
continuously raising this operating frequency of processors where fOSC is the oscillation frequency of VCO, ‘N’ is
and hence, VCO design to pump higher oscillation has number of stages and tdelay is the delay of each stage.
become the need of hour. The two notable design
approaches are LC tank VCO (LC-VCO) and ring VCO. 1.1 Related prior arts
The LC-VCO is hardly considered due to its complexity in
terms of fabrication and large area overhead. Also, the non- There have been many attempts made to output higher
linearity of LC-VCO in terms of tuning range and fre- oscillation frequency in recent times. In Ko et al. (2015), a
quency gain (Kvco) is the major concern, which degrades new technique of VCO with voltage-to-current converter is
the overall performance of PLL. But, ring VCO is preferred explored to lower down the phase noise by giving away
for its easy integration, lesser device footprint and wide penalty in terms of power dissipation and chip area over-
head. To overcome such demerits a feedback transformer
based VCO is designed to note low power consumptions
& Alak Majumder
[email protected] (Liu et al. 2012a). The article (Jerng and Sodini 2005)
conveys another technique to decrease the phase noise by
1
Integrated Circuit and System (I-CAS) Lab, Department of optimizing the cell ratio, where a lower flicker noise is
Electronics and Communication Engineering (ECE), obtained with less tuning range. The biasing circuit of VCO
National Institute of Technology, Yupia,
Arunachal Pradesh 791112, India may be made of PMOS transistor to lower down thermal

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 Microsystem Technologies

noise and flicker noise by curbing down the bias current

(Yin and Luong 2013). VCO behavior depends on phase
noise and power supply noise, which is attempted to
manage by using a bias current source in Mrakami et al.
(2011) and Hegazi et al. (2001). To increase the frequency
tuning range a new front-end-of-the line technique is
implemented by using current mode logic (CML) and
observed a full swing at the output (Kim et al. 2009), which
however burns large power. To compensate the energy
loss, the current-reuse cross-connected pair is introduced as
a negative conductance generator (Zhu et al. 2014). How-
ever, the performance of conventional CML circuits is
found to be affected by current and power supply noise. In
Mondal et al. (2017), CML based VCO is found to have
generated high frequency oscillation with wide tuning
range. Considering the aforementioned issues, we have
come up with an approach of ring VCO as a cascaded form
of Current Source (CS) amplifiers, where the active load is
varied through a biasing network to modulate output
oscillation and we have noted a large frequency and wide
tuning sensitivity along with good KVCO and lesser phase
noise.
The rest part of this paper is organized as follows:
Section 2 describes the workflow of the design followed by
the working of proposed VCO in Section 3. Section 4
estimates the frequency of the new design in terms of a
mathematical model. The performance metrics of the Fig. 1 Workflow of proposed CS amplifier based VCO
design along with worst case simulation and corner varia-
tion are discussed in Section 5. Section 6 compares our (c) The reliability of the design is scrutinized under
design with previous works and validation of design in worst case simulation and corner variation with 500
commercial process node in done in Section 7. Finally, runs of Monte-Carlo.
Section 8 concludes the paper with possible future scopes (d) To imitate the effect of a power delivery network
on this work. (PDN), we have tested our VCO by introducing a
noise of ± 10% of VDD (with 10 MHz oscillation)
and noted pretty minor deviation in all the perfor-
2 Workflow and highlights of the paper mance metrics.
(e) The circuit functionality is also validated for lower
The preeminent aim of this work is to design a current process nodes like 28 nm UMC.
mode VCO to output high frequency oscillation, which
indeed is a prominent need of the modern era CPU ICs for
speed up the computation. The steps followed to design the
3 VCO design using CS amplifier
same is displayed in Fig. 1.
The highlights of the new VCO presented in this article
The proposed 5th stage VCO (refer Fig. 2a) comprises of
may be summarized as below:
cascaded CS amplifier based ring structure to provide full
(a) A new approach of CS amplifier based VCO is swing oscillation with considerably higher frequency and
tendered with active load being modulated by a bias better tuning range. Here, the PMOS transistors namely
circuit to achieve higher oscillation frequency (fOSC) PM1–PM5 serve as active load, which is varied by VBIAS
and good tuning range. generated from the Bias network made of NMOS transis-
(b) A closed form mathematical model is derived to tors (NM1–NM3). The rise in control signal (VCtrl) at the
estimate frequency of oscillation (fOSC). Gate terminal of NM3 makes it to switch from cut-off
region to saturation, thereby lowering the drain voltage
(VBIAS). This in turn modulates the resistance of active

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which a closed form model of computing frequency is

attempted after taking into account the non-linear inherent
behavior of a VCO. Figure 3a represents an N-stage VCO
with Vb being the voltage to steer the active load of each
CS amplifier and V1, V2, V3 … VN are the node voltage at
the output of each stage. The phase behavior among the
output nodes is presented in terms of ideal waveform in
Fig. 3b, where the delay (d) between any two subsequent
stages may be written as:
   
T T T N 1
d¼  ¼ : ð3Þ
2 2N 2 N
Also, the relation among the node voltages may be
mathematically expressed by;
V1 ¼ V2 ð1 þ dÞ ¼ V3 ð1 þ 2dÞ ¼ . . . ¼ VN ð1 þ ðN  1ÞdÞ:
ð4Þ
The capacitor model of a CS amplifier stage is shown in
Fig. 2 Proposed circuit (a) 5th stage VCO schematic, b layout for Fig. 4. We have noted the following parasitic capacitors
90 nm CMOS, c transient Plot such as drain to gate (Cgdp ), drain to bulk (Cdbp ), drain to
source (Cdsp ) for PMOS and drain to gate (Cgdp ), drain to
loads from high to low thereby changing the output fre- bulk (Cdbn ), drain to source (Cdsn ) for NMOS. As the load
quency. Figure 2b displays the physical layout of the pro- capacitor is in parallel to all the parasitic capacitors, the
posed VCO in 90 nm CMOS to read an area of 0.105 mm2, effective total capacitance is written as:
which is made of the transistor dimensions stated in C ¼ CL þ Cgdn þ Cgdp þ Cdbn þ Cdbp : ð5Þ
Table 1. The functionality is verified from the transient
shown in Fig. 2c, where we have varied control signal to
notice the change in frequency. When simulated with both
supply voltage and control voltage being equal to 1.2 V,
the circuit is found to offer a frequency of 10.606 GHz and
9.21 GHz respectively in schematic and post-layout.

4 Mathematical model to estimate

frequency

Literature has witnessed a few works where simple equa-

tions were derived based on small signal analysis to esti-
mate amplitude and frequency of ring VCO (Alioto and
Palumbo 2001; Jagtap and Pable 2014; Suman et al. 2016;
Docking and Sachdev 2003). As these works deal with
linear model by considering parasitic and other secondary
effects, the accuracy of the equations is in question, for

Table 1 Transistor sizing of the proposed VCO

Transistors Width (nm) Length (nm)

NM1–NM3 120 100

PM1–PM5 1600 100
NM4–NM8 2600 100

Fig. 3 a N-stage model of proposed VCO, b ideal transient

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     2
Kn N 1
C0 þ Cn cos xt þ p  Vton
2 N
d
 C ðC0 þ Cn cos xtÞ
dt
Kp  2
þ Vdd  Vb  Vtop ¼ 0: ð12Þ
2
  p   p
Putting, cos N1
N p ¼ cos N and sin N1 N p ¼ sin N
the Eq. (12) may be written as;
Kn   p  p  2
C0 þ Cn cos xt cos  sin xt sin  Vton
2 N N
Kp  2
 CxCn sin xt þ Vdd  Vb  Vtop ¼ 0:
Fig. 4 Parasitic capacitive model of one stage CS amplifier 2
ð13Þ

4.1 Analysis for saturation region Now, applying boundary conditions i.e. xt ¼ 0, xt ¼ p
and xt ¼  p2 in (13), the following four mathematical
   
Let Kn ¼ 12 ln Cox WL and Kp ¼ 12 lp Cox WL .When both representation may be devised.
PMOS & NMOS are in saturation, by applying KCL at Kn    p  2 K 
p 2
C0 þ Cn cos  Vton þ Vdd  Vb  Vtop
each node ‘Vn’ of Fig. 3a, we get, 2 N 2
¼ 0;
For Node 1 :
Kn dV1 Kp  2 ð14Þ
ðVn  Vton Þ2 C þ Vdd  Vb  Vtop ¼ 0;
2 dt 2 Kn    p  2 K 
p 2
C0  Cn cos  Vton þ Vdd  Vb  Vtop
ð6Þ 2 N 2
¼ 0;
For Node 2 :
ð15Þ
Kn dV2 Kp  2
ðV1  Vton Þ2 C þ Vdd  Vb  Vtop ¼ 0: Kn    p  2
2 dt 2 C0 þ Cn  sin  Vton þCxCn ;
ð7Þ 2 N ð16Þ
Kp  2
Similarly, for Node n the equation may be written as; þ Vdd  Vb  Vtop ¼ 0
2
Kn dVn Kp  2 Kn    p  2
ðVn1  Vton Þ2 C þ Vdd  Vb  Vtop ¼ 0: C0 þ Cn sin  Vton CxCn
2 dt 2 2 N
ð8Þ Kp  2
þ Vdd  Vb  Vtop
2
Let, V1 ¼ V2 ¼ . . .Vn ¼ C0 þ Cn sinðxt þ hÞ: ¼ 0: ð17Þ
So, output voltage may be written as;
By subtracting Eq. (14) from Eq. (15) we
Vout ¼ ðC0 þ C n cos xtÞ: ð9Þ get;2kn ðC0  Vton ÞCn cos Np ¼ 0 and this results to:Cn ¼ 0
where C0 = DC level and C n = Amplitude of the signal. or 2kn ðC0  Vton Þ cos Np ¼ 0
From the phase relation presented in Fig. 3b and refer- 1
ring to the Eq. (3), we may also represent V1 and V2 as C0 ¼ Vton þ : ð18Þ
2kn cos Np
below:
    By rearranging Eq. (15) we get;
N1 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
ffi
V1 ¼ C0 þ Cn cos xt þ p ð10Þ  2
N Kp Vdd  Vb  Vtop Kn ðC0  Vton Þ2
Cn ¼ : ð19Þ
V2 ¼ C0 þ Cn cos xt ð11Þ Kn cos2 Np

Putting the value of V1 and V2 in Eq. (7) we get; By rearranging Eq. (16), we get the frequency of
oscillation for saturation region;
Kp  2  2
2 Vdd  Vb  Vtop  K2n C0  Cn sin Np  Vton
f ¼ :
2p:C:Cn
ð20Þ

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4.2 Analysis for linear region 4.3 Analysis for cut-off region

Considering both PMOS and NMOS are in linear region In this case, PMOS and NMOS are considered to be in cut-
and following the similar mathematical approach stated in off region and the node equations after applying boundary
Sect. 4.1, the node equations after applying boundary conditions are:
conditions may be written as follows: Kn h  p i
h   i ðC0 þ Cn Þ C0 þ Cn cos  Vton
Kn p 2 N
ðC0 þ Cn Þ C0 þ Cn 2 cos þ 1  Vton Kp  2
2 N þ Vdd  Vb  Vtop ; ð28Þ
Kp  2 2
þ Vdd  Vb  Vtop ; ð21Þ h 
2 Kn p i
h   i ðC0  Cn Þ C0  Cn cos  Vton
Kn p 2 N
ðC0  Cn Þ C0  Cn 2 cos  1  Vton Kp  2
2 N þ Vdd  Vb  Vtop ; ð29Þ
Kp  2 2
þ
2
Vdd  Vb  Vtop ; ð22Þ Kn h  p  i
C0  Cn sin  Vton C0 þ Cx Cn
Kn h  p  i 2 N
2C0  2Cn sin  Vton C0  ðC0 Þ2 þ Cx Cn Kp  2
2 N þ Vdd  Vb  Vtop ; ð30Þ
Kp  2 2
þ
2
Vdd  Vb  Vtop : Kn h  p  i
C0 þ Cn sin  Vton C0  Cx Cn
ð23Þ 2 N
h     i Kp  2
Kn p þ Vdd  Vb  Vtop : ð31Þ
2C0 þ 2Cn sin  Vton C0  ðC0 Þ2  Cx Cn 2
2 N
Kp  2 Let’s subtract Eq. (28) from Eq. (29) to
þ Vdd  Vb  Vtop : get;Cn Kn ðC0  Vton Þ ¼ 0, which produces
2
ð24Þ C0 ¼ Vton ð32Þ
Now, the Eq. (21) is subtracted from Eq. (22) to obtain
 

the following:Kn Cn C0 2 cos Np  Vton ¼ 0, which results

to
Vton
C0 ¼   ð25Þ
2 cos Np  1

By rearranging Eq. (22) we get;

  qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
 2      2ffi
 Kn Vton  2Kn C0 cos Np  Kn Vton  2Kn C0 cos Np 4  Kn 2 cos Np  1  Kn C02  C0 Kn Vton þ Kp Vdd  Vb  Vtop
Cn ¼   :
2Kn 2 cos Np  1
ð26Þ

The oscillation frequency may be obtained from

Eq. (23) and is written as;

 2 h    i
Kp
 2 Vdd  Vb  Vtop  K2n 2C0  2Cn sin Np  Vton C0  ðC0 Þ2
f ¼ : ð27Þ
2p C Cn

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Table 2 Analytical and

Parameters Under saturation region Under linear region Under cut-off region
simulation result
Analytical Simulation Analytical Simulation Analytical Simulation

DC level (C0) 0.526 V 0.6 V 0.3511 V 0.5 V 0.217 V 0.250 V

Amplitude level (Cn) 1.1034 V 1.2 V 0.9281 V 1V 0.8667 V 0.9 V
Frequency (f) 12.9 GHz 10.606 GHz 10.757 GHz 8.879 GHz 5.1738 GHz 5.14 GHz

From Eq. (29), Cn may be obtained as;

  qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2      2
 Kn Vton  Kn C0  Kn C0 cos Np  Kn Vton  Kn C0  Kn C0 cos Np 4  Kn cos Np  Kn C02  C0 Kn Vton þ Kp Vdd  Vb  Vtop
Cn ¼   :
2Kn cos Np
ð33Þ

Rearrangement of Eq. (30) offers the expression of 5 Performance metrics

oscillation frequency,
Kp  2    
The proposed design of CS amplifier based VCO is
 2 Vdd  Vb  Vtop  K2n C0  Cn sin Np  Vton C0
f ¼ : designed on Cadence virtuoso platform for 90 nm CMOS
2p C Cn
technology with a supply voltage of 1.2 V. In the following
ð34Þ
sub-sections, we have discussed the various performance
Equations (20), (27) and (34) are considered to compute metrics of this new VCO:
the oscillation frequency of the proposed VCO at 3 dif-
ferent operating regimes and noted them in Table 2 along 5.1 Computation of average power
with the simulated values. The device parameters used to and frequency
analyze the frequency is presented in Table 3. It is
observed from Table 2 that the analytical frequency gets To check the performance and reliability of the circuit, a
deviated by 17.78%, 17.46% and 0.65% during simulation 500 runs of Monte Carlo is carried out at different process
in saturation, linear and cut-off region respectively. corners in both ‘no skew’ and ‘5% skew’ to note the

Table 4 Power and frequency of oscillation Analysis

Analysis Process No skew 5% process skew
corners
Power Fosc Power Fosc (GHz)
Table 3 Device parameters (mW) (GHz) (mW)
Parameters Value X r X r

Technology 90 nm Pre NN 2.12 10.6 2.13 90.4 10.6 73.3

Supply voltage 1.2 V layout FF 2.69 13.2 2.70 111 13.2 82.5
Load capacitor 10f F FS 1.57 9.15 1.58 69.3 9.15 83.8
Vton 0.217 V SF 2.57 11.1 2.58 109 11.0 62.5
Vtop 0.269 V SS 1.52 7.73 1.52 67.3 7.73 68.6
W/L (for PMOS) 16 Post NN 2.09 9.21 2.10 89.1 9.15 72.2
W/L (for NMOS) 26 layout FF 2.64 11.3 2.65 110 11.2 81.6
Vb 0.080 V FS 1.56 8.03 1.56 68.8 7.96 82.8
lp Cox (for PMOS) 0.82 9 10-4 SF 2.52 9.53 2.53 106 9.48 61.7
ln Cox (for NMOS) 0.77 9 10-4 SS 1.50 6.80 1.51 66.9 6.75 66.8
No of stages (N) 5
X = Mean and r = Standard deviation

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different temperatures. When both the control signal and

supply voltage are at 1.2 V, the power consumption is
measured to be 2.126 mW and 2.092 mW in pre layout and
post layout respectively. Also, it is seen that the rise in
temperature reduces the mobility and so the delay at each
stage will be increased to curb down the oscillation.

5.3 Oscillation frequency as a function

of temperature and no. of stages

As stated in the previous section, the proposed design

portrays decrement in frequency with the rise in tempera-
ture and it is noted from Fig. 7a that the temperature
change from – 30 to 150 C reflects a lowering of fre-
quency from 12.49 to 7.97 GHz and 10.77 to 6.97 GHz in
pre layout and post layout respectively. We have also
Fig. 5 Histogram Plot a Avg. Power. b Oscillation frequency studied this metric as a function of odd number of stages as
seen in Fig. 7b, where variation from 3rd stage to 13th
stage has resulted in lowering of frequency from 18.275 to
4.433 GHz and 15.55 to 3.75 GHz in pre-layout and post
layout respectively.

5.4 Analysis of VCO gain

The change in oscillation frequency as a function of change

in control voltage is termed as tuning sensitivity or gain of
VCO and is represented as:

Fig. 6 Metrics varying Vctrl a Power. b Oscillation frequency

fluctuation in values of average power and frequency. It is

perceived from Table 4 that both the metrics got deviated
very marginally from pre-layout to post layout. On the
other end, the reading of average power dissipation and fosc
in nominal (NN) corner for ‘no skew’ is found to get
changed by 0.047% and 0.048% in pre layout and 0.09%
and 0.65% in post layout respectively for ‘5% skew’.
Figure 5 displays the histogram plot of both the metrics
simulated in post layout with 500 runs of Monte Carlo to
note the mean of both metrics to be almost equal to the Fig. 7 Frequency as a function of a temperature, b no. of stages
values in NN corner, thereby making a statement on the
reliability of the design.

5.2 Effect of control voltage sweep

The rise in control voltage in the proposed VCO saturates

the active load thereby allowing large current to flow
through it, which increases both power consumption and
frequency of oscillation. Figure 6 validates the above
statement for both metrics. Figure 6a displays power as
function of Vctrl at different supply voltage and Fig. 6b
portrays change in oscillation frequency by varying Vctrl at
Fig. 8 VCO gain vs Vctrl in a pre-layout, b post layot

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Dfosc noise. Figure 9 presents the phase noise as a function of

KVCO ¼ ð35Þ frequency in pre-layout and post layout, whereas Table 5
DVctrl
summarizes the values of both phase noise and output noise
Figure 8 refers to the gain plot, estimated using
at 1 MHz offset in all different process corners to note
Eq. (35), to notice a linear increase approximately up to
marginal deviation in both no skew and 5% skew based run
0.25 V of control signal and subsequently it decreases to
and that makes the design a resilient one.
saturate beyond 1 V. When the oscillation of proposed
design is at its peak the corresponding value of KVCO is
5.6 Estimation of figure of merit (FoM)
found to be 232.21 MHz/V and 272.41 MHz/V in pre
layout and post layout respectively. As the control signal
Figure of Merit (FoM) of VCO is a way to quantify the
swing derives good deviation in tuning sensitivity, it is
quality factor of a new design and is extensively used as the
advised to take substantial care in managing the loop
yardstick to contrast different approaches. It, being a
dynamics of frequency synthesizer.
function of average power, resonant frequency and phase
noise is expressed mathematically as;
5.5 Noise analysis    
fosc Pavg
FoM ¼ LðDf Þ  20 log þ 10 log ; ð36Þ
The noise analysis is one of the key concerns of any Df 1mW
voltage controlled oscillator design, its timing behavior and where Pavg is the average power, L(Df) is the phase noise at
frequency spectrum are a direct function of change in phase offset frequency ðDf Þ. This equation measures the FoM of
the new VCO to be - 216.22 dBc/Hz and - 213.98 dBc/
Hz in schematic and layout respectively.

5.7 Worst/best case analysis

To observe the best or worst case, the circuit undergoes a

simulation through FF corner (@1.26 V and – 40 C) and
SS corner (@1.14 V and 90 C) respectively to note the
variability of performance metrics under acute operating
and environmental conditions. Table 6 summarizes the
measured values, which portrays that the frequency of
oscillation and average power in (SS, FF) corner are found
to get deviated by (36.3%, 48.2%) and (16.3%, 79.9%)
respectively with respect to NN. Also the nominal values of
Fig. 9 Phase noise @ 1 MHz offset in schematic and layout Phase noise and output noise are perceived to get altered by

Table 5 Phase noise and output

Corners Phase noise (dBc/Hz) (Pre layout) Phase noise (dBc/Hz) (Post layout)
noise analysis
No skew 5% process skew No skew 5% process skew

TT - 138.9 - 139.28 - 137.9 - 139.20

FF - 140.5 - 140.6 - 139.6 - 139.8
FS - 140.2 - 140.1 - 139.1 - 138.1
SF - 136.2 - 136.5 - 134.8 - 135.1
SS - 136.3 - 136.6 - 135.0 - 135.3

Corners Output noise (dB) (Pre layout) Output noise (dB) (Post layout)
No skew 5% process skew No skew 5% process skew

TT - 168.35 - 168.37 - 168.40 - 168.35

FF - 167.90 - 167.93 - 168.1 - 167.95
FS - 167.1 - 169.70 - 167.9 - 169.76
SF - 167.20 - 167.12 - 167.00 - 167.15
SS - 168.50 - 168.40 - 168.40 - 168.51

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Table 6 Worst/Best Case

Parameter NN @ 270 C SS @ 900 C FF @ - 400 C
Analysis
Osc frequency (GHz) 10.606 6.7534 15.7266
Average power (mW) 2.126 1.7783 3.8255
PN (dBc/Hz) @ 1 MHz - 138.992 - 134.621 - 142.811
ON (dB) @ 1 MHz - 168.35 - 167.07 - 168.912
FoM (dBc/Hz) - 216.22 - 211.214 - 226.746

Table 7 Variation of metrics

Parameter NN corner (no variation) 10% variation in VDD with 10 HMz frequency
against PDN effect
Pre-layout Post-layout Pre-layout Post-layout

fosc (GHz) 10.606 9.211 10.5703 9.1809

Pavg (mW) 2.126 2.092 2.5715 2.5169
FoM (dBc/Hz) - 216.22 - 213.98 - 215.279 - 213.149

Table 8 Comparison table with different architecture

Parameters Zhang Chang and Liu et al. Cheng Ho et al. Abdul-Latif and Proposed work
et al. Chiu (2012) (2012b) et al. 2011 (2013) Sánchez-
(2012) Sinencio (2012) Pre Layout Post
Layout

Technology (nm) 90 90 90 90 90 90 90 90
Supply (V) 1.2 1.3 0.6 0.5 0.6 0.7 1.2 1.2
Avg. Power (mW) 12.0 3.0 3.0 1.157@ 0.771 37 2.126 2.092
2.24 GHz
Phase Noise (dBc/Hz) - 109.6 - 116.4 - 114.1 - 87.0 - 89.0 - 96.0 - 138.9 - 137.9
@1 MHz offset @771 MHz
Structure Ring Differential Ring Ring Ring Cyclic coupled Common
ring source
ring
Area (mm2) 0.16 0.36 0.09 0.17 0.19 13.5 – 0.105
Oscillation 15 20.8 19 2.24 0.48 1.0 10.606 9.21
Freq. (GHz)
Tuning Range 14% 4.8% 8.2% 90% 94% 63.16% 1.44–10.6 1.27–9.21
(86.4%) (86.2%)

Table 9 Validation at lower technology of 28 nm UMC

Supply voltage Oscillation frequency Tuning range Circuit parameter @ Vctrl = 1.2 V
(V) (Ghz) (%)
Average power Fosc Phase noise (dBc/Hz) @ Output noise (dB) @
(uW) (GHz) 1 MHz 1 MHz

0.8 0.882–5.078 82.63 170.152 5.135 - 62.9066 - 143.315

1.0 0.540–7.8126 93.08 414.238 7.869 - 61.3594 - 142.145
1.2 0.880–9.775 90.99 740.724 9.775 - 61.3573 - 141.038

3.1%, 2.7% and 0.76%, 0.333% in SS and FF corner frequency of 10 MHz and then computed the metrics to
respectively. analyze the circuit. The resulted effect is displayed in
A power delivery network (PDN) consists of inductance Table 7, which portrays a tiny deviation of 0.31%, 9.70%
and capacitance offered by PCB, pin, package and via and and 0.018% in oscillation frequency, average power and
it contributes to an oscillation in supply voltage known as FoM respectively during post layout simulation, thereby
power supply noise. To emulate the PDN effect, we have making the circuit tolerant enough against supply variation
introduced a 10% variation in supply voltage along with a and supply noise.

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 Microsystem Technologies

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Information Technology (MEITY) Government of India.
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Hz/mW FOM, rotary traveling wave VCO in 90 nm CMOS.
IEEE Microw Wirel Compon Lett 22(4):206–208
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Solid-State Circuits 47(6):1278–1294 jurisdictional claims in published maps and institutional affiliations.

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