International journal of mc square scientific research,

Vol 1 , June 2009

A BIST TPG for Low Power Dissipation and

High Fault Coverage
R. Madhusudhanan R.Balarani
Research scholar Research Scholar
Sathyabama university SRM University
Chennai, India Chennai, India
[email protected]

Abstract—This paper presents a low achieving 100% fault coverage for all
hardware overhead test pattern generator ISCAS’89 benchmark circuits. Larger
(TPG) for scan-based built-in self-test (BIST) reduction in switching activity is achieved in
that can reduce switching activity in circuits large circuits. Experimental results also show
under test (CUTs) during BIST and also that the proposed BIST can be implemented
achieve very high fault coverage with with low area overhead.
reasonable lengths of test sequences. The Index Terms—Built-in self-test (BIST), heat
dissipation during test application, low power testing,
proposed BIST TPG decreases transitions power dissipation during test application, random
pattern testing.
that occur at scan inputs during scan shift
operations and hence reduces switching
I. INTRODUCTION
activity in the CUT. The proposed BIST is
Since in built-in self-test (BIST), test patterns
comprised of two TPGs: LT-RTPG and 3-
are generated and applied to the circuit-under-
weight WRBIST. Test patterns generated by
test (CUT) by on-chip hardware, minimizing
the LT-RTPG detect easy-to-detect faults and
hardware overhead is a major concern of BIST
test patterns generated by the 3-weight
implementation. Unlike stored pattern BIST,
WRBIST detect faults that remain
which requires high hardware overhead due to
undetected after LT-RTPG patterns are
memory devices required to store precomputed
applied. The proposed BIST TPG does not
test patterns, pseudorandom BIST, where test
require modification of mission logics, which
patterns are generated by pseudorandom pattern
can lead to performance degradation.
generators such as linear feedback shift registers
Experimental results for ISCAS’89
(LFSRs) and cellular automata (CA), requires
benchmark circuits demonstrate that the
very little hardware overhead. However,
proposed BIST can significantly reduce
achieving high fault coverage for CUTs that
switching activity during BIST while
contain many random pattern resistant faults
8
 International journal of mc square scientific research,
Vol 1 , June 2009

(RPRFs) only with (pseudo) random patterns 3-weight WRBIST, only three weights, 0, 0.5,
generated by an LFSR or CA often requires and 1, are assigned. Since only three weights are
unacceptably long test sequences thereby used, circuitry to generate weights is simple;
resulting in prohibitively long test time. The weight 1 (0) is obtained by fixing a signal to a 1
random pattern test length required to achieve (0) and weight 0.5 by driving a signal by an
high fault coverage is often determined by only output of a pseudorandom pattern generator,
a few RPRFs [1]. such as an LFSR. Weight sets are calculated
Several techniques have been proposed to from test cubes for RPRFs.
address this problem. Reseedable and/or
II. 3-WEIGHT WRBIST
reconfigurable LFSRs are proposed in [2]–[4]. In
[5] and [6], random patterns that do not detect A. Generator

any new faults are mapped into deterministic In this paper, we assume that the sequential
tests for RPRFs. In test point insertion (TPI) CUT has primary and state inputs, and
techniques [7], [8], control and observation employs full-scan. Even though the proposed
points are inserted at selected gates to improve BIST TPG is applicable to scan designs with
detection probabilities of RPRFs. In weighted multiple scan chains, we assume that all
random pattern testing [1], [9]–[11], the outputs primary and state inputs are driven by a single
of test pattern generator (TPG) are biased to scan chain unless stated otherwise (application
generate test sequences that have nonuniform to multiple scan chains is discussed separately in
signal probabilities to increase detection Section V) only for clarity and convenience of
probabilities of RPRFs that escape illustration. A test cube is a test pattern that has
pseudorandom test sequences, which have a uni- unspecified inputs. The detection probability of
form signal probability of 0.5. Random pattern a fault is defined as the probability that a
generators proposed in [12] and [13] use Markov randomly generated test pattern detects the fault
sources to exploit spatial correlation between [1]. In the 3-weight WRBIST scheme, fault
state inputs that are consecutively located in the coverage for a random pattern resistant circuit is
scan chain. A 3-weight weighted random BIST enhanced by improving detection probabilities
(3-weight WRBIST) can be classified as an of RPRFs; the detection probability of an RPRF
extreme case of conventional weighted random is improved by fixing some inputs of the CUT to
pattern testing BIST. However, in contrast to the values specified in a deterministic test cube
conventional weighted random pattern testing for the RPRF. A generator or weight set is a
BIST where various weights, e.g., 0, 0.25, 0.5, vector that represents weights that are assigned
0.75, 1.0, can be assigned to outputs of TPGs, in to inputs of the circuit during 3-weight

9
 International journal of mc square scientific research,
Vol 1 , June 2009

WRBIST. Inputs that are assigned weight 1 (0) switching activity during BIST by reducing
are fixed to 1 (0) and inputs that are assigned transitions at scan inputs during scan shift
weight 0.5 are driven by outputs of the operations. An example LT-RTPG is shown in
pseudorandom pattern generator, such as an Fig. 3. The LT-RTPG is comprised of an -
LFSR and a CA. A generator is calculated from stage LFSR,
a set of deterministic test cubes for RPRFs.
Fig.3. LT-RTPG.
Inputs that are assigned

’s in a generator are called conflicting inputs of the

generator.

-input AND gate, and a toggle flip-flop (T

flip-flop). Hence, it can be implemented with
Fig. 1. Example test cube sets. (a) Testcube set . (b) Testcube very little hardware. Each of
subsets .

inputs of the AND gate is connected

(weight sets).
to either a normal or an inverting output of the
LFSR stages. If large
is used, large sets of neighboring state inputs
will be assigned identical values in most test pat-
terns, resulting in the decrease fault coverage or
the increase in test sequence length. Hence, like
[23], in this paper, LT-RTPGs with only

Fig. 2. Exemplary 3-weight WRBIST. or 3 are used. Since a

flip-flop holds previous values until the input

of the
flip-flop is assigned a 1, the same value
A. LT-RTPG

The LT-RTPG proposed in [23] reduces

, where

10
 International journal of mc square scientific research,
Vol 1 , June 2009

, is repeatedly scanned into the scan circuits. In this paper we demonstrate that
chain until the value at the output of the AND augmenting the LT-RTPG with the serialfixing
gate becomes 1. Hence, adjacent scan flip-flops 3-weight WRBIST proposed in [27] can attain
are assigned identical values in most test high fault coverage without excessive switching
patterns and scan inputs have fewer transitions activity or large area overhead even for circuits
during scan shift operations. Since most that have large numbers of RPRFs.
switching activity during scan BIST occurs
during scan shift operations (a capture cycle
occurs at every

cycles), the LT-RTPG can reduce heat

VI. EXPERIMENTAL RESULTS
dissipation during overall scan testing. Various
properties of the LT-RTPG are studied and a Table I compares results obtained by
detailed methodology for its design is presented applying test sequences generated by
in [23]. regular LFSRs (LFSR sequences, for
It has been observed that many faults that short) and results obtained by applying
escape random patterns are highly correlated test sequences generated by the proposed
with each other and can be detected by TPGs (the proposed TPG sequences, for
continuously complementing values of a few TABLE I COMPARISONS WITH LFSR GENERATED PATTERNS (SINGLE
SCAN CHAIN)
inputs from a parent test vector. This
observation is exploited in [26][27], [31], and
[32] to improve fault coverage for circuits that
have large numbers of RPRFs. We have also
observed that tests for faults that escape LT-
RTPG test sequences share many common input
assignments. This implies that RPRFs that
escape LT-RTPG test sequences can be
effectively detected by fixing selected inputs to short). Columns under the heading LFSR give
binary values specified in deterministic test results of LFSR sequences while columns under
cubes for these RPRFs and applying random the heading proposed give results of proposed
patterns to the rest of inputs. This technique is TPG sequences. The column # pat under the
used in the 3-weight WRBIST to achieve high heading LFSR shows the number of test patterns
fault coverage for random pattern resistant generated by the LFSR and the column achieved

11
 International journal of mc square scientific research,
Vol 1 , June 2009

by the LFSR sequence. correlated. The proposed BIST is comprised

of two TPGs: LT-RTPG
[23] and 3-weight WRBIST [27]. Test sequences
VII. CONCLUSION
generated by the LT-RTPG detect easy-to-detect
faults. Faults that escape LT-RTPG test
sequences are detected by test patterns generated
This paper presents a low
by the 3-weight WRBIST. The number of
hardware overhead TPG for scan-based BIST
weight sets (generators) is minimized by guiding
that can reduce switching activity in CUTs
the proposed ATPG with cost functions that
during BIST and also achieve very high fault
reflect the number of conflicting inputs to be in-
coverage with a reasonable length of test
curred by setting an input to a binary value. An
sequence. Unacceptably long test sequences
algorithm to design the 3-weight WRBIST that
are often required to attain high fault coverage
requires minimal hardware overhead and whose
with pseudorandom test patterns for circuits
patterns cause minimal number of transitions
that have many random pattern resistant
during scan shift cycles is presented. Hardware
faults. The main objective of most recent
overhead for the proposed TPG is further
BIST techniques has been the design of TPGs
reduced by identifying compatible scan chains in
that achieve high fault coverage at acceptable
multiple scan chain designs. Experimental re-
test lengths for such circuits. While this ob-
sults for ISCAS’89 benchmark circuits
jective still remains important, reducing heat
demonstrate that the proposed BIST can
dissipation during test application is also significantly reduce switching activity during BIST
becoming an important objective. Since the while achieving 100% fault coverage for all
correlation between consecutive patterns benchmark circuits. Larger reduction in switching
applied to a circuit during BIST is activity is achieved for large circuits, which have
significantly lower, switching activity in the long scan chains. The proposed BIST structure does

circuit can be significantly higher during BIST not require modification of mission logic which can
cause performance degradation. Experimental results
than that during its normal operation.
for large industrial circuits demonstrate that the
Excessive switching activity during test ap-
proposed TPG can significantly improve fault
plication can cause several problems. The
coverage of LFSR generated test sequences with low
proposed TPG reduces the number of
hardware overhead.
transitions that occur at scan inputs during
scan shifting by scanning in the test
patterns where neighboring bits are highly

12
 International journal of mc square scientific research,
Vol 1 , June 2009

for generating weighted random test

patterns,” IEEE Trans. Comput., vol. 33,
no. 2, pp. 149–161, Mar. 1989.
[11] H.-C. Tsai, K.-T. Cheng, C.-J. Lin, and S.
Bhawmik, “Efficient test-point selection
for scan-based BIST,” IEEE Trans. Very
REFERENCES Large Scale Integr. (VLSI) Syst., vol. 6,
[1] P. H. Bardell, W. H. McAnney, and J. no. 4, pp. 667–676, Dec. 1998.
Savir, Built-In Test for VLSI: [12] W. Li, C. Yu, S. M. Reddy, and I.
Pseudorandom Techniques. New York: Pomeranz, “A scan BIST generation
Wiley, 1987. method using a markov source and partial
[2] S. Hellebrand, J. Rajski, S. Tarnick, S. BIST bit-fixing,” in Proc. IEEE-ACM
Venkataraman, and B. Courtois, “Built-In Design Autom. Conf., 2003, pp. 554–559.
test for circuits with scan based on [13] N. Z. Basturkmen, S. M. Reddy, and I.
reseeding of multiple-polynomial linear Pomeranz, “Pseudo random patterns using
feedback shift registers,” IEEE Trans. markov sources for scan BIST,” in Proc.
Comput., vol. 44, no. 2, pp. 223–233, Feb. IEEE Int. Test Conf., 2002, pp. 1013–
1995. 1021.
[3] N. Zacharia, J. Rajski, and J. Tyszer, [14] Y. Zorian, “A distributed BIST control
“Decompression of test data using scheme for complex VLSI devices,” in
variable-length seed LFSRs,” in Proc. Proc. VLSI Testing Symp., 1993, pp. 4–9.
IEEE 13th VLSI Test Symp., 1995, pp. [15] S. W. Golomb, Shift Register Sequences.
426–433. Laguna Hills, CA: Aegean Park, 1982.
[4] S. Hellebrand, S. Tarnick, and J. Rajski, [16] C.-Y. Tsui, M. Pedram, C.-A. Chen, and
“Generation of vector patterns through A. M. Despain, “Low power state
reseeding of multiple-polynomial linear assignment targeting two-and multi-level
feedback shift registers,” in Proc. IEEE logic implementation,” in Proc. IEEE Int.
Int. Test Conf., 1992, pp. 120–129. Conf. Comput.-Aided Des., 1994, pp. 82–
[5] N. A. Touba and E. J. McCluskey, 87.
“Altering a pseudo-random bit sequence [17] P. Girard, L. Guiller, C. Landrault, and S.
for scan-based BIST,” in Proc. IEEE Int. Pravossoudovitch, “A test vector
Test Conf., 1996, pp. 167–175. inhibiting technique for low energy BIST
[6] M. Chatterjee and D. K. Pradhan, “A new design,” in Proc. VLSI Test. Symp., 1999,
pattern biasing technique for BIST,” in pp. 407–412.
Proc. VLSITS, 1995, pp. 417–425. [18] V. Dabholkar, S. Chakravarty, I.
[7] N. Tamarapalli and J. Rajski, Pomeranz, and S. Reddy, “Techniques for
“Constructive multi-phase test point in- minimizing power dissipation in scan and
sertion for scan-based BIST,” in Proc. combinational circuits during test
IEEE Int. Test Conf., 1996, pp. 649–658. application,” IEEE Trans. Comput.-Aided
[8] Y. Savaria, B. Lague, and B. Kaminska, Des. Integr. Circuits Syst., vol. 17, no. 12,
“A pragmatic approach to the design of pp. 1325–1333, Dec. 1998.
self-testing circuits,” in Proc. IEEE Int. [19] R. M. Chou, K. K. Saluja, and V. D.
Test Conf., 1989, pp. 745–754. Agrawal, “Scheduling tests for VLSI
[9] J. Hartmann and G. Kemnitz, “How to do systems under power constraints,” IEEE
weighted random testing for BIST,” in Trans. Very Large Scale Integr. (VLSI)
Proc. IEEE Int. Conf. Comput.-Aided Syst., vol. 5, no. 2, pp. 175–185, Jun.
Design, 1993, pp. 568–571. 1997.
[10] J. Waicukauski, E. Lindbloom, E. [20] T. Schuele and A. P. Stroele, “Test
Eichelberger, and O. Forlenza, “A method scheduling for minimal energy con-
13
 International journal of mc square scientific research,
Vol 1 , June 2009

sumption under power constrainits,” in [31] K.-H. Tsai, J. Rajski, and M. Marek-
Proc. VLSI Test. Symp., 2001, pp. 312– Sadowska, “Star test: The theory and its
318. applications,” IEEE Trans. Comput.-
[21] N. H. E. Weste and K. Eshraghian, Aided Des. Integr. Circuits Syst., vol. 19,
Principles of CMOS VLSI Design: A no. 9, pp. 1052–1064, Sep. 2000.
Systems Perspective, 2nd ed. Reading, [32] I. Pomeranz and S. Reddy, “3-weight
MA: Addison-Wesley, 1992. pseudo-random test generation based on
[22] S. Gerstendorfer and H.-J. Wunderlich, a deterministic test set for combinational
“Minimized power consumption for scan- and sequential circuits,” IEEE Trans.
based BIST,” in Proc. IEEE Int. Test Comput.-Aided Des. Integr. Circuits
Conf., 1999, pp. 77–84. Syst., vol. 12, pp. 1050–1058, Jul. 1993.
[23] S. Wang and S. K. Gupta, “LT-RTPG: A [33] T. H. Cormen, C. E. Leiserson, and R. L.
new test-per-scan BIST TPG for low heat Rivest, Introduction to Algorithm.
dissipation,” IEEE Trans. Comput.-Aided Cambirdge, MA: MIT Press, 1990.
Des. Integr. Circuits Syst., vol. 25, no. 8, [34] J. Savir, “Skewed-load transition test:
pp. 1565–1574, Aug. 2006. Part I, calculus,” in Proc. IEEE Int. Test
[24] S. Wang and S. K. Gupta, “DS-LFSR: A Conf., 1992, pp. 705–713.
BIST TPG for low heat dissipation,” [35] E. M. Sentovich, K. J. Singh, L.
IEEE Trans. Comput.-Aided Des. Integr. Lavagno, C. Moon, R. Murgai, A.
Circuits Syst., vol. 21, no. 7, pp. 842– Saklanha, H. Savoj, P. R. Stephan, R. K.
851, Jul. 2002. Brayton, and A. Sangiovanni-Vincentelli,
[25] F. Corno, M. Rebaudengo, M. S. “SIS: A system for sequential circuit
Reorda, G. Squillero, and M. Violante, synthesis,” Electron. Res. Lab.
“Low power BIST via non-linear hybrid Memorandum, Univ. California, Los
celluar automata,” in Proc. VLSI Test. Angeles, UCB/ERL M92/41, 1992.
Symp., 2000, pp. 29–34. [36] L. Li and K. Chakrabarty, “Test set
[26] S. Wang, “Generation of low power embedding for deterministic BIST using a
dissipation and high fault coverage reconfigurable interconnect network,”
patterns for scan-basedBIST,” in Proc. IEEE Trans. Comput.-Aided Des. Integr.
IEEE Int. Test Conf., 2002, pp. 834–843. Circuits Syst., vol. 23, no. 9, pp. 1289–
[27] S. Wang, “Low hardware 1305, Sep. 2004.
overhead scan based 3-weight weighted [37] N.-C. Lai, S.-J. Wang, and Y.-H. Fu,
random BIST,” in Proc. IEEE Int. Test “Low-power BIST with a smoother and
Conf., 2001, pp. 868–877. scan-chain reorder under optimal cluster
[28] S. Wang, “Minimizing Heat size,” IEEE Trans. Comput.-Aided Des.
Dissipation During Test Application,” Integr. Circuits Syst., vol. 25, no. 11, pp.
Ph.D. dissertation, EE-Systems Dept., 2586–2594, Nov. 2006.
Univ. Southern California, Los Angeles, [38] N. Z. Basturkmen, S. M. Reddy, and I.
1998. Pomeranz, “A low power pseudo-
[29] L. H. Goldstein and E. L. Thigpen, random BIST technique,” J. Electron.
“SCOAP: Sandia controllability/ob- Test.: Theory Appl., vol. 19, no. 6, pp.
servability analysis program,” in Proc. 637–644, Dec. 2003.
IEEE-ACM Des. Autom. Conf., 1980, pp.
190–196.
[30] P. Goel, “An implicit enumeration
algorithm to generate tests for com-
binational logic circuits,” IEEE Trans.
Comput., vol. C-30, no. 3, pp. 215–222,
Mar. 1981.
14