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Vlsi Data Conversion Circuits: Problem Set 4

The document discusses two latch circuits used in data conversion and poses five problems: 1. The first problem asks to simulate two latch circuits to determine dynamic offset and explains how this is done. 2. The second problem discusses a circuit that subtracts differential references from a differential input using coupling capacitors and asks how it works and how elements would be chosen. 3. The third problem asks to design a 4-bit flash ADC using the circuit from problem 2 as a basic building block and explains specifications like input range and ideal voltage sources. 4. The fourth problem asks to show the spectrum of the ADC output for a full-scale sinewave and calculate signal-to-noise ratio.

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Kiruba K
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57 views

Vlsi Data Conversion Circuits: Problem Set 4

The document discusses two latch circuits used in data conversion and poses five problems: 1. The first problem asks to simulate two latch circuits to determine dynamic offset and explains how this is done. 2. The second problem discusses a circuit that subtracts differential references from a differential input using coupling capacitors and asks how it works and how elements would be chosen. 3. The third problem asks to design a 4-bit flash ADC using the circuit from problem 2 as a basic building block and explains specifications like input range and ideal voltage sources. 4. The fourth problem asks to show the spectrum of the ADC output for a full-scale sinewave and calculate signal-to-noise ratio.

Uploaded by

Kiruba K
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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VLSI DATA CONVERSION CIRCUITS : PROBLEM SET 4

Problem 1 Problem 2
Vrefp Vcm Vcm Vrefm
Vdda
Lb L Cb La Vdda La Cb L
LC LC LC LC
Vdda ip im
M1 M4 ip M1 M4 im
LC om L op
ip
X LR
Y L Ld Ld
im Lb
LC
M2 M3 gnda
Lb M2 M3 Lb
L Ld
gnda
gnda L , La

L LC

LC
Ld
LR
Ld

Figure 1: Latch circuits for Problem 1. Figure 2: Latch circuit for Problem 2.

In this problem, we attempt to understand the issue of This problem discusses another way of subtracting
dynamic offset. Consider the two latch circuits in Fig. 1. The differential references from the differential input. This is
first latch was discussed in class. Another candidate latch done by the use of coupling capacitors Cb as shown in Fig. 2.
(with the advantage of greatly simplified clocking) is shown
towards the right of the figure. In both latches, L is the latch 1. Explain clearly how this circuit works.
signal, while Lb is its complement. For simplicity, use an
2. What is the capacitance looking in from the input when
ideal clock generator. Vdd = 1.8 V. The input is fully differ-
LC is high?
ential, with a common-mode voltage of 0.9 V. The clock fre-
quency is 10 MHz. 3. How will you choose Cb ?

1. Use minimum sizes for all transistors. Choose appro- 4. Using this as the basic building block, design a 4 bit flash
priate implementations for the switches. Determine dy- ADC. Vdd = 1.8 V. The full scale input is to be 3 V (peak-
namic offset using the following procedure - the differ- to-peak differential), with a common-mode voltage of
ential input is to be made a slow ramp, increasing at 0.9 V. Assume you have ideal voltage sources of 1.65 V
2 mV every clock period, starting from −V dd/5 and go- and 0.15 V from which to operate the ladder. How will
ing all the way to V dd/5. We hope that the offset will lie you choose the value of the ladder resistors ? Design
within this range. The “threshold” of the latch (ideally the digital back-end (transition detect and the 1-of-N to
to be zero) can be found to within 2 mV by observing binary converter).
when the regenerated output flips sign. Take care of the 5. Show the spectrum of the ADC output for a full-scale
following during simulation - choose the time step of sinewave at about fs/2. What is the SQNR (in dB) ? One
the simulation to be sufficiently small so that the wave- way of doing this is to print the four ADC output bits
forms during regeneration do not change appreciably. into a file, read the file into MATLAB, convert from bi-
Which of the latches has more dynamic offset ? Why ? nary to decimal, and do the FFT in MATLAB. Another
In your report, draw the circuit diagrams with all device way of doing this is to use an ideal 4-bit DAC at the out-
sizes marked. Also on one graph, plot the waveforms of put of the ADC and run an FFT on the DAC output in
all latch nodes in that clock period where the latch flips Eldo.
sign.

2. Deliberately add a capacitance of 0.5 fF at the drain of


M1 only, and repeat part (a). What do you notice? Why?

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