Gate Driver Design – from Basics to Details

Wei Zhang
What will I get out of this session?
 PURPOSES: • Part numbers mentioned:
• What is the difference: low side, • Low side: UCC2751x, UCC2752x,
high and low side driver, and UCC27x24
isolated gate driver? • H-/L- Side: UCC2771x, UCC272xx
• How to maximize the gate driver • Isolated: UCC2152x, UCC2122x UCC53xx
performance – from basic to details • Reference designs mentioned:
 Parasitics in the gate driver • TIDA-01160, TIDA-01159
 Hard/soft switching
 High dv/dt and di/dt
• Relevant end equipment:
 Isolated gate driver • EV/HEV, UPS, telecom, servers,
solar, motor drive
Where are gate driver ICs used?
Li-ion battery Adaptors and
portables chargers Server/telecom/UPS

Electric vehicles
Gate driver class D audio
applications

Solid state lighting Motor drive (VFD)

Renewables
(SSL)
 48V
PFC #n DC-DC #n
Bus converters POLs
AC EMI (Power Factor
#2
400VDC #m
85~265V PFC
Correction) DC-DC Batteries
filter
(Power Factor #1
PFC #1 DC-DC
Correction) POLs
(power factor 12V …
correction) uProcessor, memory, HDD…

VDC-Link 400V

Lkp 48V 48V

Lk
9.6V/12V
CR
CB
Lm

1. 1Ch/2Ch low side driver

CB Lks
2. High and low side driver 12V
100V/200V 600V Lks
3. Isolated gate driver
 Si-MOSFET IGBT SiC-MOSFET GaN

Nom-ON Nom-OFF
Voltage ratings 20~650V ≥650V ≥650V ≤650V
Optimal VGS 0~15V -10~15V -5~20V -5~10V -4~6V
Max.limit (±20V) (±20V) (-10~25V) (±18V) (-10~7V)
Si-MOSFET 10V IGBT 12V SiC-MOSFET GaN 5V
20V 4V
18V
16V

3V

2V
- I-V curves are from datasheets of Infineon, Fairchild, ST, CREE, EPC
 Lkp 48V 48V
Lk
9.6V/12V
CR
CB
Lm

Level shift circuit + NPN/PNP totem pole

Now
3.3V/5V
PWM signal from
microcontroller or
DSP
- Reduces BOM component count
Micro/DSP
- Reduces PCB space
- Protects from spurious signals
during power up (such as UVLO)
Level shifted 12V with high peak
12V signal source/sink current
- Improves reliability
 Lkp 48V 48V
Lk
9.6V/12V
CR
CB
Lm

VBias
HV(100~700V)
RBoot DBoot
HO
VDD-VF
VDD
HB
Q1 HV
Level Shift
SGND (100~680V) HS

Canceller
HI

Noise
HO
PWM1 CBoot
HS HS High
side
GND Q2
Similar as low
VDD VDD LO side driver
PWM2
LI
LO
GND LI HI
GND UCC27714, UCC27201A, UCC27712, UCC27282 GND
 VDC-Link 400V 12/48V
Insulation
85V~265V Lkp
L EMI
filter
CR
CB
N Lm

PE
Primary Secondary
Half/full bridge feedback,
gate driver controller

IEC 60950-1 ed. 2.0, Table 5B

Test voltage for electric strength based on peak working voltage
Working voltage V, peak or
Functional insulation Basic insulation Reinforced insulation
DC
(VRMS) (VRMS) (VRMS)
≤210 1000 1000 1500
≤420 1500 1500 3000
Isolation Definition

Functional Insulation that is necessary only for the correct functioning of the equipment

Basic Insulation to provide basic protection against electric shock

Independent insulation applied in addition to BASIC insulation in order to reduce the risk of
Supplementary
electric shock in the event of a failure of the BASIC insulation

Double Insulation comprising both BASIC insulation and SUPPLEMENTARY insulation

Single insulation system that provides a degree of protection against electric shock
Reinforced
equivalent to DOUBLE insulation under the conditions specified in this standard
 AC/DC-DC/DC (36V~75V) Telecom BMP
VDC-Link 400V 48V DC link

EMI 9.6V/12V
L
&
PFC
N

ISO driver ISO driver

UCC21230 ISO driver Low
UCC21230side
2× ISO Driver
ISOLATION BARRIER
2× 2× ISO Driver
ISOLATION BARRIER
1× driver
ISOLATION BARRIER

Reinforced Functional Basic

ISOLATION BARRIER ISOLATION BARRIER ISOLATION BARRIER ISOLATION BARRIER

(≥200V and Ground bouncing) (≥200V and Ground bouncing)

μ-controller μ-controller

PE

According to Figure 2H of IEC60950-1

 AC/DC-DC/DC (36V~60V) Telecom BMP
VDC-Link 400V 48V DC link

EMI 9.6V/12V
L
&
PFC
N

ISO driver ISO driver

UCC21230 ISO driver Low
UCC21230side
2× ISO Driver
ISOLATION BARRIER
2× 2× ISO Driver
ISOLATION BARRIER
1× driver
ISOLATION BARRIER

Basic Functional Functional

ISOLATION BARRIER ISOLATION BARRIER ISOLATION BARRIER ISOLATION BARRIER

(≥200V and Ground bouncing) (≥200V and Ground bouncing)

μ-controller μ-controller

PE
According to Figure 2H of IEC60950-1
 TYPE A HV
TYPE B
VCC VCC VBias DBoot HV
CIO Q1 VCC
LDO HB Q1
PWM1 VCC HO
PWM1 High side
Controller

HI
Low CByp

Controller
and
Side HS CByp
Q2 LI Low side
Driver Gate driver
PWM2 PWM2 VSS Q2
LO
EN/NC
VSS
COM
SGND PGND VSS
CIO SGND Isolator PGND

Type A Type B
TProp ≈20ns ≈100ns
Bias power NO Yes
CIO ≥10pF <1pF
Parasitics Large (LLK) Very small
Overshoot Large Small
Size Bulky Small
 TYPE A HV
TYPE B
VCC VCC VBias DBoot HV
VCC
Q1
LDO HB Q1
PWM1 VCC HO
PWM1 High side
Controller

HI
Low CByp

Controller
and
side HS CByp
Q2 LI Low side
driver Gate driver
PWM2 PWM2 VSS Q2
LO
EN/NC
VSS
COM
SGND PGND VSS SGND Isolator PGND

Area Vol
W (mm) L (mm) H (mm)
(mm2) (mm3) TYPE C: ISO driver
UCC27324 5 6.2 1.75 31 54.25
Type A  CMTI>100V/ns
GA3550-BL 17.4 24.13 10 420 4200
 5kVrms reinforced isolation
SUM 451 4254
ISO7520C 10.5 10.6 2.65 111.3 295
 TProp: 19ns typ.
Type B UCC27714 8.75 6.2 1.75 54.25 95  Match./TPWD < 5ns
MURS360 8.1 6.1 2.4 49.41 119
SUM 215 509  110mm2
 TYPE A HV
TYPE B
VCC VCC VBias DBoot HV
VCC
Q1
LDO HB Q1
PWM1 VCC HO
PWM1 High side
Controller

HI
Low CByp

Controller
and
side HS CByp
Q2 LI Low side
driver Gate driver
PWM2 PWM2 VSS Q2
LO
EN/NC
VSS
COM
SGND PGND VSS SGND Isolator PGND

Area Vol
W (mm) L (mm) H (mm)
(mm2) (mm3) TYPE C: ISO driver
UCC27324 5 6.2 1.75 31 54.25
Type A  CMTI>100V/ns
GA3550-BL 17.4 24.13 10 420 4200
 5kVrms reinforced isolation
SUM 451 4254
ISO7520C 10.5 10.6 2.65 111.3 295
 TProp: 19ns typ.
Type B UCC27714 8.75 6.2 1.75 54.25 95  Match./TPWD < 5ns
MURS360 8.1 6.1 2.4 49.41 119
SUM 215 509  110mm2
• A) Optocoupler
• Signal transfer between two isolated circuits
using light – LED + phototransistor, ~1970s

• B) Transformer
• Integrated micro-transformer and electronic
circuitry, ~2001

• C) Capacitor
• Signal transmission through capacitive isolation
with on-off-keying (OOK) modulation, ~2004
UCC2122x, UCC2x520: 2-ch. Isolated Gate Driver

• 6A/4A sink/source active pull down

• 19ns propagation delay • UVLO options: 5V, 8V,
12V
• >100V/ns
• 3.0kV, 5.7kV basic /
• Up to 3~18V wide input reinforced isolation
range and 6.5~30V wide
output voltage range • Pin-2-pin compatible to
industry standard
• Programmable overlap,
and interlock/delay time • UL, VDE, CQC certified
from 0ns~5µs
• Output fail safe low with
UCC53xx single ch. isolated gate driver
Miller clamp: Split output: Emitter – UVLO control:
3-kV – UCC5310M and UCC5350M 3-kV – UCC5320S, UCC5350SB, UCC5390S 3-kV – UCC5320E and UCC5390E
5-kV – UCC5310M 5-kV – UCC5320S 5-kV – UCC5390E

• Features active Miller clamping • Two outputs OUTH and OUTL can • UVLO protection by monitoring the
which prevents false turn-on of be used to separately control rise voltage between the VCC2 and
the power transistors induced and fall times of power transistor GND2 pins to prevent the power
by the Miller current • Rise and fall times are controlled by transistors from operating in a
• Tie clamp pin to gate of FET series resistors: RGON and RGOFF saturation region
 CMT VCMT CMTI (V/ns)
IL CD
rising 300
Lf
250
VChg COSS
200

150

Positive-ChA
CMT COSS VCMT 100
Positive-ChB
CD
falling 50 Negative-ChA
Negative-ChB
0
-50 0 50 100 150
Lf IL Temperature
VChg
(°C)
 1. Parasitics in gate driver?
2. Gate driver soft/hard switching difference?

Driver 3. Strong gate driver and MOSFET nonlinear COSS?

4. Common mode transient immunity(CMTI), dv/dt and
di/dt through parasitics L and C?
5. How to separate power ground noise by PCB layout?
6. Power supply for isolated gate driver in UPS, server
and Telecom system
7. TIDA and experimental waveforms

Gate driver deep dive

Very critical role in converter efficiency and reliability
 SW-node
VCC

Driver CGD
Turn-ON
P
PWM CDS
N Turn-OFF

CGS

𝑪𝑰𝑺𝑺 = 𝑪𝑮𝑺 + 𝑪𝑮𝑫

𝑪𝑹𝑺𝑺 = 𝑪𝑮𝑫
𝑪𝑶𝑺𝑺 = 𝑪𝑮𝑫 + 𝑪𝑫𝑺
 Turn-ON Turn-OFF Switching on loss
VGS 𝒕𝟑
𝑽𝑫𝑺 𝒕 ∙ 𝑰𝑫 𝒕 𝒅𝒕 + 𝐸𝑂𝑆𝑆
VTH 𝒕𝟏
VDS 𝟏
𝒕𝟏~𝟑 ∝
𝑰𝑫𝒓𝒗
ID
PON POFF Stronger driver  lower
switching loss
t0 t1 t2 t3 t4 t0 t1 t2 t3 t4

VCC t0~t2 SW-node VCC t2~t3 SW-node VCC t3~t4 SW-node

CGD CGD CGD

P P P

N CGS CDS N CGS CDS N CGS CDS

 IF Diode reverse
recovery SJ-MOSFET IGBT
QRR VIN
VIN

VF IL IL
SW SW

Parasitic Anti-parallel diode

VGS Turn-on w/ diode (co-package)
QRR
VTH VGS
15V/div VGE
VDS
VDS 10V/div
100V/div
VCE
100V/div
ID_pk
ID
QRR 𝐼𝑑𝑠
20𝐴/𝑑𝑖𝑣 𝐼𝐶
𝟖𝟎𝒏𝒔/𝒅𝒊𝒗 10𝐴/𝑑𝑖𝑣 𝟐𝟎𝒏𝒔/𝒅𝒊𝒗
t0 t1 t2a t2b t3 t4
 LR
IL
VDC-Link Lks
CR 12V
85V~ EMI
400V Lm
265V filter
Lks

CRM totem pole PFC

LLC converter + center-tap rectifier
VGS …

IL … S1
S2

VDS
VGS ZVS
ILr
IL (A)
ILm

VDS (V)
ZVS
 Hard-switching Soft-switching
VGS a b c VGS c
VTH VTH
VDS VDS
Coss discharge

ID ID Current slope
decided by inductor

t0 t1 t2 t3
VCC a SW-Node VCC b SW-Node VCC c SW-node

CGD CGD CGD

P P P

N CGS CDS N CGS CDS N CGS CDS

 Soft-switching
VGS
c
VTH
VDS
Coss discharge

AHS_ON ID Current slope decided by

inductor

t0 t1 t2 t3
AHS_OFF
𝐸𝐺_𝐻𝑆 = 𝐴𝐻𝑆_𝑂𝑁 + 𝐴𝐻𝑆_𝑂𝐹𝐹 = 𝑉𝐺𝑆 ∙ 𝑄𝐺_𝐻𝑆

QG_HS
𝑷𝑮𝒂𝒕𝒆𝑫𝒓𝒗 = 𝑬𝑮 ∙ 𝒇𝑺𝑾
Qgate[nc]
 Soft-switching
VGS
c
VTH
VDS
AZVS_ON Coss discharge

ID Current slope decided by

inductor
AZVS_OFF t0 t1 t2 t3

𝐸𝐺_𝐻𝑆 = 𝐴𝐻𝑆_𝑂𝑁 + 𝐴𝐻𝑆_𝑂𝐹𝐹 = 𝑉𝐺𝑆 ∙ 𝑄𝐺_𝐻𝑆

QG_ZVS 𝐸𝐺_𝑍𝑉𝑆 = 𝐴𝑍𝑉𝑆_𝑂𝑁 + 𝐴𝑍𝑉𝑆_𝑂𝐹𝐹 ≈ 𝑉𝐺𝑆 ∙ 𝑄𝐺_𝑍𝑉𝑆
QG_HS
𝑷𝑮𝒂𝒕𝒆𝑫𝒓𝒗 = 𝑬𝑮 ∙ 𝒇𝑺𝑾
Qgate[nc]
 w/ Weak driver w/ Strong driver w/ Strong driver w/
VGS VGS VGS nonlinear COSS
VTH

VDS VDS VDS

ID ID ID

t0 t1 t2 t3 t4 t0 t1 t2 t3 t0 t1 t2 t3
COSS(0V)
=6nF
• Switching behavior is not controlled by gate current,
but by COSS and load current

COSS(400V)
• Large COSS at low voltage performs as natural snubber
<30pF • Small COSS at high voltage shortens V-I overlap
• Fast dv/dt and di/dt, other bad things
 Zoom IN

VGS VGS
(10V/div)
15A (5V/div)
IDS
(10A/div)
IDS
(5A/div)
VDS
VDS (5V/div)
(100V/div)
200ns/div 20ns/div
 Vin Vin
ID_Coss2 VGS_S1
ID_Coss2 VGS(plt)
S2
Coss2
I S2
Coss2
II
VGS(th) COSS Recovered
IM charge at turn-on
t
ID_CH ID_Coss1 Im ID_CH ID_Coss1 Im ID_CH
S1 S1 (EOSS)
Coss1 Coss1 t
Lm T Lm T IM
ID_Coss

Vin Vin t
Vin
tfi
S2 III S2 IV
Coss2 Coss2
VDS_S1

ID_Coss1 Im Im t
S1 S1
Coss1 I II III IV
Coss1
Lm T Lm T

In period II, V DS _ S1 VDS _ S 2 ; C oss1C oss2 High

I D _ Coss I D _ Coss1  I D _ Coss2  I D _ Coss1 dv/dt, di/dt
 VBias
RBoot DBoot
VHV

VCC Q1
Level Shift HB

Noise Canceller
GND
HI
CIO HO
PWM1 CBoot
Controller

HS

GND CIO Q2
VSS
VCC VCC LO
PWM2
LI
Missing

VSS
HO pulses COM

GND Driver IC GND

HI
 dv/dt (IOFF
dv/dt
dv/dt =15A)
(V/ns)
(V/ns) di/dt (IOFF
di/dt
di/dt =15A)
(A/ns)
(A/ns)
180 180 12 12
160 160
159 159 10 10
140 140
145 145 GaN
GaN 10 10 GaN
GaN
V/ns

A/ns
120 120 130 130 8 8 9 9
8 8
100 100 7.4 7.4
102 102 6 6 6.75 6.75
80 80 90 90
52.7 52.7
60 60 4 4
37.4 37.4
40 40 29.5 29.5
23.7 23.7 19.8 19.8 2 21.02 1.02 SJ-MOSFET
SJ-MOSFET
20 20 0.65 0.65 0.55 0.55 0.5 0.5 0.4 0.4
SJ-MOSFET
SJ-MOSFET
0 0 0 0
0 0 5 5 10 10 15 15 20 20 0 0 5 5 10 10 15 15 20 20
(a)(Ω)
RG-EXT (a) (b) (b) (Ω)
RG-EXT
 VBias

RBoot VHV
PGND
DBoot
VCC Q1
HB

Noise Canceller
VSS
HI
High side HO
PWM1 level shift CBoot
Controller

HS

VSS Q2
VSS
VCC VCC LO
PWM2
LI
Low side
VSS level shift COM
VSS
UCC27714

VSS PGND
[1] Laszlo Balogh, “Design And Application Guide For High Speed MOSFET Gate Drive Circuits”
[2] Bob Mammano, et al., “Safety Considerations in Power Supply Design”
[3] Ernest H. Wittenbreder, Jr., “From Control to Gate”
[4] Fanny Bjoerk, et al., “How to make most beneficial use of the latest generation of super junction
technology devices”
[5] “An introduction to LLC resonant half-bridge converter”, AN2644, ST
[6] Bo Yang, et al., “LLC Resonant Converter for Front End DC/DC Conversion”
[7] Zhengyang Liu, et al., “Design and Evaluation of GaN-Based Dual-Phase Interleaved MHz
Critical Mode PFC Converter”, IEEE, 2014
[8] Wei Zhang, et al., “Gate drive design considerations for high voltage cascade GaN HEMT”,
IEEE, 2014

THANK YOU