Switching Circuits &

Logic Design
Jie-Hong Roland Jiang
江介宏

Department of Electrical Engineering

National Taiwan University

Fall 2012

§16 Sequential Circuit Design

Chomsky Hierarchy

http://www.cs.lmu.edu/~ray/notes/languagetheory/ 2
Outline
Summary of design procedure for
sequential circuits
Design example – code converter
Design of iterative circuits
Design of sequential circuits using ROMs
and PLAs

Summary of Design Procedure for

Sequential Circuits
1. Derive state table (and/or state graph)
 Given the problem statement, determine the required relationship
between the input and output sequences and derive a state table
 For many problems, it is easiest to first construct a state graph
2. Reduce state table
 State minimization by row matching or using an implication table
3. Perform state assignment
 log2m flip-flops are needed to encode m states
4. Form transition table
 Substitute the assigned flip-flop states for each state in the reduced
state table
5. Derive flip-flop input equations and output functions
 Plot next-state maps and input maps for each flip-flop to derive the
flip-flop input equations
6. Realize flip-flop input equations and output functions using
available logic gates
7. Check design
 Use signal tracing, computer simulation, or lab testing

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 Design Example – Code Converter
 Convert BCD to excess-3 code
 Add 3 to a binary-coded-decimal X Z
digit in the range 0 to 9 Input Output
(BCD) (excess-3)
 Assume serial input and output
with the least significant bit first t3 t2 t1 t0 t3 t2 t1 t0
 Reset to initial state after 0 0 0 0 0 0 1 1
receiving every 4 inputs 0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
X Code Z 0 1 0 0 0 1 1 1
(BCD) Converter (excess-3) 0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
Can the converter be realized
1 0 0 0 1 0 1 1
without delaying the output?
1 0 0 1 1 1 0 0
t0 t1 t2 t3 …
other codes - - - -
X = X(0) X(1) X(2) X(3) …
Z = Z(0) Z(1) Z(2) Z(3) … 5

Design Example – Code Converter

 Step 1: derive state table and state graph
Input Next Present
Sequence State Output (Z)
Received Present
Time (LSB first) State X=0 1 X=0 1

t0 reset A B C 1 0 A
t0 0/1 1/0
0 B D F 1 0
t1
1 C E G 0 1
B C
00 D H L 0 1 t1 0/1 1/0 0/0 1/1
01 E I M 1 0
t2
10 F J N 1 0
11 G K P 1 0
D F E G
t2 0/0 1/1 0/1 1/0 0/1 1/0 0/1 1/0
000 H A A 0 1
001 I A A 0 1
010 J A - 0 -
H L J N I M K P
t3 0/0 1/1 0/0 0/0 0/1 0/0 1/1 0/1 0/0 0/1
011 K A - 0 -
t3
100 L A - 0 -
101 M A - 1 -
110 N A - 1 -
111 P A - 1 - 6
 Design Example – Code Converter
 Step 2: Reduce state table
Input Next Present Next Present
Sequence State Output (Z) State Output (Z)
Received Present Present
Time (LSB first) State X=0 1 X=0 1 Time State X=0 1 X= 0 1
t0 reset A B C 1 0 t0 A B C 1 0
0 B D F 1 0 t1 B D E 1 0
t1
1 C E G 0 1 C E E 0 1
00 D H L 0 1 t2 D H H 0 1
01 E I M 1 0 E H M 1 0
t2
10 F J N 1 0
t3 H A A 0 1
11 G K P 1 0
M A - 1 -
000 H A A 0 1
001 I A A 0 1
The matching assumes, under
010 J A - 0 -
011 K A - 0 - X=1, the next state is A and Z=1
t3
100 L A - 0 -
101 M A - 1 - The matching imposes no
110 N A - 1 - particular condition on these
111 P A - 1 - don’t cares
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Design Example – Code Converter

 In reducing a state table by row matching,
sometimes there can be multiple incompatible
choices in matching a row
Example
Next Present
Present State Output (Z)
State X=0 1 X=0 1
Q Q S 0 1
R - - - 1
S S Q 1 -

R can be matched with either Q or S, but not both

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 Design Example – Code Converter
 Step 3: Perform state assignment
 Need 3 flip-flops for 7 states

Reduced state table Assignment map

Next Present Q1
State Output (Z)
Q2Q3 0 1
Present
Time State X=0 1 X= 0 1 00 A B
t0 A B C 1 0
t1 B D E 1 0 01 C
C E E 0 1
t2 D H H 0 1 11 H D
E H M 1 0
t3 H A A 0 1 10 M E
M A - 1 -
An even better assignment?
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Design Example – Code Converter

 Step 4: Form transition table
Next Present
State Output (Z)
Present
Transition table Time State X=0 1 X= 0 1
t0 A B C 1 0
Q1+Q2+Q3+ Z t1 B D E 1 0
C E E 0 1
Q1Q2Q3 X=0 X=1 X=0 X=1
t2 D H H 0 1
A 000 100 101 1 0 E H M 1 0
B 100 111 110 1 0 t3 H A A 0 1
M A - 1 -
C 101 110 110 0 1
D 111 011 011 0 1 Q1
Q2 Q3 0 1
E 110 011 010 1 0
00 A B
H 011 000 000 0 1
01 C
M 010 000 xxx 1 x
11 H D
- 001 xxx xxx x x
10 M E 10
 Design Example – Code Converter
 Step 5: Derive flip-flop input equations and
output functions
XQ1 XQ1
X Q1 Q2 Q3 Z D1 D2 D3 Q2Q3 00 01 11 10 Q2Q3 00 01 11 10

0 0 0 0 1 1 0 0 00 1 1 1 1 00 0 1 1 0
0 0 0 1 x x x x 01 X 1 1 X 01 X 1 1 X
0 0 1 0 1 0 0 0 11 0 0 0 0 11 0 1 1 0
0 0 1 1 0 0 0 0
10 0 0 0 X 10 0 1 1 X
0 1 0 0 1 1 1 1
0 1 0 1 0 1 1 0 D1=Q1+=Q2' D2=Q2+=Q1
0 1 1 0 1 0 1 1
0 1 1 1 0 0 1 1 XQ1 XQ1
1 0 0 0 0 1 0 1 Q2 Q3 00 01 11 10 Q2 Q3 00 01 11 10
1 0 0 1 x x x x 00 0 1 0 1 00 1 1 0 0
1 0 1 0 x x x x
01 X 0 0 X 01 X 0 1 X
1 0 1 1 1 0 0 0
1 1 0 0 0 1 1 0 11 0 1 1 0 11 0 0 1 1
1 1 0 1 1 1 1 0 10 0 1 0 X 10 1 1 0 X
1 1 1 0 0 0 1 0
1 1 1 1 1 0 1 1 D3=Q3+=Q1Q2Q3+X'Q1Q3'+XQ1'Q2' Z=X'Q3'+XQ3
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Design Example – Code Converter

 Step 6: Realize circuit

Flip-flop input functions

Q2' D Q Q1
FF1
Q1 A1 Q' Q1'
Q2 G1
Q3
Q1 D Q Q2 Output function
Q1 FF1 X
I1 A2 A5
Q3' G2 Q2'
Q' G5

D3 Q3
A3 D Q A6 G7 Z
X Q1' G3
G4
X'
Q2' FF1 Q3' G6
Q'
CLK
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 Design of Iterative Circuits
 Many of the design procedures used for sequential circuits can be
applied to the design of iterative circuits
 E.g., the design procedure used for the (sequential) serial adder of
Unit 13 can be applied to the design of the parallel adder of Unit 4
 Unilateral iterative circuit is the simplest form of an iterative
circuit
 A linear array of combinational cells with signals between cells
traveling in only one direction

X1 X2 X3 Xi Xn

a2 Cell a3 Cell a4 ai ai+1 an an+1

Cell Cell Cell
a1
1 2 3 i n

Z1 Z2 Z3 Zi Zn
Xi and Zi are the primary input and output, respectively, of cell i
ai and ai+1 resemble the present state and next state, respectively, of cell i
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Design of Iterative Circuits

Design of a Comparator
 Compare two n-bit binary numbers
X = x1x2…xn and Y = y1y2…yn
and determine if they are equal or which one is
larger if they are not equal
 Assume x1 and y1 are the most significant bits (we plan
to do the comparison from left to right)

x1 y1 x2 y2 xi yi xn yn
a1 a2 a3 ai ai+1 an an+1
Output Z1(X<Y)
Cell b2 Cell bi Cell b Cell b
b1 b3 i+1 bn n+1 Net- Z2(X=Y)
1 2 i n
work Z3(X>Y)

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Design of Iterative Circuits
Design of a Comparator
 Steps 1,2: derive and reduce state table
Si+1
Si xiyi=00 01 11 10 Z1 Z2 Z3
X=Y S0 S0 S2 S0 S1 0 1 0 Z1:X<Y
X>Y S1 S1 S1 S1 S1 0 0 1 Z2:X=Y
X<Y S2 S2 S2 S2 S2 1 0 0 Z3:X>Y

 Steps 3,4: Perform state assignment and form

transition table
ai+1bi+1
ai bi xiyi=00 01 11 10 Z1 Z2 Z3 state assignment
S0=00
0 0 00 10 00 01 0 1 0
S1=01
0 1 01 01 01 01 0 0 1
S2=10
1 0 10 10 10 10 1 0 0
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Design of Iterative Circuits

Design of a Comparator
 Steps 5,6: derive and realize cell input and
output functions
yi xi
Typical cell for comparator
xiyi xiyi
aibi 00 01 11 10 aibi 00 01 11 10 ai+1
00 0 1 0 0 00 0 0 0 1 ai
01 0 0 0 0 01 1 1 1 1 ai'
11 X X X X 11 X X X X
bi+1
10 1 1 1 1 10 0 0 0 0
bi
ai+1=ai+xi'yibi' bi+1=bi+xiyi'ai' bi'
Output circuit for comparator
an+1 an+1 an+1
an+1 Z1(X<Y)
bn+1 0 1 bn+1 0 1 bn+1 0 1
0 1 0 1 0 Z2(X=Y)
1 X 1 X 1 1 X bn+1 Z3(X>Y)

Z1=an+1 Z2=an+1'bn+1' Z3=bn+1 16

Design of Iterative Circuits
Design of a Comparator
 Sequential comparator
xi yi
ai+1 ai
ai Da Z1(X<Y)

Typical Cell Clock CK

Z2(X=Y)
bi+1 bi
bi Db Z3(X>Y)

Clock CK

t1 t2 tn time
X = x1 x2 … xn …
Y = y1 y2 … yn …
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Design of Sequential Circuits Using

ROMs and PLAs
 For a Mealy sequential circuit, the combinational
part can be realized using a ROM (PLA)
 For the circuit with m inputs, n outputs, and k state
variables, we need k D flip-flops and a ROM with m+k
inputs (2m+k words) and n+k outputs
 Similarly, for a Moore sequential circuit, the next-
state and output combinational subcircuits can be
realized using two ROMs (PLAs) or, alternatively,
a single ROM (PLA)

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 Design of Sequential Circuits Using
ROMs
 Example
 Realize the prior BCD to excess-3 code converter using a
ROM and D-FFs
State table Transition table
Present
Present Next State Output (Z) Q1+Q2+Q3+ Z
state X=0 1 X=0 1 Q1Q2Q3 X=0 X=1 X=0 X=1
A B C 1 0 A 0 0 0 001 010 1 0
B D E 1 0 B 0 0 1 011 100 1 0
C E E 0 1 C 0 1 0 100 100 0 1
D 0 1 1 101 101 0 1
D H H 0 1
E 1 0 0 101 110 1 0
E H M 1 0
H 1 0 1 000 000 0 1
H A A 0 1
M 1 1 0 000 - 1 -
M A - 1 -
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Design of Sequential Circuits Using

ROMs
 Example (cont’d)
 Realize the prior BCD to excess-3 code converter using a
ROM and D-FFs
X Q1 Q2 Q3 Z D1 D2 D3
Truth table
0 0 0 0 1 1 0 0
0 0 0 1 x x x x
X
ROM
0 0 1 0 1 0 0 0 4 input Q1
0 0 1 1 0 0 0 0
lines Q2
0 1 0 0 1 1 1 1 16 Words
0 1 0 1 0 1 1 0  4 Bits
0 1 1 0 1 0 1 1
Q3
0 1 1 1 0 0 1 1
1 0 0 0 0 1 0 1
1 0 0 1 x x x x Z D1 D2 D3
1 0 1 0 x x x x
1 0 1 1 1 0 0 0
1 1 0 0 0 1 1 0 4 output lines
1 1 0 1 1 1 1 0
1 1 1 0 0 0 1 0
1 1 1 1 1 0 1 1
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Design of Sequential Circuits Using
ROMs
 Example (cont’d)
 Realize the prior BCD to excess-3 code converter using a
ROM and D-FFs
X Z
Q1+
D1 Q1
ROM
CK
16 Words Q2+
D2 Q2
 4 Bits
CK
Q3+
D3 Q3

CK
Clock
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Design of Sequential Circuits Using

PLAs
 Example
 Realize the prior BCD to excess-3 code converter using a
PLA and D-FFs

Assignment map Transition table

Q1
Q2Q3 0 1 Q1+Q2+Q3+ Z
Q1Q2Q3 X=0 X=1 X=0 X=1
00 A B
A 000 100 101 1 0
B 100 111 110 1 0
01 C
C 101 110 110 0 1
D 111 011 011 0 1
11 H D
E 110 011 010 1 0
H 011 000 000 0 1
10 M E
M 010 000 xxx 1 x

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 Design of Sequential Circuits Using
PLAs
 Example (cont’d)
 Realize the prior BCD to excess-3 code converter using a
PLA and D-FFs
XQ1 XQ1
Q2Q3 00 01 11 10 Q2Q3 00 01 11 10
00 1 1 1 1 00 0 1 1 0
01 X 1 1 X 01 X 1 1 X
11 0 0 0 0 11 0 1 1 0
10 0 0 0 X 10 0 1 1 X

D1=Q1+=Q2' D2=Q2+=Q1
XQ1 XQ1
Q2Q3 00 01 11 10 Q2Q3 00 01 11 10
00 0 1 0 1 00 1 1 0 0
01 X 0 0 X 01 X 0 1 X
11 0 1 1 0 11 0 0 1 1
10 0 1 0 X 10 1 1 0 X

D3=Q3+=Q1Q2Q3+X'Q1Q3'+XQ1'Q2' Z=X'Q3'+XQ3 23

Design of Sequential Circuits Using

PLAs
 Example (cont’d)
 Realize the prior BCD to excess-3 code converter using a
PLA and D-FFs

PLA table
X Q1 Q2 Q3 Z D1 D2 D3
Q2' - - 0 - 0 1 0 0
Q1 - 1 - - 0 0 1 0
Q1Q2Q3 - 1 1 1 0 0 0 1
X'Q1Q3' 0 1 - 0 0 0 0 1 D1 = Q1+ = Q2'
XQ1'Q2' 1 0 0 - 0 0 0 1 D2 = Q2+ = Q1
X'Q3' 0 - - 0 1 0 0 0 D3 = Q3+ = Q1Q2Q3+X'Q1Q3'+XQ1'Q2'
XQ3 1 - - 1 1 0 0 0 Z = X'Q3'+XQ3

AND plane OR plane

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Design of Sequential Circuits Using
PALs
 Example
 A segment of a sequential PAL realizing the next-state
equation Q+ = D = A'BQ'+AB'Q

A A' B B' Q Q' Clock En

A'BQ'
D Q Q'
AB'Q
A Q'
Q' Inverting
B Tri-State
Q Output
Buffer

Programmable AND Array

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