AE 242

Aerospace Measurements
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 Number system
( N) b  d n 1d n 2 ...d i ....d1d 0  d 1d 2 ...d f ...d m
N - a number
b - radix or base of the number system
n - number of digits in integer portion
m - number of digits in fractional portion
dn-1 - most significant digit (msd)
d-m - least significant digit (lsd)
Decimal number can be obtained by multiplying di and d-f by their weights and
adding the terms. Weights are equal to bi for the terms on the left of radix point
and b-f for the terms on the right of radix point.
 Binary number system
Number with a radix two or base two
only two numbers (0 and 1) are used to represent numbers

Binary to decimal conversion

(11111)2= 1x24+ 1x23+ 1x22+ 1x21+ 1x20=(31)10

(1100.1011)2= 1x23+ 1x22+ 0x21+ 0x20+ 1x2-1+ 0x2-2+ 1x2-3+ 1x2-4 =

(12.6875)10
 Signed binary numbers
In decimal system + is used to represent positive number and - is used to
represent negative number
In binary system left most bit, most significant bit (MSB) is used to represent
the sign. 1 means negative and 0 means positive
Unsigned binary form (1000100)2 = (68)10
Signed binary form (11000100)2 = (-68)10 (eight bit number one bit reserved
for sign)
Signed binary form (01000100)2 = (68)10 (eight bit number one bit reserved
for sign)
Maximum representation in unsigned 8 bit binary number is 255
Maximum representation in signed 8 bit binary number is 127
 One’s complement representation
In a binary number, if 1 is replaced by 0 and 0 by 1, the resulting number is
one’s complement of the original number.
If one of these number is positive, then the other number will be negative with
the same magnitude. Widely used for representing the signed numbers. MSB 0
means positive number, 1 means negative number.
(+15)10 = (01111)2 and (-15)10 = (10000)2
For n bit number, maximum positive number in one’s complement number is
(2n-1 - 1) and maximum negative number is - (2n-1 - 1)
All the bits are complemented including sign bit in case of one’s complement
representation of a negative number
Signed magnitude representation of (-15)10 = (11111)2
Only the sign bit is complemented in case of signed magnitude representation
of a negative number
 Two’s complement representation
If 1 is added to one’s complement of a binary number, the resulting number is a
two’s complement. The maximum positive number is +7 and maximum negative
number is -8. 2’s complement of 2’s complement of a number is a number itself.
Two’s complement representation
If the LSB of the number is
Number 01001110
0, its 2’s complement is
One’s complement 10110001 obtained by scanning the
Add 1 1 number from LSB to MSB
Two’s complement 10110010 bit by bit and retaining the
bits as they are up to and
including the occurrence of
the first 1 and complement
all other bits
Number 00110101 If the LSB of the number is
One’s complement 11001010 1. It’s 2’s complement is
obtained by changing each
Add 1 1
0 to 1 and 1 to 0 except the
Two’s complement 11001011 least significant bit
 Binary arithmetic
Binary addition
Augend Addend Sum Carry Result
0 0 0 0 0
0 1 1 0 1
1 0 1 0 1
1 1 0 1 10

0 1 0 1
Binary number
addition + 1 1 1 1
1 0 1 0 0
 Binary arithmetic
Binary subtraction
Minuend Subtrahend Difference Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

1 0 1 1 Minuend
Binary number - 0 1 1 0 Subtrahend
subtraction 0 1 0 1 Difference
 Binary arithmetic
Binary multiplication : Similar to decimal multiplication

1 0 0 1 Multiplicand
x 1 1 0 1 Multiplier
1 0 0 1
0 0 0 0
1 0 0 1
1 0 0 1 .
1 1 1 0 1 0 1 Final Product

In digital circuit, the multiplication operation is performed by repeated

additions of all partial products to obtain full product.
 Binary arithmetic
Binary division : Similar to decimal division

1101 Quotient
Divisor 1001)1110101 Dividend
1001
1011
1001
1001
1001
0000
Answer : 1101
 2’s Complement arithmetic
Problem of subtraction can be converted in to a addition problem. This
eliminates additional circuit for subtraction.

Subtraction using 2’s complement

Binary subtraction can be performed by adding the 2’s complement of the
subtrahend to the minuend. If the final carry is generated, discard the carry
and the answer is remaining bits which is positive (minuend > subtrahend). If
the final carry is 0, the answer is negative (minuend < subtrahend) and it is in
2’s complement.

7 0111 Minuend 5 0101 Minuend

-5 1011 2’s Complement -7 1001 2’s Complement
+2 1 0 0 1 0 -2 1110
 Digital signal
Digital system only two discrete levels or values, low (0) or high (1). In case of
positive logic, high is from 3.5-5v and low is 0-1v. In case of negative logic high
is 0-1v and low is 3.5-5v. As long as voltage remains in these levels the state is
considered low or high depending on logic used. Digital system are less
susceptible to noise due to the range in logic voltages. High is also called as on
and low as off.

For TTL
Vin = 0-0.8 (low)
Vin = 2-5 (high)
Vout = 0-0.4 (low)
Vout = 2.4-5 (high)

(a) Positive logic and (b) negative logic

Digital signal
 Basic digital circuits
AND operation

Y  A  B  C  ...N
Y  ABC...N Standard symbol for AND gate

A,B,C .. N are input variables (possible values only 0 &1 ) and Y is output. Y
will be high only when all the inputs are high (positive logic)

Truth table for a 2-input AND gate

 Basic digital circuits
OR operation

Y  A  B  C  ...N
Standard symbol for OR gate

Output of OR gate is 1, if and only if one or more inputs are 1

Truth table for a 2-input OR gate

 Basic digital circuits

NOT operation

YA Standard symbol for NOT gate

NOT gate also known as inverter. It is one input (A) and one output (Y) device.
Output is complement of input. Bubble in the circuit always denotes inversion in
digital circuits.

Truth table for a NOT gate

 Derived gates

Basic gates in digital circuitry are AND, OR and NOT. Using these
three basic gates any Boolean (logic expression) can be realized.
Other type of gates obtained using basic gates are NAND, NOR, XOR,
XNOR
 NAND operations
NOT-AND operation is known as NAND, it is a AND gate followed by a NOT
gate. Complemented output of AND. Standard symbol is AND with bubble.

Y  A  B  C  ...N; Y  ABC...N

Truth table for a NAND gate

 NAND as universal gate
Using NAND gate, basic digital circuits i.e. AND, OR, NOT can be
obtained and this property makes it a universal gate.
 NOR operations
NOT-OR operation is known as NOR. It is OR gate followed by a
NOT gate. Complemented output of OR gate. Standard symbol is
OR gate with a bubble.

Y  A  B  C  ...N

Truth table for a two input NOR gate

 Using NOR as universal gate
Using NOR gate, basic digital circuits i.e. AND, OR, NOT can be
obtained and this property makes it a universal gate.
Exclusive-OR (EX-OR) operations
It is not a basic gate, and the operation can be performed using the
basic gates - AND, OR and NOT. Output is logic one when odd
number of inputs are one.
Standard notation
Y  AB Y  A B  AB

Truth table for a EX-OR gate

 Exclusive-OR (EX-OR) operations
Truth table for three inputs. Input Output
Output is logic one when odd
number of inputs are one. x y z p
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

Truth table for a EX-OR gate

Exclusive-NOR (EX-NOR) operations
It is EX-OR gate followed by a NOT

Y  A B  AB
Standard notation B
Y  A
Y  A B  AB
 Digital circuit classification
Mainly two type of classification in digital circuits. Combinational logic
circuits and Sequential logic circuits. Combinational logic circuits only
depends on the combination of the gates. Output at any time are
determined from the present combination of inputs. Where as sequential
logic circuit depends on the combination of gates and sequence of input, it
is history dependent. Sequential circuit employs storage elements in
addition to logic gates.

n Combinational m
inputs Circuit outputs
 Half adder
A logic circuit adding two bits is
called as half adder. A and B are
two inputs. S is sum and C is carry
as output.

Sum S AB
Carry C  AB
 1

0 B
1

0 A

0 S
1

0 C
 Full adder
In a full adder carry coming from low order bit is also considered. Input is An,
Bn and Cn-1 Output is Sn and Cn

Sn  A n Bn Cn 1  A n Bn Cn 1  A n Bn Cn 1  A n Bn Cn 1
C n  A n Bn  Bn C n 1  A n C n 1

SUM  ( A  B)  Cin
 N-bit adder

An adder circuit for two n bit

number consist of n full adder
circuits. It accepts two n-bit
number and produces output
of (n+1) bit binary number as
sum. Half adder may be used
to add least significant bit
 BCD-to-7-segment decoder
Digital display consisting of seven segments is commonly used and can
represent all the decimal numerals. This display device requires the logic
circuit to convert binary to decimal display in terms of a,b,..g segments.
 BCD-to-7-segment decoder
Seven segment display available as common anode (positive) or common
cathode (ground). In case of common anode, output of the decoder should be
active low i.e. negative logic. Logic is available to make display blank in case of
0, useful in leading zero in an integer, for example 005.
 One digit BCD adder
Four bit binary adder can be used to perform
additions of BCD. Simple addition will not give
correct results. If a carry is obtained in the
decimal addition then the output is to be
corrected by adding 6 in the second adder.

3+4 = 7 6+4 = 10 6+6 = 12

0100 (4) 0110 (6) 0110 (6)
0011 (3) 0100 (4) 0110 (6)
0111 1010 1100
0000 (0) 0110 (6) 0110 (6)
0111 10000 10010
Digital Circuits
Sequential Logic
 Digital circuit classification
Mainly two type of classification in digital circuits. Combinational logic
circuits and Sequential logic circuits. Combinational logic circuits only
depends on the combination of the gates. Output at any time are
determined from the present combination of inputs. Where as sequential
logic circuit depends on the combination of gates and sequence of input, it
is history dependent. Sequential circuit employs storage elements in
addition to logic gates.

n Combinational m
inputs Circuit outputs
 Sequential Logic
It is a combination of combinational digital circuits. The output depends
on the input sequence. The output depends on the past history and it is
given in some form of feed back to the input.

Inputs Outputs
Combinational
circuit
Memory
elements
 Asynchronous & Synchronous
Asynchronous: A sequential circuits whose output depends upon the
sequence of input signals. Output will be affected whenever input
changes.

Synchronous: A sequential circuits whose output can be defined from

the knowledge of timing signal. Output will be affected only during
timing signal. In general timing signal is called as clock signal.

Inputs Outputs
Combinational
circuit
Memory
Clock signal elements
 Edge triggered flip flops
Clock signal: Output changes only during the transition of the
signal. Rising edge or falling edge. After the transition output is
immune to any input changes.
 Clock signal
It is a periodic train of clock pulses, generated by system clock and
used for synchronization of the events. Or the outputs are affected only
by application of clock pulse. Output will change with 0, or 1 or rising
edge or falling edge.

Rising Edge Falling Edge

 NOR operations
NOT-OR operation is known as NOR. It is OR gate followed by a
NOT gate. Complemented output of OR gate. Standard symbol is
OR gate with a bubble.

Y  A  B  C  ...N

Truth table for a two input NOR gate

Sequential Logic - NOR

Q’

R
S
 NAND operations
NOT-AND operation is known as NAND, it is a AND gate followed by a NOT
gate. Complemented output of AND. Standard symbol is AND with bubble.

Y  A  B  C  ...N; Y  ABC...N

Truth table for a NAND gate

 Sequential Logic
Q’

R
S
Sequential Logic

X
 Bounce elimination switch
Mechanical switches have bouncing characteristics- multiple contacts. It
also means multiple change in state. Switch position decided 1 as input
in one of the terminals. At t = 0, switch is thrown from A to B. At t=0+ at
S will be Vcc and at time t1 R will be 0. In this position output is immune
to any change at R and hence even at t2, t3 etc output is maintained.
 Master-slave flip flop
Output is isolated from the input by applying out of phase clock
signal (positive level triggered)
Edge triggered flip flops
Edge triggered flip flops
Edge triggered flip flops
Edge triggered flip flops
 J-K flip-flop

Both the inputs can be high in case

of J-K flip flop

Symbol of J-K flip flop

Truth table for J-K flip flop J-K flip flop using NAND gates
 Counters
Digital counters are used for counting the number of events. n-flip flop
can count 2n number. A 3-bit counter can count from 0 to 7. Flip-flop
used are toggle type, toggles the output at falling edge.

3-bit counter using flip-flops

 Counters
The output of Q0 (LSB) changes at every falling edge of the input pulse.
The output of Q1 changes at every falling edge of Q0 and so on. The
output at  is 100 (i.e. 4). A decoder circuit is required to get the decimal
number.

Wave form of a counter

Input-output for different conditions
a) Clock
b) Input signal

c) Positive edge trig

d) Positive level trig

e) Negative edge trig

f) Master-slave J-K
QM - Master and Q -
slave, (K=1)
 Registers
A register is a group of flip-flops to store a group of bits (word). For
storing n-bit word n flip-flops are required. Data is applied at D-inputs
and output is available at Q with the rising edge of the pulse. Preset
and clear is used to set or reset the output.
 Data representation
Serial data - one bit at a time or with every clock pulse. One signal line is
sufficient. More clock pulses for a given data.
Parallel data - many bits at a time and same number of lines as number of
bits. In one clock pulse a word can be represented.

a) Serial form b) 4-bit parallel form

 Registers
Registers are classified depending upon the way input is given and
output is retrieved. Four possible mode of operations :
1) Serial-in, serial-out (SISO)
2) Serial-in, parallel-out (SIPO)
3) Parallel-in, serial-out (PISO)
4) Parallel-in, parallel-out (PIPO)
A register which can work in all the above four modes is called as
universal register
 Shift register
Master-slave flip-flops are cascaded to form shift register. The circuit
shown is a universal shift register. Generally, preset is set high to make
output 0, before data transfer. After this data is fed serial or parallel,
depending on requirements.

5 bit universal register

 Shift register
Data 10110 is at serial input and seen at parallel output after 5 clock
pulses. It is shown how the data shifts with clock pulse.

Waveform of shift registers for serial input