Connecting To A Target Board With The Avr Jtagice Mkii: Microcontrollers
Connecting To A Target Board With The Avr Jtagice Mkii: Microcontrollers
8-bit
Introduction
Microcontrollers
JTAGICE mkII is Atmel’s on-chip debugging tool for the AVR® microcontroller family.
The JTAGICE mkII supports debugging with AVR’s traditional JTAG interface and with
the debugWIRE interface. The JTAGICE mkII supports PC communication via RS-232
and USB.
JTAGICE mkII
The JTAGICE mkII is supported by AVR Studio version 4.09 and later. Quick Start
Connecting to target through the debugWIRE interface Guide
The debugWIRE interface uses only one pin, the RESET pin, for communication with
the target. To enable the debugWIRE interface on an AVR Device, the debugWIRE
Enable fuse, DWEN, must be programmed (DWEN=0).
AVR devices with debugWIRE interface are shipped with the DWEN fuse unpro-
grammed. ISP or High-Voltage Programming is required to enable debugWIRE.
Programming the fuse via ISP requires an ISP header on the target board. Using the
6-pin ISP header as shown in Figure 1 is recommended.
The JTAGICE mkII supports ISP as a general programming interface, as well as hav-
ing built in support for handling the DWEN fuse and performing the Chip Erase when
debugging. ISP is also supported by Atmel’s STK500 and AVRISP mkII. See the rele-
vant user guides for more information. All user guides are found in the AVR Studio On-
line help.
The recommended connection when the JTAGICE mkII is used for both debugWIRE
and limited ISP, is the ISP6PIN header. See Figure 1, Figure 2 on page 2 and Table 1
on page 2.
Note: When the DWEN fuse is set, the ISP interface is disabled. This is because the debug-
WIRE must have full control over the RESET pin.
1 2
MISO VCC
SCK MOSI
RESET GND
ISP6PIN
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The connection between the JTAGICE mkII probe and the 6-pin header on the target is
described in Table 1.
Once the DWEN fuse is programmed by ISP, there is only need for the GND, VTref, and
RESET lines when using the debugWIRE interface, thus the JTAGICE mkII will set lines
TCK, TDO and TDI to high impedance. The user can choose whether to disconnect the
three unused lines.
Note: Some precautions regarding the RESET line should be taken to ensure proper communi-
cation via the debugWIRE interface. Pull-up resistors on the RESET line must not be
smaller than 10KΩ (the pull-up resistor is not required for debugWIRE functionality), and
there should be no capacitive load (besides the one created by the line itself). Other logic
connected to the RESET line should be removed during debugging.
Figure 2. Connecting JTAGICE mkII probe to 6-pin ISP header using the squid cable
3
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Table 2. JTAG Connections
Pin Signal I/O Description
1 TCK Output Test Clock, clock signal from JTAGICE mkII to target
JTAG port
2 GND - Ground
3 TDO Input Test Data Output, data signal from target JTAG port to
JTAGICE mkII
4 VTref Input Target reference voltage. Also used to power level
converter inputs.
5 TMS Output Test Mode Select, mode select signal from JTAGICE
mkII to target JTAG port
6 nSRST Out-/In-put Open collector output from adapter to the target
system reset. This pin is also an input to the adapter so
that the reset initiated on the target application board
may be reported to the JTAGICE mkII
7 - - Not connected
8 nTRST NC(Output) Not connected, reserved for compatibility with other
equipment (JTAG port reset)
9 TDI Output Test Data Input, data signal from JTAGICE mkII to
target JTAG port
10 GND - Ground
Supported Devices See the JTAGICE mkII “Related devices” list on www.atmel.com/avr, or use the AVR
Studio On-line Help for the most updated device list.
Literature Requests
www.atmel.com/literature
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