Operational Amplifier

Circuits

Contents:

o Op-Amp & Op-Amp Circuits

o DC Imperfection of Op-Amp
o Practical Op-Amp & Its Output Impedance
o Common Mode & Power Supply Rejection Ratio
Op-Amp & Op-Amp Circuits

Operational Amplifier (Op-Amp)

An operational amplifier is a direct coupled amplifier with two differential inputs and a single
output. It is a versatile device used in almost all analog circuits. It provides very high open
loop gain. It is a linear active device, which consists of different stages as show in figure.

+VCC=15V

1
-
V1 3

2 O/P
+
V2

-VCC=-15V

Fig: Circuit Symbol With Power

Supply Connection

+VCC=15V

1 - O/P
Stage Stage Stage Stage
I/P
2 + 1 2 3 4

-VCC=-15V

Fig: Different Stages of Operational

Amplifier

Stages:

1. Differential Amplifier with Double Ended Output

2. Differential Amplifier with Single Ended Output
3. Level Shifting Amplifier
4. Emitter Follower Output Stage

It was originally designed for performing mathematical operation such as, summation,
subtraction, multiplication, differentiation, integration, sigh changing etc. Now-a-days it has
numerous usages e.g. scale changing analog computer operation, in instrumentation and
control system and in various phase-shift and oscillator circuits.
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Stage 1:
It is a differential amplifier with a non-inverting and an inverting input terminal. It has also
double ended output. It has very high input impedance, so it amplifies very small signals
applied differentially and rejects small and large common mode input signal.

Stage 2:
It is a medium level signal amplifier biased by constant current source. Its output is a single
ended. So that it could be conveniently cascaded to the follower circuits.

Stage 3:
It is a common emitter amplifier which is responsible for level shifting as well as
amplification

Stage 4:
It is basically emitter follower type circuit to obtain low output impedance and high current
gain. So that it could drive the external load approximately.

Technical Characteristics: Ideal Vs. Practical Op-Amp

S.N. Characteristics Practical Op-Amp (NE 741) Ideal Op-Amp

1 Voltage Gain (Open Loop) 10 5

2 Input Resistance (Rin) 106 
3 Output Resistance (Rout) 75 0
4 Input Bias Current 200 nA 0
5 Input Offset Current 20 nA 0
6 Input Offset Voltage 2mV 0
7 Unity Gain Band-Width 1 MHz 0 to 
8 Slew Rate 0.7 µV/sec 

Ideal Operational Amplifier

The Op-amp is designed to sense and amplify the difference between the voltages signal
applied at its two input terminals. The output of Op-amp is:

Vo = A(V2-V1)

Where, A = Open loop gain.

V2 = Voltage between terminal 2 and ground, and
V1 = Voltage between terminal 1 and ground.
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Characteristics of Ideal Operational Amplifier

1. The input impedance of an ideal Op-amp is V1

I1=0
-
infinity, i.e. the signal current into terminal Vout

one and two both are zero.

V2 +
I2=0

2. The output impedance of an ideal Op-amp Fig: Ideal Op-Amp with Zero Signal
Current Due to Infiniter I/P Impedance
is zero, i.e. the output voltage with respect to
ground is always equal to VO = A(V2-V1)
and is independent of the load. I1=0
-
V1 A(V2-V1)
Vo
3. It has infinite common mode rejection, i.e.

+
-
it ignores any signal common to both inputs.
+
V2 I2=0
4. Ideal Op-amp has infinite band width, i.e. it
has gain ‘A’ that remains constant down to Fig: Ideal Op-Amp with
zero frequency up to infinite frequency. Zero o/P Impedance

Virtual Short Circuit & Virtual Ground

If the Op-amp has infinite open loop gain, i.e. A→∞; and producing finite voltage at output,
then voltage between the Op-amp input terminals should be negligibly constant as shown.

Vout = A(V2 − V1 ) V1 -

Vout ∞ Vout
i.e. V2 − V1 = = A
A A
V2 +
i.e. V2 − V1 = 0
Fig: Virtual Short-Circuit &
i.e. V2 = V1 Virtual Ground

This means that, Gain (A) → ∞; the voltage V1→V2, we call this as two input terminal
‘Tracking Each Other in Potential’ or ‘Virtual Short Circuit’ exists between the two input
terminals. A virtual short circuit means that whatever voltage is at terminal two, will
automatically appear at terminal one because of infinite gain.

If terminal two is grounded, voltage at terminal one is zero volts, so we call the terminal one
as a virtual ground.
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Op-Amp Circuits

1. Inverting Configuration
In this configuration input is supplied on the inverting terminal of the op-amp, so called
inverting configuration. R2 closes loop around the op-amp, so acts as a negative feedback.

R2

i2
R1
V1 1
-
i1
Vi
A Vo

+
V2=0 2

Fig: Op-Amp Inverting Configuration

Calculation of closed loop gain:

Case I: If A → Infinite (∞);

From short circuit theory: V2 = 0 = V1 and also i1 = i2 … (i)
(Vi −V1 ) Vi
As, = i1 i.e. = i1 … (ii)
R1 R1

Again, V1 = i2 R 2 − Vo = 0
V
Or, Vo = V1 − i2 R 2 = −i1 R 2 = − R i . R 2
1

Vo R2
 Closed loop gain (A) = =−
Vi R1

Case II: If A → Finite;

Vo
Then, Vo = A(V2 − V1 ) i. e. V1 = − … (i) (V2 = 0, but V1  V2)
A
V
(Vi −V1 ) Vi + Ao
and also, i1 = i2 = = … ii
R1 R1
V
Vo Vi + Ao Vo R Vo R 2
Again Vo = V1 − i2 R 2 = V1 − i1 R 2 = −
A
− R1
R2 = −
A
− Vi R 2 − A R1
1

1 1 R2 R
i.e. Vo (1 + +
A A R1
) = −Vi R2
1
R R
Vo − 2 R1
− 2 R1
Gain: = 1 1R = 1 R
29

Vi (1+A+AR2 ) 1+A(1+R2 )
1 1
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2. Non Inverting Configuration
Here, input is fed into the non-inverting terminal-2 of an op-amp, so called non-inverting
configuration.

R2

i2
R1
V1 1
-
i1
A Vo

+
V2 2
Vi

Fig: Op-Amp Non Inverting Configuration

Calculation of closed loop gain:

Case I: If A → Infinite (∞);

From short circuit theory: V1 = Vi and also, i1 = i2 … (i)
(0−V1 ) Vi
As, = i1 i.e. i1 = − = i1 … (ii)
R1 R1

Again, V1 = i2 R 2 − Vo = 0
V
Or, Vo = V1 − i2 R 2 = Vi − i1 R 2 = Vi + R i . R 2
1

R2
Or, Vo = Vi (1 + )
R1
Vo R2
 Closed loop gain (A) = =1+
Vi R1

Case II: If A → Finite;

Vo Vo
Then, Vo = A(V2 − V1 ) = A(Vi − V1 ) i. e. Vi − V1 = i. e. V1 = Vi − …(i)
A A
V
(0−V1 ) −Vi + Ao
and also, i1 = i2 = = … (ii)
R1 R1
V
Vo Vi − Ao Vo Vo R 2 R
Again Vo = V1 − i2 R 2 = V1 − i1 R 2 = Vi −
A
+ R1
R 2 = Vi −
A
− A R1
+ V𝑖 R 2
1

1 1 R2 R
i.e. Vo (1 + +
A A R1
) = Vi (1 + R2)
1
R R
Vo − 2 R1
(1+ 2 )
R1
Gain: = =
30

1 1R 1 R
Vi (1+A+AR2 ) 1+A(1+R2 )
1 1
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Design an operational amplifier having:
a) Vo = -10Vi and
b) Vo = 5Vi

Solution:

a) When Vo = -10Vi
i.e. Gain (A) = Vo/Vi = -10
Since, it has negative voltage gain, so using a inverting configuration of op-amp, in
which, Vo = -(R2/R1)Vi
i.e. A = Vo/Vi = -R2/R1
i.e. -10 = -R2/R1
i.e. R2 = 10R1

Let; R1 = 10K, then R2 = 1010 = 100K

Now, the resulting circuit of the op-amp looks like as follow in fig(a).

40K
100K

i2
i2
10K V1 1
10K -
V1 1
-
i1
i1 A Vo
Vi
A Vo
+
V2 2
Vi
+
V2=0 2

Fig(a): Op-Amp Inverting Configuration Fig(b): Op-Amp Non Inverting Configuration

b) When Vo = 5Vi
i.e. Gain (A) = Vo/Vi = 5
Since, it has positive voltage gain, so using a non-inverting configuration of op-amp,
in which, Vo = (1+R2/R1)Vi
i.e. A = Vo/Vi = 1+R2/R1 = (R1+R2)/R1
i.e. 5 = (R1+R2)/R1
i.e. 5R1 – R1 = R2
i.e. R2 = 4R1

Let; R1 = 10K, then R2 = 410 = 40K

Now, the resulting circuit of the op-amp looks like as in above fig(b).
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 3. The Voltage Follower
The non-inverting configuration has infinite input resistance. It enables using this circuit
as a buffer amplifier to connect a source with high impedance to low impedance. Buffer
amplifier has voltage gain of one.

Vi = V1 Vi = V1
- -
Vo
A=1 A=1
V2 V2
Ro Vo = Vi
+ +
Vi Ri

Fig: Basic Connection of Vi Fig: Circuit Connection of

Voltage Follower Voltage Follower

4. Integrator
It consists of a capacitor C in the feedback path of the inverting configuration.

Vc(t)

I2(t)
R1 1
Vi(t) -
V1
I1(t)
Vo(t)

+
V2 = 0 2

Fig: Op-amp as an Integrator

From figure:
ϑi(t) −ϑ1 ϑi(t) −0 ϑi(t) −ϑ1 ϑi(t)
i1 = = ; (V2 = 0 = V1) i.e. i1 = = = i2 . …(i)
R1 R1 R1 R1

Again from loop equation:

V1 − ϑc(t) − ϑo(t) = 0
1 t
i.e. V1 − ∫0 i2(t) dt = ϑo(t)
C
1 t
i.e. 0 − ∫0 i2(t) dt = ϑo(t)
C
1 t
i.e. ϑo(t) = − ∫0 i2(t) dt
C
1 t ϑi(t)
= − ∫0 dt { From … (i)}
C R1
32

1 t
i.e. ϑo(t) = − ∫ ϑ dt
R1 C 0 i(t)
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 5. Differentiator
In this case, a capacitor C is connected in the inverting terminal -1 of the inverting
configuration of an operational amplifier. In which V2 = 0 = V1.

I2(t)
Vc(t)
Vi(t) -
V1
I1(t)
Vo(t)

+
V2 = 0

Fig: Op-amp as a Differentiator

From figure:
ϑi(t) − ϑc(t) − V1 = 0 i.e. ϑi(t) = ϑc(t) … (i) (V1 = 0)
dϑc(t) dϑi(t)
Since, i1(t) = C =C = i2(t) … (ii)
dt dt

Again from loop equation:

V1 − Ri2(t) − ϑo(t) = 0
dϑi(t)
i.e. ϑo(t) = −Ri2(t) = −RC
dt
dϑi(t)
i.e. ϑo(t) = −RC
dt

6. Difference Amplifier
Op-amp can be used in subtracting mode. The alongside figure shows a circuit that can
provide the difference between two inputs.

Rf

i2

R1 1
Vi1 -
V1
i1
A=1 Vo

V2
Vi2 +
2
i2 R3
33

Fig: Op-amp as a Substracter

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 R3
From figure, we have: V2 = V = V1 … (i)
R3 +R2 i2
Vi1 −V1
As; Vi1 − i1 R1 − V1 = 0; i.e. i1 = = i2 … (ii)
R1

Again from loop equation:

V1 − i2 R f − V0 = 0
R3 V −V
i.e. V0 = V1 − i2 R f = V − i1 1 R f
R3 +R2 i2 R1
R3 Vi1 V1
= V − R + Rf
R3 +R2 i2 R1 f R1
R3 Rf R R
= V − Vi1 + f 3 Vi2
R +R i2
3 2 R 1R R +R 1 3 2

Let: Rf/R1 = R3/R2; then:

R3 /R2 Rf Rf R3 /R2
V0 = Vi2 − Vi1 + V
R3 /R2 +R2 R1 R1 R3 /R2 +R2 i2
Rf /R1 Rf Rf Rf /R1
= V − V + V
Rf /R1 +R2 i2 R1 i1 R1 Rf /R1 +R2 i2
Rf Rf Rf Rf
= V − V + V
R1 +Rf i2 R1 i1 R1 R1 +Rf i2
Rf Rf Rf Rf R1 +Rf Rf Rf Rf
= Vi2 (1 + )− Vi1 = Vi2 ( )− Vi1 = Vi2 − V
R1 +Rf R1 R1 R1 +Rf R1 R1 R1 R1 i1
Rf
 V0 = (Vi2 − Vi1 )
R1

7. Comparator
Comparators are similar to Op-amp except that open loop gain is made longer by
including positive feedback in the internal circuit. Due to very large open loop gain,
output voltage essentially provides digital operation.

Vin -
There are only two possible outputs, Vo
they are Vmax and Vmin. VR +

Fig: Comparator Circuit

When, Vin > VR Symbol
then Vo = Vmax Vo
Vmax
When, Vin < VR VR
Vin

then Vo = Vmin
Vmin
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Fig: Comparator Characteristics

Curve
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Examples

1. If 𝛝𝐢(𝐭) = 5sin(t), R = 100K, C = V1(t)=50cost

1µF, then 𝛝𝐨(𝐭) = ?

t
Solution:
1 t
V2(t)=5 -
We have: ϑo(t) = − ∫ ϑ dt 0
R1 C 0 i(t)
1 t t
ϑo(t) = − ∫ 5sin(t)dt
100×103 ×1×10−6 0
Vo(t)=50cost-50 =
1 t
=− . 5cos(t)|
100×103 ×1×10−6 0
1 t
=− (5cost − 1)
100×103 ×1×10−6

ϑo(t) = 50cost − 50 Fig: The Output of Integrator

When Input is Sinusoidal

2. If Vi = 2V, RC = 1, then V0 = ? Vi(t)=2

Solution:
t
1 t Vo(t)=2t
We have: ϑo(t) = − ∫ ϑ dt
R1 C 0 i(t)
1 t
ϑo(t) = − ∫0 2dt Slope = -2 t
1
t
= −2t|
0 Fig: The Output of Integrator
Subjected to Step Input
ϑo(t) = −2t

8. Weighted Summer

It consists of a summing of currents i1 R Rf

V1
through the resistors at each branch 1

supplied with corresponding input i2 R i

V2 2 -
voltages. The summed current is fed to V
Vo
i3 R
the inverting terminal of an op-amp, to V3 3
which the output voltage V0, is feed +
backed with resistor Rf as shown in figure
35

alongside.
Fig: Resistor Summing Network
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 V1 −V V1 −0 V1
Here; i1 = = =
R1 R1 R1

V2 V3
Similarly, i2 = ; i3 = and so on.
R2 R3
V1 V2 V3 Vn
At a junction; i = i1 + i2 + i3 + …. + in i.e. i = + + +⋯ …(i)
R1 R2 R3 Rn

Again from loop equation:

V1 − iR f − V0 = 0
V1 V2 V3 Vn Rf Rf Rf Rf
i.e. V0 = −iR f = −( + + +⋯ )R f = V + V + V +⋯ Vn
R1 R2 R3 Rn R1 1 R2 2 R3 3 Rn

Rf Rf Rf
Where, , … are known as the weights of V1, V2, …Vn respectively. Since, the output
R1 R2 R3
voltage is the sum of all weights, so it is called by weighted summer.

Examples
1. Realize a circuit to obtain, Vo = -2V1+3V2+4V3. Use minimum value of R as 10K.

Solution:
Here; Vo = -2V1+3V2+4V3 = -{2V1+3(-V2)+4(-V3)} …(i)
Rf Rf Rf Rf
Comparing (i) with the equation: V0 = −( V1 + V2 + V3 + ⋯ V ); We get:
R1 R2 R3 Rn n
Rf Rf Rf Rf Rf Rf
= 2; i.e. = R1 ; = 3; i.e. = R 2 and = 4; i.e. = R3
R1 2 R2 3 R3 4

Here; R3<R2<R1; So, choosing R3 = 10K. Then: Rf = 4R3 = 410 = 40K, R1 = Rf/2 =
40/2 = 20K, R2 = Rf/3 = 40/3 = 13.33K. Now, the realization of the circuit is as follow.
10K

i1 R1 = 20K Rf = 40K
10K V1
-
V2 i
i2 R2 = 13.3K i
-
V
+ Vo
i3 R2 = 10K
10K

+
10K
V3 -

Fig: Realization of the Resistor Summing Network:

36

When Vo = -2V1+3V2+4V3
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DC Imperfection of Op-Amp
Output Offset Voltage
The actual value of output voltage when the inputs are zero is called the output offset voltage.
It is the output level about which the signal variation occurs. If an op-amp is used only for
an ac signal, it can be capacitor coupled to block the dc component represented by offset. On
the other hand, at low level and low frequency signal, the offset voltage creates the error, so
it has to be reduced.

Output offset voltages are the result of two distinct input phenomenons, they are;
a) Input bias current and
b) Input offset voltage.

 Input Bias Current

In the first-stage of op-amp i.e. differential stage, some dc bias current must flow when
the transistor is properly biased. This current is called input bias current. Although, small
input bias current flowing through the external resistor in an amplifier circuit produces a
dc input voltage that in terms create an outpur offset voltage.

R2

IB1 R1 -

+ IB1 Vo (IB)
s
+
IB2
IB2

Fig(a): Input Bias Currents Fig(b): Output Offset Voltage

due to Input Bias Current
IB1 & IB2

The input bias currents through two terminals are represented by two current sources IB1
and IB2 connected on two input terminals as shown below.

Generally, average input bias current is given by IB = (IB1 +IB2)/2 and the difference is
called input offset current, i.e. Iios = | IB1 - IB2|.

o Output offset voltage for closed loop configuration due to input bias current:

Referring fig (b)

Vos(IB) = R2IB1 … (i)

So, if R2  Vos Then: Gain (-R2/R1) 

if R2  Gain  Then: Vos 
37

Where Vos = Output offset voltage.

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o Reduction of output offset voltage due to input bias current:

 This method consists of introducing a resistance R3 in series with the non-inverting
input load as shown below.
R2

R2

R1 - R1
Vi1 = IB2R1 -
Vo
IB1 Vo

R3 + R3
Vi2 = IB2R3 +
IB2
Vi2 = -IB2R3

Fig: Reduction of Output Offset Voltage due to Input Bias Current by Adding
Series Resistance R3 With Non-Inverting Input Load

 Total output offset voltage (Vos) = Offset due to Vi1 + offset due to Vi2
i.e. Vos = Vi1(-R2/R1) + Vi2(1+R2/R1) = -IB1R1(-R2/R1) + (-IB2R3)(1+R2/R1)

Putting Vos = 0 and assuming IB1 = IB2 = IB, then:

0 = IBR2 - IBR3(1+R2/R1)
i.e. R3 = R2/(1+R2/R1) = R1R2/(R1+R2) = R1 // R2
 R3 = R1 // R2

Where R3 is called a compensation resistor.

Examples
1. Calculate the output offset voltage due to 300nA of bias current. How can you reduce
this offset voltage?
10K

100K

10K - 10K -
Vo
Vo

+ 9.09K +

Fig (a) Fig (b)

Solution:
Given; IB = 300 nA, i.e. IB1 = IB = 300 nA; R1 = 10K and R2 = 100K
a) VOS(IB) = R2.IB1 = 10010330010-9 = 0.3 mV
b) In order to reduce this offset voltage, an external resistance R3 should be connected
in series at terminal-2, for which R3 = R1//R2 = 10K//100K = 9.09K
38

Now, the resulting circuit will be as give in above fig (b).

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 Note: We have, R3 = R1//R2 (only for IB = IB1 = IB2). If IB1  IB2; it should be noted that
inserting R3 in terminal-2 cannot nullify the offset voltage but in this case output offset
voltage is given by: VOS = IOS.R2 = |IB1 – IB2|.R2

2. Given IB = 80nA, IOS = 10nA, R1 = 10K and R2 = 100K (Note: IB2>IB1)

Find:
a) Optimum value of compensation resistor.
b) Offset voltage with compensation resistor.
c) Offset voltage without compensation resistor.

Solution:
Since, IB = (IB1 + IB2)/2 = IB1 + IB2 = 802 = 160 … (i)
And IOS = |IB1 - IB2| = | IB2 - IB1| = 10 … (ii)
Solving I and II, we get: IB1 = 75nA and IB2 = 85nA

Now,
a) R3 = R1//R2 = 10K//100K = 9.09K
b) VOS = IOS.R2 = 1010-9100103 = 1mV
c) VOS(without R3) = IB1.R2 = 7510-9100103 = 7.5mV.

 Input Offset Voltage

Another input phenomenon that contributes to output offset voltage as an internally

generated potential difference that exists because of imperfect matching of the input
transistors. This internally generated potential difference is called input offset voltage. In
another words, input offset voltage can be defined as the voltage required to supply
through the input to make the output offset voltage zero.

-
1 3
+
2
Vios
Offset Free
Input Offset Op-Amp
Voltage

Fig: Demonstration of
Input Offset Voltage

The effect of this voltage can be analyzed by modeling op-amp as shown in above figure.
It consists of a dc source of value Vios placed in series with the input load of an offset free
39

op-amp.
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o Output offset voltage of a closed loop op-amp configuration due to input offset
voltage.

Here; R2
i1 = i2 and V1 = Vios
i2
i1 = -V1/R1 = -Vios/R1 R1
-
Vos
Again; i1

Offset Free
Vos = V1 – i2R2 + Op-Amp

= Vios – i1R2 Vios

= Vios + Vios.(R2/R1) Fig: Demonstration of Output Offset Voltage of Closed

Loop Op-Amp Configuration Due to Input Offset Voltage
Vos = Vios{1+(R2/R1)}

Hence; total offset voltage is given by:

Vtos = Offset voltage due to i/p bias current + Offset voltage due to i/p offset voltage
i.e. Vtos = IB1.R2 + Vios{1+(R2/R1)}

This is the case when compensation resistor is not used. When compensation resistor R3
is used, then: Vtos = IOS.R2 + Vios{1+(R2/R1)}; Where, R3 = R1/R2

Examples:

1. Given: R1 = 15K, R2 = 75K, IB = 100nA, IOs = 20nA, Vios = 0.5mV. Find Vtos when;
a) Compensation resistor is used under the assumption of i) IB1>IB2, ii) IB2>IB1.
b) Compensating resistor is not used as i) IB1>IB2, ii) IB2>IB1.
c) Find R3 ie; compensating resistor.

Solution:

a) When R3 is used:

Vos1 = Ios.R2 = 2010-975103 = 1.5 mV

Vos2 = Ios.{1+(R2/R1)} = 0.5(1+75/15) = 3 mV
Vtos = Vos1 + Vos2 = 3 + 1.5 = 4.5 mV (for both case i and ii)

b) When R3 is not used:

i) If IB1>IB2
Then, Ios = |IB1 - IB2| = 20 nA
i.e. IB1 – IB2 = 20nA …(i) and IB = (IB1+IB2)/2, i.e. IB1+IB2 = 200nA … (ii)
Solving i and ii, we get: IB1 = 110nA and IB2 = 90nA
40

Now; Vtos = Vos1 + Vos2

= IB1.R2 + 3mV
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= 11010-975103 + 3mV = 11.25 mV

 ii) If IB1< IB2
Then, from similar calculation we get: IB1 = 90nA and IB2 = 110nA

Vtos = Vos1 + Vos2

= IB1.R2 + 3mV
= 9010-975103 + 3mV = 9.75 mV

c) Compensation resistor, R3 = R1 // R2 = 75K // 15K = 12.5K

Equivalent Model of Practical Op-Amp

Icm
2Ricm
2

RO VO
Vid iid Rid
+
-

AVd
i

Icm 2Ricm
2

Fig(a): Equivalent Model

of Practical Op-Amp

R2 R2

Icm
2Ricm
2
R1 R1

V1 -
RO VO RO VO = AVid
iid Rid Vid Rid
+

+
-

Loop I
Vin AVd Vin AVid
+
iin iin

Icm 2Ricm
2
41

Fig(b): Before Considering Fig(c): After Considering

Assumption Assumption
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Legends:

Ricm = Common mode resistance between terminal and ground

icm = Common mode current
Rid = Differential resistance between two terminal.
iid = Differential current.
A = Open loop gain of op-amp
Ro = Output resistance of Op-amp

For input resistance of non-inverting configuration: R1 << Ricm

i.e. Ro  0 and 2Ricm >> Rid

Therefore, input impedance of non inverting configuration is very high while that of inverting
configuration is very low.
R1
Referring fig: c) V1 = × VO
R1 +R2

R1
If = ; then: V1 = βVo …(i)
R1 +R2

From loop I
Vin − iin R id − V1 = 0 i.e. Vin = Vid + V1

Now;
Rin = Input terminal resistance = input voltage/input current

i.e. Rin = Vin/iin

Vid +V1 Vid +V1 Vid +βVo Vid +βAVid (1+Aβ)Vid (1+Aβ)
i.e. R in = = = = = =
iid Vid /Rid Vid /Rid Vid /Rid Vid Rid Rid

(1+Aβ)
i.e. R in =
Rid

Output Impedance of Closed Loop Op-Amp

To find output resistance, input sources are made short and grounded. Applying a test voltage
at output resistance, Rout = Vx/Ix.

Let us assume, Ricm  and Rid >> R1 i.e. Rid//R1 = R1

Now;
R2
V1 = × Vx = β Vx i.e. V1 = β Vx …(i)
R1 +R2
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At junction ‘O’ ix = i1 + i2 …(ii)

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But:
Vx Vx
i1 = = and
R1 //Rid +R2 R1 +R2

Vx −AVd Vx −A(0−V1 ) Vx +AV1 Vx +AβVx Vx

i2 = = = = = (1 + Aβ)
Ro Ro Ro Ro Ro

R2

R1 Vx
- i1
V1
RO R2
Vid i2 ix
Rid
+
-

Loop I o
Vin AVid Vx
+ R1 Rid

Fig(c): Output Impedance of

a Colsed Loop Op-Amp

 ix = i1 + i2
Vx Vx 1 (1+Aβ)
i.e. ix = + (1 + Aβ) = Vx { + }
R1 +R2 Ro R1 +R2 Ro
ix 1 (1+Aβ)
i.e. = +
Vx R1 +R2 Ro
1 1 1
i.e. = +
Rout R1 +R2 Ro /(1+Aβ)

i.e. R out = (R1 + R 2 )//{R o /(1 + Aβ)}

If gain is high then: Ro/(1+AB) becomes low.

1
i.e. ≫ (R1 + R 2 )
Ro /(1+Aβ)
43

So, for parallel case; R out = R o /(1 + Aβ)

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Common Mode Rejection Ratio (CMRR)

The operational amplifier basically operates to amplify the difference between the signals
applied across its two terminals i.e. it is intended to operate in differential mode. So, when
input terminals are tied together, the output voltage should be ideally zero but due to some
imperfections within an actual op-amp, some common mode voltage will appear at the
output. The ratio of output common mode voltage to input common mode voltage is called
common mode voltage gain.
Vocm
i.e. ACM =
Vicm

Now;
CMRR is defined as the ration of differential gain Ad to common mode gain Acm.

Ad
i.e. CMRR =
Acm

Since, Ad >> Acm, CMRR is very high, so it is expressed in dB.

Ad
i.e. CMRR = 20 log( )dB
Acm

Typically CMRR ranges from 80dB to 100dB. The op-amps with high CMRR will be least
affected by noise signals, that are common to both terminals because of higher ability to
reject the common mode signals.

 Output voltage in terms of CMRR

Since, Output voltage = Output voltage due to differential mode + Output voltage due
to common mode

Acm Vicm 1 Vicm

i.e. Vo = Ad Vd (1 + . ) = Ad Vd (1 + . )
Ad Vd CMRR Vd

Where;

Ad = Differential Gain
Vd = Differential Voltage
Acm = Common mode gain
Vicm = Common mode input voltage

Example

The input terminals of an op-amp are connected to voltage signals of strength 745 µV and
740 µV respectively. The gain of the op-amp in differential mode is 5105 and its CMRR is
44

80 dB. Calculate the output voltage and percentage error due to common mode.
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Solution

Vd = |V2 – V1| = |740-745| = 510-6 V

Ad = 5105 and CMRR = 80dB

1 Vicm 1 Vicm
As: . Vo = Ad Vd (1 + . ) = 5105 × 510−6 (1 + . )
CMRR Vd CMRR 510−6

Where, Vicm = Vcm = (740+745)/2 = 742.5 µV and

(CMRR)dB = 20log(CMRR)
i.e. 80 = 20log(CMRR)
i.e. CMRR = 104

1 742.510−6
 Vo = 5105 × 510−6 (1 + . ) = 2.537V
104 510−6

Output Voltage due to common mode

%-age error = × 100
Total Output Voltage
Vcm ×Acm
= × 100
2.537
d A
Vcm ×CMRR
= × 100
2.537
5105
742.5×
104
= × 100 = 1.46%
2.537

Power Supply Rejection Ratio (PSRR)

PSRR is defined as the ration of change in output voltage to change in power supply.

∆VO
i.e. PSRR =
∆VS

PSRR is considered as the measure of ability of op-amp to ignore changes in power supply.
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