BIRA With Optimal Repair Rate Using Fault-Free Memory Region For Area Reduction
BIRA With Optimal Repair Rate Using Fault-Free Memory Region For Area Reduction
BIRA With Optimal Repair Rate Using Fault-Free Memory Region For Area Reduction
Abstract— As manufacturing process technology scales down, be performed in two ways, which are to use an automatic test
memory capacity and density continue to grow. As the number of equipment (ATE) and to use built-in logic. The ATE based
memory cells per area increases, so does the possibility of having method may not require additional on-chip logic, however,
defects in the memory cells. Therefore, built-in redundancy
analysis (BIRA) is widely used for memory test and repair. it needs test pins for the ATE and the bandwidth is limited.
BIRA repairs faulty cells by replacing them with healthy spare Unlike the ATE based approach, with built-in logic, memory
cells. To perform BIRA, the faulty memory cell information is can carry out self-test and also perform self-repair. A built-in
required and is collected via a memory test. By using the faulty self-test (BIST) finds the locations of defective memory cells
cell information, BIRA can analyze and perform the repair by and built-in redundancy analysis (BIRA) determines the repair
assigning spares to defective cells. However, it requires extra
hardware to store the faulty cell information. Most conventional solution by analyzing the memory defect location information.
BIRA approaches utilize content-addressable memories (CAMs) Through BIST and BIRA, the memory can be tested and
to store faulty cell information. Owing to the CAMs’ fast access repaired without depending on ATE and this is referred as
speed, the repair time can be reduced. However, CAMs are the built-in self-repair (BISR).
critical source of an area overhead for BIRA, and a CAM could The role of BIRA is determining how to replace the faulty
be shared across multiple memory banks. The shared structure
limits simultaneous repair operations for the banks, and when cells with spare ones. To improve the repair rate, most RA
the CAM is faulty, the conventional CAM-based BIRA cannot algorithms for planar memory use a 2-D spare architecture
be performed. This paper proposes a new BIRA method, which which consists of spare rows and spare columns. By using this
does not require extra memory and instead utilizes a fault-free architecture, RA algorithms can achieve a higher repair rate
memory region to store the faulty cell information. Because than an 1-D spare architecture. Due to its complexity, finding
extra memory is not required in the proposed BIRA method,
the area overhead is decreased. The proposed hierarchical repair repair solutions to allocate redundancy is an NP-complete
algorithm thus helps to reduce the analysis time, while achieving problem in 2-D spare architecture.
optimal normalized repair rate. There have been a number of studies to find efficient
Index Terms— Area overhead, built-in redundancy analy- repair solutions using RA. Repair-most (RM) [2] is one
sis (BIRA), built-in self-repair (BISR), built-in self-test (BIST). of the simplest RA algorithms. RM counts the number of
I. I NTRODUCTION faults in each memory line using bitmaps. Using the fault
information in bitmaps, RM then assigns spare lines to each
W ITH the advancement of manufacturing technology,
memory capacity and density have steadily increased.
This advancement also increases the possibility of defects in
faulty line in descending order based on the number of
faults. RM is an intuitive approach, yet this RA algorithm
the memory, making the yield problem more critical. Hence, does not perform an exhaustive search, and its repair rate
memory repair is essential to improve the yield. For memory would therefore not be optimal. Local repair-most (LRM) [3]
repair, redundancy is commonly used in the form of spare reduces the size of the bitmap as compared to that of RM.
cells. Spare cells are included to replace defective ones in LRM collects partial faulty cell information instead of using
the memory array. Redundancy analysis (RA) determines how whole memory information. This helps to alleviate the area
to assign spares for faulty memory cells. After testing the overhead for storing faulty cell information. Essential spare
memory to find defects, RA is performed. Memory test can pivoting (ESP) [3] utilizes repair registers instead of bitmaps
to store faulty cell information. ESP predefines a threshold
Manuscript received April 1, 2017; revised July 13, 2017 and August 14, value and repairs the faulty lines having more faults than the
2017; accepted August 31, 2017. Date of publication September 26,
2017; date of current version November 22, 2017. This research was threshold value. The amount of faulty cell information stored
supported by Basic Science Research Program through the National is less than that for a bitmap, hence, the area overhead for ESP
Research Foundation of Korea (NRF) funded by the Ministry of Education is reduced. To reduce hardware overhead, a BIRA using spare
(NRF-2015R1D1A1A01058856) and in part by the MOTIE (Ministry of
Trade, Industry & Energy (10080594) and KSRC (Korea Semiconductor mapping registers [25] is proposed. This approach uses the
Research Consortium) support program for the development of the future concept of ‘must-repair’ and reduces the number of registers
semiconductor device. This paper was recommended by Associate Editor for faulty cell information. Another approach to enhance the
D. Zito. (Corresponding author: Joon-Sung Yang.)
The authors are with the Department of Semiconductor and Display ESP algorithm is the Memory BISR (MBISR) scheme based
Engineering, Sungkyunkwan University, Suwon 16419, South Korea (e-mail: on configurable spares [29]. This method suggests configurable
js.yang@skku.edu). spare remapping. It remaps either a faulty row or column to
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. the same spare element so that a spare utilization efficiency
Digital Object Identifier 10.1109/TCSI.2017.2750702 increases. Flexible spare architecture helps to improve the RA
1549-8328 © 2017 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
OH et al.: BIRA WITH OPTIMAL REPAIR RATE USING FAULT-FREE MEMORY REGION FOR AREA REDUCTION 3161
repair rate. However, since LRM, ESP, mapping register based is proposed in [22] and [24]. In the first phase, a parallel
BIRA and configurable spares based MBISR do not store test-repair scheme is used to search for faulty memory cells.
faults information for all the faults in the memory, the optimal In the second phase, a serial test-repair is performed for faulty
repair rate is not guaranteed. To enhance the repair rate, memories. To achieve the optimal repair rate, an exhaustive
a block-based redundancy architecture is proposed [31]. This search is performed. A 3D BISR scheme sharing redundancies
architecture divides traditional spare rows/columns architec- and parallelizing the BISR for each layer has been proposed
ture into blocks. Since spare row/column blocks can replace in [9]. A BIRA approach sharing redundancies for pre-bond
faulty cells anywhere within a bank, the repair rate increases. and post-bond repair with a new fuse architecture was intro-
Reconfigurable BISR (ReBISR) [27] is another scheme with duced in [10].
a suboptimal repair rate. ReBISR can be shared by multiple The latest RA algorithms that can achieve the optimal repair
RAMs of different sizes on a system-on chip (SoC). Since each rate are based on a binary search tree. BRANCH analyzer [4]
RAM does not require an individual BISR, the area overhead and BIRA using AMT [5] also deploy the binary search
of the BISR for SoC can be reduced. tree to select a repair solution from solution candidates. The
A binary search based exhaustive search BIRA is introduced binary search based algorithms can perform an exhaustive
to obtain the optimal repair rate [26]. In this method, a binary search. However, BRANCH and BIRA using AMT require
search tree is used to check every possible repair candidates. extra storage, such as CAMs, to store faulty cell information.
By checking non-orthogonal faulty cells before orthogonal The CAM area becomes a significant portion of the entire
faulty cells, this approach reduces an area and delay overhead. area overhead of BIRA. Unlike an RA procedure using an
High Repair-Efficiency BISR (HRE-BISR) [21] is another automatic test equipment (ATE), BIRA needs to be inserted
heuristic based algorithm that also does not ensure the optimal in a chip. Hardware area overhead reduction is consequently
repair rate. Compared to other heuristic algorithms such as one of the main focuses in BIRA research.
LRM or ESP, however, HRE-BISR achieves a higher repair In this paper, we propose a novel BIRA architecture reduc-
rate by reusing the local bitmap as spare bits. In test mode, ing the area overhead as well as achieving the optimal repair
the bitmap is used to store faulty cell information, while in rate (it extends and improves the preliminary results in [1]).
normal mode it is used as spare memory. Comprehensive real- This approach utilizes a fault-free memory region of a memory
time exhaustive search test and analysis (CRESTA) is proposed array to store the faulty cell information. To achieve the
in [28]. It stores the faulty cell information in content- optimal repair rate and fast analysis speed, the proposed BIRA
addressable memories (CAMs) and has as many sub-analyzers deploys a hierarchical repair scheme.
as solution candidates to find a repair solution in a single The remainder of this paper is organized as follows. Sec. II
test. However, the CAM size is a significant area overhead. explains a background of RA. Sec. III explains the details of
To reduce the area overhead, BIRA with the optimal repair the proposed method. Experimental results are given in Sec. IV
rate for word-oriented memories [30] is proposed. This scheme and Sec. V concludes the paper.
allows for a smaller CAM size than CRESTA by dividing the
BIRA process into two analysis phases, must-repair analysis II. BACKGROUND
and final analysis. BRANCH analyzer [4] also requires CAMs The purpose of BIRA is to determine how the spare lines are
to store the faulty cell information. However, it only stores to be assigned to faulty lines. In a planar memory structure,
the fault information which is essential for finding a repair spare rows and columns are used for repair after manufac-
solution. BIRA using AMT [5] uses spare memory (i.e., spare turing. In [12], the definition of must-repair faulty lines is
rows) as an address-mapping table (AMT). The AMT maps given using Rs and Cs denoting the number of spare rows and
the shortened fault addresses in the CAMs to full addresses columns, respectively. If there are more faults in a row (col-
in the spare memory. Therefore, BIRA using AMT can work umn) than Cs (Rs), the faulty line is identified as a must-repair
with smaller size CAMs than BRANCH analyzer. BRANCH faulty row (column). The must-repair faulty row (column)
analyzer and BIRA using AMT achieve the optimal repair must be replaced by a spare row (column) since there is an
rate via exhaustive search. The two approaches build repair insufficient number of spare columns (rows) to repair the must-
solution candidates based on the stored faulty cell information. repair faulty row (column). Fig. 1 illustrates an example of a
After candidates building, if a candidate can cover all the must-repair faulty column. There are 8 columns (C0 ∼ C7),
faults in the memory, BIRA selects that candidate as the repair 8 rows (R0 ∼ R7) and two spare columns and rows. In C2,
solution. BIRA using RAM [6] uses a healthy bank as a bitmap there are three faults, while there are only two spare rows
of the other bank under test. Another BIRA approach using available. Since there is no way to repair the faults in C2 with
various types of spares is introduced in [7]. This suggests spare rows, C2 must be repaired by a spare column. As for,
a more efficient way to repair multiple memory blocks by C2 in Fig. 1, if a faulty line can be repaired by only one
repairing several faulty lines with a global spare line. of the two types of spare lines, the faulty line (i.e., faulty
ECC-enhanced BISR (EBISR) is a method to improve the row or column) becomes a must-repair faulty line.
reliability and yield of the memories [23]. EBISR repairs a The performance of BIRA is measured by the repair rate,
single permanent fault using ECC and allows a repair for area overhead and analysis speed. The repair rate is mainly
the remaining faults by spares. To obtain an optimum BISR considered as the most important factor in BIRA performance
performance in terms of repair speed and area overhead, two- since BIRA is fundamentally used to find a repair solution
phase-BISR for multiple memories and 3-D stacked memories for defective memories. The repair rate indicates how many
3162 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 64, NO. 12, DECEMBER 2017
defective memories can be repaired by BIRA, and the normal- Fig. 2. Block diagram of the proposed BIRA architecture.
ized repair rate is defined as the ratio of memories repaired
by BIRA to those that are repairable. To maximize the yield, storage for the faulty cell information. Because the proposed
the normalized repair rate needs to be optimal. An exhaustive BIRA does not require an extra storage for faulty cell informa-
search based on the fault addresses is unavoidable for achiev- tion, the area overhead is reduced. To achieve an acceptable
ing the optimal repair rate. This requires BIRA to store the analysis speed and optimal repair rate, this paper proposes
faulty cell information, including the fault addresses. Storage a novel BIRA method which performs a hierarchical RA
for the faulty cell information is the main source of the algorithm. The first stage of the RA finds a repair solution
area overhead in BIRA. Since BIRA is implemented on chip, by counting the number of faults in a faulty line with fault
the area overhead needs to be minimized. The analysis speed counters. If a repair solution is not found in the first stage,
of BIRA is another important factor since the test and repair the second stage of RA looks for the repair solution using a
cost is proportional to the analysis time. An ideal BIRA needs binary search tree. Because the second stage of the proposed
to have the optimal repair rate, low area overhead and a fast RA is an exhaustive search, the repair solution with the optimal
analysis speed. These three features, however, have a trade-off repair rate is guaranteed. It should be noted that the second
relationship. stage of RA becomes active only when the first stage fails to
To find a repair solution, BIRA stores the faulty cell find a solution. The activation of the second stage is likely
information, including fault addresses on the chip. Most BIRA when the defect rate is high.
algorithms store the faulty cell information in CAMs or regis- Fig. 2 shows the architecture of the proposed BIRA. After
ters [3]–[5], [22], [24]–[26], [29]–[31]. Due to the fast access finding a fault-free region, the proposed BIRA stores a start
speed of CAMs and registers, a comparison between a newly and end address of the fault-free region in a window register.
found fault address and already stored fault addresses can Since the start and end address of the fault-free region is
be performed in one cycle. However, the area overhead of known, the BIRA can access it directly using the window
the required storage is considerably large since a CAM cell address. The proposed BIRA does not require extra storage for
consists of 3 to 10 transistors [13]–[18]. Moreover, the area faulty cell information. Using the window register information,
overhead for the faulty cell information storage dominates the BIRA controller interacts with the fault-free region. The
overall area overhead in BIRA architectures [3]–[5]. There- BIRA controller is composed of the comparator, controller
fore, it is important to minimize the BIRA storage size in and analyzer. The comparator compares the incoming faults
memories. with the stored faulty cell information and the results are
sent to the controller. It determines whether the new faulty
III. P ROPOSED BIRA A RCHITECTURE cell information to be stored in the fault-free region. After
A. Overview of the Proposed BIRA fault collection, the analyzer finds the repair solution using
the faulty cell information in the fault-free region. Details of
The three main considerations in BIRA are 1) repair rate, the fault collection and repair algorithm are discussed in Sec.
2) analysis speed, and 3) area overhead. Most previous BIRA III.C and D, respectively. The repair solution, once found, is
architectures require external storage such as CAMs and stored in the repair register.
registers, and it causes a significant area overhead. In addition,
if the external storage is found defective, the memory under B. Fault-Free Memory Region for Faulty Cell
test cannot be repaired even if it is repairable. This is because Information Storage
the RA algorithms run using the information stored in the The proposed BIRA utilizes a fault-free region of the main
defective CAMs or registers. memory array for faulty cell information storage. This method
In this paper, we propose a new BIRA architecture that thus requires finding a fault-free region. After determining its
exploits the fault-free region of the memory under test as a required size, the proposed BIRA first finds a fault-free region
OH et al.: BIRA WITH OPTIMAL REPAIR RATE USING FAULT-FREE MEMORY REGION FOR AREA REDUCTION 3163
Fig. 5. Example of fault collection. (a) Memory-Under-Test with eight fault. (b) Fault-free region after 1st fault. (c) Fault-free region after 2nd fault.
(d) Fault-free region after 3rd fault. (e) Fault-free region after 4th fault. (f) Fault-free region after 5th fault. (g) Fault-free region after 6th fault. (h) Fault-free
region after 7th fault. (i) Fault-free region after 8th fault.
proposed BIRA analyzer takes the values from the fault-free rate would not be guaranteed in the first stage. However,
memory region and finds the repair solution. The proposed it should be noted that if the valid repair solution is found,
BIRA uses a two-stage hierarchical algorithm to obtain a it is an effective solution since its analysis speed is much
fast analysis speed and optimal repair rate. In the first stage, faster than an exhaustive search. If the first stage fails to find
the proposed method tries to find a repair solution without a repair solution, the proposed BIRA enables a second stage
performing an exhaustive search. Hence, the optimal repair in which an exhaustive search is performed. Because most of
3166 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 64, NO. 12, DECEMBER 2017
Fig. 6. RA algorithm flow in the proposed BIRA. (a) First stage of the proposed BIRA. (b) Second stage of the proposed BIRA.
the repairable memory can be repaired only by the first stage, spares, are zero, the memory-under-test becomes repairable.
the total analysis speed of the proposed BIRA is fast. This is Otherwise, the memory cannot be repairable with the first
further discussed in Sec. IV. stage of RA only.
The first stage of the proposed RA algorithm uses the Fig. 7 shows an example of the first stage of the proposed
information from the fault counters and the fault storage of RA procedure for the faulty memory used in Fig. 5(a).
the fault-free memory region. The flow of the first stage is Fig. 7(a) illustrates the fault-free region after fault collection.
shown in Fig. 6(a). First, the proposed BIRA searches for a In the RA procedure, BIRA first searches the fault counters
must-repair faulty rows and columns which have the highest for the stored must-repair faulty lines. The row counter of
counter value, and spare lines are assigned to the must-repair the fourth entry is three, which equals Cs + 1. BIRA marks
faulty lines. If the row counter value is Cs + 1, the row is the faulty row corresponding to the fourth entry as a must-
a must-repair faulty row. A must-repair faulty column can repair faulty row and repairs the faulty row with a spare row.
also be detected in a similar manner. Once a spare row has The proposed BIRA can find the location of faults in the
been assigned to the faulty row, BIRA decrements the column faulty line through the column bitmap. It then decrements
counters of the faults in the faulty row. In the same manner, the counter of the column for which the bit of the column
after a spare column is assigned to a faulty column, BIRA bitmap is set to 1 as shown in Fig. 7(b). The BIRA next selects
decrements the corresponding row counter for the faults in the maximum counter value to repair. The maximum counter
the faulty column. After repairing all must-repair faulty lines, value among the unrepaired faulty lines is two, and the BIRA
BIRA continues to repair the faulty lines with the largest thus selects the third entry of the row counter to repair. The
counter values in descending order. If there are two or more third entry of row address in fault storage is for row 2, so the
counter entries with the same counter value, the BIRA selects column counters corresponding to the fault location in row 2 is
the leftmost entry to repair. The repair process continues decremented. Fig. 7(c) shows the status after decrementing
until all of the spare lines are consumed, or all counter the column counters. After repairing row 2, the BIRA has no
values become zero, except those for lines repaired by the remaining spare rows. Therefore, the BIRA finds the maximum
spares. If all counter values, except for the lines replaced by counter value in the column counter to repair faulty columns.
OH et al.: BIRA WITH OPTIMAL REPAIR RATE USING FAULT-FREE MEMORY REGION FOR AREA REDUCTION 3167
Fig. 7. Fault-free region status on the first stage of the proposed RA procedure. (a) Fault-free region after fault collection. (b) Fault-free region after first
spare line assigned. (c) Fault-free region after second spare line assigned. (d) Fault-free region after third line spare assigned. (e) Fault-free region after fourth
spare line assigned. (f) Fault-free region after the first stage of the proposed RA.
After finding the maximum column counter value, the BIRA region, the original counter values in the fault-free region are
decreases the row counters in the same manner as for column maintained. Therefore, the decreasing counter method can also
counters. In this case, the BIRA must search the entire column be accurately performed in the second stage. A repair solution
bitmap to know which row has the fault in the target column. is required to repair all must-repair faulty lines. By checking
Fig. 7(d) and (e) show the status of the fault-free region after whether all the addresses of must-repair faulty lines are
repairing column 5 and column 3, respectively. Fig. 7(f) shows included in a candidate, the proposed BIRA can confirm that
the status of the fault-free region after finishing the first stage the candidate repairs the must-repair faulty lines. If a candidate
of the proposed BIRA. All of the counter values except for covers all of the must-repair faulty lines, the covering must-
those of the repaired faulty lines are zero, so the memory- line bit of the candidate is set to 1. Therefore, the proposed
under-test is repairable. The selected faulty line to repair is BIRA only selects candidates covering all the must repair lines
the repair solution. In this example, the repair solution is R5 and then executes the decreasing counter method.
(fourth entry of the row counter), R2 (third entry of the row The only difference between the first and second stages
counter), C5 and C3. is the way the faulty lines to be repaired are selected. The
If the first stage of the proposed BIRA finds a repair solu- first stage repairs the faulty lines having the highest counter
tion, the RA procedure finishes. However, if the repair solution values, while the second stage determines the faulty lines
is not found in the first stage, the proposed BIRA continues to be repaired using the candidates. Thus, the second stage
to the second stage. The second stage operates an exhaustive selects the row (column) faulty line to be replaced from
search. With the second stage operation, the proposed BIRA the candidates, and decrements the column (row) counters
can reach the optimal repair rate. of the faults in the row (column) faulty line. After repairing
The second stage of the RA algorithm utilizes the pivot all the faulty lines in a candidate, if entire counter values
fault storage. The flow of this stage is presented in Fig. 6(b). except for the lines belonging to the candidate are zero, the
Based on the stored pivot faults, the proposed BIRA builds memory-under-test is repairable. When some pivot storage
repair candidates using a binary search tree. Depending on entries remain empty, the candidates are built in another way.
whether the pivot storage is full or not, candidates can be When some pivot-enable flags remain as 0, the faults that are
built in different ways. When all of the pivot-enable flags not pivot faults should also be included in the candidates.
are set to 1, the BIRA selects Rs pivot faults from among Before including non-pivot faults in candidates, the BIRA
the stored pivot faults to repair with spare rows. There are constructs the candidates only using pivot faults. In this
Rs+CsCRs combinations. The BIRA repairs unselected pivot moment, the proposed BIRA can select Rs to Np – Rs of pivot
faults with spare column lines. Each candidate repairs Rs faults to repair by spare row where Np denotes the number of
faulty row lines and Cs faulty column lines. At this point, stored pivot faults. The rest of pivot faults are repaired by spare
the proposed BIRA calculates the priority of each candidate. column. Then, the decreasing counter method is performed in
Because a faulty line that contains more faults is more likely the same way as when the pivot storage is full. If all of the
to be a repair solution, the BIRA obtains the priority of each counter values expect for those of the repaired lines are zero
candidate by adding counter numbers of the faulty lines consti- and must-repair lines are covered, the memory is repairable
tuting the candidate. After finding candidates, the decreasing and the RA is finished.
counter method used in the first stage is performed from the If nonzero counter values are left and the repair solution is
candidate having the highest priority value. Because the first not found, the BIRA chooses (Rs + Cs – Np) of the counter
and second stage of redundancy algorithms is carried out in the values that should be zero and allocates the remaining spare
BIRA analyzer after taking counter values from the fault-free lines to the faulty lines. If all the counter values except those
3168 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS, VOL. 64, NO. 12, DECEMBER 2017
Fig. 8. The second stage of the proposed RA algorithm. (a) The memory-under-test. (b) Priority and covering must-repair faulty lines of each candidates for
repair solution, (c) Fault-free region after fault collection, (d) Fault-free region after first stage of the proposed RA, (e) Fault-free region after applying second
candidate in (b), (f) Fault-free region after applying sixth candidate in (b).
for lines replaced with spares become zero, after assigning zero, as shown in Fig. 8(f). Therefore, the sixth candidate is
spare lines, the memory is repairable and the repair solution the repair solution.
is found. Otherwise the memory is irreparable. Because the proposed BIRA performs the second stage
Fig. 8 illustrates an example of the second stage of the pro- of the RA algorithm only when the first stage fails to find
posed RA procedure. Fig. 8(a) shows the memory-under-test. a repair solution, the analysis time is effectively reduced.
Fig. 8(b) represents the candidates found using stored pivot Since the second stage of the RA is an exhaustive search,
faults. It also includes priority and information as to whether it guarantees the optimal repair rate. Moreover, the proposed
the candidate covers all must-repair fault lines. The fault- BIRA does not require extra storage, such as CAMs, to store
free region after fault collection is demonstrated in Fig. 8(c). faulty cell information, therefore, the area overhead of BIRA
Fig. 8(d) shows the fault-free region after performing the first is minimized.
stage of the proposed RA algorithm. Because the fifth row
counter and sixth column counter, which are not assigned to
spares, are not zero, the memory-under-test cannot be repaired IV. S IMULATION R ESULT
by the first stage alone. Therefore, the proposed RA builds The performance of the proposed BIRA can be evaluated
candidates. Then, the proposed RA investigates the priority with respect to three main considerations of BIRA: 1) repair
and must-repair fault lines coverage for candidates as shown rate, 2) analysis speed, and 3) area overhead. Regarding
in Fig. 8(b). When the covering must-line bit is one, it means the area overhead, although BIRA is composed of several
the candidate covers every must-repair faulty line. As shown components, the size of the faulty cell information storage
in Fig. 8(b), the second and sixth candidate have the highest is commonly compared since this dominates the size of
priority. They also cover all the must-repair faulty lines. BIRA [3]–[5]. In this sense, because the proposed BIRA does
Therefore, the proposed RA first applies the decreasing counter not require an extra storage element such as a CAM for the
method to these candidates. After applying this to the second faulty cell information, the area overhead is minimized.
candidate, because the counter of the fifth column, which is not For the repair rate and analysis speed, the proposed method
replaced with a spare column, is not zero as shown in Fig. 8(e), is compared with BRANCH analyzer [4] and BIRA using
this candidate is a non-repair solution. Therefore, the proposed AMT [5], [26], [30], since they demonstrate the best perfor-
BIRA considers the sixth candidate. In this case, all counter mance in planar memory. The experiments are performed with
values of the faulty lines which are not assigned to spares are a memory which has 1024 rows and 32 columns. We assume
OH et al.: BIRA WITH OPTIMAL REPAIR RATE USING FAULT-FREE MEMORY REGION FOR AREA REDUCTION 3169
TABLE I
T HE N UMBER OF T RANSISTORS FOR CAM C ELLS IN BRANCH
A NALYZER AND BIRA U SING AMT (R S , C S = 4)
TABLE II
T HE A REA OVERHEAD OF BIRA A PPROACHES (R S , C S = 2)
Fig. 9. Normalized repair rate comparison with different number of faults.
that there are 4 spare rows and 4 spare columns. For the
experiments, 10000 sets of random faults are generated.
To compare the BIRA approaches, we made a BIRA simu-
lator using the C language. The simulation parameters include
memory size, the number of spare rows and spare columns,
and the faults in the memory. After analysis, the results consist
of the repair rate and analysis time.
Table. I shows the number of transistors for CAM cells Fig. 10. Analysis speed comparison with different number of faults when
required in BRANCH analyzer and BIRA using AMT to repair the used main memory is DRAM.
1024×32 memory with Rs, Cs = 4. Based on the type of CAM
cell, the number of transistors can be different [14]–[17]. Even
though the area of control logic is not counted, the required While the area overhead for extra storage linearly increases as
area for the CAM cells are considerable. Since the proposed the memory size grows, the area overhead by BIRA controller
BIRA does not require extra storage for faulty cell information, would not be linearly increasing. Because the extra storage
the area overhead is much smaller than that of BRANCH size is proportional to the size of memory to repair [3]–[5],
analyzer and BIRA using AMT. the BIRA controller size becomes negligible as the memory
Generally, the storage for faulty cell information is the size is increased.
dominant part of the area overhead. Nevertheless, we com- The normalized repair rate comparison results are given
pared the entire area of BIRA for a more precise compari- in Fig. 9. This shows that the proposed BIRA method
son. The control logic of BRANCH, BIRA using AMT and along with the BRANCH, BIRA using AMT, BIRA for
the proposed BIRA were implemented in Verilog HDL and word-oriented memory [30] and binary search tree based
synthesized using Synopsys Design Compiler. We synthesized BIRA [26] achieve the optimal repair rate. For the proposed
BIRA circuits using Synopsys 32-nm library. The storage method, the first stage achieves a normalized repair rate higher
size of the CAMs for BRANCH and BIRA using AMT is than 95%. This means that only less than 5% of the fault
calculated based on [4], [5], and [13]–[18]. sets require the second stage of the proposed BIRA. Hence,
We compare the area in terms of gate counts for each BIRA compared to the BIRA methods which require an exhaustive
circuit as shown in Table. II. The gate count is calculated as search for all cases, the proposed BIRA achieves a faster
the number of two input NAND gate. The two input NAND analysis speed. In most cases, the proposed BIRA can find
gate is used as the unit gate. We compare the area of BIRA a repair solution using only the first stage.
using the memory size of 1024 × 32 and Rs, Cs = 2. Fig. 10 and Fig. 11 show the normalized analysis time
In Table. II, the control logic is the BIRA circuit excluding comparisons when the proposed method is applied to RAM
the storage for faulty cell information. As shown in Table. II, (Random Access Memory) – DRAM and SRAM, respec-
the area of control logic for BIRA using AMT and the pro- tively. The analysis time of redundancy analysis algorithms
posed BIRA is similar. However, BRANCH and BIRA using are normalized as the number of CAM accesses while per-
AMT require extra storage for storing faulty cell information. forming each RA. The normalized analysis time is calculated
Finally, the entire area overhead of the proposed BIRA is the as follows. For BRANCH, AMT, BIRA for word-oriented
smallest. memory and binary search tree based BIRA, the number of
Besides of the extra storage, the dominant part in CAM accesses is counted to measure the analysis time, and for
area overhead of BIRA is the logic for BIRA controller. AMT and the proposed method, the number of accesses to the
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a minimized binary search tree,” ETRI J., vol. 32, no. 4, pp. 638–641, conductor system engineering from Sungkyunkwan
Aug. 2010. University, Suwon, South Korea, in 2016.
[27] T.-W. Tseng, J.-F. Li, and C.-C. Hsu, “ReBISR: A reconfigurable built-in She is currently pursuing the M.S. degree with
self-repair scheme for random access memories in SOCs,” IEEE Trans. Sungkyunkwan University. She has done an intern-
Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 6, pp. 921–932, ship with Samsung Electronics Company, Ltd.,
Jun. 2010. Hwasung, South Korea, in 2015. Her current
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Proc. Int. Test Conf., Atlantic City, NJ, USA, 2000, pp. 567–574. memory error correction architecture.
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BISR techniques for embedded memories considering cluster faults,”
IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 2,
pp. 184–193, Feb. 2010. Joon-Sung Yang (S’05–M’09) received the
B.S. degree from Yonsei University, Seoul, South
Korea, in 2003, and the M.S. and Ph.D. degrees
from The University of Texas at Austin, Austin,
TX, USA, in 2007 and 2009, respectively, all in
Chang-Hyun Oh (S’17) received the B.S. degree electrical and computer engineering. He was with
in semiconductor system engineering from Intel Corporation for four years. He is currently an
Sungkyunkwan University, Suwon, South Korea, Associate Professor with Sungkyunkwan University,
in 2016, where he is currently pursuing the South Korea. His research interests are VLSI
M.S. degree with the Department of Semiconductor testing, silicon debug, and nanometer scale test and
and Display Engineering. design methodologies.
He had an internship program with Samsung Dr. Yang was a recipient of the Korea Science and Engineering Foundation
Electronics, Inc., Hwasung, South Korea, in Scholarship in 2005. He received the Best Paper Award from the 2008 IEEE
2014. His research interests are built-in redundancy International Symposium on Defect and Fault Tolerance in VLSI Systems
analysis, hardware security, and design methodology. and from the 2016 IEEE International SoC Design Conference, and was
nominated for the Best Paper Award at the 2013 IEEE VLSI Test Symposium.