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Artix7 Verilog Word File

The document describes the FPGA design flow for a 1-bit full adder circuit using Xilinx Vivado tools. The steps include: 1) Developing a Verilog model for the full adder circuit and a test bench; 2) Running synthesis and implementation to optimize, place and route the design; 3) Analyzing the timing, power usage, and resource utilization of the implemented design. The full adder circuit is then tested through simulation before generating a bitstream file for the FPGA.

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Swapna Sarker
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42 views7 pages

Artix7 Verilog Word File

The document describes the FPGA design flow for a 1-bit full adder circuit using Xilinx Vivado tools. The steps include: 1) Developing a Verilog model for the full adder circuit and a test bench; 2) Running synthesis and implementation to optimize, place and route the design; 3) Analyzing the timing, power usage, and resource utilization of the implemented design. The full adder circuit is then tested through simulation before generating a bitstream file for the FPGA.

Uploaded by

Swapna Sarker
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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FPGA Design Flow For Full Adder

Aim:
The purpose of this design is to introduce to the basic FPGA
design and programming tools. For this purposes, first
perform an installation of the tools and then implement an
adder circuit using FPGA design flow.

Objective :
Design and develop a Verilog model for full adder on FPGA
and calculating power, area and time delay.

Equipment & tools:


Nexys 4 Artix-7, Xilinx Vivado Suite.
Product: Artix 7
Family: Artix-7
Part name: xc7a100tcsg324-1
Introduction:
This is a step-by-step process flow for building a 1-bit full
adder in Xilinx Vivado, a Design Suite software that provides
with the ability to code designs in a hardware description
language such as VHDL or Verilog. The ISE Design Suite
also provides the ability to apply FPGA pin and timing
constraints, analyze for errors and violations, and synthesize
to generate configuration bit file formats for FPGAs
Below shown actual FPGA design flow:

Procedure(Step-by-step 1-bit Full Adder Design):


Step1: Design the full adder. An example 1-bit full adder block
diagram and Boolean circuit are shown in Fig.2 (a) and (b),
respectively.
Step2: Develop a Verilog model for full adder
Step3:Write a test bench(provides a path to test the
functionality for different inputs at different time intervals)to
test its functionality.
Go to add sources Add or create design source

Verilog Code:
Test Bench:

Simulation Result:
Step4:
Go to RTL AnalysisOpen Elaborated design

Go to Layout  I/O planning


Make the constraint file by assigning the following pin numbers to the
ports. A .xdc constraint file will be created as shown below.
RTL Schematic
 The RTL schematic is independent of technology

Step 5: Run Synthesis.


Step 6: Run Implementation (where optimisation, placement and
routing happens)
Go to Report timing summary Check the critical path delay.
Timing Analysis:

Critical path delay(Total delay): 12.424ns


Logic delay: 5.141ns
Net delay:7.282ns

Power Analysis:
Go to Project Summary  Check on chip power
Total on chip power = 2.815W
Dynamic power = 2.707W
Static power = 0.108W

Area Analysis:
Go to Project Summary Utilization  Table
No of LUTs: 1
No of IO: 5

Step 7:Generate Bitstream

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