Digital Signal Processing Project Report

Ihtisham ul haq
8th Semester
Morning Section
16PWMCT0478

Instructor: Dr. Shehzad Anwar

Department of Mechatronics Engineering

University of Engineering and Technology
Peshawar

Dated: 22 july , 2020.

Title: Generate PWM Signal In MATLAB With Varying Duty Cycle

ABSTRACT:
This article manages the age PWM signals with variable obligation from 0% to 100% utilizing VHDL and
its application in field programmable door clusters. The article too talks about the use DCM for decline
the clock recurrence. DCM is an advanced clock supervisor that is valuable to diminish the slant of clk
signal when we need to separate the clk recurrence. We utilized a fixed recurrence to create the info
information that produce the PWM signals utilizing one comparator. The comparator analyzes between
two info information. First information is produced utilizing PWM counter and second information is
created by up-down counter utilizing two press catches. PWM has a fixed recurrence also, a variable
voltage. This voltage esteem changes for 0V to 2.5 V. Inside signs are observed on the PC by stage link
usbII and ChipScope program. We need a board fpga and ISE bundle version1.

INTRODUCTION:
Heartbeat width adjustment (PWM) is an amazing method for controlling simple circuits with a
processor's computerized yields. PWM is utilized in a wide assortment of utilizations, running from
estimation and interchanges to control and transformation. The utilizations of PWM are utilized in charge
frameworks like DC-DC converters have been clarified in references [1], [2], [3] where the PWM signals
were utilized to change over unregulated DC voltage to controlled or variable DC voltage at the yield. In
AC engine drives, PWM inverters permit to control both recurrence and size of the voltage and current
applied to the engine. A PWM signal isn't consistent, the principle boundary is an obligation cycle D that
is a piece of PWM period and portrays the extent of on an ideal opportunity to ordinary stretch. The
condition (1) portrays the obligation cycle as the accompanying. The main advantage PWM is that power
loss is very low in the switching devices. Many digital circuits can generate PWM signals [1]. In this article
a simple method is used where a sawtooth waveform and carried data are required. A comparator
compares between two values in order to generate pulse width modulation. Hardware Description
Language (VHDL) is used to generate the required signals in FPGA. Engineers use microcontrollers
largely to build control system [4], but the microcontrollers are going to disappear with the appearance
FPGA. With FPGA, all control system features can be added to a single chip, and new functions can be
used by the designer. This article scans the steps of building a PWM signals using VHDL in FPGA XILINX,
these signals can be used in many control systems such as: DC-DC converter, DC motors and DSP system.
Board FPGA, ISE software and platform cable USB II are necessary to implement the design.
PROBLEM STATEMENT AND OBJECTIVE:

 WHY USE PWM:

In a circuit controlled by an analog voltage, there is considerable power used because of the
continuous current flow in the load. This creates a great deal of wasted power being lost as heat.
On the other hand digital systems only generate heat when the voltage is at a high level. In PWM
control applications, this can be a very small amount of time.
The effect is a large savings in the power used in the circuit.
 OBJECTIVES:
Pulse width modulation is used for a wide variety of control applications on mobile and plant
equipme
PWM signal has a slower response time than an analog signal, but it is more stable against
circuit resistance and supply voltage change
A critical application controller or ECM may detect a wiring failure by monitoring the frequency of
a PWM signal from a sensor.

NEEDS AND REQUIREMENT:

 The frequency that the PWM signal needs to be set at will be dependent on the application and
the response time of the system that is being powered.
 Heating elements or systems with slow response times: 10-100 Hz or higher. DC electric motors:
5-10 kHz or higher.
 Power supplies or audio amplifiers: 20-200 kHz or higher .

 Multifunction I/O Device

 C Series Digital Module
 Counter/Timer Device
  Multifunction Reconfigurable I/O Device
 Matlab labview.

LITERATURE REVIEW:

 The modern inverter technology for serving the society through comfort, making not only changes
the domestic life style but in industries where VFD and other lifting & tackles require a new and
efficient technology for betterment of performance of the drive and lifting tackles. Here the paper
gives the schematic work of various scholars and comparison of different techniques of different
pulse width modulation techniques for Power Electronics Inverters used for different industrial
and commercial applications
 Pulse-width-Modulation techniques are used for, harmonic elimination and/or reduction at the
output of the inverter and simultaneously achieving the output voltage control. Microprocessor
based implementation offers many advantages hence stress is to develop PWM techniques so that
on-line microprocessor based implementation is easily possible. Different PWM techniques like
Square-Wave, Sinusoidal, Regular-Sampled, harmonic elimination PWM and the Regular-Sampled
Harmonic-Elimination PWM are the available options for a designer. Depending on the
requirements, a suitable PWM scheme is selected. This paper reviews these PWM techniques in
details. Their theoretical development and harmonic plots (Harmonic amplitudes versus
Modulation index) are presented. The paper also compares all the PWM schemes.

APPROACH AND METHODOLOGY :

The PWM generator block outputs either 1 when the duty cycle is greater than the carrier counter
value, or 0 otherwise. You can set the period of each cycle by specifying the timer period Tper. You can
change the initial output, or phase, of the PWM output by specifying one of three types of carrier
counters:

 Up counter.
 Down counter.
 Up-Down Counter.
1. Up counter: The PWM output signal initializes at the start of the on cycle. This graphic shows
the carrier counter signal and the corresponding PWM output.

2. Down counter: The PWM output signal initializes at the start of the off cycle. This graphic
shows the carrier counter signal and the corresponding PWM output
 3. Up-Down counter: The PWM output signal initializes halfway through the on cycle. This
graphic shows the carrier counter signal and the corresponding PWM output.

To produce the input data to generate the PWM using a high-speed N-bit free running counter, whose
output is compared with register output and stores desired input duty cycle with the help of
comparator. The comparator output is set to 1 when both these values are equal. This comparator output
is used to set RS latch. The overflow signal from the counter is used to reset the RS latch. The  output of RS
latch gives the desired PWM output. This overflow signal is also used to load new N-bit duty cycle in the
Register. PWM has a fixed frequency and a variable voltage. This voltage value changes from 0V to 5 V.

Figure 1: PWM Signal with Variable Duty Cycle

The basic PWM generates the signals, which gives the output of PWM, requires a comparator that
compares between two values. The first value represents the square signal generated by the N bit counter
and the second value represents the square signal which contains the information about duty cycle. The
counter generates the load signal whenever there is an overflow. Once the load signal becomes active, the
register loads the new duty cycle value. The load signal is used to reset the latch also. Latch output is a
PWM signal. This is varying with the change in duty cycle value.
MATLAB CODE:
RESULTS:
For Duty Cycle =20:

Duty Cycle =50:

Duty Cycle =75:

REFERENCES:
REFERENCES:

[1]…. John G Proakis “Digital Signal Processing”, 3rd edition

[2]…. https://www.mathworks.com/help/physmod/sps/ref/pwmgenerator.html

[3]…. https://www.jcbrolabs.org/

[4]…. https://www.elprocus.com/generating-pwm-signals-variable-duty-cycle-fpga/

[5]…. https://www.youtube.com/watch?v=p0cSizhrhkQ&feature=youtu.be