Computer Organization & Architecture

MODULE 3

Input/ Output Organization

Accessing I/O devices

A simple arrangement to connect I/O devices to a computer is to use single bus

arrangement as shown in Fig1. The bus enables the devices connected to it to exchange
information. It consists of three set of lines to carry address, data and control signals. Each
I/O device is assigned unique set of addresses.

With the memory mapped I/O any machine instruction that can access memory can be
used to transfer data to or from an I/O device.

Move DATAIN, R0

Reads data from the DATAIN and stores into processor register R0. Similarly

Move R0, DATAOUT

Sends the contents of register R0 to location DATAOUT which is the output data
buffer of a display unit or a printer.

Processor Memory

I/O Device 1 I/O Device n

Fig1: Simple bus structure

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Krishna Teja, Asst. Prof, Dept of ECE, CMRIT
Computer Organization & Architecture

Address lines

Bus Data lines

Control lines

Address Control Circuits Data & Status

Decoder Registers

Input Device

Fig 2: I/O interface of an input device

Fig 2 illustrates the hardware required to connect the I/O device to the bus. The address
decoder enables the device to recognize its address when its address appears on the address
lines. The data register holds the data being transferred to or from the processor. The status
register contains the information relevant to the operation of I/O device. Both status and data
registers are connected to the data bus and assigned unique addresses.

The address decoder, data & status registers and the control circuitry required to
coordinate I/O transfers constitutes the device interface circuit.

Let us consider a simple example of I/O operation involving a keyboard and a display
device in the computer system. The four registers shown are used for data transfer operations.
Register STATUS contains two control flags SIN and SOUT which provide status
information for keyboard and display unit. The two flags KIRQ and DIRQ are used in
conjunction with interrupts. Data from the keyboard are made available in DATAIN register
and data sent to the display unit are stored in the DATAOUT register.

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Krishna Teja, Asst. Prof, Dept of ECE, CMRIT
Computer Organization & Architecture

DATAIN

DATAUOT

STATUS DIRQ KIRQ SOUT SIN

CONTROL DEN KEN

Fig 3: Registers in keyboard and display interface

The program reads the line of characters from the keyboard and stores it in the memory
buffer starting from the memory location LINE.

Move #LINE, R0 Initialize memory pointer

WAITK Testbit #0, STATUS Test SIN

Branch=0 WAITK Wait for the character to be entered

Move DATAIN, R1 Read character

WAITD Testbit #1, STATUS Test SOUT

Branch=0 WAITD Wait for display unit to be ready

Move R1, DATAOUT Send character to be displayed

Move R1, (R0) + Store character and advance pointer

Compare #$0D, R1 Check if carriage return

Branch ≠ 0 WAITK if not get another character

Move #$0A, DATAOUT otherwise send line feed.

Call PROCESS call the subroutine to process the input line

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Krishna Teja, Asst. Prof, Dept of ECE, CMRIT
Computer Organization & Architecture

Interrupts

The other tasks can be performed by the processor while waiting for the I/O device to
become ready. When the I/O device becomes ready, it sends a hardware signal called
interrupt to the processor. Using the interrupts waiting periods can be eliminated.

Consider a task that requires some computations to be performed and the results to be
printed on a line printer. This is followed by more computations and output and so on. Let the
program consists of two routines COMPUTE and PRINT. Assume COMPUTES produces a
set of ‘n’ lines of output to be printed by PRINT routine.

Program 1 Program 2

COMPUTE routine PRINT routine




interrupt

occurs

here

Fig 4: Transfer of control through the use of interrupts

It is possible to overlap printing and computation ie to execute COMPUTE routine

while printing is in progress, a faster overlap speed of execution will result. Whenever printer
becomes ready, it alerts the processor by sending a interrupt request signal. In response the
processor interrupts the COMPUTE routine and transfers the control to the PRINT routine.
This process continues until all ‘n’ lines are printed and PRINT routine ends.

If COMPUTE takes longer to generate ‘n’ lines than the time required to print them,
then the processor will be performing useful computations all the time.

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Krishna Teja, Asst. Prof, Dept of ECE, CMRIT
Computer Organization & Architecture

Saving registers also increases the delay between the time the interrupt request is
received and the start of execution of interrupt service routine. This delay is called interrupt
latency.

Interrupt Hardware

I/O device requests an interrupts by activating a bus line called interrupt request. A
single interrupt may be used to serve ‘n’ devices.

Fig 5: Circuit for common interrupt request line

To request an interrupt device closes its associated switch. Thus if all the interrupt
request signals INTR1 to INTRn are inactive, the voltage on the interrupt request line is Vdd.
This is the inactive state of the line. When the device requests the interrupt by closing its
switch, the voltage line drops to zero causing the interrupt request line INTR received by the
processor to go to 1. The value of INTR is the logical OR of the requests from individual
devices, that is

INTR=INTR1 + . . . .+ INTRn

R is the pull up register because it pulls line voltage up to high voltage when the switches
are open.

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Krishna Teja, Asst. Prof, Dept of ECE, CMRIT
Computer Organization & Architecture

Enabling and disabling the interrupts

The enabling and disabling interrupts must be available to the programmer. A simple
way is to provide machine instructions such as Interrupt-enable and Interrupt-disable that
performs these functions.

When the device activates interrupt request signal, it keeps this signal activated until
it learns that the processor has accepted its request. It is essential to ensure that this active
signal does not lead to successive interruptions causing the system to enter an infinite loop
from which it cannot recover. There are three ways to avoid this problem.

The first option is that processor must ignore the interrupt request line until the
execution of first instruction of interrupt service routine (ISR) has been completed. Then by
using the Interrupt disable instruction as the first instruction in the ISR, programmer can
ensure that no further interruption will occur.

The second option is to have processor automatically disable the interrupts before
staring the execution of Interrupt service routine. After saving the contents of PS on the stack
with Interrupt enable bit equal to 1, the processor clears the Interrupt enable bit in PS register
thus disabling further interrupts. When a return from interrupt instruction is executed, the
contents of PS are restored from the stack setting the Interrupt enable bit back to 1. Hence
interrupts are again enabled.

In the third option, processor has a special interrupt request line for which the interrupt
handling circuit responds only to leading edge of the signal. Such a line is said to edge
triggered.

The sequences of events involved in handling the interrupt request from a single
device are as follows.

1. The device raises an interrupt request.

2. The processor interrupts the program currently being executed.

3. Interrupts are disabled by changing the control bits in the PS register.

4. The device is informed that the request has been recognized and in response
deactivates the interrupt-request signal.

5. The action requested by the interrupt is being performed by the interrupt service
routine.

6. Interrupts are enabled and the execution of interrupted program is being resumed.

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Krishna Teja, Asst. Prof, Dept of ECE, CMRIT
Computer Organization & Architecture

Handling Multiple devices

The information needed to determine whether a device is requesting an interrupt is

available in its status register. When a device raises an interrupt request, one of the bits of the
status register is set to 1 which we call IRQ bit.

KIRQ, DIRQ are the interrupt request bits for keyboard and display. The polling
scheme ha the disadvantage that the time spent interrogating the IRQ bits of all the devices
that may not be requesting any service. An alternate approach is to use vectored interrupts.

Vectored Interrupts

A device requesting an interrupt can identify itself by sending special code to the
processor over the bus. The code supplied by the device represents the starting address of the
interrupt service routine. The code length is 4 to 8 bits. The processor reads this address
called the interrupt vector and stores it in to the PC. The interrupt vector may also include a
new value for a processor status register.

The interrupted device must wait to put on the bus only when the processor is ready to
receive it. When the processor is ready to receive the vector interrupt code, it activates the
interrupt acknowledge line INTA. The I/O device responds by sending its interrupt vector
code and turning off INTR signal.

Interrupt Nesting

I/O devices should be organized in a priority structure. An interrupt request from a high
priority should be accepted while the processor is serving another request from the lower
priority device.

We can assign priority level to the processor that can be changed under program
control. The priority level of the processor is the priority of the program that is currently
being executed. The processor accepts interrupts from devices that have priorities higher than
its own.

The processor is in supervisory mode when it is executing the OS routines. It switches

to User mode before beginning to execute application programs. The privileged instructions
can be executed only while the processor is running in the supervisory mode. A multiple
priority scheme can be implemented by using separate interrupt request and interrupt
acknowledge lines from each device.

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Krishna Teja, Asst. Prof, Dept of ECE, CMRIT
Computer Organization & Architecture

Fig 6: Implementation of interrupt priority using individual interrupt request & acknowledge
lines

Simultaneous Requests

If several devices share one interrupt request line, some other mechanism is needed.
When several devices raises interrupt request and line is activated, the processor
responds by setting the INTA line to 1. The signal is received by device 1. Device 1 passes
the signal onto device 2 only if it does not require any service. If device 1 has pending
request for interrupt, it blocks the INTA signal and proceeds to put its identification code on
to data lines. In daisy chain the device that is electrically closest to the processor has the
highest priority.

Fig 7: Daisy chain

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Krishna Teja, Asst. Prof, Dept of ECE, CMRIT
Computer Organization & Architecture

Devices can be organized in groups and each group is connected at a different priority
level. Within group devices are connected in daisy chain.

Fig 8: Arrangement of priority groups

Controlling Device requests

It is important to ensure that interrupt requests are generated by only those I/O devices
that are being used by the given program. Consider a program that uses vectored interrupt
scheme where the staring address of interrupt service routine is stored at the memory location
INTVEC. Interrupts are enabled by setting Interrupt enable bit to 1in processor status register
which we assume is bit 9.

Assume that at some point in the program called Main we wish to read an input line
from keyboard and store the character in successive byte locations in memory locations
starting at location LINE. To perform this operation using interrupts, we need to initialize
interrupt process.

1. Load the starting address of interrupt-service routine in location INTVEC.

2. Load the address LINE in memory location PNTR. The Interrupt-service routine uses
this location as pointer to store the i/p character in memory.

3. Enable keyboard interrupts by setting bit 2 in register CONTROL to 1.

4. Enable interrupts in processor by setting to 1 the IE bit in processor status register PS.

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Krishna Teja, Asst. Prof, Dept of ECE, CMRIT
Computer Organization & Architecture

Once this initialization is completed, typing a character will cause an interrupt request to
be generated by keyboard interface. The interrupt service has to perform following tasks:

1. Read the input character from keyboard input data registers. This cause the interface
circuit to remove interrupt request.

2. Store the characters in memory location pointed to by PNTR and increment PNTR.

3. When end of line is reached, disable keyboard interrupt and inform the program Main.

4. Return from interrupt.

Main Program

Move #LINE, PNTR initialize buffer pointer

Clear EOL clear end of line indicator

BitSet # 2, CONTROL Enable keyboard interrupt

BitSet #9, PS Set Interrupt enable bit in PS register

Interrupt-Service Routine

READ MoveMultiple R0-R1, - (SP) Save registers R0-R1 on to stack

Move PNTR, R0 Load address pointer

MoveByte DATAIN, R1 Get input character & store it in memory

MoveByte R1, (R0) +

Move R0, PNTR update pointer

CompareByte #$0D, R1 check if carriage return

Branch ≠ 0 RTRN

Move #1, EOL indicate end of line

BitClear #2, CONTROL Disable Keyboard interrupts

RTRN MoveMultiple (SP) + , R0-R1 Restore registers R0 & R1

Return-from-interrupt

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Krishna Teja, Asst. Prof, Dept of ECE, CMRIT
Computer Organization & Architecture

Direct Memory Access

To transfer large blocks of data at high speeds, an alternate approach is used. A special
control unit may be provided to allow transfer of block of data directly between external
device and main memory without intervention by processor. This approach is called direct
memory access or DMA.

DMA transfers are performed by control circuits that are part of I/O interface called
DMA controller. The DMA controller performs functions that would normally be carried out
by processor when accessing main memory.

Fig 9: Registers in DMA interface

The R/ bit determine the direction of transfer. When this bit is set to 1 by a program
instruction, the controller performs read operation that is it transfers data from memory to I/O
device. When transfer is complete, it sets done flag to 1. When IE is1, it causes the controller
to raise an interrupt after it has completed transferring block of data. Finally IRQ bit is set to
1 when it has requested interrupt.

Requests from DMA devices are given high priority than processor requests. Among
different DMA devices high priority is given to high speed peripherals such as disks, high
speed network interface or graphic display device.

The processor originates most memory cycles, the DMA controller is said to steal
memory cycles from processor. This technique is called cycle stealing. DMA controller is
given access to main memory to transfer a block of data without interruption. This is called as
block or burst mode.

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Krishna Teja, Asst. Prof, Dept of ECE, CMRIT
Computer Organization & Architecture

Fig 10: Use of DMA controllers in computer system

Assignment Questions

1. Explain how I/O devices can be interfaces with a block diagram.

2. Give comparison between memory mapped I/O and program mapped I/O.
3. Define Interrupt. With example illustrate the concept of interrupt.
4. With a diagram explain daisy chaining technique.
5. With a neat sketch, explain a method for handling interrupts from multiple devices.
6. Explain the following terms
a. a. Interrupt Service Routine b. Interrupt Latency
b. Interrupt disabling.
7. Explain how Interrupt request from several I/O devices can be communicated to a
processor through a single INTR Line.
8. With a neat diagram, explain DMA controller.
9. Write short notes on: a. Vectored interrupt b. Interrupt nesting.

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Krishna Teja, Asst. Prof, Dept of ECE, CMRIT