DIGITAL ELECTRONICS:

PRINCIPLES AND APPLICATIONS

 The Author
Soumitra Kumar Mandal has completed BE (Electrical Engineering) from Bengal Engineering
College, Shibpur, Calcutta University; MTech (Electrical Engineering) with specialisation in Power
Electronics from Institute of Technology, Banaras Hindu University, Varanasi and PhD from Punjab
University, Chandigarh. He began his academic career as a lecturer of Electrical Engineering at S.S.G.M.
College of Engineering, Shegaon. Subsequently, he joined Punjab Engineering College, Chandigarh, as
a lecturer (Mar 1999 to Jan 2004). Presently, he is an Assistant Professor of Electrical Engineering at
National Institute of Technical Teachers’ Training and Research, Kolkata.
Dr Mandal is also a life member of ISTE as well as a member of IE. Twenty of his research papers
have been published in National and International Journals. He has also presented several papers
at National and International Conferences. His research interests are in computer controlled drives,
microprocessor- and microcontroller-based system design, embedded system design and neuro-fuzzy
computing.
 DIGITAL ELECTRONICS:
PRINCIPLES AND APPLICATIONS

Soumitra Kumar Mandal

Assistant Professor
Department of Electrical Engineering
National Institute of Technical Teachers’ Training and Research, Kolkata

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 Dedication
In the memory of
my youngest son —Late Gajanan Mandal
and to
my parents — Smt. Arati Mandal and Shri Prokash Mandal
my wife — Malvika
and
my children — Om and Puja.
 CONTENTS
Preface xi 2.5 Logic Gates 55
2.6 Universal Gate 61
1. NUMBER SYSTEM 1
2.7 Simplification of Logic Circuits 64
1.1 Introduction 1
2.8 Consensus Theorem 69
1.2 Analog Systems 2
2.9 Positive Logic and Negative Logic 70
1.3 Digital Systems 2
Summary 71
1.4 Limitations of Digital Systems 4
Multiple Choice Questions 72
1.5 Digital Number Systems 4
Review Questions 74
1.6 Binary Arithmetics 20
1.7 Signed Magnitude 24 3. DIGITAL LOGIC FAMILY 76
1.8 One’s Complement 25 3.1 Introduction 76
1.9 Two’s Complement 25 3.2 Classification of Digital Logic Family 76
1.10 Subtraction by using Two’s Complement 26 3.3 Characteristics of Digital Logic Family 77
1.11 Overflow 27 3.4 BJT Characteristics 81
1.12 Binary Coded Decimal (BCD) Number 3.5 Direct Coupled Transistor Logic (DCTL) 82
System 29 3.6 Resistor Transistor Logic (RTL) 82
1.13 Packed BCD 29 3.7 Diode Transistor Logic (DTL) 83
1.14 Gray Code (Reflected Code) 30 3.8 Transistor-Transistor Logic (TTL) 83
1.15 Gray Code to Binary Conversion 31 3.9 Emitter Coupled Logic (ECL) 85
1.16 Binary to Gray Code Conversion 31 3.10 Schottky TTL 85
1.17 Excess-3 (XS3) Code 32 3.11 High Threshold Logic (HTL) 86
1.18 Decimal to Excess-3 (XS3) Conversions 32 3.12 Integrated Injection Logic (IIL) 86
1.19 Weighted BCD Codes 32 3.13 TTL Logic Gates 88
1.20 ASCII Code 35 3.14 Characteristics of TTL 96
1.21 EBCDIC 37 3.15 Metal Oxide Semiconductor FETs (MOSFET)
1.22 Parity Bit 38 Characteristics 102
1.23 Error Correcting Code: Hamming Code 40 3.16 MOS Characteristics 107
Summary 42 3.17 CMOS Gates 107
3.18 CMOS Characteristics 111
Multiple Choice Questions 42
3.19 Interfacing TTL and CMOS Logic
Review Questions 44
Family 113
2. BOOLEAN ALGEBRA AND LOGIC GATES 46 3.20 Advantages and Disadvantages of CMOS Over
2.1 Introduction 46 TTL 116
2.2 Boolean Algebra 47 Summary 117
2.3 Boolean Laws 49 Multiple Choice Questions 117
2.4 De Morgan’s Theorem 53 Review Questions 119
 viii Contents

4. COMBINATIONAL LOGIC 122 6.3 Binary Subtraction 238

4.1 Introduction 122 6.4 Carry Look-Ahead Addition 244
4.2 Elements of Combinational Logic 122 6.5 Serial Adder 245
4.3 Boolean Equation 123 6.6 Parallel Addition 246
4.4 Canonical Sum of Product (SOP)/Minterm 6.7 Binary Multiplier 247
Representation 124 6.8 Binary Division 250
4.5 Canonical Product of Sum (POS)/Maxterm 6.9 Arithmetic Logic Units (ALU) 251
Representation 126 6.10 Digital Comparators 255
4.6 Minterm vs. Maxterm 128 Summary 258
4.7 Conversion between Canonical SOP and Multiple Choice Questions 258
Canonical POS Forms 129 Review Questions 260
4.8 Development of Truth Table from Logic
7. FLIP-FLOPS 262
Expression 130
7.1 Introduction 262
4.9 Logic Simplification using Boolean
Algebra 132 7.2 Inverter with Feedback 263
4.10 Karnaugh Maps 137 7.3 Two Inverters form a Memory Cell 263
4.11 Construction of Karnaugh Maps from Logic 7.4 Memory Cell using NAND and NOR
Expression 144 Gates 263
4.12 Logic Simplification using Karnaugh 7.5 Latch 264
Maps 146 7.6 S-R Latch using NOR Gates 265
4.13 Product of Sums Simplification using Karnaugh 7.7 S-R Latch using NAND Gate 266
Maps 148 7.8 S-R Latch with Enable 268
4.14 Don’t Cares 150 7.9 The D Latch 269
4.15 Minimisation of Simultaneous Functions 154 7.10 D Latch with Enable 269
4.16 Variable Mapping 157 7.11 Flip-Flops 271
4.17 Tabular Method of Minimisation 159 7.12 Edge-triggered S-R Flip Flop 271
Summary 168 7.13 Cascading S-R Flip-Flops 272
Multiple Choice Questions 168 7.14 S-R Flip-Flop with Asynchronous Inputs 273
Review Questions 169 7.15 Edge-Triggered D Flip-Flops 275
5. COMBINATIONAL LOGIC DESIGN 172 7.16 D Flip-Flop with Asynchronous Inputs 276
5.1 Introduction 172 7.17 The J-K Flip-Flop 277
5.2 Combinational Logic Design 172 7.18 T Flip-Flop 280
5.3 Decoders 174 7.19 Conversion from One Type of Flip-Flop to
5.4 Encoders 183 Another Type 283
5.5 Priority Encoders 186 7.20 Operating Characteristics of Flip-Flops 287
5.6 Multiplexers 190 7.21 Applications of Flip-Flops 289
5.7 Demultiplexer 201 7.22 Flip-Flop ICs 292
5.8 Code Conversion using Logic Gates and MSI Summary 297
ICs 209 Multiple Choice Questions 297
5.9 Hazards 220 Review Questions 298
5.10 Fault Detection of Combinational Logic
8. SEQUENTIAL CIRCUITS 302
Circuit 226
8.1 Introduction 302
Summary 231
8.2 Register 302
Multiple Choice Questions 231
8.3 Shift Register 303
Review Questions 232
8.4 Classification of Shift Register 303
6. ARITHMETIC LOGIC CIRCUITS 234 8.5 Unidirectional Shift Registers 304
6.1 Introduction 234 8.6 Bi-directional Shift Registers 304
6.2 Binary Addition 234 8.7 Serial In-Parallel Out (SIPO) Shift
 Contents ix

Registers 305 Multiple Choice Questions 392

8.8 Serial In-Serial Out Shift Registers 307 Review Questions 394
8.9 Parallel In-Parallel Out Shift Registers 309
8.10 Parallel In-Serial Out Shift Registers 309 10. MULTIVIBRATORS 397
8.11 Buffer Register 310 10.1 Introduction 397
8.12 Universal Shift Register 311 10.2 Classification of Multivibrators 397
8.13 Universal Shift Register using MUX 314 10.3 Clock Oscillator using BJTs 398
8.14 Applications of Shift Registers 315 10.4 Monostable Multivibrator using BJTs 400
8.15 Counter 318 10.5 Bistable Multivibrator using BJTs 401
8.16 Classification of Counter 318 10.6 Astable Multrivibrator using NOT Gates 402
8.17 Asynchronous (Ripple) Counters 319 10.7 Monostable Multrivibrator using NAND
8.18 Asynchronous Decade Counters 323 Gates 405
8.19 Simultaneous Up-down Counter 324 10.8 Multivibrator using OP AMPs 405
8.20 Asynchronous Up-down Counters 324 10.9 555 Timer 415
8.21 Propagation Delay in Asynchronous 10.10 Applications of 555 Timer 422
Counter 325 10.11 556 Timer 424
8.22 Asynchronous Counter ICs 326 10.12 74121 Monostable Multivibrator 426
8.23 Synchronous Counters 328 10.13 74122 Retriggerable Monostable
8.24 Synchronous Down Counter 330 Multivibrator 428
8.25 Synchronous Up-down Counters 330 10.14 Retriggerable Monostable Multivibrator IC
8.26 Synchronous Decade Counters 331 74123 431
8.27 Propagation Delay in Synchronous Summary 433
Counter 332 Multiple Choice Questions 433
8.28 Synchronous Counter ICs 333 Review Questions 435
8.29 MOD n Counter 335
8.30 Synchronous Counter Design Steps 337
11. ANALOG DIGITAL CONVERSION 437
8.31 Cascade Counters 340
11.1 Introduction 437
8.32 Programmable or Presettable Counters 342
11.2 Sample and Hold Circuit 438
8.33 Self Starting and Self Correcting
Counters 342 11.3 Quantisation 441
8.34 Counter Applications 344 11.4 Binary Digit Weight 442
Summary 347 11.5 Operational Amplifiers 443
Multiple Choice Questions 347 11.6 Digital to Analog Converters (DAC) 443
Review Questions 351 11.7 Extended Capacity of DAC 454
11.8 Current Mode DAC 455
9. SEQUENTIAL CIRCUITS DESIGN 356
11.9 Switched Capacitor DAC 456
9.1 Introduction 356
11.10 D/A Converter Specification 457
9.2 Sequential Circuit Model 357
11.11 DAC ICs 459
9.3 Classification of Sequential Circuits 357
11.12 ADC Converter 461
9.4 State Table 359
11.13 Medium Speed Analog to Digital
9.5 State Diagram 359
Converters 470
9.6 State Equation 361
11.14 High Speed Analog to Digital
9.7 Design Procedure of Synchronous Sequential
Converters 472
Circuits 361
11.15 Specification of ADC 474
9.8 State Reduction of Synchronous Sequential
Circuits 374 11.16 ADC ICs 476
9.9 Asynchronous Sequential Circuits 378 11.17 Bipolar DAC and ADC 478
9.10 Design Procedure of Asynchronous Sequential 11.18 Applications of DAC and ADC 481
Circuits 379 Summary 481
9.11 Algorithmic State Machines (ASM) 384 Multiple Choice Questions 481
Summary 392 Review Questions 483
 x Contents

12. SEMICONDUCTOR MEMORIES 485 15. LABORATORY EXPERIMENTS 643

12.1 Introduction 485 15.1 Introduction 643
12.2 Classification of Memory 486 15.2 Development of Instruction Manual for
12.3 Memory Organisation 488 Laboratory Experiments 644
12.4 Memory Operation 488 15.3 Experiment on Basic Logic Circuits using
12.5 Semiconductor Read-Only Memories 490 Diodes and Transistors 646
12.6 Random-Access Memory (RAM) 506 15.4 Experiment on Basic Logic Circuits using Logic
12.7 Sequential Memory 520 Gates 649
12.8 Charge-Coupled Device (CCD) 527 15.5 Experiment on Combinational Logic Circuits
12.9 Magnetic Disks Memory 530 using Logic Gates 651
12.10 Content-Addressable Memory (CAM) 536 15.6 Experiment on Flip-Flops 654
12.11 Advance Memory 540 15.7 Experiment on Register 656
Summary 542 15.8 Experiment on Seven Segment Display and
Decoder Driver 658
Multiple Choice Questions 542
15.9 Experiment on Counters 659
Review Questions 544
15.10 Experiment on Cascade Counters 662
13. PROGRAMMABLE LOGIC DEVICES 546 15.11 Experiment on Self Starting and Self Correcting
13.1 Introduction 546 Counters 664
13.2 Programmable Read Only Memory (PROM) 15.12 Experiment on Sequence Generator 666
Devices 548 15.13 Experiment on Up-down Counter 667
13.3 Programmable Logic 558 15.14 Experiment on Multivibrators 669
13.4 Programmable Logic Array (PLA) 558 15.15 Experiments on DAC 672
13.5 Programmable Array Logic (PAL) 568 15.16 Experiment on ADC 673
13.6 Comparison between PROM, PAL, and 15.17 Experiment on VHDL Simulation of Digital
PLA 579 System 675
13.7 Simple Programmable Logic Devices Summary 678
(SPLDs) 582 Review Questions 678
13.8 Complex Programmable Logic Device
(CPLDs) 583 Appendix A: IEEE Standard Symbols 681
13.9 Field Programmable Gate Array (FPGA) 585 Appendix B: Pin Diagram of Logic Gates 692
Summary 589 Appendix C: Glossary 693
Multiple Choice Questions 589 Appendix D: Answers of Multiple Choice Questions 701
Review Questions 590 Index 703
14. COMPUTER AIDED DIGITAL SYSTEM DESIGN 592
14.1 Introduction 592
14.2 Computer Aided Digital System Design 592
14.3 Computer Aided Design (CAD) Tools 594
14.4 Hardware Description Language (HDL) 595
14.5 Very High Speed Integrated Circuit Hardware
Description Languages (VHDL) 597
14.6 Verilog HDL 629
Summary 639
Multiple Choice Questions 640
Review Questions 640
 PREFACE
Digital technology has a wide range of applications today and is witnessing tremendous advancement from simple logic
gates to Field Programmable Gates Arrays (FPGAs). Due to its growing importance, this subject has been incorporated
in undergraduate courses of Electrical, Instrumentation, Electronics, Computer Science & Engineering, and Information
Technology.
Rationale
It has been observed that majority of the books available on the subject cover only digital electronics principles without
any focus on the practical applications. Since almost none of the reference books have syllabus compatibility and right
pedagogy, many students find it difficult to conceptualise the subject. Feedback received from students and teachers
have strongly recommended the need for a single book that would cover all topics as per the university curriculum. This
book—an outcome of my vast experience of teaching digital electronics at S.S.G.M. College of Engineering, Shegaon and
Punjab Engineering College, Chandigarh—abridges the gap between the principles and its practices followed in digital
electronics. Here, I must particularly mention Prof. Kanchandhani of S.S.G.M. College of Engineering, Shegaon (author
of Power Electronics) for inspiring me to write a book that would deal with digital electronics principles and practical
experiments using hardware as well as software, thereby providing the requisite foundation in the subject to our students.
Users
This text is particularly well suited for the undergraduate students of CSE, IT, ECE, EEE, and Electronics & Instrumentation
Engineering. It will also be a useful reference for students of BSc and MSc (Computer Science/IT/Electronics), BCA/
MCA, polytechnics, diploma and DOEACC courses in Computer Sciences.
Prerequistes
This book is intended for undergraduate and postgraduate students in electrical engineering, researchers, hardware
designers and teachers. This subject requires no prerequisites other than a basic understanding of analog electronics and
algebra. Undergraduate and polytechnic students without prior knowledge of digital electronics can also grasp the subject
due to lucid and step-by-step explanation of concepts throughout the book. Principles of operation are explained using
examples and solved problems that range from simple to complex. After studying this book, students will be thoroughly
equipped to excel in semester as well as competitive examinations.
Goals and Coverage
This book has been designed to provide working knowledge about digital logic elements and develop any digital system
with logic elements. It covers the following areas—number system, boolean algebra, logic gates, digital logic family,
combinational logic circuits design, arithmetic logic unit, flip-flops, sequential circuits and their design, multivibrators, DAC
and ADC, digital memory, fundamental knowledge of VLSI, PLDs, CPLDs and FPGAs, computer-aided digital system
design, programming in VHDL and Verilog, and experiments on digital electronics using hardware and software. Hands-on
practice with hardware and computer-aided design tools for digital system design will enhance the skills of students.
Features
The book begins with a discussion on the fundamental concepts of digital electronics such as number systems, boolean
algebra, logic families followed by topics (like combinational and sequential logic, multivibrators, A/D conversion and
memories) related to design and analysis of digital systems and finally, covers basics of digital design using VHDL and
Verilog HDL.
 xii Preface

The features of the book are given below:

ã Instructional objectives of each chapter have been written in a very specific manner.
ã The concepts are concisely explained and supported with numerous examples, illustrations, equations, tables and
circuit diagrams.
ã Step-wise methodology for explaining solved examples.
ã A brief summary of topics has been presented at the end of each chapter.
ã The language used is simple and coherent.
ã Hands-on practice with hardware, ICs, CAD tools and VHDL for designing a digital system.
ã The book provides objective, theoretical and numerical problems for testing and enhancing one’s subject-related
knowledge and understanding.
ã This book contains multiple choice questions and review questions at the end of each chapter. The objective
questions would be helpful in the preparation of competitive examinations.
ã References and website addresses provide pointers to further in-depth information.
ã Alphabetical glossary with explanation of key terms has been provided in Appendix C.
ã Strong pedagogy includes:
• Solved examples : 179
• Multiple choice questions : 278
• Review questions (theoretical and numerical): 352
• Laboratory experiments: 15
Organisation
This book is organised into 15 chapters and 4 appendices. Chapters 1 to 6 are devoted to combinational logic design
whereas Chapters 7 to 14 cover sequential logic circuit design. Electrical engineering students usually follow these
courses within one semester dealing with Chapters 1 to 5, Chapters 7 to 9, Chapter 11 and Chapter 14. This book can
also be used in a Master’s course on Digital System Design and as a reference text for graduate engineers working in
their fields.
Chapter 1 presents the basic concepts of number system, analog and digital systems with their limitations. This
chapter provides binary arithmetic, signed magnitude, one’s complement, two’s complement, various codes such as BCD,
packed BCD, gray code, XS3 code, ASCII code, EBCDIC code, parity bit, error detecting code and code conversion
along with their applications in detail.
Chapter 2 describes the basic postulates and theorems of boolean algebra and various logic operations. The
correlation between boolean expression and implementation using logic gates has been explained. The operation of logic
gates with logic diagram, positive logic and negative logic, DeMorgan’s theorem, consensus theorem and simplification
of logic circuits are also incorporated.
Chapter 3 deals with various digital logic families and their characteristics. The TTL logic gates, characteristics of
TTL, MOS logic gates, MOS characteristics, CMOS gates, CMOS characteristics, interfacing of TTL and CMOS logic
family, and comparison between CMOS over TTL are explained elaborately.
Chapter 4 explains combinational logic circuit. The different elements of combinational logic, SOP and POS
representation, conversion between SOP and POS forms are discussed. The various methods of minimisation and
simplification of Boolean expression, karnaugh maps, minimisation of simultaneous functions, variable mapping and
tabular method of minimisation are elaborately explained.
Chapter 5 deals with design and implementation of combinational logic circuits such as decoder encoders, priority
encoders, multiplexers, and de-multiplexers. The code conversion using logic gates and MSI ICs, hazards and fault
detection of combinational logic circuit are highlighted.
 Preface xiii

Chapter 6 gives a detailed exposition of arithmetic and logic circuits such as binary addition, subtraction, carry
look-ahead addition, serial and parallel adder, binary multiplier, binary division, Arithmetic Logic Units (ALU), and
digital comparators.
Chapter 7 elucidates various types of latches and flip-flops such as S-R Latch using gates, D latch, edge - triggered
S-R, D, T, and JK flip-flop, flip-flop with asynchronous inputs, conversion from one type of flip-flop to another type,
operating characteristics and applications of flip-flops. The structures of flip-flops are discussed highlighting the difference
between latch and flip-flops with level-triggered and edge-triggered.
Chapter 8 covers sequential circuits such as register, shift register, buffer register, universal shift register,
applications of shift registers, asynchronous (Ripple) and synchronous counters, propagation delay in counter, mod-n
counter, counter design steps, cascade counters, programmable or pre-settable counters, self-starting and self-correcting
counters, and counter applications.
Chapter 9 deals with sequential circuits design. The sequential circuit model, state table, state diagram, state equation,
design procedure of sequential circuits, state reduction of synchronous sequential circuits, and asynchronous sequential
circuits are discussed. The Algorithmic State Machines (ASM), ASM Chart, difference between conventional flow chart
and ASM Chart are discussed in this chapter. Abundant examples of sequential circuits design are incorporated.
Chapter 10 gives the basic concept of multivibrators and types of multivibrators such as monostable, bistable, and
astable multivibrators. The 555 timer and its applications, 556 timer, 74121 monostable multivibrator, 74122 and 74123
retriggerable monostable multivibrators are explained.
Chapter 11 covers various methods of Digital to Analog Converters (DAC) and Analog to Digital Converters
(ADC), specification of ADC and DAC and applications of ADC and DAC.
Chapter 12 describes the fundamental concept of semiconductor memories, classification of memory, memory
organisation and its operation. Read Only Memory (ROM), Random Access Memory (RAM), sequential memory, Charge
Coupled Device (CCD), magnetic disk memory, and Content Addressesable Memory (CAM) are explained.
Chapter 13 covers the various programmable logic devices such as PROM, PLA and PAL. The comparison
between PROM, PAL and PLA is highlighted, and fundamental knowledge of Simple Programmable Logic Devices
(SPLDs), Complex Programmable Logic Devices (CPLDs) and Field Programmable Gate Array (FPGA) are discussed.
Chapter 14 deals with computer aided digital systems design. The basic concept of Computer Aided Design
(CAD), CAD tools, Hardware Description Language (HDL), Very high speed integrated circuit Hardware Description
Language (VHDL) and Verilog HDL are elaborately discussed.
Chapter 15 presents laboratory experiments that can be performed with hardware and be simulated with software.
Experiments on basic logic circuits using diodes, transistors and logic gates, combinational logic circuits, flip-flops,
registers, seven-segment display and decoder driver, counters, cascade counters, self-starting and self-correcting
counters, sequence generator, up-down counter, multivibrators, DAC and ADC are presented with their required formal
information. Experiments on VHDL simulation of digital systems are also incorporated.
Appendix A is a discussion on the IEEE standard graphic symbols for logic functions.
Appendix B provides the pin diagram of logic gates.
Appendix C contains glossary with explanation of important terms.
Appendix D includes answers of multiple choice questions.
Web Resources
This book is accompanied with an exhaustive online learning centre designed to provide valuable resources for instructors and
students.
For Instructors: For Students:
• Solutions Manual • Test Bank (includes Additional Questions for Practice)
• PowerPoint Slides • Tutorials on Digital Electronics
• Lab Assignments • Solutions to Selected Questions
• Chapter-wise Objectives
• References and Website Addresses
 xiv Preface

Acknowledgements
The author has received inspiration and co-operation for completion of this book from Dr Gurnam Singh, PEC, Chandigarh;
Dr S Chatterjee, NITTTR, Chandigarh; Dr S K Bhattachariya, Former Director, NITTTR, Kolkata; Prof Amitabha Sinha,
Director School of Information Technology, WBUT; Dr C K Chanda and Dr P Shyam, Bengal Engineering College,
Shibpur; Dr P Sarkar, Professor and Head Electrical, Dr S Chattopadhay, Assistant Professor, and Dr S Pal, Senior
Lecturer, NITTTR, Kolkata. The author is thankful to the Electrical Engineering staff, specially A K Das, N K Sarkar,
S Roy Choudhury, and Surojit Mallick for their valuable assistance. Special thanks go to the Tata McGraw Hill team,
namely, Vibha Mahajan, Shalini Jha, Surabhi Shukla, Surbhi Suman, Dipika Dey, Anjali Razdan and Baldev Raj for their
excellent publishing initiatives.
A note of acknowledgement is due to the following reviewers for their valuable suggestions.

Arvind Rajawat B Chakraborty

Maulana Azad National Institute of Technology (MANIT) National Institute of Technology, Durgapur,
Bhopal, Madhya Pradesh West Bengal
Kanak Saxena
Rakesh K Sarin Samrat Ashok Technological Institute (SATI),
Dr B R Ambedkar National Institute of Technology, Vidisha, Madhya Pradesh
Jalandhar, Punjab
Bijoy Bandyopadhyay
Pradeep Kumar University of Calcutta, Kolkata,
Amity School of Engineering & Technology, West Bengal
Noida, Uttar Pradesh Abir Chattopadhyay
Camellia School of Engineering and Technology,
Sampath Kumar
West Bengal
JSS Academy of Technical Education,
Noida, Uttar Pradesh V J Dongre
Government Polytechnic, Nagpur, Maharashtra
Sangeeta Shukla
M G Sumithra
Sagar Institute of Research and Technology,
Bannari Amman Institute of Technology,
Bhopal, Madhya Pradesh
Erode, Tamil Nadu
Sunil Mathur Thimmarayaswamy K
Maharaja Agrasen Institute of Technology, B M Sreenivasaiah College of Engineering,
New Delhi Bangalore, Karnataka

The readers of the book are encouraged to send their comments, queries and suggestions at the following email
id—[email protected] (kindly mention the title and author name in the subject line).
SOUMITRA KUMAR MANDAL
 CHAPTER

1
NUMBER SYSTEM
1.1 INTRODUCTION
In science, technology, business, and all other fields, we always deal with quantities. Quantities can be
measured, monitored, recorded, manipulated arithmetically, observed, or in some other way utilised in
most physical systems. It is necessary to represent their values efficiently and accurately. Quantities are
represented by two ways: analog and digital. In analog representation, a quantity is represented by a volt-
age or current. Analog quantities have an important characteristic: they are continuous and can vary in
wide range of values. Figure 1.1 shows the analog voltage variation with time.
In digital representation, the quantities are represented by symbols called digits. In a digital watch, the
time of day is represented in the form of decimal digits which stand for hours, minutes and seconds.
Though the time of day changes continuously, the digital watch reading does not change continuously.
It changes in steps of one per minute or per second. Therefore, this digital representation changes in
discrete steps, as compared to an analog watch, where the dial reading changes continuously. The ana-
log voltage is digitalised and represented by discrete steps as shown in Fig. 1.2. The major difference
between analog and digital quantities can be simply stated that analog signal is continuous and digital
signal is discrete one.

Fig. 1.1 Analog voltage variation

Fig. 1.2 Digital voltage represented by sampled or quantised levels

 2 Digital Electronics: Principles and Applications

1.2 ANALOG SYSTEMS

Any analog system consists of integrated circuits of transistors to perform different operations on
any physical quantity which is represented in analog form. In an analog circuit, transistors operate
in between blocked and saturated states, and an analog datum is represented by a continuous signal.
This continuous analog signal is either voltage or current. When it is voltage, the amplitude of voltage
can be varied in between the ground and power supply voltages (+VCC or –VCC). Consequently, the
output signal can be varied from zero to maximum positive or negative value of analog system.
Examples of analog systems are measurement of voltage, current, power, energy and any physical
quantity (force, displacement, and speed, etc.), audio amplifier, magnetic tape recording, cell phones,
data transmission, and video recording. Since nineteenth century, we are using radio but the normal
radio still uses analog transmission. Analog system is also very popular for video recording. In
video recording system, information is video and audio. When information is recorded by an analog
system, the recording has a very high quality. To transmit the recorded information from one place to
other, initially it is modulated directly with a carrier wave and then it is transmitted through air, cable,
and satellite. During this transmission, the carrier and modulated signal will loose amplitude and
some noise is also introduced to the carrier and its modulated signal due to interference. Therefore,
receiving end signal always has a lower quality than the transmitted signal and the modulated signal
will also be of lower quality than the original signal. In this way, analog transmission system is
unable to maintain the quality.
The original cell phone technology is analog, but analog cell phones are obsolete due to lot
of disadvantages and presently it is replaced by digital cell phone. The disadvantages of analog
cell phone are as follows: (i) the battery life is about one fourth of that of a digital phone, (ii)
they are more susceptible to noise and disturbance, (iii) the voice quality is not clear, (iv) new
features, namely date, time, text messaging, internet are not available on analog cell phones, (v)
they need more power and thus can potentially disturb other electronics equipments. From the above
discussion, it is very clear that analog systems have a lot of disadvantages. Now-a-days, digital
systems are used due to greater flexibility, high accuracy, more generality, and the design itself is
technology independent.
1.3 DIGITAL SYSTEMS
In digital systems, signals are represented
in binary form. As a binary quantity can
be represented by two operating states
called ‘0’ and ‘1’, it may be transmitted
in the form of electronic OFF and ON
pulses respectively. ON means binary
‘1’ and OFF means binary ‘0’. When
these pulses are received by any digital
system, they are processed. The typical
representation of voltage is shown in
Fig. 1.3 (a) Voltage representation of binary ‘1’ and Fig. 1.3. Binary ‘1’ means any voltage
binary ‘0’ (b) A digital signal between 2V to 5V and binary ‘0’ states
 Number System 3

any voltage between 0V to 0.8V. It will be noted that voltage between 0.8V to 2V is not used and
this may create error in a digital circuit.
In a digital system, all communication within the system are carried out in a digital manner. Usually,
the digital communication means that all signals within the system can have only two possible states of
OFF and ON or ‘0’ and ‘1’. Digital electronics is the branch of electronics and these electronic systems
are composed of elements that exhibit this digital behavior. As a digital system can only exhibit one of
two possible states, they are usually easier to understand than analog systems, which can have an infinite
number of states. The field of digital electronics is very exciting, and fast changing. Advances in digital
electronics make it possible to do very complex system in a simple manner. Digital electronics are a key
element of many products, namely personal computers, sophisticated sewing machines, microwave ov-
ens, compact disc players, and video cassette players, etc. The brains of all of these products and many
parts of these products are composed of digital electronics. Presently, it is very difficult to survive in this
world without digital electronics.

1.3.1 Advantages of Digital Systems

In analog systems, the noise is transmitted from one component to the next and it increases with the
number of interconnected hardware elements between inputs and outputs. So very careful design and
manufacturing procedures are required for the analog system, thus increasing the price of the product. If
digital system replace the analog system, the following advantages are possible:
• It is simple to design. Exact values of voltage or current are not important, but only the range,
HIGH or LOW in which they fall.
• The storage of digital information is easy.
• Accuracy and precision are better than analog signals.
• Operation of digital system can be programmed and variety of operation can be done. The analog
system can also be programmed, but the variety and complexity of the available operations is very
limited.
• Digital circuits are less affected by noise. We can easily distinguish the binary ‘0’ and binary ‘1’
signal, though there are some noises in signal.
• In digital ICs, a large number of digital circuits can be incorporated compared to analog ICs.
• Simple, inexpensive and safe implementation of complex data processing algorithms.
• Simple design and implementation procedures.
• High immunity to noise (virtually no loss of information due to noise). Each digital component
behaves as a filter eliminating the noise on its inputs.

1.3.2 Disadvantages of Digital Systems

Every system has some disadvantages and few drawbacks. Similarly, the disadvantages of digital
systems are as follows:
 4 Digital Electronics: Principles and Applications

• Large numbers of transistors are required for performing some operations that can be implemented
using simpler analog hardware. For instance, additions and multiplications by constants can be
easily implemented using analog circuits based on operational amplifiers.
• In some situations, the operation speed is lower than the speed offered by equivalent analog
circuits.

1.4 LIMITATIONS OF DIGITAL SYSTEMS

In real world, all physical quantities are analog in nature. These quantities are used as input signals of
system and monitored for controlling the system. To take advantage of digital electronics, the following
steps are followed:
Step 1 Convert the analog inputs to digital form by using analog to digital converter, ADC.
Step 2 Process the digital information.
Step 3 Convert the digital outputs back to analog form by digital to analog converter, DAC.

The block diagram of speed control system is shown in Fig.1.4 and this speed control system requires
analog to digital converter for converting analog signals to digital form. Firstly, the speed is measured in
analog form and then converted into digital form by using analog to digital converter. This digital speed
signal is used as input of digital signal processor. After that digital signal is processed by digital signal
processor circuit, its digital output is fed to digital to analog converter. The digital to analog converter
converts the digital signal to analog form. This analog output is used as an input of the controller and
controller’s output takes necessary action to adjust the speed. Therefore, it is confirmed from the above
system that the data conversion is the major drawback of application of digital electronics.

Fig. 1.4 Block diagram of speed control system that requires analog to digital converter

1.5 DIGITAL NUMBER SYSTEMS

In general, numbers are represented using ‘10’ symbols or figures. These ‘10’ symbols or figures are 0,
1, 2, 3, 4, 5, 6, 7, 8, 9. The significance of each figure depends on its position inside the string of figures
used to represent the number. These are numbers represented in “base 10”. In digital system, there are
many number systems but most commonly used number systems are the decimal, binary, octal, and
 Number System 5

hexadecimal systems. The decimal system is the most familiar number system that we commonly use
in everyday life.

1.5.1 Decimal Number

The decimal number is composed of ‘10’ symbols. These ‘10’ symbols are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9. By
using these symbols we can write any quantity. The decimal system is also called the base ‘10’ system
as it has ‘10’ digits. The representation of decimal number is shown in Table 1.1.

Table 1.1 Representation of decimal number

103 = 1000 102 = 100 101 = 10 100 = 1 . 10–1 = 0.1 10–2 = 0.01 10–3 = 0.001
Most Decimal Least
Significant point Significant
Digit (MSD) Digit (LSD)

The example of decimal numbers are 6897 and 27.95. The decimal number (6897)10 can be written
as
(6897)10 = 6 × 103 + 8 × 102 + 9 × 101 + 7 × 10° and the number (27.95)10 can be represented
as
(27.95)10 = 2 × 101 + 7 × 10° + 9 × 10–1 + 5 × 10–2.
Any positive integer can be represented by symbol or digits in a positional number system. The
number N can be represented in the equation form

N = dn dn–1 dn–2 …….. d3 d2 d1 d0 . d–1 d–2 d–3 . . . d–n–1 d–n (1.1)

Ø

Decimal Point

The di represents the digits, which have ten values ranging from 0 to 9. The value of ‘n’ may be any
real integer to express the number N. The digit on the extreme right is called the least significant digit
(LSD) because it has the lowest positional value of 1 for integers. The next digit to the left of this least
significant digit has the positional value of 10; the next, 100; and so on. The digit on the extreme left
is called the most significant digit (MSD) as it has the highest positional value. The use of positional
numbers can be extended to fractions by adding a decimal point and letting digits to the right of the
decimal represent 1/10ths, 1/100ths, and so on, depending on position. The number N can be determined
from equation (1.2).

N = dn × 10n + dn–1 × 10n–1 + . . . . . . . + d1 × 101 + d0 × 100 + d–1 × 10–1 + d–2 × 10–2 . . . (1.2)

1.5.2 General Positional Numbers

Generally, we use ‘base 10’ in decimal system to represent a number, but a number system can have any
base. The base of a number system is also called the radix. The rules concerning the decimal number
 6 Digital Electronics: Principles and Applications

representation in “base 10” can be extended to 2 (binary), 8 (octal), and 16 (hexadecimal) based number
system. The generalised representation of a positional number to any base b is given by equation (1.3)
and (1.4).

Nb = dn dn–1 dn–2 . . . . . . d3 d2 d1 d0 . d–1 d–2 d–3 . . . d–n–1 d–n …… (1.3)

↑
Radix Point
The equation (1.3) means

Nb = dn × bn + . . . + d0 × b0 + d–1, × b–1 + d–2 × b–2 …… + d–n × b–n …… (1.4)

where, the di represents the digits, b is the base or radix, and the “.” represents the radix point .
The notation of generalised positional number system is Nb. Here the subscript denotes the base.

1.5.3 Binary Number

The simplest information is either TRUE or FALSE. This can
be represented by two voltage levels: 5 Volts for TRUE and 0
Volts for FALSE or Switch is ON and switch is OFF as shown
in Fig. 1.5. A voltage signal, which has only two possibilities, is
represented by a BIT. BIT stands for Binary Digit. Binary means:
only 2 possible values. Advantages of using binary representation
are simple to implement in electronic hardware (switch) and
good tolerance to noise. FALSE means ‘0’ and TRUE means ‘1’.
Electronic storage devices are used two distinct different states:
‘0’ and ‘1’. So, these electronic storage devices use a number
Fig. 1.5 Representation of binary
by switch ON and OFF system based on only two digits. In binary number system, the
digits are zero (0) and one (1) and the radix/base is two (2). The
example of an binary number is

N = 10101010112 = (1010101011)2
where, the subscript ‘2’ denoting the base of binary number system.
By using the formula of the general position number system, the number N can be presented in terms
of base 10 or decimal numbers.
N = 1 × 29 + 0 × 28 + 1 × 27 + 0 × 26 + 1 × 25 + 0 × 24 + 1 × 23 + 0 × 22 + 1 × 21 + 1 × 20
= 512 + 0 +128 + 0 + 32 + 16 + 8 + 2 + 1 = (699)10
It is very convenient to determine the equivalent decimal number if we represent the positional value
of each of the digits existing in binary. After that, we add the positional values corresponding to nonzero
digits ‘1’. The positional value of each digit is given below:
512 256 128 64 32 16 8 4 2 1
 Number System 7

In the binary system, there are only two symbols or possible digit values, ‘0’ and ‘1’. This base-2
system can be used to represent any quantity that can be represented in decimal. Table 1.2 shows the
representation of binary number.

Table 1.2 Representation of binary number

23 = 8 22 = 4 21 = 2 20 = 1 . 2–1 = 1/2 2–2 = 1/4 2–3 = 1/8

Most Binary Least
Significant point Significant
Bit (MSB) Bit (LSB)

The four bit binary number with different possibilities is represented by decimal equivalent as shown
in Table 1.3.

Table 1.3 Four bit binary numbers and it’s decimal equivalent

23=8 22=4 21=2 20=1 Decimal Equivalent

0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
1 0 1 0 10
1 0 1 1 11
1 1 0 0 12
1 1 0 1 13
1 1 1 0 14
1 1 1 1 15

1.5.4 Binary-to-Decimal Conversion

Any binary number can be converted to its decimal equivalent simply by summing together the weights
of the various positions in the binary number, which contain 1. The decimal equivalent of binary number
(111011)2 is (59)10 as shown below:
 8 Digital Electronics: Principles and Applications

(1 1 1 0 1 1) 2 (binary)
25 + 24 + 23 + 0 + 21 + 20 = 32 + 16 + 8 + 0 + 2 + 1
= 5910 (decimal)
and similarly, the binary number (110110101)2 is converted into decimal number (437)10.
11 0 1 1 0 1 0 1 2 (binary)
8 7 5 4 2 0
2 +2 +0+2 +2 +0+2 + 0+2 = 256 + 128 + 0 + 32 + 16 + 0 + 4 + 0 + 1
= 43710 (decimal)
It should be noticed that this method is to find the weights (i.e., powers of 2) for each bit position that
contains a 1, and then to add them up.

1.5.5 Decimal-to-Binary Conversion

There are 2 methods namely reverse of binary to decimal and repetitive division. Each method is
represented in this section.

Reverse of Binary-to-Decimal Method

The decimal number (45)10 can be represented as sum
of 32, 8, ,4, and 1. So, the binary equivalent of (45)10
is (101101)2.
45 10 = 32 + 0 + 8 + 4 + 0 + 1 (decimal) = 25 + 0 + 23
+ 22 + 0 + 20 = 1 0 1 1 0 12 (binary)
Repetitive Division
This method uses repeated division by 2. The flow
chart for converting decimal number into binary by
repeated division is shown in Fig. 1.6. For example,
to convert 2510 to binary is given below:
25/2 = 12 + remainder 1 1 LSB
Least Significant Bit)
12/2 = 6 + remainder 0 0
6/2 = 3 + remainder 0 0
3/2 = 1 + remainder 1 1
1/2 = 0 + remainder 1 1 MSB
(Most Significant Bit)
Result 2510 = 1 1 0 0 12

The repetitive division method of conversion

Fig. 1.6 Flow chart for converting decimal
number into binary by repeated of decimal number to binary number can also be
division represented as shown below:
 Number System 9

600 / 2 = 300 remainder 0

300 / 2 = 150 remainder 0
150 / 2 = 75 remainder 0
75 / 2 = 37 remainder 1
37 / 2 = 18 remainder 1
18 / 2 = 9 remainder 0
9 /2= 4 remainder 1
4 /2= 2 remainder 0
2 /2= 1 remainder 0
1 /2= 0 remainder 1
1 0 0 1 0 1 1 0 0 0

MSB LSB
All of the remainders from the division are then arranged in reverse order, from MSB to LSB
to form the correct binary sequence. Therefore, the binary equivalent of decimal number (600)10 is
(1001011000)2. The binary equivalent values for 0-15 are presented in Table1.4.
Table 1.4 The binary equivalent values for 0–15

Decimal Binary Decimal Binary

102 101 100 23 22 21 20 102 101 100 23 22 21 20
0 0 0 0 0 0 0 0 0 8 1 0 0 0
0 0 1 0 0 0 1 0 0 9 1 0 0 1
0 0 2 0 0 1 0 0 1 0 1 0 1 0
0 0 3 0 0 1 1 0 1 1 1 0 1 1
0 0 4 0 1 0 0 0 1 2 1 1 0 0
0 0 5 0 1 0 1 0 1 3 1 1 0 1
0 0 6 0 1 1 0 0 1 4 1 1 1 0
0 0 7 0 1 1 1 0 1 5 1 1 1 1

1.5.6 Conversion of Fractional Decimal Number into Binary

To convert a fractional decimal number to a binary number, we multiply the fractional part of the number
repeatedly by base 2. The integer part obtained after multiplication is noted separately and the fractional
part is again considered for further multiplication. This process will continue till a zero fractional part
has been obtained. In this conversion method, the first integer is Most Significant Bit (MSB) and the last
integer is the Least Significant Bit (LSB) of the fractional decimal number. The flow chart of conversion
of fractional decimal number into binary is depicted in Fig. 1.7.
For example, the conversion of (0.625)10 into binary is explained below:
To convert 0.625 decimal to binary, the computation uses repeated multiplication by 2. The integer
part and fractional part of the product are separated after each multiplication.
 10 Digital Electronics: Principles and Applications

Fraction Product Fractional Integer

Number part Part
.625 .625 × 2 = 1.25 .25 1 MSB
.25 .25 × 2 = .5 .5 0
.5 .5 × 2 = 1 0 1 LSB

The binary equivalent of (.625)10 is (.101)2. Similarly, the

binary equivalent of .475 is given below:

Fraction Product Fractional part Integer Part

Number
.475 .475 × 2 = .95 .95 0 MSB
.95 .95 × 2 = 1.9 .9 1
.9 .9 × 2 = 1.8 .8 1
.8 .8 × 2 = 1.6 .6 1
.6 .6 × 2 = 1.2 .2 1
.2 .2 × 2 = .4 .4 0
.4 .4 × 2 = .8 .8 0
.8 .8 × 2 = 1.6 .6 1
. . .
. . .
Fig. 1.7 Flow chart for conversion
of fractional decimal The binary equivalent of (.475)10 is (.01111001100…)2.
number into binary

Example 1.1 Convert the following binary numbers to decimal numbers

(a) 1110011 (b) 1101.11

� Solution
(a) (1110011)2 = 1 × 26 + 1 × 25 + 1 × 24 + 0 × 23 + 0 × 22 + 1 × 21 + 1 × 20
= 1 × 64 + 1 × 32 + 1 × 16 + 0 × 8 + 0 × 4 + 1 × 2 + 1 × 1
= 64 + 32 + 16 + 2 + 1 = 115
(b) (1101.11)2 = 1 × 23 + 1 × 22 + 0 × 21 + 1 × 20 + 1 × 2–1 + 1 × 2-2
= 1 × 8 + 1 × 4 + 0 × 2 + 1 × 1 + 1 × 0.5 + 1 × 0.25
= 8 + 4 + 1 + 0.5 + 0.25 = 13.75
 Number System 11

Example 1.2 Convert the following decimal numbers to binary numbers

(a) 11 (b) 255
� Solution
(a) Conversion of (11)10 to binary
11/2 = 5 + remainder of 1 1 (Least Significant Bit)
5/2 = 2 + remainder of 1 1
2/2 = 1 + remainder of 0 0
1/2 = 0 + remainder of 1 1(Most Significant Bit)
Result (11)10 = 1 0 1 12
(b) Conversion of (255)10 to binary
255/2 = 127 + remainder of 1 1(Least Significant Bit)
127/2 = 63 + remainder of 1 1
63/2 = 31 + remainder of 1 1
31/2 = 15 + remainder of 1 1
15/2 = 7 + remainder of 1 1
7/2 = 3 + remainder of 1 1
3/2 = 1 + remainder of 1 1
1/2 = 0 + remainder of 1 1(Most Significant Bit)
Result 25510 = 1 1 1 1 1 1 1 12

Example 1.3 Convert the following decimal numbers to binary numbers

(a) 0.72 (b) 24. 625
� Solution
(a) Conversion of (0.72)10 to binary

Fraction Number Product Fractional part Integer Part

0.72 .72 × 2 = 1.44 .44 1 MSB
.44 .44 × 2 = .88 .88 0
.88 .88 × 2 = 1.76 .76 1
.76 .76 × 2 = 1.52 .52 1
.52 .52 × 2 = 1.04 .04 1
.04 .04 × 2 = .08 .08 0
.08 .08 × 2 = .16 .16 0
.16 .16 × 2 = .32 .32 0
.32 .32 × 2 = .64 .64 0
.64 .64 × 2 = 1.28 .28 1
.28 .28 × 2 = .56 .56 0
.56 .56 × 2=1.12 .12 1 LSB

(.72)10 is equal to (0.101110000101)2

 12 Digital Electronics: Principles and Applications

(b) Conversion of (24.625)10 to binary

24/ 2 = 12+ remainder 0 0 (Least Significant Bit)
12/ 2 = 6 + remainder 0 0
6 / 2 = 3 + remainder 0 0
3 / 2 = 1 + remainder 1 1
1 / 2 = 0 + remainder 1 1 (Most Significant Bit)
Result 2410 = 1 1 0 0 02

Fraction Number Product Fractional part Integer Part

.625 .625 × 2 = 1.25 .25 1 MSB
.25 .25 × 2 = .5 .5 0
.5 .5 × 2 = 1 0 1 LSB

(24.625)10 is equal to (11000.101)2

1.5.7 Octal Number

The octal number system has a base of eight, meaning that it has eight possible digits: 0,1,2,3,4,5,6, and
7. The octal number system is shown in Table 1.5.
Table 1.5 Octal number system

83 = 512 82 = 64 81 = 8 80 = 1 . 8–1 = 1/8 8–2 = 1/64 8–3 = 1/512

Most Octal Point Least
Significant Significant
Digit (MSD) Digit (LSD)

1.5.8 Decimal-to-Octal Conversion

Generally, decimal to octal conversion is done by using reverse octal to decimal and repetitive division
method. Both methods are presented below:
Reverse of Octal-to-Decimal Method
The decimal number (20.75)10 can be written as summation of 16 , 4 and 6/8. The decimal number can
be represented by using Table 1.5 as given below:

20.7510 = 2 × (81) + 4 × (80) + 6 × (8–1) = 24.68

Repetitive Division
This method uses repeated division by 8. Figure 1.8 depicted the flow chart for converting decimal
number into by repeated division.
The example is converting 17810 to octal:
178/8 = 22+ remainder 2 2 (Least Significant Digit)
22/ 8 = 2 + remainder 6 6
2 / 8 = 0 + remainder 2 2
(Most Significant Digit)
Result 17810 = 2628
 Number System 13

The repetitive division method of conversion of

decimal number to octal number is also presented
into
602 / 8 = 75 remainder 2
75 / 8 = 9 remainder 3
9 / 8 = 1 remainder 1
1 / 8 = 0 remainder 1

1 1 3 2

MSD LSD
All of the remainders from the division are then
arranged in reverse order, from MSD to LSD to
form the correct octal sequence. Therefore the octal
equivalent of decimal number (602)10 is (1132)8.

1.5.9 Binary-to-Octal/Octal-to-Bi-
nary Conversion
The binary equivalent of octal digits 0 to 7 are Fig. 1.8 Flow chart for converting decimal
number into octal by repeated
presented in Table 1.6. division

Table 1.6 Binary equivalent of octal digit

Octal Digit 0 1 2 3 4 5 6 7
Binary Equivalent 000 001 010 011 100 101 110 111

It is clear from Table 1.6 that each octal digit is represented by three bits of binary digit. The example
of binary to octal conversion is
(111 100 111 010)2 = (111) (100) (111) (010)2 =(7 4 7 2 )8.
Similarly, the octal number (24657)8 can represented by binary number (010) (100) (110) (101)
(111)2= (010100110101111)2.

Example 1.4 Convert the following octal numbers to decimal numbers

(a) 416 (b) 360.15
� Solution
(a) (416)8 = 4 × 82 + 1 × 81 + 6 × 80 = 4 × 64 + 1 × 8 + 6 × 1 = 256 + 8 + 6 = 270
(b) (360.15)8 = 3 × 82 + 6 × 81 + 0 × 80 + 1 × 8–1 + 5 × 8–2 = 3 × 64 + 6 × 8 + 0 × 1 + 1 × 0.125 + 5 × 0.0156
= 192 + 48 + 0.125 + 0.0781 = 240.2031

Example 1.5 Convert the following decimal numbers to octal numbers

(a) 234 (b) 2988.6875
 14 Digital Electronics: Principles and Applications

� Solution
(a) Conversion of (234)10 to octal
234/ 8 = 29+ remainder of 2 2 (Least Significant Digit)
29 / 8 = 3 + remainder of 5 5
3 / 8 = 0 + remainder of 3 3 (Most Significant Digit)
Result 23410 = (352)8
(b) Conversion of (2988.6875)10 to octal
2988/ 8 = 373 + remainder of 4 4 (Least Significant Digit)
373/ 8 = 46 + remainder of 5 5
46 / 8 = 5 + remainder of 6 1
5/8 = 0 + remainder of 5 5(Most Significant Digit)
Result 298810 = (5154)8

Conversion of (0.6875)10 to octal

Fraction Number Product Fractional part Integer Part

0.6875 .6875 × 8 = 5.5 .5 5 MSD
.5 .5 × 8 = 4 .0 4 LSD
(2988.6875)10 is equal to (5104.54)8

Example 1.6 Convert the following octal numbers to binary numbers

(a) 370.526 (b) 2702

� Solution
(a) Conversion of (370.526)8 to binary (370.526)8 = 011 111 000.101 010 110
(b) Conversion of (2702)8 to binary (2702)8 = 010 111 000 010

Example 1.7 Convert the following binary numbers to octal numbers

(a) 101111001110.001 100 (b).111001111

� Solution
(a) Conversion of (101111001110.001 100)2 to octal
(101111001110.001 100)2 = (101) (111) (001) (110). (001) (100) = (5716.14)8
(b) Conversion of (.111001111)2 to octal (.111001111)2 = (.111) (001) (111) = (.717)8

1.5.10 Hexadecimal Number

In hexadecimal system, the base is 16. So, this system has 16 possible digit symbols. It uses the digits
0 through 9 and the letters A, B, C, D, E, and F as the 16 digit symbols. The letters A to F are used for
the values of 10–15. This hexadecimal system is also used extensively in computing. The hexadecimal
equivalent of decimal numbers 0 to 15 is presented in Table 1.7. Table 1.8 shows the hexadecimal
number system.
 Number System 15

Table 1.7 Represent the decimal number into hexadecimal

Decimal Base 10 Hexadecimal Base 16

0 0
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 A
11 B
12 C
13 D
14 E
15 F

Table 1.8 Hexadecimal number system

163 = 4096 162 = 256 161 = 16 160 = 1 . 16–1 = 1/16 16–2 = 1/256 16–3 = 1/4096
Most Hexadeci- Least
Significant mal Point Significant
Digit (MSD) Digit (LSD)

1.5.11 Decimal to Hexadecimal Conversion

Decimal to Hexadecimal conversion can be done by two methods, namely reverse hexadecimal to
decimal and repetitive division. These methods are explained below:

Reverse of Hexadecimal to Decimal Conversion

The conversion of decimal number into hexadecimal number by using Table 1.8 is explained below:
The decimal number (687)10 can be written as summation of 512 (2 × 256), 160 (10 × 16) ñnd 15 (15
× 1). Therefore, hexadecimal equivalent of decimal number can be represented by (687)10 = 2 × (162)
+ 10 × (161) + 15 × (160) = (2AF)16

Repetitive Division Method

For converting decimal to hexadecimal, repeated division method uses successive division by 16. The
flowchart for converting decimal number into hexadecimal by repeated division is depicted in Fig.1.9.
The example of converting 37810 to hexadecimal is given below:
 16 Digital Electronics: Principles and Applications

378/16 = 23+ remainder 10 A

(Least Significant Digit)
23/ 16 = 1 + remainder 7 7
1 / 16 = 0 + remainder 1 1
(Most Significant Digit)
Result (378)10 = (17A)16

To convert a decimal number into hexadecimal,

a similar process is performed as described in binary
and octal. The example is given here the numbers are
successively divided by 16:
(5789)10 / 16 = 361 remainder 13(D)
(361)10 / 16 = 22 remainder 9 (9)
(22)10 / 16 = 1 remainder 6 (6)
(1)10 / 16 = 0 remainder 1 (1)
1 6 9 D

MSD LSD
All of the remainders from the division are then ar-
ranged in reverse order, from MSD to LSD to form the
Fig. 1.9 Flow chart for converting decimal correct hexadecimal sequence. Therefore, the hexa-
number into hexadecimal by
repeated division decimal equivalent of decimal number (5789)10 is
(169D)16.

1.5.12 Binary to Hexadecimal and Hexadecimal to Binary Conversion

Binary equivalent of hexadecimal digits (0 to F) are shown in Table 1.9. It is depicted in this table
that each group of 4 binary digits (bits) is 1 hexadecimal digit. The example of binary to hexadecimal
conversion is given below:
(1111 1011 0011)2 = (1111) (1011) (0011) = (F B 3)16 .
The Hexadecimal number (24657A)16 can be represented by binary number (0010) (0100) (0110)
(0101) (0111) (1010)2 = (0010 0100 0110 0101 0111 1010)2.
Table 1.9 Binary equivalent of hexadecimal digit
Binary Equivalent Hexadecimal Digit
0000 0
0001 1
0010 2
0011 3
0100 4
0101 5
0110 6
0111 7
(Contd.)
 Number System 17

Table 1.9 (Contd.)

1000 8
1001 9
1010 A
1011 B
1100 C
1101 D
1110 E
1111 F

1.5.13 Octal-to-Hexadecimal and Hexadecimal-to-Octal Conversion

Octal-to-Hexadecimal
To convert an octal number to hexadecimal number, the following steps are required:
In first step, the octal number is converted into binary. The second step is regrouping the binary
number in 4 bits and a group starts from the LSB. In third step, the 4 bits group binary number can be
represented by hexadecimal number. The example is given below.
To convert octal number (547)8 to hexadecimal number, step 1, step 2 and step 3 have been presented
in tabular form.
(547)8 = (101 100 111)2 (Binary) Step 1
= (0001) (0110) (0111) Step 2
= (167)16 (Hexadecimal ) Step 3

Hexadecimal-to-Octal Conversion
In hexadecimal to binary conversion, three steps are required. The first step is to convert hexadecimal to
binary. The second step is regrouping the binary number in 3 bits a group which starts from the LSB. In
third step, the groups of 3 bits binary number can be represented by octal numbers. One example is the
conversion of (5A8)16 to Octal number as follows:
To convert hexadecimal number (5A8)16 to octal number, all the three steps are presented below:
5A816 = (0101 1010 1000)2 (Binary) Step 1
= (010) (110) (101) (000) Step 2
= (2 6 5 0)8 (Octal) Step 3

Example 1.8 Convert the following hexadecimal numbers to decimal numbers

(a) F2C (b) DF8.28

� Solution
(a) (F2C)16 = F × 162 + 2 × 161 + C × 160 = 15 × 256 + 2 × 16 + 12 × 1
= 3840 + 32 + 12 = 3884
 18 Digital Electronics: Principles and Applications

(b) (DF8.28)16 = D × 162 + F × 161 + 8 × 160 + 2 × 16–1 + 8 × 16–2

= 13 × 256 + 15 × 16 + 8 × 1 + 2 × 0.0625 + 8 × 0.0039
= 3328 + 240 + 8 + 0.125 + 0.0312 = 3576.1562

Example 1.9 Convert the following decimal numbers to hexadecimal numbers

(a) 905 (b) 6786

� Solution
(a) Conversion of (905)10 to hexadecimal
905/ 16 = 56+ remainder of 9 9(Least Significant Digit)
56/ 16 = 3 + remainder of 8 8
3/16 = 0 + remainder of 3 3(Most Significant Digit)
Result (905)10 = 38916

(b) Conversion of (6786)10 to hexadecimal

6786/ 16 = 424+ remainder of 2 2 (Least Significant Digit)
424/ 16 = 26 + remainder of 8 8
26 /16 = 1 + remainder of 10 A
1/16 = 0 + remainder of 1 1(Most Significant Digit)
Result (6786)10 = 1A8216

Example 1.10 Convert the following decimal numbers to hexadecimal numbers

(a) 0.625 (b) 2824.5

� Solution
(a) Conversion of (0.625)10 to hexadecimal

Fraction Number Product Fractional part Integer Part

0.625 .625 × 16 = 10 .0 A

(.625)10 is equal to (0.A)16

(b) Conversion of (2824.725)10 to hexadecimal
2824/16 = 176+ remainder of 8 8(Least Significant Digit)
176/ 16 = 11 + remainder of 0 0
11 /16 = 0 + remainder of 11 B (Most Significant Digit)
Result 282410 = B 0 816

Fraction Number Product Fractional part Integer Part

.725 .725 × 16 = 11.6 .6 B MSD
.6 .6 × 16 = 9.6 .6 9
.6 .6 × 16 = 9.6 .6 9 LSD

(.725)10 is equal to (.B99)16

Therefore, (2824.725)10 is equivalent to (B08.B99)16
 Number System 19

Example 1.11 Convert the following hexadecimal numbers to binary numbers

(a) A4C (b) 3E7.DA

� Solution
(a) Conversion of (A4C)16 to binary (A4C)16 = (1010 0100 1100)2
(b) Conversion of (3E7.DA)16 to binary (3E7.DA)16 = (0011 1110 0111.1101 1010)2

Example 1.12 Convert the following binary numbers to hexadecimal numbers

(a) 101111001011 (b) 1011110011.00110010

� Solution
(a) Conversion of (101111001011)2 to hexadecimal
(101111001011)2 = (1011) (1100) (1011) = (BCB)16
(b) Conversion of (1011110011.00110010)2 to hexadecimal
(1011 1100 1101.00110010)2 = (1011) (1100) (1101) . (0011) (0010) = (BCD.32)16

Example 1.13 Convert the following octal number to hexadecimal number

(a) 744 (b) 3472.56

� Solution
(a) Conversion of (744)8 to hexadecimal
(744)8 = (111 100 100)2
Forming into groups of 4 bits
= (0001 1110 0100)2 = (1E4)16
(b) Conversion of (3472.56)8 to hexadecimal
(3472.56)8 = (011 100 111 010.101 110)2
Forming into groups of 4 bits
= (0111 0011 1010.1011 1000)2 = (73A.B8)16

Example 1.14 Convert the following hexadecimal number to octal number

(a) B7A4 (b) D43E.5A

� Solution
(a) Conversion of (B7A4)16 to octal
(B7A4)16 = (1011 0111 1010 0100)2
Forming into groups of 3 bits
= (001 011 011 110 100 100)2 = (133644)8
(b) Conversion of (D43E.5A)16 to octal
(D43E.5A)16 = ( 1101 0100 0011 1110 . 0101 1010)2
Forming into groups of 3 bits
= (001 101 010 000 111 110 . 010 110 100)2 = (152076.264)8
 20 Digital Electronics: Principles and Applications

1.6 BINARY ARITHMETICS

In numerical system, the most common arithmetical operations are addition, subtraction, multiplication,
division, roots, powers, and logarithms, etc. If we perform one plus one operation, we get two by
using simple arithmetic operation of addition. But computers perform arithmetic operations on binary
numbers only. In binary arithmetics, the output of one plus one is 0. So, this binary operation of addition
can be confusing to a person accustomed to work with decimal arithmetic operation only. In this section,
the four basic operations of binary arithmetic are explained.
1.6.1 Binary Addition
Table 1.10 Rules of binary addition
It is a very simple task to add two binary numbers and
it is very similar to the addition of decimal numbers.
0+0=0 In decimal numbers, we start by adding the bits one
1+0=1 column at a time, from right to left. Unlike decimal
addition, there is little to memorise the rules for the
0+1=1
binary addition of bits. The rules of binary addition is
1 + 1 = 0 and a carry 1 ( i.e. 10 in binary)
given in Table 1.10.
1 + 1 + 1 = 1 and carry 1 ( i.e. 11 in binary) If the sum in one column is a two-bit number, the
least significant bit is written as part of the total sum and
the most significant bit is “carried” to the next left column as carry. The following examples of binary
addition are given below :
Addition of two binary number (1 0 0 1 1 0 1)2 and (0 0 1 0 0 1 0)2 is
1001101
+ 0010010
1011111
Similarly, addition of (1 0 0 1 0 0 1)2 and (0 0 1 1 0 0 1)2 is
11 1 <- - - Carry bits
1001001
+ 0011001
1100010
The another example of binary addition of (1 0 0 0 1 1 1)2 and (0 0 1 0 1 1 0)2 is
Carry bits ——> 1 1
1000111
+0010110
1011101
In the first problem of addition, there is no bit to be carried, since the sum of bits in each column was
1 or 0, not 10 or 11. In the other two problems, there are definitely bits to be carried, but the process of
addition is still quite simple.
 Number System 21

1.6.2 Binary Subtraction Table 1.11 Rules of binary

subtraction
To subtract one binary number from another, we use the standard
techniques, which are adopted for decimal numbers. The subtraction 0–0=0
of each bit pair, from right to left, borrowing as needed from bits to 1–0=1
the left. The rules of binary subtraction are shown in Table 1.11. 1–1=0
The examples of binary subtractions are given below: 0 – 1 = 1 with a borrow of 1
The subtraction of 1001 from 101 is 100 and 110.001 from 101.110
is 10.011
1 Borrow bits
1001
–101

100
11 Borrow bits
1 1 0 .0 0 1
– 1 0 1 .1 1 0
0 1 0. 0 1 1
By using rules of binary subtraction, we will be able to subtract two binary numbers as shown above.
But there is another method for binary subtraction, i.e., two’s complement. This method is better than
conventional method and explained latter on.

1.6.3 Binary Multiplication

Binary multiplication is the same as in real-number algebra, i.e., anything multiplied by 0 is 0, and
anything multiplied by 1 remains unchanged. The rules of binary multiplication are given in Table 1.12.
The examples of binary multiplication are given below:
The first example is the multiplication of (1011010)2 and (11011)2

1011010
×11011 Table 1.12 Rules of binary
multiplication
1011010
0×0=0
1011010×
1×0=0
0000000××
1011010××× 0×1=0
1011010×××× 1×1=1

100101111110
The result of the multiplication of (1011010)2 and (11011)2 is (10 0 1 0 1 1 1 1 1 10)2.
The second example to perform (1100)2 ¥ (1010)2 is
 22 Digital Electronics: Principles and Applications

1100
×1010
0000
1100×
0000××
1100×××
1111000
The result of the multiplication of (1100)2 and (1010)2 is (11110000)2.
The third example is multiplication between (1.01)2 and (10.1)2
1.01
×10.1
101
000×
101××
1 1. 0 0 1
The result of the multiplication of (1.01)2 and (10.1)2 is (1 1 . 0 0 1)2.

1.6.4 Binary Division

Division can be performed by repetitive subtraction. The rules of binary division are given below:
The example of binary division is presented below:
Table 1.13 Rules of binary The division of (1100010)2 by (111)2 is (1110)2 as calculated
division below
0/0 = Undefined
111) 1100010 (1110
1/0 = Undefined 111
0/1 = 0
1/1 = 1 01010
111

00111
111
000

Example 1.15 Add the following binary numbers

(a) 10101 (b) 1001
11010 0011
 Number System 23

� Solution
a) 1 0 1 0 1
11010
101111

Carry
11 Carry
(b) 1 0 0 1
0011

1100

Example 1.16 Subtract the following binary numbers

(a) 101010 (b) 1110010
– 100 – 0000110

� Solution
1 Borrow
(a) 101010
–100

100110
(b) 1110010
– 0000110
1101100

Example 1.17 Multiply the following binary numbers

(a) 10101 (b) 1111
× 101 × 1100

� Solution
(a) 10101
×101
10101
00000×
10101××

1101001
(b) 1111
×1100
 24 Digital Electronics: Principles and Applications

0000
0000×
1111××
1111×××
10110100

Example 1.18 Divide the following binary numbers

(a) 110)100001 (b) 111)1011011
� Solution
(a) 1 1 0 ) 1 0 0 0 0 1 ( 1 0 1.1
110
1001
110
110
110

(b) 1 1 1 ) 1 0 1 1 0 1 1 (1101
111
1000
111

111
111

1.7 SIGNED MAGNITUDE

This is one of the simplest codes. In this code, initially the decimal number is converted from base 10
into base 2 and then an additional bit is added to code the sign of the number. The first bit of binary
number is dedicated to represent positive or negative sign—sign ‘0’ for positive ‘+’ and sign ‘ 1’ for
negative ‘–’. The rest represent the absolute value of magnitude. The sign magnitude numbers from –7
to +7 are depicted in Fig. 1.10. The example of 8 bit signed magnitude numbers are given below:
+3 = 00000011
–3 = 10000011
+15 = 00001111
+30 = 00011110
–30 = 10011110
+50 = 00110010
–50 = 10110010
 Number System 25

1.8 ONE’S COMPLEMENT

The one’s complement of a binary number can be obtained by
substituting each ‘1’ by ‘0’ and ‘0’ by ‘1’. The example of one’s
complement is shown in Table 1.14.
From Table 1.14, it is very clear that first bit is sign bit and +3
is complement of –3 as shown below:
+3 = 00000011
–3 = 11111100

Fig. 1.10 Sign-magnitude

number
Table 1.14 One’s complement number
Positive Decimal Binary Equivalent Negative Decimal One’s Complement of
Number Number Binary Equivalent
+0 0000 –0 1111
+1 0001 –1 1110
+2 0010 –2 1101
+3 0011 –3 1100
+4 0100 –4 1011
+5 0101 –5 1010
+6 0110 –6 1001
+7 0111 –7 1000
The positive number +0 to +7 can be represented by Table 1.14 and negative number – 0 to –7 are
also shown in Table 1.14. The range for n bit number is +/-(2n–1–1).

1.9 TWO’S COMPLEMENT

The two’s complement of a binary number can be obtained from
the following steps:
Step-1: Firstly, complement each bit of binary number i.e.
‘1’ is replaced by ‘0’ and ‘0’ is replaced by ‘1’ to get
one’s complement.
Step-2: Add 1 to this one’s complement to obtain two’s
complement. By using a general representation, two’s
complement can be written as
2’s complement = Bit wise complement +1
Let us take an example of two’s complement of a binary number
(0100)2 or (+4)10. One’s complement is 1011 and after adding 1
with this number we get (1100) – 4. Therefore two’s complement
represents the magnitude of a number. Figure 1.11 shows the
two’s complement of number and Table 1.15 also depicts the two’s Fig. 1.11 Two’s complement of
complement of numbers. numbers
 26 Digital Electronics: Principles and Applications

Table 1.15 Two’s complement numbers

Zero 0000 negative one 1111

positive one 0001 negative two 1110
positive two 0010 negative three 1101
positive three 0011 negative four 1100
positive four 0100 negative five 1011
positive five 0101 negative six 1010
positive six 0110 negative seven 1001
positive seven 0111 negative eight 1000
Two’s complement is the code used by microprocessors to represent integer numbers. Two’s
complement is preferred over other codes because it simplifies the structure of the hardware required to
implement arithmetical operations, such as additions and subtractions.

1.10 SUBTRACTION BY USING TWO’S COMPLEMENT

The negative binary numbers can be represented by the two’s complement. Here, we will use the negative
binary number to subtract through addition. The example is subtraction of 810 – 510. This is actually
addition of 810 + (–510). For addition of 810 + (–510), it is required to represent eight and negative five in
binary. The positive eight is equivalent to (1000)2. Negative five is represented by two’s complemented
form as given below:
Negative five is equivalent to 10112. Then addition of positive eight 10002 and negative five, 10112
is as follows
1 Carry bits
1000
+1011

10011

Discard extra bit

After discarding the fifth bit (extra bit) in the answer, the correct answer is 00112 or positive three.
Another example is to perform (14)10 – (11)10. The number (14)10 is equivalent to (00001110)2 and –(11)10
is represented by 11110101 in two’s complement form. The addition of two numbers is shown below:
14 = 0 0 0 0 1 1 1 0
– 11 = + 1 1 1 1 0 1 0 1
3 00000011
Here, an additional example of subtraction with larger numbers. If we would like to add -2510 to 1810,
firstly we represent -2510 and 1810 in binary form. Initially, represent negative twenty-five, then finding
the two’s complement. Five bits are required to represent twenty five and one extra bit is also required
for the negative weight bit. In this way, six bits are used for binary representation of -2510 .
 Number System 27

Positive twenty five, +2510 = 0110012

One’s complement of (11001)2 = (100110)2
Two’s complement of (11001)2 = One’s complement + 1 = (100111)2 .
Therefore, –2510 is equivalent to (100111)2.
Positive eighteen in binary form is 1810 = 0100102
Then add these two binary numbers
11 Carry bits
100111
+010010
111001
As there are no extra bits, no bits will be discarded. The leftmost bit is 1 and the answer should be
negative in two’s complement form. Initially, the result will be converted into decimal by summing all
the bits respective weight; we obtain the final result as given below:
1 × (–32) + 1 × 16 + 1 × 8 + 1 × 1 = –7.

Example 1.19 Perform the following operations

(a) (–15)10 + (–22)10 (b) (22)10 –(15)10

� Solution
(a) 15 = 0000 1111 in 8 bit notation
one’s complement of 15 = 1111 0000
In two’s complement form, –15= 1111 0000 + 1 = 1111 0001.
22 = 0001 0110 in 8 bit notation
one’s complement of 22 = 1110 1001
In two’s complement form, –22 = 1110 1001 + 1 = 1110 1010.
11110001 –15
11101010 –22
111011011 –37
(b) 22 = 0001 0110
–15 = 1111 0001
00010110 22
11110001 –15
100000111 7

Discard extra bit

1.11 OVERFLOW
In digital system, the size of the word is fixed. If the magnitude of the number after addition or subtraction
operation exceeds the allotted number of bits, an overflow occurs. Therefore, errors are generated. With
 28 Digital Electronics: Principles and Applications

eight bits, we can represent one hundred twenty eight steps from zero to one hundred twenty seven (0 to
+127) or (0 to –127). This means that maximum number is +127 (0111 1111) and lowest number is –128
(1000 0000). In this case, the eighth binary digit is used to represent sign. During addition of two binary
numbers, if the result is more than +127, over flow exists. Consider two numbers (64)10 and (75)10. The
binary representation of (64)10 and (75)10 are (64)10 = (0100 0000)2 and (75)10= (0100 1011)2 respectively.
The addition of two binary numbers (0100 0000)2 and (0100 1011)2 is shown below:
0100 0000 (64)10
0100 1011 (75)10
1000 1011 (–11)10
The result is (1000 1011)2. After discarding the left most bit, the result will be incorrect as it is
negative number (–11)10 in place of (139)10. Another example is addition of two negative numbers
(–64)10 and (–75)10.
(–64)10 = 1111 1110
(–75)10 = 1011 0101
11011 0011
The result of addition of (–64)10 and (–75)10 is equal to (11011 0011)2. After discarding the extra bit,
the result is (–41)10, but the correct answer is (–139)10 . Therefore, to get the correct results bit fields
must be sufficiently large. Presently, consider nine bits to represent numbers and the ninth bit (most
significant bit) can be used as sign bit. Then the addition of (+64)10 & (+75)10 and (–64)10 & (–75)10 are
given below :
Addition of (+64)10 & (+75)10
0 0100 0000 (+64)10
0 0100 1011 (+75)10
0 1000 1011 (+139)10
Addition of (–64)10 & (–75)10
(–64)10 = 1 1111 1110
(–75)10 = 1 1011 0101

(–139)10 = 11 1011 0011

Discard

Form the above examples; we get correct answers by using sufficiently large bit fields to handle the
magnitude of the sums. The overflow can be detected after decimal addition and compare the result
with binary answers. After addition (+64)10 and (+75)10 we are supposed to get (+139)10, but binary sum
checked out to be (–11)10. Therefore, we can say that something has to be wrong. Actually overflow is
the reason for wrongness. Auspiciously, overflow detection is easily implemented in electronic circuits
and it is a standard feature in digital adder circuits.
 Number System 29

1.12 BINARY CODED DECIMAL (BCD) NUMBER SYSTEM

We are already familiar with the Binary, Decimal and Hexadecimal Number System. If we represent
single digit values for hex, the numbers 0 - F, and then these numbers can represent the values 0 – 15
in decimal, and occupy a nibble. Often, we wish to use a binary equivalent of the decimal system. This
system is called Binary Coded Decimal or BCD, which also occupies a nibble. In BCD, the binary
patterns 1010 through 1111 do not represent valid BCD numbers, and cannot be used. Table 1.16 shows
the BCD equivalent of decimal number from 0 to 9. This Code is called as 8421 BCD code. This code
replaces each decimal figure with a group of 4 bits in binary form. The conversion from Decimal to
BCD is performed according to Table 1.16.
Table 1.16 BCD code

Decimal Number Binary Coded Decimal Number

8 4 2 1
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1

Conversion from Decimal to BCD is very simple as shown in Table 1.16. Each digit of the decimal
number can be represented by a byte. Then we can convert 0 through 9 to 0000 0000 through 0000 1001.
The BCD equivalent value for the decimal number 5,219 is shown below. Since there are four digits in
our decimal number, there are four bytes in our BCD number.

Thousands Hundreds Tens Units

5 2 1 9
00000101 00000010 00000001 00001001

In computer, the minimum of 1 byte is required for storage of a number. Therefore, we can say that the
upper nibble of each BCD number is wasting storage space. BCD is still a weighted position number system
so we can perform mathematics, but we must use special techniques in order to obtain a correct answer.

1.13 PACKED BCD

The storage data on disk and in RAM is so valuable, we would like to eliminate this wasted storage. This
may be accomplished by packing the BCD numbers. In a packed BCD number, each nibble has a weighted
position starting from the decimal point. Therefore, instead of requiring 4 bytes to store the BCD number
5219, we can represent it by using 2 bytes, i.e., half the storage. The upper nibble of the upper byte of the
 30 Digital Electronics: Principles and Applications

number will be stored as the THOUSANDS value and the lower nibble of the upper byte can be stored as
the HUNDREDS value. Similarly, the lower byte would store the TENS value in the upper nibble and the
UNITS digit in the lower nibble. Therefore, 5219 can be represented by 2 bytes as shown below:
Thousands - Hundreds Tens - Units
5 2 1 9
0101 0010 0001 1001

The example of conversion from decimal to BCD is illustrated below:

Decimal Number BCD equivalent
123 0001 0010 0011
99 1001 1001
255 0010 0101 0101
5487 0101 0100 1000 0111

1.14 GRAY CODE (REFLECTED CODE)

The BCD code is a weighted code and each bit position has been assigned a definite weight. But the Gray
code is a non-weighted code. In this code, weights are not assigned to the bit positions. Actually, Gray code
is ordering of 2n binary numbers such that only one bit changes from one entry to the next. On the other
hand, we can say that in this code successive numbers differ by only one digit. This code is very useful
in mechanical encoders since a slight change in position only affects one bit. This is useful in avoiding
erroneous counts and in designing reliable sequential control modules. Using a typical binary code, up to
‘n’ bits could change, and slight misalignments between reading elements could cause wildly incorrect
readings. In 1878, French Engineer Emile Baudot used Gray code in telegraph. Frank Gray first patented
the codes in 1953. To construct a Gray code for ‘n’ bits, we take a Gray code for ‘n-1’ bits with each code
prefixed by 0 and append the ‘n-1’ Gray code reversed with each code prefixed by 1. This is called a Binary-
reflected Gray code. The example of creating a 3-bit Gray code from a 2-bit Gray code is given in Table
1.17. According to this table, 3-bit Gray code is (000, 001, 011, 010, 110, 111, 101, 100). Another 3 bit Gray
code is (000, 010, 011, 001, 101, 111, 110, 100). Table 1.18 shows the Gray code of 4 bit binary number.
Table 1.17 A 3-bit Gray code from a 2-bit Gray code
00 01 11 10 A Gray code for 2 bits
000 001 011 010 The 2-bit code with ‘0’ prefixes
10 11 01 00 The 2-bit code in reverse order
110 111 101 100 The reversed code with ‘1’ prefixes
000 001 011 010 110 111 101 100 A Gray code for 3 bits

Table 1.18 Four bit Gray code

Decimal Number Binary Number Gray Code Decimal Number Binary Number Gray Code
0 0000 0000 8 1000 1100
1 0001 0001 9 1001 1101
2 0010 0011 10 1010 1111
3 0011 0010 11 1011 1110
(Contd...)
 Number System 31

Table 1.18 (Contd...)

4 0100 0110 12 1100 1010
5 0101 0111 13 1101 1011
6 0110 0101 14 1110 1001
7 0111 0100 15 1111 1000

Consider the binary numbers for decimal numbers 3 and 4. We can see that there is a change in three
bit positions. So the chance of error increases in binary numbers. In the Gray code, since only one-bit
position changes between decimal numbers 3 and 4, the chances of errors are reduced. As less number of
bit changes are required for two numbers and a finite time is also required for each bit change, the Gray
code circuit can operate at higher speed. The disadvantage of the Gray code is that it cannot be used in
arithmetic operations. If addition, subtract, etc operations are necessary, the Gray code is converted into
binary and then arithmetic operations will be performed using binary data.

1.15 GRAY CODE TO BINARY CONVERSION

Using simple arithmetic method, we can do the conversion from Gray code to binary. The rules of
arithmetic method for Gray code to binary conversion is as given below:
Rule-1 The most significant bit (MSB) of the Gray code can be used as most significant bit (MSB)
in the binary.
Rule-2 The most significant bit (MSB) of binary will be added with the next bit immediately on
its right. Determine the sum and carry should be ignored.
Rule-3 Continuously add bits to bits immediately to their right until adding of all bits are
completed.
Rule-4 The binary equivalent of Gray code is the result and the number of bits will be same as the
Gray code.
This method has been explained with Fig. 1.12.
Consider a Gray code 1000 and it can be converted into
its binary.
According to rule 1, there is no change in the most
significant bit (MSB) of Gray code and binary. Hence
MSB of binary is 1. Then apply rule 2. So, MSB of the
binary number can be added with the next bit of Gray
Fig. 1.12 Gray code to binary conversion
code immediately on its right. Determine the sum and
carry should be ignored. The result of addition 1 and 0 is 1 and it can be considered as the next bit of the
binary number. According to rule 3, this bit is added with the next bit that is 0. The result of operation
1 + 0 is 1. So 1 is added to 0 of the LSB and the sum is 1. The final result is 1111, which is the binary
equivalent of Gray code.

1.16 BINARY TO GRAY CODE CONVERSION

The binary to Gray code conversion rules are similar with the Gray code to binary conversion. In this
case also the MSB of binary can be used as the MSB of the Gray code. The MSB of the binary number
is then added to the next bit to its right. The sum can represent the next bit of the Gray code. The
 32 Digital Electronics: Principles and Applications

process can be repeated upto the LSB. The binary to Gray code
conversion of binary number 1010 is shown in Fig. 1.13. The
Gray code 1111 is the equivalent of the binary number 1010.

1.17 EXCESS-3 (XS3) CODE

The Excess-3 (XS3) code is a non-weighted code and it is used
with binary coded decimal (BCD) numbers. This code is an
Fig. 1.13 Binary to Gray code
important 4-bit code and each 4-bit code represents a specific
conversion
decimal digit. Table 1.19 shows the BCD code and the XS3 code
for decimal digits from 0 through 9. It is very clear from the
above table that the Excess 3 (XS3) code number is three graters than BCD equivalent. The example is
that the BCD code for decimal digit 7 is 0111 but the said number in Excess 3 (XS3) code is 1010. This
code simplifies the BCD addition and other arithmetic operations. Therefore, the Excess-3 (XS3) code
has been used in arithmetic operations.
Table 1.19 Excess-3 code
Decimal Digit BCD Code XS3 Code
0 0000 0011
1 0001 0100
2 0010 0101
3 0011 0110
4 0100 0111
5 0101 1000
6 0110 1001
7 0111 1010
8 1000 1011
9 1001 1100

1.18 DECIMAL TO EXCESS-3 (XS3) CONVERSIONS

To convert any decimal number into it’s XS3 form, we add 3 to the decimal number and then the sum is
converted into BCD number. The example is conversion of decimal number 5 into XS3 code. Initially,
we add 3 with the decimal number 5:
Decimal number 5
Add 3 3
Sum 8
Then we convert the sum to BCD form. So the decimal number 5 represents 1000 in Excess 3 (XS3)
code.

1.19 WEIGHTED BCD CODES

We are already familiar with the binary code. It is a weighted code as it is represented by the 8421 BCD
code. There are also some weighted codes namely 4221, 2421, and 5211. The numbers 8, 4, 2 and 1
represent the weights of the bit positions. Similarly, weighted codes 4221, 2421, and 5211 are also used
to represent the weight of the bit position. Table 1.20 shows the weighted BCD code.
 Number System 33

Table 1.20 The weighted BCD code

Decimal Digit Weighted BCD Codes
8421 4221 2421 5211
0 0000 0000 0000 0000
1 0001 0001 0001 0001
2 0010 0010 0010 0011
3 0011 0011 0011 0101
4 0100 1000 0100 0111
5 0101 0111 1011 1000
6 0110 1100 1100 1010
7 0111 1101 1101 1100
8 1000 1110 1110 1110
9 1001 1111 1111 1111

Example 1.20 Determine the decimal equivalent of the following BCD numbers
(a) 0011 1001 0101 0001 (b) 1001 0111 0011 0101

� Solution
(a) BCD number is 0011 1001 0101 0001.
The BCD number is divided into 4-bit groups and then converted into decimal equivalent
0011 1001 0101 0001 = (0011) (1001) (0101) (0001) = 3951
(b) BCD number is 1001 0111 0011 0101.
The BCD number is divided into 4-bit groups and then converted into decimal equivalent
1001 0111 0011 0101 = (1001) (0111) (0011) (0101) = 9735

Example 1.21 Determine the XS3 equivalent of the following decimal numbers
(a) 345 (b) 698

� Solution
(a) Firstly, add 3 to each decimal digit. Then convert into BCD form
Decimal number 345
Add 3 333
678
The XS3 equivalent of 345 is 0110 0111 1000.
(b) Firstly, add 3 to each decimal digit. Then convert into BCD form
Decimal number 698
Add 3 333

9 12 11
The XS3 equivalent of 698 is 1001 1100 1011.
 34 Digital Electronics: Principles and Applications

Example 1.22 Convert the following XS3 numbers into decimal numbers
(a) 1011 (b) 1001 0011 0111

� Solution
(a) Subtract 3 from XS3 number and then convert into decimal form
XS3 number 1011
Subtract 3 0011
1000
The decimal equivalent of XS3 number 1011 is 8 .
(b) Subtract 3 from XS3 number and then convert into decimal form
XS3 number 1001 0011 0111
Subtract 3 0011 0011 0011
0110 0000 0100
The decimal equivalent of XS3 number 1001 0011 0111 is 604 .

Example 1.23 Convert the following binary numbers into Gray code number
(a) 1010 (b) 1101

� Solution
(a) 1 0 1 0 Add 1 + 0 = 1, Add 0 + 1 = 1, Add 1 + 0 = 1
1111
(b) 1 1 0 1 Add 1 + 1 = 0, Add 1 + 0 = 1, Add 0 + 1 = 1
1011

Example 1.24 Convert the following decimal numbers into 4221 BCD code
(a) 575 (b) 945

� Solution
(a) 5 represent 1001
7 represent 1101
5 represent 1001
Therefore, 4221 BCD representation of 575 is 1001 1101 1001.
(b) 9 represent 1111
4 represent 1000
5 represent 1001
Hence, 4221 BCD representation of 945 is 1111 1000 1001.
 Number System 35

1.20 ASCII CODE

A computer handles numerical and non-numerical
data for communication with environment. So,
computer should recognise the characters, numbers,
symbols, punctuations, etc. by using alphanumeric Fig. 1.14 7 bit ASCII code
codes. Most commonly used alphanumeric code is
ASCII code. ASCII code stands for American Standard Code for Information Interchange. ASCII
is pronounced as “Ask-ee”. This code is extensively used for digital data communication, and digital
computers. It is a 7-bit code. This code is used to represent each small and capital letter, numerical digits
(0 to 9) and punctuation characters. This 7-bit code is made up of a 3-bit group followed by a 4-bit group
as shown in Fig.1.14. For example, if we want to represent A, the 3-bit group is 010 and 0001 stands
for 4-bit group. Therefore, the 7-bit code for A is 0100001. Computers process data in byte form. So
ASCII is also used to represent data in byte form and this representation is called Extended ASCII. The
Extended ASCII set uses 8-bits codes and comprises special symbols for generating tables and other
simple graphical elements. Extended ASCII code for A is 10100001.
There are 128 characters in ASCII. The ASCII character set except the extended characters is divided
into four groups of 32 characters. All four groups of ASCII codes are represented in combined form as
shown in Table 1.21 and all four groups are explained below:
ASCII Code - Group I The first 32 characters of ASCII codes represented by 00H through 1FH
are called the control characters. This group of codes is formed for a special set of non-printing charac-
ters and these characters are used to perform various printers and display control operations. Table 1.21
shows the data representation of the ASCII code for the characters 00H through 01FH. The examples
of common control characters are given here. For example, ASCII code for carriage return operation is
0DH. This changes the position of the cursor to the left side of the current line of characters. Similarly in
line feed operation the ASCII code is 0AH, which moves the cursor down one line on the output device.
Another example is backspace, which moves the cursor back one position to the left. For this operation
ASCII code is 08H.
ASCII Code - Group II The second group of 32 ASCII character codes is used for various punc-
tuation symbols, special characters, and the numeric digits. The data representation of the ASCII code for
the characters 20H through 3FH is depicted in Table 1.21. The examples of the second group of ASCII
code are space character and numeric digits 0 to 9. For space character, ASCII code is 20H and numeric
digits 0 through 9 can be represented by ASCII codes 30H through 39H.
ASCII Code - Group III The 32 characters of ASCII code group III are reserved for the upper
case alphabetic characters and six special symbols. Table 1.21 shows the data representation of the ASCII
code for the characters 040H through 05FH. The ASCII codes for the characters “A” through “Z” lie in
the range 41H through 5AH. In view of the fact that there are only 26 different alphabetic characters and
the remaining six codes hold various special symbols.
ASCII Code - Group IV The fourth and last group of 32 ASCII character codes is reserved for
the lower case alphabetic symbols, five additional special symbols, and the control character namely
delete. Table 1.21 shows the data representation of the ASCII code for the characters 60H through 7FH.
36 Digital Electronics: Principles and Applications

Table 1.21 ASCII code chart

ASCII Code ASCII Code ASCII Code ASCII Code

– Group I – Group I I – Group III – Group IV
HEX DEC CHR CTRL HEX DEC CHR HEX DEC CHR HEX DEC CHR
00 0 NUL ^@ 20 32 SP 40 64 @ 60 96 ‘
01 1 SOH ^A 21 33 ! 41 65 A 61 97 a
02 2 STX ^B 22 34 “ 42 66 B 62 98 b
03 3 ETX ^C 23 35 # 43 67 C 63 99 c
04 4 EOT ^D 24 36 $ 44 68 D 64 100 d
05 5 ENQ ^E 25 37 % 45 69 E 65 101 e
06 6 ACK ^F 26 38 & 46 70 F 66 102 f
07 7 BEL ^G 27 39 ‘ 47 71 G 67 103 g
08 8 BS ^H 28 40 ( 48 72 H 68 104 h
09 9 HT ^I 29 41 ) 49 73 I 69 105 i
0A 10 LF ^J 2A 42 * 4A 74 J 6A 106 j
0B 11 VT ^K 2B 43 + 4B 75 K 6B 107 k
0C 12 FF ^L 2C 44 , 4C 76 L 6C 108 l
0D 13 CR ^M 2D 45 − 4D 77 M 6D 109 m
0E 14 SO ^N 2E 46 . 4E 78 N 6E 110 n
0F 15 SI ^O 2F 47 / 4F 79 O 6F 111 o
10 16 DLE ^P 30 48 0 50 80 P 70 112 p
11 17 DC1 ^Q 31 49 1 51 81 Q 71 113 q
12 18 DC2 ^R 32 50 2 52 82 R 72 114 r
13 19 DC3 ^S 33 51 3 53 83 S 73 115 s
14 20 DC4 ^T 34 52 4 54 84 T 74 116 t
15 21 NAK ^U 35 53 5 55 85 U 75 117 u
16 22 SYN ^V 36 54 6 56 86 V 76 118 v
17 23 ETB ^W 37 55 7 57 87 W 77 119 w
18 24 CAN ^X 38 56 8 58 88 X 78 120 x
19 25 EM ^Y 39 57 9 59 89 Y 79 121 y
1A 26 SUB ^Z 3A 58 : 5A 90 Z 7A 122 z
1B 27 ESC 3B 59 ; 5B 91 [ 7B 123 {
1C 28 FS 3C 60 < 5C 92 \ 7C 124 |
1D 29 GS 3D 61 = 5D 93 ] 7D 125 }
1E 30 RS 3E 62 > 5E 94 ^ 7E 126 ~
1F 31 US 3F 63 ? 5F 95 - 7F 127 DEL
 Number System 37

The lower case character symbols use the ASCII codes 61H through 7AH. The upper case and lower
case characters differ from their lower case equivalents in exactly one bit position that is bit five. Upper
case characters always contain a zero in bit five but lower case alphabetic characters always contain a
one in bit five.

Example 1.25 What is the ASCII code of message “MAY I HELP YOU”?

� Solution
Using the Table1.21, the message can be represented in the hex code and 7-bit ASCII code
Character Hex Code ASCII Code
MAY 4D 41 59 100 1101 100 0001 101 1001
I 49 100 1001
HELP 48 45 4C 50 100 1000 100 0101 100 1100 101 0000
YOU 49 4F 55 100 1001 100 1111 101 0101

Example 1.26 The ASCII code message, 100 0111 100 1111 100 0100 is stored in memory of a
computer. What is the message?

� Solution
Using the Table1.21, the ASCII code message can be represented by characters
ASCII Code Character
100 0111 G
100 1111 O
100 0100 D

1.21 EBCDIC
The EBCDIC is an 8-bit code primarily used by IBM and IBM compatible computer systems. It is
known as Extended Binary Coded Decimal Interchange Code. Like ASCII code, it is also widely used
in digital data communication of large computers. It is an 8-bit code. This 8-bit code is made up of two
groups. Group - I represents the zone and Group - II stands for numeric data as depicted in Fig. 1.15.
This code is used to represent the various characters, printable special characters and non-printable
control characters. The printable control characters are printer vertical spacing, and movement of cursor,
etc.
The Extended Binary Coded Decimal Interchange
Code (EBCDIC) for representing characters (A to Z),
digits (0 to 9) and a few special characters are shown
in Table 1.22. It is observed that this code is similar, to
punch card codes. Fig. 1.15 8 bit EBCDIC
 38 Digital Electronics: Principles and Applications

Table 1.22 EBCDIC

Character Zone Numeric Hexadecimal Character Zone Numeric Hexadecimal

A. 1100 0001 C1 0 1111 0000 F0
B. 1100 0010 C2 1 1111 0001 F1
C. 1100 0011 C3 2 1111 0010 F2
D. 1100 0100 C4 3 1111 0011 F3
E. 1100 0101 C5 4 1111 0100 F4
F. 1100 0110 C6 5 1111 0101 F5
G. 1100 0111 C7 6 1111 0110 F6
H. 1100 1000 C8 7 1111 0111 F7
I. 1100 1001 C9 8 1111 1000 F8
J. 1101 0001 D1 9 1111 1001 F9
K. 1101 0010 D2 Blank 0100 0000 40
L. 1101 0011 D3 . 0100 1011 4B
M. 1101 0100 D4 < 0100 1100 4C
N. 1101 0101 D5 ( 0100 1101 4D
O. 1101 0110 D6 + 0100 1110 4E
P. 1101 0111 D7 & 0101 0000 50
Q. 1101 1000 D8 $ 0101 1011 5B
R. 1101 1001 D9 * 0101 1100 5C
S. 1110 0010 E2 ) 0101 1101 5D
T. 1110 0011 E3 ; 0101 1110 5E
U. 1110 0100 E4 - 0110 0000 60
V. 1110 0101 E5 / 0110 0001 61
W. 1110 0110 E6 , 0110 1011 6B
X. 1110 0111 E7 % 0110 1100 6C
Y. 1110 1000 E8 > 0110 1110 6E
Z. 1110 1001 E9 ? 0110 1111 6F
: 0111 1010 7A
# 0111 1011 7B
@ 0111 1100 7C
= 0111 1110 7E

1.22 PARITY BIT

During transmitting data from one system to another system, if one bit of 8 bit data is lost; an incorrect
code will be received at receiving end. This data lost may occur due to electrical disturbance during
data transmission, unacceptable humidity level and dust particle on storage media. To overcome this
 Number System 39

problem, an extra bit is added with data for detecting errors. This extra bit is called as parity bit. There
are two types of parity bit, namely even parity and odd parity. In even parity, the parity bit is selected in
such a way that even numbers of ones are in word. In case of odd parity, the parity bit is selected so that
total numbers of ones is an odd number. When even number of ones is present in a word, this is known
as even parity word. Similarly, if odd numbers of ones are present in a word, the word is called odd
parity word. The example of even parity word and odd parity word are given below:
Even parity word 1001 1111
Odd parity word 1000 1001
ASCII code information is actually 7bit code. During
communications, 8-bit information (7 bit for ASCII code and
one extra bit for parity) has been transmitted accurately. The
extra bit or parity bit can be generated by parity generator.
The circuit diagram of odd parity bit generator is shown in
Fig. 1.16. Exclusive OR gate is used to generate the parity bit
as output of this gate is 1 when only one input is 1 and other
is 0. Seven input Exclusive – OR gate has been depicted in Fig. 1.16 Odd parity bit generation
the figure for generating parity bit.
When ASCII code is 100 1111, a parity bit 1 is added with data to make it even number of ones. Then
the new code after addition of parity bit is 1100 1111.
ASCII Code 1001111
Data 11001111

Parity bit
In another example, the ASCII code is 100 0100, a parity bit 0 is added with data as even number of
ones are already present in data. After addition of parity bit, the code has been changed to 0100 0100.
Table 1.23 and Table 1.24 represent the even parity and odd parity respectively.
ASCII Code 100 0100
Data 0 1000100

Parity bit
Table 1.23 Even parity

ASCII Code Parity bit Word transmitted Word received

100 0001 0 0 100 0001 0 100 0001
100 0010 0 0 100 0010 0 100 0010
100 0011 1 1 100 0011 1 100 0011
100 0100 0 0 100 0100 0 100 0100
 40 Digital Electronics: Principles and Applications

Table 1.24 Odd parity

ASCII Code Parity bit Word transmitted Word received

100 0001 1 1 100 0001 1 100 0001
100 0010 1 1 100 0010 1 100 0010
100 0011 0 0 100 0011 0 100 0011
100 0100 1 1 100 0100 1 100 0100
Figure 1.17 shows the block
diagram of digital data trans-
mission. Here, two devices,
namely transmitter and receiv-
er are communicating with
even parity. In this digital data
transmission, parity generator
is used at the side of transmis-
sion and parity checker is also
required at receiving end. The
transmitting device sends data
and parity generator counts
the number of set bits in each
group of seven bits. When the
Fig. 1.17 Digital data transmission
number of set bits is even, par-
ity generator sets the parity bit
to 0. If the number of set bits is odd, parity generator sets the parity bit to 1. As a result, every byte has an
even number of set bits. At the receiving end, the receiver receives transmitted data. Then parity checker
checks each byte to make sure that it has an even number of set bits. When parity checker finds an odd
number of set bits, the receiver knows that there was an error during transmission. Therefore, during
digital data transmission, the sender and receiver must both agree to use parity checking and there will
be advanced agreement whether parity is to be odd or even. If sender and receiver are not configured
with the same parity, communication will be impossible. Parity checking is most commonly used in
communications and testing memory storage devices. Generally, computers perform parity check on
memory when each byte of data is read from memory.

1.23 ERROR CORRECTING CODE: HAMMING CODE

Binary data can be transmitted through any communication medium such as optical fiber cables or radio
waves. If any noise is introduced in a communication system, there will be some error between the
transmitted and received data. Therefore, an error detecting code should be used to detect errors during
data transmission. Parity bit checking is commonly used to detect error, but it cannot correct the errors
(discussed in Section 1.22). The errors can be corrected by error correcting code which is known as
hamming code.
 Number System 41

The hamming code was developed by R.W. Hamming. In this code, one or more parity bits are added
to the data in such a way that error can be detected and corrected. The number of bits changed from one
code word to another code word is called as hamming distance.
Now consider Ai and Aj are to be any two code words. The hamming distance dij between two different
codewords Ai and Aj is defined by the number of components in which they differ. Assuming that dij is
determined for each pair of code words, the minimum value of dij is known as the minimum hamming
distance dmin.
7 6 5 4 3 2 1 ¨ Bit Position
1 0 0 1 0 1 1 ¨ Ai
Ø Ø
1 0 1 1 0 0 1 ¨ Aj
In the above example, the code words differ in the second and fifth bit positions from the right.
Therefore Dij is 3. The important properties of hamming code distance is that—
i. To detect single error, dmin should be at least two.
ii. For single error correction, dmin should be at least three. The relationship between number of errors
and minimum hamming distance dmin is E £ (dmin – 1)/2.
iii. When the values of dmin is greater than 3, more number of errors will be detected and corrected.
This code should have a minimum distance of three between two code words, in order to achieve
single bit error detection and correction. The code word consists of parity check bits and message bits.
When ‘r’ represents the number of parity check bits, the codeword must be 2r – 1 bits. The number of
message bits are determined from m = 2r – 1 – r. For example, if r = 3, the maximum number of message
bits are four as m = 2r – 1 – r = 23 – 1 – 3 = 4.
The bit positions in the code word are numbered from 1 to 2r – 1 and the position of parity bit in
the code word is a power of 2. In a 7-bit codeword, the format of the transmitted codeword (TC) bits
position are 7, 6, 5, 4, 3, 2, and 1, and the parity bits occupy position 1, 2 and 4. Assume TC = b3 b2 b1
r3 b0 r2 r1.
The 7-bit hamming (7,4) code word is b3 b2 b1 r3 b0 r2 r1 which is associated with binary message bits
b3 b2 b1 b0.
In the above TC = b3 b2 b1 r3 b0 r2 r1, the positions occupied by the parity bits 100 (4), 010(2) and
001(1). The message bits occupy the bit positions 011(3), 101(5) 110(6) and 111(7).
The parity bit r1 can be determined by EX-ORing the message bits in bit positions 7, 5, and 3.
Therefore,
r1 = b3 ≈ b1 ≈ b0
The parity bit r2 is obtained by EX-ORing the message bits in position 7, 6 and 3 so that
r2 = b3 ≈ b2 ≈ b0
Lastly r3 is expressed by EX-ORing the message bits in bit positions 7, 6 and 5
r3 = b3 ≈ b2 ≈ b1
 42 Digital Electronics: Principles and Applications

For example, when the message bits b3 b2 b1 b0 = 1011, the parity check bits are determined from
r1 = b3 ≈ b1 ≈ b0, r2 = b3 ≈ b2 ≈ b0, and r3 = b3 ≈ b2 ≈ b1. Here the parity check bits are r1s, r2s, r3s
and which are transmitted with message bits.
r1s = 1 ≈ 1 ≈ 1 = 1; r2s = 1 ≈ 0 ≈ 1 = 0; r3s = 1 ≈ 0 ≈ 1 = 0
Then, the transmitted codeword or Hamming code is
TC = b3 b2 b1 r3 b0 r2 r1 = 1010101
If the code word is transmitted, the message is received at the receiving end and we find an error in
bit b0. Then the received codeword is
RC= b3 b2 b1 r3 b0 r2 r1 =1010001
To determine the error in the received codeword, the parity bits at the receiving end must be determined
as follows:
r1r = 1 ≈ 1 ≈ 0 = 0; r2r = 1 ≈ 0 ≈ 0 = 1; r3r = 1 ≈ 0 ≈ 1 = 0
The position of the error can be determined by EX-ORing the transmitted and received parity bits.
r1s ≈ r1r = 1 ≈ 0 = 1; r2s ≈ r2r = 0 ≈ 1 = 0; r3s ≈ r3r = 0 ≈ 0 = 0
Then error can be indicated by code 011 which indicates that there is an error in the third bit position
of codeword.

SUMMARY

Decimal, binary, octal and hexadecimal number systems are explained briefly. The conversions from one number
system to others are incorporated in this chapter. The rules of binary arithmetic operations, namely addition,
subtraction, multiplication and division are discussed with examples. The signed numbers, one’s complement and
two’s complement of numbers are discussed in detail. The application of two’s complement in binary subtraction is
also included with examples.
To represent numbers, alphabets and special symbols, different codes are used. In this chapter, BCD, Packed BCD,
Gray code, Excess 3 code, weighted BCD code, ASCII code and EBCDIC are explained properly. The conversion from
one code to other is also discussed. The ASCII code is an alphanumeric code and it is commonly used in computer for
digital data transmission. During the digital data transmission from one computer to other, there may be some error
due to the presence of electrical noise. To detect error, parity bit is used. The error detection and correction technique
is also explained.

MULTIPLE CHOICE QUESTIONS

1. Which of the following is the limitation of analog electronics?
(a) Slow speed (c) Combination of (a) and (b)
(b) High speed (d) None of these
 Number System 43

2. Why digital electronics are more widely used as compared to analog electronics? Select one reason
from the following.
(a) They are easier to maintain
(b) They are less expensive
(c) They are useful over wider ranges of problem types
(d) They are always more accurate and faster
3. The number of nibbles, which make up one byte, is
(a) 2 (b) 16 (c) 4 (d) None of these
4. The decimal equivalent of the hexadecimal number E5 is
(a) 229 (b) 279 (c) 327 (d) None of these
5. Which of the following statements is correct?
(a) Decimal 10 is presented as 10101 in binary code
(b) Decimal 9 is presented as 1011 in Excess 3 code
(c) Decimal 9 is presented as 1010 in BCD code
(d) Decimal 10 is presented as 1100 in Gray code
6. (1111.01) is
(a) (15.25)10 (b) (12.25)10 (c) (23)10 (d) (12)10
7. In the 8421 BCD code, the decimal number 125 is written as
(a) 1111101 (b) 000111 (c) 7D (d) None of these
8. Indicate which of the following binary additions is correct
(a)10101 + 1111= 111101 (b) 1010 +1101=1111
(c)1010+1110=11000 (d) 1010 + 1001=1111
9. The binary equivalent of decimal number 13 is
(a) 1001 (b) 1100 (c) 1010 (d) 1101
10. The decimal number 422 is equal to which of the following hexadecimal number?
(a) 229 (b) 279 (c) 327 (d) 1A6
11. The binary number 101011 is equivalent to
(a) 229 (b) 279 (c) 327 (d) None of these
12. The decimal equivalent of 101.101 is
(a) 5.29 (b) 5.625 (c) 327 (d) None of these
13. Convert (11001.1)2 into octal
(a) (31.4)8 (b) (32.4)8 (c) (35.4)8 (d) None of these
14. Convert (347)8 into base 2
(a) 011100111 (b) 11100111 (c) 11101011 (d) None of these
15. Parity bit for error detection doses not imply
(a) Automatic error correction (c) Odd number of error detection
(b) Increase in the hardware in the system (d) Increase in the length of code
 44 Digital Electronics: Principles and Applications

REVIEW QUESTIONS
1.1 What is the difference between analog and digital quantities?
1.2 Explain advantages of digital system over analog system.
1.3 What is overflow in digital computer?
1.4 Discuss weighted code with examples.
1.5 What is the difference between ASCII code and EDCDIC code?
1.6 What is parity bit?. Explain briefly applications of parity bit.
1.7 Convert the following binary numbers to decimal numbers.
(a) 1100111 (b) 111010101 (c) 101.11011 (d) 10111.011011
1.8 Convert the following decimal numbers to binary numbers.
(a) 5635 (b) 256 (c) 100.425
(d) 0.625 (e) 100.25 (f) 37
1.9. Convert the following binary numbers to octal, and hexadecimal number.
(a) 101111010111111 (b) 110110110111 (c) 1111100111110 (d) 11101010110
1.10 Convert the following octal numbers to binary numbers.
(a) 57.35 (b) 222 (c) 50.25
(d) 2765 (e) 2567 (f) 67
1.11 Convert the following hexadecimal numbers to binary numbers.
(a) FFAF (b) 9BCD6 (c) CF
(d) AA2 (e) 87D4 (f) AE0F
1.12 Convert the following decimal numbers to octal and hexadecimal number.
(a) 546 (b) 2777 (c) 5235
(d) 46 (e) 9898 (f) 65
1.13 Add the following binary numbers.
(a) 10110111 (b) 11111101 (c) 11010011
10100110 10101100 11110110
1.14 Subtract the following binary numbers
(a) 11111011 (b) 00011011 (c) 11110011
– 01110001 –10000011 – 01110111
1.15 Divide the following binary numbers
(a) ( 10001110 ) 1001011011110111 (b) ( 10110110 ) 1101100000101001
(c) ( 11010011 ) 11001100111011111
1.16 Determine the 2’s complement of following numbers
(a) 01101101 (b) 11101111 (c) 10000011
1.17 Convert the following 2’s complement numbers into decimal
(a) 10001101101 (b) 101101111 (c) 111000011
1.18 Convert the following decimal numbers into 2’s complement numbers
(a) 599 (b) –77 (c) 365
 Number System 45

1.19 Convert the following decimal numbers to 8 bit, 2’s complement numbers,
(a) 256 (b) 56 (c) –106
1.20 Convert the following decimal numbers to BCD
(a) 298 (b) 25 (c) 56 (d) 86 (e) 99
1.21 Convert the following BCD numbers into decimal numbers
(a) 0011 0111 1001 (b) 1001 0101 0110 1000 (c) 0111 1001 1001 0011 1001
1.22 Add the following BCD numbers
(a) 1001 0111 1001 (b) 1001 0101 0110 0001 (c) 0111 1001 1001 0011 1001
0011 1001 0011 1001 1001 0100 1001 1000 0100 0011 1001 1001
1.23 Subtract the following BCD numbers
(a) 1001 0111 1001 (b) 1001 0101 0110 1001 (c) 0111 1001 1001 0011 1001
– 0011 1001 0011 – 0011 0110 0100 1001 0011 0100 0011 1001 0011
1.24 Determine characters of the following ASCII code
(a) 101 0100 100 1000 100 0101 100 0101 100 0001 101 0010 101 0100 100 1000
(b) 100 1101 100 1111 100 1111 100 1110
(c) 101 0011
(d) 101 0101 100 1110
1.25 Define Parity bit. What are the types of parity bit?. Explain applications of parity bit.
1.26 Explain Hamming Code with an example.
 CHAPTER

2
BOOLEAN ALGEBRA
AND LOGIC GATES
2.1 INTRODUCTION
Boolean algebra has been introduced by the mathematician, George Boole in 1854. It is a two state
algebra to solve logic problems and used the logical and arithmetic calculations for digital equipments.
This operates with logic variables, namely ‘0’ and ‘1’. The logic variables can also be represented by
logical TRUE (T) and logical FALSE (F). Any statement can be represented by logic variable. One
example is “The Sun rises in the east” (TRUE). In this way, any statement can be model as logic
variable. In the other way, new statements can be built based on existing statements using logic variables
and logic operators. The new statements may be false or true. Consider X= “The Sun rises in the east”
then NOT X = Y= “The Sun does not rises in the east” (FALSE).
Boolean logic variable “0” or “1” is not used to represent actual numbers but it is used to represent
the state of voltage variable called logic level. Commonly used representation of logic levels are shown
in Table 2.1.
Transistors can be operated at two different states namely saturation and cut-off. Figure 2.1 shows
the saturation operation of transistor. In this circuit, 5 volt is applied through the two-position switch
to operate in saturation. When the transistor is in saturation region, the voltage between collector and
emitter is very small. So, the output voltage is 0 volts. Therefore, this circuit can be used to represent
binary bits. The input signal is a logic ‘1’ and the output signal is a logic ‘0’. These voltage levels can
also be represented by logic level HIGH and LOW respectively as depicted in Table 2.1. Similarly, due
to change the position 0V (logic 0) is used as input and transistor operates in cut-off region and output
voltage will be 5V or logic ‘1’ as shown in Fig. 2.2.

Table 2.1 Representation of logic level

Logic 0 Logic 1
False True
Open Switch Close Switch
Low High
No Yes
Off On
Fig. 2.1 Transistor in saturation
 Boolean Algebra and Logic Gates 47

In this way, a single transistor can be used as a logic

gate or gate. A gate is a electronic circuit which is designed
to receive and generate voltage signals into binary form.
Figures 2.1 and 2.2 can implement the NOT gate or inverter.
Generally, gate circuits are represented by symbols. The
symbol of NOT gate is presented in proper place.
2.2 BOOLEAN ALGEBRA
The English mathematician, George Boole (1815–1864) is Fig. 2.2 Transistor in cut-off
known as the father of Boolean Algebra. His work namely
“An Investigation of the Laws of Thought, on Which Are Founded the Mathematical Theories of Logic
and Probabilities” was published in 1854. Actually, this consists of several rules of relationship between
mathematical quantities namely true or false, ‘1’ or ‘0’. This mathematical system is called as Boolean
algebra. This is a two-state algebra to solve logic problems. This new algebra had no practical use
until Shanon applied it to telephone switching circuits. Presently, Boolean algebra is the backbone of
computer and it is also used to analyse and design of digital circuits.
Boolean algebra uses alphabetical letters to denote variables same as normal algebra. Boolean
variables are always CAPITAL letters, never lower-case, as these variables are allowed to possess only
one of two possible values, either ‘1’ or ‘0’. The inversion, AND and OR operation of Boolean algebra
are explained as follows.
2.2.1 Inversion Operation
Each variable has a complement means the opposite of its value. If we consider variable A has a value
of ‘0’, then the complement of A has a value of ‘1’. Boolean notation uses a bar above this variable
character to denote complementation as given below:
– –
If A = 0 then A = 1 or If A = 1 then A = 0
The complement of A is denoted as A-not or A-bar. The prime symbol is also used to represent
complementation. For an example, the complement of A will be A¢.
For inversion operation, NOT gate is used as depicted in Fig.2.3. This gate has one input and an out-
put. When input is A, output, O is always complement of A due to inversion. The equation for this is
O = NOT A
If A is 0,
O = NOT 0 = 1
On the other hand, if A is 1,
Fig. 2.3 Inversion operation O = NOT 1 = 0
In Boolean algebra, the NOT operation is denoted by the over-bar and the equation for NOT operation
can be written as
–
O=A
The above equation can be interpret as “ output, O equals NOT A” or “output O equals the complement
of A”.
 48 Digital Electronics: Principles and Applications

2.2.2 OR Operation
In mathematics, the sum of any number and zero is the same as the original number. This algebraic
identity can be written as X + 0 = X, where X is any number. Similar to ordinary algebra, Boolean algebra
has its individual identities based on the bivalent states of Boolean variables. In Boolean algebra, the
sum of anything (1 or 0) and zero(0) is the same as anything (1 or 0). This logical function is known as
OR operation. The equation for OR operation is
O = A OR B
With given the inputs, we can find the output. If A = 0 and B = 0,then output
O = 0 OR 0 = 0
So, output of an OR gate is zero when both inputs are 0s.
But, when A = 0 and B = 1, the output is 1
O = 0 OR 1 = 1
Therefore, it is clear that output of an OR gate is 1 when either input is 1. Similarly, if A = 1 and B = 0,
output is 1
O = 1 OR 0 = 1
In Boolean algebra, the ‘+’ sign stands for the OR operation and the equation for OR operation is
O = A + B. Figure 2.4 shows the relationship between inputs and output for OR operation.

Fig. 2.4 OR operation

2.2.3 AND Operation

The multiplication is also valid in Boolean algebra and it is the same as in real-number algebra. Anything
multiplied by 0 is 0, and anything multiplied by 1 output is 1. This is nothing but the truth table for an
AND gate. In other words, Boolean multiplication corresponds to the logical function of an AND gate.
The equation for AND operation is
O = A. B
In Boolean algebra, the multiplication sign “.” stands for AND operation. The above equation can be
written simply O = AB.
This equation can be interpreted as “ output, O equals as A AND B”.
If both the inputs are low, output is low,
O = 0.0 = 0
In fact, the output will be 1 only in one case when both the inputs are high. That is
O = 1. 1 = 1.
 Boolean Algebra and Logic Gates 49

Figure 2.5 shows the AND operation.

Fig. 2.5 AND operation

2.3 BOOLEAN LAWS

Boolean laws have been derived by using Boolean postulates. These laws are used to design and analyse
logic circuit mathematically. The Table 2.2 shows the Boolean laws. In this section, all these laws are
explained below:
Table 2.2 The Boolean laws
Laws of Union
Law 1 A+0=A
Law 2 A+1=1
Laws of Intersection
Law 3 A.0 = 0
Law 4 A.1 = A
Laws Tautology
Law 5 A+A=A
Law 6 AA = A
Laws of Complements
–
Law 7 A+A =1
Law 8 A.A = 0
Laws of Double Complements
=
Law 9 A =A
Laws of Commutation
Law 10 A+B=B+A
Law 11 AB = BA
Laws of Association
Law 12 A + (B + C) = (A + B) + C
Law 13 A(BC) = (AB)C
Laws of Distribution
Law 14 A(B + C) = AB + AC
Law 15 (A + B)(C + D) = AC + AD + BC + BD
Laws of Absorption
Law 16 A (A + B) = A
Law 17 A + AB = A
–
Law 18 A(A + B) = AB
– –
Law 19 AB + B = A + B
–
Law 20 AB + B = A + B
DE Morgans Theorem
—–— – –
Law 21 A + B = A. B
–—– – –
Law 22 A. B = A + B

2.3.1 Laws of Union

This is the first Boolean identity. It means that the sum of anything (1 or 0) and zero (0) is the same as the
anything (1 or 0). There is no difference between the Boolean identity, laws of union and real number
 50 Digital Electronics: Principles and Applications

algebra. Law 1 and Law 2 of Laws of Union are shown in Fig 2.6(a) and (b)
respectively and their operations are explained as follows:
Law 1 A+0=A Fig. 2.6
When A = 0, A + 0 = 0
When A = 1, A + 1 = 1
Law 1 means that the output is always A and depends on the value of A. When A = 1, the output will
be 1. If A = 0, output will be 0.

Law 2 A+1=1
When A = 0, A + 1 = 1, When A = 1, A + 1 = 1
It means that output is independent of A and it will be always the same when A = 1 or A = 0. This identity
is different from any seen in normal algebra. Here, we can see that the sum of anything and ‘1’ is ‘1’.

2.3.2 Laws of Intersection

There are two intersection identities: A.0, and A.1. These two laws are
stated below with the help of Fig. 2.7 (a) and (b):
Fig. 2.7

Law 3 A.0 = 0
When A = 0, A.0 = 1, When A = 1, A.0 = 0
This law states that if one of two inputs AND gate is logic zero (0) and other input is connected with
signal A, the output will be logic zero (0).

Law 4 Α.1 = A
When A = 0, A.1 = 0, When A = 1, A.1 = 1
It is depicted in Fig. 2.7(b) that if one of two inputs AND gate is logic 1 and other input is connected
with signal A, the output will be A.

2.3.3 Laws of Tautology

Law 5 A+A=A
The output of adding A and A together is A as shown in Fig. 2.8 (a). When both inputs of an OR gate are
connected to each other, output will be A same as input.
Law 6 A.A = A
In normal algebra, the product of a variable and itself is the square of that
variable. But, in Boolean algebra, A.A is equal to A as depicted in Fig.2.8(b).
The equation, A.A = A means that the product of a Boolean quantity and
itself is the original quantity like 0 ¥ 0 = 0 and 1 ¥ 1 = 1. If both inputs of a
AND gate are connected to each other and output will be A same as input. Fig. 2.8
 Boolean Algebra and Logic Gates 51

2.3.4 Laws of Complements

–
Law 7 A + A = 1
In laws of complement of Boolean algebra, the output of OR
operation of any variable and it’s complement is always ‘1’. So,
the sum of any Boolean quantity and its complement must be ‘1’ as
shown in Fig. 2.9 (a).
–
Law 8 A.A = 0
In Boolean mathematics, the AND operation output between a vari-
able A and its complement, A– is 0. Therefore, the output must be ‘0’
for AND operation between any variable and its complement. As the
product of any Boolean quantity and ‘0’ is ‘0’, the product of a vari-
able and its complement must be ‘0’ as shown in Fig. 2.9 (b). Fig. 2.9

2.3.5 Laws of Double Complements

=
Law 9 A = A
There is also one identity with complementation that is known as
double complements. Double complement means that a variable
inverted twice. It simply states that it is actually complement of
the complement of a variable. After complementing a variable
twice, we get the original Boolean value as shown in Fig. 2.10.
– ==0=A Fig. 2.10
If A = 0, A = 1 and A
2.3.6 Laws of Commutation
Law 10 A+B = B+A
Law 11 AB = BA
The Commutative Law is also applicable for Boolean algebra,
and it applies equally to addition and multiplication. From this
commutative property, we can say that we can reverse the order
of variables in addition or multiplication as shown in Fig.2.11 (a)
Fig. 2.11
and (b).
2.3.7 Laws of Association
Law 12 A+(B+C) = (A+B)+C
Law 13 A(BC) = (AB)C
Laws of Association of Boolean algebra
are same as for conventional algebra. So
associative property can be applied in
addition and multiplication of variables as
depicted in law 12 and law 13. Using this
property, we can able to add or multiply
between associate groups with parentheses
as depicted in Fig. 2.12(a) and (b). In this
case, the truth table will not be changed. Fig. 2.12
 52 Digital Electronics: Principles and Applications

2.3.8 Laws of Distribution

Law 14 A(B+C) = AB+AC
Law 15 (A+B)(A+C) = A+BC
The laws of distribution are used to expand any Boolean expression. The law 14 and law 15 show the
product of a sum and in reverse
how all terms can be factored out
of Boolean sums-of-products as
depicted in Fig. 2.13 (a) and (b)
respectively.

2.3.9 Laws of Absorp-

tion
Law 16 A (A + B) = A
Law 17 A + AB = A Fig. 2.13
–
Law 18 A (A + B) = AB
– –
Law 19 AB + B = A+ B
–
Law 20 A + AB = A + B
There are five laws of absorption in Boolean algebra as given above. These laws are used in the
simplification of logic circuits. When logic circuits are represented by most simplified Boolean form,
the logic circuit can able to perform the same function with fewer logic gates. As a result, reliability of
logic circuit will be increased and cost of manufacture will be decreased.
The law 16 can be proved by using Boolean identity. Consider the Boolean expression A(A+B)
A(A+B) = AA + AB = A + AB applying AA = A
Factoring A out of both terms, we get A(1 + B)
We already know that B + 1 = 1. Then apply this in the above
equation, we get A.1
Applying identity 1.A = A, we finally get A.
–
Similarly, we can prove that A + A B = A + B
–
Applying the rule A + AB = A, the Boolean expression A + A B can
–
be written as A + AB + A B
–
Factoring out of second and third terms A + B(A+ A )
–
Applying (A+ A ) =1, we get A + B.1
Applying 1. A = A, we finally get A + B
Figure 2.14(a) and (b) show logical implementation of law 16 and
Fig. 2.14 law 20 using logic gates respectively. In the same way, we can be able
to prove other laws and to implement using logic gates.

Example 2.1 Prove A(A + B) = A

 Boolean Algebra and Logic Gates 53

� Solution
A(A + B) = AA + AB Applying distributive property
= A + AB Applying identity AA = A
= A.1 + AB Factoring out A
= A(1 + B) Apply identity 1 + A = 1
= A.1 Apply identity A.1 = A
=A

Example 2.2 Prove (A + B) (B + C) = B + AC

� Solution
(A + B) (B + C) = AB + AC + BB + BC Applying distributive property
= AB + AC + B + BC Applying identity AA = A
= B + AB + AC + BC Apply B + AB = B
= B + AC + BC
= B + BC + AC Apply B + AB = B
= B + AC

2.4 DE MORGAN’S THEOREM

De Morgan was developed two important rules for group complementation in Boolean algebra. These
two rules are:
De Morgan’s First Theorem
—————— – –
A +B = A . B
De Morgan’s Second Theorem
––– – –
A .B = A + B
De Morgan’s First Theorem De Morgan’s Second Theorem
Break Break

——
———
— ———
—
—
A +B A ·B

— — — —
A.B A+ B
2.4.1 De Morgan’s First Theorem
According to De Morgan’s first theorem, when a long bar is broken, the operation directly under the
break changes from addition to multiplication as given below
——
———— – –
A +B = A . B
Both sides of Boolean expression can be represented by logic circuits.

Fig. 2.15
 54 Digital Electronics: Principles and Applications

Figure 2.15 (a) is a 2 input NOR gate —— and

———
Fig.2.15 (b) is the substitute of NOR gate using OR and
—
inverter. Here the output is equal to O = A + B .
Figure 2.15(c) has inverted inputs before they reach the AND gate. Therefore, the Boolean equation
– –
of output is O = A . B
After comparing Table 2.3 and Table 2.4, we can say that they are identical. This means the two
circuits are logically equivalent; given the same inputs, the outputs are same. In other words, the cir-
cuits shown are inter- Table 2.4 Truth table
Table 2.3 Truth table
changeable. Therefore,
De Morgan’s first the- Inputs Output Inputs Output
–––– – –
orem is proved from A B O = A+B A B O=A +B
0 0 1 0 0 1
truth tables.
0 1 0 0 1 0
When three inputs 1 0 0 1 0 0
are involved, De Mor- 1 1 0 1 1 0
gan’s first theorem is
written as
——
——— — ———
— – – –
A + B +C = A . B . C
Similarly, for 4 inputs it will be
——— — ——————— —— – – – –
A +B+ C + D = A . B . C . D
2.4.2 De Morgan’s Second Theorem
According to De Morgan’s second theorem, when a long bar is broken, the
operation directly under the break changes from multiplication to addition as
given below:
––– – –
A .B = A + B
Both sides of the above Boolean equation can be implemented by logic
circuits as shown in figures below.
Figure 2.16 (a) is a 2 input NAND gate. Therefore, the Boolean equation
––––
of output is O = A . B
Fig. 2.16
Figure 2.16 (b) has inverted inputs before they reach the OR gate. Therefore
– –
the Boolean equation of output is O = A + B
Table 2.5 Truth table We can say that Table 2.5 and Table 2.6 are identical. This
means that the two circuits are logically equivalent; given the
Inputs Output
–––– same inputs, the outputs are same. In other words, the circuits
A B O = A. B shown are interchangeable.
0 0 1 Thus, the De Morgan’s second theorem is proved.
0 1 1
When three inputs are involved, De Morgan’s second theorem
1 0 1 is written as
1 1 0 ——— – – –
A . B. C = A + B + C

For 4 inputs,
———— – – – –
A . B.C. D = A + B + C + D
 Boolean Algebra and Logic Gates 55

If multiple layers of bars exist in a Boolean expression, we Table 2.6 Truth table
can only break one bar at a time, and it is usually easier to begin Inputs Output
simplification by breaking the longest bar first. For an example, – –
–— A B O=A+B
consider the Boolean expression is AB + CD . The expression 0 0 1
–—
AB + CD can be reduced using De-Morgan’s Theorems. Firstly, 0 1 1
–— –—
break the longest bar and we get A B .CD. Then we break A B . 1 0 1
– –
So, finally we find A CD + B CD.
1 1 0

Example 2.3 Prove A + B + C + D + ABCD = 1

� Solution
– – – –
A + B + C + D + ABCD = A + B + C + D + A + B + C + D Breaking long bar in ABCD
– – – – –
=A+A +B+B +C+C +D+D Apply identity A + A = 1
=1+1+1+1=1

2.5 LOGIC GATES

Logic gates are electronic circuits with a number of inputs and one output. The output voltage depends
on the input voltages. Logic gate circuits are most commonly represented in a schematic by symbols
in place of constituent transistors and resistors. The digital systems can be made by using three basic
logic gates. These are AND gate, OR gate and NOT gate. The AND gate is an electronic circuit whose
output is high when it’s all inputs are high. The OR gate is also an electronic circuit which gives a high
output if one or more of it’s inputs are high. The NOT gate generates an inverted version of the input
logic at it’s output. The most commonly used other logic gates are NAND, NOR, XOR, INV, and BUF.
The term INV stand for “inverter” and BUF stand for “buffer”. In this section, function of all logic gates
have explained elaborately.

2.5.1 Truth Table

The truth table describes the output of a logic circuit, which depends on the inputs of the logic circuit.
Figure 2.17 shows the block diagram of two inputs logic circuit and it’s output is shown in Table 2.7.
The relationship between input and output should be expressed by Boolean logic function that is un-
known (?). Similarly, three inputs and one output logic circuit represented by Fig.2.18 and the output
for different values of inputs are depicted in Table 2.8. The correlation between inputs and output should
be expressed by Boolean function. Therefore, the “?” in the box as shown in Fig. 2.17 and Fig.2.18 will
be replaced by logic gates. The two inputs AND gate is required for Fig.2.17 and a three inputs OR gate
can able to represent the Fig. 2.18.

Fig. 2.17 Two inputs and one output Fig. 2.18 Three inputs and one output
 56 Digital Electronics: Principles and Applications

Table 2.7 Two inputs and one output Table 2.8 Three inputs and one output
Inputs Output Inputs Output
A B O A B C O
0 0 0 0 0 0 0
0 1 0 0 0 1 1
1 0 0 0 1 0 1
1 1 1 0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

2.5.2 AND Gate

The expression O = A.B means output “O” equals A AND B. The “.” sign stands for the AND operation
and actually it is same as ordinary multiplication of 1s and 0s. The AND operation produces a result of
‘1’, when all input variables are ‘1’. But the output is ‘0’ when one or more inputs are ‘0’. Figure 2.19
shows the two inputs AND gate and truth table is given in Table 2.9.
Table 2.9 Truth table of two inputs AND gate

Inputs Output
A B O = A.B
0 0 0
0 1 0
Fig. 2.19 Two inputs AND gate 1 0 0
1 1 1

An example of three inputs AND gate and its truth table are shown in Fig. 2.20 and Table 2.10 respectively.
It is also depicted in truth table that output is ‘1’ when all inputs are ‘1’ and otherwise output is ‘0’.
Table 2.10 Truth table of three inputs AND gate
Inputs Output
A B C O = A.B.C
0 0 0 0
0 0 1 0
0 1 0 0
Fig. 2.20 Three inputs AND gate
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1

The three inputs and four inputs AND gate using two input AND gates are depicted in Fig. 2.21(a)
and Fig. 2.21(b) repectively.
 Boolean Algebra and Logic Gates 57

2.5.3 OR Gate
The expression O = A + B defined as output “O” equals A OR B.
The “+” sign stands for the OR operation and it is not for arithmetic
addition. When any of the inputs of OR gate is ‘1’ the output of the
OR gate will be ‘1’. But, the output of OR gate is ‘0’ only when
all the input variables are ‘0’. The symbol of two inputs OR gate is
shown in Fig. 2.22 and truth table is also given in Table 2.11.

Fig. 2.21

Table 2.11 Truth table of two inputs OR gate

Inputs Output
A B O=A+B
0 0 0
0 1 1
1 0 1 Fig. 2.22 Two input OR gate
1 1 1

Figure 2.23 shows the three inputs OR gate and its truth table is given in Table 2.12. It is depicted in
this table that the output of the OR gate is ‘1’ when any of the inputs of OR gate is ‘1’ and output is ‘0’
only when all the input variables are ‘0’.
Table 2.12 Truth table of three inputs OR gate
Inputs Output
A B C O=A+B+C
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1 Fig. 2.23 Three inputs OR gate
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1

Three inputs and four inputs OR gate can be designed by using two inputs OR gates as shown in
Fig. 2.24 (a) and (b) respectively.

2.5.4 NOT Gate

The circuit which is shown in Fig. 2.1 as given in Section 2.1, is known as an inverter or NOT gate. This
inverter circuit is also represented by symbol as given in Fig. 2.25. An alternative symbol for an inverter
is shown in Fig. 2.26. The NOT Gate has one input signal and one output signal. When the input signal
A is subjected to the NOT operation, the output O can be expressed as
58 Digital Electronics: Principles and Applications

–
O = A or O = A¢
Here, ‘ – ’ or ( ¢ ) represents the NOT operation. This
expression means output ‘O’ equals NOT A or O equals the
inverse of A or O equals the complement of A. The truth
table of the NOT gate is shown in Table 2. 13. The NOT gate
operations can be referred as inversion or complementation.
Table 2.13 Truth table of NOT gate

Input Output
–
A O = A = A′
0 1
Fig. 2.24 1 0

The NOT operation is also referred as inversion or

complementation, and these terms are used interchangeably.

2.5.5 NOR Gate

NOR gate is extensively used in digital electronic circuit. This
gate is the combination of the basic gates AND, OR and NOT.
Fig. 2.25 NOT gate
NOR is the same as the inverted OR gate and its symbol is shown
in Fig. 2.27. This gate has a small circle on the output. This
small circle represents the inversion operation and the output
expression of the two inputs NOR gate is
——
O = A + B = (A + B)¢.
The truth table of the NOR gate is shown in Table 2. 14. An
Fig. 2.26 NOT gate three inputs OR gate can be designed by using a NOR gate and
a NOT gate as shown in Fig. 2.28.
Table 2.14 Truth table of two inputs NOR gate

Inputs Output
A B O = A + B = (A + B)′
0 0 1
0 1 0
1 0 0
Fig. 2.27 Two inputs NOR gate 1 1 0

2.5.6 NAND Gate

The inverted operation of AND gate is the NAND gate
and its symbol is depicted in Fig. 2.29. There is a small
circle on the output. This small circle represents the
inversion operation. The output of the two inputs NAND
Fig. 2.28 The three inputs OR gate gate can be expressed as
 Boolean Algebra and Logic Gates 59

–—
O = A B = ( AB )¢.
The truth table of two inputs NAND gate is given in Table 2.15.
Table 2.15 Truth table of two inputs NAND gate

Inputs Output
–—
A B O = A B = (AB)¢
0 0 1
0 1 1
1 0 1
1 1 0
Fig. 2.29 Two inputs NAND gate
Digital logic can be described in terms of standard logic symbols and their corresponding truth tables.
The transistor based digital ICs (Integrated chips) have been manufactured by using the function of all
gates. The horizontal lines represent inputs or outputs of the gates and the small circle at the outputs
means inverted operation of output.
A three input NAND gate and four input NAND gate can be designed by using two inputs AND and
NAND gates as shown in Fig. 2.30 (a) and (b).

Fig. 2.30

2.5.7 Exclusive-OR Gate

The operation of Exclusive-OR gate is something quite different from OR gate. When the inputs of
Exclusive-OR gate are at different logic levels either ‘0’ and ‘1’ or ‘1’ and ‘0’, its output is “high”. On
the other hand, output of Exclusive-OR gate is “low” logic level if the inputs are at the same logic levels.
The Exclusive-OR gate can be written as XOR or Ex-OR gate. Figure 2.31 shows the two inputs Ex-OR
gate and truth table is given in Table 2.16.

Table 2.16 Truth table of XOR gate

Inputs Output
A B O=A⊕B
0 0 0
0 1 1
1 0 1
1 1 0
Fig. 2.31 Ex-OR gate
 60 Digital Electronics: Principles and Applications

An Exclusive-OR gate can be build up by using NAND,

AND, and OR gates. The equivalent circuit of Ex-OR gate
is shown in Fig. 2.32. In this circuit, the output of NAND
gate and OR gate are fed to AND gate for final output.
Here, AND gate acts as a buffer. For the first three input
combinations (00, 01, and 10) the output of NAND gate is
Fig. 2.32 Equivalent circuit of Ex- high. When the NAND gate’s output is high, the output of
OR gate
AND gate is equal to the OR gate’s output. When inputs are
“high”, the output of NAND gate outputs a “low” and the
output of AND gate is “low”.
Figure 2.33 shows the alternative equivalent circuit of
the Exclusive-OR gate. This circuit uses two AND gates
with inverters and an OR gate. The output of AND gates
can be “high” for input conditions 01 and 10. Then OR gate
allows either of the AND gates’ “high” outputs to create a fi-
Fig. 2.33 Equivalent circuit of Ex-OR nal “high” output. Exclusive-OR gates are used to compare
gate
binary numbers. This gate is also used for error detection,
parity check and code conversion, like binary to Grey.
The three inputs Ex-OR and four inputs Ex-OR gates can be developed by using two inputs Ex-OR
gate as shown in Fig. 2.34(a) and (b) respectively. The truth table of three inputs Ex-OR gate is shown
in Table 2.17.
Table 2.17 Truth table of three inputs Ex-OR gate

Inputs Output
A B C O = A⊕B⊕C
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
Fig. 2.34
1 1 1 1

2.5.8 Exclusive-NOR gate

The last gate for analysis is the Exclusive-NOR gate
and it is known as the XNOR gate. It is equivalent to an Table 2.18 Truth table of XNOR gate
Exclusive-OR gate with an inverted output. The truth table Inputs Output
for this gate is absolutely opposite of the Exclusive-OR ——–
A B O = A⊕B
gate as given in Table 2.18.
0 0 1
Figure 2.35 shows the two inputs Ex-NOR gate and its
equivalent is depicted in Fig.2.36. From the truth table, it is 0 1 0
very clear that the purpose of an Exclusive-NOR gate is to 1 0 0
output a ‘high’ when both inputs are at the same logic levels. 1 1 1
 Boolean Algebra and Logic Gates 61

Fig. 2.35 Ex-NOR gate Fig. 2.36 Equivalent circuit of Ex-NOR gate

2.6 UNIVERSAL GATE

NAND and NOR gates have a unique property that they are universal. It means that universal gates
are able to mimic the operation of any other gates. For an example, the interconnected NAND gates
can generate the OR function. Similarly, any gates can be replaced by the NAND and NOR gates. The
construction of NOT, Buffer, AND, OR, NOR gate using NAND and NOR gates are explained below:
2.6.1 The NOT Gate Using NAND and
NOR
It is depicted in Fig. 2.37 that there are two ways to construct
a NOT gate or an inverter using NAND and NOR gates. The
first method is that both input terminals of NAND and NOR
gates will be interconnected and it will be same as inverter
input terminal. In Fig. 2.37 (a) and Fig. 2.37(c), both terminals
are interconnected and used as an inverter input terminal. In Fig. 2.37 (a) NOT gate using NAND,
the other method, one terminal is used as input and the unused (b) NOT gate using NAND,
terminal is connected with +Vcc for NAND gate and ground (c) NOT gate using NOR,
(d) NOT gate using NOR
for NOR gate as shown in Fig. 2.37 (b) and Fig. 2.37(d)
respectively.
2.6.2 The Buffer Using NAND and NOR Gate
Figure 2.38 shows the symbol of buffer. The buffer gate construction using NAND
and NOR gates is very simple and two NAND or NOR gates are used for this
Fig. 2.38 Buffer
purpose as given in Fig 2.39 and Fig. 2.40. Actually, two inverters connected in
cascade form behaves as buffer. The output of buffer is same as the input.

Fig. 2.39 (a) and (b) Buffer using NAND gate Fig. 2.40 (a) and (b) Buffer using NOR gate

2.6.3 The AND Gate Using NAND Gate

To construct an AND gate from NAND gates, an inverter or a NOT gate is required to invert the output
of a NAND gate. This inversion cancels out the first inverted operation of NAND gate and the final
result will be AND function as depicted in Fig.2.41. The same function can also be implemented using
NOR gates. Initially all of the inputs are inverted using NOR gates as inverter and then fed to another
NOR gate. So, three NOR gates are required to build up a AND gate as shown in Fig. 2.42.
 62 Digital Electronics: Principles and Applications

Fig. 2.41 AND gate using NAND gate Fig. 2.42 AND gate using NOR gate

2.6.4 The NAND Gate Using NOR Gate

The NAND gate construction using NOR gate is shown in
Fig. 2.43. Here, firstly all inputs are inverted by using NOR
gates and fed to another NOR gate. The NOR gate’s output
is inverted by another NOR gate. Therefore, four NOR gates
Fig. 2.43 NAND gate using NOR gate can implement a NAND gate.

2.6.5 The OR Gate Using NAND and NOR

Figure 2.44 shows the construction of OR gate using NAND gates. Initially, all inputs are inverted by
using NAND gates and then results are fed to another NAND gate for getting OR function. In this way,
an OR gate can developed using three NAND gates. On the other hand, an OR gate can be created by
inverting the output of a NOR gate as shown in Fig. 2.45.

Fig. 2.44 OR gate using NAND gate Fig. 2.45 OR gate using NOR gate

2.6.6 The NOR Gate Using NAND

Gate
The procedure for making NOR gate using NAND gate
is same as construction of OR gate using NAND gate.
All inputs are inverted and used as inputs of a NAND
gate. After that, NAND gate’s output is inverted by
another NAND gate. So, the NOR gate function can
be developed by using four NAND gates as depicted
Fig. 2.46 NOR gate using NAND gate in Fig. 2.46.
 Boolean Algebra and Logic Gates 63

Example 2.4 Write the truth table of the logic circuit as shown in Fig. 2.47.

Fig. 2.47
� Solution
Truth table of the logic circuit expression A + B + CD is given below:
Table 2.19 Truth table for A + B + CD
Inputs A+B CD A + B + CD A + B + CD
A B C D
0 0 0 0 1 0 1 0
0 0 0 1 1 0 1 0
0 0 1 0 1 0 1 0
0 0 1 1 1 1 1 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 0 1
0 1 1 0 0 0 0 1
0 1 1 1 0 1 1 0
1 0 0 0 0 0 0 1
1 0 0 1 0 0 0 1
1 0 1 0 0 0 0 1
1 0 1 1 0 1 1 0
1 1 0 0 0 0 0 1
1 1 0 1 0 0 0 1
1 1 1 0 0 0 0 1
1 1 1 1 0 1 1 0

Example 2.5 Draw the circuit diagram of the logic expression

———
O = A + BC + ACD
� Solution
The logic circuit diagram of Boolean expression is shown in Fig.
2.48. It is clear from this figure that two AND gates, one NOR gate
and one OR gate are required to implement the logical equation
———
O = A + BC + ACD Fig. 2.48

Example 2.6 Draw the circuit diagram of the logic expression

O = AB + BC + AC + BD

� Solution
Figure 2.49 shows the logic circuit diagram for the logic expression

O = AB + BC + AC + BD. The AND gates, two inverters, one NOR, and two
OR gates are used to implement the above logical equation. Fig. 2.49
 64 Digital Electronics: Principles and Applications

Example 2.7 Draw the output of the two input Ex-NOR gate with the given inputs A and B.

Fig. 2.50

� Solution
The A waveform can be read as 10101 and B waveform can be represented as 11011. The digital output of
OR gate will be 10000. The waveform of output is given below:

Fig. 2.51

2.7 SIMPLIFICATION OF LOGIC CIRCUITS

The logic circuit is defined as a circuit, which is developed, by combinations of logic gates. The outputs
of the logic circuit at any given time depends on the logic inputs at that instance. Therefore, due to
change in input combinations, output will be changed. During the logic implementation, we can use
the original Boolean expression directly or we can use Boolean laws for simplification of the logic
expression to reduce number of gates in logic circuit.
Consider a Boolean expression O = AB + BC (B+C).
This expression can be implemented by using three AND
gates and two OR gates as shown in Fig. 2.52. Now, the
task is circuit simplification by using Boolean Laws.
The step-by-step procedure is explained here.
The original expression O is equal to AB + BC(B + C).
Fig. 2.52
O = AB + BC(B + C).
After distributing terms, we get AB + BBC + BCC
Then apply Boolean law AA = A to second and third term, we find AB + BC + BC
We apply A + A = A, we get AB + BC
Taking common B from both terms, we determine B(A + C)
 Boolean Algebra and Logic Gates 65

So, after using Boolean laws in original expression, we get the simplified expression O = B(A + C).
To implement this logic expression, one OR gate and one AND gate are required as shown in Fig. 2.53.
It is very clear from Fig. 2.52 and Fig. 2.53 that the second imple-
mented logic circuit is most simple from the original one. Here,
only two logic gates are used instead of five. As a result, this circuit
has the following advantages: higher operating speed, less power
Fig. 2.53 consumption, less cost, and more reliability.
Another Boolean expression is O = A + B(A + C) + AC. We apply Boolean Laws to reduce this
expression to its simplest form.
O = A + B (A + C) + AC
After distributing terms, we find O = A + AB + BC + AC
Apply Boolean law A + AB = A in first and second terms, we get O = A + BC + AC
Then apply A + AB = A in first and third terms, we obtain O = A + BC
The simplified form of the expression, O = A + B(A + C) + AC is O = A + BC.
Simplification of Boolean expression by using De Morgan’s
laws. Consider the expression A + BC . The digital implementation
of this logic expression is given in Fig. 2.54.
By using the De Morgan’s laws, we break the bar covering the
Fig. 2.54
entire expression as

A + BC = A . BC
= – –
Applying double complements identity, A = A we get A BC
Therefore, the original circuit can be implemented by using a three-
input AND gate and a inverter as shown in Fig. 2.55.
Fig. 2.55
Simplification of logic expression O = A + BC + AB
To represent this logic expression, we apply two NOR, one AND, one NAND and one Inverter as
depicted in Fig. 2.56.

Fig. 2.56

To reduce the above logic expression, Boolean identities and De Morgan’s theorems are used as
follows:
After breaking the longest Bar of logic expression O = A + BC + AB , we get (A + BC) (AB)
 66 Digital Electronics: Principles and Applications

= –
Applying double complements A = A, we get (A + BC) (AB )
– –
Then applying distribution law, we obtain AAB + BCAB
– –
Applying Boolean identity AA = A and AA = 0, we get AB + 0
–
After applying identity A + 0 = A, we finally get AB
–
The simplified logic expression AB can be implemented by using logic gates. Figure 2.57 shows the
equivalent circuit of the expression. This figure consists of one inverter
and one AND gate.
Another logic expression is considered for circuit simplification task.
The equation is Fig. 2.57
– – –
O = A BC + AB C + ABC + ABC.
The logic circuit based on this
expression can be designed by using
four three input AND gates, three
Inverters and one four input OR gate
as shown in Fig. 2.58.
The above circuit is quite complex.
The expression can be significantly
simplified by using Boolean laws.
The steps of simplification are given
below: Fig. 2.58
– – –
O = A BC + AB C + ABC + ABC
– – –
Factoring BC of the first and forth terms, we get O = BC(A + A) + AB C + ABC
– – –
Applying identity A +A = 1, we find BC + AB C + ABC
– –
Factoring B from first and third term, B(C + AC ) + AB C
– –
Apply Boolean identity A + A B = A + B, we get B(C + A) + AB C
–
After applying distribution law, we obtain BC + AB + AB C
–
Taking common A from second and third terms, we get BC + A(B + B C)
–
Then apply Boolean identity A + A B = A + B and
we find BC + A(B + C)
After distributing, we finally get BC + AB + AC
Therefore, the simplified logic circuit can be
developed by using logic expression BC + AB + AC.
Figure 2.59 shows the logic circuit for BC + AB + AC
which is consists of three two inputs AND gates and
Fig. 2.59 three inputs OR gate.
 Boolean Algebra and Logic Gates 67

Example 2.8 Simplify the following logic expressions.

–– – – –– – – ––
(a) O= ABC D + AB C D + ABC D
–– – – – – – –– –––
(b) O= ABC D + A BC D + ABC D + ABC D
– – –
(c) O= (A + B + C ) + (A + B + C )
� Solution
–– – – –– – – –– ––
(a) O = ABC D + AB C D + ABC D Factoring out AC
–– –– – – –
= AC (BD + B D + BD) Factoring out B from first and
–– – –
second terms of (BD + B D + BD)
–– – – – –
= AC (B(D + D) + BD) Applying D + D = 1)
–– – –
= AC (B + BD)
–– – – – – – –– –––
(b) O = ABC D + ABC D + ABC D + ABC D
––– – –– – –––
= AC D(B + B) + AC D(B + B) Factoring out AC D from first and second terms
–– – – – – – –– –––
of O = ABC D + ABC D + ABC D + ABC D
––
and AC D from third and fourth terms
––– ––
= AC D + AC D
– –– –
= (A + A)C D Applying (A + A) = 1
––
= CD
– – –
(c) O = (A + B + C ) (A + B + C ) Applying distribution identity
– – –– – – –– –
= AA + AB + AC + AB + BB + B C + AC + C B + C C)
–
Applying AA = A and C C = 0

– – – – – ––
= A + AB + AC + AB + B + B C + AC + C B + 0) Factoring out A from first to fourth terms
–
and seventh term and B from fifth, sixth
– – – – – –
= A (1 + B + C + B + C ) + B (1 + C + C ) = A + B and eighth terms.

Example 2.9 Simplify the following logic expressions using De-Morgan’s Theorem.
–
(a) O = (A + B + C) (A + B– + C)
(b) O = A + BCD
(c) O = (A + B + CD–)AB
� Solution
– – –– – –
(a) O = (A + B + C) (A + B + C) = A + B + C + A + B + C = A B C + ABC
– – – –
(b) O = A + BCD = A · BCD = A (B + C + D)
–– –– – – – – –– – –
(c) O = (A + B + C D)AB = (A + B + CD) + AB = ABC D + A + B = A B (C + D) + A + B
 68 Digital Electronics: Principles and Applications

Example 2.10 Make truth table of the binary expression O = A + B + C.D

� Solution
The truth table of the binary expression O = A + B + C.D is given in Table 2.20.
Table 2.20 Truth table for O = A + B + C.D

Inputs Output
A B C D A+B C.D A + B + C.D
0 0 0 0 0 0 0
0 0 0 1 0 0 0
0 0 1 0 0 0 0
0 0 1 1 0 1 1
0 1 0 0 1 0 1
0 1 0 1 1 0 1
0 1 1 0 1 0 1
0 1 1 1 1 1 1
1 0 0 0 1 0 1
1 0 0 1 1 0 1
1 0 1 0 1 0 1
1 0 1 1 1 1 1
1 1 0 0 1 0 1
1 1 0 1 1 0 1
1 1 1 0 1 0 1
1 1 1 1 1 1 1

Example 2.11 Derive the logic expression from the truth table and implements the logic circuit
using NAND gates.
Table 2.21
Inputs Output
A B C O
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
Fig. 2.60
� Solution
– – –– – –
The logic expression of the above truth table is O = A BC + A BC + ABC + ABC and it can be simplified by
using Boolean laws as given below. The final result is A.C AB and hardware implementation with the help
of NAND gates is depicted in Fig. 2.60.
– – –– – – –– – –
O = A BC + A B C + ABC + ABC = A C (B + B ) + AB(C + C)
––
= A C + AB = A.C AB
 Boolean Algebra and Logic Gates 69

2.8 CONSENSUS THEOREM

– – – –
(a) AC + BC + AB = AC + BC (b) (A + C)(B + C ) (A + B) = (A + C)(B + C )
–
Assume a three variables logic function F = AC + BC in which variable C is present in one of the
–
terms and the complement of C, (C ) is present in the other term. An extra product term of the remaining
–
two variables, AB is added in the logic function and it becomes F = AC + BC + AB. This extra product
term, AB is known as consensus term. It can be proved that the output of F is equal to the output of as
fol lows:
–
F = AC + BC + AB
– – –
= AC + BC + AB(C + C ) Applying (C + C ) = 1
– – – – –
= AC + BC + ABC + ABC = AC + ABC + BC + ABC = AC(1 + B) + BC (1 + A)
–
= AC + BC Applying (1 + B) = 1 and (1 + A) = 1
Hence, the presence of consensus term in a Boolean function does not change the value of function
and the optional product term AB is redundant. But sometimes, the consensus term may eliminates other
terms and simplify the original Boolean equation. For example, assume a Boolean function F 1 = C +
–
ABC . For this function, the consensus term is AB which is added to the Boolean function F 1 and the new
Boolean function is F 2 .
– – – –
F 2 = C + ABC + AB = C + ABC + AB(C + C ) Applying (C + C ) = 1
– – –
= C + ABC + ABC + ABC = C + AB(C + C) = C + AB
–
Now, the original term ABC has been eliminated from original Boolean function and the consensus
term AB becomes essential. The technique of forming consensus terms and add them to a Boolean
function without changing its value is known as consensus theorem.
The duality principle is that a theorem can be obtained from another theorem by interchanging binary
operators ‘+’ and ‘.’ and the identity elements ‘0’ and ‘1’. For example, ‘A + 1 = 1’ is given as a theorem,
we can obtain its dual by interchanging ‘+’ with ‘.’. Then the new theorem is ‘A.0 = 0’. In the same way,
if ‘A.0’ is given as a theorem, we can obtain‘A + 1 = 1’ as dual. By using the duality principle, we can
– – –
prove that (A + C)(B + C ) (A + B) = (A + C)(B + C ) as this Boolean function is the duel of AC + BC +
–
AB = AC + BC by changing ‘+’ with ‘.’ and ‘.’ with ‘+’.
– –
Example 2.12 Prove that ABC + DC + ABD = ABC + DC using consensus theorem.
� Solution
–
Consider F = ABC + DC
–
= ABC + DC + ABD Add the consensus term ABD
– – –
= ABC + DC + ABD(C + C ) Applying (C + C ) = 1
– –
= ABC + DC + ABDC + ABDC
–
= ABC (1 + D) + DC (1 + AB)
–
= ABC + DC As (1 + D) = 1 and (1 + AB) = 1
 70 Digital Electronics: Principles and Applications

2.9 POSITIVE LOGIC AND NEGATIVE LOGIC

The Binary input – output signals have always
one of two values: logic ‘0’ and logic ‘1’.
There are two different ways to assign a signal
value to logic level such as positive logic
and negative logic. Figure 2.61 shows the Fig. 2.61 Positive logic
representation of positive logic and negative
logic representation is illustrated in Fig. 2.62.
In this figures, H stands for higher signal level
when signal value is high. Similarly, L stands
for lower signal level when signal value is low.
Fig. 2.62 Negative logic
When high level signal H represents logic ‘1’
and low level signal L corresponds to logic ‘0’, this signal representation is known as positive logic. If signal
level H represents logic level ‘0’ and signal level L stands for logic ‘1’, this method of signal representation
is called as negative logic. Therefore, positive and negative logic levels are not actual signal values, but they
are different types of logic.
Integrated circuit manufactures always mention the logic level of digital gates in their data sheet. For
example, the representation of positive logic AND and OR gates and negative logic AND and OR gates are
illustrated in Fig. 2.63 (a), (b), (c) and (d) respectively. The truth table of positive as well negative logic AND
and OR gates are given in Fig. 2.63(e), (f), (g) and (h) correspondingly. The small triangle in the input and
output terminals of negative logic AND or OR gate or any other gates stand for polarity indicator. When the
polarity indicator is absent in a logic symbol of gates, the logic gates operate in positive logic. In the same
way, when the polarity indicator is present in a logic symbol of gates, the logic gates operate in negative logic.
During design of logic circuit, sometimes it is necessary to convert positive logic to negative logic or vice
versa. When we convert positive logic to negative logic, logic level ‘1’ changes to logic level ‘0’ and logic level
‘0’ changes to logic level ‘1’. Figure 2.63(d) shows the negative logic OR gate and its truth table is Fig. 2.63(h).
If AND operation is compared with the truth table of negative OR gate, we find that the negative logic OR gate
is equivalent to positive logic AND gate. Similarly, negative AND gate can represent an positive logic OR gate
when we convert positive logic to negative logic. Therefore, if any logic circuit represented by AND and OR
gates and the logic level changed from positive to negative, all AND gates will be replaced by negative OR
gate and all OR gates will be substituted by negative AND gate to maintain the same output functions.

Fig. 2.63 (a) Positive logic AND gate (b) Negative logic AND gate (c) Positive logic OR gate
(d) Negative logic OR gate (e) Truth table of positive logic AND gate
(f) Truth table of negative logic AND gate (g) Truth table of positive logic OR gate
(h) Truth table of negative logic OR gate
 Boolean Algebra and Logic Gates 71

SUMMARY
In this chapter, the operation, symbol and truth table of logic gates are conferred. The summary of logic gates is
represented in Table 2.22. The universal gates and their applications to form any gates are incorporated. A brief
introduction to Boolean laws, De Morgan’s theorem, Consensus theorem and positive and negative logic are also
discussed. The simplification of logic expressions using Boolean laws and De Morgan’s theorem explained with
examples. The implementation of logic functions using logic gates is also given.

Table 2.22 Summary of logic gates

Gate Logic Symbol Truth Table

Buffer
Input Output
A O=A
0 0
1 1

Inverter
Input Output
–
A O=A
0 1
1 0

AND
Inputs Output
A B O = A.B
0 0 0
0 1 0
1 0 0
1 1 1

NAND
Inputs Output
——
A B O = A.B
0 0 1
0 1 1
1 0 1
1 1 0

OR
Inputs Output
A B O=A+B
0 0 0
0 1 1
1 0 1
1 1 1
(Contd.)
 72 Digital Electronics: Principles and Applications

Table 2.22 (Contd.)

NOR
Inputs Output
—–—
A B O = A +B
0 0 1
0 1 0
1 0 0
1 1 0

XOR
Inputs Output
A B O=A B
0 0 0
0 1 1
1 0 1
1 1 0

XNOR
Inputs Output
———
A B O=A B
0 0 1
0 1 0
1 0 0
1 1 1

MULTIPLE CHOICE QUESTIONS

1. In a positive logic circuit,
(a) Logic 0 and 1 represented by 0V(ground) and positive voltage(+VCC) respectively
(b) Logic 0 and 1 represented by negative and positive voltages respectively
(c) Logic 0 voltage level is higher than logic 1 voltage level
(d) Logic 0 voltage level is lower than logic 1 voltage level
2. In negative logic, the logic 1 state corresponds to
(a) Ground level (c) High voltage level
(b) Negative voltage level (d) Low voltage level
3. A NAND gate is called a universal logic element because
(a) All digital computers use NAND gates
(b) All the minimisation techniques are applicable for optimum NAND gate realisation
(c) Everybody use this gate
(d) Any logic function can be realised by NAND gates alone
4. If a input signal A=11100 is applied to a NOT gate, its output signal is
(a) 00011 (b) 01001 (c) 00011 (d) 1000
 Boolean Algebra and Logic Gates 73

5. A 3 inputs logic gate has its three inputs: A = 1, B = 0 and C = 1. If its output O = 1, the gate is
(a) NOR (b) NAND (c) AND (d) OR
6. When A and B represent the inputs of an Exclusive OR logic gate, its output O will be
– – –—
(a) O = AB + A B (b) O = AB + A + B (c) O = A + B + A B (d) None of these
7. In positive logic, the logic 0 state corresponds to
(a) Zero voltage (c) High voltage level
(b) Any positive voltage (d) Low voltage level
8. A two input OR gate is designed for positive logic. Consider that this gate is operated with negative
logic. Then the logic operation will be
(a) OR (b) AND (c) NOR (d) Ex-OR
9. The following equation corresponds to De Morgan’s theorem in Boolean algebra
–— – –
(a) (A + B)(A + B) = A + AB + B (c) A B = A + B
(b) (A + B)(A + B) = AA + AB + BB + BA (d) None of these
10. A 2 input logic gate has its inputs A = 0, and B = 1. If its output O = 1, the gate would be
(a) NOT (b) OR (c) AND (d) NOR
11. The NOT symbol at the output of an OR gate converts it into-gate
(a) OR (b) NAND (c) AND (d) NOR
12. The Boolean algebra is based on the premise that
(a) Differential equations can be solved by analog circuits
(b) There are two states
(c) Data can be stored and retrieved
(d) None of these
13. Which of the following functions is referred as complementary?
(a) NAND (b) NOR (c) OR (d) NOT
14. What are the values of the inputs for a NAND gate if output is 1?
(a) A = 0, B = 0 (b) A = 1, B = 0 (c) A = 0, B = 1 (d) A = 1, B = 1
15. What is the output function of the circuit shown in Fig. 2.64?

Fig. 2.64

(a) O = ABCD (b) O = AB + CD (c) O = AB + CD (d) None of these

16. Which function is implemented by the circuit as shown in Fig. 2.65?

Fig. 2.65
(a) O = ABC (b) O = A + B + C (c) O = AB + C (d) None of these
17. Boolean algebra is different from ordinary algebra in which way?
(a) Boolean algebra can represent more than 1 discrete level between 0 and 1.
 74 Digital Electronics: Principles and Applications

(b) Boolean algebra have only 2 discrete levels: 0 and 1.

(c) Boolean algebra can describe up to levels of logic levels.
(d) They are actually the same.
18. If output of a three inputs OR gate is ‘0’, what are the conditions of inputs A, B, and C ?
(a) A = 0, B = 0, C = 0 (b) A = 1, B = 0, C = 0 (c) A = 0, B = 1, C = 0 (d) A = 1, B = 1, C = 1
19. What is the output of the circuit shown in Fig. 2.65 if A = 0, B = 1 and C = 0
(a) 0 (b) 1 (c) High impedance (d) None of these
20. De-Morgan’s law converts
(a) OR to NOR (b) NOR to NAND (c) NOR to AND (d) None of these

REVIEW QUESTIONS
2.1 Draw the logic symbol of four input AND gate and write the truth table of four input AND gate.
2.2 Draw the circuit diagram of Ex-OR gate using NAND and NOR gates.
2.3 Write the truth table of the logic circuit as given below:

Fig. 2.66
2.4 Derive the logic expression of the logic circuit as given below and also write the truth table.

Fig. 2.67
2.5 Draw the output of the two input NAND gate with the given inputs A and B.

Fig. 2.68
2.6 Draw the output of the two input AND gate with the given inputs A and B.

Fig. 2.69
2.7 Draw the output of the three input NAND gate with the given inputs A, B and C.

Fig. 2.70
 Boolean Algebra and Logic Gates 75

2.8 Draw the output of the three inputs Ex-OR gate with the given inputs A, B and C.

Fig. 2.71
2.9. Prove the following identities of Boolean algebra
– –
(a) A + A = A (b) A. A = 0 (c) A + A = 1 (d) A.A = A
2. 10 Prove the commutative law
(a) A + B = B + A (b) AB = BA
2.11 Prove the distributive law
(a) A + (BC) = (A + B)(A + C) (b) A(B + C) = (AB) + (AC)
2.12 Prove the following relationship
(a) AB + AC + BC = AB + AC (b) (A + B)(A + C)(B + C) = (A + B)(A + C)
2.13 Simplify the following logic expressions.
–– – – –– – –– – ––
(a) O = A B C D + A B C D + A B CD + A B CD
–– – –
(b) O = A B D + AB D + ABD + B CD
–– – –– –
(c) O = ABC + ABD + A B C + A B D
2.14. Simplify the following logic expressions using De Morgan’s Theorem
––
(a) O = (A + BC) (A B + C) (c) O = AB + CD
––
(b) O = A + B + CD (d) O = (AB + CD)
2.15 Make truth tables for each of the following 1-bit binary expressions.
–
(a) O = A B + C (c) O = ABC + D
– –—
(b) O = A + BC (d) O = AB + CD
–
(e) O = BC + AD
2.16 Derive the logic expression from the truth table as given in Table 2.23 and implements the logic
circuit using NAND or NOR gates.
Table 2.23

Inputs Output
A B C O
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
 CHAPTER

3
DIGITAL LOGIC FAMILY

3.1 INTRODUCTION
The logic gates are discussed in Chapter 2. Presently, these gates are available in integrated form and
the digital Integrated Circuits (ICs) are most commonly used in complicated digital circuits design. The
logic gates can be designed in different methods. Therefore, there are different types of logic family, but
unipolar and bipolar logic family are the main logic family. Transistors, diodes and resistors are main
elements of bipolar logic family, but MOSFETs are used in unipolar logic family. In this section, bipolar
and unipolar logic families are discussed briefly.

3.2 CLASSIFICATION OF DIGITAL LOGIC FAMILY

The digital logic family has broadly two-categories, namely bipolar logic and unipolar logic. The bi-
polar logic families are classified as saturated and unsaturated types. In saturated type of bipolar logic
family, transistors are operated in between cut-off and saturation. Resistor transistor logic (RTL), Di-
rect coupled transistor logic (DCTL), Integrated
injection logic (IIL or I2L), Diode transistor logic
(DTL), Transistor transistor logic (TTL), and High
threshold logic (HTL) are commonly used bipolar
logic families. In unsaturated bipolar logic family,
the transistors are operated in between cut-off and
non-saturation. Schotty TTL and Emitter coupled
logic (ECL) are examples, of unsaturated bi-polar
logic family. There are two types of unipolar logic
family, namely p-channel MOS (PMOS) and n-
channel MOS (NMOS) and complementary MOS
Fig. 3.1 Classification of digital logic family
(CMOS). The classification of digital logic family
is shown in Fig. 3.1. The logic family can also be classified into four groups depending on the number
of transistors in an IC. Table 3.1 shows all four groups. The various logic types of logic families are
explained in this chapter.
 Digital Logic Family 77

Table 3.1 Classification of logic family based on complexity measured by number of transistors
Name of Group No of Transistors Applications
Small scale integration Less than 100 SSI circuits are used for educational purposes, and inter-
(SSI) face complex digital devices.
Medium scale Above 100 but below 1000 MSI circuits used in multiplexers, demultiplexers, regis-
integration(MSI) ters, and counters, etc.
Large scale Above1000 but below 10000 LSI circuits are used in small memory chips, and pro-
integration(LSI) grammable logic devices.
Very large scale More than 10000 VLSI are applied in large computer memories, micropro-
integration(VLSI) cessors, microcontrollers, and digital signal processors

3.3 CHARACTERISTICS OF DIGITAL LOGIC FAMILY

Before discussion on various types of logic families, the performance parameters of a logic family are
explained for better understanding. The most important performance parameters are given below:
∑ Speed of operation
∑ Power dissipation
∑ Voltage parameters
∑ Current parameters
∑ Noise immunity
∑ Fan in
∑ Fan out
∑ Cost
∑ Availability
The designer should select a particular logic family for any application based on the actual requirement.
To design a efficient logic circuit, the designer should
study the performance parameters from IC manuals
in detail.
Speed of Operation The operating speed of a
logic family is determined from the propagation delay.
If a square wave is applied to the input of an inverter,
output of the inverter will be a square wave as shown in
Fig. 3.2. It is very clear from Fig. 3.2 that the propagation
delay is measured from the time difference between
50% logic transition of input from its initial value and
50% logic transition of output. There are two types of
propagation delay times, namely tPHL and tPLH. Fig. 3.2 Input and output waveform of an
inverter
The propagation delay tPHL is the delay time when
output changes from HIGH to LOW due to change in input. Similarly, tPLH is the propagation delay for output
changes from LOW to HIGH. Generally, tPHL and tPLH are very close to each other. Actually, we consider
the average value of tPHL and tPLH. The propagation delay varies in between 1 to 20 nano seconds. For proper
operation of a logic gate, the time period of input signal must be more than propagation delay time. If input
frequency is very high, and cycle time is less than propagation delay, the switch starts malfunctioning.
 78 Digital Electronics: Principles and Applications

Power Dissipation Power dissipation is the amount of

power drawn from supply during static and dynamic condition. In
static condition, the power dissipated in a logic gate is called static
power consumption and similarly, the dynamic power consumption
takes place in dynamic condition or switching transitions. The static
power consumption is the power dissipated in logic gate when the
device is either ON or OFF. During the transition from OFF to ON
or ON to OFF, the power consumed in a gate is called dynamic
power consumption. The voltage and current waveforms of logic
gate are depicted in Fig. 3.3.
The power dissipation is directly proportional to switching
frequency and inversely proportional with cycle time. CMOS ICs
have very low power consumption at low frequency. If frequency
Fig. 3.3 Voltage and current
wave form of a logic gate increases, power dissipation increases. The average power
dissipation is determined by the simplest expression VCCIC, where
IC is the average value of current. Generally, the power dissipation
varies in the range of milli-watts (mW).
Voltage Parameters
High level input voltage (VIH ): VIH is the minimum input voltage guaranteed to be recognised as
logic 1 or HIGH. VIH is 2 V for TTL and 3.5 V for CMOS. If input voltage is less than VIH, it will not be
accepted as logic 1 or HIGH.
Low level input voltage ( VIL ): VIL is the maximum input voltage guaranteed to be recognised as
logic 0 or LOW. VIL is 0.8 V for TTL and 1.5 V for CMOS. When input voltage is greater than VIL, it will
not be accepted as logic 0 or LOW.
High level output voltage (VOH ): VOH is the minimum output voltage for HIGH state or logic1
under defined load conditions. VOH is 2.4 V for TTL and 4.9 V for CMOS.
Low level output voltage (VOL): VOL is the maximum output voltage for LOW state or logic 0. VOL
is 0.4V for TTL and 0.1V for CMOS.
Current Parameters
High level input current (IIH): IIH is the current that flows into an input when a high level or logic
‘1’ voltage is applied to that input.
Low level input current (IIL): IIL is the current that flows into an input when a low level or logic
‘0’ voltage is applied to that input.
High level output current (IOH): IOH is the maximum current that flows from an output and the
output can source in HIGH state or logic ‘1’ while still maintaining the output voltage above VOH.
Low level output current (IOL): IOL is the maximum current that the output can sink in LOW state
or logic ‘0’ while still maintaining the output voltage below VOL.
Noise Immunity Noise is always present in electronics circuits due to stray electric and magnetic
fields. This signal is unwanted and spurious. Sometimes, the noise signal distorts the output voltage
of the gate. Noise immunity of a logic gate means the circuit’s ability to tolerate noise. In order to
correctly recognise logic ‘0’ and logic ‘1’ states, noise immunity is measured quantitatively which is
 Digital Logic Family 79

known as noise margin (NM). There are two types of noise margin such as low noise margin and high
noise margin.
Low noise margin (LNM), VNL: VNL is the largest noise amplitude that is guaranteed for no change
of the output voltage level when the input voltage of the logic gate is in the LOW interval. The low noise
margin is measured by the expression as given below:
VNL =VIL– VOL.
High noise margin (HNM), VNH : VNH is the largest noise amplitude that is guaranteed for no
change of the output voltage level when the input voltage of the logic gate is in the HIGH interval. It is
measured by
VNH = VOH – VIH.
Fan In Fan in is the maximum number of inputs for a logic gate in a particular logic family. This
number is limited due to delay time. For example, a two inputs AND gate has fan-in of two, a three
inputs OR gate as a fan-in of three and a NOT gate or an inverter has a fan-in of one. Generally, delay
of operation of any gate increases with increasing fan-in quadratically. Gate delay is the delay offered
by a gate for the signal applied at input terminals, before it reaches the gate output. Gate delay is also
known as propagation delay.
Fan Out Fan out is defined as the number of similar logic gates driven by a single logic gate. While
a logic gate has high fan out, it is advantageous to design integrated chips, as less number of driving
circuits are required. The fan-out depends on the amount of source or sinks current of a gate while the
gate drives other gates. When a logic gate output with more than its rated fan-out, the logic gate has the
following effects:
∑ The operating temperature of the device will be increased. Hence, reliability of the device will
be reduced and eventually the device may fail.
∑ Propagation delay will be increased and it may be above specified value.
∑ The output rise and fall times may be increased beyond specification.
∑ In the low state, the output voltage VOL may increase above maximum value of VOL .
∑ In the high state, the output voltage VOH may decrease below the minimum value of VOH .
The factors that limit the fan-out of a gate are the output current capacity as specified by the parameters
IOH and IOL, and the input current requirements of the driven gates as specified by their parameters IIH and
IIL. Certainly, the sum of the currents IIH for all the gates driven by a gate must be less than the current IOH
of the driving gate. In the same way, the sum of the IIL current parameters must be less than IOL for these
gates. When all of the gates have the same current parameter values, then the fan-out due to current
considerations can be expressed by a constant integer which is the maximum number of gate inputs that
can be connected to a single gate output. The fan-out can be defined as the largest integer less than or
equal to minimum of (IOH/IIH, IOL/IIL), where IOH/IIH is the number of gates that can be driven by a single
gate when output signal is high, and IOL/IIL is the maximum number if the output signal is low. Figure
3.4 shows a TTL AND gate drives ‘N’ numbers of similar AND gates for high level output and low level
output. Here, N is the fan out of the gate and it can be determined from current driving capability of
output and the current requirement of input. If maximum current driving capability IOH and maximum
current requirement of each input IIH are known, the fan out of the gate will be
 80 Digital Electronics: Principles and Applications

I OH
N=
I IH
For example, consider IOH is equal to 500µA
and IIH is 25µA. The fan out is
I 500
N = OH = = 20.
I IH 25
Cost The cost of a digital IC depends on the
quantity manufactured. The designer always tries
to design low cost ICs though the quantity of ICs
Fig. 3.4 (a) Fan out computation for high level output used is large.
(b) Fan out computation for low level output Availability To choose a logic family for
particular applications, availability is an impor-
tant parameter. Availability can be considered in to different ways as given below:
The popularity of the logic family: The popularity of a particular logic family depends upon
the users and digital circuit designers. If application of a logic family is more, a large number of ICs of
that logic family will be manufactured. Therefore, the cost per IC will be very small and easily available
in the market.
The breadth of the logic family: The breadth of the logic family means to the number of different
logic functions, ICs available. The complex functions would have to be constructed using basic ICs. For
example, the TTL logic family has very good popularity and high breadth over other logic families.
Wired logic capability: Due to wired-logic capability, the outputs may be connected jointly to
achieve extra logic without additional hardware. Various flexibilities are available in different IC logic
families and these must be considered while selecting a logic family.
Availability of complement outputs: If the complement of outputs is available in ICs, the ad-
ditional inverter is not required to invert the output.

Example 3.1 Calculate the fan out of a NAND gate which drives NAND gates.
Assume IOH = 0.4 mA, IOL = 16 mA, IIH = 0.1 mA, and IIL = 0.4 mA.
� Solution

I OH 0.4
Fan out at high level output, N = = = 20
I IH 0.02

I OL 16
Fan out at low level output, N = = = 40
I IL 0.4

I OH I OL
The fan-out of the gate is minimum of ( , ) = minimum of (20, 40) = 20
I IH I IL
 Digital Logic Family 81

3.4 BJT CHARACTERISTICS

The characteristic of bipolar junction transistor (BJT), which is used
in internal structural design of digital circuits has been discussed in
this section. Bipolar transistors are n-p-n and p-n-p type and they are
constructed either with germanium or silicon semiconductor material.
Generally, IC transistors are made with silicon and they are usually n-p-
n type. The schematic symbol of n-p-n and p-n-p transistors with base
(B), emitter (E) and collector (C) terminals are shown in Fig. 3.5(a) and
(b) respectively.
The information about the characteristic curves of a common emitter Fig. 3.5 Schematic symbols
n-p-n silicon transistor as shown in Fig.3.6 are required for the analysis of (a) n-p-n BJT
of digital circuits. Figure 3.6 (a) is a simple inverter circuit which is and (b) p-n-p BJT
consists of two resistors RC and RB and a transistor. The current IC flows
through the resistor RC and the collector of the transistor. This current is known as collector current.
The current IB flows through the resistor RB and the base of the transistor. This current is called as base
current. The emitter terminal is grounded and the current flows through emitter IE = IC + IB. The VCE
stands for the collector to emitter voltage and VBE stands for base emitter voltage.

Fig. 3.6 (a) Inverter circuit (b) Base characteristics of npn transistor
(c ) Collector characteristics of npn transistor

The base–emitter characteristic of n-p-n BJT is illustrated in Fig. 3.6(b). This is the plot of base
current variation with respect to VBE. For silicon made transistor, when the base emitter voltage VBE is
less than 0.6V, the transistor is said to be cut-off. Consequently, base current IB = 0 and very small current
flows in the collector. Then collector to emitter circuit behaves as an open circuit. When the base-emitter
junction is forward biased and is greater than 0.6V, the transistors starts to conduct and the base current
IB increases rapidly as shown in Fig. 3.6(b) and the voltage across base-emitter junction is about 0.8V.
The collector emitter characteristics with a typical load line are shown in Fig. 3.6( c). When VBE is
less than 0.6V, the transistor is at cut-off and no base current flows, but negligible current flows in the
collector. The collector to emitter circuit behaves like an open circuit. In active region, the collector
to emitter voltage VCE can be varied from about 0.8V to VCC. The collector current in this region is
approximately hfe IB, where hfe is the dc current gain of the transistor. It should be noted that the maximum
collector current does not depend on the IB, but on the external resistance RC. Therefore, VCE is always
positive and its lowest possible value is 0V. After assuming VCE = 0, the maximum IC current can be
determined from IC = VCC/RC.
 82 Digital Electronics: Principles and Applications

Table 3.2 Parameters of the typical n-p-n silicon transistor The relationship between collector
current and base current IC = hfe IB is
Operating VBE (V) VCE (V) Current rela-
region tionship
valid only when the transistor operates
at active region. The parameter hfe
Cut-off <0.6V Open circuit IB = IC = 0
varies widely over the operating range
Active 0.6 to 0.7V >0.2V IC = hfe IB of the transistor, but it is very useful to
Saturation 0.7 to 0.8V 0.2 V I ≥
hfe B CS I consider an average value for the shake
of analysis of transistor. In a typical
operating range, hfe is about 50 and it may be varied up to 20. It can be observed that the base current
may be increased to any desirable value, but the collector current is limited by the external resistance RC.
As a consequence, a situation can be reached when hfe IB is greater than IC. When this condition arises,
the transistor is said to be in saturation region. Thus, the condition for saturation is determined from the
relation hfe IB ≥ ICS, where ICS is the maximum collector current flow during saturation. VCE is not zero in
the saturation region, but it is approximately 0.2V. The typical values
of basic parameters of the transistor characteristics are listed in Table
3.2. The above information will be used for better understanding of
circuits operation and the analysis of basic circuits of all bipolar
logic families which are discussed in this chapter.

3.5 DIRECT-COUPLED TRANSISTOR LOGIC

(DCTL)
Figure 3.7 shows the Direct–coupled Transistor Logic (DCTL) for
a three inputs NOR gate. The input voltage is applied to the base of
transistors and the output is taken from the collector of transistor.
When logic 1 or + VCC is input to A, B, and C, transistors saturate, the
Fig. 3.7 Direct-coupled tran- output voltage drops to its saturation voltage or OV. The operation of
sistor logic (DCTL) DCTL is highly affected due to change in slight differences in charac-
teristics of transistors. If the base emitter of one transistor is slightly
less than other transistors, then transistor draws most of the current and
proper operation of DCTL circuit will be disturbed. This phenomena
is called current hogging. This current hogging can be reduced if resis-
tances are connected in series with base of transistor and then base cur-
rent is less depended on base emitter characteristics. Then the circuit is
called Resistor Transistor logic (RTL).

3.6 RESISTOR TRANSISTOR LOGIC (RTL)

A Resistor Transistor Logic (RTL) circuit of a three inputs NOR gate
is shown in Fig. 3.8. In this circuit, resistance is connected in series
with the base of each transistor to reduce the hogging current effect.
Actually, the input capacitance has been charged and discharged
through this additional resistance and time constant will be increased.
Fig. 3.8 Resistor transistor Therefore, the switching speed becomes slower. The fan-out of RTL
logic (RTL) is four or five and time delay is approximately 50 ns.
 Digital Logic Family 83

If inputs A, B and C are LOW, transistors T1, T2 and T3 are cut-off and the output is HIGH or + VCC. When
any one of the inputs A, B and C is HIGH, the corresponding transistor operates in saturation and the output
will be LOW or 0.2 V approximately. Thus NOR logic is satisfied.
3.7 DIODE TRANSISTOR LOGIC (DTL)
Diode Transistor Logic (DTL) circuit is most commonly
used in logic family. Figure 3.9 shows a DTL logic circuit.
This circuit is actually a NAND gate. To perform logical
operation, inputs are given at the terminals A, B, and C of
the diodes D1, D2 and D3 respectively. Then the signal is
coupled with a diode D and an inverter, which consists of
a transistor and a load resistance.
When all inputs are logical 1 or + VCC, diodes D1, D2,
D3 are reversed biased and no current passes through
diodes. The diode D is forward biased and current will
flow through Resistance RB, Diode D and base of the Fig. 3.9 Diode transistor logic (DTL)
transistor T. Then transistor T operates at saturation. The output voltage of the transistor is logic 0. When
any one input signal is low (A = logical 0, B and C are logical 1), diode D1 is forward bias and current
will flow through RB and D1. Then diode D is not conducting and current will not flow through D and
base of Transistor T. Hence T is in cut-off and output will be high or logic level 1. As the signal passes
through the forward bias diodes to transistor, the switching speed of DTL is faster than RTL. Fan out is
also increased due to high input impedance. The switching delay is approximately 25 ns and fan out is
8. Therefore, DTL integrated circuits are economical.
3.8 TRANSISTOR-TRANSISTOR LOGIC (TTL)
In Transistor Transistor logic (TTL), logic gates are built only around transistors. TTL was developed
in 1965. All TTL families are available in small scale integration (SSI) package and in more complex
forms as MSI and LSI packages. The differences in the TTL series are not in the digital functions that
they perform but rather in the values of resistances and different type transistors which are used to
develop basic gates. There are many versions or families of TTL, such as Standard TTL, High Speed
TTL, Low Power TTL and Schhottky TTL. TTL gates in all the versions come in three different types
of output configuration such as
∑ Totem pole output configuration
∑ Open collector output configuration
∑ Tristate or three states output configuration
TTL circuit is most popular in bipolar logic family as it
is the fastest saturating logic family Figure 3.10 shows the
basic TTL circuit for a two inputs NAND gate. A single
multi-emitter transistor replaces input diodes and the
series diode of DTL. Each emitter-base diode serves
as one input, and the base-collector diode functions as the Fig. 3.10 Transistor-transistor logic
(TTL)
series diode. The multi-emitter transistor is economically
fabricated in monolithic form. In a multi-emitter transistor, a single isolated collector region is dif-
 84 Digital Electronics: Principles and Applications

fused, a single base region is diffused and formed in the collector region, and the several emitter regions
are diffused as separate areas into the base region.
An output stage using an active pull-up transistor is added to the basic logic circuit to give current-
gain drive for switching in both directions. This output configuration results in faster switching speed
and higher fan-out capability. The TTL circuit is adaptable to virtually all forms of IC logic and produces
the highest performance-to-cost ratio of all logic types. TTL circuits for all gates have been discussed
later in detail.
The different series of TTL circuits are presently available. All these circuits are based on the same basic
circuit, but some of their properties have been optimised based on special applications. These devices in
the standard TTL series are designated with a number prefixed by a 74. For example, 7400 stands for a
NAND gate, and 7404 stands for an inverter, etc. If the resistor values in the TTL circuit are increased, its
average power dissipation can be reduced. On the other hand, propagation delay will be increased. This low
power TTL series are designated as 74LXX (74L00, 74L04, etc) and the typical power dissipation range
is 1mW to 10mW for any standard gate. Typical propagation delays are 33ns for 74L circuits as compared
to 9ns for 74 series circuits. The high speed TTL series are designated as 74HXX (74H00, 74H04, etc).
The typical power dissipation of a 74H00 NAND gate is 22.5mW, but its propagation delay is about 6ns.
The 74XX, 74LXX, and 74HXX TTL series are the early logic families. In these circuits, some of
their transistors operate into saturation. Therefore, there is an excess of charge in base region and limits
the speed at which the transistor can switch from the saturated to the cut-off mode. Then the standard
TTL circuit is modified by using a special type of diode called a Schottky-barrier diode to prevent the
transistors from going into saturation. This series is known as Schottky TTL and is designated as 74SXX
(74S00, 74S04, etc.). This series has a typical power dissipation of 18.75mW and a typical propagation
delay of about 3ns. Though 74SXX series use a more complicated circuit than the other series, but due
to high speed, the circuit is more susceptible to noise.
The low-power Schottky TTL series is developed
Table 3.3 Comparison of different TTL family by reducing the resistor values in a Schottky circuit
Series Propagation Power in order to minimise power dissipation. This series
Delay Dissipation is designated as 74LSXX (74LS00, 74LS04, etc.).
74XX 10ns 10mW The propagation delay of 74LSXX series is about
9.5ns and power dissipation is approximately 2mW.
74LXX 33ns 1mW
Consequently, 74LSXX series has about the same
74SXX 3ns 19mW
speed as a standard 74XX series, but the power
74LSXX 9.5ns 2mW dissipation is about one fifth power dissipation of
74HXX 6ns 22mW 74XX series.
74ASXX 1.5ns 10mW The other members of TTL family are the Ad-
74ALSXX 4ns 1mW vanced Schottky and Advanced Low Power Schott-
ky series. The Advanced Schottky is represented by
74AS and the Advanced Low Power Schottky series is designated as 74ALS. These TTL series have
significant improvements in speed and power dissipation over Schottky and Low Power Schottky. The
typical power dissipations of 74AS series gates are about 10mW and 1mW for ALS parts. Due to high
speed and low power consumption, the 74ALS and 74AS series are very popular in design of TTL gates.
The comparison of different TTL family based on speed and power consumption is given in Table 3.3.
 Digital Logic Family 85

3.9 EMITTER-COUPLED LOGIC (ECL)

The emitter-coupled logic circuit is shown in Fig. 3.11.
The emitters of transistors T1, and T3 are coupled with
the emitter of a reference transistor T2. The common-
emitter resistor of transistors T1, T2, and T3 is very high so
that it behaves as a constant-current source. Figure 3.11
depicts a constant current source in place of the common-
emitter resistor of transistors T1, T2, and T3. A reference
voltage VR is connected to the base of transistor T2.
When the inputs A and B are logical ‘0’ or ground
potential, T1 and T3 are in cut-off. Current will not flow
Fig. 3.11 Emitter-coupled logic (ECL)
through RC, and the output Y1 will be logical high, +Vcc.
If one of the inputs or both inputs are logical ‘1’ and greater than the reference voltage VR, transistor
T1 or T3 or both transistors conduct. As current flows through the corresponding transistors and RC, the
collector potential becomes low. Then output Y1 is logical ‘0’.
When current through the transistors T1 or T3 increases, current through the reference transistor T2
decreases. The threshold voltage of T1 or T3 is equal to the reference voltage VR. As Emitter coupling is
present in the circuit, it does not allow transistors to operate in saturation. Therefore, the switching speed
of ECL is very fast and it is approximately few nanoseconds. Power dissipation of ECL is comparatively
high and its value is about 50 mW. As output impedance of ECL circuit is very low, fan-out of this logic
family is very high approximately 25.
Table 3.4 Comparison of logic family
The standard digital circuits of DCTL, RTL,
DTL, TTL and ECL are explained above. The Logic Power Propagation Fan out
designer chooses a particular logic family family dissipation delay
for a specific application after reading all RTL 24mW 50ns 5
performance parameters of each logic family DTL 10mW 30ns 8
from their data sheet. Table 3.4 shows the TTL 10mW 10ns 10
comparison between RTL, DTL, TTL and ECL
ECL 40mW 2ns 25
logic families based on power dissipation,
propagation delay and fan-out.
3.10 SCHOTTKY TTL
The Schottky TTL is a unsaturated logic family and this TTL series is actually known on the name of
Schottky diode inverter. In Schottky TTL circuit, transistors are prevented from saturation by using
Schottky transistors. These transistors are obtained when a Schottky diode is connected between the base
and the collector of a normal transistor as shown in Fig. 3.12(a). Figure 3.12(b) shows the symbol of
Schottky transistors. Schottky diodes have different characteristic from normal p-n junction diodes and
these diodes have very low saturation voltage of the order of 0.4V. In case of normal p-n junction diodes,
the saturation voltage is about 0.6V. In TTL logic family, transistors operate in saturation. When a silicon
transistor operates in saturation, the base to emitter voltage (VBE) is about 0.7V and the collector to emitter
voltage (VCE) is about 0.1V. If a Schottky diode is connected with normal transistor, the collector to emit-
ter voltage (VCE) voltage will be more than 0.4V but less than the base to emitter voltage (VBE). Conse-
 86 Digital Electronics: Principles and Applications

quently, the Schottky diode holds the collector to a voltage, which prevents the transistor to operate in fully
saturation. So, the diffusion capacitance and propagation delay are reduced. Therefore, Schottky transistors
can operate at very high switching speeds and perform consistently up to about 100MHz. A Schottky TTL
NAND is shown
in Fig. 3.13. Tran-
sistors T2 to T6 are
Schottky transistors
and diodes D1 to D5
are Schottky diodes
in Fig. 3.13. All re-
sistances (R1 to R6)
are high value com-
pared to TTL logic
family. Four differ-
ent types Schottky
TTL, namely Schott-
Fig. 3.12 Schottky transistor Fig. 3.13 Schottky TTL NAND gate ky TTL, low power
Schottky TTL, ad-
vanced Schottky TTL and advanced low power Schottky TTL are available. Table 3.5 shows the compari-
son between Schottky TTLs based on power dissipation, propagation delay and fan-out.

Table 3.5 Comparison of logic family

Logic family Power dissipation Propagation delay Fan-out

Schottky TTL 20mW 3 ns 10
Low power Schottky TTL 2mW 10 ns 20
Advanced Schottky TTL 17mW 1.5 ns 40
Advanced low power Schottky TTL 1mW 4 ns 20

3.11 HIGH THRESHOLD LOGIC (HTL)

This logic is particularly designed to work in industrial environments, where the noise level is quite
high. The principle of operation is the same as that of DTL, but the voltage level used is 15V. The noise
margin obtained by HTL is around 7V.

3.12 INTEGRATED INJECTION LOGIC (IIL)

This logic family uses a combination of p-n-p and n-p-n transistors. In an IC, it is always easier to
make p-n-p and n-p-n pair, and such a pair occupies less space. Thus, the packing density on the chip is
improved. Therefore, the gate size is very small.

Example 3.2 Determine the fan out of the DTL circuit as shown in Fig. 3.14.
Assume R = 5KΩ, R1 = R2 =… RN = 10 KΩ, VCE(sat) = 0.2V, VD = 0.7V and IC = 1.8mA.
 Digital Logic Family 87

� Solution
Consider input at terminal A is logic level 1 and other terminals are
in logic level 0. Therefore, transistor T1 operates in saturation.
The current flow through diodes D1, D2 …. DN is IL and it is
calculated by
VCC - VD - VCE (sat) 5 - .7 - .2
IL = = mA = 0.41mA
R1 10
The current flow through the resistance R is I1
VCC - VCE (sat ) 5 - .2
I1 = = mA = 0.96mA
R1 5
Fig. 3.14
The collector current of transistor T1 is
IC1 = N IL + I1 where, N is the fan out
I - I 1.8 - .96
So, the fan out N = C 1 = = 2.04 = 2
IL .41

Example 3.3 Calculate fan out and average power dissipation of DTL circuit as shown in Fig. 3.15.
Assume Vd = 0.7V, VBE = 0.75V, VCE sat = 0.2V, hfe = 50, R1 = 4.7K, R2 = 4.7K, R3 = 3.3K

� Solution
Consider A, B, and C are high and diodes D1, D2 and D3 are reverse
biased. Diode D4 is conducting and transistor T1 is in saturation, the
voltage at P1 is
VP1 = on state voltage of D4 +on state voltage of D5 + VBE sat = 0.7 +
0.7 + 0.75 = 2.15 V
Current flow through D4 is
V - VP1 5 - 2.15
I1 = CC = mA = 0.606 mA
R1 4.7
Current flow through R2 is
V 0.75
I 2 = CE = mA = 0.16 mA
R2 4.7
Applying KCL at P2, the base current of transistor T1
IB = I1 – I2 = (0.606 – 0.16) mA = 0.446 mA
Fig. 3.15
The collector current
V - VCE 5 - 0.2
I C = CC = mA = 1.45 mA
R3 3.3
The hfe IB = 50 ¥ 0.446 mA = 22.3 mA.
As hfe IB is grater than IC, the transistor T1 operates in saturation. The output of the transistor will be low.
To determine the fan out, consider load current IL = 0.9 mA.
 88 Digital Electronics: Principles and Applications

IL N + IC £ 22.3 mA
0.9N + 1.45 £ 22.3 mA
22.3 - 1.45
N= = 23.1
.9
The fan out of the transistor T1 is 23.
The power dissipation in transistor T1 when output is Low
P1 = VCC (I1 + IC) = 5(0.606 + 1.45)mW = 10.28 mW
The power dissipation in transistor when output is High
P2 = VCC I1 = 5 ¥ 0.606 = 0.303 mW
Average power dissipation is
P + P2 10.28 + 0.303
Pav = 1 = mW = 5.29 mW
2 2

Example 3.4 Determine the voltages at P1, and P2 of TTL circuit as shown in Fig. 3.16.
Assume VA= 1.1V, VB = 4.5V, VBE = 0.7V, VCC = 5V, R1 = 4.7K,
R2 = 4.7K, R3 = 2.2K
� Solution
The input voltages at A, B are VA = 1.1V, and VB = 4.5V
respectively. As VA is 1.1V, emitter base junction of T1 to input
terminal A is conduction state.
Consequently, the VP1 = VA + VBE = 1.1V + .7V = 1.8V
The base emitter junction of T2 will be saturate when VP1 = 0.7
+ 0.7 + 0.8 = 2.2V.
As VP1 is 1.8 V, T2 will be OFF but transistor T1 conducts to input
terminal A.
Fig. 3.16 Transistor-transistor logic
Therefore, IB2 = 0 and the output voltage is equal to 5V.
(TTL)
So VP2 = 5V.

3.13 TTL LOGIC GATES

The TTL logic based Inverter, buffer, NAND, AND, OR
and NOR gates are explained below:
3.13.1 The NOT Gate with Totem–
Pole Output
The single-transistor inverter circuit is already explained in
Chapter 2 and this is not most commonly used. Actually, all
practical inverter circuits contain more than one transistor
for improving voltage gain and transistors operate in full
cut-off or full saturation. Other components of inverter
circuit are used to reduce the possibility of damage. Figure
Fig. 3.17 Practical inverter circuit 3.17 shows the practical inverter circuit.
 Digital Logic Family 89

In the circuit as shown in Fig. 3.18, diode D1 will be reverse-biased. As diode D1 is not conducting,
no current will flow through it. Actually, D1 is used in the circuit to protect transistor when a negative
voltage is impressed on the input. With no voltage between the base and emitter of transistor T1, no
current will flow through transistor. A back-to-back pair of diodes can replace T1 as shown in Fig. 3.19.
Depending on the logic level of the input, the function of diodes is to steer current to or away from
the base of transistor T2. When the input is Vcc, no current will flow through the left steering diode of
T1. But, there will be current through the right steering diode of T1 through resistor R1, as well as through
base-emitter diode junction of T2 and T4. So, transistors T2 and T4 will have base current, and T2 and T4
will be turn on. The voltage between the base of T1 and ground will be approximately 2.1 volts. This
voltage drop is equal to the combined voltage drops of three p-n junctions, namely the right steering
diode of T1, base-emitter diode of T2, and base-emitter diode of T4.

Fig. 3.18 Practical inverter circuit with Fig. 3.19 Practical inverter circuit with input VCC
input Vcc
As base current is flow through transistor T2, it will be turned on and it also be saturated. When T2 is
saturated, the voltage drop across resistor R3 will be enough to forward-bias the base-emitter junction of
transistor T4. Therefore, transistor T4 will operate in saturation.
As T4 is saturated, the output voltage will be almost 0 volts or a binary ‘0’ or logic level low. The
voltage between the base of T3 and its emitter is not enough
to turn on it due to diode D2. So, T3 remains in cut-off.
If input is connected with ground as shown in Fig. 3.20, all
of the current goes through the left steering diode of T1 and
none of it through the right diode. We know that p-n junction
diodes are very non-linear devices. If the forward biased
voltage is more than threshold voltage, it conducts. When
diodes begin to conduct, the voltage drop across diodes are
not more than 0.7 volts. In this circuit, the left diode of the
steering diode pair is fully conducting, and the voltage drop
across it is approximately about 0.7 volts.
This eliminates current through the base of T2, thus turning
it off. When T2 is off, there is no longer a path for T4 base Fig. 3.20 Practical inverter circuit
current. So T4 goes into cut-off. On the other hand, T3 has with input ground
 90 Digital Electronics: Principles and Applications

sufficient voltage dropped between its base and ground to forward-bias its base-emitter junction and
saturate it. Accordingly, the output terminal voltage will be logical high. In actuality, the output voltage
will be somewhere around 4 volts depending on the degree of saturation and any load current, but still
high enough to be considered a high logic level.
Now, we can say that the circuit behave as inverter. When input is binary ‘1’ and output is ‘0’. If input
is binary ‘0’ output will be ‘1’. Table 3.6 shows the truth table of inverter.

Table 3.6 Truth table of inverter

Input Transistor Output

A T1 T2 T3 T4 O
Low Saturation Cut-off Saturation Cut-off High
High Cut-off Saturation Cut-off Saturation Low

The advantage of totem-pole output circuits is that there is always one of the totem-pole transistors is
cut-off, except during the transition from one output state to the other output state. Therefore, the required
pull-up resistor R4 should be much smaller than the simple passive pull-up circuit resistance. Since RC
time constant reduces, the time required to charge the input capacitance of gates which is connected to a
totem-pole output decreases. There are some disadvantages of the totem-pole output circuit as follows.
When the circuit output changes from one state to the other, the two transistors (T3 and T4) must both
change modes, and they will not change at exactly the same time, so that there is a very short interval
when both are conducting and the current through R3 will be larger during this interval than when one of
the transistors is cut-off. As a result, a surge of current is generated and a noise voltage “spike” can be
detected on the power supply line. The magnitude of this voltage spike is proportional to the resistance
of the supply line. Accordingly, TTL gates generate noise themselves, and extra precautions should be
taken to eliminate its adverse effect and use by-pass capacitors throughout the system built with TTL
gates to reduce the magnitude of the noise spikes.

3.13.2 The Buffer Gate with Open Collector Output

When the outputs of gates are connected together as shown in Fig. 3.21 (a), the load resistors in the
gates are connected in parallel. Therefore, the total load resistance is reduced and the current flowing
through the switches is increased. While only one switch is closed, all of this current will flow through
that switch. If this current is large, it could damage the switch. Hence the number of outputs that can
be connected together becomes limited. To provide the logic designer more flexibility in connecting
gate outputs, circuits are designed without an internal pull-up resistor. This type of circuit is called
open-collector gates for the bipolar transistors or open-drain gates for the unipolar transistors. In open
collector, the collector of the output transistor is brought directly to the gate output terminal. To use this
gate, an external load resistor must be connected between the output terminal and a positive voltage
supply. Generally, the outputs of open collector TTL gates are tried together with a single external
resistor and a wired-AND logic is performed. Figure 3.21.(c) shows the wired – logic graphic symbol to
denote wired AND connections on logic diagram.
 Digital Logic Family 91

Fig. 3.21 (a) The output of connected inverter (b) Equivalent logic diagram
(c) Wired – logic graphic symbol

While two inverter gates are connected together like the output of one inverter is used as the input of
another, the circuit can be worked as a buffer. Due to the two stage inversion, final output of buffer is
same as input. The buffer circuits are used as signal amplifiers. A weak signal source may be boosted by
means of two inverters connected in cascade. The logic level is unchanged, but the full current-sourcing
or current-sinking capability of buffer is available to drive a load. An open-collector type buffer circuit is
shown in Fig. 3.22. This circuit is similar with inverter. Only one difference is that it has one additional
common-emitter transistor, which can re-invert the output signal.

Fig. 3.22 Buffer with open collector output Fig. 3.23 Buffer with open collector output
when input is VCC
When input is high +VCC as depicted in Fig. 3.23, no current flow through the left steering diode of
T1. The current flows through resistance R1 and the base of transistor T2 so that transistor T2 operates in
saturation.
As T2 is saturated, T3 will also be saturated. Therefore, the voltage between the base and emitter of
the transistor T4 is very small. Then transistor T4 operate in cut-off. The output of transistor T4 is high or
+VCC. Thus, in buffer circuit, when the input voltage is high, output will be high. Similarly with a low
input voltage, the output will be low.
When input is low as shown in Fig. 3.24, current flow through switch base emitter junction of
transistor T1 and resistance R1. Consequently, no current will flow through the base of T2 and transistor
T2 operate in cut-off. Hence, no base current goes through T3 and T3 is also in cut-off condition. As T3
in cut-off, a current flow through resistance R4 and base emitter junction of transistor T4. The output of
transistor T4 is low. A buffer circuit with totem pole output transistor is shown in Fig. 3.25. The circuit
operation is same as open collector circuit. Table 3.7 shows the truth table of buffer.
 92 Digital Electronics: Principles and Applications

Fig. 3.24 Buffer with open collector output Fig. 3.25 Buffer circuit with totem pole output
when input is ground

Table 3.7 Truth table for buffer

Input Transistor Output
A T1 T2 T3 T4 O
Low Saturation Cut-off Cut-off Saturation Low
High Cut-off Saturation Saturation Cut-off High

3.13.3 TTL NAND and AND Gates with Open Collector Output
Figure 3.26 shows the two inputs inverter circuit. The steering diodes marked as T1 is actually a
transistor. The three p-n junction diodes cannot be replaced by a simple n-p-n transistor. Therefore, a
different transistor is required. This transistor should have two emitters with one base and one collector.
Figure 3.27 shows the multi emitter transistor based NAND gate.
When both inputs are grounded as shown in Fig. 3.28(a), transistor T2 will be operated in cut-off
mode. Then T3 is forced to operate in cut-off. The output of the transistor T3 is high. If one input terminal
is grounded other terminal is connected with +VCC, transistor T2 is in cut-off. Then transistor T3 is also
in cut-off and output will be high. But output is low when all inputs are high. Transistor T2 is turned on
and operate in saturation. Then T3 is forced to operate in saturation. The truth table of two inputs NAND
gate is given in Table 3.8.

Fig. 3.26 The two inputs Fig. 3.27 The multi-emitter transistor
inverter circuit based NAND gate
 Digital Logic Family 93

Table 3.8 Truth table for NAND gate

Input Transistor Output

A B T1 T2 T3 O
Low Low Saturation Cut-off Cut-off High
Low High Saturation Cut-off Cut-off High
High Low Saturation Cut-off Cut-off High
High High Cut-off Saturation Saturation Low

Fig. 3.28 (a) The multi-emitter transistor based NAND gate with both inputs grounded
(b) The multi-emitter transistor based NAND gate with one input high and other grounded

Fig. 3.28 (c) The multi-emitter transistor based NAND gate with one input high and other
grounded (d) The multi-emitter transistor based NAND gate with both inputs high

An AND gate can be developed by using

an NAND gate and an inverter to the output
as shown in Fig. 3.29. However, the NAND
function is actually the simplest, most natural
mode of operation for this TTL design. To
create an AND function using TTL circuitry,
we should add an inverter at the output of TTL
NAND gate and the complexity of the circuit
increases. Table 3.9 shows the truth table of two
inputs AND gate. Fig. 3.29 AND gate with open-collector output
 94 Digital Electronics: Principles and Applications

Table 3.9 Truth table for AND gate

Inputs Transistor Output

A B T1 T2 T3 T4 O
Low Low Saturation Cut-off Cut-off Saturation Low
Low High Saturation Cut-off Cut-off Saturation Low
High Low Saturation Cut-off Cut-off Saturation Low
High High Cut-off Saturation Saturation Cut-off High

3.13.4 TTL NOR and OR Gates with Open Collector Output

Figure 3.30 shows a two inputs TTL NOR gate. Here, transistors T1 and T2 are connected in same
manner. In this circuit both transistors T1 and T2 are used as two steering diode as shown in Fig. 3.31.
When input A is connected with +Vcc, current will flow through the base of transistor T3 with
right steering diode of T1 and resistance R1. Then T3 is turned on and operate in saturating condition.
Similarly, if input B is ground potential, current will flow through left steering diode of T2 and
resistance R2, no current will go through base of transistor T4. Therefore, transistor T4 is in cut off. In
this circuit Transistors T3 and T4 are connected in parallel through resistance R3 and R4. If any one of
the two transistors T3 and T4 is operated in saturation mode, current will flow through resistance R3
and R4. As input A is high and input B is low, T3 is turned on and T4 is cut-off, current passes through
resistance R3 and R4. A positive voltage is applied across the base of transistor T5 and a current a
current flow through base emitter junction of transistor T5. Hence, T5 is turned on and operate in
saturation. Consequently the output of transistor T5 is low.

Fig. 3.30 NOR gate with open collector Fig. 3.31 NOR gate with open collector

In the same way, if both inputs A and B are high, transistor T3 and T4 will be in saturation, and
transistor T5 is also in saturation. Then output will be low. But the output of transistor T5 is only high
when both inputs A and B are low. In this case, left steering diodes of T1 and T2 are conducting through
resistance R1 and R2 respectively. No current goes through base of transistor T3 and T4. So T3 and T4 are
in cut-off. Hence, no voltage is applied across base emitter junction of T5 and T5 is in cut-off. As a result,
output will be high. Therefore, we can say that this circuit behaves as NOR gate. Table 3.10 shows the
truth table of two inputs NOR gate.
 Digital Logic Family 95

Table 3.10 Truth table for NOR gate

Inputs Transistor Output

A B T1 T2 T3 T4 T5 O
Low Low Saturation Saturation Cut-off Cut-off Cut-off High
Low High Saturation Cut-off Cut-off Saturation Saturation Low
High Low Cut-off Saturation Saturation Cut-off Saturation Low
High High Cut-off Cut-off Saturation Saturation Saturation Low

An OR gate can be developed by adding an

inverter to the output of the NOR gate as shown
in Fig. 3.32. In this circuit, the output of 2 inputs
NOR gate is inverted by using transistor T6. The
truth table of two inputs OR gate is depicted in
Table 3.11. The totem-pole output stages are
also possible in both NOR and OR TTL logic
circuits. But the output-switching time will be
increased in proportion to the number of load
being driven.

Fig. 3.32 OR gate with open collector

Table 3.11 Truth table for OR gate
Input Transistor Output
A B T1 T2 T3 T4 T5 T6 O
Low Low Saturation Saturation Cut-off Cut-off Cut-off Saturation Low
Low High Saturation Cut-off Cut-off Saturation Saturation Cut-off High
High Low Cut-off Saturation Saturation Cut-off Saturation Cut-off High
High High Cut-off Cut-off Saturation Saturation Saturation Cut-off High

3.13.5 TTL Gate with Tristate Output

All TTL gates have two output states: logic ‘0’ and logic ‘1’, but the tri-state logic gates have three
output states as given below:
∑ Low level state or logic ‘0’ state
∑ High level state or logic ‘1’ state
∑ High impedance state (Z).
The graphic symbol of tri-state logic gates are shown
in Fig. 3.33. The tri-state gate consists of an extra input
terminal called enable or control input (C). When the
control input is at logic ‘0’, the gate performs its normal Fig. 3.33 Gate symbols of tri-state gates
 96 Digital Electronics: Principles and Applications

operation. If the control input is at logic ‘1’, the output of gate becomes tri-state or high impedance
state irrespective of inputs. In high impedance state, the gate is physically disconnected from its output
terminal when C is at logic ‘1’ and the output appears as an open circuit.
Figure 3.34 shows the tri-state two inputs NAND
gate. In this circuit, A and B are the inputs and C
is used as control input. When control input (C) is
HIGH or logic ‘1’, it works like any other NAND
gate. But when control input (C) is LOW or logic
‘0’, T1 conducts, and the diode connecting between
T1 emitter and T2 collector starts to conduct and
driving T3 into cut-off. As T2 is not conducting, T4
is also at cut-off. When both pull-up and pull-down
transistors are not conducting, the output (O) is in
Fig. 3.34 Tri-state NAND gate high-impedance state (Z). The circuit operation is
given in tabular form as depicted in Table 3.12.
The outputs of two or more tri-state gates can be
Table 3.12 Truth table for tri-state NAND gate
directly wired together as illustrated in Fig. 3.35. In
Control Data input Output (O) this circuit, C1 C2 …. CN are control inputs and D1
input C D2….. DN are data inputs and output is O. Assume
A B
0 0 0 1
that during operation at most one of them is not in
0 0 1 1 the high impedance state. Certainly those gates are
0 1 0 1 in the high-impedance state, they are effectively
0 1 1 0 disconnected from the common point and they
1 x x High impedance(Z) cannot affect the operation of any of the others in
any way. Consequently, the activated gate controls
the value of the common output line. Hence,
tri-state gates with their outputs wired together
can be used as a bus. In fact, tri-state gates were
developed and are used almost exclusively for this
application. The advantages of using tri-state gates
instead of open-collector gates are that more gates
outputs can be wired together and bigger busses
can be built. The tri-state gates are faster as they
Fig. 3.35 Bus realisation using tri-state gates have lower propagation delay.

3.14 CHARACTERISTICS OF TTL

Transistors are used to design TTL gates. During design of gates the limitations of transistors are
considered to get proper performance. The performance parameters of TTL logic family are logic
levels, source current, sink current, noise-margin, voltage transfer characteristics, fan-in, fan-out, power
dissipation, and propagation delay. All these parameters are explained below:
 Digital Logic Family 97

3.14.1 Logic Levels

Figure 3.36 shows the inverter circuit. The output of an Inverter
is logic ‘0’ when input voltage is low and logic ‘1’ if input
voltage is high. According to manufacturers specifications of
TTL ICs, low input voltage is varied between 0V and 0.8V.
While input voltage is in this range, output of the inverter will
be high, logical ‘1’. The low input voltage can be any value up
to 0.8 V. In the data sheet of TTL ICs, the worst-case low input
voltage is denoted as VILmax = 0.8 V. Figure 3.37 shows the
positive logic level of TTL transistor. VILmax is the maximum
allowable input voltage for a logic low level. Similarly, VIH is
also the minimum allowable input voltage for a logic high level.
If the input voltage exceeds VILmax, the output will be random
value. In the same way, the input voltage between 5.0V to 2.0V
is considered as high input voltage, VIH. When input voltage is Fig. 3.36 Inverter transistor circuit
varied in the above range, output will be low. The worst-case
high input voltage is denoted as VIHmin = 2V.
Between the two levels, VIL and VIH,
the transistor operates in the active region,
output level is not specially determined. In
this condition, the control on the transistor
parameters is lost. This is called forbidden
region. The difference between VIHmin and VILmax
is called the Transition Width (TW).
TW = VIHmin – VILmax = 2.0 – 0.8 = 1.2V
In the same way, the output voltage of TTL
ICs is not possible practically to achieve zero
output voltage, 0V for the low output voltage Fig. 3.37 Input and output voltage profile of TTL
and 5.0V for the high output voltage. As per
data sheet of TTL ICs, the low output voltage,
VOL = 0.4V. VOH represent the high state output voltage and lies between 2.4V and 5V. The worst-case
high output voltage is listed in data sheets as VOH = 2.4V. The worst case input and output voltages have
been listed below:
Maximum low input voltage VIL max 0.8 V
Minimum high input voltage VIH min 2.0 V
Maximum low output voltage VOL max 0.4 V
Minimum high output voltage VOH min 2.4 V
Logic Swing is defined as the difference between the two output voltage levels.
LS = VOH min – VOL max = 2.4 – 0.4 = 2.0V
 98 Digital Electronics: Principles and Applications

3.14.2 Voltage Transfer Characteristic

The voltage-transfer characteristic is one of the important
properties of TTL devices. It is actually the relation between
output voltage and input voltage under steady state conditions.
Figure 3.38 shows the voltage transfer characteristics of
TTL devices.
The BP1 means breakpoint one and the BP2 means
breakpoint two. At breakpoint BP1, input voltage is just at
the point of turning on the transistor. But output voltage is
still very close to the cut-off value and collector current is
very small. At breakpoint, BP2, input voltage is sufficient
so that the transistor is at the edge of saturation region
and collector current nearly at maximum value. Since any
further increase in the input voltage results in hardly any
change the output voltage. These breakpoints separate the
following three regions of operation, namely Cut-off, Ac-
Fig. 3.38 Voltage transfer characteris-
tics of TTL
tive and Saturation. The co-ordinates of BP1 and BP2 are
as follows BP1 Æ (VIL, VOH) and BP2 Æ (VIH, VOL)
where,VIL input low voltage, maximum value of VIN to guarantee that VOUT = VOH
VIH input high voltage, minimum value of VIN to guarantee that VOUT = VOL
The TTL inverter circuit as shown in Fig. 3.36 has R1 = 10K, R2 = 1K, VBE(ON) = 0.7 V, VBE(SAT) = 0.8,
and VCE(SAT) = 0.1 V. VOH is equivalent to VCE with the transistor at edge of cut-off region, and VOH is equal
to VCC. VOL is equivalent to VCE with transistor at the edge of saturation region. In this example VCE(SAT)
= 0.1V, and VOL = VCE(SAT).
VIL is the input voltage at which transistor will be just turn on. In this example, VBE(ON) = 0.7 V, and VIL
= VBE(ON). VIH is the input voltage, which is just sufficient to saturate the transistor. When the transistor
just at the Edge of Saturation (EOS), the collector current is given below:
VCC - VCE (SAT )
I C ( EOS ) =
R2
But also at the edge of the active region,
IC = IC(EOS)
IC(EOS) = hfeIB(EOS)
The input VIH is determined by the following steps as given below:
VIH - VBE (SAT )
I B ( EOS ) =
R1
R VCC - VCE (SAT )
VIH = VBE (SAT ) + 1 ◊
R2 h fe
10 5 - 0.1
VIH = 0.8 + ◊ = 1.5V
1 70
 Digital Logic Family 99

The co-ordinates of BP1 and BP2 are VIN = 0.7V, VOUT = 5.0V and VIN = 1.5V, VOUT = 0.1V respectively.

3.14.3 Noise Margins

Various kinds of noise are always present in electronic circuits, which distort the output voltage of the
gate. When output of one gate is used as input to another gate, it is very required to recognise ‘0’ and ‘1’
logic states, immunity to unwanted signal must be built into each gate in the form of noise margin. The
noise margin low level (NML) is the difference between VOHmin and VIHmin and noise margin high level
(NMH) is the difference between VILmax and VOLmax as given below:
NMH = VOH min – VIH min NML = VIL max – VOL max
= 2.4 – 2.0 = 0.4 V = 0.8 – 0.4 = 0.4 V

3.14.4 Fan-Out
Fan-out is the maximum number of TTL loads that can
be connected to the output of a TTL driver circuit. Figure
3.39 shows that only one TTL load gate is connected to the
output of a TTL transistor. Since the fan out of the driver
T0 is one, 1.
If there is no load at output of inverter, VOH of the inverter
is VCC = + 5V and the High noise margin NMH = 3.5V.
Figure 3.39 shows that only one load is present. VOH at
VOUT is due to voltage divider action of R2 and R1.
R1 Fig. 3.39 Fan-out of TTL circuit
VOH = VBE (SAT ) + (VCC - VBE (SAT ) )
R2 + R1
10
= 0.8 + (5.0 - 0.8) = 4.6V
1 + 10
In this way, when one load is connected to the TTL drive; VOH has been reduced from 5.0V to 4.6V.
Therefore, NMH is also reduced and its value is
NMH = VOH – VIH = 4.6 – 1.5 = 3.1V
Subsequently, we can determine the maximum number of TTL
load that can connect to the output of a TTL driver. To find out the
fan out, NMH is equal to 0.
NMH = 0
fiVOH = VIH
While T0 is off and N number of TTL load is connected with
the TTL driver as depicted in Fig. 3.40. There are N base resistors
R1 and all are connected in parallel to VBE(SAT). So we can write the
expression for N number of TTL load. Fig. 3.40 Fan-out of TTL circuit
 100 Digital Electronics: Principles and Applications

R1 N R Ê VCC - VCE (SAT ) ˆ

VBE (SAT ) + (VCC - VBE (SAT ) ) = VBE (SAT ) + 1 Á ˜
R2 + R1 N R2 Ë h fe

After solving the above equation, the fan out can be determined. After substituting all know parameters
in the above equation, we get N which may be integer or real number. As fractional loads are unfeasible,
fan-out always will be in round figure. To determine the maximum number of TTL load gates for the
fan-out, we always consider NMH = 0 and NMH is equal to NML.

3.14.5 Propagation Delay

When input to a gate changes suddenly, TTL gates response to the input signal and it takes finite time
to change the output state. This is due to change the switch from cut-off state to saturation state or vice
versa. This time delay is called the propagation delay. On the other hand, the switching times of the
bipolar junction transistor is also known as propagation delay. This is calculated by carrying out analysis
of the charge-control model of the BJT.
The analysis of the switching sequences is explained here. While the input voltage is a rectangular
pulse at time t0, it is considered that the input voltage changes suddenly from 0 to 5V. Initially, transistor
was in the cut-off and output voltage is VCC, 5V.
Delay time(td ) When the input voltage suddenly changes at time t0, there is no change at the output
until time t1. Here t1 is the time when output voltage start to decrease due to changes collector current. The
delay is generated as the voltage across the emitter and collector junctions do not change instantaneously
due to the junction capacitances at the depletion regions. The delay time (td) is determined from the dif-
ference between t1 and t0. It is (t1 – t0) as depicted in Fig. 3.41.

Fall Time (tf ) Due to the junction capacitance effects, the output voltage decreases as depicted in
Fig. 3.42. At time t2, the transistor is at the edge of saturation and output voltage of transistor is about
VCE(sat) = 0.1V. The fall time can be determined from (t2 – t1).

Fig. 3.41 N TTL load connected to a TTL driver Fig. 3.42 Rise time, fall time, delay time and
circuit saturation time
 Digital Logic Family 101

Saturation Time(ts ) It is clear from Fig. 3.42 that there is another step change in the input volt-
age from 5V to 0V at time t3. Though input voltage changes suddenly, output voltage does not change
till t4 due to the removal of the overdrive charge from the base, or the base and collector regions. The
saturation time is computed as (t4 – t3).

Rise Time (tr ) Due to junction capacitance effects output voltage rises similar to fall time, and the
transistor is now turning off. At time t5, the transistor is at the edge of cut-off. Consequently the output
is VCC, 5V. The rise time is the difference between t5 and t4.

The switching times namely delay, fall, saturation and rise time are required for digital circuit designer.
But propagation delay is most important for designers. In a inverter circuit, the turn-on delay time tPHL is
calculated as the output is changing from a high voltage level to a low voltage level.
tf
t PHL = td +
2

The turn-off delay time tPLH is computed as the output is changing from a low voltage level to a high
voltage level.
tr
t PLH = ts +
2

Thus, the average propagation delay time is defined as

t PHL + t PLH
tp =
2

3.14.6 Power Dissipation

In the data sheet of transistor, the specification of power dissipation is represented by average power
dissipation. The power dissipation rating of TTL gate is 10 mW per gate. In the active state, the output
is continuously changing, power dissipation increases and it must be taken into account where heat
dissipation and power supply ratings gets importance.
Consider that the power dissipation is constant at constant output. When the output is low, T1 conducts.
When the output is high, T1 does not conduct. This causes more current drain from the power supply per
gate, when the output is low than when it is high. The power dissipation per gate is given below
In the low state, 5V ¥ 3mA = 15 mW
In the high state, 5V ¥ 1mA = 5mW
If we assume that the gate is on and off for equal time periods, the total dissipation per gate will be
as follows:
Total dissipation: (15 + 5)/2 = 10mW.
 102 Digital Electronics: Principles and Applications

3.14.7 Sourcing and Sinking

Current
A TTL logic gate circuit has the ability to handle output
current in two directions, namely in and out. Technically, this
is called as sourcing and sinking current respectively. When
the gate output is high, current will flow through ground, load
and VCC. This is represented in simplified form in Fig. 3.43.
Fig. 3.43 The simplified gate circuit
source current In simplified form, the output of a gate circuit as being
a double-throw switch, capable of connecting the output
terminal either to VCC or ground, depending on its state. For a gate outputting a high logic level, a
double-throw switch is in the VCC position, providing a path for current through a grounded load.
A TTL logic gate is said to be sourcing current when it provides a path for current between the output
terminal and the positive side of the DC power supply (VCC). In other words, it is connecting the output
terminal to the power source (+V).
Consequently, when a gate circuit is outputting a
low logic level to a load, it is analogous to the double-
throw switch being set in the “ground” position.
Current will then be going the other way if the load
resistance connects to VCC.. In this condition, the gate
is said to be sinking current as depicted in Fig. 3.44.
A gate is said to be sinking current when it provides
a path for current between the output terminal and
ground. In other words, it is grounding (sinking) the
Fig. 3.44 n-channel depletion–mode MOSFET output terminal. Table 3.13 shows the characteristics
of a TTL.

Table 3.13 Characteristics of TTL

Parameter Value
3.15 METAL OXIDE SEMICONDUCTOR
VIH min 2.0V
FETS (MOSFET) CHARACTERISTICS
VIL max 0.8V
The Field–Effect Transistor (FET) is a three terminal voltage
VOH min 2.4
controlled semiconductor device. The three leads of the FET
VOH max 0.4V are drain (D), source (S) and gate (G). The gate is used as input.
IIH 0.02mA The operation of FET depends on the flow of only one type
IIL 0.4mA of carrier–either holes or electrons. The current flow in the
IOH 4mA FET occurs between the source and drain. The path connection
IOL 8mA between the source and drain is called the channel. The
tPHL 10ns
FETs are classified into two categories: Junction Field-Effect
Transistors (JFETs) and Metal Oxide Semiconductor Field-
tPLH 10ns
Effect Transistors (MOSFETs). The JFETs are used in linear
Pd 10mW circuits but the MOSFETs are employed in digital circuits.
 Digital Logic Family 103

There are two types of MOSFETs : n-channel and p-channel. MOSFETs are also classified by the
conducting state: depletion mode and enhancement mode. Actually the mode of operation depends on
bias voltage. When the MOSFET is conducting with zero bias voltage, it is said to be a depletion mode
device. If the device is not conducting with zero bias, the device will be known as enhancement–mode
MOSFET. The name enhancement MOSFET is derived from the fact that a voltage is required on the
gate to enhance or increase the current flow in the channel. Similarly, the depletion MOSFET derives
from the fact that a voltage on the gate is used to deplete or reduce the current flow in the channel.
The basic structure of an n-channel depletion–mode
MOSFET is shown in Fig. 3.45. This device consists of
two n-type regions diffused on a p-type substrate. The two
heavily doped n–type regions are called the source and drain.
The moderately doped n-type channel runs between source
and drain. This channel is insulated from the gate by a layer
of silicon oxide SiO2. Generally, the gate is constructed by a
thin layer of aluminium located in the centre of the channel.
Fig. 3.45 The simplified gate circuit When a positive voltage is applied to the drain and a negative
sinking current
voltage is applied to the gate, the channel will be appeared
as shown in Fig. 3.46. The negative
potential will attract holes from the p-
type substrate and repel or neutralise the
electrons in the moderately doped n-type
channel. As the channel being depleted of
carriers, subsequently the drain current
will decrease.
As the gate of the MOSFET is electri-
cally isolated from the channel, the device
Fig. 3.46 Biasing of n-channel depletion–mode MOSFET can be able to operate with a positive gate
to source voltage. If VGS increases, the
number of free electrons flowing through the
channel increases. Consequently, the current
flow increases with increasing VGS. The drain
curves of a typical n-channel depletion mode
MOSFET are depicted in Fig. 3.47. These
curves are formed by varying VGS to various
positive as well as negative values and observ-
ing the relationship between VDS and ID for each
value of VGS.
The construction of an n-channel
Fig. 3.47 Drain curves of n-channel depletion–
mode MOSFET enhancement type MOSFET is shown in Fig.
3.48(a). The main difference between depletion
and enhancement type MOSFET is that there is no channel in enhancement type MOSFET. The biasing
arrangement of this MOSFET is given in Fig. 3.48(b). When VGS is increased, the conductivity of the
 104 Digital Electronics: Principles and Applications

channel is enhanced and electrons are pulled into the substrate just below the layer of insulation under
the gate. Ultimately, a channel is formed between the source and drain as the minority electron carriers
are drawn from the substrate to the positive gate voltage. The amount of gate voltage required to develop
a channel is called the threshold voltage (VTH). When the bias voltage is below the threshold voltage,
current flow stops. A negative bias voltage can generate cut-off in an enhancement–mode MOSFET. The
schematic symbols of all MOS transistors are shown in Fig. 3.49.

Fig. 3.48 (a) n-channel enhancement –mode MOSFET

(b) Biasing of n-channel enhancement –mode MOSFET

Fig. 3.49 Symbols of MOS transistors (a) n-channel depletion type (b) p-channel depletion type (c)
n-channel enhancement type (d) p-channel enhancement type

Metal-Oxide-Semiconductors (MOS) are extensively used in digital electronics circuits due to the
following advantages:
(i) MOS requires less space than BJT for fabrication a silicon chip
(ii) High input resistance
(iii) Very low power consumption
(iv) MOS logic family is compatible with BJT due to matching voltage levels.
(v) Very economical
(vi) Few steps are required for MOS fabrication process
(vii) MOS circuit’s speed is very high due to reduction of internal dimension of devices
(viii) Dynamic circuit techniques are used in MOS technology. Therefore less number of transistors is
required to implement a given circuit.
(ix) Presently local oxidation technique is used to increase circuit density and to improve circuit
performance.
The MOS logic has three categories such as
 Digital Logic Family 105

P Channel MOSFETs , PMOS

N Channel MOSFETs, NMOS
Complementary MOSFETs, CMOS
P-channel MOSFET becomes obsolete. Now-a-days, N channel MOSFETs are very popular due to
high speed. An n-channel MOS consists of a lightly doped n-type silicon substrate . The source and
drain are formed by diffusion with p-type impurities. The
region between two p-type impurities namely source and
drain acts as a channel. This device operates in enhanced
and depletion mode. The mode of operation depends on
the state of the channel region. An n-channel enhancement
MOSFET requires a positive gate voltage for conduction.
Figure 3.50 shows the symbols of MOS devices.
If VGS and VGD are less than threshold voltage, VTH, the
device operates in cut-off and no current flows from drain Fig. 3.50 (a) p-channel MOS and
to source as depicted in Fig. 3.51(a). When VGS is greater (b) n-channel MOS
than threshold voltage, VTH, the device is ON and operates in saturation. Therefore, current flows from
Drain to Source as shown in Fig. 3.51(b).

Fig. 3.51 (a) MOS in cut-off (b) MOS in saturation

3.15.1 MOS Inverter
The MOS inverter circuit can be classified into static and dynamic circuits. This classification depends on
the requirement of periodic clock pulse. If there is no requirement of periodic clock pulse for operating
a combinational logic circuit, this circuit is called static circuit. On the other hand, dynamic circuits
require periodic clock pulse for operation in combinational logic circuits.
Figure 3.52 shows a MOSFET inverter circuit with a passive resistive load RD. If the input voltage is
HIGH, MOSFET will be ON and output voltage will be LOW. Similarly if input is reversed, output will
be HIGH. In contrast to TTL technology, linear resistors are used as pull-up element in an inverter. In
MOSFET technology, MOSFET fabrication is easier than a resistor and it requires twenty times less space.
Therefore, another MOSFET can be used in place of load resistance as shown in Fig. 3.53. As gate of the
MOSFET, T2 is connected with the drain, the MOSFET, T2 is always conducting and it acts as a resistance.
During design process, the resistance of MOSFET, T2 is ten times greater than MOSFET, T1. Consequently,
 106 Digital Electronics: Principles and Applications

MOSFET, T2 behaves as a resistance and MOSFET, T1 acts as a switch. To provide greater current, the
pull-down devices are first turned off and a capacitive load must be charged as shown in Fig. 3.52(b).

Fig. 3.52 MOS Inverter Fig. 3.53 MOS Inverter

3.15.2 NMOS NAND Gate

Figure 3.54 shows the two inputs MOS NAND gate. If one input or both
inputs are LOW, the corresponding MOS is OFF. Then voltage across T3
is zero and output is Vdd. If both inputs are high, T1 and T2 are ON and
output will be low. Table 3.14 shows the truth table of a NAND gate.
Table 3.14 Truth table for two inputs MOS NAND gate

Inputs Transistors Output

A B T1 T2 O
Low Low Cut-off Cut-off High
Fig. 3.54 Two inputs
NAND gate Low High Cut-off Saturation High
High Low Saturation Cut-off High
High High Saturation Saturation Low

3.15.3 NMOS NOR Gate

The two inputs NOR gate is depicted in Fig. 3.55. If any one input is HIGH or both inputs are HIGH, the
corresponding transistors are ON and output is LOW. When both transistors T1 and T2 are OFF, output
is low. The truth table of NOR gate is shown in Table 3.15.

Table 3.15 Truth table for two inputs MOS NOR gate
Inputs Transistors Output
A B T1 T2 O
Low Low Cut-off Cut-off High
Low High Cut-off Saturation Low
High Low Saturation Cut-off Low
High High Saturation Saturation Low
Fig. 3.55 Two Inputs NOR gate
 Digital Logic Family 107

3.16 MOS CHARACTERISTICS

The MOS logic families have slow operating speed; have a better noise margin, a greater supply voltage
range, and a higher fan-out compared to the TTL logic families. The MOS devices require less space in
ICs and consume small power with respect to TTL. The some basic characteristics are explained below:
Fan Out Due to very high input impedance, MOS devices have large fan out. But increasing with no of MOS
gates, the capacitance will be increased at the output. Therefore, the speed of MOS is reduced. NMOS devices
are directly interfaceable with TTL devices as voltage and current parameters of MOS are similar with TTL.
Operating Speed The MOS devices have relatively high output resistance and the capacitive loading
is also present when the inputs of the logic circuits drive the devices. MOS logic inputs have very high input
resistance, subsequently, this logic inputs have a reasonably high input capacitance called MOS capacitor.
The MOS capacitor varies in between 2 to 5 pico-farads. Actually, capacitance is charged and discharged
through resistance. The switching speed of MOS devices depends on the rate of charge and discharge
of capacitance. Therefore, switching time increases due to large output resistance and large capacitance.
Power Dissipation The power dissipation of MOS logic circuits is very small. So this logic cir-
cuit can be very useful for Large-Scale Integration (LSI) and Very Large Scale Integration (VLSI) ICs.
During the design of ICs, the power consumption should be minimum. As 10,000 or more gates can be
easily placed in a LSI IC, average power consumption per gate of LSI IC should be less than 100mW.
Propagation Delay A large capacitance is present at input and output of MOS devices. The propagation
delay is large due to capacitance. For a N-MOS NAND gate, the propagation delay time is approximately 50 ns.
Noise Margin Typically, N-MOS noise margins are around 1.5V when operated from Vdd = 5 V
and will be proportionally higher for larger values of Vdd.

3.17 CMOS GATES

CMOS is most widely used digital circuit technology in comparison to other logic families. This logic family
has the following advantages: lowest power dissipation and highest packing density. Virtually, all-modern
microprocessors are manufactured in CMOS and older versions are now reprocessed in CMOS technology.
Complementary MOS (CMOS) Inverter analysis makes use of both NMOS and PMOS transistors in
the same logic gate. All static parameters of CMOS inverters are superior to those of NMOS inverters.
Price paid for these substantial improvements and increased process complexity to provide isolated
transistors of both polarity types. The logic level operation of NMOS and PMOS are given below:
logic 1(Positive VGS) turns on an NMOS
turns off a PMOS
logic 0 turns off an NMOS
turns on a PMOS
Thus, for the output high and low states both devices are never ON simultaneously. NMOS acts as the
output transistor and the PMOS acts as the load transistor. The output pull-up and pull-down paths never
conflict during operation of the CMOS inverter. By connecting, the complementary transistors as shown
in Fig. 3.56, can work as an inverter. VGS is needed to enable the Drain-Source current channel.
 108 Digital Electronics: Principles and Applications

NMOS enhancement-mode transistor is the lower T1 and PMOS enhancement-mode transistor is the
upper T2. Gates of both NMOS and PMOS are connected together. Drains are also connected together.
One transistor can be considered as load for the other. Here, T1 will be act as the load for T2 in the PMOS
inverter. Similarly, T2 can be considered as the load on the NMOS inverting transistor. The operation of
T1 and T2 is complementing each other. The output of a CMOS inverter does reduce all the way to 0V.
Since output can range from 0 volts to VDD, output is said to rail-to-rail.
3.17.1 CMOS Inverter
Two complementary MOSFETs, namely, p-channel MOSFET (PMOS) and n-channel MOSFET (NMOS)
are connected in such a way
that the circuit behaves as in-
verter. Figure 3.56 shows the
complementary CMOS in-
verter. The drains are joined
together. Vdd is connected
with source of PMOS and
source of NMOS is also
connected with ground.
Figure 3.57(a) shows the
operation of CMOS invert-
er when input is connected
with low voltage (logic 0).
Fig. 3.56 Complementary Fig. 3.57 (a) Complementary CMOS When input voltage is low,
MOS inverter inverter circuit with input ground the NMOS will be cut-off
and PMOS will be oper-
Table 3.16 The truth table of CMOS
inverter
ating in saturation mode.
Then output will be Vdd. Similarly, when input voltage is
Input Transistor Output high, PMOS will be in cut-off and NMOS operate in satura-
A T1 T2 O tion. Therefore, the output voltage will be almost zero volt. In
Low Cut-off Saturation High this way, this circuit be-
haves as inverter. Table
High Saturation Cut-off low
3.16 shows the truth ta-
ble of CMOS inverter.
The transistor T2 is a P-channel MOSFET. When the channel
is more positive than the gate, the channel is enhanced and
current is allowed between source and drain. Therefore, the
upper transistor T2 is turned on. The transistor T1, having zero
voltage between gate and source, is in its cut-off mode. Thus,
the actions of these two transistors are such that the output
terminal of the gate circuit has a solid connection to Vdd and a
very high resistance connection to ground. This makes the
output high or logic 1 for the low or logic 0 state of the input. Fig. 3.57 (b) Complementary
CMOS inverter
Similarly, when the input is +VCC, the operation of the circuit circuit when input
is depicted in Fig. 3.57(b). The transistor T1 is saturated as it has connected to VCC
 Digital Logic Family 109

sufficient voltage of the correct polarity applied between gate and substrate
to turn it on due to positive on gate, and negative on the channel. The
transistor T2, having zero voltage applied between its gate and substrate,
is in its cut-off mode. Thus, the output of this gate circuit is now “low”
or logical ‘0’. Clearly, this circuit exhibits the behaviour of an inverter, or
NOT gate. The multiple-input CMOS gates such as AND, NAND, OR, and
NOR are also explained in the next section.
3.17.2 CMOS NAND and AND GATE
Figure 3.58 shows the two inputs CMOS NAND gate. The two p-channel
MOSFETs namely T1 and T2 are connected in parallel. Two n-channel
MOSFETs T3 and T4 are connected in series. It can be noticed that transistors
T1 and T3 are in series connected complementary pair and form an inverter
circuit. These transistors are controlled by input signal A. When the input Fig. 3.58 CMOS NAND
is high, the transistor T1 is cut-off and transistor T3 is ON. On the other gate
hand, when input is low, T1 is ON and T3 is OFF. Similarly, transistors T2
and T4 are controlled by the same input signal (input B), and they will also exhibit the same ON/OFF
behaviour for the same input logic levels. The following sequence of switching shows the behaviour of
this NAND gate for all four possibilities of input logic levels (00, 01, 10, and 11) in Fig. 3.59 (a), (b),
(c) and (d) respectively. Table 3.17 shows the truth table for two inputs CMOS NAND gate.

Fig. 3.59 (a) CMOS NAND gate with both inputs grounded (b) CMOS NAND gate when one input
grounded and other connected with Vdd (c) CMOS NAND gate when one input grounded and
other connected with Vdd (d ) CMOS NAND gate when both inputs connected with Vdd
 110 Digital Electronics: Principles and Applications

The CMOS NAND gate circuit can be used as an AND gate

by inverting the output of NAND gate. For this, one inverter
circuit is connected after NAND gate. Figure 3.59 shows the
two input CMOS AND gate and the truth table of CMOS AND
gate is illustrated in Table 3.18.

3.17.3 CMOS NOR and OR GATE

Figure 3.61 shows two inputs CMOS NOR gate. Transistors
T1 and T3 work as a complementary pair, as do transistors
T2 and T4. Each pair is controlled by a single input signal.
When input A or input B are high (1), at least one of the
Fig. 3.60 CMOS AND gate transistors (T3 or T4) will be saturated, thus the output will
be low (0). Only in the event of both inputs being low
(0), both lower transistors will be in cut-off mode and both upper
transistors be saturated, the conditions necessary for the output to go
high (1). This behaviour, of course, defines the NOR logic function.
Table 3.19 shows the truth table of two inputs CMOS NOR gate.

Table 3.17 Truth table for two inputs CMOS NAND gate
Inputs Transistors Output
A B T1 T2 T3 T4 O
Low Low Saturation Saturation Cut-off Cut-off High
Low High Saturation Cut-off Cut-off Saturation High
Fig. 3.61 Two inputs CMOS High Low Cut-off Saturation Saturation Cut-off High
NOR gate High High Cut-off Cut-off Saturation Saturation Low

Table 3.18 Truth table for two input CMOS AND gate
Inputs Transistors Output
A B T1 T2 T3 T4 T5 T6 O
Low Low Saturation Saturation Cut-off Cut-off Cut-off Saturation Low
Low High Saturation Cut-off Cut-off Saturation Cut-off Saturation Low
High Low Cut-off Saturation Saturation Cut-off Cut-off Saturation Low
High High Cut-off Cut-off Saturation Saturation Saturation Cut-off High

Table 3.19 Truth table for two inputs CMOS NOR gate
Inputs Transistors Output
A B T1 T2 T3 T4 O
Low Low Cut-off Cut-off Cut-off Cut-off High
Low High Cut-off Saturation Cut-off Saturation Low
High Low Saturation Cut-off Saturation Cut-off Low
High High Saturation Saturation Saturation Saturation Low

The OR function can be built up from the basic NOR gate and an inverter on the output of NOR
gate. Figure 3.62 shows the two inputs CMOS OR gate. The truth table of two inputs CMOS OR gate
is depicted in Table 3.20.
 Digital Logic Family 111

Fig. 3.62 Two inputs CMOS OR gate

Table 3.20 Truth table for two inputs CMOS OR gate

Inputs Transistors Output

A B T1 T2 T3 T4 T5 T6 O
Low Low Cut-off Cut-off Cut-off Cut-off Cut-off Saturation Low
Low High Cut-off Saturation Cut-off Saturation Saturation Cut-off High
High Low Saturation Cut-off Saturation Cut-off Saturation Cut-off High
High High Saturation Saturation Saturation Saturation Saturation Cut-off High

3.18 CMOS CHARACTERISTICS

The basic performance parameters are same for TTL and CMOS. So, the CMOS parameters are logic
levels, source current and sink current, noise-margin, fan-in,
Table 3.21 Characteristics of CMOS
fan-out, power dissipation, and propagation delay. Table 3.21
shows the CMOS characteristics. The characteristics of CMOS Parameter Value
are different from TTL as values of parameters are different. VIH min 3.5V
All these parameters are explained in this section. V 1.5V IL max

VOH min 4.9V

3.18.1 Logic Levels VOH max 0.1V
According to manufacturers specifications of CMOS ICs, low IIH 1µA
input voltage is varied between 0V and 1.5V. In the data sheet IIL –1µA
of CMOS ICs, the worst-case low input voltage is denoted IOH –100µA
as VIL max =1.5V. VIL max is the maximum allowable input IOL 360µA
voltage for low logic level. In the same way, VIH min is also
tPHL 60ns
the minimum allowable input voltage for high logic level. The
worst-case high input voltage is denoted as VIH min = 3.5V. The tPLH 45ns
high input voltage of CMOS varies in the range 3.5V to 5V. Pd 10nW
 112 Digital Electronics: Principles and Applications

When input voltage varies in between the two levels VIL max and VIH min, the CMOS transistor operates
in the active region and output level is not specially determined. In this case, there is no control on the
transistor parameters. The difference between VIH min and VIL max is called the Transition Width (TW).
TW = VIH min – VIL max = 3.5 – 1.5 = 2V
On the other hand, the low output voltage of CMOS, VOL varies in 0 to 0.1V, and the maximum low
state output voltage is VOL max= 0.1 V. VOH represent the high state output voltage and lies between 4.9
V and 5 V. The worst-case high output voltage, VOH min =4.9 V according to data sheet of CMOS. Figure
3.62 shows the input and output voltage profile of CMOS. The worst case input and output voltages
have been listed below:
Maximum low input voltage VILmax 1.5 V
Minimum high input voltage VIH min 3.5 V
Maximum low output voltage VOL max 0.1 V
Minimum high output voltage VOH min 4.9 V
The Logic Swing (LS) of CMOS can be determined from the difference between the two output
voltage levels as given below
LS = VOH min – VOL max = 4.9 – 0.1 = 4.8V

3.18.2 Noise Margins

The low level noise margin (NML) is the difference between VOH max and VIH min and high level noise
margin (NMH) is the difference between VIL min and VOL min as given below:
NMH = VOH min – VH min = 4.9 – 3.5 = 1.4 V NML = VIL max – VOL max = 1.5 – 0.1 = 1.4 V
In general, the CMOS devices have greater noise margins than TTL. The noise margin would be
more if the CMOS devices were operated at a supply voltage greater than 5V.

3.18.3 Fan-Out and Fan In

Fan-out is the maximum number of CMOS logic gates that can be driven by a single CMOS logic gate.
The fan-out of CMOS varies in the range of 20 to 50 depending upon the operating condition. Fan-in
means the maximum number of inputs for a CMOS gate and this is limited by technological factors. The
fan-in of CMOS lies between 2 to 8.

3.18.4 Propagation Delay

The propagation delay of CMOS ICs generally varies in between about 20ns to 100ns. As compared to
TTL ICs, CMOS ICs have more propagation delay. When CMOS ICs are connected in cascade form,
the propagation delay will be increased. If the CMOS operates at high supply voltage and low load
capacitance, switching speed of CMOS increases significantly.

3.18.5 Power Dissipation

In the data sheet of CMOS transistor, the specification of power dissipation is represented by aver-
age power dissipation. The power dissipation of a CMOS gate is about 10nW. When the frequency
 Digital Logic Family 113

of input signal increases, CMOS gate dissipates more power. However, CMOS gates draw transient
current during every change of output state, from low to high and high to low. Therefore, CMOS ICs
have greater power dissipation at greater fre-
quencies. At 1 MHZ, the power dissipation is
approximately 1mW.

3.18.6 Sourcing and Sinking

Current
Just like TTL ICs, CMOS ICs also have source
and sink current. The source and sink current of
CMOS are very small compared to TTL. Figure
3.63 illustrates a CMOS driver interface with a
CMOS inverter load. While the output of CMOS
driver is low, the driver sinks a current about
1µA. The CMOS driver can source a current Fig. 3.63 Input and output voltage profile of
about 1µA when the output of CMOS driver is CMOS
high as depicted in Fig. 3.65. IILmax is the current,
which is flowing out of the load when the driver output is low and it has a negative sign. Similarly, if the
driver output is high, IIH max is the current, which is flowing into the load and it has positive sign.

Fig. 3.64 CMOS driver sinks a current Fig. 3.65 CMOS driver source a current
from a CMOS load to a CMOS load

3.19 INTERFACING TTL AND CMOS LOGIC FAMILY

To design a complex digital electronics circuit, designer use devices of two different logic families or
same logic family. Therefore, there are two types of devices namely driving and loading devices exist-
ing in any circuit. The driving device is connected to the loading device. For proper interface, the output
characteristic of the driving device should match with the input characteristic of loading device. If they
are not properly matched, an interfacing problem will arise between driving and loading devices. So out-
put will not be the desired output. To get desired output, some external circuit is connected in between
two devices. TTL and CMOS logic families are most commonly used in digital circuits. Therefore,
interfacing on TTL to TTL, CMOS to CMOS, TTL to CMOS and CMOS to TTL are given below.
 114 Digital Electronics: Principles and Applications

3.19.1 TTL to TTL

The output and input voltage profiles of TTL devices are
shown in Fig. 3.66. The output and input voltage levels
of TTL are VOH min= 2.4V, VOL max = 0.4V, VIH min = 2V, and
VIL max = 0.8V. The VOH min is greater than VIL min and VOLmax
is less than VIL max. Therefore, output voltage levels VOH
V
min, OL max
fall within the acceptable input voltage levels
VIH min and VIL max. Consequently, there is no interfacing
problem between two TTL devices and a TTL driver
can be connected directly with a TTL load.

Fig. 3.66 (a) Output voltage profile of TTL

(b) Input voltage profile of TTL

3.19.2 CMOS to CMOS

Figure 3.67 shows the output and input voltage
profiles of CMOS devices. The output and input
voltage levels of CMOS are VOH min = 4.9V, VOL max =
0.1V, VIH min = 3.5V, and VIL max = 1.5V. In CMOS the
VOH min is greater than VIL min and VOL max is less than
VIL max. So, CMOS output voltage levels (VOH min, VOL
max
) fall within the acceptable input voltage levels
(VIH min ,VIL max) of CMOS. Accordingly, there will not
be any interfacing problem between two CMOS ICs.
Therefore, a CMOS driver can be connected directly Fig. 3.67 (a) Output voltage profile of CMOS
with a CMOS load. (b) Input voltage profile of CMOS

3.19.3 TTL to CMOS

The output voltage profiles of TTL and input voltage profiles of CMOS devices are depicted in
Fig. 3.68. The output and input voltage levels of
TTL and CMOS are VOH min = 2.4V, VOL max = 0.4V,
VIH min = 3.5V, and VIL max = 1.5V repectively. If the TTL
output is low, the maximum output voltage of TTL,
VOL max is 0.4V. As VOL max is less than VIL max, it is
suitable for a CMOS load. When the TTL output is
high, the maximum output voltage of TTL, VOH min is
2.4V, which is not acceptable for a CMOS load as
VOH min is less than VIH min. Therefore, high state output
voltage level of a TTL is not sufficient/compatible to
drive a CMOS load. Consequently, there is an interfacing
problem between TTL and CMOS ICs , when two types Fig. 3.68 (a) Output voltage profile of TTL
of ICs are used in same system. (b) Input voltage profile of CMOS
 Digital Logic Family 115

For example a TTL NAND gate output is fetched to a CMOS Inverter as shown in Fig. 3.69. Both
gates are powered by the 5V power supply. When TTL gate
output is low (0 to 0.4V), it will be accurately recognised by the
CMOS gate as a low (0 to 1.5V). If the TTL gate output is high
(2.4 to 5V), it will not be accurately recognised by the CMOS
gate as a high (3.5 to 5V). Due to different voltage levels, there is
some mismatch. Therefore, the output of a TTL falls with in the
unacceptable range of the CMOS input and it will be accepted as
low. The problem can be solved by connecting a pull-up resistance
at output of TTL as shown in Fig. 3.70 and Fig. 3.71. Fig. 3.69 Interfacing a TTL driver
Sometimes, it is required to interface a TTL IC with a CMOS and a CMOS load
IC when CMOS IC is powered by a greater voltage as depicted

Fig. 3.70 Interfacing a TTL driver and Fig. 3.71 (a) Output voltage profile of TTL with
a CMOS load with pull-up pull-up resistance (b) Input voltage
resistance profile of CMOS

in Fig. 3.72. In this case, the CMOS can able to recognise the both low and high output as low because
the high state output voltage level (2.4V to 5V) is less than the high state input voltage of CMOS (7V to
10V). So, a pull-up resistance is connected in between output of TTL and Vdd as shown in Fig. 3.73 to
increase the TTL high state output voltage to full power supply voltage.

Fig. 3.72 Interfacing a TTL driver and Fig. 3.73 Interfacing a TTL driver and
a CMOS load at different a CMOS load with pull-up resistance
power supply at different power supply
 116 Digital Electronics: Principles and Applications

3.19.4 CMOS to TTL

During interfacing between CMOS andTTLdevices, we take into account the limiting values of output voltage
and current of CMOS (VOH min, VOL max, IOH max, IOL min) and the input voltage and current of TTL (VOH min, VOL max,
IOH max, IOL min). The voltage and current profiles of CMOS are VOH min = 4.9V, VOL max = 0.1V, IOH max =
–360µA, and IOL min = 360µA. Similarly, limiting values of voltage and current of TTL are VOH min= 2V,
VOL max = 0.8V, IOH max= 40µA, and IOL min = –1.6mA. Figure 3.74 shows the output and input voltage pro-
file of CMOS and TTL respectively. As output voltage levels of CMOS driver (VOH min, VOL max ) fall within the
acceptable range of TTL input voltage levels (VIH min and VIL max), there is no interfacing problem connecting a
CMOS output to a TTL load input. But the only significant issue is that the current loading of TTL inputs
is present and the CMOS output must sink current for each of the TTL inputs in the low state.
CMOS gate gives better performance, when it is operated at voltage around 9 to 12V. Therefore, to
get best performance CMOS operates in at 10V but TTL operates at 5V. When CMOS gate is connected
with 10V power supply, the interfacing problem will arise. The high output state of CMOS gate is
greater than 5V, which exceed the acceptable high input voltage level of TTL. This problem can be
solved by adding an open collector inverter using NPN transistor at the output of CMOS as depicted in
Fig. 3.75. The Rpull-up resistance is optional, as TTL inputs presume a high state. But one important fact
that inverted output of CMOS is used as input of TTL. When the CMOS output is low, the TTL gets a
high input signal. While the CMOS output is high, the TTL gets a low input signal.

3.20 ADVANTAGES AND DISADVANTAGES OF CMOS OVER TTL

Since it appears that any gate possible to construct using TTL technology can be duplicated in CMOS,
why do these two “families” of logic design still coexist? The answer is that both TTL and CMOS have
their own unique advantages.
A CMOS consist of a NMOS and a PMOS transistor. The complementary P and N channel MOSFET
pairs of a CMOS are never conduct simultaneously. So, the CMOS gate draws very little current from
the Vdd power supply. Therefore, power dissipation of CMOS is very small in the range of nW. On the
other hand, TTL always draw some current from supply, as the bias current is required to operate the
bipolar transistors. The range of power dissipation of TTL is mW.

Fig. 3.75 Interfacing a CMOS

Fig. 3.74 (a) Output voltage profile of driver and a TTL load at different
CMOS (b) Input voltage profile of TTL power supply
 Digital Logic Family 117

The power dissipation of a TTL device remains somewhat constant at different operating conditions.
However, the power dissipation of a CMOS device depends on the operating frequency. If the frequency
of input signal increases, the CMOS devices dissipate more power. When a CMOS operates in a static
condition, it dissipates approximately zero power.
As a CMOS gate also draws much less current from a driving gate output than a TTL gate because
MOSFETs are voltage-controlled, not current-controlled, devices; this means that one gate can drive
many more CMOS inputs than TTL inputs. The measure of how many gate inputs a single gate output
can drive is called fan-out.
Another advantage of CMOS is that CMOS ICs can operate in wide range of power supply voltages
than TTL gate.
The disadvantage of CMOS is slow speed, as compared to TTL. As the input capacitances of a
CMOS gate are greater than the input capacitances of TTL, the RC time constant developed by CMOS
logic circuit resistances will be more. As a result, CMOS ICs are operated in slow speed.

SUMMARY
In this chapter, the classification of digital logic family is explained. The operation of different logic families, namely
DTL, TTL, ECL, and CMOS are discussed with circuit diagrams. The characteristics of digital logic family are
incorporated for better understanding of TTL, MOS and CMOS logic gates. TTL inverter, buffer, NAND, AND,
NOR and OR gates are explained with the help of truth table and circuit diagrams. An inverter is one that output is
the opposite of input. If input is ‘low’ output is ‘high’. When two inverter gates connected in ‘series’, input is inverted
two times, so that buffer output is same as input. Buffer gates are commonly used to amplify weak signal before driving
a load. Taking a TTL inverter circuit and adding another input we could build a TTL NAND gate. An AND gate
may be developed by adding an inverter gate to the output of the NAND gate. An OR gate can also be formed after
addition of an inverter at the output of the NOR gate. The MOS inverter, NAND and NOR gate are explained in this
chapter. CMOS logic gates are made using complementary transistors namely NMOS and PMOS. CMOS inverter,
NAND, AND, NOR and OR gates are also discussed in this chapter. The characteristics of TTL, MOS and CMOS
are explained briefly to understand the applications of TTL, MOS, and CMOS logic families in digital systems. The
interfacing of TTL and CMOS is also enlightened in this chapter.

MULTIPLE CHOICE QUESTIONS

1. Which of the following range is used as low level (logic 0) input voltage in TTL circuit?
(a) 0.4V – 1.2V (b) 0V – 0.8V (c) 0.8V – 2.4V (d) 1V – 2.4V
2. Which of the following range is used as high level (logic 1) input voltage in TTL circuit?
(a) 2V – 5V (b) 0.8V – 5V (c) 0.8V – 2.4V (d) 1V – 5V
3. Which of the following range is used as low level (logic 0) input voltage in CMOS circuit?
(a) 0V – 1.5V (b) 0.8V – 2V (c) 0.8V – 2.4V (d) 1V – 2.4V
4. Which of the following logic family is fastest of all?
(a) TTL (b) RTL (c) DCTL (d) ECL
5. Which of the following technology is used for microprocessors?
(a) CMOS (b) NMOS (c) PMOS (d) None of these
118 Digital Electronics: Principles and Applications

6. Which of the following logic family is most widely used?

(a) TTL (b) DTL (c) ECL (d) None of these
7. Which of the following logic family consumed least power?
(a) TTL (b) RTL (c) DCTL (d) ECL
8. Which of the following MOS logic family is used in LSI technology?
(a) NMOS (b) PMOS (c) CMOS (d) None of these
9. The propagation delay of TTL is
(a) 10ns (b) 120ns (c) 200ns (d) None of these
10. What is the fan-out of TTL devices?
(a) 2 (b) 4 (c) 6 (d) 10
11. Which of the following devices have 200 gates
(a) SSI (b) MSI (c) LSI (d) VLSI
12. A gate can drive the number of similar gates that is known as
(a) Fan in (b) Fan out (c) Shinking current (d) Propagation delay
13. CMOS stands for
(a) Charged Metal Oxide Switch
(b) Complementary Metal Oxide Semiconductor
(c) Complementary Metal Oxide Switch
(d) None of these
14. What will be the power consumption of CMOS circuits if frequency increases?
(a) Increases (b) Decreases (c) Same (d) None of these
15. A tri-state logic gate has three output states. They are
(a) High, Low, Open circuit (high impedance) (c) High, Low, Saturated
(b) High, Low, Short circuit (d) None of these
16. Which of the following logic family consumes the least power in static state?
(a) TTL (b) ECL (c) CMOS (d) I2L
17. What are the three basic modes of operation of a transistor?
(a) Saturated, cut-off, active (c) open, closed, off
(b) High, low, open-circuit (d) None of these
18. Noise margin of TTL is
(a) 0.4V (b) 2V (c) 3V (d) 1.5V
19. Noise margin of CMOS is
(a) 1.4V (b) 2.4V (c) 3.4V (d) 4.4V
20. The power dissipation of a CMOS is approximately
(a) 10nW (b) 20nW (c) 30nw (d) None of these
21. What are the three basic parameters for selecting digital logic family?
(a) Speed, cost, power consumption (b) Speed, size, power consumption
(c) Speed, size, propagation delay (d) None of these
 Digital Logic Family 119

REVIEW QUESTIONS
3.1 What are the types of digital logic family? Explain briefly any one logic family with circuit dia-
gram.
3.2 Draw the circuit diagram of DCTL to perform logical AND and explain briefly the operation of
circuit.
3.3 Determine fan out of transistor T0 as shown in Fig. 3.76. Consider VCC = 5V, R = 12K, IB = 0.15mA
for saturation.

Fig. 3.76
3.4. Determine IB1, IB2, IC1 and IC2 for the transistor T1 and T2 as depicted in Fig. 3.77.
Consider R1 = R2 = 1.5, R = 4.7K, VCC = 5V, hfe = 50, and VCE = 0.2V.

Fig. 3.77
3.5. Determine the rise time of a RTL circuit as depicted in Fig. 3.78. Consider R1 = 450 ohms , R = 640
ohms, C = 5pF, N = 10.

Fig. 3.78
 120 Digital Electronics: Principles and Applications

3.6. Determine the current through diode D1 as shown in Fig. 3.79.

Consider RB = RC = 1.5K, R = 4.7K V1 = 0.2V and VD1 = 0.7V.

Fig. 3.79

3.7. Write the truth table of the DTL circuit as depicted in Fig. 3.80.

Fig. 3.80

3.8. Determine the voltage V1 in a HTL NAND gate for the following conditions:
i. T1 begins to come out of cutoff
ii. T2 operates at the edge of saturation

Consider R1 = 3K, R2 = 10K, R3 = 5K, R4 = 10K, VZ = 6.8V, VCC = 12V. Assume all necessary
parameters.
 Digital Logic Family 121

Fig. 3.81 HTL NAND Gate

3.9. Explain the operation CMOS NAND gate with circuit diagram.
3.10. Give a list for the characteristics of TTL logic family.
3.11. Give a list for the characteristics of CMOS logic family and compare with TTL logic family.
3.12. Draw a circuit diagram of TTL NAND gate and explain its operation.
3.13. Define propagation delay, noise margin and fan-out.
3.14. Draw the circuit diagram CMOS NOR gate and explain with truth table.
3.15. Explain interfacing of two logic families for the following conditions:
i. TTL driving CMOS logic family
ii. CMOS driving TTL logic family
3.16. What is noise margin? Explain the effect of noise Table 3.22
margin in operation of logic family.
Parameter Value
3.17. How a TTL device can interface with CMOS device
VIH min 2.0V
when TTL is connected with 5V and CMOS is con-
nected with 12V? VIL max 0.7V
3.18. The specification of TTL gate is given in Table 3.22. V OH min
2.4V
Determine noise margin and propagation delay. VOH max 0.4V
3.19. Calculate the value of pull-up resistance for an open I IH
0.02mA
collector TTL gate with a fan-out of 10. IIL 0.4mA
Consider VIH min = 2.0V, IOH = 20mA and the leakage IOH 4mA
current flows through the collector of TTL output IOL 8mA
transistor is 40 mA.
tPHL 10ns
3.20. Draw the circuit diagram of Schottky NAND gate
tPLH 10ns
and explain its operation briefly.
 CHAPTER

4
COMBINATIONAL LOGIC
4.1 INTRODUCTION
A digital circuit is combinational if its output is depending on inputs. The combinational logic circuit is memory
less. This logic circuit deals with the method of combining basic gates to get desired solution. Combinational
logic circuits can be constructed using logic gates and without feedback from output to input.
A simple mathematical model of combinational logic functions is a unit with inputs and outputs as
shown in Fig. 4.1.
X is the set of input variables X0, X1, X2,
…………. to Xn and Y is the set of output variables
Y0, Y1, Y2 ……………… Yn. The combinational
function operates on the input variables X0, X1, X2,
…………. to Xn and the output variables Y0, Y1, Y2
……………… Yn.
The output Y0 is a function of X0, X1, X2,
Fig. 4.1 Combination logic functions …………. to Xn and it is mathematically written
as Y0 = F(X0, X1, X2, …………. to Xn).
Similarly, Y2, Y3 … Yn are also functions of X0, X1, X2, …………. to Xn. The combination logic circuit
can be designed by the following steps:
Step 1 - Select the problem.
Step 2 - Construct the truth table.
Step 3 - Write switching functions.
Step 4 – Simplify switching functions.
Step 5 - Draw logic diagram.
Step 6 - Develop logic circuit using gates.

4.2 ELEMENTS OF COMBINATIONAL LOGIC

Literal, Product Term, Sum Term, Sum of Products, Product of Sum, Maxterm, Minterm are related with
combinational logic circuits. The definations of all these terms are explained below:
Literal: It is a Boolean variable. It will be either primed or unprimed state in the logic expression.
– – –
As for example, X and X are both literals. Similarly, ABCD consists of four literals A, B, C and D .
–
Product Term: A product term is the logical product (AND) of literals. For example, X, XY , XYZ
are the product of terms when X, Y, Z are Boolean variables. But X + Y + Z is not a product term due to
presence of plus (+) sign in the expression.
 Combinational Logic 123

–
Sum Term: A sum term is sum of literals or the logical OR of literals. For example, X+Y and X +
–
Y + Z are sum terms, when X, Y, Z are Boolean variables. X(Y + Z) is not a sum term as the logical AND
operation is present.
Sum of Products: Sum of product (SOP) is the logical expression in which OR of multiple product
terms are present. Each product term is the logical AND of literals. The example of SOP expression is
–
Y + X Y + XYZ.
Products of Sums: Product of Sum (POS) is the logical expression in which AND of multiple
– –
OR terms are present. Each sum term is the OR of literals. The expression (X + X Y ) (XY + Z) (Y + Z) is
an example of POS.
Minterms: It is a special type of product (AND) term. It is a product term which contains all the
input variables that make up a Boolean expression.
Maxterm: A maxterm is a special type (OR) term. A maxterm is a sum term that contains all the
input variables that make up a Boolean expression.
Canonical Forms: Canonical is defined as “conforming to a general rule”. The rule for boolean
logic is that each term used in a boolean equation must contain all of the variables.
Canonical Sum of Products: A canonical Sum of Products (SOP) is a complete set of min-
terms that defines when an output variable is a logical ‘1’. Each minterm corresponds to the row in the
truth table when the output function is 1.
Canonical Product of Sums: A canonical Product of Sums (POS) is a complete set of max-
terms that defines when an output variable is a logical ‘0’. Each maxterm corresponds to the row in the
truth table when the output function is 0.
Sum of Minterms: Sum of minterms is the logical expression in which OR of multiple product
terms are present. Each product term is the logical AND of literals.
Product of Maxterms: Product of maxterms is the logical expression in which AND of multiple
product terms are present. Each sum term is the logical OR of literals.
Any logic expression can be implemented by logic gates. Then we use Boolean algebra to simplify
the expressions by eliminating redundancy at low cost logic circuit. In design, it is required to realise
logic expression in one form to another form by converting. There are two useful techniques for reducing
combinational logic equations and logic diagrams to the fewest possible elements, namely mapping and
tabular minimisation.
4.3 BOOLEAN EQUATION
Logic can be described by truth table, logic diagram and boolean equation.
There are sixteen possible logic functions for two inputs variable and one out-
put. Figure 4.2 shows the logic function and all possible outputs, namely F0 to Fig. 4.2 Combinational
F15 are depicted in Table 4.1. The output function, F is a function of X and Y. logic function

Table 4.1 All possible output functions of two input variables

All possible output functions

X Y
F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
 124 Digital Electronics: Principles and Applications

–
The output function F0 = 0, F1 = X.Y, F3 = X, F4 = X Y, F5 = Y, F6 = X ≈ Y,
——– — —– – –– – –
F7 = X + Y, F8 = X + Y , F9 = X ≈ Y , F10 = Y , F11 = X Y + XY + XY, F12 = X ,
– – – – –
Fig. 4.3 Logic dia- F13 = X Y + X Y + XY, F14 = X .Y and F15 = 1. These output functions can be
gram of function F1 represented by NOT, AND, NAND, OR, NOR and Ex-OR and Ex-NOR logic
gates. The logic diagram for switching function F1 is shown in Fig. 4.3. Similarly, truth table, logic
diagram and Boolean equations for two, three and four input variables are also explained in this chapter.
4.4 CANONICAL SUM OF PRODUCT (SOP)/MINTERM
REPRESENTATION
A truth table is a table that shows all the input-output possibilities of any logic circuit. A map is visual
display of fundamental products needed for sum of products solution. Two, three and four variables,
truth tables are explained below:
4.4.1 Two Variables
A truth table for two variables A and B is depicted in Table 4.2. It is clear from this truth table that there
are four possible combinations of the variables and corresponding to these four combinations of the
variables there are four possible minterms m0, m1, m2 and m3. Minterm-0 (m0) occurs when the variable A
––
is ‘0’ and the variable B is ‘0’ and then m0 is represented by A B . Assume that the variable A will always
be represented as the most significant bit and the variable B will be represented as the least significant
–
bit. Similarly, Minterm-1(m1) occurs when A is ‘0’ and B is ‘1’ . Consequently, m1 is represented by A B.
In the same way, the other two minterms m2 and m3 can be obtained as given in Table 4.2.
Table 4.2 Truth Table and minterms representation for two-variables
Inputs Output Minterms Numerical Representation
A B O M
––
0 0 0 m0 = A B 0
–
0 1 1 m1 = A B 1
–
1 0 1 m2 = AB 2
1 1 0 m3 = AB 3
It can be seen that each row of the truth table represents a minterm. Below the output (O), 1’s are
placed to indicate that output contains a particular minterm in its sum and 0’s when that term is excluded
from the sum. According to the truth table, the output (O) contains minterm 1 and 2 only. Then the
output can be expressed as – –
O = A B + AB
Another way of representing this relationship is to use the
Greek letters sigma, S and an ‘m’ to represent “the sum of
minterms”. Applying these notations, we can represent Table
4.2 as O = S m(1, 2). The expression O = S m(1,2) should
– – be read as “O is the sum of minterms 1 and 2”. The logic
Fig. 4.4 Logic diagram of O = AB + AB diagram of O = S m(1,2) is shown in Fig. 4.4
4.4.2 Three Variables
Table 4.3 shows the truth table for a three variables function with minterms. According to the truth table
–– – –
the output (O) contains minterm 1, 2, 6 and 7. Consequently the output expression is O = A B C + A BC +
–
ABC + ABC. By using sigma notation, this can be expressed as O = S m(1, 2, 6, 7). The logic diagram
–– – – –
of O = A B C + A BC + ABC + ABC is shown in Fig. 4.5.
 Combinational Logic 125

Table 4.3 Truth table for three variables and minterms

Inputs Output Minterms Numerical
A B C O M Representation
–– –
0 0 0 0 m0 = A B C 0
––
0 0 1 1 m1 = A B C 1
– –
0 1 0 1 m2 = A BC 2
–
0 1 1 0 m3 = A BC 3
––
1 0 0 0 m4 = AB C 4
–
1 0 1 0 m5 = AB C 5
–
1 1 0 1 m6 = ABC 6
1 1 1 1 m7 = ABC 7

4.4.3 Four Variables

The truth table of a four variables function
is depicted in Table 4.4. It is clear from
the truth table that the output, O contains
minterms 1, 2, 6, 7, 11, 12, 14 and 15.
–– – –– –
The expression is O = A B C D + A B CD
– – – – ––
+ A BCD + A BCD + AB CD + ABC D +
–
ABCD + ABCD. Using sigma notation, –– – – –
this can be expressed as O = S m (1, 2, 6, Fig. 4.5 Logic diagram of O = AB C + ABC + ABC + ABC
–– – –– – – – – – ––
7, 11, 12, 14, 15). The logic diagram of O = A B C D + A B CD + A BCD + A BCD + AB CD + ABC D +
–
ABCD + ABCD is shown in Fig. 4.6.
Table 4.4 Truth table of four variables
Inputs Output Minterms
A B C D O M
––––
0 0 0 0 0 m0 = A B C D
–––
0 0 0 1 1 m1 = A B C D
–– –
0 0 1 0 1 m2 = A B CD
––
0 0 1 1 0 m3 = A B CD
– ––
0 1 0 0 0 m4 = A BC D
– –
0 1 0 1 0 m5 = A BC D
– –
0 1 1 0 1 m6 = A BCD
–
0 1 1 1 1 m7 = A BCD
–––
1 0 0 0 0 m8 = AB C D
––
1 0 0 1 0 m9 = AB C D
– –
1 0 1 0 0 m10 = AB CD
–
1 0 1 1 1 m11 = ABCD
––
1 1 0 0 1 m12 = ABC D
–
1 1 0 1 0 m13 = ABC D
–
1 1 1 0 1 m14 = ABCD
1 1 1 1 1 m15 = ABCD
 126 Digital Electronics: Principles and Applications

4.5 CANONICAL PRODUCT OF SUM (POS)/MAXTERM

REPRESENTATION
4.5.1 Two Variables
The truth table for a two variables function can
also be represented in maxterm as shown in
Table 4.5. To find the maxtern from minterm,
all minterms will be complemented. For
—
example, the complement of minterm m3 is A
– – –
B = A + B = M3. The maxterm are represented
as M0, M1, M2 and M3 for two input variables.
The truth Table 4.5 can be expressed in terms
of maxterms as follows.
– – ––– –– –
O = (A + B )(A + B). Fig. 4.6
– – –Logic diagram
– of O =– –A B C D +–A B C D +
This can also be represented as O = ∏(1, 2). A BC D + A BC D + AB C D + ABC D + ABCD + ABCD
The logic circuit diagram is also shown in Fig. 4.7.
Table 4.5 Two-variable truth table and maxterm representation
Inputs Output Maxterms Numerical
A B O M Representation
0 0 1 M0 = A + B 0
–
0 1 0 M1 = A + B 1
–
1 0 0 M2 = A + B 2
– –
1 1 1 M3 = A + B 3

4.5.2 Three Variables

Table 4.6 shows the truth table of the three variables A, B
and C and their maxterm representation are also given in this
table. As per truth table, the output consists of four maxterms
M1, M2, M6 and M7. The maxterm expression of output is
– – – – – – –
O = (A + B + C )(A + B + C)(A + B + C)(A + B + C ).
The above expression can also be represented as O = ∏(1, Fig. 4.7 Logic diagram of O = (A + B–)(A– + B)
2, 6, 7). The logic circuit diagram is also shown in Fig. 4.8.
Table 4.6 Truth table for three variables and maxterms
Inputs Output Maxterms Numerical
A B C O M Representation
0 0 0 1 M0 = A + B + C 0
–
0 0 1 0 M1 = A + B + C 1
–
0 1 0 0 M2 = A + B + C 2
– –
0 1 1 1 M3 = A + B + C 3
–
1 0 0 1 M4 = A + B + C 4
– –
1 0 1 1 M5 = A + B + C 5
– –
1 1 0 0 M6 = A + B + C 6
– – –
1 1 1 0 M7 = A + B + C 7
 Combinational Logic 127

4.5.3 Four Variables

The truth table of four logic variables function and
their maxterm representation are also given in Table
4.7. The max term expression of the given logic
function is
– – –
O– = (A + B +–C + –D)(A– + –B + C + D)(A–+ B +
C + D)(A + B + C + D)(A + B + C + D)
This is can also represented as O = ∏(1, 2, 6, 7, 9).
The logic circuit diagram is depicted in Fig. 4.9.
–
Fig. 4.8 –Logic diagram
– – of O – = (A
– +B
– + C)
Table 4.7 Truth table of four variables
(A + B + C)(A + B + C)(A + B + C )
Inputs Output Maxterms
A B C D O M
0 0 0 0 1 M0 = A + B + C + D
–
0 0 0 1 0 M1 = A + B + C + D
–
0 0 1 0 0 M2 = A + B + C + D
– –
0 0 1 1 1 M3 = A + B + C + D
–
0 1 0 0 1 M4 = A + B + C + D
– –
0 1 0 1 1 M5 = A + B + C + D
– –
0 1 1 0 0 M6 = A + B + C + D
– – –
0 1 1 1 0 M7 = A + B + C + D
–
1 0 0 0 1 M8 = A + B + C + D
– –
1 0 0 1 0 M9 = A + B + C + D
– –
1 0 1 0 1 M10 = A + B + C + D
– – –
1 0 1 1 1 M11 = A + B + C + D
– –
1 1 0 0 1 M12 = A + B + C + D
– – –
1 1 0 1 1 M13 = A + B + C + D
– – – Fig. 4.9 Logic diagram of O = P(1, 2, 6, 7, 9)
1 1 1 0 1 M14 = A + B + C + D
– – – –
1 1 1 1 1 M15 = A + B + C + D

Example 4.1 Determine the boolean function of the truth Table 4.8 in terms of minterms and draw
the logic diagram.

� Solution
The truth Table 4.8 can be represented in terms of minterms 0, 1, 4 & 5 and it can be expressed as
– – – –– –– –
O = ∏ m (0,1, 4, 5) = A B C + A B C + AB C + AB C . Figure 4.10 shows the logic circuit diagram.
Table 4.8
Inputs Output
A B C O
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 0
Fig. 4.10 Logic diagram of O = S m(0, 1, 4, 5) 1 1 1 0
 128 Digital Electronics: Principles and Applications

Example 4.2 Determine the boolean function of the truth Table 4.9 in terms of maxterms and draw
the logic diagram.
Table 4.9
Inputs Output
A B C D O
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
� Solution
The Table 4.9 consists of the following maxterms 0, 1, 2, 3 &15 and it can be represented by O = ∏(0,1,2,3,15).
This function can be expressed as
– – – – – – – –
O = (A + B + C + D)(A + B + C + D)(A + B + C + D) (A + B + C + D) (A + B + C + D ) and its logic
diagram is depicted in Fig. 4.11.

–
Fig. 4.11 Logic Diagram of O = (A + B + C + D)(A + B + C + D)
– – – – – – –
(A + B + C + D) (A + B + C + D) (A + B + C + D )

4.6 MINTERM VS. MAXTERM

Any Boolean function can be written either as sum of minterms or product of maxterms. When the
function is represented by minterms, the function is easily formed by ORING together the minterms
for which the function is true (1). This form of representation is called Canonical sum of product (SOP)
 Combinational Logic 129

representation. Similarly, in the maxterm expressions, the function is formed by ANDING together the
maxterms for which the function is false (0). This form of the function is called the Canonical Product
of Sums (POS) representation. Minterms and maxterms can be formed for any number of variables.
We can form the minterm for any row of truth table by ANDING together all the variables that are
true (1) in that row and the complements of all the variables that are false (0) in that row. In the same
way, we can also form the maxterm for any row by ORING together all the variables that are false (0)
in that row and the complements of all the variables that are true (1) in that row.

4.7 CONVERSION BETWEEN CANONICAL SOP AND CANONICAL POS

FORMS
The Canonical SOP and Canonical POS forms representation of a Boolean function are complementary.
The numbers, which are existing in SOP representation, do not appear in POS representation. Similarly
all the numbers which are exist in POS representation, do not appear in SOP representation.
To convert from one Canonical form to other Canonical form, the symbols S and P will be interchanged
and the list of numbers will be present in new form which is actually missing from original form.
If “n” is the number of variables of the function, there will be 2n number of minterms and maxterms.
When “m” number minterms are present in original expression, then its maxterm representation consists
of (2n – m) maxterms. The conversion from Canonical SOP to Canonical POS Form and Canonical POS
to Canonical SOP form are explained below:

4.7.1 Canonical SOP to Canonical POS Form

The complement of a function which is expressed as the Canonical sum of products (SOP) is equal to the
Canonical product of sum (POS). Table 4.10 shows the truth table of a typical Boolean function. The original
function can be expressed by the minterms which make the function equal to ‘1’. When we take complement
of minterms, we can represent the same function in maxterms which make the function equal to ‘0’.

Table 4.10 Truth table for three variables and maxterms

Inputs Output Minterms Maxterms
A B C O M M
–– –
0 0 0 0 m0 = A B C M0 = A + B + C
–– –
0 0 1 1 m1 = A B C M1 = A + B + C
– – –
0 1 0 1 m2 = A BC M2 = A + B + C
– – –
0 1 1 0 m3 = A BC M3 = A + B + C
–– –
1 0 0 0 m4 = ABC M4 = A + B + C
– – –
1 0 1 0 m5 = ABC M5 = A + B + C
– – –
1 1 0 1 m6 = ABC M6 = A + B + C
– – –
1 1 1 1 m7 = ABC M7 = A + B + C
According to the truth table as given in Table 4.10, the Boolean function in minterms is
–– – – –
F(A, B, C) = S m(1,2,6,7) = m1 + m2 + m6 + m7 = A B C + A BC + ABC + ABC
After incorporating the missing minterm numbers in original function, we can get the complement of
function F(A, B, C) is F¢(A, B, C) = S m(0, 3, 4, 5) .
–– – – –– –
Therefore, F¢(A, B, C) = S m(0, 3, 4, 5) = m0 + m3 + m4 + m5 = A B C + A BC + AB C + ABC
 130 Digital Electronics: Principles and Applications

– ◊ m– ◊ m
The complement of the function F¢(A, B, C) = F(A, B, C) = m0 + m3 + m4 + m5 = m – ◊ m–
0 3 4 5

Applying DeMorgans theorem, we find that

–– – – –– –
F(A, B, C) = m0 + m3 + m4 + m5 = A B C + A BC + AB C + ABC = A–B–C– ◊ A–BC ◊ AB–C– ◊ AB–C
– – – – –
= (A + B + C) (A + B + C )(A + B + C)(A + B + C )
= M0 M3 M4 M5 = P (0,3,4,5)
It can be stated that minterms complement is the maxterm and it can be expressed as
m¢j = Mj , where M = maxterm, m = minterm and j = 0, 1, 2 …..(2n – 1).

4.7.2 Canonical POS to Canonical SOP Form

The complement of a function which is expressed as the Canonical product of sum (POS) is equal to the
Canonical sum of products (SOP). The original function can be expressed by the maxterms which make
the function equal to ‘0’. When we takes complement of maxterms, we can represent the same function
in minterms which make the function equal to ‘1’ .
According to the truth table as given in Table 4.10, the Boolean function in maxterms is
– – – – –
F1(A, B, C) = P (0, 3, 4, 5) = M0 M3 M4 M5 = (A + B + C) (A + B + C )(A + B + C)(A + B + C )
The complement of function F1(A, B, C) is F1¢(A, B, C) = P (1, 2, 6, 7)
Therefore,
– – – – – – –
F1¢(A, B, C) = P (1, 2, 6, 7) = M1 M2 M6 M7 = (A + B + C ) (A + B + C) (A + B + C) (A + B + C )
The complement of the function F1¢(A, B, C) = F1(A, B, C) = M1 M2 M6 M7
Applying DeMorgans theorem, we find that
— — — —
F1(A, B, C) = M 1 + M 2 + M 6 + M 7
– – – – – – –
=A+B+C +A+B+C+A+B+C+A+B+C
–– – – –
= A B C + A BC + ABC + ABC = m1 + m2 + m6 + m7
= S m(1,2,6,7)
It can be stated that maxterm complement is the minterms and it can be expressed as
M¢j = mj , where M = maxterm, m = minterm and j = 0, 1, 2 … (2n – 1).

4.8 DEVELOPMENT OF TRUTH TABLE FROM LOGIC EXPRESSION

Sometimes, we have a Boolean expression and we want to find its truth table. The Boolean expression
can be written in minterms or maxterms. For example, we consider that the Boolean logic function is
O = P(0, 1, 4, 5, 10, 11, 14, 15).
The logic expression for the function O = P(0, 1, 4, 5, 10, 11, 14, 15) is
– – – – – –
O = (A + B + C + D)(A + B + C + D)(A + B + C + D)(A + B + C + D )(A + B + C + D)
– – – – – – – – – –
(A + B + C + D)(A + B + C + D)(A + B + C + D )
In this logic expression, the equation is written in the form of maxterms. The truth table for the above
Boolean expression is shown in Table 4.11, where we have placed a ‘0’ in each row that corresponds
 Combinational Logic 131

to a maxterm in the function and a ‘1’ in all other rows at output column. To form a truth table for any
function written in maxterms, the process is almost identical. The logic circuit diagram of O = ∏(0, 1,
4, 5, 10, 11, 14, 15) is depicted in Fig. 4.12.
Table 4.11
Inputs Output Maxterms
A B C D O M
0 0 0 0 0 M0 = A + B + C + D –
0 0 0 1 0 M1 = A + B + C– + D
0 0 1 0 1 M2 = A + B + C– + D –
0 0 1 1 1 M3 = A + B– + C + D
0 1 0 0 0 M4 = A + B– + C + D–
0 1 0 1 0 M5 = A + B– + C– + D
0 1 1 0 1 M6 = A + B– + C– + D –
0 1 1 1 1 M7 = A– + B + C + D
1 0 0 0 1 M8 = A– + B + C + D–
1 0 0 1 1 M9 = A– + B + C–+ D
1 0 1 0 0 M10 = A– + B + C– + D –
1 0 1 1 0 M11 = A– + B– + C + D
1 1 0 0 1 M12 = A– + B– + C + D–
1 1 0 1 1 M13 = A– + B– + C– + D
1 1 1 0 0 M14 = A– + B– + C– + D–
1 1 1 1 0 M15 = A + B + C + D

Fig. 4.12 Logic diagram of O = P(0,1,4,5,10,11,14,15)

To develop a logic expression written in minterm from the truth Table 4.12, the procedure is same.
Consider the logic function is O =∑ m (1, 3, 5, 7, 8, 9, 12, 13) and it can be expressed as
––– –– – – – ––– –– –– –
O = A B C D + A B CD + A BCD + A BCD + AB C D + AB C D + ABCD + ABC D.
The truth table of the logic function is illustrated in Table 4.12 and the logic circuit diagram is
depicted in Fig. 4.13.
 132 Digital Electronics: Principles and Applications

Table 4.12
Inputs Output Minterms
A B C D O M– – – –
0 0 0 0 0 m0 = A– –B C
–D
0 0 0 1 1 m1 = A–B–C D –
0 0 1 0 0 m2 = A–B–CD
0 0 1 1 1 m3 = A– B CD
––
0 1 0 0 0 m4 = A– BC– D
0 1 0 1 1 m5 = A–BC D –
0 1 1 0 0 m6 = A–BCD
0 1 1 1 1 m7 = A BCD
–––
1 0 0 0 1 m8 = AB– C– D
1 0 0 1 1 m9 = AB–C D–
1 0 1 0 0 m10 = AB–CD
1 0 1 1 0 m11 = AB CD––
1 1 0 0 1 m12 = ABC– D
1 1 0 1 1 m13 = ABC D –
1 1 1 0 0 m14 = ABCD
1 1 1 1 0 m15 = ABCD

Fig. 4.13 Logic diagram of O = Sm (1, 3, 5, 7, 8, 9, 12, 13)

4.9 LOGIC SIMPLIFICATION USING BOOLEAN ALGEBRA

The maxterm and minterm expressions can be simplified by using Boolean algebra. The procedure is
given below for both expressions.
For example, the maxterm expression is
– – – –
O = (A + B + C + D)(A + B + C + D)(A + B + C + D)(A + B + C + D )
– – – – – – – – – – – –
(A + B + C + D) (A + B + C + D)(A + B + C + D)(A + B + C + D )
 Combinational Logic 133

–
The product of sum expression can be simplified by using logic adjacency D + D = 1
= (A + B + C) (A + B + C)(A– + B + C–)(A– + B– + C–)
– –
= (A + C) (A + C )
– –
Thus, the simplified expression is O = (A + C) (A + C ) and Fig. 4.14 shows the logic circuit diagram.
––– –– – – –
Similarly, we consider that the minterm expression is O = A B C D + A B CD + A BCD + A BCD
––– –– –– –
+ AB C D + AB C D + ABCD + ABC D and apply Boolean algebra to simplify it. Therefore, the simplified
form of minterm expression is given below:
–– – – – –– – – –
= A B D(C + C) + A BD(C + C) + AB C (D + D) + ABC (D + D)
–– – –– – – –
= A B D + A BD + AB C + ABC , where (C + C) = 1 and D + D = 1
– – – – – –
= A D(B + B) + AC (B + B) = A D + AC

Figure 4.12 represents the logic diagram of the Boolean expression O = (A + B + C + D)(A + B + C +
– – – – – – – – – – – – – – – –
D)(A + B + C + D)(A + B + C + D ) (A + B + C + D) (A + B + C + D)(A + B + C + D)(A + B + C + D ) us-
– –
ing gates before simplification. After simplification we get the simplified expression O = (A + C) (A + C )
and the logic diagram of this simplified expression using logic gates is depicted in Fig. 4.14. Similarly,
––– –– – – – ––– ––
the logic diagram of the Boolean expression O = A B C D + A B CD + A BCD + A BCD + AB C D + AB C D
–– –
+ ABCD + ABC D is shown in Fig. 4.13 using gates before simplification. After simplification, we obtain
– –
the simplified expression of O = A D + AC and Fig. 4.15 represents the logic diagram of the simplified
– –
expression of O = A D + AC . Consequently, it is very clear, from the circuit diagrams that we can be able
to represent the same logic function by different circuit diagrams and also in most simplified form. The
simplified representation of a logic function using logic gates has the following advantages: less cost,
reduce number of logic gates, reduce complexity, simple circuit, and reduce delay and first logic output.

– – – –
Fig. 4.14 Logic diagram of O = (A + C) (A + C ) Fig. 4.15 Logic diagram of O = A D + AC

Example 4.3 Develop the truth table of the logic expression O = P(0,1,2,4,5,7).
� Solution
Table 4.13 shows the truth table of the logic function O = P(0,1,2,4,5,7).

Table 4.13
Inputs Output Maxterms Numerical
A B C O M Representation
0 0 0 0 M0 = A + B + C 0
(Contd...)
 134 Digital Electronics: Principles and Applications

(Contd...)
–
0 0 1 0 M1 = A + B + C 1
–
0 1 0 0 M2 = A + B + C 2
– –
0 1 1 1 M3 = A + B + C 3
–
1 0 0 0 M4 = A + B + C 4
– –
1 0 1 0 M5 = A + B + C 5
– –
1 1 0 1 M6 = A + B + C 6
– – –
1 1 1 0 M7 = A + B + C 7

Example 4.4 Develop the truth table of the logic expression O =∑m(1,2,3,4,6,7).

� Solution
Table 4.14 shows the truth table of the logic function O = ∑m(1, 2, 3, 4, 6, 7)

Table 4.14
Inputs Output Minterms Numerical
A B C O M Representation
–––
0 0 0 0 m0 = A B C 0
––
0 0 1 1 m1 = A B C 1
– –
0 1 0 1 m 2 = A BC 2
–
0 1 1 1 m 3 = A BC 3
––
1 0 0 1 m 4 = AB C 4
–
1 0 1 0 m 5 = AB C 5
–
1 1 0 1 m 6 = ABC 6
1 1 1 1 m 7 = ABC 7

Example 4.5 Simplify the logic expression using Boolean algebra and draw the logic circuit for
O = Σ(0, 1, 2, 6, 10, 11).

� Solution
The logic function O = Σ(0, 1, 2, 6, 10, 11) contains four
variables. Table 4.15 shows the truth table of the logic
function and this function can be expressed in standard
SOP form as given below:
–––– ––– –– – – – – –
O = A B C D + A B C D + A B CD + A BCD + AB CD +
–
AB CD.
Then Boolean algebra is used to simplify the function.
––– – – – – – –
O = A B C (D + D) + A CD (B + B) + AB C(D + D)
––– – – – –
= A B C + A CD + AB C where, A + A = 1
–––
Therefore, the simplified logic expression is O = A B C +
– – –
A CD + AB C and the logic circuit diagram is shown in Fig. 4.16 Logic diagram of
––– – – –
Fig. 4.16. O = A B C + A CD + AB C
 Combinational Logic 135

Table 4.15
Inputs Output Minterms
A B C D O m ––––
0 0 0 0 1 m 0 = AB CD
–––
0 0 0 1 1 m 1 = AB CD
–– –
0 0 1 0 1 m 2 = A B CD
––
0 0 1 1 0 m 3= A B CD
– ––
0 1 0 0 0 m 4= A BC D
– –
0 1 0 1 0 m 5 = A BC D
– –
0 1 1 0 1 m 6 = A BCD
–
0 1 1 1 0 m 7 = A BCD
–––
1 0 0 0 0 m 8 = AB C D
––
1 0 0 1 0 m 9 = AB C D
– –
1 0 1 0 1 m 10 = AB CD
–
1 0 1 1 1 m 11 = AB CD
––
1 1 0 0 0 m 12 = ABC D
–
1 1 0 1 0 m 13 = ABC D
–
1 1 1 0 0 m 14 = ABCD
1 1 1 1 0 m 15 = ABCD

Example 4.6 Simplify the logic expression using Boolean algebra and draw the logic circuit for
O = ∏ (4, 5, 8, 9, 10, 11)
� Solution
Table 4.16 shows the truth table of logic function O = ∏ (4,5, 8, 9, 10,11) and the standard POS representation
of the function is
– – – – – – – – – – –
O = (A + B + C + D) (A + B + C + D ) (A + B + C + D) (A + B + C + D ) (A + B + C + D) (A + B + C + D )
The above expression can also be simplified using logic adjacency of Boolean algebra and the simplified
of the function is given below:
– – – – – –
O = (A + B + C) (A + B + C) (A + B + C ) = (A + B + C) (A + B)
– –
The logic circuit diagram of this simplified logic expression O = (A + B + C) (A + B) is depicted in Fig. 4.17.
Table 4.16
Inputs Output Maxterms
A B C D O M
0 0 0 0 1 M0 = A + B + C + D
–
0 0 0 1 1 M1= A + B + C + D
–
0 0 1 0 1 M2= A + B + C + D
– –
0 0 1 1 1 M3= A + B + C + D
–
0 1 0 0 0 M4 = A + B + C + D
–
0 1 0 1 0 M5= A + B + C + D
– –
0 1 1 0 1 M6= A + B + C + D
– – –
0 1 1 1 1 M7 = A + B + C + D
–
1 0 0 0 0 M8 = A + B + C + D
(Contd...)
 136 Digital Electronics: Principles and Applications

(Contd...)
– –
1 0 0 1 0 M9= A + B + C + D
– –
1 0 1 0 0 M10= A + B + C + D
– – –
1 0 1 1 0 M11= A + B + C + D
– –
1 1 0 0 1 M12 = A + B + C + D
– – –
1 1 0 1 1 M13= A + B + C + D
– – –
1 1 1 0 1 M14= A + B + C + D
– – – –
1 1 1 1 1 M15= A + B + C + D

– –
Fig. 4.17 Logic diagram of O = (A + B + C) (A + B)

—– —–
Example 4.7 Simplify the logic expression (AB(C + BD) + A B ) CD.

� Solution
—– —–
(AB(C + BD) + A B ) CD
– – – –
= (AB(C + B + D) + A + B )CD Applying DeMorgan
– – – –
= (ABC + ABB + ABD + A + B )CD After distribute
– – – –
= (ABC + ABD + A + B )CD As ABB = 0
– – –
= ABCD + ABDCD + A CD + B CD After distribute
– – –
= ABCD + A CD + B CD As ABDCD = 0
– –
= CD(AB + A + B ) Distribute
—–
= CD(AB + A B ) Applying DeMorgan
—–
= CD As AB + A B = 1

Example 4.8 Simplify the logic diagram as given below:

� Solution
The output Y of the logic diagram as shown in Fig. 4.18 is

Y = AB BC BC CD Applying DeMorgan
= (AB + BC)(BC + CD) After distribute
= (ABBC + ABCD) + (BCBC + BCCD) Remove repeated variables
= ABC + ABCD + BC + BCD Apply absorption
= ABC (1 + D) + BC(1 + D)
—–
= ABC + BC = BC(A + 1) = B C Fig. 4.18
 Combinational Logic 137

4.10 KARNAUGH MAPS

M. Karnaugh published his work in 1953 with the title “The map method for synthesis of combinational
logic circuits”. Actually, this map method is graphical representation of Boolean functions and is used
to simplify Boolean functions considering the idea of an array of next neighbor, and logic adjacent
minterms. In place of writing all the minterms, M. Karnaugh represented the Boolean functions using
minterm relations. This map method is known as a Karnaugh map or K-map. A Karnaugh map is a
matrix of squares and each square represents a minterm or maxterm from of a Boolean expression.
A Karnaugh map is used to find input variable redundancies and to reduce output Boolean equation.
Each map lists the 2n product terms that can be formed from ‘n’ variables, each in a different square. A
product term in ‘n’ variables is called a minterm.
For 3 variables, 23=8 minterms and for 4 variables, 24=16 minterms..The Karnaugh map for two,
three, four, five and six variables are explained below:
4.10.1 Two Variables Karnaugh Map
Figure 4.19 shows the Karnaugh map for a two variable function. Each square or cell in the map represents
a minterm in terms of variables A and B. The value of one of the variables associated with the cell is given
above the cell and the value of the other variable associated with the same cell is given to the left of the cell.
At the upper left corner of the K-map, variable names A and B are shown above and below a diagonal line
respectively. In this figure, the column variable is A and the row variable is B. The minterm indices associated
with a cell is given in the lower right corner of the cell. For example, in this map the minterm associated with
the lower right cell is m3 = AB, this minterm is true if A = 1, and B = 1 as depicted in Fig. 4.19(c).

Fig. 4.19 (a), (b) and (c) Two variables map

Figure 4.19 (a), (b) and (c) are alternatively used in Karnaugh map representation. The names of
the variables are listed on both sides of the diagonal line. The ‘A’ above the diagonal indicates that the
–
variable A is assigned to the columns. The ‘0’ is a substitute for A , and the ‘1’ substitutes for A. Below
–
the diagonal ‘B’ is associated with the rows: ‘0’ stands for B , and ‘1’ stands for B.
Table 4.17 shows the truth table of a two variables function. The outputs of the truth table correspond
on an one-to-one basis are entered into Karnaugh map as depicted in Fig. 4.20. For example, enter “0”
––
in cell-0 corresponding to Boolean expression A B . Similarly, enter “1” in cell-1, 2 and 3 corresponding
 138 Digital Electronics: Principles and Applications

– –
to Boolean expressions A B, AB and AB respectively. The minterm
relationship of the function as given in the Karnaugh map (K-map)
– –
is O = A B + AB + AB.
This map has two grouping of two minterms because of the
logic adjacency of 2 adjacent cell regions in the K-map. The shaded
Fig. 4.20 Two variable map
rectangle region corresponds to A and another shaded rectangle
encloses the region corresponding to B. So the simplified function
is O = A + B .
Figure 4. 21 (a), (b), and (c ) show the different adjacent 2-cell regions in the 2-variable K-map.

Table 4.17 Two-variables truth table and minterm representation

Inputs Output Minterms Numerical
A B O m Representation
––
0 0 0 m0 = A B 0
–
0 1 1 m 1 = AB 1
–
1 0 1 m 2 = AB 2
1 1 1 m 3 = AB 3

Fig. 4.21 The adjacent 2 cell regions of two variable K map

Example 4.9 Figure 4.22 (a) and 4.22(b) are given. Determine the Boolean expression.

Fig. 4.22 Two variables Karnaugh map

 Combinational Logic 139

� Solution
K-map is used to simplify the boolean expression based on adjacent cells. Actually, cells make one or more
variables common in boolean expression. The procedure of
determining the boolean expression as follows:
Step-1 Group the two 1s in the column of K-map;
Step-2 Determine the variables top and/or side, which are the
same for the group;
Step-3 Write the Boolean expression. Here the Boolean
–
expression of the function of Fig. 4.22(a) is B.
The procedure of determining the Boolean expression for Fig.
4.22 (b) is given below:
Step-1 Group the two 1’s in the row of K-map;
Step-2 Determine the variables top and/or side, which are the
same for the group;
Step-3 Write the Boolean expression. At this time, the boolean
expression of the function of Fig. 4.22 (b) is A.

Fig. 4.22 (a) and (b)

Example 4.10 Table 4.18 shows the truth table of a function. Transfer the outputs to the Karnaugh
and write the Boolean expression.
� Solution
Transfer the 1s from the locations in the Truth table to the corresponding
Table 4.18
locations in the K-map. Fig. 4. 23 shows the K-map for the truth table 4.18.
A B Output Then the following procedure is done to determine the Boolean function
0 0 0
0 1 1 Step – 1 Group rectangle the two
1 0 1 1’s in the column under B
1 1 1 Step – 2 Group rectangle the two
1’s in the row right of A
Step – 3 The product term for first group is B
Step – 4 The product term for second group is A
Step – 5 The sum-of-products of above two terms is O = A + B

Fig. 4.23

Example 4.11 Simplify the logic diagram as shown in Fig. 4.24.

Fig. 4.24
 140 Digital Electronics: Principles and Applications

� Solution
The logic diagram as shown in Fig. 4.24 can be simplified in the
following steps as given below:
Step – 1 The Boolean expression for the logic diagram as shown in
Fig. 4.24 can be written as
– –
O = A B + AB + AB
Step – 2 Relocate the product terms to the Karnaugh map as depicted
in Fig. 4.25.
Step – 3 Form groups of adjacent cells.
Fig. 4.25
Step – 4 The Boolean expressions for groups can be written.
Step – 5 The sum-of-products of above two terms is O = A + B.
Step – 6 The simplified logic diagram can be drawn as shown in Fig.
4.26. Fig. 4.26

Example 4.12 Simplify the logic diagram as shown in Fig. 4.27.

Fig. 4.27
� Solution
The logic diagram as shown in Fig. 4.26 can be simplified in the
following steps as given below:
Step – 1 The Boolean expression for the logic diagram as shown in Fig.
– –
4.27 can written and it is O = A B + AB
Step – 2 Relocate the product terms to the Karnaugh map as depicted in Fig. 4.28
Fig. 4.28.
Step – 3 The grouping of adjacent cells is not possible as only diagonal
cells are present. Hence simplification is not possible.
Step – 4 The simplified logic diagram can be drawn using Exclusive Fig. 4.29
OR gate as shown in Fig. 4.29.

4.10.2 Three Variables Karnaugh Map

Table 4.19 shows the truth table of a three variable function and
the 3-variable Karnaugh map can be used to represent the same
as illustrated in Fig. 4.30. This 3-variable Karnaugh map has
23 = 8 cells, the small squares within the map. Each individual
cell is exclusively identified by the three Boolean variables A,
––
B, C. It is depicted in Fig. 4.30 that A B C distinctively selects
Fig. 4.30 Three variable maps
 Combinational Logic 141

the lower left most cell m1 or 1. Similarly, each cell can

be uniquely identified by a 3-variable product term, a
–
Boolean AND expression. For example, AB C following
–
the C row across to the right and the AB column down,
–
both intersecting at the lower right most cell AB C.
The sequence of numbers across the top of the map
is not a binary sequence and it should be 00, 01, 11, 10.
Actually, 00, 01, 11, 10 is Gray code sequence as only
one binary bit changes during one number to the next
number in Gray code sequence. As adjacent cells are al-
ways varied by one bit, we use Gray code in K-map rep-
resentation. For this, it is required to organise the outputs
of a logic function in such a way so that we can visualise
all at a time. Therefore, the column and row headings of
a Karnaugh map must be in Gray code order. Three vari-
able Karnaugh map with adjacent cells combinations is
given in Fig. 4.31(a), (b), (c) and (d).

Table 4.19
Inputs Output Minterms Numerical
A B C O M Representation
–– –
0 0 0 0 m0= A BC 0
––
0 0 1 1 m 1= A B C 1
– –
0 1 0 1 m 2= A BC 2
–
0 1 1 0 m 3= A BC 3
––
1 0 0 0 m 4= AB C 4
–
Fig. 4.31 Three variable Karnaugh map 1 0 1 0 m 5= AB C 5
–
with adjacent cells combinations (a) four 1 1 0 1 m 6= ABC 6
cells (b) four cells (c) four cells (d) eight cells 1 1 1 1 m 7= ABC 7

4.10.3 Four Variables Karnaugh Map

The truth table of a function of four variables is illustrated in
Table 4.20. Since 24 is 16, there are 16 combinations of variables
labeled 0 through 15. Figure 4.32 shows the Karnaugh map
for four variables. This map has four rows and four columns.
The columns are assigned to variables A and B, but rows for
variables C and D. All variables are follows the gray code for
shifting from one cell to next cell. All product terms of four
variables as shown in Table 4.20 can be placed in all 16 cells of
Fig. 4.32 Four variables K map
 142 Digital Electronics: Principles and Applications

map. In minimisation of a four variables function, initially, we find out the most distinguished -1 cells, which
lead to essential prime implicants. After that, the rest ‘1’ cells are grouped to provide the minimal form of
the function. The simplification procedure of Boolean function using K-map is explained later in detail.
Table 4.20 Truth table of four variables

Inputs Output Minterms

A B C D O M
–– – –
0 0 0 0 0 m0 = A BCD
–– –
0 0 0 1 1 m1 = A BCD
–– –
0 0 1 0 1 m2 = A BCD
––
0 0 1 1 0 m3 = AB CD
– ––
0 1 0 0 0 m4 = ABC D
– –
0 1 0 1 0 m 5 = ABC D
– –
0 1 1 0 1 m 6 = A BCD
–
0 1 1 1 1 m 7 = A BCD
–––
1 0 0 0 0 m 8 = ABCD
––
1 0 0 1 1 m 9 = ABCD
– –
1 0 1 0 1 m 10 = ABCD
–
1 0 1 1 0 m 11 = ABCD
––
1 1 0 0 0 m 12 = ABCD
–
1 1 0 1 0 m 13 = ABC D
–
1 1 1 0 0 m 14 = ABCD
1 1 1 1 1 m 15 = ABCD

4.10.4 Five Variables Karnaugh Map

Karnaugh maps can be extended to five variables by using a three dimensional array of cells. In three-
dimensional representation all next neighbour cells are logic adjacent. But it is little bit difficult to
represent in a two dimensional Karnaugh map. In this two dimensional representation, each section of
map are placed side by side sequentially according to their sequence in three dimensional form.
To represent five variables K-map, 25=32
cells are required to accommodate all the
product terms and two blocks of sixteen
cells are required. Figure 4.33 shows the
five variables K-map. In this figure, the left
block is used for minterms from m0 to m15
where most significant variable A=0 and
the right block can be used minterms for
m16 to m31 where A=1. The most significant
variable is shown as the map-heading
variable. During visualisation of the map, Fig. 4.33 Five variables Karnaugh map
 Combinational Logic 143

we consider the block of the map is stacked on the top of the right block. Therefore, cell 0 is logic
adjacent to cell 16, cell 2 is logic adjacent to cell 18, cell 8 is logic adjacent to cell 24, cell 10 is logic
adjacent to cell 26 and so on. Table 4.21 shows the truth table for a function of five variables and a five
variable map can be accommodated from this table as shown in Fig. 4.33.
The minterm representation of Table 4.21 is
O = Σ(m0, m1, m2, m3, m8, m16, m17, m18, m19, m24)
To simplify this function, we try to make group all entries of K-map cells. When left block lies above
the right block, all cells that are neighbours side-to-side and top to bottom. Cell 2 is logic adjacent to cell
18 and cell 8 is logic adjacent to cell 24 and so on. So cells 0, 1, 2, 3 and cells 16, 17, 18, 19 are logic
adjacent and makes a group of eight cells. Similarly, the group of two cells consists of cell 8 and 24. In
normal minimisation of a five variables, we may not be able to find out the minimum numbers of terms
or literals. The better approach is to find the most distinguished –‘1’ cells which lead to essential prime
implicants. After that the rest 1’s are grouped to provide the minimal from of the function.
Table 4.21 Truth table of five variables
Inputs Output Minterms
A B C D E O M
0 0 0 0 0 1 m0
0 0 0 0 1 1 m1
0 0 0 1 0 1 m2
0 0 0 1 1 1 m3
0 0 1 0 0 0 m4
0 0 1 0 1 0 m5
0 0 1 1 0 0 m6
0 0 1 1 1 0 m7
0 1 0 0 0 1 m8
0 1 0 0 1 0 m9
0 1 0 1 0 0 m10
0 1 0 1 1 0 m11
0 1 1 0 0 0 m12
0 1 1 0 1 0 m13
0 1 1 1 0 0 m14
0 1 1 1 1 0 m15
1 0 0 0 0 1 m16
1 0 0 0 1 1 m17
1 0 0 1 0 1 m18
1 0 0 1 1 1 m19
1 0 1 0 0 0 m20
1 0 1 0 1 0 m21
1 0 1 1 0 0 m22
1 0 1 1 1 0 m23
1 1 0 0 0 1 m24
1 1 0 0 1 0 m25
1 1 0 1 0 0 m26
1 1 0 1 1 0 m27
1 1 1 0 0 0 m28
1 1 1 0 1 0 m 29
1 1 1 1 0 0 m 30
1 1 1 1 1 0 m 31
 144 Digital Electronics: Principles and Applications

4.10.5 Six Variables Karnaugh Map

The six variables Karnaugh map can be developed based on the method of five variables Karnaugh
map. Figure 4.34 shows the six variables map. In this map, four blocks of 16 cells are required and
four variables C, D, E, and F are used. The other two variables are the two most significant variables
that can be used as map headings for each four variables block of the map. During three-dimensional
representation of six variables Karnaugh map, the four blocks of four variables are stacked one on top of
another according to variation of two most significant bits A and B. The sequence is started with 00 and
others will be 01, 11 and 10. According to sequence of stack, subsequent elements at the top and bottom
of the stack are logic adjacent. Consequently, cell 0 is logic adjacent to cell 16, cell 16 is logic adjacent
to cell 48, cell 48 is logic adjacent to cell 32 , and so on.

Fig. 4.34 Six variables Karnaugh map

4.11 CONSTRUCTION OF KARNAUGH MAPS FROM LOGIC

EXPRESSION
The Karnaugh map for a given Boolean expression can be constructed by the following steps:
Step – 1 Find out the size of the K-map. Actually the number of variables in the function can deter-
mine the size of the K-map. If the function has ‘n’ variables, then K-map of the said function
consists of 2n cells.
Step – 2 Assemble all 2n cells in the form of m ¥ n matrix. Generally, m is equal to n. Here m =
number of rows and n = number of columns.
Step – 3 Locate the decimal number to each cell according to gray code sequence.
Step – 4 Enter a ‘1’ in each cell subsequent to each decimal number of the minterms expression,
SOP and enter a ‘0” in each square corresponding to each decimal number of the maxterms,
POS.
 Combinational Logic 145

–
Example 4.13 Construct a Karnaugh Map for the Boolean function O = AB + CD

� Solution
–
The expression O = AB + CD is a four variables function. So the K-map of the said function consists of
2 = 16 cells. The K-map can be represented by 4 ¥ 4 matrix as shown in Fig. 4.35. The first term of the
4
–
expression is AB, we put 1s in all the cells of the map where A = 1 and B = 1. Then the second term is CD,
we also locate 1’s in all the cells, where C = 1and D = 0.

Fig. 4.35 Four variable map

Example 4.14 Construct a Karnaugh map for the function O = ABC + BC

� Solution
The expression O = ABC + BC is a three variables function. So the K-map of the said function consists
of 23 =8 cells. The K-map can be represented by 4 ¥ 2 matrix as shown in Fig. 4.36. The first term of the
expression is ABC, we put 1s in all the cells of the map where A = 1, B = 1 and C = 1. Then the second term
is BC, we also locate 1s in all the cells, where B = 1and C = 1.

Fig. 4.36 Three variable maps

 146 Digital Electronics: Principles and Applications

4.12 LOGIC SIMPLIFICATION USING KARNAUGH MAPS

In general, Karnaugh map is used to find the simplest form of logic expression. The Karnaugh map can
reduce any logic function very rapidly and easily compared to Boolean algebra. As the logic expression
is simplified, the number of gates and inputs will be reduced. Hence, the logic circuit will be cheap
due to elimination of components. Therefore, to design a low cost and efficient logic circuit, designer
should choose the lowest number of gates with the lowest number of inputs per gate. The minimisation
procedure using Karnaugh map is explained below:
Step – 1 Initially, truth table or Boolean expression of a logic function is converted into correspond-
ing K - map.
Step – 2 Start groupings of 1’s in all the entries of the K-map. Actually, consider groupings of two
terms, then four terms, then eight terms and so on. After that choose minimum number of
groupings to cover all the entries in the map. In this step, we always try to avoid forming
groupings, which are already covered by larger groupings.
Step – 3 Find all the single entries which can not be covered by any grouping.
Step – 4 When steps from 1 to 3 are completed, write the minimum expression corresponding to
groupings so that every 1s of the K-map is covered by at least one grouping.
For example, consider a logic expression
–– – – –– – – – – –
O = ABC D + ABC D + ABCD + ABCD + A B CD + A BCD + AB CD .
This is a four variables function. Therefore, a four variables Karnaugh map is required to represent
the logic function. Fig. 4.37 shows the Karnaugh map
of this logic function.
The above Boolean expression has seven product
terms. They are mapped top to bottom and left to right
on the K-map as given in Fig. 4.37. For example, the
––
first P-term ABC D is first row 3rd cell, corresponding
to map location A = 1, B = 1, C = 0, D = 0. Then other
product terms are placed in a similar manner. After
that, start groupings of 1s in all the entries of the
K-map. It is very clear from the Fig. 4.37 that there are
only two groups of four terms to cover all the entries
in the map. The dashed horizontal group corresponds
– Fig. 4.37
the simplified product term CD . The vertical group
corresponds to Boolean expression AB. Representing two groups, we find the minimum expression in
–
the sum-of-products form O = AB + CD .
The four variables logic function can also be reduced by Boolean algebra but it is very tedious as
given below:
–– – – –– – – – – –
O = ABC D + ABC D + ABCD + ABCD + A B CD + A BCD + AB CD .
– – – – – – – –
= ABC (D + D) + ABC(D + D) + BCD(A + A) + B CD(A + A)
– – – – – – – –
= ABC + ABC + BCD + B CD = AB(C + C) + CD (B + B) = AB + CD
As the Karnaugh map reduction process is faster and easier than Boolean algebra, we commonly used
K-map specially if there are many logic reductions to do.
 Combinational Logic 147

– –– –
The K-map for logic expression O = A BC D + A
– – – – –– – –
BC D + A BCD + A BCD + ABC D + ABCD + ABCD +
ABCD is shown in Fig. 4.38 and we can determine its
simplified form using K-map that is O=B.

Fig. 4.38
––– – –
Similarly, the logic expression O = A B C D + A BC D
–– – –– – –
+ AB C D + ABCD + A B CD + A BCD + AB CD + ABCD
can simplified using K-map and it is O = D as depicted
Fig. 4.39
in Fig. 4.39.
When we fold up the corners of the map, it is a napkin
to make the four cells physically adjacent as shown in Fig.
4.40, The four cells of the above K-map are a group of four
– –
as the Boolean variables B and D are in common. The logic
–– – – –– – –– – – –
expression O = A B C D + A B CD + AB C D + ABCD can be
––
represented in the simplified form that is O = B D .
In the K-map as shown in Fig. 4. 41, if we roll the top and bot-
tom edges of K-map,
a cylinder is formed
with eight adjacent
cells. This group of
eight adjacent cells
has one common
Fig. 4.40 Boolean variable D
= 0. Consequently,
the logic expression
–––– – –
O = A B C D + A BC
– –– – ––
D + ABCD + ABC D
–– – – – Fig. 4.41
+ A BCD + A BCD +
– – – –
ABCD + ABCD can be represented by one product term, D. The
–
original eight term Boolean expression simplifies to O = D.
To simplify the Karnaugh map as given in Fig. 4.42,
we can sketch out two groups of eight cells. A group of
–
eight cells can be represented by B and another group
–
Fig. 4.42 of eight cells represents D . Therefore, the simplified
–––– – –– –– – ––
output of O = A B C D + A BC D + AB C D + ABC D
–– – – – – – – –– – –– –– – – –
+ A B CD + A BCD + AB CD + ABCD + A B C D + A B CD + AB C D + AB CD is O = B + D . Similarly,
 148 Digital Electronics: Principles and Applications

–– –
Fig. 4.43 can be represented by O = A C + BC + D. Figure 4.44 can also be represent by grouping 2n of
–– –
cells and can be represented by O = A B + AB + A CD.

Fig. 4.43 Fig. 4.44

4.13 PRODUCT OF SUMS SIMPLIFICATION USING KARNAUGH MAPS

We are already familiar with Sum-of-Product (SOP) solutions to simplify Boolean function using
Karnaugh map. But there is also a Product-of-Sums (POS) solution for each SOP solution, which
sometimes be more useful depending on the application. In this simplification, we use the maxterms
of the function. A maxterm is a Boolean expression resulting in a ‘0’ for the output of a single cell
expression, and 1s for all other cells in the Karnaugh map.
Figure 4.45 shows the three variables K-map. There is a
single ‘0’ in a map and other cells are 1s. Therefore, 1s covers
maximum area of K-map. The maxterm is a ‘0’, not a ‘1’ in the
–
Karnaugh map. The maxterm is a sum term, A + B + C. The
–
equation of the map is O = A + B + C. The procedure for placing
a maxterm in the K-map is given below:
Step-1 Identify the sum term to be mapped.
Step-2 Write corresponding binary numeric value.
Step-3 Form the complement Fig. 4.45 Three variables K-map
Step-4 Use the complement as an address to place a 0 in
the K-map
Step-5 Repeat for other maxterms
– – –
Consider a maxterm A + B + C. Numeric value 000 corre-
– – –
sponds to A + B + C. The complement of 000 is 111. Then Place
– – –
a 0 for maxterm A + B + C in this cell (1, 1, 1) of the K-map as
– – –
shown in Fig. 4.46. When A + B + C is (1¢ + 1¢ + 1¢), all 1s in,
which is (0+0+0) after taking complements, we have the only
condition that will give us a 0. All the 1s are complemented to
all 0s, which is 0 when OR operation is done. Fig. 4.46 Three variables K-map
 Combinational Logic 149

A Boolean product-of-sums expression is multiple of

– – – – –
maxterms like O = (A + B + C) (A + B + C ). The maxterm
– –
(A + B + C) stands for numeric 001 and its complements is 110,
– – –
placing a 0 in cell (1,1,0). Similarly the maxterm ((A + B + C ))
yields numeric 000 which complements to 111, placing a 0 in
cell (1,1,1) as depicted in Fig. 4.47. At present, we are truly
interested to simplify product-of-sums expression. Therefore,
form the 0s into groups. According to K-map as shown in
Fig. 4.48, this can be a group of two cells. The binary value
Fig. 4.47 Three variables K-map corresponding to the sum-term is (1, 1, X). In this case, both A
and B are 1 for the group although C is both 0 and 1. Therefore,
we can write an X as a place holder for C. Then we can write
– –
the sum-term (A + B) discarding the C and the X, which held
its’ place.
The procedure for writing the product-of-sums simplifica-
tion-using K-map
Step-1 Form largest groups of 0s possible, covering all
maxterms. Groups must be a power of 2.
Step-2 Write binary numeric value for group.
Fig. 4.48 Three variables K-map Step-3 Complement binary numeric value for group.
Step-4 Convert complement value to a sum-term.
Step-5 Repeat steps for other groups. Each group yields a sum-term within a product-of-sums
result.

Example 4.15 Simplify the product-of-sums Boolean expression using K-map

– – – – – – – – – – –
O = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)

� Solution
Firstly, transfer the six maxterms to the K-map as 0s. It is very clear from map that the ‘0’ entries in the map
covering minimum area. To find the proper cell location
in the K-map, it is required to complement the input
variables.
Once the cells are in proper place, form groups of
cells as shown in Fig. 4.49. Larger groups will give a
sum-term with fewer inputs. Fewer groups will yield
fewer sum-terms in the result.
We have two groups. Therefore, POS expression has
two sum-terms. The group of 4-cells yields a 2-variable
sum-term. The second group of 2-cells give us two 3-
variable sum-terms. The simplified function of the
Fig. 4.49 – –
Boolean expression is O = (A + C + D) (C + D). The
final result is product of the two sums.
 150 Digital Electronics: Principles and Applications

Example 4.16 Simplify the product-of-sums Boolean function as shown in K-map

� Solution
The minimal covering for the ‘0’ entries in the K-map is shown in Fig. 4.50(a). After grouping we get the
–
simplified expression is O = (C + D)A .

Fig. 4.50 Fig. 4.50 (a)

The first factor in the expression is form the grouping of entries in cells 2,6,10 and 14. The second factor is
form the grouping of entries in cells 0, 1, 2, 3, 4, 5, 6, 7.
Table 4.22 Truth table with don’t care state
4.14 DON’T CARES Inputs Output
We know that output of a function is depends on input A B C D O
0 0 0 0 0
variables. But in some cases, output does not matter on 0 0 0 1 1
combination of input variables. This is happened as input 0 0 1 0 1
combinations are invalid and the outputs corresponding 0 0 1 1 0
to these input combinations have no importance. These 0 1 0 0 0
0 1 0 1 0
types of input combinations are called, as don’t cares 0 1 1 0 1
and are shown in the truth Table 4.22. We use the symbol 0 1 1 1 1
‘X’ in a cell that can be either 1 or 0. The same notation 1 0 0 0 0
is also used in K-map. Figure 4.51 shows the Karnaugh 1 0 0 1 1
1 0 1 0 1
map with don’t care. Actually, don’t cares increase the
1 0 1 1 x
versatility of the 1 1 0 0 x
designer. In the K- 1 1 0 1 x
map, ‘X’ entries are 1 1 1 0 x
the don’t care entries. 1 1 1 1 x
It may be either 1 or
0. Always designer chooses the value, which will make the simplest
expression in both SOP and POS forms.

Fig. 4.51
 Combinational Logic 151

Example 4.17 Simplify the logic function F(A, B, C, D) = Sm (0, 1, 2, 5, 6, 8) + d(3, 4, 7, 14) using
K-map in SOP and POS form.

� Solution
(a) SOP Expression
The minimal covering for the 1 entries is shown in Fig. 4.52. We consider the don’t cares in cells 3, 4, 7, 14
as 1s and used in grouping of 1 entries.
– –– – –
The simplified SOP expression is F(A, B, C, D) = F1 + F2 + F3 = O = A + BCD + BCD.

Fig. 4.52
(b) POS Expression
The minimal covering for the 0 entries is shown in Fig. 4.53. We consider the don’t cares in cells 3, 4, 7, 14
as 0’s and used in grouping of 0 entries. The simplified POS expression is F(A, B, C, D) = F1. F2 . F3 . F4 = O
– – – – – – –
= (C + D) (A + C ) (A + D) (B + C + D)

Fig. 4.53
 152 Digital Electronics: Principles and Applications

Figure 4.54 and 4.55 show the logic diagram of SOP and POS solution respectively. Now, we can compare
between the product-of-sums solution and the sum-of-products solution. The SOP uses one three inputs OR
gate and two three input AND gate, while the POS uses three two inputs OR gates, one three inputs OR gate,
and one four input AND gate. For minimal cost solution, the SOP solution is simpler.

Fig. 4.54

Fig. 4.55

Example 4.18 Simplify the logic function F(A, B, C, D) = P (3, 5, 6, 11, 13, 14, 15) + d(4, 9, 10)
using K-Map in SOP and POS form.

� Solution
(a) SOP Expression
The minimal covering for the ‘1’ entries is shown in Fig. 4.56. We consider the don’t cares in cells 4,9,10 as
1s and used in grouping of ‘1’ entries. The simplified SOP expression is F(A, B, C, D) = F1 + F2 + F3 + F4 =
–– –– – ––– –
O = CD + A B C + A B D + A BCD.
 Combinational Logic 153

Fig. 4.56
(b) POS Expression
The minimal covering for the ‘0’ entries is shown
in Fig. 4.57. We consider the don’t cares in cells
4,9,10 as 0s and used in grouping of ‘0’ entries.
The simplified POS expression is F(A, B, C, D)
– –
= F1. F2 . F3 . F4 . F5 = O = (A + B + C)(B +
– – – – – – –
C + D) (B + C + D) (A + D) (A + C ). Three
– – –
different group expressions, (A + B + C), (A + D)
– –
and (A + C ) are depicted in Fig. 4.57. When two
–
adjacent cells 6 and 14 are grouped, we get (B +
–
C + D). Similarly, if two adjacent cells 3 and 11
– –
are grouped, we find (B + C + D).
Figure 4.58 and 4.59 show the logic diagram
Fig. 4.57
of SOP and POS solution respectively. Now, we

Fig. 4.58
 154 Digital Electronics: Principles and Applications

can compare between the product-of-sums solution and the sum-of-products solution. The SOP uses one four
inputs OR gate, one four inputs AND gate, two three inputs AND gate and one two inputs AND gate, while
the POS uses three three inputs OR gates, two two inputs OR gate, and one five input AND gate. Therefore,
the SOP solution becomes simpler.

Fig. 4.59

4.15 MINIMISATION OF SIMULTANEOUS FUNCTIONS

Figure 4.60 shows the block diagram of simultaneous function. It is a combinational logic circuit,
which has multi inputs and multi outputs. X is the set of input variables X0, X1, X2, … to Xn and Y is
the set of output variables F0, F1, F2 … Fn.
The combinational logic circuit operates on
the input variables X0, X1, X2, … to Xn and the
output variables F0, F1, F2 … Fn.
Here, the electronic circuit of combina-
tional logic shown as the black box has ‘n’
Fig. 4.60 Simultaneous functions different outputs F0, F1, F2 … Fn for the same
combination of inputs. Such circuits are called
as multiple output circuits and the functions corresponding to the outputs (F0, F1, F2, … Fn) are called
simultaneous functions. At this instant, the designer works on implementation of simultaneous functions
with minimum hardware. Actually the designer reduces the output functions to their minimal forms,
and then each output function will require minimum hardware. Though, there is a possibility of the
hardware duplicity as some output functions have similar terms. In that case, all common terms of the
output functions can be shared. Therefore, all common terms are detected and shared during hardware
implementation of simultaneous functions.
To minimise multioutput functions, essential prime implicants from the K-map of the product of 2
functions at a time, then 3 functions at a time etc. should be taken into account depending on the number
of functions.
 Combinational Logic 155

The example of simultaneous output function is given below:

Two simultaneous output function are F1(A, B, C, D) = Sm(0, 1, 2, 3, 4) and F2(A, B, C, D) = Sm
(1, 2, 3, 7, 14, 15). Figure 4.61 and 4.62 show the Karnaugh map for F1(A, B, C, D) = Sm (0, 1, 2, 3, 4)
and F2(A, B, C, D) = Sm (1, 2, 3, 7, 14, 15) respectively. The functions F1 and F2 can be reduced to SOP
–– ––– –– – ––
forms using Karnaugh maps as F1 = A B + A C D and F2 = A B D + A B C + BCD + ABC

Fig. 4.61 Karnaugh map for F1 Fig. 4.62 Karnaugh map for F2

From the minimal expressions F1 and F2, we can say

that two functions F1 and F2 should be implemented Table 4.23 The shared term
independently as there is no common term between F1 F1 F2 F1.F2
and F2. Luckily, the function F1 can also be expressed by 1 0 0
one more minimal expression as given below:
1 1 1
– –– –– –––
F1 (A, B, C, D) = A B C + A B C + A C D 1 1 1
In this minimal expression of F1, it is very clear that 1 1 1
there is a common expression in F1 and F2. During 1 0 0
implementation of F1 and F2, the common term will 0 0 0
be shared. In this way, the designer always find out 0 0 0
the common terms and able to design in most simple 0 1 0
way. There are different methods to detect the sharing
0 0 0
possibilities.
0 0 0
The most common method is the construction of a
0 0 0
map in which each output minterm F1 and F2 is AND
0 0 0
operated with the corresponding minterms and the results
placed on the third map. The third map represents all the 0 0 0
minterms, which are common to the F1 and F2 functions. 0 0 0
This shared term K-map be able to draw using Table 0 1 0
4.23. 0 1 0
 156 Digital Electronics: Principles and Applications

Example 4.19 Simplify the following simultaneous equations

F1(A, B, C, D) = Σm(1, 2, 3, 4) and
F2(A, B, C, D) = Σm (1, 2, 3, 7).

� Solution
The K-maps for F1, F2 and F1.F2 are depicted in Fig. 4.63(a), (b) and (c) respectively.

Fig. 4.63 (a) Karnaugh map for F1 Fig. 4.63 (b) Karnaugh map for F2

It is very clear from K-map of F1.F2, the following terms:

–– ––
A B D and A B C are common to both F1 and F2 . Therefore, during
deriving the minimal expressions of F1 and F2, these common
terms are included as far as possible. The sub cubes of F1 and F2
are shown in Fig. 4.63. Then output functions for F1 and F2 are
given below:
–– –– – ––
F1= A B D + A B C + A BCD
–– –– –
F2= A B D + A B C + A CD
Unfortunately, the other common term could not be retained
in the minimal expressions for F1 and F2 because if we would
Fig. 4.63 (c) Karnaugh map for F1.F2 have tried to retain, the functions would not been minimal.
The incompletely specified (with don’t cares) multiple output
functions (simultaneous functions) can also be solved by the above method. However, solving of more than
two incompletely specified functions becomes difficult.

Example 4.20 Simplify the following simultaneous equations

F1(A, B, C, D) = Σm(1, 2, 3, 4) + d(10, 11, 12) and
F2(A, B, C, D) = Σm (1, 2, 3, 7) + d(8, 9, 10)
 Combinational Logic 157

� Solution
The K-maps for F1, F2 and F1.F2 are depicted in Fig. 4.64(a), (b) and (c) respectively.

Fig. 4.64 (a) Karnaugh map for F1 Fig. 4.64 (b) Karnaugh map for F2
Table 4.24 The shared term

F1 F2 F1.F2
0 0 0
1 1 1
1 1 1
1 1 1
1 0 0
0 0 0
0 0 0
0 1 0
0 X 0
Fig. 4.64 (c) Karnaugh map for F1.F2
0 X 0
X X X
The K-map for F1.F2 is drawn based on the Table X 0 0
4.24 with shared terms. From the shared K-map of X 0 0
–– ––
F1.F2, the following common terms: A B D and A B C
0 0 0
are obtained. When we write the function for F1 and
F2, we have to keep in mind to include all common 0 0 0
terms. The output functions are written as 0 0 0
–– –– ––
F1= A B D + A B C + BCD
–– –– –
F2= A B D + A B C + A CD

4.16 VARIABLE MAPPING

Variable mapping is a technique, which is used to achieve the minimal expression of the output function
for large number of variables without K-map. Consider the Boolean expression
 158 Digital Electronics: Principles and Applications

–– – –– – – –
F(ABCK) = A B C + A B C + A BC + A BC + ABCK.
The above Boolean expression is a function of four variables A, B, C, and K. Hence a four variables
K-map can be used for reducing the function. But we interested to represent the said function using three
variables K-map. Therefore the above function can be mapped into three variables K-map as shown in
Fig. 4.65 which is based on Table 4.25.

Table 4.25 Represent cell value and cell No.

Cell Value Cell No.

–– –
A BC 0
––
ABC 1
– –
A BC 2
–
A BC 3
––
AB C 4
–
AB C 5
–
ABC 6
Fig. 4.65 Three variable K-map
ABC 7

From the K-map as shown in Fig. 4.65, we find a 2 cell sub cube F1 and a 4 cell sub cube F2. Then
the minimal expression is
–
F(ABCD) = K. F1 + F2 where F1 = BC and F2 = A
– –
= K. BC + A = A + K. BC

Example 4.21 Simplify the following expression

–– – – – – ––
ABC D + ABC D + ABCD + A BCD + A B CD + ABCD

� Solution
The three variables K-Map of the Boolean function
–– – – – – ––
ABC D + ABC D + ABCD + A BCD + A B CD +
ABCD is shown in Fig. 4.66 and selection of the
subcubes are also indicated in the same figure.
The simplified from of this Boolean function is as
follows
–– – – – – ––
ABC D + ABC D + ABCD + A BCD + A B CD +
ABCD
– – – – ––
= ABC (D + D) + ABC(D + D) + A (B Fig. 4.66 Three variable K-map of ABC D +
– – – – – – – – –
+ B )CD (As D + D = B + B = 1) ABC D + ABCD + A BCD + A B CD + ABCD
– – – – – –
= ABC + ABC + A CD = AB(C + C) + A CD = AB + A CD ( As C + C = 1)
The minimal expression from K-map is
– –
F(ABCD) = F1 + F2 = AB + A CD where F1 = AB and F2 = A CD
 Combinational Logic 159

4.17 TABULAR METHOD OF MINIMISATION

The graphical method or Karnaugh map method is very convenient to obtain the minimal expression
of a Boolean function relating with 3 or 4 variables only. But the difficulty arises with increasing the
number of variables. When the number of variables increases, the visualisation of adjacent cells of the
Karnaugh maps is very difficult. Although, Karnaugh map method can also be used for 5 to 6 variables
function.
To overcome the visualisation difficulty, the tabular method is used for minimisation of a Boolean
function of any number of variables. W.V.Quine and E.J.Mc Clusky developed the tabular method of
minimisation and this method is known as Quine Mc Clusky method of minimisation.
The tabular method depends upon combining adjacent cells. The procedure is in combining two
adjacent cells, four adjacent cells and eight adjacent cells combination. This procedure is also applicable
to search out combinations as big as possible. So a designer can develop a logic function using tabular
method. Some definitions related with the Quine McClusky method of minimisation are discussed
below:

Implicant
An implicant is a simplified expression and can be obtained after combining the adjacent minterms
of the set of minterms. There are two types implicants, namely, Prime implicants and Essential prime
implicants. Prime implicant is an implicant when it is not a subset of another implicant of the function.
A Prime implicants is called as essential prime implicants if it includes a cell, which is not incorporated
in any other prime implicant.
The logical function is
––– –– – – – – – – –
F(ABCD) = AB C D + AB C D + AB CD + AB CD + A BC D + A BCD + ABCD + ABCD and the K-map
for this function is shown in Fig. 4.67. The logical expression of the said function is F (A, B, C, D) = F1
– –
+ F2 + F3 + F4 , where F1 = AB , F2 = A BD, F3 = BCD and F4 = AC. Here F1, F2, F3, and F4 are the prime
implicants of the function F(ABCD). In this example, prime implicant F3 is not essential.

Minimal SOP Form

The minimal SOP form representation of a Boolean
function is that the prime implicants can covered all 1’s
in the Karnaugh map. When we want to choice one prime
implicant from the two prime implicants, the simplest
one should be selected. The set of prime implicants of the
Karnaugh map as shown in Fig. 4.67 are F1, F2, F3, and F4.
All prime implicants are unnecessary to represent function
and some prime implicants are eliminated. The minimal
function is now the sum of these selected prime implicants.
Therefore, the procedure results in a minimal SOP form.
But the minimal SOP expression is F(ABCD) = F1 + F2 +
F3 + F4. The same method can be used for POS form using
Fig. 4.67
maxterms. The procedure of Quine McClusky Method is
given below:
 160 Digital Electronics: Principles and Applications

Step 1
i. Represent each minterms of the Standard SOP form of logic function by a binary code and its
decimal equivalent.
ii. Form the groups containing the number of 1s in the binary code. Each group should have specified
group number known as index number. In group-0 of minterms, number of 1’s is zero; in group
1 minterms have a single 1; in group-2, minterms have two 1’s; in group-3, minterms have three
1s; and in group-4, minterms have four 1s. Arrange all the minterms according to groups with
ascending order of decimal number. For example, Table 4.26 shows the minterms with number
of 1’s in binary code, group and variables.

Step 2
–
iii. Apply the theorem, A + A = 1 in two minterms from adjacent groups. Here, two minterms are
combined together if their binary representations differ by just a single bit. The combined term
consists of the original binary representation, with the difference bit replaced by (–). Table 4.27
shows the combination of two minterms. The check mark (÷) is placed just after the each minterm,
which has been combined with at least one term as depicted in Table 4.26.

Step 3
iv. Four minterms of adjacent groups are combined if possibilities exist. In this case, dashes (–) ex-
ist in same position of two groups and only one position will be different. Table 4.28 shows the
combination of four minterms.
v. Combine eight minterms of adjacent groups if possibilities exist. For this case, position of two
dashes (–) will be same and only one position will be different.

Step 4
vi. Construct the table of prime implicants in which each column has a decimal number at the top
in ascending order which corresponds to the minterms in the standard SOP form and each row
represents the prime implicant.
vii. Use a trick mark (÷) under each decimal number, which means the particular minterm is contained
in the prime implicants represented by the row.
viii. Find out all the columns, which contain a single trick mark (÷) and give a star mark (*) at the left
of the rows. The star marked rows are called essential prime implicants.
ix. Derive the minimal SOP logic function incorporating all essential prime implicants.
x. Find out all prime implicants, which covers the maximum number of minterms and also include
the prime implicants in the minimal SOP logic function.

The examples of Quine-McClusky procedure are given below.

Example 4.22 Simplify the Boolean function F = Sm (0, 1, 2, 7, 8, 9, 10, 11, 14, 15)
using Quine McClusky method.
 Combinational Logic 161

� Solution
Step-1
The highest minterm is 15; therefore the function is a four variables function. Initially, the table is created
representing all minterms, group and variables of the function. All the minterms are arranged ascending
order considering numbers of 1’s in binary representation of minterms as shown in Table 4.26.

Table 4.26

No. of 1’s Group Minterms Variables

A B C D
0 0 0 ÷ 0 0 0 0
1 I 1 ÷ 0 0 0 1
2 ÷ 0 0 1 0
8 ÷ 1 0 0 0
2 II 9 ÷ 1 0 0 1
10 ÷ 1 0 1 0
3 III 7 ÷ 0 1 1 1
11 ÷ 1 0 1 1
14 ÷ 1 1 1 0
4 IV 15 ÷ 1 1 1 1

Step-2
The combinations of two minterms are shown in Table 4.27. The minterms, which are combined with other
minterms, are tick (÷) marked in the Table 4.26. After the combinations of two minterms, the results consist
of the original binary representation with different bit placed by ‘–’ as depicted in Table 4.27.

Table 4.27 The combinations of two minterms

Combination Binary Code

A B C D
0,1 ÷ 0 0 0 -
0,2 0 0 - 0
0,8 ÷ - 0 0 0
1,9 ÷ - 0 0 1
2,10 - 0 1 0
8,9 ÷ 1 0 0 -
8,10 ÷ 1 0 - 0
9,11 ÷ 1 0 - 1
10,14 ÷ 1 - 1 0
7,15 - 1 1 1
11,15 ÷ 1 - 1 1
14,15 ÷ 1 1 1 -
 162 Digital Electronics: Principles and Applications

Step-3
Table 4.28 shows the possible combinations of four minterms. In four minterms, combination, two different
combinations of two minterms are combined. Give the tick marked in Table 4.27 for two combinational
minterms that are covered in combinations of four minterms. Some terms of Table 4.27 are not tick marked
and these non-tick marked terms are known as prime implicants.

Table 4.28 The combinations of four minterms

Combination Binary Code

A B C D
0,1,8,9 - 0 0 -
8,9,10,11 1 0 - -
10,11,14,15 1 - 1 -

Step-4
The table of prime implicants is constructed for finding out the essential implicants. Table 4.29 shows the
table of prime implicants.

Table 4.29 Table of Prime Implicants

Prime Implicants Minterms

0 1 2 7 8 9 10 11 14 15
0,1 ÷ ÷
1,9 ÷ ÷
2,10* ÷ ÷
8,9 ÷ ÷
7,15* ÷ ÷
14,15 ÷ ÷
0,1,8,9* ÷ ÷ ÷ ÷
8,9,10,11* ÷ ÷ ÷ ÷
10,11,14,15* ÷ ÷ ÷ ÷

To select the essential prime implicants, Table 4.29 is scanned all minterms in column wise. All the minterms,
which have only one tick mark, contribute one essential prime implicants. In this table minterms 2, and 7
are essential prime implicants and put star (*) on these prime implicants. Then prime implicants are to be
selected for the remaining minterms. The procedure is that select prime minterms, which cover maximum
number of unaccounted minterms. There are three prime implicants which take care of these minterms are
(0, 1, 8, 9); (8, 9, 10, 11) and (10, 11, 14, 15). Again put star marks at the proper places. The essential prime
implicants are selected the star marked terms from Table. Hence the minimal form of the logic function is
–– – – –
F = B C + AB + AC + BCD + B CD
 Combinational Logic 163

Step-5
The result can be verified by the help of Karnaugh map, Fig. 4.68. The simplified expression is F = F1 + F2 +
–– – – – –– – – –
F3 + F4 + F5 = B C + AB + AC + BCD + B CD, where F1 = B C, F2 = AB , F3 = AC, F4 = BCD and F5 = B CD.

Fig. 4.68 Karnaugh map for F

Example 4.23 Simplify the function F = S(0, 1, 2, 3, 5, 9, 11) +d (4, 7, 15) using Quine Mclusky
method and verify the result by Karnaugh map.

� Solution
It is clear from the logic function that the highest minterm is 15. So, the function is a four variable function.
This logic function has three don’t care entries. To derive the logic expression the procedure is same, but the
last step is different one. In the last step the essential prime implicants are selected for compulsory terms.

Step-1
Initially, the table is created representing all minterms and variables of the function. All the minterms are arranged
increasing order considering numbers of 1’s in binary representation of minterms as given in Table 4.30.

Table 4.30
No. of 1’s Group Minterms Variables
A B C D
0 0 0 ÷ 0 0 0 0
1 I 1 ÷ 0 0 0 1
2 ÷ 0 0 1 0
4 ÷ 0 1 0 0
2 II 3 ÷ 0 0 1 1
5 ÷ 0 1 0 1
9 ÷ 1 0 0 1
3 III 7 ÷ 0 1 1 1
11 ÷ 1 0 1 1
4 IV 15 ÷ 1 1 1 1
 164 Digital Electronics: Principles and Applications

Step-2
Table 4.31 shows the all-possible two minterms combinations. The result of combinations of two minterms
consists of the original binary representation with different bit placed by ‘–’ as depicted in the same table.
The minterms, which are combined with other minterms, are tick marked in the Table 4.30.

Table 4.31 Combinations of two minterms

Combination Binary Code

A B C D
0,1 ÷ 0 0 0 -
0,2 ÷ 0 0 - 0
0,4 ÷ 0 - 0 0
1,3 ÷ 0 0 - 1
1,5 ÷ 0 - 0 1
1,9 ÷ - 0 0 1
2,3 ÷ 0 0 1 -
4,5 ÷ 0 1 0 1
3,11 ÷ - 0 1 1
3,7 ÷ 0 - 1 1
5,7 ÷ 0 1 - 1
9,11 ÷ 1 0 - 1
11,15 ÷ 1 - 1 1
7,15 ÷ - 1 1 1

Step-3
Table 4.32 gives possible combinations of four minterms. There is no possibility of combinations of eight
minterms.

Table 4.32 Combinations of four minterms

Combination Binary Code

A B C D
0,1,2,3 0 0 - -
0,1,4,5 0 - 0 -
1,5,3,7 0 - - 1
1,3,9,11 - 0 - 1
3,7,11,15 - - 1 1

Step-4
Table 4.33 is constructed to find out the essential implicants.
 Combinational Logic 165

Table 4.33 Table of prime implicants

Prime Minterms
Implicants 0 1 2 3 5 9 11
0,1, 2,3* ÷ ÷ ÷ ÷
0,1,4,5* ÷ ÷ ÷
0,1,5,7 ÷ ÷ ÷
1,3,9,11* ÷ ÷ ÷ ÷
3,7,11,15 ÷ ÷
9,11 ÷ ÷
11,15 ÷

The procedure of selection prime minterms is to cover maximum number of minterms. There are three prime
implicants (1, 3, 9, 11); (0, 1, 2, 3) and (0, 1, 4, 5) which cover all compulsory minterms (0, 1, 2, 3, 5, 9, 11).
Then put star marks at the proper places of the three prime implicants. Hence the minimal form of the logic
function is
–– – ––
F = AB + BD + A C

Step - 5
The result can be verified by the help of Karnaugh map, Fig. 4.69. The simplified expression is F = F1 + F2
–– – –– –– – ––
+ F3 = A B + B D + A C , where F1 = A B , F2 = B D and = F3 = A C .

Fig. 4.69 Karnaugh map for F

 166 Digital Electronics: Principles and Applications

Example 4.24 Simplify the function F = S(1, 2, 3, 6, 7, 8, 10, 11, 12, 14, 17, 18, 20, 21, 22, 24, 28,
29, 31) using Quine Mclusky method

� Solution
In the logic function, the highest minterm is 31. Therefore, the logic function is a five variables function. To
derive the logic expression, the procedure is same as given below:

Step-1
Initially, the table is created representing all minterms and variables of the function. All the minterms are
arranged increasing order considering numbers of 1’s in binary representation of minterms as illustrated in
Table 4.34.

Table 4.34

No. of Group Minterms Variables

1’s A B C D E
1 I 1 ÷ 0 0 0 0 1
2 ÷ 0 0 0 1 0
8 ÷ 0 1 0 0 0
2 II 3 ÷ 0 0 0 1 1
6 ÷ 0 0 1 1 0
10 ÷ 0 1 0 1 0
12 ÷ 0 1 1 0 0
17 ÷ 1 0 0 0 1
18 ÷ 1 0 0 1 0
20 ÷ 1 0 1 0 0
24 ÷ 1 1 0 0 0
3 III 7 ÷ 0 0 1 1 1
11 ÷ 0 1 0 1 1
14 ÷ 0 1 1 1 0
21 ÷ 1 0 1 0 1
22 ÷ 1 0 1 1 0
28 ÷ 1 1 1 0 0
4 IV 29 ÷ 1 1 1 0 1
4 IV 31 ÷ 1 1 1

Step-2
Table 4.35 shows the combinations of two minterms. The minterms, which are combined with other minterms,
are tick marked in the Table 4.34.
 Combinational Logic 167

Table 4.35 Combinations of two minterms

Combinations Binary Code

A B C D E
1,3 0 0 0 - 1
2,3 ÷ 0 0 0 1 -
2,6 ÷ 0 0 - 1 0
3,7 ÷ 0 0 - 1 1
8,10 0 1 0 - 0
8,12 ÷ 0 1 - 0 0
10,11 0 1 0 1 -
10,14 ÷ 0 1 - 1 0
18,22 ÷ 1 0 - 1 0
20,21 ÷ 1 0 1 0 -
20,22 1 0 1 - 0
24,28 ÷ 1 1 - 0 0
28,29 ÷ 1 1 1 0 -
29,31 1 1 1 - 1
1,17 - 0 0 0 1
8,24 ÷ - 1 0 0 0
12,28 ÷ - 1 1 0 0
2,18 ÷ - 0 0 1 0
6,22 ÷ - 0 1 1 0

Step-3
All possible combinations of four minterms are shown in Table 4.36. There is no possibility of an eight-cell
combination.

Table 4.36 Combinations of four minterms

Combinations Binary Code

A B C D E
2,3,6,7 0 0 - 1 -
2,6,10,14 0 - - 1 0
8,10,12,14 0 1 - - 0
20,21,28,29 1 - 1 0 -
8,12,24,28 - 1 - 0 0
2,6,18,22 - 0 - 1 0

Step-4
To choose the essential implicant Table 4.37 is constructed
 168 Digital Electronics: Principles and Applications

Table 4.37 Table of prime implicants

Prime Minterms
Implicants 1 2 3 6 7 8 10 11 12 14 17 18 20 21 22 24 28 29 31
2,3,6,7* ÷ ÷ ÷ ÷

2,6,10,14* ÷ ÷ ÷
÷
8,10,12,14 ÷ ÷ ÷ ÷
20,21,28,29* ÷ ÷ ÷ ÷
8,12,24,28* ÷ ÷ ÷ ÷
2,6,18,22* ÷ ÷ ÷ ÷
1,17* ÷ ÷
10,11* ÷ ÷
29,31* ÷ ÷
In this table, minterms 1, 11, 17, and 31 are essential prime implicants and put star (*) on these prime
implicants. Then prime implicants are also be selected for the remaining minterms. The procedure is that
select prime minterms, which cover maximum number of unaccounted minterms. There are five prime
implicants which take care of these minterms are (2, 3, 6, 7), (2, 6, 18, 22), (2, 6, 10, 14), (8, 12, 24, 28) and
(20, 21, 28, 29). Then put star marks at the proper places. The essential prime implicants are selected from
the star marked terms of the Table 4.37. Hence, the minimal form of the logic function is
––– – – –– – – – – – ––
F = B C DE + A BC D + ABCE + A B D + B DE + A DE + ACD + BD E

SUMMARY
In this chapter, the basic combinational logic function and its element are discussed. The circuit development of
combinational logic function is explained. The logic circuit can be designed by the Canonical sum of product (SOP)
and Canonical product of sum (POS) methods. The Canonical sum of products (SOP) represent in AND – OR circuit
but Canonical product of sums (POS) can be represented in OR – AND circuit. The sum of product and product of
sum expressions of any truth table have been explained. These SOP and POS expressions can be simplified by using
Boolean algebra as designer select the simplest circuit for low cost and high reliability. To design a most simplified
logic circuit using Boolean algebra is a tedious work. The Karnaugh method is substitute of logic simplification by
converting a truth table into a Karnaugh map. The greatest simplified Boolean expression of a truth table is possible
in this case. Sum of product form and product of sum expressions of a truth able using Karnaugh map are possible.
Three, four, five and six variables Karnaugh maps are illustrated in this chapter. It is very inconvenient to use Karnaugh
map to simplify logic function if number of variables are more than six. Then Quine-McCluskey method used for
large number of variables and this method has been explained with examples. The simultaneous functions are also
incorporated in this chapter.

MULTIPLE CHOICE QUESTIONS

1. A Karnaugh map is used for
(a) Minimising Boolean expressions (c) Develop digital circuits
(b) Computer interface (d) None of these
2. Which of the following could be used to detect a potential static hazard when designing a combina-
tional logic circuit?
(a) Karnaugh map (b) Truth table (c) State table (d) None of these
 Combinational Logic 169

3. In addition to minimising logic expressions, a Karnaugh map can also be used for
(a) Static hazard detection (c) Synchronous circuit design
(b) Sequential logic circuit design (d) None of these
4. A four variables Karnaugh map contains
(a) 4 cells (b) 8 cells (c) 16 cells (d) 32 cells
5. A five variable Karnaugh map contains
(a) 4 cells (b) 8 cells (c) 16 cells (d) 32 cells
6. Quine McCluskey method uses
(a) Tabular Method (b) Karnaugh map (c) Boolean Algebra (d) None of these
7. AND –OR realisation is equivalent to
(a) SOP (b) POS (c) K-map (d) None of these
8. OR - AND realisation is equivalent to
(a) SOP (b) POS (c) K-map (d) None of these
9. What is the simplified Boolean expression for K-map (Fig.4.70) in SOP?

Fig. 4.70
–
(a) AB (b) BC (c) A C (d) None of these
10. What is the simplified Boolean expression for K-map (Fig.4.70) in POS?
– –
(a) B + C (b) A + C (c) C(A + B) (d) None of these
11. The minimisation of logic expression is done due to
(a) Reduce space (c) Reduce number of gates
(b) Reduce cost (d) All of these
– –– –
12. The simplified form of logic expression AB + A B + A B + AB is
(a) 1 (b) A (c) AB (d) None of these
– – – –
13. The simplified form of logic expression A BC + ABC + A BC + ABC is
(a) B (b) A + BC (c) C (d) None of these

REVIEW QUESTIONS
4.1. Define SOP and POS. What is the difference between SOP and POS?
4.2. Write the standard SOP form for the following logic functions given below:
–– – ––– –– – –
a) AB + BC b) C D + A B c) A B C + ABCD + BC d) A B D + A D + B D
4.3. Write the standard POS form for the following logic functions given below:
– – – –
a) (A + B) (B + C) (c) (A + B + C) (B + C + D) (B + C )
– – – – – – – – – –
b) (A + B+ C) (A + B + D) (B + C) d) (A + C + D) (B + C + D) (A + C )
 170 Digital Electronics: Principles and Applications

4.4 Determine Boolean function of the truth table 4.38 in terms of minterms and draw logic diagram
using NAND gate.
Table 4.38
Inputs Output
A B C D O
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1

4.5. Determine Boolean function of Table 4.39 in terms of maxterms and draw logic diagram using
NOR gate.
Table 4.39
Inputs Output
A B C O
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0

4.6. Make truth table for the following logic functions:

a) F1(A, B, C, D) = Sm(0, 1, 2, 3, 5, 7, 11, 15)
b) F1(A, B, C, D) = Sm(1, 3, 5, 11, 15) + d(0, 1, 4, 7)
c) F1(A, B, C, D) = P( 2, 3, 5, 6, 13, 14)
d) F1(A, B, C, D) = P( 5, 6, 11,12,13, 14) + d(7,15)
4.7. Simplify the following logic expression using Boolean algebra:
(a) F1(ABCD) = Sm(0, 2, 3, 4, 8, 9, 11, 15)
(b) F1(ABCD) = Sm(1, 3, 5, 8, 9, 11, 15) + d( 7, 13)
(c) F1(ABCD) = P( 2, 4, 10, 12, 13, 14)
(d) F1(ABCD) = P( 1, 2, 6, 7,13, 14, 15) +d(0, 3, 5)
4.8. Explain the two, three and four variables K-map and their applications to reduce logic functions
with examples.
 Combinational Logic 171

4.9. What are the advantages of K-map method reduction?

4.10. Draw the Karnaugh map for the following logic functions:
(a) F1(A, B, C, D) = Sm( 1, 2, 3, 5, 11, 15)
(b) F1(A, B, C, D) = Sm(1, 5, 9, 11, 13, 15) + d(3, 7)
(c) F1(A, B, C, D) = P( 0, 2, 3, 4, 5, 6, 13, 14)
(d) F1(A, B, C, D) = P( 0, 4,6, 11,12,13) + d(7, 14, 15)
4.11. Make a Karnaugh map of the following functions and derive the expression in SOP form:
(a) F1(A, B, C, D) = Sm(0, 1, 2, 4, 5, 6, 13, 15)
(b) F1(A, B, C, D) = Sm( 5, 8, 9, 11, 13,15) + d( 7,12)
(c) F1(A, B, C, D) = P( 2, 3, 5, 6, 10, 11, 13, 15)
(d) F1(A, B, C, D) = P( 1,5, 8, 9, 10,11 ) + d(0,4)
4.12. Make a Karnaugh map of the following functions and derive the expression in POS form:
a) F1(A, B, C, D) = Sm(0, 2,3, 4, 8, 9, 10, 11, 13, 15)
b) F1(A, B, C, D) = Sm( 5, 8, 9, 11, 12, 13,15) + d( 0, 1, 3, 7)
c) F1(A, B, C, D) = P( 0, 1, 2, 3, 5, 6, 10, 11, 13, 15)
d) F1(A, B, C, D) = P( 0, 1,5, 8, 9, 10,11 ) + d(2,4)
4.13. What are simultaneous functions? Why simultaneous functions are used in digital systems?.
4.14. Minimise the following simultaneous functions:
(a) F1 (A, B, C, D) = Sm(0, 2,3, 4, 8, 9, 10, 11, 13, 15)
F2 (A, B, C, D) = Sm(5, 8, 9, 11, 12, 13,15) + d( 0, 1, 3, 7)
(b) F1 (A, B, C, D) = P(0, 1, 2, 3, 5, 6, 10, 11, 13, 15)
F2 (A, B, C, D) = P(0, 1,5, 8, 9, 10, 11 ) + d(2,4)
(c) F1 (A, B, C, D) = Sm(1, 2, 3, 5, 11, 15)
F2 (A, B, C, D) = Sm(1, 5, 9, 11, 13, 15) + d(3, 7)
d) F1 (A, B, C, D) = P( 0, 1, 2, 3, 5, 6, 10, 11, 13, 15)
F2 (A, B, C, D) = P( 0, 1,5, 8, 9, 10,11 ) + d(2,4)
4.15. Explain variable mapping with examples.
4.16. Simplify the following expressions using variable map:
– –– – – – – – –
(a) AB D + A BC + ABD + A BC (c) (A + B + D ) (A + B + D) (A + B + C)
– –– –– – – –
(b) ABC + ABD + C D + ABC D (d) D(A + B + C) (A + B + C)
4.17. What are the advantages of Tabular method over K-map method in minimisation of logic
functions?
4.18. Minimise the following functions using Quine-McClusky tabular method:
(a) F1(A, B, C, D) = Sm( 1, 2, 3, 5, 11, 15)
(b) F1 (A, B, C, D) = Sm(5, 8, 9, 11, 12, 13,15) + d( 0, 1, 3, 7)
(c) F1 (A, B, C, D) = Sm(1,2, 3, 4, 5,6, 7, 10, 11, 15, 18, 19, 20, 21, 22, 23, 25, 26, 27)
(d) F1 (A, B, C, D) = Sm(1, 2, 3, 5,6, 10, 11, 15, 18, 19, 20, 21, 22, 23, 25, 26, 27, 31) + d(4, 7, 30)
 CHAPTER

5
COMBINATIONAL
LOGIC DESIGN
5.1 INTRODUCTION
The general logic gates AND, OR, NAND, NOR and NOT are commonly used in combinational logic
circuit design using Karnaugh map and Quine-Mc Cluskey minimisation method. But practically, NOR
and NAND universal gates are used to implement combinational logic circuits. Small-Scale Integration
(SSI) circuits are available to implement logic circuits. As medium and large-scale integrated circuits
are introduced, the conventional logic circuits designs have been changed. Traditionally, the design
engineer has developed a Boolean equation to solve a particular problem. Then this function has been
minimised and implemented using SSI ICs. If combinational logic circuits may have a large number of
inputs and outputs, the use of truth tables in the design of such circuits is impractical. Furthermore, it is
not economical to provide sufficient pins on an IC package to allow access to each of the gates. Many
functions, such as counting, addition, parity checking are common in a large number of designs and a
useful library of digital circuits for implementing these functions has been developed. As a fabrication
techniques improved day-by-day, it became possible to implement these functions on a single chip. There
is an array of devices, such as multiplexers, demultiplexers, adders, parity generators and checkers,
decoders, and comparators. These devices significantly reduce the number of ICs and the system cost.
Therefore, the system design becomes simplified. This improves the reliability of the system by reducing
of external wired connections.
The development of MSI circuits has led to the technique of splitting complex design into a number
of sub-systems. The designer has the task of interconnecting available MSI circuits in such a way that
satisfies the design specification.
5.2 COMBINATIONAL LOGIC DESIGN
In the combinational logic circuit design process, the logic designer
initially defines the input variables for representing all conditions.
The system may be single output or multi-outputs. Consequently, the
designer must assign the output variables. After assigning the input
variables and output variables, the designer writes the truth table to
represent all combinations of input and output variables. The designer
builds up the Boolean expressions in canonical sum of product (SOP) or
Fig. 5.1 Block diagram of a canonical product of sum (POS) form. The written Boolean expression
combinational logic circuit may be or may not be minimised form. Therefore, the equations should
 Combinational Logic Design 173

be expressed in the minimum SOP and POS form. Finally, the designer implement the logic expressions
by electronics circuits, namely AND, NAND, OR, NOR and NOT gates; MSI chips explicitly decoders,
encoders, multiplexers and demultiplexers. Figure 5.1 shows the block diagram of a typical combinational
logic circuit with three inputs A0 , A1 , A2 and one output O.

Example 5.1 Design a full-adder circuit using gates.

� Solution
Step - 1: The block diagram of full-adder is shown in Fig. 5.2.
The two inputs A and B will be added with the carry from
previous stage CIN. Therefore, three input variables A, B and CIN
are considered for combinational logic circuit. There are two
outputs sum(S) and carry output (COUT).
Step - 2: The truth table of full adder is shown in Table 5.1 Fig. 5.2 Block diagram of full
adder circuit design
Table 5.1 Truth table of full adder
Inputs Outputs
CIN B A S COUT
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Step - 3: The outputs S and COUT can be expressed in SOP and POS form respectively as given below:
S = F(A, B, CIN) = S(1, 2, 4, 7) = ’(0, 3, 5, 6)
COUT = F(A, B, CIN)=Σ(3, 5, 6, 7) = ’(0, 1, 2, 4)
The above Boolean expressions can be minimised by using K-map. Figure 5.3 shows the K-map for sum(S)
COUT).

Fig. 5.3 K-map for sum (S) Fig. 5.4 K-map for carry output (COUT)
– – —— – –
S = F(A, B, CIN) = CIN A B + CIN AB + CIN AB + CIN AB
–– – – –
= CIN (AB + A B ) + CIN (A B + AB )
——— –
= CIN (A ≈ B ) + CIN (A ≈ B) = C ≈ B ≈ A
COUT = F(A, B, CIN) = AB + CINB + CINA
Step - 4 : Implementation of the circuit using logic gates. Figure 5.5 shows the implementation of full adder
using EX-OR, AND and OR gates.
 174 Digital Electronics: Principles and Applications

Fig. 5.5 Implementation of full Fig. 5.6 Block diagram of 2 line to

adder using gates 4 line decoder
5.3 DECODERS
Decoder is a combinational logic circuit which has ‘n’ inputs and one output out of 2n outputs. For
example, if there are two inputs, the decoder asserts one of the four outputs depending upon inputs.
Figure 5.6 shows the block diagram of 2 to 4 line decoder. Here, A and B are two inputs and E stands for
chip enable. O0, O1, O2 and O3 are the outputs of decoder.

5.3.1 2:4 Decoder

The structure of 2 to 4 line decoder is depicted
in Fig. 5.7. Four NAND gates are used for this
decoder. If the input is 00 (A=0 and B=0), output
O0 will be asserted; if input is 01(A=0 and B=1),
output O1 will be asserted and so on. Table 5.2
shows the truth table of 2:4 decoder. For any
combination of inputs, only one output will be low
and other outputs will be high. Therefore, decoder
selects only one output at a time. Similarly, 3:8,
Fig. 5.7 Basic structure of a 2 to 4 line decoder
4:16 and 5:32 decoder can be made using logic
gates and also in terms of ICs.
5.3.2 3:8 Decoder
The IC 74138 is 3 to 8 line decoder. When this IC is enable, the selected output then depends upon the
input combination of A, B and C. For example, when
Table 5.2 Truth table of 2 to 4 line decoder
C=0 and B=A=1, output O6=0 and all the other outputs
Inputs Outputs are 1 as depicted in Table 5.3. Table 5.4 can also be
E A B O0 O1 O2 O3 used as 3:8 decoder, if the output O6=1 and all the other
0 0 0 0 1 1 1 outputs are 0 for the same input combination C=0 and
0 0 1 1 0 1 1 B=A=1. The equations for each output of the decoder
0 1 0 1 1 0 1
0 1 1 1 1 1 0
can be represented by minterms and maxterms. The
1 x x 1 1 1 1 truth tables of 3:8 decoder for minterm and maxterm
representation are shown in Table 5.5 and Table 5.6
respectively. The structure of 3 to 8 line decoder using NAND is depicted in Fig. 5.8. Eight NAND gates
are used for this decoder. If the input is 001, output O1 will be asserted. Similarly, if input is 101, output O5
will be asserted and so on. The implementation 3 to 8 line decoder using AND is given in Fig. 5.9.
 Combinational Logic Design 175

Fig. 5.8 3 line to 8 line decoder Fig. 5.9 3 line to 8 line decod-
using NAND gates er using AND gates

Table 5.3 Truth table of 3 to 8 line decoder using NAND gates

Inputs Outputs
A B C O0 O1 O2 O3 O4 O5 O6 O7
0 0 0 0 1 1 1 1 1 1 1
0 0 1 1 0 1 1 1 1 1 1
0 1 0 1 1 0 1 1 1 1 1
0 1 1 1 1 1 0 1 1 1 1
1 0 0 1 1 1 1 0 1 1 1
1 0 1 1 1 1 1 1 0 1 1
1 1 0 1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 1 1 1 0
Table 5.4 Truth table of 3 to 8 line decoder using AND gates
Inputs Outputs
A B C O0 O1 O2 O3 O4 O5 O6 O7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Table 5.5 Minterms of three variables
Inputs Product Minterms
Symbol
A B C term m0 m1 m2 m3 m4 m5 m6 m7
–– – m0
0 0 0 A BC 1 0 0 0 0 0 0 0
–– m1
0 0 1 A BC 0 1 0 0 0 0 0 0
– – m2
0 1 0 A BC 0 0 1 0 0 0 0 0
– m3
0 1 1 ABC 0 0 0 1 0 0 0 0
–– m4
1 0 0 ABC 0 0 0 0 1 0 0 0
(Contd...)
 176 Digital Electronics: Principles and Applications

Table 5.5 (Contd...)

– m5
1 0 1 AB C 0 0 0 0 0 1 0 0
– m6
1 1 0 ABC 0 0 0 0 0 0 1 0
1 1 1 ABC m7 0 0 0 0 0 0 0 1
Table 5.6 Maxterms of three variables
Inputs Maxterms
Sum Term Symbol
ABC M0 M1 M2 M3 M4 M5 M6 M7
0 0 0 A+B+C M0 0 1 1 1 1 1 1 1
–
0 0 1 A+B+C M1 1 0 1 1 1 1 1 1
–
0 1 0 A+B+C M2 1 1 0 1 1 1 1 1
– –
0 1 1 A+B+C M3 1 1 1 0 1 1 1 1
–
1 0 0 A +B+C M4 1 1 1 1 0 1 1 1
– –
1 0 1 A +B+C M5 1 1 1 1 1 0 1 1
– –
1 1 0 A +B+C M6 1 1 1 1 1 1 0 1
– – –
1 1 1 A +B+C M7 1 1 1 1 1 1 1 0

5.3.3 4:16 Decoder

4:16 decoder can be implemented similar to 3:8 decoders. Figure
5.10 shows the 4:16 decoder. This has 4 inputs and 16 outputs.
In this decoder also, only one output will be low at a time. For
example, if input is 1000, output O8 will be low and other outputs
will be high. The truth table of 4:16 decoder is shown in Table
5.7. This 4 : 16 decoder can be used for converting any 4-bit
code, which is used to represent the decimal digits to give decimal
output.
Fig. 5.10 4 line to 16 line
decoder
Table 5.7 Truth table of 4 to 16 line decoder
Inputs Outputs
A B C D O0 O1 O2 O3 O4 O5 O6 O7 O 8 O 9 O10 O11 O12 O13 O14 O15
0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
0 1 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
0 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1
0 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1
1 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1
1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1
1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1
1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1
1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1
1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
 Combinational Logic Design 177

The IC 74154 is a 4 line to 16-line decoder. The PIN configuration and

logic diagram of IC74154 are shown in Fig. 5.11 and 5.12 respectively.
The 74154 decoder has four address inputs (A0, A1, A2, A3) and gives 16
mutually exclusive active low outputs (Q–0, Q–1 …… Q–15). The 2-inputs
Enable (E0, E1) gate can be used to strobe the decoder to eliminate the
normal decoding “glitches” on the outputs, or it can be used for expansion
of the decoder. The enable gate has two AND’ed inputs, which must be
Low to enable the outputs. In 74154, one of the Enable inputs is used as
the data input and the other Enable is Low, the addressed output will follow
the state of the applied data.
5.3.4 Cascading Decoders
Two or more decoders can be combined to produce a decoder with large
number of input bits by using the enable bit of decoder. The cascade
Fig. 5.11 Pin configuration combination of two 2 line to 4 line decoder to develop a 3 to 8 line decoder is
of IC 74154
shown in Fig. 5.13. An input variable is used
as an enable input of the first decoder and
the complement of the same input variable
is attached to the enable input of the second
decoder. The most significant input variable
can be used to select which decoder is
enabled and lower input variables are fed to
each decoder. It is depicted in Fig. 5.13 that
E is enable input and A, B are lower input
variables. A block diagram of a 4 line to 16
line decoder is also depicted in Fig. 5.14 and
it consists of five 2 to 4 line decoders.

Fig. 5.12 Logic Diagram of IC 74154

Fig. 5.13 3 line to 8 line decoder using two Fig. 5.14 4 line to 16 line decoder using
2 line to 4 line decoders. five 2 line to 4 line decoders
 178 Digital Electronics: Principles and Applications

Example 5.2 Design a 4 line to 16 line decoder using 3 line to 8 line decoder.
� Solution
Figure 5.15 shows the implementation of a 4 line to
16 line decoder using 3 line to 8 line decoder where
four inputs are A,B, C and Enable(E) and 16 outputs
D0 to D15.

Fig. 5.15 4 line to 16 line decoder using

3 line to 8 line decoder

5.3.5 Applications of Decoders

Decoders can produce either all the minterms or maxterms for ‘n’ input variables. A decoder can be used
to realise any Boolean function of ‘n’ input variables with the help of an OR gate in sum of product
(SOP) representation or a AND gate in product of sum (POS) representation. For example, consider a
four variable Boolean function
F(A, B, C, D) = Sm(0, 1, 2, 3, 4, 5, 7).
The Boolean function can be expressed by
F = m0+m1+m2+m3+m4+m5+m7
The inversion of the above Boolean function is
F¢ = m0 + m1 + m2 + m3 + m4 + m5 + m7
=m – m– m– m– m– m– m–
0 1 2 3 4 5 7

The IC74154 can be used to implement the above logic using a NAND gate as shown in Fig. 5.16.

Fig. 5.16 Combinational logic circuit implementation for Σm(0,1,2,3,4,5,7)

 Combinational Logic Design 179

Example 5.3 Design combinational logic circuits for the logic functions F1, F2 and F3 as given
below using 4:16 decoder IC 74514.
F1=Sm(1,2,3,4,5,7); F2=Sm(2,4,7,9,11); F3=Sm(10,12,14,15)
� Solution
The IC 74514 has an enable terminal, E. When E is
low logic level, the IC is active and A, B, C and D
input variables are used for addressing the output
terminal. The logic function F1=Sm(1,2,3,4,5,7)
can be written in minterm representation as
F1= m1 + m2 + m3 + m4 + m5 + m7 and its complement
F1¢= m– m– m– m– m – m–.
1 2 3 4 5 7
This logic function can be implemented using
an IC74154 and a six inputs NAND gate as
depicted in Fig. 5.17. Similarly, F2 and F3 are
also represented by minterm equations and
implementation circuits are also illustrated in Fig. 5.17 Implementation of combinational
Fig. 5.17. logic circuits of F1=Σm(1,2,3,4,5,7),
F2=Σm(2,4,7,9,11) and F3=Σm(10,12,14,15)

5.3.6 Binary Adder Using Decoder

Figure 5.18 shows the block diagram of full adder circuit. In the full adder circuit there are three inputs
A, B, and CIN, where A and B are two inputs which are added
and CIN is the carry from the previous stage. The sum (S)
and carry output (COUT) are obtained from the addition of
A,B and CIN. The truth table of summation of two numbers
with carry is shown in Table 5.8. The sums and COUT can be Fig. 5.18 Block diagram of full adder
circuit
represented by minterm functions as given below:
S=F(A,B,CIN)=Sm(1,2,4,7) and COUT=F(A,B,CIN)=Sm(3,5,6,7).
Figure 5.19 shows the implementation of full adder using decoder.

Table 5.8 Truth table for binary adder

CIN A B COUT S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1 Fig. 5.19 Binary adder using decoder
 180 Digital Electronics: Principles and Applications

5.3.7 BCD to 7 Seg-

ment Display
The seven segment display wide-
ly used in calculators, digital
watches, and measuring instru-
ments, etc. Generally light emit-
ting diode (LED), liquid crystal
display (LCD) segments provide
Fig. 5.20 (a) Segment identification and (b) numerical displays
the display output of numerical
numbers and characters. To dis-
play any number and character, seven-segment display is most
commonly used. Figure 5.20(a) shows the segment identification
and display of decimal numbers 0 to 9 is given in Fig.5.20(b).
The light emitting diodes emit light when anode is positive with
respect to cathode. There are two possible connections of light
emitting diodes namely common anode and common cathode.
In common anode connection, seven anodes are connected to a
common voltage and cathode will be controlled individually to
get the proper display. But in common cathode connection, an-
odes can be controlled individually for display when all cathodes
are connected to a common supply.
Fig. 5.21 Block diagram of seven
Figure 5.21 shows the block diagram of 7-segment display.
segment display The decimal number 0 to 9 can be displayed by the binary coded
decimal input. For example, the segments a, b, c, d, e, and f will be bright for decimal number 0.Table 5.9
shows the different segments will be bright for decimal number 0 to 9. Using the truth table, the K-map for
each segment is drawn and derives the minimised Boolean expression. Then the circuit is implemented by
using decoder circuit. The Boolean expressions of each output functions can be written as given below:
Table 5.9 Truth table for seven segment display
Decimal Inputs Outputs
Number A B C D a b c d e f g
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 0 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 0 0 1 1
10 1 0 1 0 x x x x x x x
11 1 0 1 1 x x x x x x x
12 1 1 0 0 x x x x x x x
13 1 1 0 1 x x x x x x x
14 1 1 1 0 x x x x x x x
15 1 1 1 1 x x x x x x x
 Combinational Logic Design 181

a=F1(A,B,C.D)=Sm(0,2,3,5,7,8,9)
b=F2(A,B,C.D)=Sm(0,1,2,3,4,7,8,9)
c=F3(A,B,C.D)=Sm(0,1,3,4,5,6,7,8,9)
d=F4(A,B,C.D)=Sm(0,2,3,5,6,8)
e=F5(A,B,C.D)=Sm(0,2,6,8)
f=F6(A,B,C.D)=Sm(0,4,5,6,8,9)
g=F7(A,B,C.D)=Sm(2,3,4,5,6,8,9)
Figure 5.22 shows the pin configuration of IC 7447 and logic
diagram of IC 7447 is depicted in Fig. 5.23. The pin description of IC Fig. 5.22 Pin configuration of
7447 is given below: IC 7447
A0 – A3 BCD inputs
—
RB 1 Ripple blanking
—
LT Lamp test input
— ——
BI /RBO Blanking input/Ripple
blanking output
a– – – Segment outputs
The IC 7447 decodes the input data
given in the truth Table 5.9. IC 7447 is
BCD to 7-Segment Decoder with open-
collector outputs. The 74LS47 has four
input lines of BCD(8421) data, and it
generates their complements internally.
Then decoder decodes the data with seven
AND/OR gates having open-collector
outputs to drive indicator segments di-
rectly. Each segment output sinks about
24 mA in the ON/LOW state and can
withstand up to 15V in the OFF/HIGH
state. Some auxiliary inputs namely ripple
blanking, lamp test and cascadable zero- Fig. 5.23 Logic diagram of IC 7447
suppression functions are also provided in
IC 7447. Zero suppression logic is very
useful in multi seven segment decoders.
Zero suppression is possible in different
ways, namely leading zero suppression
and trailing zero suppression. Leading
zero suppression is blanking of zeros on
the front of the number and trailing zero
suppression is blanking of the zeros after
the number.
Figure 5.24 shows the block diagram Fig. 5.24 Block diagram of 4-digit display of
of four-digit display. The most significant leading zero suppression
 182 Digital Electronics: Principles and Applications

digit (MSD) is always blank if BCD inputs are zero and the blanking input is HIGH. The next higher order digit
is also blank as blanking output is HIGH.
The ripple blanking output indicates that it
has BCD inputs 0 and higher order digits
are 0. The blanking output is connected
to the blanking input of the next decoder.
Then other two digits are displayed.
To display the digits of the right
side of decimal point, trailing zero
suppression is used. The lowest order
digit will be blank when BCD input 0.
Figure 5.25 shows the block diagram
Fig. 5.25 Block diagram of 4-digit display of trailing
zero suppression of 4 digit display for trailing zero
suppression. The blanking output of one
decoder is connected to the blanking input of the next decoder. Here, the lowest order digit is blanked,
as its BCD input is 0. The next digit is also blanked, as blanking input is HIGH and BCD input is 0.
Subsequently remaining two bits are displayed.

5.3.8 BCD to Decimal Decoder

The BCD to decimal decoder converts BCD (8421) code into one of the decimal digits 0 to 9. It is also
called as 4 line to 10 line decoder. Truth table of BCD to decimal decoder is shown in Table 5.10 and
it is implemented by using BCD to decimal decoder IC 7442.The 74HC/HCT42 are high-speed Si-gate
CMOS devices and are pin compatible with low power Schottky TTL. Figure.5.26(a) shows the pin
configuration of IC 7442 and logic symbol of IC 7442 is depicted in Figure.5.26(b). The pin description
of IC 7442 is given below:
A0 to A3 data inputs
Y0 to Y9 data outputs
VCC positive supply voltage
GND ground
The 74HC/HCT42 decoders have four active BCD inputs and provide ten mutually exclusive active
outputs. The logic design of the IC 7442 is such that all outputs are HIGH when binary codes greater than
nine are applied to the inputs. Figure 5.27 shows the logic diagram of BCD to decimal decoder. The most
significant input(A3) generates an useful inhibit function when the IC7442 is used as a 1-of-8 decoder.
Table 5.10 Truth table of BCD to decimal converter
Inputs Outputs
A3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9
0 0 0 0 0 1 1 1 1 1 1 1 1 1
0 0 0 1 1 0 1 1 1 1 1 1 1 1
0 0 1 0 1 1 0 1 1 1 1 1 1 1
0 0 1 1 1 1 1 0 1 1 1 1 1 1
0 1 0 0 1 1 1 1 0 1 1 1 1 1
(Contd...)
 Combinational Logic Design 183

Table 5.10 (Contd...)

0 1 0 1 1 1 1 1 1 0 1 1 1 1
0 1 1 0 1 1 1 1 1 1 0 1 1 1
0 1 1 1 1 1 1 1 1 1 1 0 1 1
1 0 0 0 1 1 1 1 1 1 1 1 0 1
1 0 0 1 1 1 1 1 1 1 1 1 1 0
1 0 1 0 1 1 1 1 1 1 1 1 1 1
1 0 1 1 1 1 1 1 1 1 1 1 1 1
1 1 0 0 1 1 1 1 1 1 1 1 1 1
1 1 0 1 1 1 1 1 1 1 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1

Fig. 5.26 (a) Pin configuration of IC 7442, and Fig. 5.27 Logic diagram of BCD to
(b) logic symbol of IC 7442 decimal converter

5.4 ENCODERS
The operation of encoders is the opposite of decoders. Encoders have 2n inputs and encode them into
‘n’ outputs. When ‘n’ is equal to two, there are four input lines and two output lines. The operation of
4:2, 8:3 and 16:4 encoders are explained in article 5.4.1, 5.4.2 and
5.4.3 respectively.
5.4.1 4:2 Encoder
The block diagram of a four inputs encoder is depicted in Fig.
5.28. Table 5.11 shows the truth table of 4 line to 2-line decoder. If
the line 0 is selected, output will be 00; if line 2 is selected, output Fig. 5.28 Block diagram of 4
will be 10 and so on. The encoder truth table allocates one of the line to 2 line encoder
 184 Digital Electronics: Principles and Applications

Table 5.11 Truth table of 4 line to 2 line encoder

Inputs Outputs
F0 F1 F2 F3 A B
0 0 0 0 0 0
1 0 0 0 0 0
0 1 0 0 0 1
0 0 1 0 1 0
Fig. 5.29 Implementation of 4:2 encoders 0 0 0 1 1 1

four combinations of the address variables A and B to each of the inputs. The outputs of encoder can be
expressed by Boolean expression as given below:
A=F2 +F3
B=F1 + F3
Implementation of 4 line to 2 line encoder is shown in Fig. 5.29.
5.4.2 8:3 Encoder
The block diagram of a eight inputs and three
outputs encoder is depicted in Fig. 5.30. Table
5.12 shows the truth table of 8 lines to 3-line
decoder. The outputs of encoder can be expressed
by Boolean expression as given below:

A=D4+D5+ D 6+ D 7; B= D 2+ D 3+ D 6+ D 7
C= D 1+ D 3+ D 5+ D 7
Fig. 5.30 Block diagram of 8 line to 3 line encoder

The limitation of above decoder is that if all inputs D 0 to D 7 are 0, all outputs will be equal to 0.
Therefore, one additional output is sometimes incorporated to point out this state. Another limitation is
that only one of the encoder’s inputs must be asserted at a time; otherwise the output will be illogical.

Table 5.12 Truth table for 8 line to 3 line encoder

Inputs Outputs
D7 D6 D5 D4 D3 D2 D1 D0 A B C
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
 Combinational Logic Design 185

5.4.3 16:4 Encoder

The block diagram of a sixteen inputs and four outputs encoder
is depicted in Fig. 5.31. Table 5.13 shows the truth table of 16
line to 4-line decoder. The outputs of encoder can be expressed
by Boolean expressions as given below:

A = D8+ D9+ D10+ D11+ D12+ D13+ D14+ D15

B = D4+ D5+ D6+ D7+ D12+ D13+ D14+ D15

C = D 2+D3+D6+ D7+ D10+ D11+ D14+ D15

D = D1+ D3+ D5+ D7+ D9+ D11+ D13+ D15

Fig. 5.31 Block diagram of 16 line

to 4 line encoder

Table 5.13 Truth table of 16:4 encoder

Inputs Outputs
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A B C D
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0
0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0
0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
 186 Digital Electronics: Principles and Applications

Example 5.4 Design an encoder for the truth table 5.14 given below:

Table 5.14 8 line to 3 line encoder

Input Output
I7 I6 I5 I4 I3 I2 I1 I0 B2 B1 B0
x 0 0 0 0 0 0 1 0 0 0
x 0 0 0 0 0 1 0 0 0 1
x 0 0 0 0 1 0 0 0 1 0
x x x 0 1 0 0 0 0 1 1
x 0 0 1 0 0 0 0 1 0 0
x x 1 0 x 0 0 0 1 0 1
x 1 x 0 x 0 0 0 1 1 0
1 x x x x x x 0 1 1 1

� Solution
The outputs of encoder can be expressed by Boolean expressions as given below:

B0= I1+I3+I5+I7

B1= I2+ I3+ I6+ I7

B2= I4+ I5+ I6+I7
Fig. 5.32 8:3 binary encoder
The implementation of above Boolean expressions using OR gates is given in Fig. 5.32.

5.5 PRIORITY ENCODERS

The priority encoder can perform the basic operation of encoder but it has some additional flexibility.
The additional feature is priority detection. The priority detection is that can produce BCD output
according to highest order decimal number. For example, when decimal number inputs 9 and 6 both are
high, the output will be 1001. The operation of most commonly used 4 line to 2 line, 8 line to 3 line and
10 line to 4 line priority encoders are explained below:

5.5.1 4 line to 2 line Priority Encoder

In a 4 line to 2 line encoder, when one input line is selected, according to that, output lines A and B will
be set. But there is no way when two or more inputs are requested for servicing at the same time. In this
situation priorities of inputs will be considered as
Table 5.15 Truth table of 4: 2 priority encoder
parameter to control the output of encoder. A truth
table for 4:2 priority encoder is shown in Table, Inputs Outputs
5.15. In this table priority is assigned to highest F0 F1 F2 F3 A B
asserted input. For example, when inputs F0 and 0 0 0 0 x x
x x x 1 1 1
F1 are asserted, the output should be 01 as the x x 1 0 1 0
input F1 has highest priority. From the truth table x 1 0 0 0 1
5.15, the following equations are obtained 1 0 0 0 0 0
 Combinational Logic Design 187

–
A = F3 + F 3F2 = F3 + F2
– – –
B = F3 + F 3F 2F1 = F3 + F 2F1
The implementation of above equations is shown in Fig. 5.33

5.5.2 8: 3 Priority Encoder

The 8 line to 3 line priority encoder generates a 3 bit binary
output depending on input lines. When line 0 is selected, the
encoder output will be 000. If line 1 is selected, the encoder
Fig. 5.33 4:2 priority encoder
output is 001. In this priority encoder, priority has assigned
to the highest output. Truth table of 8 lines to 3-line priority
encoder is depicted in Table 5.16.

Table 5.16 Truth table for 8 line to 3 line priority encoder

Inputs Outputs
EI I0 I1 I2 I3 I4 I5 I6 I7 A2 A1 A0 GS EO
1 X X X X X X X X 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1 1 1 0
0 X X X X X X X 0 0 0 0 0 1
0 X X X X X X 0 1 0 0 1 0 1
0 X X X X X 0 1 1 0 1 0 0 1
0 X X X X 0 1 1 1 0 1 1 0 1
0 X X X 0 1 1 1 1 1 0 0 0 1
0 X X 0 1 1 1 1 1 1 0 1 0 1
0 X 0 1 1 1 1 1 1 1 1 0 0 1
0 0 1 1 1 1 1 1 1 1 1 1 0 1

To create a priority encoder it is first useful to create functions that are true only if their corresponding
input lines are true. For a 8 to 3 encoder these functions will be:
H7=I7
–
H6 = I6 I 7
– –
H5= I5 I 6 I 7
– – –
H4= I4 I 5 I 6 I 7
– – – –
H3= I3 I 4 I 5 I 6 I 7
– – – – –
H2= I2 I 3 I 4 I 5 I 6 I 7
– – – – – –
H1= I1 I 2 I 3 I 4 I 5 I 6 I 7
– – – – – – –
H0= I0 I 1 I 2 I 3 I 4 I 5 I 6 I 7
where, H stands for highest priority, and I stands for inputs.
Then H0, H1 …… H7 functions are used to create the outputs A0 to A2 as follows
 188 Digital Electronics: Principles and Applications

A0= H1 + H3 + H5 + H7
A1= H2+ H3+ H6+ H7
A2= H4+ H5+ H6+ H7
IC74148 is an MSI encoding circuit for the 8 to 3 line priority encoder.
The features of IC 74148 are code conversions, decimal-to-BCD converter,
cascading for priority encoding of ‘n’ bits, input enable capability, priority
encoding of highest priority input line, output enable-active Low when all
inputs are high, group signal output-active when any input is Low.
The 8-input priority encoder IC 74148 acknowledges data from eight
active-low inputs and provides a binary representation on the three active
Fig. 5.34 Pin diagram low outputs. A priority is assigned to each input so that when two or more
of IC 74148 inputs are simultaneously active. The input with the highest priority is
represented on the output, with input line I7 having the highest priority.
The pin diagram of IC74148 is given in Fig. 5.34 and the pin description as follows:
I 1 – I7 Priority inputs (active Low)
I0 Priority input (active Low)
EI Enable input (active Low)
EO Enable output (active Low)
GS Group select output (active Low)
A0 – A2 Address outputs (active Low)
The logic circuit diagram of IC74148 is shown in Fig. 5.35. When enable input signal EI is active
low, the IC will be enable. The high EI signal will force all outputs to the inactive or high state and
allow new data to settle without producing erroneous
information at the outputs. When the numbers of
input signals to be encoded are more than eight,
two or more encoders are connected in cascade.
To operate in combination with other encoders, the
group select signal (GS) and enable output signal
(EO) are provided in encoder. The GS is active-low
when any input is low. The EO is active-low when all
inputs are high. If EO and GS are active-high, when
the enable input is high. The enable output and group
select signals can be expressed as
—
EO = EI I0I1I2I3I4I5I6I7
—
GS = EI + I0I1I2I3I4I5I6I7EI
Priority encoders are commonly used in micro-
processor, micro-controller and computer to handle
interrupt signals and the processor should response
Fig. 5.35 Logic diagram of IC 74148 to the highest priority pending interrupt request.
 Combinational Logic Design 189

5.5.3 10 Line to 4 Line

Priority Encoder
IC 74147 is a 10-line to 4-line priority encoder
and encodes 10-line decimal to 4-line BCD.
The pin diagram of IC 74147 is depicted in Fig.
5.36 and the pin description as follows:

Y0 to Y3 BCD address outputs

(active LOW)
A0 to A8 decimal data inputs (active LOW)
VCC positive supply voltage
GND ground (0 V) Fig. 5.36 (a) Pin configuration of IC74147 and
n.c. not connected (b) Logic symbol of IC 74147

The 9-input priority encoders IC74147

accept data from nine active low inputs (A0
to A8) and provide a binary representation
on the four active low outputs (Y0 to Y3).
A priority is assigned to each input so that
when two or more inputs are simultaneous-
ly active, the input with the highest priority
is represented on the output. The input line
A8 has the highest priority. The IC 74147
provides the 10-line to 4-line priority en-
coding function by use of the implied deci-
mal ‘0’. The ‘0’ is encoded when all nine
data inputs are high and all four outputs are
high. The logic diagram of 74147 is shown
Fig. 5.37 Logic diagram of IC 74147-priority encoder
in Fig. 5.37 and the truth able for IC 74147-
priority encoder is given in Table 5.17.

Table 5.17 Truth table for 74147-priority encoder

Inputs Outputs
A0 A1 A2 A3 A4 A5 A6 A7 A8 Y3 Y2 Y1 Y0
1 1 1 1 1 1 1 1 1 1 1 1 1
X X X X X X X X 0 0 1 1 0
X X X X X X X 0 1 0 1 1 1
X X X X X X 0 1 1 1 0 0 0
X X X X X 0 1 1 1 1 0 0 1
X X X X 0 1 1 1 1 1 0 1 0
X X X 0 1 1 1 1 1 1 0 1 1
X X 0 1 1 1 1 1 1 1 1 0 0
X 0 1 1 1 1 1 1 1 1 1 0 1
0 1 1 1 1 1 1 1 1 1 1 1 0
 190 Digital Electronics: Principles and Applications

5.5.4 Cascading Priority Encoders

By cascade connection of several priority encoders, we can create a larger priority encoder. In an
encoder IC, EI is enable input. This input enables the priority encoder. EO is enable output. This output
is asserted only when EI is asserted and none of the other inputs are asserted. This output is used to
enable other lower priority encoders. Figure 5.38 shows the cascade connection of two 74148 ICs to
form a 16 line to 4 line encoder. The enable input EI of the IC2 is connected to ground. If any input of
IC2 goes low, its EO goes high. As EO of IC2 is connected to the enable input, EI of the IC1, IC1 will be
disabled. If IC2 is enabled, the GS output of the IC2 goes low when any of its input becomes low. But
the GS outputs of both the ICs will be high, while no input of any of the ICs is low. This 16 line to 4
line encoder can be used for converting hexadecimal number to binary form. In hexadecimal to binary
conversion, hexadecimal inputs 0 to 7 are connected to the input lines of encoder IC1 and hexadecimal
inputs 8 to F are connected to the input lines of encoder IC2.

Fig. 5.38 16 inputs priority encoder

5.6 MULTIPLEXERS
The multiplexer is a combinational logic circuit, which operates as controlled switch with ‘n’ inputs
and one single data output. It selects one of the inputs according to
binary signals applied on select pins of combinational circuit and Table 5.18 Multiplexer ICs
passes the information of the selected line to the common output. IC NO. Description
Therefore multiplexer is also called as data selector. Generally 74157 Quad 2:1 Multiplexer
the number of data inputs is a power of two (2, 4, 8, 16 etc). The 74158 Quad 2:1 Multiplexer
operation of 2:1, 4:1, 8:1 and 16:1 multiplexers are explained in 74153 Dual 4:1 Multiplexer
74352 Dual 4:1 Multiplexer
article 5.6.1, 5.6.2, 5.6.3 and 5.6.4 respectively. Table 5.18 shows the
74152 8:1 Multiplexer
available multiplexer ICs. 74150 16:1 Multiplexer
 Combinational Logic Design 191

5.6.1 2:1 Multiplexer

Figure 5.39 shows the block diagram of 2:1 multiplexer and the multiplexer has two inputs (D0 &
D1), one select input (S) and one output (F).
The switch connects the output to the one
input or the other depending on a select signal.
Since there are only two possible ways to
connect the input lines, only one select signal
is needed. If the select line is high, the output
will be switched to D1 and if the select line
is low, the output will be switched to input
D0. Figure 5.40 shows the actual 2:1 analog
multiplexer. In analog multiplexer, the output Fig. 5.39 Block diagram of 2:1 multiplexer
is literally equal to the input signal. In a digital
multiplexer, the output will be high if input is high and output will be low if input is low. The truth table
of 2:1 multiplexer is shown in Table 5.19.

Table 5.19 Truth table of 2:1 multiplexer

Select Inputs Output

S D1 D0 F
0 0 0 0
0 0 1 1
1 1 0 1
1 1 1 1
Fig. 5.40 2: 1 analog multiplexer

Figure 5.41 shows logic circuit of 2:1 multiplexer

using logic gates. When S=0, output of lower AND gate
D0, but output of upper AND gate is 0. Therefore, output
generated by OR gate is equal to D0. Similarly, when
S=1, output of upper AND gate is D1 and output of lower
AND gate is 0. Consequently, output of OR gate is D1.
–
Then output expression is O = S D0 + SD1.
Simple logic gates can implement multiplexers and Fig. 5.41 Logic circuit of 2:1 multiplexer
these gates can be fabricated in a IC. Usually four 2 line
to 1 line multiplexers are fabricated in a single IC. IC 74157 and IC 74158 are the examples of 2:1
multiplexer. The connection diagram and logic circuit diagram of IC 74157 and IC 74158 are shown
in Figs 5.42 and 5.43 respectively. Strobe and select signals are common to all four 2 line to 1 line
multiplexer. When strobe is low, multiplexer is enable and data can pass from selected input line to
output line. When strobe is high, multiplexer is disable and no data can pass from input to output. The
selected signal is used to select one of the 2 inputs.
 192 Digital Electronics: Principles and Applications

Fig. 5.42 (a) Connection diagram of IC 74157 and (b) Logic diagram of quad
2 line to 1 line multiplexers IC 74157

Fig. 5.43 (a) Connection diagram of IC 74158 and (b) Logic diagram of
quad 2 line to 1 line multiplexer IC 74158

5.6.2 4:1 Multiplexer

Figure 5.44 shows the block diagram of a multiplexer
with four inputs, D0, D1, D2 and D3. There are two select
lines S0 and S1 and an enable line, E. The multiplexer
decodes the input through select line. Table 5.20 shows
the truth table of 4:1 multiplexer. When select inputs
S1=0 and S0=0, the data output Y is equal to D0. The data
output Y is equal to D1, if select inputs S1=0 and S0=1. If
select inputs S1=1 and S0=0, the data output Y is equal to
D2. The data output Y is equal to D3, if select inputs S1=1
and S0=1. The output expression is Fig. 5.44 Block diagram of 4:1 multiplexer
 Combinational Logic Design 193

– — – –
Y = DO S 1 S 0 + D1S 1S0 + D2S1S 0 + D3S1S0
Figure 5.45 shows the implementation of 4 line to single line multiplexer using gates. The inputs of
the multiplexer are D0, D1, D2 and D3 and two select lines S0 and S1. Four 3 inputs AND gates and one
four inputs OR gate are used for implementation of a 4:1 multiplexer.
Table 5.20 Truth table for 4:1 Muxtiplexer
Selects Data Inputs Output
S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3

Fig. 5.45 4:1 multiplexer

Generally, dual 4 line to 1 line multiplexers ICs are available. IC74153 is a dual 4 line to 1 line
multiplexer and its logic symbol and circuit diagram are shown in Fig. 5.46 (a) and (b) respectively. This
multiplexer has two select input lines (A and B). When AB = 00, the D0 input line is selected. If AB =
11 the D3 input line is selected. Like quad 2 line to 1 line multiplexer, dual 4 line to 1 line multiplexers
have two strobe which are used to switch on and off the multiplexers. The functional table of IC74153
is given in Table 5.21.

Fig. 5.46 (a) Logic symbol of dual 4:1 multiplexers and (b) Logic diagram
of dual 4 line to 1 line multiplexer IC 74153
 194 Digital Electronics: Principles and Applications

Table 5.21 Functional table of dual 4 line to 1 line multiplexer IC 74153

Select Inputs Inputs Strobe Output
–
B A C0 C1 C2 C3 G Y
x x x x x x 0 0
0 0 0 x x x 0 0
0 0 1 x x x 0 1
0 1 x 0 x x 0 0
0 1 x 1 x x 0 1
1 0 x x 0 x 0 0
1 0 x x 1 x 0 1
1 1 x x x 0 0 0
1 1 x x x 1 0 1

5.6.3 8-line to 1-line Multiplexer

The block diagram of 8:1 multiplexer is shown in Fig. 5.47. This multiplexer has eight input lines D0 to
D7 and three select inputs S0 to S2. The multiplexer
decodes the inputs through select lines. Table 5.22
shows the truth table of 8:1 multiplexer. If select
inputs S2 = 1, S1 = 0 and S0 = 0, the data output Y
is equal to D4. Similarly the data outputs D0 to D7
will selected through S2 , S1 and S0 as shown in Table
5.22. The output Y can be expressed as

Table 5.22 Truth table of 8:1 multiplexer

Selects Data Inputs Output
S2 S1 S0 Y
Fig. 5.47 Block diagram of 8:1 multiplexer 0 0 0 D0
– – – – – – – – 0 0 1 D1
Y = D0S 2S 1S 0 + D1S 2S 1S0 + D2S 2S1S 0 + D3S 2S1S0 0 1 0 D2
– – – –
+ D4S2S 1S 0 + D5S2S 1S0 + D6S2S1S 0 0 1 1 D3
+ D7S2S1S0 1 0 0 D4
1 0 1 D5
1 1 0 D6
1 1 1 D7

The multiplexer IC 74151A has eight input lines from D0 to

D7 and three select inputs A, B and C. There is also provision for
a strobe, which is active low. If strobe is low, the multiplexer
is enabled. When strobe is held high, IC is disabled. The data
output and its complement are available at output pins. Figure
5.48 shows the pin configuration of this multiplexer and the
logic diagram for this multiplexer is in Fig. 5.49.
IC 74151A is a 8 line to 1 line multiplexer and its circuit diagram
is shown in Fig.5.49. This multiplexer has three select lines A, B
and C. Every time one of the inputs will be selected through select
Fig. 5.48 Pin diagram of 74151A
 Combinational Logic Design 195

lines and send the data of the selected line to output line.
In this multiplexer, strobe signal is used as a switch to
turn on and off the multiplexer. Table 5.23 shows the
functional table of 8 lines to 1 line multiplexer.
Table 5.23 Functional table of 8 lines to
1 line multiplexer

Inputs Outputs
Select inputs Store
– Y W
C B A G
X X X 1 0 1
–
0 0 0 0 D0 D0
–
0 0 1 0 D1 D1
–
0 1 0 0 D2 D2
–
0 1 1 0 D3 D3
–
1 0 0 0 D4 D4
–
1 0 1 0 D5 D5
–
1 1 0 0 D6 D6 Fig. 5.49 Logic diagram for
– multiplexer 1C 74151
1 1 1 0 D7 D7

5.6.4 16-line to 1-line Multiplexer

This multiplexer has 16 input lines, four select
lines and one output. Figure 5.50 shows the
block diagram of 16 lines to 1 line multiplexer.
The multiplexer select one out of 16 inputs D0
to D15 through four select lines S0 to S3 and send
information to output. Table 5.24 shows the truth
table of 16 lines to 1 line multiplexer. The 16:1
data selectors/multiplexers contain full on-chip
decoding to select the desired data source. The IC
74150 is a 16:1 multiplexer and is used to select
one-of-sixteen data sources. Pin connections of
multiplexer IC 74150 are given in Fig. 5.51(a) and
its logic symbol is also shown in Fig. 5.51(b). The
bubble at the output point out that the output is
active low if the selected data bit is high. So, the
output is always the complement of the selected
data bit. The 74150 have a strobe input, which must Fig. 5.50 Block diagram of 16:1 multiplexer
be at a LOW logic level to enable these devices. A
HIGH level at the strobe forces the W output HIGH and the Y output LOW. The 74150 features an
inverted (W) output only. The logic circuit diagram of IC 74150 is shown in Fig. 5.52.
196 Digital Electronics: Principles and Applications

Table 5.24 Truth table of 16:1 multiplexer

Selects Data Inputs Strobe Output
–
S3 S2 S1 S0 G Y
0 0 0 0 0 D0
0 0 0 1 0 D1
0 0 1 0 0 D2
0 0 1 1 0 D3
0 1 0 0 0 D4
0 1 0 1 0 D5
0 1 1 0 0 D6
0 1 1 1 0 D7
1 0 0 0 0 D8
1 0 0 1 0 D9
1 0 1 0 0 D10
1 0 1 1 0 D11
1 1 0 0 0 D12
1 1 0 1 0 D13
1 1 1 0 0 D14
1 1 1 1 0 D15

Fig. 5.51 (a) Pin diagram of 74150 and (b) Logic symbol of 74150
 Combinational Logic Design 197

Fig. 5.52 Logic diagram of 74150

5.6.5 Cascading Multiplexers

One can connect two or more multiplexers in cascade by using
the enable input on a multiplexer and an OR gate to construct
a larger multiplexer. The example is that two 4 line to 1 line
multiplexers are combined to create one 8 to 1 multiplexer.
Three select lines are required for a 8 to 1 multiplexer. 2 of the
three lines are directly connected to the select inputs of each
4:1 multiplexer. The other select line is connected to enable
one of the two multiplexers and inverted enable is connected
to other 4:1 multiplexer. The outputs of two 4:1 multiplexers
are combined by using an external OR gate to develop 8:1
multiplexers. Figure 5.53 shows the 8:1 multiplexer using two Fig. 5.53 8:1 multiplexer using two
4:1 multiplexers. 4:1 multiplexers
 198 Digital Electronics: Principles and Applications

Example 5.5 Design a 32:1 multiplexer using two 16:1 multiplexers.

� Solution
The 16:1 multiplexers are the largest available ICs. Therefore, 32:1 multiplexer can be designed by using two
16:1 multiplexers with the help of enable/strobe inputs. Figure 5.54 shows the 32 line to 1 line multiplexer
using two 16:1 multiplexers and an OR gate.

Fig. 5.54 32:1 multiplexer using two 16:1 multiplexers

5.6.6 Applications of Multiplexers

Multiplexers are used in
∑ Boolean function implementation
∑ Pulse train generator
∑ Register to register data transfer
∑ Encoders
∑ Combinational logic circuit design.
The example of Boolean function implementation and pulse train generator are given below.
 Combinational Logic Design 199

Example 5.6 Implement the Boolean function F(A,B,C,D)=Sm(1,2,4,5,7,9,11,12) using a multiplexer.

� Solution
As there are four variables, a four select lines multiplexer is required to implement the Boolean function
F(A,B,C,D)=Sm(1,2,4,5,7,9,11,12) . So, 16:1 multiplexer IC74150 will be selected. The circuit diagram for
implementation of above Boolean function is shown in Fig. 5.55.

Fig. 5.55

Example 5.7 Implement the Boolean function F(X,Y,Z)=Σm(1,2,6,7) using 4:1 multiplexer.

� Solution
As 4:1 multiplexer is used to implement the Boolean function F(X,Y,Z)=Σm(1,2,6,7) , two select inputs can
be used for selecting the 4 input address lines. Since the output is depends on the value Z, the output F will
Table 5.25 Truth table of 4: 1 multiplexer

Inputs Output
X Y Z F
0 0 0 0 F=Z
0 0 1 1 F=Z
–
0 1 0 1 F=Z
–
0 1 1 0 F=
1 0 0 0 F=0
1 0 1 0 F=0
1 1 0 1 F=1 Fig. 5.56
1 1 1 1 F=1
 200 Digital Electronics: Principles and Applications

–
be derived from Z, Z , 1, and 0. The relation between Z and F is depicted in Table 5.25. Figure 5.56 shows the
implementation of Boolean function F(X,Y,Z)=Σm(1,2,6,7) using 4:1 multiplexer.

Example 5.8 Implement the Boolean function F(A,B,C,D) =Σm(1,3,4,11,12,13,14,15) using 8:1
multiplexer.

� Solution
Create truth table for F as shown in Table 5.26. A, B, and C are used as variables to the selection inputs. The
last input variable D can be considered as input data and the values of F to select the inputs for each of the
–
multiplexer’s data input lines are D, D , 0 or 1. Figure 5.57 shows the implementation of Table 5.26, which
represents the Boolean function F(A,B,C,D) = Sm(1,3,4,11,12,13,14,15).

Table 5.26 Truth table of 4: 1 multiplexer

Select Data Output

A B C D F
0 0 0 0 0 F=D
0 0 0 1 1 F=D
0 0 1 0 0 F=D
0 0 1 1 1 F=D
–
0 1 0 0 1 F=D
–
0 1 0 1 0 F=D
0 1 1 0 0 F=0
0 1 1 1 0 F=0
1 0 0 0 0 F=0
1 0 0 1 0 F=0
1 0 1 0 0 F=D
1 0 1 1 1 F=D
1 1 0 0 1 F=1
1 1 0 1 1 F=1 Fig. 5.57

1 1 1 0 1 F=1
1 1 1 1 1 F=1

Example 5.9 Design a circuit for a pulse train 10101011 using a multiplexer.

� Solution
As the length of the pulse train is 8 bits, 8:1 multiplexer and MOD 8 counter will be used to generate the
pulse 10101011. Figure. 5.58 shows the implementation of pulse train.
 Combinational Logic Design 201

Fig. 5.58

Table 5.27 Demultiplexer ICs

5.7 DEMULTIPLEXER
Demultiplexer is the inverse of the multiplexing. A demultiplexer IC NO. Description
bypass the binary input data to one of it’s many output lines. The 74139 Dual 1:4 Demultiplexer
selection of which output line receives the information can be 74136 1:8 Demultiplexer
determined by the binary input on the select lines. Commonly 74154 1:16 Demultiplexer
available demultiplexers are 1:4, 1:8 and 1:16. Table 5.27 shows
the available demultiplexer ICs.

5.7.1 1:2 DEMULTIPLEXER

Figure 5.59 shows the 1:2 demultiplexer, which has one input
and two outputs. The switch connects the input to one of the
output depending on a select signal. Since there are only two
possible ways to connect the input and output lines, only one
select signal is required. If the select line is low, the input will
be switched to D0 and if the select line is high, the input will be
switched to D1.
Fig. 5.59 Block diagram of 1:2
Table 5.28 Truth table of 2:1 multiplexer demultiplexer
Select Input Outputs
S F D1 D0 Figure 5.60 shows the actual 1:2 analog demulti-
0 0 0 0 plexer. In analog demultiplexer, the output is literally
0 1 0 1
equal to the input for all values of input. In a digital
demultiplexer, the output will be high if input is high
1 0 0 0
and output will be low if input is low. The truth table
1 1 1 0 of 1:2 demultiplexer is shown in Table 5.28.
 202 Digital Electronics: Principles and Applications

5.7.2 1:4 Demultiplexer

1:2 demultiplexer can be extended to 1:4 demultiplexer
by increasing the number of select lines. 1:4 de-
mutiplexer has four output lines and two select inputs.
If the select input lines are 00, the input is connected
to output line D0; if the select lines are 01, then input is
connected to output line D1. Table 5.29 shows the truth
Fig. 5.60 1 : 2 analog demultiplexer
table of 1:4 demultiplexer. Figure 5.61 shows the circuit
for 1:4 demultiplexer. The output logic can be expressed
by meanterms as given below:
– –
D0 = ES 1S 0
–
D1 = ES 1S0
–
D2 = ES1S 0
D3 = ES1S0
where, E is as input data, S0 and S1 are select lines and
output lines are D0 to D4. Fig. 5.61 Logic diagram of 1 line to 4 line
demultiplexer

Table 5.29 Truth table of 1 line to 4 line demultiplexer

Inputs Output
E S1 S0 D0 D1 D2 D3
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
1 x x 1 1 1 1

The IC74139 is a dual 1-of-4 demultiplexer. The pin configuration of 1:4 demultiplexer is shown in
Fig. 5.62 and pins description of IC 74139 is given below:
A0n, A1n Address inputs
Ea, Eb Enable inputs (active-Low)
Q0n, Q3n Data outputs
This IC has two independent demultiplexers. Each demultiplexer can accept two binary weighted
inputs (A0n, A1n) and provides four mutually exclusive active-low outputs (Q0n – Q3n). Each demultiplexer
has an active-low enable (E). When E is high, all outputs are high. The enable can be used as the data
input for a 1-of-4 demultiplexer application. The functional table for one of demultiplexer is given in
Table 5.30. Logic diagram of dual 1 line to 4 line demultiplexer is depicted in Fig. 5.63.
 Combinational Logic Design 203

Fig. 5.62 (a) Pin configuration of 1:4 demultiplexer, (b)Logic symbol of dual 1:4 line demultiplexer

Fig. 5.63 Logic diagram of dual 1:4 line demultiplexer

Table 5.30 Functional table of 1:4 demultiplexer

Inputs Output
Enable Select – – – –
Q0 Q1 Q2 Q3
E A0 A1
1 x x 1 1 1 1
0 0 0 0 1 1 1
0 1 0 1 0 1 1
0 0 1 1 1 0
0 1 1 1 1 1 0
 204 Digital Electronics: Principles and Applications

5.7.3 1:8 Demultiplexer

The IC74237 is a 3-to-8 line decoder/ 1:8 demultiplexer with latches
at the three address inputs (A0 to A2). Pin configuration of IC 74237
is shown in Fig. 5.64 and pin description is given below:
A0 to A2 data inputs
Y0 to Y7 demultiplexer outputs
LE latch enable input (active LOW)
E1 data enable input (active LOW)
E2 data enable input (active HIGH)
GND ground (0 V)
VCC positive supply voltage.
Figure 5.65 shows the functional diagram of demultiplexer IC Fig. 5.64 Pin configuration of
1:8 demultiplexer
74237 and its functional table is Table 5.31. This demultiplexer
has three enable inputs LE, E1 and E2, which can be used to extend the higher demultiplexers. The
IC74237combines the 3-to-8 decoder function with a 3-bit storage latch. When the latch is enabled (LE
= low), the IC74237 acts as a 3-to-8 active low decoder. When the latch enable (LE) changes from low-
to-high, the last data present at the inputs before this transition, is stored in the latches. Further address
changes are ignored as long as LE remains high.
The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs
or latch operation. All outputs are high unless E1 is low and E2 is high. The logic circuit diagram of
demultiplexer IC 74237 is depicted in Fig. 5.66.

Table 5.31 Functional table of 1:8 demultiplexer IC 74237

Inputs Output
Enable Select Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
–— – –
LE E1 E2 A0 A1 A2
x 1 x x x x 0 0 0 0 0 0 0 0
x x 0 x x x 0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0 0 0 0 0 0 0
0 0 1 1 0 0 0 1 0 0 0 0 0 0
0 0 1 0 1 0 0 0 1 0 0 0 0 0
0 0 1 1 1 0 0 0 0 1 0 0 0 0
0 0 1 0 0 1 0 0 0 0 1 0 0 0 Fig. 5.65 Functional diagram of 1:8
demultiplexer
0 0 1 1 0 1 0 0 0 0 0 1 0 0
0 0 1 0 1 1 0 0 0 0 0 0 1 0
0 0 1 1 1 1 0 0 0 0 0 0 0 1
 Combinational Logic Design 205

Fig. 5.66 Logic diagram of 1:8 demultiplexer

5.7.4 1:16 Demultiplexer

The 4-to-16 line decoders/ 1 : 16 demultiplexers IC74514 are having four binary weighted address
inputs (A0 to A3), with latches, a latch enable input (LE), and an active LOW enable input (E). The
16 outputs (Q0 to Q15) are mutually exclusive active HIGH. When LE is HIGH, the selected output is
determined by the data on An. When LE goes LOW, the last data present at An are stored in the latches
and the outputs remain stable. When E is LOW, the selected output, determined by the contents of the
latch, is HIGH. At E HIGH, all outputs are LOW. The enable input (E) does not affect the state of the
latch. When the IC74514 is used as a demultiplexer, E is the data input and A0 to A3 are the address
inputs. Pin configuration and logic symbol of IC 74514 are shown in Fig. 5.67 (a) and (b) respectively.
The functional diagram of 1:16 demultiplexer IC 74514 is illustrated in Fig. 5.68 and functional table of
1:16 demultiplexer is given in Table 5.32. Figure 5.69 shows the logic diagram of 1:16 demultiplexer IC
74514. The pin description of IC 74514 is given below:
LE latch enable input (active HIGH).
A0 to A3 address inputs
Q0 to Q15 demultiplexer outputs (active HIGH)
GND ground (0 V)
n enable input (active LOW)
VCC positive supply voltage
206 Digital Electronics: Principles and Applications

Fig. 5.67 (a) Pin configuration 1:16 demultiplexer IC 74514 and

(b) Logic symbol 1:16 demultiplexer

Table 5.32 Functional table of 1:16 demultiplexer

Inputs Outputs
–
E A0 A1 A2 A3 Q0 Q1 Q2 Q3 Q 4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15
1 x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0
0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
 Combinational Logic Design 207

Fig. 5.68 Functional diagram of 1:16 demultiplexer IC 74514

Fig. 5.69 Logic diagram of 1:16 demultiplexer IC 74514

 208 Digital Electronics: Principles and Applications

5.7.5 Cascade Demultiplexer

1:16 demultiplexer is the largest available ICs. When large demultiplexer is required, we can not
implemented by using single MSI ICs. Therefore, two or more demultiplexers are connected in cascade
to fulfill the requirement. The expansion of 1:16 demultiplexer to 1:32 demultiplexer is possible using
enable input terminals. The Enable E is the most significant bit and A will be least significant bit. Figure
5.70 shows the 1:32 demultiplexer.

Fig. 5.70 Logic diagram of 1:32 demultiplexer

5.7.6 Applications of Demultiplexers

Demultiplexers are used in
• Boolean function implementation
• Data transmission
• Combinational logic circuit design.
• Generate enable signals (enable one out of many). The application of enable signals in micropro-
cessor systems are:
i. Selecting different banks of memory
ii. Selecting different input/output devices for data transfer
iii. Enabling different functional units
iv. Enabling different rows of memory chips depending on address
Generally, demultiplexers are used to implement multiple Boolean functions and decoder circuits.
The application of demultiplexer in multiple Boolean functions implementation is given in Example
5.10.
 Combinational Logic Design 209

Example 5.10 Design a circuit using multiplexer for the following Boolean functions:

F1(A,B,C,D)=S (1,2,3,4,5,7)
F2(A,B,C,D)=S (2,4,7,9,11)
F3(A,B,C,D)=S (10,12,14,15)

� Solution
As there are four variables, 1: 16 demultiplexer can be used with four select lines. Figure 5.71 shows the
implementations of above Boolean functions using demultiplexer and OR gates.

Fig. 5.71

5.8 CODE CONVERSION USING LOGIC GATES AND MSI ICs

In digital system, most commonly used codes are Binary, BCD, Excess-3, Gray code, 9’s complement
and 10’s complement of decimal number. In different applications, different codes are used. For example,
BCD data must be converted to seven-segment code, which is incorporated in article 5.3.7 to display
BCD numbers in seven-segment display form. Therefore, BCD to Excess-3, BCD to Binary, Binary to
Gray, Gray to Binary, 9’s complement and 10’s complement of Decimal number conversions using logic
gates and MSI ICs are explained in this section

5.8.1 BCD to Excess–3 Decoder

In Excess-3 code, each decimal digit is represented by it’s binary code plus 3. Truth table for BCD to
Excess-3 decoder is given in Table 5.33. The K-map of the corresponding truth table and reduction of
all the output functions are shown in Fig. 5.72.
210 Digital Electronics: Principles and Applications

Table 5.33 Truth table for BCD to excess-3 decoder

Decimal BCD Inputs Excess-3 Output

Numbers
A B C D O3 O2 O1 O0
0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 1 0 0
2 0 0 1 0 0 1 0 1
3 0 0 1 1 0 1 1 0
4 0 1 0 0 0 1 1 1
5 0 1 0 1 1 0 0 0
6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0
10 1 0 1 0 x x x x
11 1 0 1 1 x x x x
12 1 1 0 0 x x x x
13 1 1 0 1 x x x x
14 1 1 1 0 x x x x
15 1 1 1 1 x x x x

The minimal SOP functions for the outputs are

–
O0 = D
––
O1 = CD + C D
–– – –
O2 = BC D + BC + BD
O3 = A + BC + BD
These expressions can be implemented using AND, OR and NOR gates as depicted in Fig. 5.73.
The outputs O0, O1, O2 and O3 can be expressed in minterms as given below:

O0=Σm(0,2,4,6,8)

O1=Σm(0,3,4,7,8)

O2=Σm(1,2,3,4,9)

O3=Σm(5,6,7,8,9)
The implementation of O0, O1, O2 and O3 using 4 line to 16 line decoder IC is given in Fig. 5.74.
 Combinational Logic Design 211

Fig. 5.72 (a) K-map for O3; (b) K-map for O2; (c) K-map for O1; (d) K-map for O0

Fig. 5.73 Binary to Excess 3 converter using logic gates

 212 Digital Electronics: Principles and Applications

Fig. 5.74 Binary to Excess 3 converter using decoder

5.8.2 Gray Code to Binary Code

Table 5.34 shows the Gray code and it’s equivalent decimal number. From this table, the binary code
A,B,C and D are expressed in terms of G0,G1, G2 and G3 as given below.
A = F1 ( G0, G1, G2, G3) = Sm(8,9,10,11,12,13,14,15)
B = F2 ( G0, G1, G2, G3) = Sm(4,5,6,7,8,9,10,11)
C = F3 ( G0, G1, G2, G3) = Sm(2,3,4,5,8,9,14,15)
D = F4 ( G0, G1, G2, G3) = Sm(1,2,4,7,8,11,13,14)
K-maps can be constructed for these expressions for getting the minimal SOP form for them. The
corresponding K-maps are shown in Fig. 5.75 (a), (b), (c) and (d).

Table 5.34 Truth table for Gray code to binary code

Decimal Gray Code Binary Code

Numbers G3 G2 G1 G0 A B C D
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 1 0 0 1 0
3 0 0 1 0 0 0 1 1
4 0 1 1 0 0 1 0 0
5 0 1 1 1 0 1 0 1
6 0 1 0 1 0 1 1 0
7 0 1 0 0 0 1 1 1
8 1 1 0 0 1 0 0 0
(Contd.)
 Combinational Logic Design 213

Table 5.34 (Contd.)

9 1 1 0 1 1 0 0 1
10 1 1 1 1 1 0 1 0
11 1 1 1 0 1 0 1 1
12 1 0 1 0 1 1 0 0
13 1 0 1 1 1 1 0 1
14 1 0 0 1 1 1 1 0
15 1 0 0 0 1 1 1 1

Fig. 5.75 (a) K-map for A; (b) K-map for B; (c) K-map for C; (d) K-map for D
The minimal SOP functions for the outputs are given below.
A=G3
B=G3≈G2
C=G3≈G2≈G1
D=G3≈G2≈G1≈G0
 214 Digital Electronics: Principles and Applications

These expressions can be implemented using X-OR gates as

shown in Fig. 5.76. IC 7486 IC can be used as a binary to Gray
converter based on X-OR logic gates. These logic expressions
can also be implemented by using 4 line to 16-line decoder.

5.8.3 Binary Code to Gray Code

Table 5.35 shows the binary code and it’s equivalent Gray Fig. 5.76 Gray to Binary converter
code. From the table, the Gray code G0, G1, G2 and G3 can be using X-Or gates
expressed in terms of A,B,C and D as given below.
G0 = F1 (A, B, C, D) = Sm(1,2,5,6,9,10,13,14)
G1 = F2 (A, B, C, D) = Sm(2,3,4,5,10,11,12,13)
G2 = F3 (A, B, C, D) = Sm(4,5,6,7,8,9,10,11)
G3 = F4 (A, B, C, D) = Sm(8,9,10,11,12,13,14,15)

Table 5.35 Truth table for binary code to Gray code

Decimal Binary Code Gray Code

Numbers A B C D G3 G2 G1 G0
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0
4 0 1 0 0 0 1 1 0
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
7 0 1 1 1 0 1 0 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
10 1 0 1 0 1 1 1 1
11 1 0 1 1 1 1 1 0
12 1 1 0 0 1 0 1 0
13 1 1 0 1 1 0 1 1
14 1 1 1 0 1 0 0 1
15 1 1 1 1 1 0 0 0

The binary to Gray converter can also implemented by X-OR gates. It is depicted from the Table 5.35
that the most significant bits of binary and Gray codes are the same. Consequently, the most significant
bits does not require any conversion. Figure 5.77 shows the circuit of binary to Gray code conversion.
The Boolean expressions of binary to Gray code are given below:
 Combinational Logic Design 215

G3=A
G2=A≈B
G1=A≈B≈C
G0=A≈B≈C≈D

Fig. 5.77 Binary to Gray converter

5.8.4 9’s Complements of Decimal Number

Table 5.36 shows the truth table of IC 74184 to convert BCD number into 9’s complement. Here, ABCD
are BCD inputs and 9’s complement output are NA, NB, NC and ND. Figure 5.78 shows the circuit diagram
for converting BCD numbers into 9’s complement numbers.

Table 5.36 9’s complement of decimal number

Decimal Inputs Outputs 9’s complement

Numbers E G D C B A Y8 Y7 Y6 ND NC NB NA
0 0 0 0 0 0 0 1 0 1 1 0 0 1
1 0 0 0 0 0 1 1 0 0 1 0 0 0
2 0 0 0 0 1 0 0 1 1 0 1 1 1
3 0 0 0 0 1 1 0 1 0 0 1 1 0
4 0 0 0 1 0 0 0 1 1 0 1 0 1
5 0 0 0 1 0 1 0 1 0 0 1 0 0
6 0 0 0 1 1 0 0 0 1 0 0 1 1
7 0 0 0 1 1 1 0 0 0 0 0 1 0
8 0 0 1 0 0 0 0 0 1 0 0 0 1
9 0 0 1 0 0 1 0 0 0 0 0 0 0

Fig. 5.78 BCD to 9’s complement converter

 216 Digital Electronics: Principles and Applications

5.8.5 10’s Complements of Decimal Number

The truth table of IC 74184 to convert BCD number into 10’s complement is depicted in Table 5.37
where BCD inputs are A, B, C, and D and 10’s complement output are TA, TB, TC and TD. Figure 5.79
shows the circuit diagram for converting BCD numbers into 10’s complement numbers.

Table 5.37 10’s complement of decimal number

Decimal Inputs Outputs 10’s complement

Numbers E G D C B A Y8 Y7 Y6 TD TC TB TA
0 1 0 0 0 0 0 0 0 0 0 0 0 0
1 1 0 0 0 0 1 1 0 0 1 0 0 1
2 1 0 0 0 1 0 1 0 0 1 0 0 0
3 1 0 0 0 1 1 0 1 1 0 1 1 1
4 1 0 0 1 0 0 0 1 1 0 1 1 0
5 1 0 0 1 0 1 0 1 0 0 1 0 1
6 1 0 0 1 1 0 0 1 0 0 1 0 0
7 1 0 0 1 1 1 0 0 1 0 0 1 1
8 1 0 1 0 0 0 0 0 1 0 0 1 0
9 1 0 1 0 0 1 0 0 0 0 0 0 1

Fig. 5.79 BCD to 10’s complement converter

5.8.6 BCD to Binary Converter

Figure 5.80 shows the logic symbol of BCD to binary converter IC 74184. In six bit BCD to binary
conversion, the LSB of BCD inputs is connected to output Y0 and other BCD inputs are applied to pins
A through E. The binary outputs are obtained from Y1 to Y5 and Y6, Y7, & Y8 are not used for this BCD to
binary conversion as depicted in Fig. 5.81. The truth table of six bit BCD to binary conversion is given
in Table 5.38. The LSB of the BCD inputs, A0 and LSB of the binary outputs are not included in this
table. To convert a two decade BCD number into binary form, two 74184 ICs are required as depicted
in Fig. 5.82. Figure 5.83 shows the conversion of three decades BCD number into binary form using
six 74184 ICs.
 Combinational Logic Design 217

Fig. 5.80 Logic symbol of BCD binary Fig. 5.81 Six bit BCD to binary
converter IC 74184 converter using IC 74184

Table 5.38 Truth table of six bit BCD to binary converter

Enable Decimal BCD Inputs Binary Outputs

G Equivalent E D C B A Y5 Y4 Y3 Y2 Y1
B1 B0 A3 A2 A1
0 0-1 0 0 0 0 0 0 0 0 0 0
0 2-3 0 0 0 0 1 0 0 0 0 1
0 4-5 0 0 0 1 0 0 0 0 1 0
0 6-7 0 0 0 1 1 0 0 0 1 1
0 8-9 0 0 1 0 0 0 0 1 0 0
0 10-11 0 1 0 0 0 0 0 1 0 1
0 12-13 0 1 0 0 1 0 0 1 1 0
0 14-15 0 1 0 1 0 0 0 1 1 1
0 16-17 0 1 0 1 1 0 1 0 0 0
0 18-19 0 1 1 0 0 0 1 0 0 1
0 20-21 1 0 0 0 0 0 1 0 1 0
0 22-23 1 0 0 0 1 0 1 0 1 1
0 24-25 1 0 0 1 0 0 1 1 0 0
0 26-27 1 0 0 1 1 0 1 1 0 1
0 28-29 1 0 1 0 0 0 1 1 1 0
0 30-31 1 1 0 0 0 0 1 1 1 1
0 32-33 1 1 0 0 1 1 0 0 0 0
0 34-35 1 1 0 1 0 1 0 0 0 1
0 36-37 1 1 0 1 1 1 0 0 1 0
0 38-39 1 1 1 0 0 1 0 0 1 1
 218 Digital Electronics: Principles and Applications

Fig. 5.82 Eight bit BCD to to binary converter Fig. 5.83 BCD to to binary converter for three
for two decades using IC 74184 decades using IC 74184

5.8.7 Binary to BCD Converter

IC 74185 is used to convert binary to BCD form. Figure 5.84 shows
the six bit binary to BCD conversion. The LSB of binary inputs, B0
is directly connected with output Y0 and other binary inputs (B1, B2,
B3, B4, B5) are applied to pins A through E of IC 74185. The BCD
outputs are obtained from Y1 to Y5. The truth table of six bit binary
to BCD conversion is given in Table 5.39. The LSB of the binary
inputs, B0 and LSB of the BCD outputs are not included in this
table. Larger binary numbers can be converted to BCD form by
using more 74185 ICs. Figure 5.85 shows the conversion of eight
bit binary number into BCD form using three 74185 ICs. Fig. 5.84 Six bit binary to BCD
converter using IC 74185
 Combinational Logic Design 219

Table 5.39 Truth table of six bit binary to BCD converter

Enable Decimal Binary Inputs BCD Outputs

Equivalent E D C B A
G Y6 Y5 Y4 Y3 Y2 Y1
B5 B4 B3 B2 B1
0 0-1 0 0 0 0 0 0 0 0 0 0 0
0 2-3 0 0 0 0 1 0 0 0 0 0 1
0 4-5 0 0 0 1 0 0 0 0 0 1 0
0 6-7 0 0 0 1 1 0 0 0 0 1 1
0 8-9 0 0 1 0 0 0 0 0 1 0 0
0 10-11 0 0 1 0 1 0 0 1 0 0 0
0 12-13 0 0 1 1 0 0 0 1 0 0 1
0 14-15 0 0 1 1 1 0 0 1 0 1 0
0 16-17 0 1 0 0 0 0 0 1 0 1 1
0 18-19 0 1 0 0 1 0 0 1 1 0 0
0 20-21 0 1 0 1 0 0 1 0 0 0 0
0 22-23 0 1 0 1 1 0 1 0 0 0 1
0 24-25 0 1 1 0 0 0 1 0 0 1 0
0 26-27 0 1 1 0 1 0 1 0 0 1 1
0 28-29 0 1 1 1 0 0 1 0 1 0 0
0 30-31 0 1 1 1 1 0 1 1 0 0 0
0 32-33 1 0 0 0 0 0 1 1 0 0 1
0 34-35 1 0 0 0 1 0 1 1 0 1 0
0 36-37 1 0 0 1 0 0 1 1 0 1 1
0 38-39 1 0 0 1 1 0 1 1 1 0 0
0 40-41 1 0 1 0 0 1 0 0 0 0 0
0 42-43 1 0 1 0 1 1 0 0 0 0 1
0 44-45 1 0 1 1 0 1 0 0 0 1 0
0 46-47 1 0 1 1 1 1 0 0 0 1 1
0 48-49 1 1 0 0 0 1 0 0 1 0 0
0 50-51 1 1 0 0 1 1 0 1 0 0 0
0 52-53 1 1 0 1 0 1 0 1 0 0 1
0 54-55 1 1 0 1 1 1 0 1 0 1 0
0 56-57 1 1 1 0 0 1 0 1 0 1 1
0 58-59 1 1 1 0 1 1 0 1 1 0 0
0 60-61 1 1 1 1 0 1 1 0 0 0 0
0 62-63 1 1 1 1 1 1 1 0 0 0 1
 220 Digital Electronics: Principles and Applications

Fig. 5.85 Eight bit binary to BCD converter using IC 74185

5.9 HAZARDS
When the designer designs any combinational and sequential logic circuits, the designer should take
certain restrictions and precautions to ensure proper operation of the circuits and to get proper result.
Consequently, the designer should have a clear understanding of the mechanism, which produces any
malfunction in combinational and sequential circuits, called as hazards. When an input changes from ‘0’
to ‘1’ or ‘1’ to ‘0’, there is a momentary unexpected transient output change due to propagation delay
of logic gates. This momentary unexpected transient output change is known as output glitch. A hazard
always exists in a combinational circuit when it produces an output glitch while one or more inputs
change. There are two types of hazard which generally occur in digital systems:
∑ Static hazards
∑ Dynamic hazards
A Static hazard is a momentary change in output when an input signal undergoes a momentary transition,
but there will be no effect on steady state output. This type of hazard is present in combinational circuits
as well as gate-implemented asynchronous circuits. There are two types of static hazard namely static -0
hazard and static - 1 hazard. In static -0 hazard, the output should
be ‘0’ but goes momentary to ‘1’ as a result of an input change as
shown in Fig. 5.86(a). But in static - 1 hazard, the output should
be ‘1’ but goes momentary to ‘0’ as a result of an input change
as illustrated in Fig. 5.86(b). The Static -1 hazard present in 2-
level AND-OR circuits and the static -0 hazard present in 2-level Fig. 5.86 (a) Static 0-hazard and
OR-AND circuits. These hazards can be detected and eliminated (b) Static 1-hazard
 Combinational Logic Design 221

for 2-level circuits using K-maps. Dynamic hazards occur when the
output changes several times before reaching its steady state value
as a result of a single change in input as depicted in Fig. 5.87.
Fig. 5.87 Dynamic hazards
5.9.1 Propagation Delay
When a two-inputs NAND gate or a NOT gate acts as an inverter, there will be a finite time delay
between an input change and the corresponding change of the output. This time delay is called as
propagation delay of gate, which is depicted in the timing diagram. In Fig. 5.88, the change in A from
–
‘0’ to ‘1’ is followed by a change in A from ‘1’ to ‘0’ with a propagation delay, Dt1 seconds. Similarly
–
while A changes from ‘1’ to ‘0’ followed by a change in A from ‘0’ to ‘1’ with a propagation delay, Dt2
seconds. So far the combinational circuit analyses have discussed in this chapter ignoring propagation
delays and consider only steady-state output. To study the hazard of any combinational and sequential
logic circuits, we should consider the propagation delays of all circuit gates.

Fig. 5.88 Propagation delay of gates

5.9.2 Generation of Static -1 Hazards in Combinational Circuit

When an input to a combinational circuit, which is implemented by AND and OR gates is changing,
Static-1 hazard may be generated at the output of the circuit. The static-1 hazard occurs due to different
path lengths in the combinational network which introduce different time delays. For example, the
–
Boolean function O = AC + BC may be implemented by using inverter, AND and OR gates as shown in
Fig. 5.89(a) and K-map of this function is illustrated in Fig. 5.89 (b).
A static -1 hazard exists in the following AND-OR circuit when A=1, B=1 and C changes from ‘1’
to ‘0’. The timing diagram of the Boolean function is shown in Fig. 5.90. Assume all gates have same
propagation delay Dt. In this circuit there are two paths, the first path via G1, G2 and G4 and the second
path via G3 and G4. As all gates have the same time delay, it is evident that the delay through the first
path is greater than the delay through the second path.
 222 Digital Electronics: Principles and Applications

Fig. 5.89 (a) Logic diagram of O = AC + BC and (b) Three variables K-map

For the change in C from ‘1’ to ‘0’ and

there is a change in the output of G1 from ‘0’
to ‘1’ with a propagation delay Dt followed
by the output of G2 changing from ‘0’ to ‘1’.
For the other path of the circuit, the output
of G3 first changes from ‘1’ to ‘0’ with a
propagation delay Dt. As the G3, G4 path has
the shorter time delay; it is clear from Fig.
5.90 that the change in output propagated
along this path occurs earlier in time than the
change propagated along the G1, G2 and G4
path. Hence, for a short period of time, the
output signal is low or logic level ‘0’ when A
= 1, B = 1 and C changes from‘1’ to ‘0’.

5.9.3 Elimination of Static

-1 Hazards
A static-1 hazard occurs in AND-OR circuits Fig. 5.90 Timing diagram of O =AC– + BC when A=1
when an input variable and its complement and B=1 and C changes from 1 to 0.
are connected to two different AND gates.
Static -1 hazards can be found using K-maps by finding adjacent ‘1’ cells that are covered by different
product terms. To eliminate static-1 hazards, additional product terms or prime implicants are required
to cover such cells, which covering the transition of the variable causing the hazard. For the previous
example, the static-1 hazard can be eliminated by including the additional product term AB.
–
The consensus product term for the Boolean equation O = AC + BC is AB, and this can be added to the
– –
original equation O = AC + BC without altering its value. Then output equation will be O = AC + BC +
–
AB . For the condition A=1 and B=1, the equation reduces to O = C + C +1 and the value of the function
–
O remains at ‘1’ even if C and C are simultaneously equal to ‘0’ for a very short period of time.
The effect of adding the consensus product term can be studied by examining the K-map plot of the
function before and after the addition of the consensus product term. The K-map of original Boolean
function is shown in Fig. 5.89(a). The K-map plot of the function, after the inclusion of the consensus
 Combinational Logic Design 223

product term is shown in Fig. 5.91(a). The comparison of the two K-map plots is that before the addition
of the consensus product, there are two l’s in adjacent cells not covered by the same prime implicant. On
covering these two adjacent l’s by the same prime implicant, as in Fig. 5.91(b), the hazard is removed
–
from the circuit. The hazard-free circuit for the Boolean function O =AC + BC + AB is shown in Fig.
5.91(b), and it will be observed that an additional AND gate has been introduced for generating the
required consensus product term AB.

–
Fig. 5.91 (a) Three variables K-map; (b) Implementation of hazard-free function O = AC + BC + AB

5.9.4 Elimination of Static-0 Hazards

A static-0 hazard occurs in OR-AND circuits when an input variable and its complement are connected
to different OR gates. The static-0 hazards can be determined using K-maps by finding adjacent ‘0’ cells
that are covered by different sum terms. To eliminate static-0 hazards, additional sum terms or prime
implicants are needed to cover such cells , which covering the transition of the variable causing the
hazard. Figures 5.92 (a) and (b) show the K-map of three variables function with and without hazard
respectively.

Fig. 5.92 (a) Three variables K-map and (b) Three variables K-map hazard free

The logic diagram of the OR AND circuit

– –
of O =(B + C)( A + C ) is shown in Fig. 5.93.
–
The consensus term for this equation is (A + B)
and this can be included in the above equation
without altering its value, so that the output
– – –
function will be O = (B + C)( A + C )(A + B). The
–
logic diagram of the Boolean function O = (B +
– –
C)( A + C )(A + B) is illustrated in Fig. 5.94.
– –
Fig. 5.93 Logic diagram of O = (B + C)( A + C )
 224 Digital Electronics: Principles and Applications

– – –
Fig. 5.94 Logic diagram of O = (B + C)( A + C )(A + B ) hazard-free

– – – – –
When A = 0 B = 0, then the Boolean function O = (B + C)( A + C )(A + B) becomes O = C.C .0 = 0.
With the inclusion of the consensus term, the value of the function is always ‘0’ irrespective of whether
–
C and C are simultaneously equal to ‘1’.
–
The static-0 hazard can be eliminated by the inclusion of the consensus term (A + B). The consequential
hazard-free circuit is shown in Fig. 5.94. Elimination of the hazard requires the inclusion of an additional
gate which generates the required consensus term.
When we want to find a static-0 hazard, we use the K-map plot of the function which identifies those
combinations of the variables that cause the function value to be ‘0’. To obtain a plot of the 0-terms,
the inverse of the original function O must be plotted.Consider the equation of the original Boolean
function is:
– –
O = (B + C)( A + C )
– –
After inverting of O = (B + C)( A + C ), we find
– – –
O = BC + A C
Then inverse function is plotted as shown in Fig. 5.92(a). It is clear from this figure that the two 0’s in
the adjacent cells 010 and 011 are not covered by the same prime implicant. Subsequently the additional
–
prime implicant A B must be added with the original function, we get
– – – –
O = BC + A C + A B.
– – – –
Again inverting O = BC + A C + A B , we obtain the hazard-free function after incorporating the
consensus term to the function equation. Therefore the static -0 hazard-free function is
– – –
O = (B + C)( A + C )(A + B).
The algorithm for finding static 0-hazards are given below:
Step-1: Plot K-map of the inverse function as shown in Fig. 5.95 after 0s are replaced by 1s and 1s
are replaced by 0s in Fig. 5.92.
Step-2: Look for adjacent 1s not covered by the same prime implicant.
Step-3: Introduce additional prime implicants to cover all adjacent 1’s that are not covered by the
same prime implicant.
Step-4: Alter the inverse equation by incorporating the additional prime implicants.
Step-5: Invert the modified equation to get the hazard-free structure of the function.
 Combinational Logic Design 225

5.9.5 Dynamic Hazards

Dynamic hazards occur in combinational logic circuits when
the output changes several times before reaching its steady state
value as a result of a single change in input. Generally, it is
expected by the circuit designer that the output changes either
0 Æ 1 or 1Æ 0. But in practice, when the output transitions are
0 Æ 1 Æ 0 Æ 1 then a dynamic hazard has occurred. Similarly,
if an output changes from 1Æ 0 Æ 1 Æ 0 in place of expected Fig. 5.95 Three variables K-map
change 1Æ 0, then a dynamic hazard is present in the circuit. hazard free

In the above cases, there is a minimum of three changes which is appeared at the output as shown
in Fig. 5.87. The dynamic hazard occurs due to the factorisation of a Boolean function. If the function
has different fan-in, there will be different path lengths through a circuit to obtain a output for specified
inputs. On the other hand, the gates which are used in the circuit may have different time delays. Due
to different path lengths and different time delays, there is some possibility to exist a dynamic hazard in
the combinational logic circuit. Consider the typical Boolean function:
– –
O = (AC + BC )(A + C )
Figure 5.96 shows the implementa-
– –
tion of function O = (AC + BC )(A +
C) with AND and OR gates. There are
three different paths through this cir-
cuit for the variable C and consequent-
ly, there is a possibility that a dynamic
hazard exists in the circuit. The three
paths of the circuit are as follows:
1. Through gates G4, G7 and G8 Fig. 5.96 Logic circuit of dynamic hazard
2. Through gates G3, G5, G7 and G8,
and
3. Through gates G1, G6 and G8.
As there three variables A, B, and C, there are eight possible combinations of A, B, and C. Because
of multiple paths taken by the signal variable C in this circuit, the dynamic hazard is preset. Fig. 5.97
shows the timing diagram of the circuit when A=1, B=1, and C changes from 0 to 1. It is depicted in this
figure that the output of G3 gate has a time delay Dt1 and the output of G6 gate has a time delay Dt2 . The
output of G5 and G4 gates have a time delay Dt3 and Dt4 respectively. As ∆t4 > ∆t3 , a static 1 -hazard will
be present at the output of G7 gate. In case Dt4> Dt3> Dt2 there will be a dynamic hazard at the output of
G8 gate as shown in Fig. 5.97.
If the designer is designed the circuit either sum of products form (AND OR) or product of sum
form (OR AND), in such a way that there are no static hazards present in the circuit. When there will be
no static hazards, then the circuit will also be dynamic hazards free. To design a dynamic hazards free
circuit of four or more variable Boolean functions, the same procedure can also be followed.
 226 Digital Electronics: Principles and Applications

Fig. 5.97 Timing diagram of dynamic hazard when A = 1 and B = 1 and C changes from 1 to 0

5.10 FAULT DETECTION OF COMBINATIONAL LOGIC CIRCUIT

The simplest method of detecting faults in a combinational logic circuit is to apply every possible input
combination and compare the circuit response with the known truth table of the circuit. If there is any
fault in the circuit, there will be some mismatch between the response of the circuit and truth table and
it is known as faulty response of the circuit. But this method has certain limitations as the numbern of
input variables ‘n’ increases, the number of tests required increases exponentially and is equal to 2 in
case of a combinational circuit.
Figure 5.98 shows a typical combinational logic diagram and its response with fault and without fault
is given in Table 5.40. F1 is the response, when there is no fault and F2 response can be obtained, if there
is a fault present in the circuit. The faulty response F2 is obtained, whenever A = B = C = 0. When input
line ‘m’ is held permanently and erroneously at ‘0’, the output of G1 is then ‘0’ whenever B = 1 or 0. If
the input line ‘n’ is also held permanently and erroneously at ‘0’, the output of G2 is then ‘0’ whenever
A = 1 or 0. The fault F2 is revealed by applying A = 0, B = 0 C = 0 and examining the output. Therefore,
this fault is occurred while two input lines ‘m’ and ‘n’ are erroneously low.
An examination of the circuit in conjunction with the expected circuit response can revel the nature
of the fault. This informal fault analysis of the circuit has been carried out only by inspection. Although
it is desirable that more formal techniques for testing should be developed. In this section fault analysis
of combinational logic circuits are explained.
 Combinational Logic Design 227

Table 5.40

Inputs
Response Response
without fault without fault
A B C F1 F2
0 0 0 1 0
0 0 1 0 0
0 1 0 1 1 ––
Fig. 5.98 Logic diagram of F = AB + A C
0 1 1 0 0
Generally, unskilled instructors and engineers always
1 0 0 0 0 faced problems with a combinational logic circuit which
1 0 1 0 0 contains a unknown fault. To find the fault, they often
1 1 0 1 1 resort to remove semiconductor components at random
and attempting to test them. Sometimes, they replace
1 1 1 1 1
the components with new components without testing
the old one. This is not a right method of fault detection
and location for the following reasons:
1. When a typical digital system has many components, any fault component will be chosen at
random for removal.
2. Due to remove components by inexperienced engineers and their replacement can damage abso-
lutely good components and the circuit board.
3. In digital systems, the most common faults are mechanical failure of switches and faults in sol-
dering connection such as open circuit resistors and open circuit capacitors. Sometimes ICs and
other devices are also unlikely malfunction.
In good practice that no component should be removed or replaced until it has been proven faulty. To
prove that a component in the combinational logic circuit is faulty, it requires that voltage and continuity
checks should be performed upon the circuit while it is powered and the component should be subjected
to typical signals. The output is examined for the correct output signals.
Suppose a typical system consists of ‘n’ components connected in sequence, we want to locate a
fault in the circuit. Then signal tracing will be employed in situations where the intermediate signals are
accessible at each point in the chain. Using this technique, the signals at the outputs of the components
are examined and compared with the expected response. When correct signals are observed at the input
to a certain component but not at its output, then it is clear that the fault must be associated closely with
the component. This does not mean that this particular component is faulty. It is also possible that the
power supply to this component may be failed.
Generally, there are two types of test which are carried out on any combinational logic circuits.
1. Fault detection test, that is used to detect if there any fault in the system.
2. Fault location test, which is used to locate and identify faults.
To locate the fault as well as faulty component, assume that the fault is equally likely to occur in
any of the ‘n’ links of the chain. The correct procedure is not to trace the signal in turn through each
component in the signal chain, for this method requires, on average n/2 tests before the faulty stage
 228 Digital Electronics: Principles and Applications

is located. The more efficient method is binary division, where firstly the presence or absence of the
correct signal is established halfway through the chain of ‘n’ stages. Depending upon the result of the
single test, either the entire first half or the entire last half of the circuit can therefore be eliminated
from further attention and subsequent tests confined to the faulty half. The same principle can then be
applied to this half of the circuit and so on. By successive binary divisions, the fault can be isolated to
one single stage. With a large number of stages, this procedure requires only log2(n) tests to locate the
faulty stage. Therefore, significantly less than the average of n/2 tests are required for tracing the signal
in turn through each stage. For example, if n = 64 sequential signal tracing requires 32 tests on average,
where as binary division signal tracing require 8 tests.
All faults are either stuck-at 0 (s-a-0) or stuck-at-1 (s-a-1) in any combination logic circuit. Stuck-at-
0 means that the line is permanently at logic level ‘0’ and stuck-at-1 means that the line is permanently at
logic level ‘1’ irrespective of logic level that is actually supposed to be present on that line. This widely
used fault model does not cover all possible faults. For example, a short circuit of any line to ground
fault can be represented by a s-a-0 fault. While an open circuit on an input line to a TTL gate will cause
that input to float at a voltage corresponding to an unreliable and noise logic level ‘1’, causing an s-
a-1 fault. When any two paths of combinational logic circuit are inadvertently connected together, the
bridging or short circuit fault occurs. In this section, different faults of a 2-inputs AND gate and a typical
combinational logic circuit are discussed.

5.10.1 Faults of a 2–inputs AND Gate

Figure 5.99(a) shows a 2-inputs AND gate and it has two input lines, levelled ‘m’ and ‘n’ respectively,
and one output line labelled, o. When there is no fault, the input-output relationship of AND gate is
shown Table 5.41(a).There are six possible single faults such as any one of m, n and o paths are either
s-a-1 fault or s-a-0 fault.
When the line ‘m’ has a s-a-0 fault as depicted in Fig. 5.99 (b), it is required to determine the test
that will detect this fault. If input B is at logic level ‘1’ level or at logic level ‘0’, the gate output will
be permanently held at ‘0’ while the other input A may be at logic level ‘1’ or at logic level ‘0’.The test
result is given in Table 5.41(b). Similarly,
while the line ‘m’ has a s-a-1 fault as shown
in Fig.5.99(c), input B is at logic level ‘1’ or
at logic level ‘0’, the gates output will be ‘1’
or ‘0’ although the other input A may be at
logic level ‘1’ or at logic level ‘0’. The test
result is illustrated in Table 5.41(c) For a s-a-
1 fault on ‘n’ path as shown in Fig. 5.99(d),
input A=1 is the gate enabling signal while
the complement of the stuck-at fault value
must be applied at input B, giving B = 0.
Therefore the required test is A = 1 and B=0
and the possible test results are shown in Fig. 5.99 (a) 2-inputs AND gate and (b) 2-inputs AND
gate with s-a-0 at m and (c) 2-inputs AND gate with
Table 5.41(d). s-a-1 at m and (d) 2-inputs AND gate with s-a-1 at n
 Combinational Logic Design 229

Table 5.41(a)

Input A Input B Output O Remarks

0 0 0 Normal output. There
0 1 0 is no fault
1 0 0
1 1 1

Table 5.41(b)

Input A Input B Output O Remarks

0 0 0 As m line at s-a-0 fault,
0 1 0 output is always 0
1 0 0
1 1 0

Table 5.41(c)

Input A Input B Output O Remarks

0 0 0 As m line at s-a-1fault,
0 1 1 output is 1 when A = 0,
B = 1 and A = B = 1
1 0 0
1 1 1

Table 5.41(d)

Input A Input B Output O Remarks

0 0 0 As n line at s-a-1 fault,
0 1 0 output is 1 when A = 1,
B = 0 and A = B = 1
1 0 1
Fig. 5.100 Path sensitisation when
1 1 1 s-a-0 fault at m

5.10.2 Faults of a Combinational Logic Circuit

The determination of a test set for a single gate, where there is direct access to the input and output, is
achieved by enabling or sensitising the gate. Figure 5.100 shows path sensitisation for testing s-a-0 fault
on line ‘m’. Assume gates G1 and G2 are present inside the IC and their outputs are not accessible. When
a s-a-0 fault occurs at line ‘m’, the sensitisation of two gates G1 and G3 are required to detect the said
fault. Here a sensitised path from input A to the output F is considered and detected by thick line.
Generally, any combinational logic circuit consists of many gates which are connected in network.
Figure 5.100 shows a typical combinational logic circuit and a s-a-0 fault at ‘m’ path. The output of D
and E paths are not directly accessible as D and E paths in side the IC. So that output must be detected
 230 Digital Electronics: Principles and Applications

at output F. Therefore, the sensitisation of G1 and G2 gates are required. A sensitised path from A to F is
shown in Fig. 5.100. When B = 0 and C = 0, point D must be set at 0. The sensitivity of gate G2, point
E must be set at A and the normal output F = A. Consequently, there is no difference between normal
output and fault output at B = 0 and C = 0. Similarly, the fault can not be detected at B = 0 and C = 1.
When B = 1, C = 0 and A = 1, the normal output is 1, but the response of the circuit is 0 due to s-a-0
fault at m. In the same way, if B = 1, C = 1 and A = 1, the normal output is ‘1’, but the response of the
circuit is ‘0’. The results of combinational logic circuit are summarised in Table 5.42. Some times faults
are undetectable, when circuit malfunction s-a-0 and s-a-1 faults. During design of combinational logic
circuit, the design will develop the hazard free circuit to avoid undetectable fault.

Table 5.42

Path A-D-F and s-a-0 fault at m

Gate sensitisation input signals B = C =0 B=0C=1 B=1C=0 B=1C=1
Fault test condition A=0 A=1 A=0 A=1 A=0 A=1 A=0 A=1
Normal output F 1 0 0 0 1 1 0 1
Faulty output F 1 0 0 0 1 0 0 0

5.10.3 Bridge Faults

When any two lines of a combinational logic circuit is shorted, there is a short circuit fault in the circuit.
This type of faults occur due to careless soldering that leaves some soldering materials between two
adjacent lines and subsequently these lines are connected. This short circuit fault is known as bridge
fault. Figure 5.101 (a) shows the bridge fault m-p-o path and Fig. 5.101 (b) shows the bridge fault n-q-o
path. The test results of bridge fault are given in Table 5.43.
– – –
While inputs B and A have same logic values (B = 0 = A or B = A = 1) and though ‘m’ and ‘n’ paths
are interconnected, no faults can be detected as inputs of gates G1 and G2 are held at their correct val-
–
ues. But when B and A inputs
are driven to complementary
–
logic levels means B = 0, A =
–
1 or B = 1, A = 0, the circuit
will be different from actual
required output. Then there are
different possibilities of output Fig. 5.101 Bridge fault (a) m-p-o path (b) n-q-o path
as follows:
1. When the input signal is supposed to be set at 1 may be pulled down to 0, if the circuit is made
with TTL gates.
2. When input signal is supposed to be set at 0 may be pulled up to 1, if the circuit is made with ECL
gates.
3. Both inputs may be pulled to an indeterminate voltage level, which cannot be interpreted as either
logic level ‘1’ or logic level ‘0’. The driving gates may fail to operate properly and consequently
some stuck at faults occur on gates.
 Combinational Logic Design 231

Table 5.43
Path m-p-o path n-q-o path
Input signals A = 0, B = 0, C = 0 A = 1, B = 1,C = 1
Normal path signals p = 0, q = 1, and o = 1 p = 1, q = 0 and o = 1
Fault m-n bridge fault m-n bridge fault
– –
Test signals (A , B) = (1,0), p = 0, q = 0 and o = 0 ( A , B ) = (0,1), p = 0, q = 0 and o = 0
Normal output 1 1
Faulty output 0 0

SUMMARY
Combinational logic circuits can be used to design any type of logic operations. Some of these logic operations are
multiplexing, demultiplexing, encoding, decoding and arithmetic operations of binary numbers. In this chapter, the
working principle of multiplexers, demultiplexers, decoders and encoders are explained and their applications are also
incorporated. Commonly used MSI ICs –7447 BCD to seven segment decoder, 7442 BCD to Decimal decoder, 74154,
74148, 74147, 74157, 74158, 74150, 74151A, 74237 are discussed. When MSI ICs are used to design combinational
logic circuits, digital system design will be simplified and efficient. In this chapter, hazards and fault detection of
combinational logic circuits are explained.

MULTIPLE CHOICE QUESTIONS

1. A multiplexer has
(a) One data input and two or more than two data outputs
(b) One data output and two or more than two data inputs
(c) One data output and a number of data input and a number of select inputs
(d) One data output and a number of select inputs
2. A multiplexer can be used as
(a) Counter (b) Shift register
(c) Combinational circuit (d) 7 - segment display
3. A multiplexer, with 3-bit data select inputs, is a
(a) 4:1 multiplexer (b) 8:1 multiplexer (c) 16:1 multiplexer (d) 32:1 multiplexer.
4. A two variable Boolean logic function can be implemented by
(a) 4:1 multiplexer, (b) 1:4 demultiplexer, (c) NAND gate (d) NOR gate
5. A demultiplexer has
(a) One data input and two or more than two data outputs
(b) One data output and two or more than two data inputs
(c) One data output and a number of data input and a number of select inputs
(d) One data output and a number of select inputs
6. A demultiplexer can be used as
(a) A counter (b) A flip-flop
(c) A combinational circuit (d) A 7 - segment display
 232 Digital Electronics: Principles and Applications

7. The output of a 2-inputs gate is ‘1’ and its inputs are unequal. This is a
(a) EX-OR gate (b) AND gate (c) NOR gate (d) AND-gate
8. The ————— gate is used as two bits comparator.
(a) AND ( b) OR (c) NAND (d) EX-OR
9. Multi channel signals can be transmitted through a single channel by using _________.
(a) Demultiplexers (b) Encoder (c) Decoder (d) Multiplexer
10. Minimisation of Boolean logical expressions helps to reduce
(a) Space (b) Number of gates
(c) Cost (d) Space, number of gates and cost
11. The number of 2-line-to-4-line decoders are used to design a 4-line to 16-line decoder is
(a) 2 (b) 4 (c) 5 (d) 6
12. In 7-segment display system, zero blanking is used to blank-out
(a) All the leading zeros ( b) All the trailing zero
(c) The zero in the MSB (location) (d) a and b
13. In 8:3 priority encoder, highest priority is given on
(a) 7 (b) 0 (c) 9 (d) F
14. In 16:4 priority encoder, lowest priority is given on
(a) 7 (b) 0 (c) 9 (d) F
15. In binary to Gray converter, _______ gate is used
(a) AND ( b) OR (c) NAND (d) EX-OR

REVIEW QUESTIONS
5.1. (a) Define decoder.
(b) Design a decoder circuit to convert binary numbers to decimal.
5.2. (a) Explain cascade decoder with example
(b) Design a 5-to-32 line decoder using 2-to-4 line decoder and 3-to-8 line decoder.
5.3. A combinational circuit is defined by the following equations
F1 = AB+ABC; F2 = A+B+C; F3 = AB
Design a circuit that can implement the above equations using a decoder and NAND gates.
5.4. A combinational circuit is defined by the following equations
– – –
F1=ABC+ABC ; F2=A+B+C+D; F3=A+B+CD+AD; F4=ACD+A CD+BCD+BCD
Design a circuit that can implement the above equations using a decoder with NAND gates.
5.5. Implement the following 4 variables functions using a decoder having active low outputs and NAND
gates.
F1=S (0,1,3,9,12,14); F2=S(5,9,10,12,13,15)
F3=P (0,3,8,11,12,15); F4=P(1,2,7,8,11,12,14)
5.6. Design a 3 to 8 line decoder using NOR gates only and draw its circuit.
5.7. What will be the output of decoder 74154, if the enable is low, the data input low and the select
inputs are as follows?
(a) 1110 (b) 1001 (c) 0101 (d) 0000
 Combinational Logic Design 233

5.8. Draw a diagram for 7-segment LED display driver and explain its operating principle.
5.9. (a) Define encoder. Distinguish between encoder and decoder.
(b) Design a encoder circuit for 10 line to 4 line priority encoder.
5.10. (a) Describe the operation of a multiplexer using functional block diagram.
(b) Enumerate some of the applications of multiplexers.
(c) Explain how Boolean functions will be implemented using multiplexers.
5.11. (a) What is demultiplexers? Distinguish between
(i) A multiplexer and demultiplexer
(ii) Decoder and demultiplexer
(b) Draw the logic diagram of a one line to four line demultiplexers.
5.12. Implement the following 3-variable Boolean functions using 4:1 multiplexers:
(a) F1= Sm(0,2,3,5,7)
(b) F2=Sm( 1,3,4,6,7)
(c) F3=Sm( 0,2,4,5,6,7).
5.13. Implement the following 4-variable Boolean functions using 8:1 multiplexers
(a) F1=Sm(0,1,3,5,6,8,9,11,12,13)
(b) F2=Sm( 0,7,8,9,10,11,15)
(d) F3=Sm(0,1,3,5,9,10,11,13,14,15)
5.14. Implement the 6-variables Boolean functions
f = Sm( 0,1,3,5,7,12,14,16,18,20,22,26,28,30,32,34,37,39,41,43,45,50,51,53,60,61,62,63) using
eight-input multiplexers and 4-input multiplexers
5.15. Design a BCD to 7 segment decoder using
(a) Dual 4:1 multiplexers
(b) 1;16 demultiplexer
(c) BCD to decimal decoder
5.16. Design a 32:1 multiplexers using two 16:1 multiplexers.
5.17. Design a 1:32 demultiplexer using 1:8 and 1:16 demultiplexer.
5.18. Design a logic circuit for converting Excess-3 to 8421 code.
5.19. Design a GREY to BCD-code converter using MSI ICs and logic gates.
5.20. Design a pulse train 11011001 using MSI ICs.
5.21. Draw a connection diagram to show how multiplexer 74151 should be used to implement the Boolean
– – –
function F = A BC + AB C + ABC + ABC
5.22. Draw a diagram to show how IC 74237 can be used as an 8-output data distributor.
5.23. Design a four digit 7 segment display system.
5.24. Design a 5¥3 dot matrix display system to display alphanumeric character E.
5.25. Design a 64:1 multiplexer using 8:1 and 16:1 multiplexers.
 CHAPTER

6
ARITHMETIC
LOGIC CIRCUITS
6.1 INTRODUCTION
The arithmetic and logical operation of digital circuits are already explained in combinational logic
chapter. The design and implementation of arithmetic and logic circuits using gates are also explained
in that chapter. Now-a days, Medium Scale Integrated (MSI) circuits are used in multibit addition,
multibit subtraction, and all arithmetic logic operations. Presently, MSI ICs are available in market. But
all arithmetic functions are not available in a standard MSI IC. The designer should select a particular
ALU IC and can modify its operation as per requirement. In this chapter, arithmetic and logic operations
such as addition, subtraction, multiplication and division are explained with the help of logic gates and
integrated circuits.
6.2 BINARY ADDITION
To design binary adder circuits, the basic knowledge
of arithmetical operations in base 2 is required. Figure
6.1 shows the governing rules of addition of two binary
numbers. When two ones are added, then sum is zero and
a carry bit is generated. Then the carry bit is added to the
next pair of bits. In this section, half adder, full adder and
Fig. 6.1 Addition of two binary numbers
4-bit adder circuits are explained.
6.2.1 The Half Adder
A half adder is the simplest digital adder and it is used
Table 6.1 Truth table of half adder to add two binary digits, an addend (A) and an augend
Inputs Outputs (B). After addition of two binary digits A and B, the sum
Addend Augend Sum Carry (S) and carry (C) are generated. This carry signal may be
(A) (B) (S) (C) used to the next stage of the addition. Table 6.1 shows
0 0 0 0 the truth table for adding two binary digits A and B. The
0 1 1 0
1 0 1 0
Boolean expressions of the sum (S) and carry (C) are
– –
1 1 0 1 Sum S = A⊕B = AB + A B
Carry C = A.B
 Arithmetic Logic Circuits 235

The sum can be implemented by using an Exclusive-OR gate and an AND gate can be used for carry
generation as shown in Fig. 6.2(a). Figure 6.2(b) shows the implementation of the sum and carry functions
using AND and OR gates. A block diagram representation of a half adder (HA) is also depicted in Fig. 6.3.

Fig. 6.2 Implementation of half adder (a) Using EX-OR and AND logic gates
(b) Using AND and OR logic gates

Fig. 6.3 Block diagram of half adder

6.2.2 The Full Adder

A half-adder only adds the two input bits, but a full adder can add three input bits, an addend (A), an
augend (B) and carry input (Cin) generated by the previous stage addition. It has two outputs, sum (S)
and carry out (Cout). Table 6.2 shows the truth table of full adder. K - maps and logic gates are generally
used to implement the sum (S) and carry out (Cout).
Table 6.2 Truth table of full adder
Inputs Outputs
Carry in Addend Augend Sum Carry out
(Cin) (A) (B) (S) ( Cout)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
The block diagram of full adder is shown in Fig.
6.4. In this figure, inputs are the two binary bits A and
B and the carry input (Cin) and outputs are the sum
output (S) and the carry-out (Cout).
The sum (S) and carry-out ( Cout) can be expressed
in Boolean equations from the truth table as follows: Fig. 6.4 Block diagram of Full adder
 236 Digital Electronics: Principles and Applications

–– – — –—
Sum S = A B Cin + A BCin + AB Cin + ABCin
– – —
Carry C = A BCin + AB Cin + ABCin + ABCin
The sum can also be expressed as
– – — –— – ———
S = A (B Cin + BCin) + A(B Cin + BCin) = A (B ⊕ Cin) + A B ⊕ Cin )
Finally, sum is S = A⊕B⊕Cin and can be implemented using an three inputs EX-OR gate.
The carry out may be rewritten as
– – —
C = (A B + AB )Cin + AB(Cin + Cin) = (A⊕B)Cin+ AB
The K-maps for sum and carry out are shown in Fig. 6.5(a) and (b) respectively. The carry-out
equation may be written in simplified form using K-map as given below:
Cout = AB + BCin+ ACin = (A⊕B)Cin+ AB

Fig. 6.5 K-map of Full adder (a) for sum (b) for carry out

Implementation of full adder circuits using AND, OR and EX-OR gates are depicted in Fig. 6.6(a)
and Fig. 6.6(b). Full adder circuit can also be implemented with the help of two half-adder circuits as
shown in Fig. 6.7. The first half adder is used to add two inputs A and B and generate sum S′ and carry
output C′. Then second half adder combines the sum (S′) and carry input (Cin) and generate final sum S
and carry out C′′. The final carry can be produced by using OR operation between C′ and C′′.

Fig. 6.6(a) Implementation of full adder using AND and OR gates (b) Implementation of full ad-
der using EX-OR, AND and OR gates
 Arithmetic Logic Circuits 237

Fig. 6.7 Block diagram of full adder using half adders

6.2.3 The 4 Bit Binary Full Adder

The addition of two 4-bit digit binary
numbers, A = A3 A2 A1A0 and B=B3B2B1B0
is shown in Fig. 6.8. Initially, the lest
significant bits A0 and B0 are added with
carry input Cin and generate a sum S0
and a carry C0. If there is no carry input
(Cin=0), only two lest significant bits A0
and B0 will be added. The carry output Fig. 6.8 Addition of two 4 bit numbers
of adder C0 can be used as carry input
of the next adder operation. Then A1, B1
and carry C0 are added to generate a sum
S1 and a carry C1. Similarly, A2, B2 and
carry C1 are added to produce S2 and a
carry C2 , which is used as carry input
of the next adder. In the same way, A3,
B3 and carry C2 are added to generate a
sum S3 and a carry C3. After completion
of addition, the sum is S3S2S1S0 and
carry output is C3.
The addition of two 4-bit numbers Fig. 6.9 Block diagram of 4 bit adder using full adders
and an half adder
can be implemented by using full
adder and half adder circuits. When
initial carry input Cin=0, the full adders
and one half adders can be used to
implement addition of two 4-bit
numbers as depicted in Fig. 6.9. The
above operation can be done using
four full adder circuits as shown in Fig.
6.10 when carry input (Cin) of first full
adder is grounded. These circuits are
also known as ripple through adder for
the reason that carries from one stage
of the adder may be ripple through a Fig. 6.10 Block diagram of 4-bit adder using full adders
 238 Digital Electronics: Principles and Applications

number of the subsequent stages.

In this case, carry generated form
first full adder is ripple through
all the full adders and finally the
carry-out is generated from the
last stage of addition.
Similarly, an ‘n’ bit adder can
be build by connecting proper
number of full adders as shown
Fig. 6.11 Block diagram of ‘n’ bit adder using full adders in Fig. 6.11. In this case, the carry
output are passed from one full
adder to the next full adder but last carry out put will be the final carry output of the addition. The final
result of ‘n’ bit adder is the sum S = SN-1 SN-2….S1 S0 and carry out Cout=CN-1.
Commonly used MSI ICs for addition are IC74181, IC74182 and IC74183. The four full adders are
available in a single
IC. There are eight
inputs (four for A and
four for B), four pins
for the sum outputs,
one pin for the carry
in and one for carry-
out and two pins for
Fig. 6.12 8 bit addition using two 74283 ICs the supply voltage.
The example of a 8
bit adder using two 74283 ICs is shown in Fig. 6.12. Similarly, two or more number of ICs can be
connected to implement an ‘n’ bit adder circuit.
6.3 BINARY SUBTRACTION
Figure 6.13 shows the governing rules of subtraction of two
binary numbers. The binary subtraction of two binary num-
bers has the four possible combinations. After performing
the subtraction 0-1, the result difference, D = 1 and borrow,
Bout = 1. This borrow (Bout) will be used as borrow input Bin
for the next stage. In this section, half subtractor, full sub-
Fig. 6.13 Subtraction of two binary tractor, 4-bit subtractor and half adder/subtractor circuits
numbers
are explained.

6.3.1 Half Subtractor

A half subtractor is used to subtract two binary digits, the minuend (A) and the subtrahend (B).
After subtraction of two binary digits A and B, the difference, D = A – B and the borrow, Bout are
generated. This borrow signal may be transferred to the next stage of subtraction. Table 6.3 shows
the truth table for subtraction two binary digits A and B. The Boolean expressions of the difference
(D = A – B) and the borrow (Bout) are
 Arithmetic Logic Circuits 239

– –
Difference D = A⊕B = AB + A B Table 6.3 Truth table of Half subtractor
– Inputs Outputs
Borrow Bout = A B
Minuend Subtracted Difference Borrow
Figure 6.14 shows the implementation of the (A) (B) (D) (Bout)
difference (D) and the borrow (Bout) functions using AND 0 0 0 0
and OR gates. The block diagram representation of a half 0 1 1 1
subtractor (HS) is also shown in Fig. 6.15. 1 0 1 0
1 1 0 0

Fig. 6.14 Implementation of half subtractor Fig. 6.15 Block diagram of half subtractor
using logic gates

6.3.2 The Full Subtractor

A full – subtractor (FS) has three input bits, the minuend (A), the subtrahend (B) and the borrow (Bin). The
FS performs two-subtraction operations. In first subtraction, (A–B) is done and in second subtraction, (A-
B-Bin) is completed. After final subtraction of three binary digits A, B and Bin, the difference (D) and the
borrow output (Bout) are generated. Then borrow, Bout will be transferred to the next stage of subtraction.
Table 6.4 shows the truth table of full subtacter. K-maps and logic gates are used to implement the
difference (D) and the borrow output (Bout) of full subtractor.
Table 6.4 Truth table of full subtractor
Inputs Outputs
Borrow Minuend Subtracted Difference Borrow
(Bin) (A) (B) (D) (Bout)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

The block diagram of full subtractor is shown in Fig. 6.16. The difference (D) and the borrow output
(Bout) can be expressed in Boolean equations from the truth table as follows:
 240 Digital Electronics: Principles and Applications

–– – — –—
difference D = A B Bin + A BBin + AB Bin + ABBin
–– – — –
borrow output B out = A B Bin + A BBin + A BBin
+ ABBin
The simplified expression of difference is
– – — –— –
D = A (B— + BBin) + A(B Bin + BBin) = A (B ≈
Bin—–
Fig. 6.16 Block diagram of full subtractor Bin) + A B ≈ Bin = A ≈ B ≈ Bin
The borrow out may be rewritten as
– — –– – –——–
Bout = A B(Bin + Bin) + (A B + AB)Bin = A B + A ≈ B Bin
The K-maps of difference (D) and the borrow output (Bout) are shown in Fig. 6.17 (a) and Fig. 6.17
(b) respectively. From K-map, the simplified Boolean expression of borrow output is
– –
Bout = AB + ABin + BBin

Fig. 6.17 K-map of full subtractor (a) for difference (b) for borrow output

Figure 6.18 shows the implementation of

full subtractor circuits using EX-OR, AND, and
OR gates. Full subtractor circuit can also be
implemented with the help of two half- subtractor
circuits as shown in Fig. 6.19. The first half
subtractor is used to subtract two inputs, A and B,
and generate difference (D) and the borrow output
(Bout)¢ or B¢. Then the second half subtractor can
be used to subtract the borrow Bin from difference
Fig. 6.18 Implementation of full subtractor using (D) and generate final difference (D) and the
logic gates borrow output (Bout)¢¢ or B¢¢. The final borrow
output can be produced by using OR operation between B¢ and B¢¢.
Two 4-bit numbers can be
subtracted by using an array of full
subtractor (FS) and half subtractor
(HS) circuits as depicted in Fig.
6.20 and Fig. 6.21. Similarly,
two ‘N’-bit numbers can also be
Fig. 6.19 Block diagram of full subtractor subtracted by using an array of full
subtractors as shown in Fig. 6.22. The number B=BN-1 BN-2…..B1 B0 is subtracted from A=AN-1 AN-2……A1
A0. If initial borrow input is not present, in least significant bit subtraction, one half subtractor can be
used and for all other bits full subtractors are used. The above operation can be implemented by using
four full subtractor circuits. In this case borrow input of first full subtractor is grounded. The borrow
output is passed from one full subtractor to the next full subtractor but last borrow output will be the
 Arithmetic Logic Circuits 241

final borrow output of the subtraction. The final result of ‘N ’ bit subtraction is the difference (D) =DN-1
DN-2 ….D1 D0 and the borrow output Bout=BN-1.

Fig. 6.20 Four bit subtractor using FS Fig. 6.21 Four bit subtractor using FS and HS

Fig. 6.22 Four bit subtractor using FS

6.3.3 Half Adder/Subtractor
Figure 6.23 shows the half adder/subtractor circuit. In this
circuit, a controlled XOR gate is used to control addition as well
as subtraction operations. When mode control M=0, the output
is sum S = A ≈ B and carry C = AB and the circuit behaves as
adder. When mode control M=1, the output is difference D =
–
A ≈ B and borrow-output B = A B. Therefore, the circuit works
as a subtractor.

6.3.4 2’s Complement Adder/Subtractor Fig. 6.23 Half adder/subtractor

The XOR gate can be used, as an inverter when it’s one input is
high. Figure 6.24 shows the one’s complement of a 4-bit number.
When input B=B3B2B1B0 and mode control M=1, the output will be
– –– –
B 3B2B1B 0. 4-bit adder/subtractor using 2’s complement is shown
in Fig. 6.25. Input A = A3A2A1A0 is directly connected with full
adders but input B=B3B2B1B0 is fed to XOR gate and gates output
are connected with full adders. If mode control M = 0, output of
XOR gates are same as inputs. Therefore, two four bit numbers
A= A3A2A1A0 and B = B3B2B1B0 are added. During subtraction,
mode control M = 0, output of XOR gates are complements of
– –– –
inputs B 3B2B1B 0. If Cin = 1, the addition of two 4-bit inputs A = Fig. 6.24 one’s complement of a 4
– –– –
A3A2A1A0 and B = B 3B2B1B 0 with carry as follows. bit number
 242 Digital Electronics: Principles and Applications

– –– –
B 3B2B1B 0 1’s complement
+ 1 Cin = 1

B¢3 B¢2 B¢1 B¢0 2’s complement of B3B2B1B0

A3 A2 A1 A0 Minuend

+ B¢3 B¢2 B¢1 B¢0 2’s complement of B3B2B1B0

S3 S2 S1 S0 Difference

Fig. 6.25 4 bit adder/subtractor

Hence, the final result S3 S2 S1 S0 will
be the difference between A – B.
The addition/ subtraction can be implemented by using 4 bit adder MSI IC 74283 and a quad XOR
gate IC 7486 as depicted in Fig. 6.26. The mode control signal is used to select addition and subtraction
operations. If M = 0 and Cin = 0, the least significant stage of the adder acts as a half adder. Then IC
74283 acts as adder. When M = 1 and Cin = 1, the adder IC performs the subtraction operation. In
this case, 7486 act as an inverter and the least significant stage of the adder acts as 2’s complement
subtraction. Figure 6.27 shows the 1’s complement addition/subtraction operation. In this case, the end
about carry (EAC) is connected with Cin of the adder.

Fig. 6.26 Addition/subtraction using Fig. 6.27 Addition/subtraction using

2’s complement 1’s complement

6.3.5 Sign Magnitude Binary Subtractor

The two’s complement of a binary number is generally used to represent a negative number. The negative
number is derived from the following expression as given below:
2’s complement of a number = 1’s complement of number +1
The sign binary equivalent of decimal number +1 is 0 001

Sign Magnitude
 Arithmetic Logic Circuits 243

The first bit, 0 stands for positive sign and the Table 6.5 4 bit signed binary number
next three bits are used to represent the magnitude Decimal number Signed binary number
of the number. The 1’s complement of 0001 is 1110. Sign Magnitude
Then 2’s complement is 1110 +1= 1111 which rep-
+7 0 1 1 1
resents decimal number, –1. Here the first bit, 1 +6 0 1 1 0
stands for negative sign. Table 6.5 shows the 4 bit +5 0 1 0 1
signed binary number. +4 0 1 0 0
Figure 6.28 shows the 4-bit sign magnitude bi- +3 0 0 1 1
nary subtraction. During subtraction, the 4 bit sign +2 0 0 1 0
subtracted B is converted into two’s complement to +1 0 0 0 1
change the sign of number. It is depicted in Fig. 6.28 0 0 0 0 0
that the 4 bit sign magnitude binary number A (A0, –1 1 1 1 1
A1, A2, A3) is directly fed to first 4 bit adder IC 74283 –2 1 1 1 0
and the other number B (B0, B1, B2, B3) is inverted –3 1 1 0 1
using quad EX-OR gates and fed to the 4 bit adder. –4 1 1 0 0
When Cin is 1, the two’s complement of the 4 bit –5 1 0 1 1
sign number B is added with A and the difference of –6 1 0 1 0
the two 4 bit sign magnitude binary numbers can be –7 1 0 0 1
find at the outputs S¢3 S¢2 S¢1 S¢0 of IC 74283. If S¢3 = –8 1 0 0 0
0, output will be S¢2 S¢1 S¢0. When S¢3 = 1, output will
be two’s complement of S¢2 S¢1 S¢0. Therefore the second 74283IC is used to generate the 2’s complement
of the output S¢2 S¢1 S¢0 and final output can be obtained at S2 S1 S0. The final output of the two 4 bit sign
magnitude binary subtraction is the sign bit and the magnitude of the result of subtraction as given in
Fig. 6.28.

6.3.6 BCD Adder

Figure 6.29 shows the one digit BCD adder
circuit. Two BCD inputs are applied at inputs
A and B of 4 bit binary adder IC 74283. The
sum output of two BCD inputs is obtained
from S3 S2 S1 S0 of IC 1. If the output is less
than equal to 1001(9), there is no requirement
of decimal adjustment. When output is greater
than 1001(9) or any value from 1010 to 1111,
the output must be converted into decimal
form. Therefore, 0110(6) will be added with
S3 S2 S1 S0 to generate units and tens. For this,
output of IC1 is directly fed to the B inputs
of IC2. The carry output and the sum outputs
S3, S2 and S1 of IC1 are connected through an
inverter and two NAND gates to a 3-inputs
NAND gate. The output of NAND gate is
connected with A2 and A 1 input terminals
of IC2. A0 and A3 input terminals of IC2 are Fig. 6.28 4 bit sign magnitude binary subtraction
 244 Digital Electronics: Principles and Applications

grounded. The final result will be obtained from the output of IC2 after decimal adjustment as
depicted in Fig. 6.29.
6.4 CARRY LOOK-AHEAD
ADDITION
In the 4-bit adder, the carry signals have to propagate
from one full-adder to the next full adder. The delay
generated to produce carry output is 4d, where d =
propagation delay of each stage. This propagation de-
lay can be increased with number of bits. The circuit
performance can be improved by increasing the speed
of operation. Reducing the propagation delay, we can
increase the speed. Generally, look-ahead carry gen-
erator technique is used for this operation. The look-
ahead carry generator involves two Boolean functions
namely Generate (G) and the Propagate (P). For input
bits Ai and Bi, Generate (Gi) and the Propagate (Pi)
functions are defined as:
Gi = AiBi
Pi = Ai ≈ Bi
The carry output equation will be Cout=(Ai≈Bi)Cin+
AiBi and the above equation can be rewritten in terms
of Generate (Gi) and the Propagate (Pi) Cout=PiCin+Gi
For a 4-bit adder, the generation and propagation
Fig. 6.29 BCD adder terms for each stage are as follows

G0=A0B0 P0=A0≈B0
G1=A1B1 P1=A1≈B1
G2=A2B2 P2=A2≈B2
G3=A3B3 P3=A3≈B3
The carry outputs for the different stages are
C0= P0Cin + G0
C1= P1C0 + G1 = P1 (P0Cin +G0) + G1 = P1 P0Cin + P1G0 + G1
C2= P2 C1 + G2= P2(P1 P0 Cin + P1 G0 + G1)+ G2= P2 P1 P0 Cin + P2 P1 G0+ P2 G1+ G2
C3= P3C2 + G3 = P3 P2 P1 P0Cin+ P3 P2 P1 G0+ P3 P2 G1+ P3 G2+ G3
The final carry-out equation can be rewritten as
C3=PCin+ G
where G = P3 P2 P1G0+ P3 P2 G1+ P3 G2+ G3 and P = P3 P2 P1 P0
This carry look ahead generator can be implemented using AND, OR and XOR gates as shown in
Fig. 6.30. IC 74283 performs the addition of two 4-bit binary numbers with full internal carry look
ahead facility.
 Arithmetic Logic Circuits 245

Fig. 6.30 Carry look ahead generator Fig. 6.31 Pin diagram of IC 74283
The pin diagram and logic symbol of IC 74283 are
illustrated in Fig. 6.31 and Fig. 6.32 respectively. The sum
outputs are provided for each bit (S3 S2 S1 and S0) and the
resultant carry (C4) is obtained from the fourth bit. These
adders feature full internal look ahead across all four bits.
This provides the system designer with partial look - ahead
performance at the economy and reduced package count of
a ripple-carry implementation. The features of IC 74283 are
given below:
∑ Full-carry look-ahead across the four bits
∑ Systems achieve partial look-ahead performance with
the economy of ripple carry
∑ Typical add times: two 4-bit words 15 ns; two 8-bit
words 25 ns; two 16-bit words 45 ns
∑ Typical power dissipation per 4-bit adder is 95 mW.
For 8 bit addition, two 74283 IC are connected in cascade
and typical delay time is about 25ns. A 16 bit addition can be
implemented by cascade connection of four 74283 ICs and
delay time to get the final result will be approximately 45ns.
6.5 SERIAL ADDER
Figure 6.33 shows the serial addition of two N - bit numbers
A = AN-1 AN-2 …. A1 A0 and B= BN-1, BN-2… B1 B0. This circuit Fig. 6.32 The IC 74283 4 bit carry look
consists of three shift registers, a full adder and a D flip-flop. ahead adder
In serial adder, addition is started from the least signifi-
cant bit. Initially, the full adder inputs are Ai=A0, Bi=B0 and Ci–1=0. The outputs are sum Si=S0=A0≈B0 and
carry Ci = C0= A0B0. When the first clock pulse is applied, S0 is loaded into the SUM register. Carry out
Ci=C0 is connected with the D flip-flop. Therefore, flip-flop output Q = D after first clock pulse and is fed
 246 Digital Electronics: Principles and Applications

into full adder as carry input. In the

mean time, the next addend A1 and
augend B1 are input into the full ad-
der from register A and B respective-
ly as shift registers are shifted to the
right by one bit. Then the full adder
inputs are Ai=A1, Bi=B1 and Ci-1=C0.
The outputs are sum Si=S1=A1≈B1
and carry Ci=C1=A1.B1
Fig. 6.33 Two N bit serial adder Just after the application of second
clock pulse, S1 is loaded into the sum
register, and S0 shifted by one bit right. The carry Ci=C1 is also fed the input terminal Ci-1 of full adder.
Then the addend A2 and augend B2 are input into the full adder from registers A and B due to right shift-
ing. Therefore, the full adder inputs are Ai= A2, Bi=B2 and Ci-1=C1. The outputs are Sum Si=S2=A2≈B2 and
carry Ci=C2=A2.B2. When the next clock pulse is applied, the sum S1 is loaded into SUM register and S1
and S0 are shifted by one bit right. The similar operation will be repeated on each clock pulse. Hence, af-
ter N clock pulses, the content of A and B registers are zeros and Ai = 0, Bi = 0. When Ai = Bi = 0, the final
carry out will be available at the sum output of full adder and loaded into the sum register after N+1 clock
pulse. Consequently, final sum S = SN-1 SN-2 ……S1 S0 and carry C = CN-1 are stored in the sum register.
6.6 PARALLEL ADDITION
Figure 6.34 shows the ‘N’ bit parallel
adder circuit. It consists of addend
register, augend register, full adders
and sum register. In parallel addition,
the addend (A) and augend (B) are
added simultaneously and it is faster
than serial adder but less economi-
cal. Before addition, the addend and
augend are stored in addend register
and augend register respectively.
These registers are not shift registers
but used as storage registers and it
is not required to shift bits serially.
The register is a set of D flip-flops
and number of flip-flops actually de- Fig. 6.34 Parallel addition
pends upon the number of bits of addend and augend. The flip-flops in the addend register and augend
register are completely independent of each other but a common clock pulse operates the flip-flops.
Initial addend (A = AN-1 AN-2 …. A1 A0) and augend (B = BN-1, BN-2… B1 B0) are applied to the input
terminals of respective flip-flops. Just after application of clock pulses, the addend (A = AN-1 AN-2 …. A1
A0) and augend (B = BN-1, BN-2… B1 B0) are loaded into registers and available at the output terminals of
corresponding flip-flops. Then addend (A = AN-1 AN-2 …. A1 A0) and augend (B = BN-1, BN-2… B1 B0) are
added with carry input Cin in full adders. After addition the sum (S = SN-1,SN-2… S1 S0) and carry (CN) are
 Arithmetic Logic Circuits 247

available from full adders and fed to the flip-flops of sum register. When the clock pulse is applied, these
results will be stored in sum register.
The parallel addition has speed limitation. The carry generated of full adder must be ripple through
from one full adder to next full adder. For example, carry output of first full adder C0 will be obtainable
after a time equal to the propagation delay time of the full adder. Then this carry C0 will be used as carry
input of next full adder and generates a carry C1 after a second propagation delay. This process will
continue till the additions of all bits are completed. The sum of the propagation delays of all full adders
is actually the total delay time of operation. To reduce the total delay time, the fast adder circuits are
incorporated the carry look ahead (CLA) to ripple through carry of adders.
The addition of K N-bit numbers is S = X(1) +X(2) + X(3) +….+ X(K). When more than two N-bit
numbers are added, the Fig. 6.34 must be modified into Fig. 6.35. This adder circuit consists of N-bit
augend register, N bit full adder and N+1 bit accumulator register. Actually, the N bit full adder is the
cascade connection of N full adders.
Initially, all flip-flops of augend register and accumulator register are in reset condition and the first
number X(1) [ XN-1(1)………. X2(1) X1(1) X0(1) ] is fed to the input terminals of D flip-flops of the augend
register. After application
of clock pulse, the number
X (1) is input to the BN-1
……B2 B1 B0 terminals of
N bit full adder and other
terminals of N bit full
adder AN-1 ……A2 A1 A0 are
0 as the outputs of N–bit
accumulator are 0. Then N
bit full adder circuit added
two N bit number AN-1 =0
……A2 =0 A1 =0 A0=0 and
BN-1 = XN-1(1) ……B2=
X2(1) B1= X1(1) B0 = X0(1) Fig. 6.35 Parallel addition of K N - bit numbers
with carry input Cin=0.
After addition, the output of N bit full adder will be XN-1(1)………. X2(1) X1(1) X0(1). Therefore, the
X(1) will be stored in the accumulator register when the second clock pulse is applied and fed into the
input terminals AN-1 ……A2 A1 A0 of N-bit full adder and the next number X(2) [ XN-1(2)………. X2(2)
X1(2) X0(2) ] is also loaded in augend register. Now A = X(1) and B = X(2). The output of N-bit full
adder is the sum of X(1) and X(2). When the third clock pulse is applied, S = X(1)+ X(2) will be loaded
in accumulator register and X(3) [ XN-1(3)………. X2(3) X1(3) X0(3) ] number will be loaded into augend
register. Then above process will continue until addition of all N-bit numbers are completed. So, after
Kth clock pulse the content of accumulator register is the final sum of K N-bit numbers.

6.7 BINARY MULTIPLIER

A binary multiplier is an electronic device which is used in digital electronics for multiplication of two
binary numbers. Table 6.6 shows the rules of binary multiplication. Here, A is the multiplicand and B
is the multiplier. When the multiplicand is 0 or 1 and the multiplier is 0, the product output is 0. If the
 248 Digital Electronics: Principles and Applications

Table 6.6 Truth Table of binary multiplication multiplier digit is 1, the partial product is equal to
Inputs Output the multiplicand. Therefore, the AND operation is
equivalent to multiplication of two bits.
Multiplicand Multiplier (A.B) The process of two bit multiplication is
(A) (B) shown in Fig. 6.36. The multiplicand A (A1 A0) is
0 0 0 multiplied in turn by each digit of the multiplier
0 1 0 B (B1B0). Intially, B0 is multiplied with A1 and A0
1 0 0 and generates partial product A1B0, A0 B0. Then
1 1 1 B 1
is multiplied with A1 and A0 and generates
partial product A1 B1 , A0 B1 which are shifted by
one bit left. Then sum of threse partial products
produce the result of multiplication using AND
gates and adders as depicted in Fig. 6.37. Each
partial product is either 0 or 1 depending upon
the multiplicand and multiplier. The AND gates
produce the partial products. In a 2-bit by 2-bit
multiplier, two half adders are used to sum the
partial products, but generally full adders are used
Fig. 6.36 Process of 2 bit multiplication
in multiplication. Here P3 – P0 are the product
output. Table 6.7 shows the product output of 2 two bit binary numbers. The product output has more
digits than the multiplicand and multiplier. If two N bit binary numbers are multiplied, the product
output will be as many as 2N bits.
Table 6.7 Truth table 2×2 multiplier
Inputs Output
Multiplicand Multiplier P3 P2 P1 P0
A1 A0 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0
0 0 1 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 0
0 1 0 1 0 0 0 1
0 1 1 0 0 0 1 0
0 1 1 1 0 0 1 1
1 0 0 0 0 0 0 0
1 0 0 1 0 0 1 0
1 0 1 0 0 1 0 0
1 0 1 1 0 1 1 0
1 1 0 0 0 0 0 0
1 1 0 1 0 0 1 1
1 1 1 0 0 1 1 0
Fig. 6.37 2 - bit by 2- bit multiplication 1 1 1 1 1 0 0 1
 Arithmetic Logic Circuits 249

Figure 6.38 shows the process of 4-

bit by 4-bit multiplication. Here, the
4-bit binary number A (A3 A2 A1 A0) is
multiplied by another 4-bit number B (B3
B2 B1 B0). The first row of multiplication
is that the least significant bit of
multiplier is multiplied with each bit of
multiplicand and four partial products A3
Fig. 6.38 4-bit by 4-bit multiplication
B0, A2 B0, A1 B0, A0 B0 are produced. Then
the second row of multiplication is obtained by multiplying each bit in the multiplicand by the B1 and
generates four partial products A3 B1, A2 B1, A1 B1, A0 B1, which are shifted by one bit. Similarly, other
two rows of partial products are produced. Then the columns of partial products are added to get the
final product. The basic implementation of 4-bit by 4-bit array multiplication is depicted in Fig. 6.39. It
consists of full adders and AND gates.

Fig. 6.39 4 -bit by 4 -bit array multiplication

Logical AND operation each of the bits of the multiplicand (A3 A2 A1 A0) with the first bit of the
multiplier (B0) can generate A3 B0, A2 B0, A1B0, A0B0. The output of A0 AND B0 is the first bit of the
product output - P0. After that, AND each of the bits of the multiplicand (A3 A2 A1 A0) with the first bit of
the multiplier (B1) and generates A3B1, A2 B1, A1 B1, A0 B1. Then partial product A3B0, A2B0, A1B0 now will
be added with A3B1, A2 B1, A1 B1, A0 B1 using full adders. In this addition process, the carry is generated
and it is forwarded to the next column of partial products. Product P1 is obtained from first full adder.
The above process will continue till all multiplication and addition process are completed. The carry
output from the last adder becomes the final bit in the product. The final product of this 4 bit multiplier is
an 8 bit result P7 P6 P5 P4 P3 P2 P1 P0. In this way, combinational logic circuit (AND gates and full adders)
is used to implement 4 bit multiplication. This operation can also be implemented by 4 bit adders and
AND gates as shown in Fig. 6.40.
 250 Digital Electronics: Principles and Applications

Fig. 6.40 4-bit by 4-bit multiplication

Actually, digital multiplications are very
complex circuits. In general, when multiplying
an m-bit number by an n-bit number, there
are m × n partial products. If n = 32 and m
= 64, the multiplication circuit requires huge
number of gates and full adders. Actually, the
required combinational logic gates and full
adders increase with number of bits in the
multiplier and multiplicand and a register is
required to store the product. Now-a-days LSI
circuits are available as fast multiplier chips.
The IC 74284 and IC 74285 are commonly
used in 4-bit by 4-bit multiplication as given
Fig. 6.41 4-bit by 4-bit multiplication using IC in Fig. 6.41.
74284 and IC 74285

6.8 BINARY DIVISION

Binary division is basically the reverse operation of the binary multiplication by shift and Add or
repetitive addition. Division can be performed by repeated subtraction. Until dividend is less than the
divisor, the subtraction is continuing.
Figure 6.42 shows the schematic diagram of dividing a four bit number A= A 3 A2 A1 A 0 by a divisor
B= B3 B2 B1 B0 using repeated subtraction method. This circuit consists of a 4-bit adder, a register and
a counter. Initially, all flip-flops of dividend register are reset. Then the dividend A is loaded into the
register. The outputs of dividend register are connected as inputs of the adder. The one’s complement of
– – – –
divisor B, B 3 B 2 B 1 B 0 is also connected other input terminals of 4 bit adder. The carry output C3 must be
connected to the carry input Cin. Consider Cin =1 and the counter is initially reset at zero.
 Arithmetic Logic Circuits 251

After subtraction the difference, A-B ap-

pears at S3 S2 S1 S0. When A>B and C3=1, the
AND gate is enabled. If the clock pulse is ap-
plied, the difference A-B will be loaded into
the dividend register and the counter value
incremented by one. The register contents
again are used as input to the 4 bit adder.
Then B is subtracted from A-B, if A-B>B.
After subtraction the difference, A-B-B=A-
2B will appear at S3 S2 S1 S0. As the AND
gate will be enabled and after application of
the second clock pulse A-2B will be loaded
into the register and the counter is also in- Fig. 6.42 Division two 4-bit binary numbers by re-
peated subtraction
cremented by one. If after N clock pulses the
remainder becomes less than B, C3=becomes 0 and the AND gate will now be disabled. Then the counter will
stop counting. Therefore, the quotient is stored in the counter and the remainder will be available at S3 S2 S1 S0.
6.9 ARITHMETIC LOGIC UNITS (ALU)
Arithmetic logic units (ALU) perform arithmetic and logic operations (add, subtract, OR, AND….) on
binary inputs data. Figure 6.43 shows the block
diagram of an N bit ALU. This ALU has two N
bit inputs A = AN-1 AN-2 ..…. A1 A0 and B = BN-1 BN-2
..….B1 B0 , one N bit select inputs S = SN-1 SN-2 ..….S1
S0 and output function FN-1 FN-2 ..….F1 F0 . The
select inputs actually select the output function. If
there are three select variables in an ALU, there will
be eight output functions as shown in Table 6.8.
Arithmetic logic units are available in a variety
of medium scale integrated (MSI) circuit package
Fig. 6.43 Block diagram of an N bit ALU
types and with different numbers of pins.
Generally, the ALU is divided into two units: an arithmetic unit (AU) and a logic unit (LU). In some
processors with multiple arithmetic units, one AU may be used for fixed-point operations while other
arithmetic units AUs are used for floating-point operations.
In general, arithmetic logic units have
direct input and output access to the processor
controller, main memory and input/output (I/O)
devices. Each input consists of an operation
code (one or more operands). The operation
code determines actually which operation will
be performed. After performing the operation
ALU outputs are loaded into a storage register.
Figure 6.44 shows the general structure of a
simple arithmetic logic unit. Here, two multi-
bit data inputs A and B are applied to ALU. Fig. 6.44 General structure of a simple ALU
 252 Digital Electronics: Principles and Applications

Function indicates the action like add, subtract, AND, etc. Data outputs have same bit width as multi-bit
data inputs A and B and conditions indicates special conditions of arithmetic activity like overflow.
Arithmetic logic units may vary in terms of number of bits, supply voltage, operating current,
propagation delay, power dissipation, and operating temperature etc. The number of bits equals to the
width of the two input words on which the ALU perform arithmetic and logical operations. Common
configurations of ALU are 2-bit, 4-bit, 8-bit, 16-bit, 32-bit and 64-bit ALUs. Supply voltages varies
from –5 V to +5 V. Power dissipation of ALU is in some milliwatts (mW).
Transistor-Transistor Logic (TTL), Fairchild Advanced Schottky TTL (FAST), Emitter Coupled Logic
(ECL), Complementary Metal-Oxide Semiconductor (CMOS) logic families are used to develop ALU ICs.
Arithmetic Logic Units are available in a variety of integrated circuit (IC) package types and with different
numbers of pins. Basic IC package types for ALUs are Ball Grid Array (BGA), Quad Flat Package (QFP),
Single In-Line Package (SIP), and Dual In-Line Package (DIP).
IC74382 is an ALU IC and its logic symbol is depicted in Fig. 6.45. It is a 4-bit device and performs
eight functions as shown in Table 6.8. Three select lines S2 S1 S0 are used to select output functions.
Multi-bit ALU can be created by connecting the carry output of lower order IC to carry in of higher
order IC as shown in Fig. 6.46.
Table 6.8 Function table
Select inputs Logic function Comments
S2 S1 S0
0 0 0 CLEAR F3F2F1F0=0000
0 0 1 B Minus A CN=1
0 1 0 A Minus B
0 1 1 A Plus B CN=0
1 0 0 A≈B Exclusive OR
1 0 1 A+B OR
1 1 0 AB AND
1 1 1 PRESET F3F2F1F0=1111
Fig. 6.45 Logic symbol of ALU IC 74382

Fig. 6.46 8 bit ALU using two 4 bit ALUs

 Arithmetic Logic Circuits 253

The IC 74LS181 and IC 74S181 are also arithmetic logic units

(ALU). Figure 6.47 shows the pin diagram of IC 74181. The logic
diagram of IC 74181 is depicted in Fig. 6.48. These circuits perform
16 binary arithmetic operations on two 4-bit words as shown in Table
6.9. These operations are selected by the four function-select lines (S0,
S1, S2, S3) and include addition, subtraction, decrement, and straight
transfer. When performing arithmetic manipulations, the internal
carries must be enabled by applying a low-level voltage to the mode
control input (M). A full carry look-ahead scheme is made available
in these devices for fast, simultaneous carry generation by means of
two cascade-outputs (pins 15 and 17) for the four bits in the package.
When used in conjunction with the SN54S182 or SN74S182 full
carry look-ahead circuits, high-speed arithmetic operations can be Fig. 6.47 Pin diagram of ALU
performed. The method of cascading ‘S182 circuits with these ALUs IC 74181

Fig. 6.48 Logic diagram of ALU IC 74181

 254 Digital Electronics: Principles and Applications

to provide multi-level full carry look-ahead is illustrated in Fig. 6.49. If high speed is not of importance,
a ripple-carry input (Cn) and a ripple-carry output (Cn+4) are available. However, the ripple-carry delay
has also been minimised so that arithmetic manipulations for small word lengths can be performed
without external circuitry.

Fig. 6.49 Cascade connection of 74LS181 and 74S182

The ‘LS181 or ‘S181 can also be utilised as a comparator. The A = B output is internally decoded
from the function outputs (F0, F1, F2, F3) so that when two words of equal magnitude are applied at the
A and B inputs. Assumption is that a high level is used to indicate equality (A = B). The ALU must be
in the subtract mode with Cn = H when performing this comparison. The A = B output is open-collector
so that it can be wire-AND connected to give a comparison for more than four bits. The carry output
(Cn+4) can also be used to supply relative magnitude information. After this operation, the ALU may be
placed in the subtract mode by placing the function select inputs S3, S2, S1, S0. These circuits have been
designed to not only incorporate all of the designer’s requirements for arithmetic operations, but also to
provide 16 possible functions of two Boolean variables without the use of external circuitry. These logic
functions are selected by use of the four function-select inputs (S0, S1, S2, S3) with the mode-control input
(M) at a high level to disable the internal carry. The 16 logic functions are detailed in Table 6.9, which
is included exclusive-OR, NAND, AND, NOR, and OR functions. Series 54, 54LS, and 54S devices
are characterised for operation in the temperature range of –55°C to 125°C; and Series 74LS and 74S
devices are characterised for operation from 0°C to 70°C.
Table 6.9 Functional table of ALU IC 74181
Select inputs Logic function Arithmetic and logic functions (Active low data)
M=1 M=0 Cn=L No carry M=0, Cn=H with carry
S3 S2 S1 S0 – F F F
0 0 0 0 F = A— F = A Minus 1 F=A
0 0 0 1 F = AB
– F = AB
– Minus 1 F = AB
–
0 0 1 0 F=A+B F = AB Minus 1 F= AB
0 0 1 1 F = 1——– F = Minus 1(2’s complement)
– F = Zero –
0 1 0 0 F = A– + B F = A Plus (A + B )– F = A Plus (A + B )–Plus 1
0 1 0 1 F=B F = AB Plus (A + B ) F = AB Plus (A + B )Plus 1
——–
0 1 1 0 F = A≈ B F = A Minus B Minus 1 F = A Minus B
 Arithmetic Logic Circuits 255

Table 6.9 (Contd...)

– – –
0 1 1 1 F = A– + B F=A+B F = (A + B ) Plus 1
1 0 0 0 F = AB F = A Plus (A+B) F = A Plus (A+B) Plus 1
1 0 0 1 F=A≈B F = A Plus B F = A Plus B Plus 1
– –
1 0 1 0 F=B F = AB Plus (A+B) F = AB Plus (A+B) Plus 1
1 0 1 1 F=A+B F = (A+B) F = (A+B) Plus 1
1 1 0 0 F=0 – F = A Plus At F = A Plus A Plus 1
1 1 0 1 F = AB F = AB– Plus A F = AB– Plus A Plus 1
1 1 1 0 F = AB F = AB Plus A F = AB Plus A Plus 1
1 1 1 1 F=A F=A F = A Plus 1

6.10 DIGITAL COMPARATORS

The comparator is a device which compares
two binary numbers and also produces some
results. There are two different types of
comparators such as identity comparator and
magnitude comparator. An identity comparator
is a device that makes a bit-by-bit comparisons
of two binary numbers and asserts an output
when the two numbers are bit-by-bit equal.
When a comparator compares two binary
numbers and takes a decision whether one of
the inputs is larger (L) than, or smaller (S) than
or equal (E) to the other inputs and generates
one of the three outputs L, S and E. This
comparator is more complicated than identity comparator and is known as magnitude comparator.

6.10.1 1-bit Digital Comparator

Consider two one bit numbers A and B and compare them to find out the relative magnitude of L, S
and E. After comparison, the result
will be whether A>B, A<B or A=B.
Figure 6.50 shows the 1-bit digital com-
parator circuit. Here, XNOR gate works
as an equality comparator when A=B,
the output of the gate is high or E=1. In
practice, comparators are also used to
indicate more than equality. When A>B
or A=1 and B=0, the output L =1 which
implies that A>B. Similarly, output S=1
when A<B or A=0 and B=1.

6.10.2 2-bit Digital Comparator

Figure 6.51 shows the circuit diagram of a 2-bit comparator. Assume two 2-bit binary numbers A1 A0
and B1 B0 are used as inputs of a 2-bit comparator. The output of the comparator will be A>B, A<B and
A=B as shown in Table 6.10.
 256 Digital Electronics: Principles and Applications

Table 6.10 Truth table of 2-bit comparator

Input 1 Input 2 Output

A1 A0 B1 B0 A>B (L) A<B(S) A=B (E)
0 0 0 0 0 0 1
0 0 0 1 0 1 0
0 0 1 0 0 1 0
0 0 1 1 0 1 0
0 1 0 0 1 0 0
0 1 0 1 0 0 1
0 1 1 0 0 1 0
0 1 1 1 0 1 0
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 0 1
1 0 1 1 0 1 0
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 0 1

It is necessary to develop an algorithm which can be used for hardware implementation of any
comparator. The algorithm of 2-bits comparator as follows:

Algorithm
Step-1 Initially we take the most significant pair of digits A1 and B1 respectively. If A1>B1, then
A>B; if A1<B1 then A<B ; if A1=B1 we can not take any decision and the next pair of digits must
be compared.

Step-2 If A0>B0 and A1=B1 then A>B; if A0<B0 and A1=B1 then A<B; if A0=B0 and A1=B1
then A=B.

If the most significant pair of digits are equal or A1=B1 then

–—
E1 = A 1B1 + A1B1
When the least significant pair of digits are equal then
–—
E0 = A 0B0 + A0B0

If A=B, then E =E1E0 = 1

 Arithmetic Logic Circuits 257

— —
To determine A>B , the equation is L = A1B 1 + E1A0B 0
— —
The first term in this equation A1B1 = 1 if A1>B1. The second term E1A0B 0 = 1 if A1=B1 and A0>B0. If
those two conditions are satisfied, then A>B.
— —
The equation for determining whether A<B is S = A1B1 + E1A 0 B0
— —
In this equation, the first term A1B1 =1 if A1 < B1. The second term E1A 0 B0 =1 if A0=B0 and A0<B0. If
those two conditions are satisfied, then A<B.
— — —
The implementation of a 2 bit comparator based on E = E1E0 = 1, L= A1B 1 + E1A0B0 and S = A 1B1 +
—
E1A 0B0 is shown in Fig. 6.51.

6.10.3 4-bit Digital Comparator

The algorithm of 2-bit comparator can be modified to 4-bit comparator. Assume two four digit binary
numbers A and B. The number A is equal to A3 A2 A1 A0 and the number B is equal to B3 B2 B1 B0. The two
numbers are equal when all pairs of significant digits are equal or A3=B3, A2=B2, A1=B1, and A0=B0. The
equality relation for each pair of bits can be expressed as
—— –—
Ei = Ai Bi + Ai Bi where i = 0,1,2,3 or E3 = A 3B3 + A3B3,
–— –— ——
E2 = A 2 B 2 + A2B2, E1 = A 1 B 1 + A1B1 and E0 = A 0 B 0 + A0B0
If A=B then E = E3E2E1E0. This equation states that the binary variable is equal to ‘1’ only if all pairs
of digits of the two numbers are equal.
For each pair of input variables, an XNOR gate generates the individual equality functions. The four
equality functions and all equality signal are ANDed to provide the A=B output. A>B and A<B function
are generated by two different Boolean function as given below.
To determine whether A is greater than B or A>B the Boolean function is
— — — —
L = A3 B 3 + E3A2B 2 + E3E2A1B 1 + E3E2E1A0B 0
— — —
The first term in this equation A3 B 3 = 1 if A3> B 3 = 1. If A3= B3, then the second term E3A2B 2 = 1 if
— —
A2 = B2. When A3=B3, A2=B2, the third term E3E2A1B 1 = 1. Lastly, the fourth term E3E2E1A0 B 0 =1 if A3
= B3, A2 = B2, A1 = B1 and A0>B0. If the above four conditions are satisfied, then A>B. The equation for
determining whether A<B is
— — — —
S = A3B3 + E3 A 2B2 + E3E2 A1B1 + E3E2E1 A 0B0
The implementation of a 4 bit comparator based on the above derived equations is shown in Fig. 6.52.
Now a days a number of comparators are available in the TTL family. For example, the 74LS85 is
a 16 pin 4 bit comparator and it has three outputs A=B, A>B and A<B. After cascading connection of
comparator chips, the words of greater length can be compared. The 8-bit comparators are also available
in the TTL family such as IC 74688, IC 74682 and IC 74886. The IC 74688 are identity comparators and
generate an active low A=B output after comparing the magnitudes of two 8 bit words. The IC 74682
produces active low outputs for A=B and A>B outputs to the inputs of a NAND gate. Open–collector
and totem-pole outputs are also available in the comparators group and some chips such as the IC 74886
have either one or two enable pins.
 258 Digital Electronics: Principles and Applications

Fig. 6.52 4-bits comparator

SUMMARY

In this chapter, the arithmetic operations: addition, subtraction, 2’s complement adder/subtractor, sign magnitude
binary subtraction carry look ahead adder, serial adder, parallel adder, BCD addition, multiplication and division
using combinational logic circuits are explained. Some MSI ICs are also incorporated to perform addition and
multiplication. The operation of arithmetic logic unit (ALU) is also explained with 74382 and 74181 MSI ICs. The
operation of 1 bit, 2 bit and 4 bit comparators are discussed in this chapter.

MULTIPLE CHOICE QUESTIONS

1. In digital system, subtraction is performed using
(a) Half adders
(b) Half subtractors
(c) Adders with ones complement representation of negative numbers
(d) None of these
2. In digital electronics addition is performed using
(a) Half adders
(b) Half subtractors
(c) Adders with ones complement representation of negative numbers
(d) None of these
 Arithmetic Logic Circuits 259

3. A half adder consists of

(a) AND gate (c) NAND
(b) EXOR gate and AND gate (d) None of these
4. A full adder consists of
(a) AND gate (c) NAND
(b) EXOR gate and AND gate (d) None of these
5. A full adder can be designed
(a) Using 2 half adders (c) Using 4 half adders
(b) Using 3 half adders (d) Using 5 half adders
6. An N bit adder consists of
(a) 2 full adders (b) N full adders (c) 4 full adder (d) N-1 full adders
7. IC 74181 is an N bit adder which consists of
(a) Full adder adder (b) Half adder adder (c) Multiplier (d) None of these
8. BCD arithmetic is preferred over binary arithmetic due to
(a) BCD arithmetic circuits are simpler than binary arithmetic circuits
(b) BCD arithmetic circuits are faster than binary arithmetic circuits
(c) BCD arithmetic circuits are less expensive than binary arithmetic circuits
(d) Easy operation and output display
9. In BCD addition, 0110 is required to be added to the sum for getting the correct result, if
(a) The sum of two BCD numbers is not a valid BCD number
(b) The sum of two BCD numbers is not a valid BCD number or a carry is produced
(c) A carry is produced
(d) None of these
10. BCD subtraction is performed by using
(a) One’s complement representation (c) Nine’s complement representation
(b) Two’s complement representation (d) None of these
11. The ALU is used to perform
(a) Only logical operation (c) Arithmetic and logical operation
(b) Only arithmetic operations (d) Control operations
12. A multiplier circuit consists of
(a) AND gate and Full adders (c) NAND
(b) OR gate and EXOR gates (d) None of these
13. 2’s complement of a number is
(a) 1’s complement of a number + 1 (c) 1’s complement of a number + 10
(b) 1’s complement of a number –1 (d) None of these
14. The final carry output equation of carry look ahead addition is
(a) C3 = PCin + G (b) C3 = P + Cin +G (c) C3 = P = GCin (d) None of these
15. 74283 is a
(a) 4 bit adder (c) 4 bit subtractor
(b) 4 bit carry look ahead adder (d) None of these
 260 Digital Electronics: Principles and Applications

16. Serial adder is

(a) Faster than parallel adder (c) Costly with respect to parallel adder
(b) Slower than parallel adder (d) None of these

REVIEW QUESTIONS
6.1 Draw a half adder circuit using NAND gates and explain its operation.
6.2 Draw a full adder circuit using NAND gates and explain its operation. Write some applications of
full adders. What is the difference between half adder and full adder?
6.3 Design a 4 bit divider circuit using repeated subtraction.
6.4 Draw a 8 bit serial adder and explain it operation briefly. When serial input data’s are 1111 1001
and 1000 1000, find the output of serial adder after eight clock pulses. What are the advantages and
disadvantages of serial adder?
6.5 Design a 4 bit parallel adder circuit. Explain how 1010 and 1111 will be added in parallel adder.
What are advantages of parallel adder?
If the propagation delay time of 1 bit full adder is 100ns, determine the total delay time to get final
result.
6.6 Draw a 4 bit by 4 bit array multiplication circuit and explain its operation. What will be total delay
time to get final product output? Consider AND gate delay time 100ns and full adder delay time
200ns.
6.7 Design a circuit to convert 4 bit binary number into one’s complement form.
6.8 Design a circuit to convert 4 bit binary number into two’s complement form.
6.9 Determine the maximum propagation delay time between Cin and Cout of a 4 bit CLA adder. Assume
the propagation delay in each full adder is Tf and in gates is Tg.
6.10 Design the combinational logic circuits to perform the following operations:
(a) A+B (b) A-B (c) A¥B where A=A5A4A3A2A1A0 and B= B 5 B 4 B 3 B 2 B 1 B 0
6.11 Define ALU. Explain the operation of 74LS382 ALU IC with diagram. Show the following operation
using 74LS382 ALU IC:
(a) A PLUS B (b) A+ B (c) A MINUS B
6.12 Design a 8 bit ALU using two 4 bit 74LS382 ALU IC. Show the following operation using 74181
IC:
(a) A PLUS B (b) A ≈ B
where A=1111 1111 and B =1000 0111.
6.13 Show the following operation using 74LS181 IC:
(a) A PLUS B (b) AB Plus A
6.14 Design a combinational logic circuit to perform the arithmetic operation B =A+2, where
A= A4A 3A 2A1A 0.
6.15 Draw the connection diagram of 74283 and 7486 to perform a 8 bit parallel adder/subtractor.
6.16 Draw the 4 bit multiplication circuit and explain briefly. Write most commonly used multiplication
ICs in digital electronics.
6.17 An arithmetic circuit has two selection signals, S0 and S1. The circuit is required to perform the fol-
lowing operations
(a) F = A + B (b) F = A + B + 1 (c) F = A (d) F = B
 Arithmetic Logic Circuits 261

Design the ALU circuit using a 4 bit adder and logic gates.
6.18 Design a binary multiplier which multiplies a 4 bit number B3 B2 B1 B0 by a number A= A2 A1 A0.
6.19 Design a circuit that adds two binary bits a carry input (Cin).
6.20 What is the difference between a parallel adder and a carry look-ahead adder?. Explain the operation
of carry look-ahead adder with diagram.
6.21 Compare the following two circuits as shown in Fig. 6.53 and Fig. 6.54.

Fig. 6.53 Digital summer Fig. 6.54 Analog summer

6.22 What is the advantage of look-ahead carry? When should it be used?

6.23 If an ‘M’ bit number is multiplied by an ‘N’ bit number, what will be the length of the product reg-
ister?
6.24 Design an 8 bit adder using two 4 bit adders.
6.25 Design a 4 bit subtraction using 4 bit adders and minimum number of Ex-OR gates.
 CHAPTER

7
FLIP-FLOPS
7.1 INTRODUCTION
The combinational logic circuits are a part of digital systems and they have many applications such as
decoder, encoder, adder, subtracter, multiplexer, demultiplexer, etc. But when the circuit output not only
depends on the present state but also the previous state, the circuit is known as sequential logic circuit.
The basic block diagram of a sequential circuit is shown in Fig.7.1. This circuit consists of a combina-
tional logic circuit and a memory element. The output of combinational logic circuit is stored in memory
elements. Memory elements output entered into combinational logic circuit and used as input variables.
The output of combinational logic circuit depends upon the external inputs and input from memory ele-
ments. A memory element is a device which can store information in terms of 1 or 0 and its state can be
modified by clock signal and data inputs A flip-flop is one bit memory element which can store 1 or 0.
Flip-flop is an electronic circuit or device which is used to store a data in binary form. Actually, flip-
flop is an one-bit memory device and it can store either 1 or 0. This device has two-state characteristics.
Therefore, this device is known as two state machines as shown in Fig.7.2. There are four conditions of
transition of flip-flops due to change in input and clock signals. Condition-1, condition-2, condition-3
and condition-4 are the four different logic conditions related with input and clock signals. If the initial
state of flip-flop is 0 in condition-1, when input x = 0 and clock is applied, flip-flop output state will not
be changed and its output should retain at logic level 0. In condition-2, while flip-flop is in 0 state and
input x=1 and clock is applied, there will be transition in flip-flop’s output as its state is changed from
logic level 0 to logic level 1. Similarly, in condition-3, when flip-flop is in 1 state, input x = 1 and clock
is applied, output will not be changed and output should maintain logic level 1. But, in condition-4,
flip-flop is in 1 state, input=0 and clock signal is applied, and then output will be changed from logic
level 1 to logic level 0. Flip-flop can be constructed using inverter, NOR and NAND gates which are
discussed in this chapter.

Fig. 7.1 Block diagram of sequential logic circuit Fig. 7.2 Two state machine
 Flip-Flops 263

7.2 INVERTER WITH FEEDBACK

Figure 7.3 shows the inverter with feedback. The basic operation of this circuit is explained here. When
the input is logic level 0, the output switches to logic level 1 after
a small propagation delay. Logic level 1 output gets fed back to
the input as logic level 1. When the input is logic level 1, the
output switches to logic level 0 after a small propagation delay.
Logic level 0 outputs gets fed back to the input as logic level 0 and
the cycle repeats itself. The result is a high frequency oscillator,
if implemented with an inverter gate. The propagation delay of Fig. 7.3 Inverter with feedback
inverter varies in between 4ns to 60ns. When the propagation
delay of a TTL NOT gate is about 25ns, the time period will be 50ns and oscillator frequency will be
about 20MHz.
7.3 TWO INVERTERS FORM A
MEMORY CELL
Two inverters are connected in cascade with feedback
as shown in Fig. 7.4. This circuit behaves as a static
memory cell. This circuit hold value as long as power
is applied. We can also change the value of the memory
cell as shown in Fig. 7.5. Fig. 7.4 Two inverter form a memory cell
Initially, break the feedback path named remember
switch and data is loaded by load switch. Then the
output is data. When load switch is open and re-
member switch is closed, data will be stored. Sim-
ilar to inverter pair circuit, cross-coupled NAND
and NOR gates have capability to generate output
0 (reset) or 1 (set). On the other hand, we can say
that two NAND or NOR gates connected in such Fig. 7.5 Two inverter form a memory cell with
remember and load switch
a way that output of one NAND gate is used input
of another NAND gate or output of one NOR gate is used input of another NOR gate.

7.4 MEMORY CELL USING NAND AND NOR GATES

The memory cell can be implemented using NOR or NAND gates. Figure 7.6 shows the basic memory
cell using two NAND gates. The relationship between input
and output is
– – –
Q = A2 = A 1; Q = A1 = A 2
–
The outputs Q and Q are complements of each other. This
circuit has two stable states: Set and Reset. In set state, Q is
– –
1 and Q is 0. In reset state Q is 0 and Q is 1. If the circuit is
in 1 state, this memory cell remains in this state. Similarly, if
it is in 0 state, the circuit continuously to remain in this state. Fig. 7.6 One bit memory cell using
This property of the circuit is called as memory cell and it NAND gates
 264 Digital Electronics: Principles and Applications

Table 7.1 Truth table of one bit can store one bit information either 1 or 0. The operation of
memory cell using NAND gates one bit memory cell using NAND gates is represented by
Inputs Outputs Table 7.1.
– Figure 7.7 shows the circuit diagram of 1 bit memory cell
A1 A2 Q Q
using NOR gates and its truth table is depicted in Table 7.2.
0 1 1 0
The correlation between input and output is
1 0 0 1 – – –
Q = A2 = A 1 , and Q = A1 = A 2

Table 7.2 Truth table of one bit memory cell

using NOR gates

Inputs Outputs
A1 A2 Q
–
Q
0 1 1 0
1 0 0 1
Fig. 7.7 One bit memory cell using NOR gates

7.5 LATCH
Latch is a bistable device capable of staying in either of two states: Set and Reset for an indefinite time
period. Latches are basically similar to flip-flops as they have two states. But the difference between latches
and flip-flops is in the method of changing their states. When the Enable input of Latch is high, the output
of Latch changes depending upon inputs. If the Enable input of Latch is low, the output of Latch should
hold its previous state. The flip-flop is triggered by either positive edge or negative edge of clock signal for
changing their output states. When the clock signal changes from low to high state and the output changes
due to the inputs, it is called positive edge triggering flip-flop. If the clock signals change from high to low
state and the output changes due to the inputs, this condition is known as negative edge triggering flip-flop.
The difference between latch and flip-flop is illustrated in Table 7.3. Different types of latches are SR latch
and D latch. The operation of S-R latch and D latch is explained in Section 7.6 to 7.10.
Table 7.3 Difference between Latch and flip-flop
Latch Flip-flop
A latch is an electronic sequential logic circuit used to store A flip-flop is an electronic sequential logic circuit used to
information in an asynchronous arrangement. store information in an synchronous arrangement. It has
two stable states and maintains its states for an indefinite
period until a trigger pulse is applied.
One latch can store one bit information, but output state One flip-flop can store one bit data, but output state changes
changes only in response to data input. with trigger pulse only.
Latch is an asynchronous device and it has no clock Flip-flop has clock input and its output is synchronised
input. with clock pulse.
Latch holds a bit value and it remains constant until new Flip-flop holds a bit value and it remains constant until a
inputs force it to change. trigger pulse is received.
Latches are level-sensitive and the output tracks the input Flip-flops are edge-sensitive. They can store the input only
when the level is high. Therefore as long as the level is logic when there is either a rising or falling edge of the clock.
level 1, the output can change if the input changes.
 Flip-Flops 265

7.6 S-R LATCH USING NOR GATES

Figure 7.8 shows the two cross-coupled NOR gates. The NOR
gates are connected in such a way that the output of one feeds
back to the input of another. S and R are two inputs of S-R
latch. S is stands for set, it means that when S is 1, it stores 1.
Similarly, R stands for reset and if R=1, flip-flop reset and it’s
output will be 0. This circuit is called as NOR gate Latch or
S-R Latch. The functional table of S-R latch using NOR gate
Fig. 7.8 Cross-coupled NOR gates
is depicted in Table 7.4. The analysis of Table 7.4 is discussed
with the help of Fig. 7.9 (a), (b), (c) and (d).
Table 7.4 Truth table of S-R latch using cross-coupled NOR gates

Inputs Outputs Comments

–
S R Q Q
0 0 Latch Latch Hold
0 1 0 1 Reset
1 0 1 0 Set
1 1 0 0 Not used(Invalid)

S=0, R=0: The normal resting state of S-R Latch is S=0, and R=0. In this condition there is no effect on
–
output. Consequently, the state of Q and Q will not be changed. This is hold operation of S-R latch.

Fig. 7.9 (a) NOR Latch with R = 0 and S = 0 (b) NOR Latch with R = 1 and S = 0 (c) NOR Latch
with R = 0 and S = 1 (d) NOR Latch with R = 1 and S = 1(Invalid)
–
S=1, R=0: When S=1, and R=0, the output Q will be 1 and Q is equal to 0. This is called set operation
of S-R Latch.
 266 Digital Electronics: Principles and Applications

–
S=0, R=1: If S=0, and R=1, Latch reset the output. Accordingly output Q=0 and Q =1. This is known as
reset operation of S-R Latch.
–
S=1, R=1: If S=1 and R=1, latch is set and reset at the same time. The output will be Q=0 and Q =0.
–
But practically both outputs zero have no use. Therefore, this condition is invalid as the Q and Q outputs
must be complement of each other. Therefore, this is called an invalid or illegal state for the S-R latch.
Table 7.5 Truth table of NOR gate S-R latch Table 7.5 shows the truth table of S-R latch where Qn is
the present state and Qn-1 is the next state. Figure 7.10
Inputs Present state Next state
shows the state transition diagram of S-R latch. 0Æ0
S R Qn Qn+1
transition occurs when S = 0 and R=0 or S=0 and R=1.
0 0 0 0
0 0 1 1 Since R can be either 0 or 1, it may be indicated as don’t
0 1 0 0 care state represented by X symbol. Then 0Æ0 transition
0 1 1 0 is possible only when S=0 and R=X. The 0Æ1 transition
1 0 0 1 is generated if S=1 and R=0. Similarly, 1Æ0 transition
1 0 1 1
1 1 0 x occurs when S=0 and R=1. The 1Æ1 transition is gener-
1 1 1 x ated if S=X and R=0.
The timing diagram of a NOR latch for
different S-R inputs is depicted in Fig. 7.11.
Initially, R=1 and S=0, the output of S-R latch
–
Q is 0 and Q =0. After that R=0 and S=0, the
output of S-R latch does not changed and it
should retain its previous output. Therefore S-
–
Fig. 7.10 State transition diagram of S-R Latch R latch output Q is 0 and Q = 0. Then R=0 and
–
S=1, the output of S-R latch Q is 1 and Q =0 as
–
the latch is set. Afterwards R=1 and S=1, the output of S-R latch Q is 0 and Q =0 as this state is invalid
–
due to R=S=1. Then R=1 and S=0, the output of S-R latch Q is 0 and Q =1 as the latch is reset. Similarly,
other logic operations can be justified using Table 7.5.

Fig. 7.12 K map of S-R latch

Fig. 7.11 Timing diagram of S-R latch

The K-map of S-R latch with three inputs namely S, R, Qn and one
output Qn+1 is given in Fig. 7.12. The relationship between inputs and
output can be expressed by characteristic equation
–
Qn+1 = S + R Qn.
7.7 S-R LATCH USING NAND GATE
The S-R Latch can be constructed from two NAND gates as shown in
Fig. 7.13. Two NAND gates are cross-coupled. Output of one NAND Fig. 7.13 NAND latch
 Flip-Flops 267

–
gate is connected with the one input of the other NAND gate. Therefore, the output of gates Q and Q are
the latched outputs. In general, outputs are complement of each other. In latch, there are two inputs namely
Set (S) and Reset (R). Initially, S and R both inputs are 1 state. Then any one input will be changed to 0
(logic 0) for changing output. Truth table for operation of S-R latch using NAND gates is given in Table
7.6. The four possible states of S-R latch are shown in Fig. 7.14 (a), (b), (c) (d) and (e) and operation
detail is given below:
Table 7.6 Truth table of cross-coupled NAND gates
–
S R Q Q Comments
0 0 1 1 Not used
0 1 0 1 Reset
1 0 1 0 Set
1 1 Latch Latch Hold

Fig. 7.14 (a) NAND latch with R=0 and S=0 (Invalid) (b) NAND latch with R=1 and S=0 (c) NAND latch
with R=0 and S=1 (d) NAND latch with R=1 and S=1 (e) NAND latch with R=1 and S=1
 268 Digital Electronics: Principles and Applications

–
S=0, R=0: When S=0, R=0, the output of latch will be Q=1 and Q
=1. But practically both outputs high will not be allowed; therefore
this state is called invalid state of latch.
–
S=1, R=0: When S=1, and R=0, the output Q will be 1 and Q =0.
This is known as set operation of S-R latch.
S=0, R=1: If S=0, and R=1, flip flop reset the output. Therefore,
–
the output Q will be 0 and Q =1. This is called reset operation of
S-R latch.
Fig. 7.15 Symbol of S-R latch S=1, R=1: This is the normal resting state of S-R Latch when S=1,
R=1 and in this condition there is no effect on output. Consequently,
–
the state of Q and Q will not be changed. This is the holding state of latch. Figure 7.15 shows the logic
symbol of S-R latch.

7.8 S-R LATCH WITH ENABLE

In S-R latch using NOR or NAND gates, the output will be changed depending upon S and R inputs. But
sometimes output of S-R latch changes when only some conditions are satisfied. This means that output
is dependent on conditional input called enable (E). When E=0, the devices are disable and output has no
change. But when E=1, the device is enable and output depends on S and R inputs. Figure 7.16 shows the
S-R latch with enable. While the enable E is 0, the outputs
of AND gates will be 0. Accordingly, S and R both will be
0, NOR gates outputs cannot be changed and latching the
–
Q and Q outputs. If the enable input (E) is 1, the S-R latch
reacts with S and R inputs. The truth table of enabled S-R
latch is shown in Table 7.7. Figure 7.17 shows waveform
S-R latch with enable. It is depicted in Fig. 7.17 that anytime
S is 1 and R is 0, a logic level 1 on the E input sets the latch.
Anytime S is 0 and R is 1, a logic level 1 on the E input resets
the latch. The symbol of S-R latch with enable is depicted in
Fig. 7.16 S-R latch with enable Fig. 7.18.
Table 7.7 Truth table of S-R latch with enable
Enable Inputs Outputs Comments Remarks
–
E S R Q Q
–
0 0 0 Q Q Hold SR inputs are
–
0 0 1 Q Q Hold disabled
–
0 1 0 Q Q Hold
–
0 1 1 Q Q Hold
–
1 0 0 Q Q Hold SR inputs are
1 0 1 0 1 Reset enabled
1 1 0 1 0 Set
1 1 1 0 0 Invalid/not used
 Flip-Flops 269

Fig. 7.17 Waveform of S-R Latch Fig. 7.18 Symbol of S-R Latch with enable
with enable

7.9 THE D LATCH

In a cross coupled NAND gates as shown in Fig. 7.19, input D is connected with S and its complement
–
D is connected with R. If input D is 0, S=0 and R=1 and latch reset means Q=0, Q =1. When input D=1,
–
then S=1 and R=0 latch output Q=1 and Q =0. Table
7.8 shows the truth table of D latch. In a D latch,

Table 7.8 Truth table of D latch

Input Output
–
D Q Q
0 0 1
1 1 0

the output follows the input. When D=0, output Q=0

Fig. 7.19 D Latch and if D=1, output Q=1.

7.10 D LATCH WITH ENABLE

The D latch with enable has two inputs: one enable input (E) and other D input and one output Q
as shown in Fig. 7.20. When the enable (E) is
high, the D latch changes its states to whatever
in D input. If the enable (E) is low, the latch
does not change its state. Therefore, D latches
can be used as 1-bit memory device to store
logic level 1, high or logic level 0, low when
enable E is disabled. Hence, read new data
from the D input when enable E is enabled.
Figure 7.21 shows the state transition diagram
of the D latch. The enable input is not shown
Fig. 7.20 D latch with enable
in diagram as transitions occur only when the
enable is high. Table 7.9(b) shows the truth table of D latch representing present sate and next state
 270 Digital Electronics: Principles and Applications

Fig. 7.21 State diagram of D latch Fig. 7. 22 K-map of D latch

Table 7.9 (a) Truth table of D latch Table 7.9 (b) Truth table of D latch with E, D, Qn and Qn+1
–
E D Q Q ENABLE D Present State Next State
0 0 Latch Latch E Qn Qn+1
0 1 Latch Latch
0 0 0 0
1 0 0 1
0 0 1 1
1 1 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1

and the Karnaugh map for the next step of D latch from enable, D and present state Qn is depicted in
Fig.7.22. The expression for the next state output Qn+1 from the Karnaugh map is
–
Qn+1 = ED + E .Qn
As there are two 1’s in adjacent cells on the K-map, a static hazard is present in K-map. To eliminate
the static hazard, another term DQn will be added. Then static hazard free characteristic equation is
–
Qn+1 = ED + E .Qn + DQn
It is clear from this expression that the state of D latch does not change until the enable is high. If the
enable is asserted, the logic expression can be simplified as Qn+1
= D. Logic symbol of D flip-flop is shown in Fig. 7.23. Figure
7.24 shows the timing diagram of D latch. The outputs respond
to input D when the enable (E) input is high. When the enable
signal becomes low, the circuit remains latched. Any time D
is high and enable E is high, the output Q is high. Any time D
is low and enable E input is high, Q becomes low. When the
enable E input is low, the state of latch does not affected by the
D input. The advantages of enabled D latch is that it has only
one data input and when only output is required make the enable
Fig. 7.23 Logic symbol of D latch signal logic 1. The transition of D latch does not occur until E
with enable makes a 0Æ1.
 Flip-Flops 271

The operation of D latch can be

understood from a time delay
block diagram as depicted in
Fig. 7.25. The data input will
be available at the output only
after propagation time delay, td.
Therefore, this circuit also works
as delay circuit.
7.11 FLIP-FLOPS
A flip-flop is a device which
changes its state at the times Fig. 7.24 Timing diagram of D Latch with enable
when a change is taking place
in the clock signal. The flip-flop
is triggered by either positive
(leading) edge or negative (trail-
ing) edge of clock signal. In edge
triggering, the output of flip-flop
can be changed only when the Fig. 7.25
clock pulse is applied. If the
clock signal changes from low to high state and the output changes due to the inputs, it is called positive
edge triggering. When the clock signal changes from high to low state and the output changes due to the
inputs, this condition is called negative edge triggering. Most commonly used flip-flops are S-R, D, J-K
and T flip-flops. In this chapter, the operation of S-R, D, J-K and T flip-flops are discussed.

7.12 EDGE-TRIGGERED S-R FLIP FLOP

An edge-triggered flip-flop changes outputs either at the positive edge or negative edge of the clock
pulse. Figures 7.26 (a) and (b) show the clocked R-S flip-flop using NAND and NOR gates respectively
and this flip-flop is triggered on the positive edge of clock. The output of flip- flop can be changed when
clock is applied and transition takes place 0 to 1. Therefore, S and R are the inputs of flip-flop and clock
pulse is applied for changing the state of flip-flop. Truth table of clocked S-R flip-flop is illustrated in
Table 7.10. This is explained the operation of S-R flip-flop with inputs and clock. The operation of S-

Fig. 7.26 (a) Clocked S-R flip-flop using NAND gates (b) Clocked S-R flip-flop using NOR gates
 272 Digital Electronics: Principles and Applications

R flip flop can be analysis by waveform. Generally 50%

duty cycle clock pulse is used for clocked S-R flip-flop,
so that inputs S and R gets enough time to settle the effect
on to change output. Figure 7.27 shows the controlling of
S-R flip-flop with a clock and it has two states: stable state
and changing state. In stable state, clock is low and inputs
S and R cannot change the output of flip-flop. S and R
inputs only change output in half of clock period when
Fig. 7.27 The controlling of S-R flip-flop clock signal transition is 0Æ1 called changing state. At
with a clock the positive edge of clock pulse (CLK) - 1, S=1 and R=0,
Q changes from logic level 0 to logic level 1. Similarly, at the positive edge of clock pulse (CLK) – 2,
S=0 and R=1, Q changes from logic level 1 to logic level 0.
Symbols of positive edge-triggered without bubble at clock input and negative edge-triggered with
bubble at clock input are shown in Fig. 7.28 (a) and (b) respectively.

Fig. 7.28 (a) Positive edge triggered S-R flip-flop (b) Negative edge triggered S-R flip-flop

The truth table of positive edge triggered S-R flip-flop is given in Table 7.10. When S = 1 and R = 0,
flip-flop sets on the rising clock edge. If S = 0 and R = 1, flip-flop resets on the rising clock edge. The S
and R inputs can be changed at any time when the clock input is low or high. It is depicted in Fig. 7.27
that output changes at the transition of clock from low to high. The operation and truth table of negative
edge-triggered flip-flop are the same as positive edge triggered flip-flop but only difference is trigger
edge that will be negative or falling edge of the clock pulse. Therefore, flip-flop will be set or reset at the
negative or falling edge of the clock pulse.
Table 7.10 Truth table of positive edge triggered S-R flip-flop
Inputs Outputs Comments
–
Clock S R Q Q
(CLK) –
0 0 Q Q No change
Ø
Ø
0 1 0 1 Reset
Ø
1 0 1 0 Set
Ø
1 1 ? ? Invalid

7.13 CASCADING S-R FLIP-FLOPS

Flip-flops are the building block of sequential circuits. In sequential circuits, data can flow from one
flip-flop to other on each successive clock pulse. Therefore, flip-flops are connected in cascade means
 Flip-Flops 273

connect output of one flip-flop

to input of another. Figure 7.29
shows cascaded S-R flip-flops in
master slave form. When the clock
changes low to high, the output of
master flip-flop changes and input
to the slave flip-flop. The output of
slave flip-flop is not affecting as Fig. 7.29 Master-slave S-R flip-flop
inverted clock pulse is applied to
slave flip-flop. Maser flip-flop’s output can be
transferred to slave flip-flop when clock changes
high to low. So, at the end of each clock pulse, the
output of salve flip-flop changes and shifting of
data in cascaded maser-slave flip-flop. Waveform
of master-slave S-R flip-flop is depicted in Fig.
7.30. At the instant of first positive edge clock
pulse S=1 and R=0, the output of master flip-flop
–
is P = 1 and P = 0. As inverted clock pulse is
applied to the slave flip-flop, when the clock Fig. 7.30 Waveform of master-slave S-R flip-flop
pulse changes from 1 to 0, the first positive edge
–
clock pulse is applied to the slave flip-flop. Therefore, the output of slave flip-flop will be Q=1 and Q =
0. Similarly, other operations of master slave SR flip-flop can be justified using truth table.
7.14 S-R FLIP-FLOP WITH ASYNCHRONOUS INPUTS
–
In normal S-R flip-flop, output Q and Q will be
depends upon synchronous inputs S, R and clock
–
signal. Outputs Q and Q are also synchronised with
clock signal. In asynchronous S-R flip-flop with
asynchronous inputs, the flip-flop can be set or reset
regardless of S, R and clock signal. These inputs are
called preset (PRE) and clear (CLR).
Figure 7.31 shows the logic symbol of asynchronous
S-R flip-flop. Implementation of asynchronous S-
R flip-flop using NAND gates is given in Fig.7.32.
While the preset input (PRE) is high and clear input
– Fig. 7.31 (a) Logic symbol of Asynchronous
(CLR) is low, the flip-flop will be Q=0, Q = 1 despite S-R flip-flop with preset and clear (b) Logic
the consequences of synchronous inputs and the clock symbol of Asynchronous S-R flip-flop with
signal. So, the flip-flop is in reset state or cleared. If inverted preset and clear
the clear input (CLR) is high and the preset input
–
(PRE) is low, the flip-flop will be set as Q = 1, Q = 0. But, if both preset (PRE) and clear inputs (CLR)
–
are low, both Q and Q will be 1. This condition is an invalid state of the flip-flop and PRE=CLR=0 is
not allowed. Truth table of asynchronous SR flip-flop is shown in Table 7.11. Preset (PRE) and clear
(CLR) inputs will be used when multiple flip-flops are connected in a group to achieve a function on a
 274 Digital Electronics: Principles and Applications

multi-bit binary word and a single line is required to

set or reset all flip-flops at a time. Asynchronous inputs
may be active-high or active-low. If inputs are active-
low, there will be an inverting bubble at that input on
the block symbol same as the negative edge-triggered
clock inputs.
Table 7.11 Truth table of asynchronous S-R flip-flop
Clock Clear Preset Output Comments
(CLK) (CLR) (PRE)
1 0 0 Qn+1 Normal flip-flop
0 0 1 0 Clear
0 1 0 1 Preset
Fig. 7.32 Logic diagram of S-R flip-flop
0 0 0 Not
with preset and clear
allowed

Example 7.1 Determine the output waveform when of S-R latch when the inputs as shown in Fig. 7.33
are applied. Consider initial output of S-R Latch is low and enable is always high.

Fig. 7.33
� Solution
The output waveform of S-R Latch is illustrated in Fig. 7.34. Initial output
of S-R latch Q is 0. When S=1, R=1, this is the invalid state of SR Latch and
output Q is 0. After that S=0 and R=1, the latch is reset. So the output Q has not
changed and it retain at 0. Then S=1 R=0, latch is set. So the output Q changes
from 0 to 1. Similarly, other outputs of SR latch can be justified. Fig. 7.34

Example 7.2 Write the output of a clocked S-R flip-flop when the inputs are R=011001 and
S = 101100. Assume initially Q is low.
� Solution

Table 7.12
The output of S-R flip-flop Qn+1 is shown
Inputs Outputs in Table 7.12. Initial output Qn is 0. If S=1,
CLK S R Qn Qn+1 R=0, Qn=0 and first clock pulse is applied,
1 0 0 1 the next state output Qn+1 will be 1. When
Ø
0 1 1 0
Ø
S=0, R=1, Qn=1 and second clock pulse is
1 1 0 0
Ø
applied, the next state output will be 0. In
1 0 0 1
Ø
the same way, remaining next state outputs
0 0 1 1
Ø
with respect to clock pulse can be justified
0 1 1 0
Ø
using truth table of S-R flip-flop.
 Flip-Flops 275

Example 7.3 Draw the output waveform of a positive edge triggered S-R flip-flop when the
inputs are given in Fig. 7.35.
Assume initially flip-flop output is low.
� Solution
The output waveform is shown in Fig. 7.36. If S=1, R=0 and positive edge triggers
applied, the flip-flop will be set. If S=0, R=1 flip flop will be reset when positive
edge triggered applied. At the instant of first clock pulse, S=0 and R=1, flip-flop Fig. 7.35
will be reset and output Q is 0. During the second clock pulse, S=0 and R=0 and
flip-flop should retain its previous state and there will be no change in output. So
the output Q = 0. Subsequently, S=1 and R=1, flip-flop operates in invalid state
and output Q=0. At the instant of fourth clock pulse, S=0 and R=0, the output of
the flip-flop Q is =0. During the fifth clock pulse, S=1 and R=0, flip-flop is set
and output Q =1.
Fig. 7.36
7.15 EDGE-TRIGGERED D FLIP-FLOPS
The operation of D latch is already discussed in Section 7.9 and 7.10. It responds to the data inputs D
only when the enable input is high. But, the edge triggered D flip-flops responds on either the rising or
falling edge of a clock pulse when a clock signal is applied. In edge triggered D flip-flop, data can be
transmitted from inputs to outputs on the ris-
ing (positive) or falling (negative) edge of
clock pulse. The clocked D flip-flop has two
inputs: a clock input and D input. At the in-
stant when clock changes from low to high
or from high to low, the flip-flop changes its
states to whatever in D input. If the clock is
disabled, the flip-flop does not change its
state. Consequently, D flip-flops can be used
as 1-bit memory device to store either 1, high Fig. 7.37 Positive edge triggered D flip-flop
or 0, low state when clock is disabled, and
read new data from the D input when clock Table 7.13 Truth table of D flip-flop
is enabled. Figure 7.37 shows the positive Clock D Present State Next State
edge triggered D flip-flop. Table 7.13 shows (CLK) Qn Qn+1
the truth table of D flip flop representing 0 0 0 0
present sate and next state and the Kar- 0 0 1 1
0 1 0 0
0 1 1 1
0 0 0
Ø
0 1 0
Ø
1 0 1
Ø
1 1 1
Ø

naugh map for the next state output of D flip-flop Qn + 1 from clock
CLK, data input D and present state Qn is depicted in Fig.7.38. The
Fig. 7.38 K map of D flip-flop expression for Qn + 1 from the Karnaugh map is
———
Qn + 1 = CLK.D + C L K . Qn
 276 Digital Electronics: Principles and Applications

It is clear from this expression that the state of D

flip-flop does not change until the clock is enabled. The
timing diagram for a positive edge-triggered D flip-flop
is depicted in Fig. 7.39. The outputs respond to input D
at the positive edge of clock input only. In this timing
diagram, output only responds to the D input due to
transitions of the clock signal from low to high.
In negative edge triggering, output only responds
Fig. 7.39 Response of positive edge triggered to the D input when the clock signal changes from
D flip-flop high to low. The negative edge triggered flip-flop
produces the following response as given in Fig. 7.40. At the instant of first negative edge of clock pulse,
D=0, the output of D flip-flop Q=0. During the second negative edge of clock pulse, D=1, the output
of D flip-flop Q changes from 0 to 1. Logic symbol of positive edge triggered and of negative edge
triggered D flip-flops are shown in Fig. 7.41(a) and Fig. 7.41(b) respectively.

Fig. 7.40 Response of negative edge Fig. 7.41 (a) Logic symbol of positive edge
triggered D flip-flop triggered D flip-flop (b) Logic symbol
of negative edge triggered D flip-flop
7.16 D FLIP-FLOP WITH ASYNCHRONOUS INPUTS
–
In D flip-flop, outputs, Q and Q will depend on synchro-
–
nous input D and outputs Q and Q are synchronised with
clock signal. In asynchronous D flip-flop, asynchronous
inputs can set or reset the flip-flop regardless of D and
clock signal. These inputs are called preset (PRE) and
clear (CLR). Figure 7.42 shows the asynchronous D flip-
flop. When the preset input (PRE) is high and the clear
input (CLR) is low, the D flip-flop will be cleared or
–
reset (Q=0, Q=1) despite the consequences of synchro-
nous inputs or the clock signal. If the preset input (PRE)
is low and the clear input (CLR) is high, the D flip-flop
–
Fig. 7.42 (a) Logic symbol of asynchronous D
will be set (Q=1, Q= 0). Preset (PRE) and clear (CLR)
flip-flop with preset and clear inputs will be used when multiple D flip-flops are con-
(b) Logic symbol asynchronous D nected in a group. Asynchronous inputs may be active-
flip-flop with inverted preset and high or active-low. If inputs are active-low, there will be
clear
an inverting bubble at that input on the block symbol
same as the negative edge-triggered clock inputs.
 Flip-Flops 277

Example 7.4 Determine the output waveform of level triggered D flip-flop if the inputs waveform is
shown Fig. 7.43(a) as given below:

Fig. 7.43(a) Fig. 7.43(b)

� Solution
A level triggered D flip-flop is nothing but a D flip-flop with enable input E. When enable input E =0, the D flip-
flop should hold its previous output. If enable input E = 1, the output of D flip-flop will be the data input D. Assume
initial output of D flip-flop is 0. The output waveform of level triggered D flip-flop is shown in Fig. 7.43(b).

Example 7.5 What is race around condition of data transfer using negative edge triggered D flip-
flops? How can it be removed?
� Solution
Figure 7.44 shows the race around condition of data transfer using negative edge triggered D flip-flops. At
the instant of negative edge of the first clock pulse, Q0 becomes high or logic 1 after a propagation delay tPLH.
At the negative edge of the second clock pulse, Q0 becomes logic level 0 after a time delay tPLH. The flip-flop
FF1 is also clocked and its input is 1. Then output of FF1 is Q1=1 which creates a race condition. Actually,
a marginal condition becomes arise as Q0 does not remain in high or logic 1 after the second negative
triggering edge of the clock. Therefore, logic level 1 may not be transferred. To transfer data, Q0 must be
remaining high for time equal to the hold time thold. The data can only be transferred if tPHL> thold. If thold > tPHL,
a unreliable data transfer is created. This condition is known as race around condition of data transfer using
D flip-flops. To remove this condition, the master slave flip-flops will be used.

Fig. 7.44 Data transfer using negative edge triggered D flip-flops

7.17 THE J-K FLIP-FLOP

In S-R flip-flop, when S=1, R=1, output of flip-flop is invalid. To eliminate the invalid condition,
an feedback is added with S-R flip-flop. This feedback selectively enables set and reset inputs. This
modified S-R flip-flop is called J-K flip-flop as shown in Fig. 7.45. The operation of J-K flip-flop is
–
shown in Table 7.14. When both J and K inputs are logic 0, the outputs Q and Q will not change and
flip-flop stores the information like a latch. If J=0 and K=1, the flip-flop reset and the output Q = 0 and
 278 Digital Electronics: Principles and Applications

– –
Q =1. When J=1, K=0, the flip-flop set and the output Q=1 and Q =
0. While both J and K inputs activated (J=1, K=1), the outputs Q and
–
Q will swap states. If the flip-flop is in set state, it will be changed to
reset state. On the other hand, reset flip-flop will be changed to set state.
Therefore, the J-K flip-flop will toggle from a set state to a reset state,
or visa-versa. It is depicted in Table 7.14 that the S-R flip-flop’s invalid
state is eliminated and the additional feature, ability to toggle between
Fig. 7.45 J-K flip-flop the two stable output states is incorporated.
Table 7.14 Truth table of J-K flip-flop
Inputs Outputs –
J K Q Q
0 0 Latch Latch
0 1 0 1
1 0 1 0
1 1 Toggle Toggle

7.17.1 Clocked J-K Flip-Flop

Figure 7.46 shows the clocked J-K flip-flop. The clocked J-K flip-flop has three inputs: a clock input and
other two inputs called as J and K. Figure 7.47 shows the state transition diagram of J-K flip-flop. When
the clock is asserted, the state of flip-flop can be changed depending on the condition of J and K. When

Fig. 7.46 Clocked J-K flip-flop

Fig. 7.47 State transition diagram of J-K flip-flop

the clock is not asserted, the output of J-K

flip-flop is same as the previous sate output. Table 7.15 Truth table of J-K flip-flop
When J=0, K=1 and clock is asserted, the Clock J K Present State Qn Next State Qn+1
next state output is the complement of 0 0 0 0 0
K. If J=1, K=0 and clock is asserted, the 0 0 0 1 1
0 0 1 0 0
next state output is J. When J=1, K=1 and 0 0 1 1 1
clock is asserted, the next state output is 0 1 0 0 0
0 1 0 1 1
the complement of previous state and flip- 0 1 1 0 0
flop operates as toggle switch. The truth 0 1 1 1 1
1 0 0 0 0
table of J-K flip-flop for present state and 1 0 0 1 1
next stable state is depicted in Table 7.15. 1 0 1 0 0
1 0 1 1 0
Karnaugh map for the next state output is 1 1 0 0 1
shown in Fig. 7.48. The logical expression 1 1 0 1 1
— – 1 1 1 0 1
of Qn+1 is Qn+1 = JQn + K Qn 1 1 1 1 0
 Flip-Flops 279

7.17.2 Edge-Triggered J-K Flip-Flops

The J-K flip-flop will continuously toggle between two output states when both J and K are in high state
and the edge triggering of the clock input is not applied. Then J-K flip-flop operates as an astable device.
To operate as a bistable device, edge triggering is used so that it toggles only when the clock is asserted
on either the rising or falling edge of a clock pulse. The positive and negative edge-triggered J-K flip-
flops are depicted in Fig. 7.49 (a) and Fig. 7.49 (b) respectively.

Fig. 7.48 Karnaugh map of Fig. 7.49 (a) Logic symbol of positive edge triggered
J-K flip-flop J-K flip-flop (b) Logic symbol of negative edge
triggered J-K flip-flop
7.17.3 J-K Flip-Flop with Asynchronous Inputs
Asynchronous inputs on a J-K flip-flop have control over
–
the Q and Q outputs. These inputs are called the preset, PRE
and clear, CLR. The preset input drives the flip-flop to a
clear or reset state whereas the clear input drives it to a set
state. Figure 7.50 shows the asynchronous J-K flip-flop. If
the preset input is high and the clear input is low, the J-K
–
flip-flop will be cleared and outputs will be Q= 0 and Q =1
despite the consequences of synchronous inputs and the
clock signal. If the clear input is high and the preset input
–
is low, the J-K flip-flop will be set (Q=1, Q=0). The preset
(PRE) and clear (CLR) inputs will be used when multiple J-
K flip-flops are connected in a group. Asynchronous inputs Fig. 7.50 (a) Logic symbol of asynchro-
may be active-high or active-low. If inputs are active-low, nous J-K flip-flop with reset and clear
(b) Logic symbol of asynchronous J-K
there will be an inverting bubble at that input on the block
flip-flop with inverted reset and clear
symbol just like the negative edge-trigger clock inputs.
7.17.4 J-K Master Slave Flip-Flop
It is clear from Table 7.15 that the flip-flop is disabled when clock (CLK) =0 and flip-flop is active when
clock (CLK) = 1. Figure 7.46 exhibits instability when J=1, K=1 and CLK=1 due to the feedback of the
complementary output signals to input. In this condition the output Q is oscillatory and will stay in this
state until clock changes from 1 to 0. To overcome these difficulties, a J-K master slave flip-flop is used.
In J-K flip-flop, if J=1, K=1, Q=0 and when clock pulse is applied then output Q=1. This change in
output takes place after a propagation delay time tPLH. Now J=1, K=1 and Q=1 and if the clock pulse
is still present, Q changes back to 0. So for the certain duration of the clock pulse tP, the output will
oscillate between 0 and 1. The output Q is ambiguous. This situation is called as race-around condition.
To eliminate the race-around condition, tPHL must be grater than clock pulse tP. Therefore, J-K master
slave flip-flops are introduced to solve this problem.
 280 Digital Electronics: Principles and Applications

Figure 7.51 shows the diagram of J-K master slave flip-flop. This is the cascade connection of two
J-K flip-flops. The first flip-flop is called master and other one is called as slave. The master is clocked in
the normal way but the inverted clock is applied to slave. It is assumed that the changes in J and K inputs
does not effect on output when clock is low and master flip-flop is disabled. When the clock changes low
–
to high, the output of master flip-flop (Qm and Q m) changes and these changes are fed to the input of the
–
slave flip-flop. But there is no change at the output of slave flip-flop (Q and Q ) as inverted clock pulse is
–
applied to slave flip-flop. Consequently, feedback inputs Q and Q will not effect due to no change. When
clock changes high to low, master’s output can be transferred to slave flip-flop. Therefore, the output of
slave flip-flop changes by shifting data from maser to slave flip-flop at the end of each clock pulse. The
timing diagram of J-K master slave flip-flop is shown in Fig. 7.52.

Fig. 7.51 J-K Master slave flip-flop Fig. 7.52 Waveform of J-K flip-flop

Example 7.6 Draw the output waveform of J-K master slave flip-flop with the following inputs as
shown Fig. 7.53.

� Solution
Figure 7.54 shows the output waveform of J-K master slave flip-flop, where
–
Qm and Q m are outputs of master flip-flop and slave flip-flops outputs are Q
–
and Q . The master flip-flop is positive edge triggered but the slave flip-flop
Fig. 7.53
is negative edge triggered. Initially, J=1 and K=0 and output of the master
–
flip-flop will be Qm =1 and Q m= 0 just after the positive edge of first clock
pulse. Before the negative edge of first clock pulse, inputs of slave flip-flop
–
are J = Qm =1 and K= Q m= 0. After the negative edge of first clock pulse,
–
outputs of slave flip-flops are Q = 1 and Q = 0. Thus, we can also justify the
other outputs of J-K master slave flip-flop for remaining clock pulses.

7.18 T FLIP-FLOP Fig. 7.54

Figure 7.55 shows the symbol of T flip-flop and table of operation is given in Table 7.16. When T=0,
output of T flip-flop Qn+1= Qn. When T=1, output of T flip-flop Qn+1 is complement of Qn. As output of
—
flip-flop is complement of Qn , Qn this circuit is known as toggle circuit.
 Flip-Flops 281

Table 7.16 Truth table of T flip-flop

Input Output
T Present State Next State Remarks
Qn Qn+1
0 0 0 Latch
0 1 1 Fig. 7.55 Symbol of
1 0 1 Toggle T flip-flop
1 1 0

7.18.1 T Latch with Enable

A T latch with Enable has two inputs namely a enable input,
E and data input, T. When enable input E is asserted, the state
of T flip-flop changes. Figure 7.56 shows the state transition
diagram of the T latch. The truth table of T latch with present
state and next state is depicted in Table 7.17. Figure 7.57
Fig. 7.56 T Latch
shows the Karnaugh map for next state transition Qn+1 of
T latch with enable and present state as inputs. The logic
expression of the next state is
– —
Qn+1 = T Qn + T Q n .
The logic symbol is depicted in Fig. 7.58.
Table 7.17 Truth table of T Latch Fig. 7.57 Karnaugh
map of T latch
Enable T Present State Qn Next State Qn+1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0 Fig. 7.58 Logic symbol of
T latch with enable
7.18.2 Edge-triggered T Flip-Flops
The edge triggered T flip-flop reacts to the data input
T only when the clock input is activated. The clock is
asserted on either the rising or falling edge of a clock
pulse. The positive and negative edge-triggered D
flip-flops are depicted in Fig. 7.59 (a) and Fig. 7.59(b)
respectively.
Fig. 7.59 (a) Logic symbol of positive edge
7.18.3 T Flip-Flop With Asynchro- triggered T flip-flop
nous Inputs (b) Logic symbol of negative edge
triggered T flip-flop
Figure 7.60 shows the asynchronous T flip-flop. If
–
the preset input is high and the clear input is low, the T flip-flop will be clear (Q=0, Q =1) despite the
 282 Digital Electronics: Principles and Applications

consequences of synchronous inputs or the

clock signal. If the preset input is low and the
clear input is high, the T flip-flop will be set
–
(Q=1, Q =0). Preset (PRE) and clear (CLR)
inputs will be used when multiple T flip-flops
are connected in a group. Asynchronous inputs
may be active-high or active-low. If inputs are
active-low, there will be an inverting bubble Fig. 7.60 (a) Logic symbol of asynchronous T flip-
flop with reset and clear (b) Logic symbol
at that input on the block symbol same as the of asynchronous T flip-flop with inverted
negative edge-triggered clock inputs. reset and clear

Example 7.7 The waveforms as depicted in Fig. 7.61 are applied to a T flip-flop. Draw the output
waveform of the clocked T flip-flop.
� Solution
The output waveform of clocked T flip-flop is shown in Fig. 7.62.
Assume the initial state of T flip-flop Q is 0. During the first clock pulse Fig. 7.61
T=0, then output Q will be 0. At the instant of second clock pulse, T=1,
the output will be the complement of previous state. So, the output Q
is 1. Similarly, we can determine the output of T flip-flop for remaining
clock signal and T input.
Fig. 7.62

Example 7.8 A positive edge triggered T flip flop with PRE and CLR inputs is shown in Fig. 7.63.
Draw the output waveform. Consider initial output is low.

� Solution

Figure 7.64 shows the output waveform and its

explanation is given below:

v During the first clock pulse, the preset (PRE) and

clear (CLR) are low and T is high. The flip-flop
operates in toggle mode.
Fig. 7.63
v In second, third and fourth clock pulse preset
(PRE) is high and clear (CLR) is low, flip flop is
reset and output does not depend on input.
v During the fifth clock pulse, both preset (PRE) and clear
(CLR) are low and T is high. Then flip-flop again operates in
toggle mode.
v For sixth and seventh clock pulse, preset (PRE) is low and
clear (CLR) is high, flip flop is set regardless of synchronous
input. Fig. 7.64
 Flip-Flops 283

7.19 CONVERSION FROM ONE TYPE OF FLIP-FLOP TO ANOTHER

TYPE
The circuit diagram, logic symbol and working principle of S-R, J-K, D and T flip-flops are already in-
corporated in this chapter. Presently, the conversion from one type of flip-flop to another type by using
a formal technique is explained in this section. The problem of changing from one type flip-flop to
another type is the design
of second type of flip-flop
using the first flip-flop as
a memory element. This
conversion is very useful
in the design of clocked
sequential circuits.
Figure 7.65 shows the
bock diagram for conver-
sion from one type flip- Fig. 7.65 Block diagram of conversion of one type of flip-flop to another
flop to another type. In
this conversion process, some steps are followed. The first step of conversion is that write the present
and next state truth table of flip-flops. The next step is to design a combinational logic circuit to produce
the next state output from inputs and present output state using Karnaugh map. The final step is imple-
mentation of combinational logic circuit using logic gates. The conversion of S-R to J-K, J-K to S-R, J-K
to D, J-K to T, S-R to T and D to T are explained in this section.
7.19.1 Conversion of S-R FLIP-FLOP to J-K FLIP-FLOP
The truth tables of S-R and J-K FLIP-FLOP are depicted in Table 7.18, which will be used for conversion
from S-R flip-flop to J-K flip-flop. Figures 7.66 (a) and 7.66(b) show the Karnaugh map for S and R with
J, K and Qn inputs. From these K-maps the logic expressions for S and R are derived as follows:
–
S = J.Qn and R = K.Qn.
The implementation of JK flip-flop using SR flip-flop and logic gates is shown in Fig. 7.67.

Table 7.18 Truth table of J-K and S-R flip-flop

J-K FLIP-FLOP inputs Output S-R FLIP-FLOP inputs

J K Qn Qn+1 S R
0 0 0 0 0 x
0 1 0 0 0 x
1 0 0 1 1 0
1 1 0 1 1 0
0 0 1 1 x 0
0 1 1 0 0 1
1 0 1 1 x 0
1 1 1 0 0 1
 284 Digital Electronics: Principles and Applications

Fig. 7.66 (a) K-map for S (b) K-map for R

7.19.2 Conversion of J-K FLIP-FLOP to S-R

FLIP-FLOP
The truth table for conversion from J-K to S-R flip-flop is shown in
Table 7.19. Figure 7.68 shows the Karnaugh map for J and K with
S, R and Qn inputs. From these K-maps the logic expressions for J Fig. 7.67 Conversion from SR
and K are derived as follows: flip-flop to JK flip-flop
–
J = SR and K = RQn
Figure 7.69 shows the conversion of J-K flip-flop to S-R flip-flop by using a additional circuit consists
of one NOT and two AND gates

Table 7.19 Truth table of J-K and S-R flip-flop

S-R FLIP-FLOP inputs Output J-K FLIP-FLOP inputs

S R Qn Qn+1 J K
0 0 0 0 0 x
0 1 0 0 0 x
1 0 0 1 1 0
1 1 0 0 0 0
0 0 1 1 x 0
0 1 1 0 0 1
1 0 1 1 x 0
1 1 1 0 0 1

Fig. 7.68 (a) K-map for J (b) K-map for K

 Flip-Flops 285

Fig. 7.69 Conversion of J-K flip-flop to S-R flip-flop

7.19.3 Conversion of J-K FLIP-FLOP to T FLIP-FLOP

Truth table of conversion from J-K to T flip-flop is given in Table 7.20. It is clear from table that when
J and K inputs of J-K flip-flop are connected, it behaves as a T flip-flop. The logical expression for T is
J=K=T. Figure 7.70 shows the conversion of J-K flip-flop to T flip-flop.

Table 7.20 Truth table of conversion from J-K to T flip-flop

T flip-flop inputs Output J-K flip-flop inputs

T Qn Qn+1 J K
0 0 0 0 0
0 1 1 0 0
1 0 1 1 1 Fig. 7.70 Conversion
1 1 0 1 1 from J-K to T flip-flop

7.19.4 Conversion of D FLIP-FLOP to T FLIP-FLOP

Table 7.21 shows the truth table of conversion from D to T flip-flop. Using this table, the logical
– —
expression of D can be derived as a function of T and Qn. So D (T, Qn) = Qn.T + QnT = Qn≈T. The
implementation conversion of D flip-flop to T flip-flop using logic expression D(T,Qn)= Qn≈T is shown
in Fig. 7.71.
Table 2.21 Truth table of conversion from D to T flip-flop

T flip-flop inputs Output D flip-flop inputs

T Qn Qn+1 D
0 0 0 0
0 1 1 1
1 0 1 1 Fig. 7.71 Conversion of
1 1 0 0 D flip-flop to T
flip-flop

7.19.5 Conversion of SR FLIP-FLOP to T FLIP-FLOP

The truth table of conversion from S-R to T flip-flop is shown in Table 7.22. Using this table, the logical
—
expressions S(T,Qn) and R(T,Qn) are derived as S(T,Qn) = TQn and R(T,Qn) = TQn. The implementation
—
conversion of S-R to T flip-flop using logic expressions S(T,Qn) = TQn and R(T,Qn) = TQn is shown in
Fig. 7.72.
 286 Digital Electronics: Principles and Applications

Table 7.22 Truth table of conversion from SR to T flip-flop

T flip-flop inputs Output SR flip-flop inputs

T Qn Qn+1 S R
0 0 0 0 x
0 1 1 0 0
1 0 1 1 0
1 1 0 0 1 Fig. 7.72 Conversion of SR
flip flop to T flip-flop

7.19.6 Conversion of J-K FLIP-FLOP to D FLIP-FLOP

J-K flip-flop can be operate as a D flip-flop as shown in Fig. 7.73. The truth table of conversion from J-K to D
flip-flop is shown in Table 7.23. It is depicted in table that the input data will be transferred at the output when
–
clock is applied. Using this table, the logical expressions for J and K is derived as J=D, K = D.

Table 7.23 Truth table of conversion from JK to T flip-flop

D flip-flop inputs Output JK flip-flop inputs
D Qn Qn+1 J K
0 0 0 0 0
0 1 0 0 1
1 0 1 1 0 Fig. 7.73 Conversion JK
flip-flop to D
1 1 1 0 0 flip-flop

Example 7.9 Convert T flip-flop into J-K flip-flop

� Solution
The truth table of conversion from T flip-flop to J-K flip-flop is shown in Table 7.24. Using this table, the
—
logical expression of T(J, K, Qn) can be derived from K-map as given in Fig. 7.74. Here, T is T(J,K,Qn) = J Qn
—
+ KQn. The implementation conversion of T to J-K flip-flop using logic expression T(J,K,Qn) = JQ n+KQn is
shown in Fig. 7.75.

Table 7.24 Truth table of conversion from T to JK flip flop

J-K FLIP-FLOP inputs Output T FLIP-FLOP input
J K Qn Qn+1 T
0 0 0 0 0
0 1 0 0 0
1 0 0 1 1
1 1 0 1 1
0 0 1 1 0
0 1 1 0 1
1 0 1 1 0
1 1 1 0 1
 Flip-Flops 287

Fig. 7.74 K-map for T Fig. 7.75

7.20 OPERATING CHARACTERISTICS OF FLIP-FLOPS

In the application of flip-flops, the following parameters are always specified by the manufacturers
v Propagation Delay Time
—–– —––
tPLH(CLK to Q), tPHL(CLK to Q), tPLH(PRE to Q), and tPHL(CRE to Q)
v Set up time
v Hold time
v Maximum clock frequency
v Pulse width
v Power dissipation

Propagation Delay Time Propagation delay time means that the required interval times to
change the output after applying the input signal. The performance of flip-flop can be measured by dif-
ferent propagation delays:
Propagation delay tPLH (CLK to Q) is measured from the 50% triggering edge point of the clock pulse
to the 50% transition of the output from Low to High. This time delay is shown in Fig.7.76

Fig. 7.76 Propagation delays tPLH clock to output

Propagation delay tPHL (CLK to Q) is measured from the 50% triggering edge of the clock pulse to the
High to Low transition of the output as depicted in Fig. 7.77.
 288 Digital Electronics: Principles and Applications

—––
Propagation dealy tPLH (PRE to Q) is measured from the 50% preset input to the Low to High transition
of th e output. This delay is shown in Fig. 7.78.

Fig. 7.77 Propagation delays tPHL clock to output Fig. 7.78 Propagation delays tPLH preset to
output

— ––
Propagation dealy tPHL (CLR to Q) is measured from the 50% clear input to the High to Low transition
of the output as depicted in Fig. 7.79

Maximum clock frequency ( fmax ) Maximum clock frequency is the highest clock frequency
at which the flip-flop can be triggered. If the clock frequency is above maximum, the flip-flop will not
be able to respond properly.

Setup time (tset up ) Set up time is the minimum time that input signal must be present on input
terminal prior to the triggering edge of the clock pulse as depicted in Fig. 7.80. tset up is approximately
20ns for TTL ICs. Therefore, the input of a D FF must be held constant for at least 20ns before applying
a positive edge-triggering clock into the flip-flop.

Fig. 7.79 Propagation delays tPHL clear to output Fig. 7.80 Set-up time

Hold time (thold ) The hold time is the minimum time interval that signal must remain at the terminal
after the triggering edge of the clock pulse. thold is approximately 5ns. Therefore, the input signal of D
flip-flop will be removed at about 5ns after the positive edge of the clock has applied. Figure.7.81 shows
the hold time of a D flip-flop.
 Flip-Flops 289

Pulse width Generally, the manufacturer specifies

the minimum pulse widths for the clock, preset, and clear
inputs to operate flip-flop adequately. Typically, the clock
is specified by its minimum high pulse width and minimum
low pulse width.
Clock high pulse width This is the minimum time that
clock must remain in its high state for reliable operation. It Fig. 7.81 Hold time
is approximately 15ns.
Clock low pulse width This is the minimum time that clock must remain low for reliable opera-
tion. This time is approximately 30ns.

Power dissipation The power dissipation is one of the important characteristics of flip-
flops. It is actually the total power consumption on the device and measured from P=Vcc Icc. If the
flip-flop operates on a 5V dc supply and draws 25 mA current, the power dissipation will be P=Vcc
Icc=5V×25mA=125mW.
The comparison of operating performance of different flip-flop ICs is given in Table 7.25.

Table 7.25 Comparison of operating performance of flip-flops

Flip-flop Flip-flop ICs

parameters 7474(TTL) 7476(TTL) 7471(TTL) 74107(TTL) 74112(CMOS)
fmax MHz 15 45 3 20 20
tPHL(CLK to Q) 40 20 150 40 31
tPLH(CLK to Q) 25 20 75 25 31
——–
tPHL(C L R to Q) 40 20 200 40 41
——
tPLH(PRE to Q) 25 20 75 25 41
ts(set-up) 20 20 0 0 25
th(hold) 5 0 0 0 0
Tw(clock High) 30 20 200 20 25
Tw(clock Low) 37 25 200 47 25
Power (mW) 43 10 3.8 25 0.12

7.21 APPLICATIONS OF FLIP-FLOPS

The basic applications of flip-flops are
v Latch v Registers
v Frequency division v Counters
v Memory v Bounce elimination switch
v Glitch generators
 290 Digital Electronics: Principles and Applications

In this section, applications of flip-flop as registers, frequency division, counters, memory and bounce
elimination switch are explained.

7.21.1 Registers
Shift register is one type of sequential logic circuit. This circuit is most commonly used to store digital
data. Shift register can be constructed by a group of flip-flops. The output of one flip-flop is fed to the
next flip-flop as input. A common
clock drives all these flip-flops and
they are set or reset simultaneously.
Therefore, data process sequentially.
There are four basic types of shift
registers namely Serial In - Serial
Out, Serial In - Parallel Out, Parallel
In - Serial Out, and Parallel In -
Parallel Out.
In Serial In - Parallel Out Shift Fig. 7.82 4 bit register using flip-flop
Registers, data bits are entered
serially but the data bits are taken out of the register in parallel. Once the data are stored in the register,
each bit appears on its respective output line, and all bits are available simultaneously. A construction of
a four-bit serial in - parallel out register is shown below.
A 4 bit register using 7474 positive edge triggered flip -flop is shown in Fig.7.82. The bits to be
stored are applied at the D inputs, which are clocked in at the leading edge of the clock pulse. In this
register, the data to be entered must be available in parallel form. The detail operations of registers are
incorporated in next chapter.

7.21.2 Frequency Division

The flip-flop can also be used in frequency division. If a waveform is applied to the clock input of J-K
flip-flop, which operates in toggle mode, the frequency of output waveform is half of the input frequency
as shown in Fig. 7.83. Therefore, flip-flop is called as divide by 2 device.

Fig. 7.83 Flip-flop as divide by 2 device

7.21.3 Counters
Flip-flops are most commonly used for counting purpose. A 2-bit counter consists of two flip-flops as
shown in Fig. 7.84. The flip-flop used is 74107 J-K master slave flip-flops, which is used as T type. The
pulses to be counted are connected at the clock input of FF0. The Q0 output of FF0 is connected to the
 Flip-Flops 291

Fig. 7.84 2 bit binary up-counter

clock input FF1. The flip-flops are cleared by applying logic 0 at the clear input terminal momentarily.
For normal counting operation, it is to be maintained at logic 1. The pulses and the output waveforms
are depicted in Fig. 7.84.
The output Q0 of the least-significant stage changes at the negative edge of each pulse. The output Q1
changes at the negative edge of each Q0 pulse.
At any time, the decimal equivalent of the binary number Q1 Q0 is the number of pulses counted till
that time. For example, at the count is 01 decimal 1. The circuit resets after counting four pulses. The
different types of counters are discussed extensively in Chapter 8.

7.21.4 Memory
In digital systems, digital data stored and retrieved whenever
required. Flip-flop can be used to store data for any desired length
of time and then read out whenever required. In this memory, data
can be written into memory and data can also be read from memory.
A 1-bit read/write memory is shown in Fig.7.85. It has the three Fig. 7.85 One bit memory cell
terminal namely data inputs D, an Write/Read and an output Q.
In this one bit memory, D Flip Flop has Q Table 7.26 Modes of operation of one bit Memory cell
output that follows the D input when E ter-
minal is at logic 1. When the E input changes Inputs Mode
from logic 1 to logic 0, the Q output does not Write/Read D
change and it is retained though the D input ¥ ¥ Hold, Q=D
changes. Therefore, E enables the memory
1 0 Write 0 into memory, Q=0
cell for reading or writing operation. If E=
1 1 Write 1 into memory, Q=1
Write/Read is at logic 1 writing operation
can be performed. When Write/Read is at 0 ¥ Read , Q
logic 0, reading operation is done. The modes
of operation are given in Table 7.26. The detailed operations of memory are explained in Chapter 12.

7.21.5 Contact Bounce Elimination

Pushbutton type mechanical switches are usually used in digital instrument as input devices by which
digital information is entered into the system. For making a proper electrical contact, the switch open
and close several times within a few milliseconds. When the pushbutton switch is released, the discon-
 292 Digital Electronics: Principles and Applications

nection is not immediate. The switch opens and closes several times before final disconnection. So, it is
virtually impossible to obtain a clean voltage transition from +Vcc to 0V if a mechanical switch position
changes from 1 to 2. The reason for this is the phenomena of contact bounce as shown in Fig. 7.86. It is
clear from Fig. 7.86 that the movement of the switch from contact position 1 to 2 produces several out-
put voltage transitions as the switch bounces many times before coming to rest on contact 2. Generally,
the multiple output voltage transitions will stay on the output for few milliseconds. This type of output
voltage transition is not acceptable in many applications. Therefore, NAND or NOR latch can be used
to prevent the presence of switch bounce.

Fig. 7.86 Contact bounces Fig. 7.87 Contact bounces elimination using S-R latch

Figure 7.87 shows the contact bounce elimination using S-R latch. Initially, consider switch in position
1, S is low and the Q output is low. When switch position moved to position 2, S is high, R is low and the Q
output is high. If the connection with position 2 has been broken due to contact bounce, S is high, R is high.
In this condition, the output voltage Q will not be changed. The converse action takes place when the switch
is moved to position 1. In this way, bounce-elimination circuits can eliminate the contact bounce.

7.22 FLIP-FLOP ICS

Most commonly used flip-flop ICs are edge triggered D and J-K flip-
flops, which are available in market. T flip-flops are not available,
but J-K flip-flops can be converted into T flip-flops. An example
of D latch is the 7474 and its pin diagram is depicted in Fig. 7.88.
The pin description is given in Table 7.27. The 7474 is high-speed
Si-gate CMOS devices which are pin compatible with low power
Schottky TTL. The 7474 IC is dual positive-edge triggered, D-type
flip-flops with individual data (D) inputs, clock (CP) inputs, set
–
(SD) and reset (RD) inputs; also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate
independently of the clock input. Information on the data input is
transferred to the Q output on the LOW-to-HIGH transition of the
clock pulse. Figure 7.89 (a) and 7.89 (b) stand for the logic symbol
of individual flip-flops within IC and single block representation Fig. 7.88 Pin diagram of 7474
of IC respectively. Table 7.28 shows the functional table of 7474. duel positive edge triggered D
Figure 7.90 shows the timing diagram of D flip-flop. flip-flop
 Flip-Flops 293

Table 7.27 Pin description

Symbol Name and Function

— —
1R D, 2RD Asynchronous reset-direct input
1D, 2D Data inputs
1CP, 2CP Clock input(positive edge, Low
to High triggered)
– –
1SD, 2SD Asynchronous set-direct input
1Q, 2Q Flip-flop outputs
– –
1Q, 2Q Complement outputs
GND Ground
Vcc Positive suppy voltage

Table 7.28 Function table

Inputs Outputs
— — –
nSD nRD nCP nD nQ nQ
L H x x H L
H L x x L H
L L x x H H
H H L L H
(a) Individual logic symbol (b) Single block logic symbol
H H H H L
Fig. 7.89 Logic symbol of 7474 duel positive edge triggered
D flip-flop

74LS174 Hex D flip-flops with Clear 74LS174 IC is a positive-edge-triggered flip-flop

using TTL circuitry to implement D-type flip-flop logic. This device has six latches on a single chip with
direct clear input. Pin diagram of 74LS174 IC is shown in Fig. 7.91. Data at the D inputs is transferred
to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular
voltage level. While the clock input is at either the high or low level, the D input signal has no effect at
the output. Logic symbol of 74LS174 Hex D flip-flops with Clear input is given in Fig. 7.92.
 294 Digital Electronics: Principles and Applications

Fig. 7.90 Timing diagram of D flip-flop

Fig. 7.91 Pin diagram and logic symbol of

74LS174

74LS175 quad D flip-flops with

Clear
Figure 7.93 shows an example of a 74LS175 quad
flip-flop. This device consists of four flip-flops. The
logic symbol of 74LS175 IC is shown in Fig. 7.94.
This device has common clears, but no presets. Fig. 7.92 Logic symbol of 74LS174 Hex D flip-
flops with clear
 Flip-Flops 295

Fig. 7.93 Pin diagram of 74LS175 Fig. 7.95 Pin diagram of 74LS273

Table 7.29 Pin description of 74273

Pin Function
CP Clock pulse input
D 0 D7 Data inputs
——
MR Asynchronous master reset input
Q0 – Q7 Flip-flop outputs

IC 74LS273 The 74LS273 is a high-speed

8-bit register, consisting of eight D-type flip-flops
with a common clock and an asynchronous active
LOW master reset. Pin diagram is shown in Fig.
7.95 and logic symbol is depicted in Fig. 7.96. Table
Fig. 7.94 Logic symbol of 74LS175 IC 7.29 shows the pin description of 74LS273.
 296 Digital Electronics: Principles and Applications

Fig. 7.96 Logic symbol octal D flip-flop with buffer

74LS73A JK Flip-flops IC74LS73A is dual negative-edge-triggered master slave J-K flip-flops

with clear and complementary outputs. This device contains two independent negative-edge-triggered J-K
flip-flops with complementary outputs. The J and K data are processed by the flip-flops on the falling edge
of the clock pulse. The data on the J and K inputs is allowed to change when the clock is high to low. A
low logic level on the clear input will reset the outputs
regardless of the levels of the other inputs. Pin diagram
and logic symbol of IC74LS73A is shown in Fig.7.97
Table 7.30 shows the function table of IC74LS73A.

Table 7.30 Function table

Inputs Outputs
–
CLR CLK J K Q Q
L x x x L H
—
H L L Q0 Q0

H H L H L

H L H L H Fig. 7.97 Pin diagram and logic symbol of

IC74LS73A
H H H Toggle
—
H H x x Q0 Q0

74LS279 Quad S-R latches Figure 7.98

shows the quad S-R latches. The 74LS279 consists
of four individual and independent Set-Reset latches
with active low inputs. Two of the four latches have
an additional S input ANDed with the primary S input.
A low on any S input while the R input is high will be
stored in the latch and appear on the corresponding
Q output as a high. A low on the R input while the
S input is high will clear the Q output to a low. Si-
multaneous transition of the R and S inputs from low
to high will cause the Q output to be indeterminate. Fig. 7.98 Quad S-R Latches
 Flip-Flops 297

Table 7.31 shows the function table of S-R Latch where Q0= the level of Q before the indicated input
conditions were established.

Table 7.31 Function table of S-R Latches

Inputs Output
– –
S R Q
L L H
L H H
H L L
H H Q0

SUMMARY
In this chapter, the basic element of sequential circuits, flip-flops has been introduced as a basic memory element. This
device can be used to store 1 bit of digital information. There are four types of flip-flops, namely S-R, J-K, T type, and
D type. All four flip-flops have been explained in detail, including their design using logic gates. The triggering systems
of flip-flops have also been incorporated in this chapter. Flip-flops are converted from one type to others. Therefore,
conversions of flip-flops are also discussed here. Applications of flip-flops in registers, frequency division, counters,
memory elements, contact bounce elimination, etc. have been included in this chapter.

MULTIPLE CHOICE QUESTIONS

1. A flip-flop has two outputs which are
– – –
(a) Q=0, Q =0 (b) Q=1, Q =1 (c) Q=1, Q =0 (d) None of these
2. A flip-flop can be built by using
(a) NAND gates (b) AND gates (c) AND or OR gates (d) None of these
3. The invalid state of SR flip-flop is
(a) S=1, R=1 (b) S=0, R=0 (c) S=0, R=1 (d) S=1, R=0
4. IF a JK flip flop is in reset condition, its output will be
– – – –
(a) Q=0, Q =1 (b) Q=0, Q =0 (c) Q=1, Q =1 (d) Q=1, Q =0
5. When a T flip flop is set, its output will be
– – – –
(a) Q=0, Q =1 (b) Q=0, Q =0 (c) Q=1, Q =1 (d) Q=1, Q =0
6. A JK flip-flop can be built up using
(a) AND gates and clocked SR flip-flop (c) NOR gates
(b) OR gates and D flip-flop (d) None of these
7. JK flip-flop can be used as Toggle switch when
(a) J and K connected to ground
(b) J connected to ground and K connected to + VCC
(c) J and K connected to +VCC
(d) None of these
 298 Digital Electronics: Principles and Applications

8. In a clocked S-R flip, R is connected with S through an inverter, the circuit is called
(a) JK flip-flop (b) T flip-flop (c) D flip-flop (d) None of these
–
9. In a J-K flip-flop, if J=K=1 and clock is applied, the output Q will be
(a) 0 (b) No change (c) 1 (d) None of these
10. Race around condition occurs in JK flip-flop if
(a) J=1, K=1 (b) J=0, K=0 (c) J=0, K=1 (d) J=1, K=0
11. In a flip-flop with Preset and Clear terminals,
(a) Preset and clear operation perform separately
(b) In preset operation, clear is disabled
(c) In clear operation, preset is disabled
(d) None of these
12. Master salve is used to
(a) Improve its reliability (c) Eliminate race condition
(b) Reduce power dissipation (d) Increase its clock frequency
13. A transparent latch is a
(a) D flip-flop (b) T flip-flop (c) T or D flip-flop (d) T and D flip-flops
14. The initial output of JK flip-flop Q is 1. It changes to 0, when a clock pulse is applied. The input J
and K will be
(a) J=1, K=1 (b) J=0, K=0 (c) J=0, K=1 (d) J=1, K=0
15. The initial output of JK flip-flop Q is 0. It changes to 1, when a clock pulse is applied. The input J
and K will be
(a) J=1, K=1 (b) J=0, K=0 (c) J=0, K=1 (d) J=1, K=0
16. The initial output of SR flip-flop Q is 0. It changes to 1, when a clock pulse is applied. The input S
and R will be
(a) S=1, R=1 (b) S=0, R=0 (c) S=0, R=1 (d) S=1, R=0
17. The initial output of SR flip-flop Q is 1. It changes to 0, when a clock pulse is applied. The input S
and R will be
(a) S=1, R=1 (b) S=0, R=0 (c) S=0, R=1 (d) S=1, R=0
18. Flip-flops can be used as
(a) Latches (b) Registers (c) Counters (d) All of these
19. The digital memory element consists of
(a) Flip-flops (b) NAND gates (c) NOR gates (d) Shift registers
20. Flip-flops can be used to store
(a) One bit data (b) Two bit data (c) One byte data (d) Two byte data

REVIEW QUESTIONS
7.1 What will be the output of a NAND latch as shown in Fig. 7.13 for the following cases?
(a) S=0, R=1 (b) S=1, R=0;
7.2 Define flip-flop. Explain the principle of operation of SR flip-flop with truth table. Draw the output
waveform of SR flip-flop.
 Flip-Flops 299

7.3 Design a SR flip-flops using NOR gates and draw the output waveform. Why S=1 R=1 condition is
invalid in SR flip-flop?
7.4 What is a clocked flip-flop? Explain the principle of operation of clocked SR flip-flop with truth
table. Draw the output waveform.
7.5 Explain the function preset and clear inputs of SR flip-flop.
7.6 Explain the principle of operation of clocked maser slave SR flip-flop with output waveform.
7.7 Draw the circuit diagram of positive edge triggered D flip-flop. Explain its operation using truth
table and waveform. Why is it called as delay flip-flop?
7.8 Explain the principle of operation of clocked T flip-flop with truth table and output waveform. Why
it is called as toggle switch?
7.9 Write the truth table of JK flip-flop and explain the principle of operation of clocked JK flip-flop
with output waveform. What is race condition in flip-flop?
7.10 What will be the state of JK flip-flop in the following cases?
(a) J=1; K=1; Qn=0 (b) J=0; K=1; Clear low
7.11 Explain JK master slave flip-flop with output waveform.
7.12 What are the different forms of triggering in flip-flops? Explain any one with example.
7.13 Difference between level, negative edge tiggered and master slave flip-flop.
7.14 What is the conversion of one type of flip-flop to other type? Explain the following flip-flop conver-
sions
(a) SR to JK (b) JK to SR (c) JK to T (d) JK to D
7.15 Draw the output waveform of a clocked SR latch, when the inputs are as shown in Fig. 7.99.

Fig. 7.99

7.16 What is edge triggering and level triggering? Explain edge triggering SR flip-flop with wave-
forms.
7.17 Draw the output waveform of a clocked D latch, when the inputs are as given in Fig. 7.100

Fig. 7.100

7.18 Draw the output waveform of a clocked T latch, when the inputs are as given in Fig .7.101
 300 Digital Electronics: Principles and Applications

Fig. 7.101

7.19 Draw the output waveform of a clocked J K latch, when the inputs are as depicted in Fig. 7.102.

Fig. 7.102

7.20 Show the output for the changes of input

(a) S=1, R=0 to S=R=0 , and
(b) S=0, R=1 to S=R=0
7.21 Write the truth table of flip-flop as shown in Fig. 7.103. Sketch the waveforms of input clock and
output when J=1010 1100 and K=0110 0101.

Fig. 7.103

7.22 If the waveforms as shown in Fig. 7.102 is applied to the JK master slave flip-flop as given in Fig.
7.104, draw the output waveform.

Fig. 7.104

7.23 Define D and T flip-flop. Write the truth table and draw waveform. Design the D and T flip-flop
using JK flip flop.
 Flip-Flops 301

7.24 Carry out the following conversions

i) SR to D, ii) JK to D, iii) D to JK, iv) SR to T,
v) JK to T, vi) T to JK, vii) T to D, viii) D to SR,
ix) D to T, x) T to SR, xi) JK to SR
7.25 Proof that the circuit as shown in Fig. 7.105(a) and (b) behave as a toggle switch.

Fig. 7.105 (a) and (b)

7.26 Draw the output of flip-flop FF0 and FF1 with respect to clock signal. Assume all Flip-flops are ini-
tially reset. What is the condition for proper operation of the circuit as shown in Fig. 7.106?. How
we remove race around condition of data transfer using negative edge triggered D flip-flops.

Fig. 7.106

7.27 Draw the output of Q0 and Q1 of flip-flop, FF0 and FF1 when the clock signal is applied as per
Fig.7.107. Assume all flip-flops are initially reset.

Fig. 7.107
 CHAPTER

8
SEQUENTIAL CIRCUITS
8.1 INTRODUCTION
A sequential circuit consists of memory elements, such as flip-flops and combinational logic circuits.
Figure 8.1 shows the basic block diagram of a sequential circuit. The sequential circuit is a feedback
system as the present state of
the circuit is fed back to the
input decoder and is used to
determine the next state of the
machine. The next state of the
machine can be determined by
the present state of the circuit
and inputs. The input decoder
performs the logic operations
based on the present state of the
circuit and inputs and generates
Fig. 8.1 Basic block diagram of sequential circuit
next state code of the circuit.
Then the next state code is stored in the memory. In sequential circuit, the output depends on the im-
mediate input to the circuit and also the present state of the circuit. The present state of the circuit is also
stored in the memory element.
There are two types of sequential circuits, such as synchronous sequential circuit and asynchronous
sequential circuit. In synchronous sequential circuit, state changes are synchronised to the periodic
clock pulses but state changes of asynchronous sequential circuit are not synchronised with clock signal.
Most commonly used sequential circuits are registers and counters. In this chapter, operating principles
and applications of registers and counters are discussed in detail.
8.2 REGISTER
Registers are digital circuits which are used to store ‘n’ bits information in the same time and each bit
is stored in a flip-flop. Generally, registers are building with D flip-flops. Registers can also be designed
using S-R and J-K flip-flops and presently, they are available in MSI ICs. In a register, data can be entered
in serial form and data can also be output in serial form. Then this register is called as shift-register since
data bits are shifted in the flip-flops with each clock pulse. Data can be shifted either in right direction
or left direction or bi-directional. When the data is shifted from left to right, it is known as right shift
register. If data is shifted right to left, it is called as left shift register. In bi-directional shift register, data
can be shifted either left to right or right to left, depending upon the mode control signal.
 Sequential Circuits 303

8.3 SHIFT REGISTER

Shift register is an example of sequential logic circuit. This logic circuit is most commonly used to store
digital data during arithmetic and logical operations. Shift register can be constructed by a group of flip-
flops. Each flip-flop can store one bit, so a register composed of ‘n’ flip-flops can store a ‘n’ bit number. The
output of one flip-flop is fed to the next flip-flop as input.
All these flip-flops are driven by a common clock and they
are set or reset simultaneously. Therefore, the data process
sequentially. The storing of one bit data using D flip-flop is
shown in Fig. 8.2. It is depicted in Fig. 8.2(a) that data in-
put D is 1 and clock is applied. Then input data ‘1’ is stored
in flip-flop as output of D flip-flop is 1. If input is removed, Fig. 8.2 D flip-flop as one bit storage
output will be remaining same. Similarly, ‘0’ can be stored element
in D flip-flop as shown in Fig. 8.2(b). In this chapter, the operation of different types of shift-registers and
their applications have been discussed. The operation of bi-directional type shift register is also explained.

8.4 CLASSIFICATION OF SHIFT REGISTER

There are four basic types of shift registers, namely Serial In - Serial Out (SISO), Serial In - Parallel Out
(SIPO), Parallel In - Serial Out (PISO), and Parallel In - Parallel Out (PIPO). In this chapter, all four
types shift registers are explained briefly.
8.4.1 Serial In-Parallel Out (SIPO) Shift
Registers
In Serial In – Parallel Out (SIPO), data is applied at the input of
register in serial form and the output can be obtained in parallel
form after the completely shifting of data in register.Figure 8.3
Fig. 8.3 Serial data input and par-
shows the serial input data, and then parallel output. allel data output in SIPO
shift register
8.4.2 Serial In-Serial Out (SISO) Shift
Registers
In Serial In – Serial Out shift register, data input is in serial form and clock pulses are applied to each
flip-flop. After each clock pulse, data moves
by one position. The output can be obtained
in serial form. In this type of shift register,
data moves either in left or right direction. Fig. 8.4 Serial data input and serial data output in
It is depicted in Fig. 8.4 that data inputs in SISO shift register
the shift register are serially 1001 and data
output from shift register is also serially.
8.4.3 Parallel In-Serial Out (PISO)
Shift Registers
In Parallel In – Serial Out shift register, data is loaded into Fig. 8.5 Parallel data input and serial
shift register in parallel form and the data output obtained data output in PISO shift
will be serial form as illustrated in Fig. 8.5. register
 304 Digital Electronics: Principles and Applications

8.4.4 Parallel In-Parallel Out (PIPO) Shift

Registers
In Parallel In – Parallel out shift register, data is loaded in parallel form
and the data output will be in parallel. In Fig. 8.6, data input is in parallel
form but data output from shift register is also in parallel form.
8.5 UNIDIRECTIONAL SHIFT REGISTERS
The shift registers generally perform data shifting operation from left to
Fig. 8.6 Parallel data input right. In unidirectional shift register, data can be shifted in left or right
and parallel data output in
PIPO shift register direction. When the data movement is in left direction, the register is
called as left shift register. If the data movement is in right direction, the
register is called as right shift register.

8.5.1 Left Shift Registers

The left shift register is shown in Fig. 8.7(a)
and (b). In this shift register, data is entered
in serial form and data output is also in
serial form and data moves right to left. If
the serial data input is 1001, after fourth
clock pulse, 1001 data will be loaded into
a 4-bit shift register. After fifth clock pulse,
MSB ‘1’ will be output as serial data output
Fig. 8.7 (a) and (b) 4 bit left shift register terminal. Just after sixth clock pulse, the
next bit ‘0’ will be the output. Similarly, on
the seventh clock pulse, the next bit ‘0’ will
be out. After eight clock pulse, last bit ‘1’
will be the output.

8.5.2 Right Shift Registers

The right shift register is shown in Fig. 8.8 (a)
and (b). In right shift register, data is entered in
serial form and data output is also in serial form.
Data moves left to right. Its operation is similar
with left shift register but only difference is the
Fig. 8.8 (a) and (b) 4 bit right shift register
direction of data movement. After four clock
pulses, four bit data will be loaded completely into shift register. From fifth to eighth clock pulse, data will be
output serially at output terminal.

8.6 BI-DIRECTIONAL SHIFT REGISTERS

Sometimes, the same shift register can be used as left shift or right shift with some additional circuits. We
can multiply a binary number by 2, just simply placing the binary number in a shift register and shifting the
number by one bit to the left. Only care has to be taken that a ‘1’ is not shifted out of the most significant
stage of the register. Similarly, a binary number can be divided by ‘2’ when we simply shift the number to the
right by one stage or one bit. The operation of bi-directional shift register can be explained using Fig. 8.9.
 Sequential Circuits 305

The bi-directional shift regis-

ter is one in which the data can
be shifted either left or right. A
three bit bi-directional shift reg-
ister using D flip-flops is shown
in Fig. 8.9. Here a set of NAND
gates are used to select data in-
puts from the right or left adja-
cent flip-flops, as selected by the
—— —
LEFT/RIGHT control line. The
serial left shift and right shift
operation of register can be per- Fig. 8.9 Bi-directional shift register
—— — —— —
formed by using LEFT/RIGHT control signal. When the mode control signal LEFT/RIGHT=1, the data will
———
be shifted to the right when clock pulses are applied. In the mode control signal LEFT/RIGHT=0, the input
———
data will be shifted to the left when clock pulses are applied. The mode control signal LEFT/RIGHT should
be changed only when CLK = 0, otherwise the data stored in the shift register may be changed.

8.7 SERIAL IN-PARALLEL OUT (SIPO) SHIFT REGISTERS

8.7.1 4 bit SIPO Shift Register using D flip-flop
In SIPO shift register, data bits are entered
in shift register serially and the data bits are
taken out of the register in parallel. When the
data are stored in shift register, each bit ap-
pears on its respective output line. Therefore,
all output bits are available simultaneously.
The construction of a four-bit Serial In - Par-
allel Out shift register is shown in Fig. 8.10.
Figure 8.10 is a 4-bit shift register using D
flip-flops. The serial data is fed to the input Fig. 8.10 Four bit serial in - parallel out shift register
D of flip-flop, FF0 and output is obtained in
parallel form at the output of flip-flops, FF0, FF1, FF2 and FF3. In this shift register, positive edge triggered
flip-flops are used. So the data are transferred on the
positive edge of the clock pulse. The clear signal is applied
to all four flip-flops. The waveform of 4 bit serial input
parallel output shift register is shown in Fig. 8.11. The truth
table of this shift register is also depicted in Table 8.1.
Table 8.1 Truth table of 4 bit SIPO shift register
Clear Input before Clock Output
pulse Q 0 Q1 Q2 Q3
clock pulse
L x 0 0 0 0 0
H 1 1 1 0 0 0
H 0 2 0 1 0 0
H 0 3 0 0 1 0 Fig. 8.11 Waveform of 4-bit serial input
H 1 4 1 0 0 1 and parallel output shift register
 306 Digital Electronics: Principles and Applications

Table 8.1 gives details of the operation of SIPO shift

register. At the start clear input is low, and all flip-flops
will be reset. So the output of all flip-flops is low and
Q0 = 0, Q1 = 0, Q2 = 0, and Q3= 0. The serial input data
is marked as x. It means that the input has no effect
on output. Before applying the next clock pulses, clear
input terminal is high and data input is in serial form.
Data ‘1’ has been applied to the FF0 of shift register;
Fig. 8.12 Logic symbol of 4-bit shift register input data ‘1’ has to be transferred to the output of FF0
on positive edge of clock pulse. Therefore, after the first
clock pulse Q0 is 1 and other outputs are low means Q1 = 0, Q2 = 0, and Q3= 0. Now, input of FF0 is 0 and
input of FF1 is Q0 =1. When the next positive edge clock pulse occurs, the output of flip-flop FF0 has been
transferred to next flip-flop FF1 and the output of flip-flop FF1 has been transferred to next flip-flop FF2.
As input to the Flip flop FF0 is low, output of FF0 will be 0. Similarly, output of FF1 is Q1= 1. Therefore,
after application of second clock pulse, the output of flip-flops are Q0 = 0, Q1 = 1, Q2 = 0, and Q3= 0.
Before applying the third clock pulse, input of FF0 is 0, but inputs of FF1 and FF2 are Q0=0, and Q1=1
respectively. When the third clock pulse applied, data is shifted from FF0 to FF1, FF1 to FF2 and the output
of flip-flops are Q0 = 0, Q1 = 0, Q2 = 1, Q3= 0. When the last bit ‘1’ is applied to the data input and the fourth
clock pulse is applied, the ‘1’ is entered into FF0 and stored in this flip-flop. But data is shifted from FF0
to FF1, FF1 to FF2 and FF2 to FF3. After four-clock pulse, the output of flip-flops are Q0 = 1, Q1 = 0, Q2 =
0, Q3 = 1. Consequently, the digital output will be 1001 and this output data are in parallel form. Timing
diagram of 4 bit SIPO shift register is shown in Fig. 8.11 and it’s logic symbol is given in Fig. 8.12.
8.7.2 SIPO Shift Register using J-K flip-flop
Figure 8.13 shows the serial input parallel output shift register using J-K flip-flops. The serial input data is con-
nected to the J input of flip-flop FF0 and its complement to the K input. The normal and complement outputs
of each flip-flop are connected to the J and K inputs of the next flip-flop respectively. The clear inputs of all the
flip-flops are commonly connected. When clear input is low, all the flip-flops will be reset. The clock inputs of
all the flip-flops are also
connected to a common
line, so that clock pulse
can be applied to all flip-
flops simultaneously in
the register and all the
flip-flops are toggled si-
multaneously. This shift
register is also operates
according to Table 8.1
and its wave form will
be same as Fig. 8.11. Fig. 8.13 Four bit serial in – parallel out shift register using JK flip-flops

Example 8.1 Draw the waveform of 4-bit SIPO register, when input data is 1010.
� Solution
The logic symbol of 4-bit SIPO shift register is shown in Fig. 8.14(a). Here serial data input is 1010. Initial
data input is ‘1’, when clock pulse is applied, data ‘1’ is stored in Q0 and other flip-flops are in reset condition.
 Sequential Circuits 307

During second clock pulse, input data is ‘0’. Just after application of second clock pulse, Q0 becomes ‘0’ and
previous state of Q0 is shifted to Q1. At this instant Q1=1, and Q2=Q3=0. At the instant of third clock pulse,
input data is 1, so after third clock pulse Q0=1, Q1=0 and Q2=1. Then at fourth clock pulse, input data is 0,
output will be Q0=0, Q1=1, Q2=0 and Q3=1. As it is a four bit register, after the four clock pulse, data input

Fig. 8.14(a) Logic symbol of 4- bit SIPO

shift register Fig. 8.14(b) Waveform of 4 bit SIPO register

operation will be completed and data will be available at output terminals. The register output after four clock
pulses is 1010 as shown in Fig. 8.14(b).
8.8 SERIAL IN-SERIAL OUT SHIFT REGISTERS
A basic four-bit serial in –se-
rial out shift register can be con-
structed using four D flip-flops,
as shown in Fig. 8.15. The oper-
ation of the circuit is as follows.
In this shift register, data inputs
serially means one bit at a time
on a single line and data outs in Fig. 8.15 Four bit serial in – serial out shift register using
serial form. When clear input is D flip-flops
low, the register is first cleared
and the output of all four flip-flops will be zero. After that clear
input is in high state and the input data is applied sequentially to
the D input of the first flip-flop (FF0). As soon as clock pulse is
applied, input data has to be transferred to the output of FF0 on
positive edge of clock pulse. If the clock pulse is applied sequen-
tially, one bit is transmitted from left to right on each clock pulse. Fig. 8.16 Data inputs and
Therefore, data is shifted from FF0 to FF1, FF1 to FF2 and FF2 to clock waveform of shift register
FF3 respectively. If a data word to be 1101, after four-clock pulse the least significant bit of the data has
to be shifted through the register from FF0 to FF3 and 1101 data will be stored in register. Accordingly,
the data input operation completes. Timing diagram of shift register output is given in Fig. 8.16.
In order to get the data out of the register, data must be shifted serially and taken out from FF3.
After fourth clock pulse, the least significant bit of the data appears on FF3. When the next clock pulse
is applied, the second bit data comes out on FF3. Similarly, the third bit and fourth bit appear on FF3
sequentially after applying corresponding clock pulses. While the original four bit are being shifted
completely, a new four bit number can be entered in the shift register.
 308 Digital Electronics: Principles and Applications

The data out of shift register can be done

destructively or non-destructively. In destruc-
tive readout, the original data is lost and at the
end of the read cycle, all flip-flops are reset to
zero. To avoid the loss of data, an arrangement
for a non-destructive reading can be possible
Fig. 8.17 Non-destructive reading of SISO shift register by adding two AND gates, an OR gate and an
inverter to the shift register. The construction
of this circuit is shown in
Fig. 8.17 When the R/W
control line is high; the
data is loaded to the shift
register. If the R/W con-
trol line is low, the data
Fig. 8.18 Four bit Serial In – Serial Out shift register using JK flip-flops can be shifted out of the
register. The implementa-
tion of SISO shift register using JK flip-flops is shown in Fig. 8.18.

Example 8.2 Draw the waveform of 4- bit register as shown in Fig. 8.19 for four clock pulses, when
input data is 1001. Assume that initially the register content is 0000.

� Solution

Fig. 8.19 Four bit serial in – serial out shift register using D flip-flops
As initially the register content is 0000, Q0=Q1=
Q2= Q3= 0. During first clock pulse, data input is
1. Consequently, after first clock pulse, data ‘1’
is stored in Q0 and other flip-flops are in reset
conditions. At the instant of second clock pulse,
data is 0. Just after application of second clock
pulse, Q0 becomes 0 and Q1=1 as Q0 is shifted to
Q1. Similarly after third clock pulse, Q0=0, Q1=0
and Q2=1. At fourth clock pulse, data is 1, then
output will be Q0=1, Q1=0, Q2=0 and Q3=1. As a
result, after application of four clock pulses, ‘1’
will be output at output data terminal Q3 of shift
Fig. 8.20 Four bit serial in–serial out shift register. Figure 8.20 shows the waveform of 4 -
register using D flip-flops bit register for four clock pulses.
 Sequential Circuits 309

8.9 PARALLEL IN-PARALLEL OUT SHIFT REGISTERS

In Parallel In - Parallel Out shift registers,
all data bits are entered simultaneously
on the parallel input lines rather than on a
bit by bit basis on serial data inputs. After
simultaneously entry of all data bits, the
data bits are available on the output lines
immediately. Figure 8.21 shows a four-
bit Parallel In - Parallel Out shift register
constructed by D flip-flops. The D0, D1,
D2, D3 are the parallel inputs and the Q0,
Q1, Q2, Q3 are the parallel outputs. When
Fig. 8.21 Parallel In – Parallel Out shift register
a common clock is applied to all flip-
flops of this register, all the data at the D
inputs D0, D1, D2, D3 should appear at the corresponding Q outputs simultaneously.

8.10 PARALLEL IN-SERIAL OUT SHIFT REGISTERS

A four-bit Parallel In-Serial Out shift register is shown in Fig. 8.22. The circuit uses D flip-flops and
logic gates for enter-
ing/loading data to
the register. D0, D1,
D2 and D3 are the four
parallel input lines,
where D0 is the most
significant bit and D3
is the least signifi-
cant bit. The SHIFT/
———
LOAD input used for
entering four bits of
data into the regis-
ter. When the mode
control line, SHIFT/
———
Fig. 8.22 Logic diagram of four bit Parallel In – Serial Out shift register
LOAD is LOW, the
data is applied to the
D input of respective
flip-flops. After application of a clock pulse, the flip-flop
will be set if its D input is 1 and the flip-flop will be reset
if its D input is 0. Therefore, all four bits will be stored
simultaneously in the register. When the mode control line
is HIGH or SHIFT is active high and a clock pulse is ap-
plied, the data can be shifted right from one flip-flop to the
Fig. 8.23 Logic symbol of 4-bit Parallel next flip-flop. Figure 8.23 shows the logic symbol of four
In –Serial Out shift register bit parallel in serial out shift register.
 310 Digital Electronics: Principles and Applications

Figure. 8.24 shows the waveform of four bit

Parallel In - Serial Out shift register. If the data
input D0=1, D1=1, D2=0, D3=0; after application
of first clock pulse the parallel data 1100 are
loaded into the register and data output Q3 is 0.
When the second clock pulse is applied, data
shifted right means Q0 shifted to Q1, Q1 shifted
to Q2, and Q2 shifted to Q3. On the application Fig. 8.24 Waveform of PISO shift register
of third clock pulse Q1 data appears on Q3 and
on the fourth clock pulse, Q0 data appears on Q3. Therefore, all four bits will be shifted out sequentially.

Example 8.3 Draw the timing diagram of data output of a four bit shift register with parallel input
data 1011.
� Solution
———
When SHIFT/LOAD is low and clock pulse is applied, the parallel data 1011 are loaded into register. The
output at Q3 is 1. On the second clock pulse, the data ‘1’ at Q2 is shifted into Q3. At third clock pulse, the ‘0’
is shifted into Q3. When the fourth clock pulse is applied, the output at Q3 is 1. Figure 8.25 (b) shows the
timing diagram of PISO shift register.

Fig. 8.25 (a) Block diagram of PISO shift register and (b) Timing diagram of PISO shift register

8.11 BUFFER REGISTER

Generally, these registers are known as Tri-state Buffer Registers. In microprocessor system, the data
transfer with in the system takes place over a common set of interconnecting lines which is known
as data bus. As different devices may be connected to the single data bus, those devices need to be
connected through tri-state buffers. Therefore, bus organisation systems of microprocessor require a
tri-state buffers which operate on tri-state logic such as low, high and high impedance state or high-Z-
state. IC 74374 is an 8 bit tri-state buffer register which consists of D flip-flops and tri-state gates. Figure
8.26 shows the logic diagram of 8 bit buffer register IC 74374. The pin diagram representation of IC
74374 is also shown in Fig. 8.26. The data inputs are 1D, 2D… 8D and data outputs are 1Q 2Q …8Q.
Buffer register operates just like a PIPO register. When data inputs are given to D flip-flops and clock is
applied, input data will be loaded to flip-flops and available at output of the flip-flops but not available
 Sequential Circuits 311

Fig. 8.26 Pin diagram and logic diagram of 8 bit tri-state

buffer register IC 74374

at output bus as output bus is in high-Z state. Whenever the output is required, output enable (OE) signal
makes low and the flip-flops output available at the output terminals.

8.12 UNIVERSAL SHIFT REGISTER

The 4-bit universal shift registers features are parallel and serial inputs, parallel outputs, mode control,
and two clock inputs. These registers operate in
different modes, namely serial inputs, parallel
load, shift right, and shift left. Pin diagram and
logic symbol of 4-bit universal shift register
IC 7495A are depicted in Fig. 8.27(a) and (b)
respectively. Logic diagram of IC 7495A is
illustrated in Fig. 8.28. The mode control signal
controls the serial and parallel inputs.
Applying the four bits of data and taking
the mode control input high, we can achieve
Fig. 8.27 Pin diagram and logic symbol of 7495A parallel loading. Then the data is loaded into
 312 Digital Electronics: Principles and Applications

Fig. 8.28 Logic diagram of 7495A

the associated flip-flops and appears at the outputs after the high to low transition of the clock-2 input.
During parallel loading, the entry of serial data is inhibited. When mode control is low, data is serially
entered into shift register. Shift right takes place on the high to low transition of clock-1 when the mode
control is low; shift left takes place on the high to low transition of clock-2 when the mode control
is high by connecting the output of each flip-flop to the parallel input of the previous flip-flop. The
functional table of 7495A is given in Table 8.2.
Table 8.2 Functional Table of 7495A
Inputs Outputs
Clocks Parallel
Mode control Serial QA QB QC QD
2(L) 1(R ) A B C D
H H x x x x x x QA0 QB0 QC0 QD0
H ↓ x x a b c d a b c d
H ↓ x x QB↑ QC↑ QD↑ d QBn QCn QDn d
L L H x x x x x QA0 QB0 QC0 QD0
L X ↓ H x x x x H QAn QCn QCn
L X ↓ L x x x x L QAn QCn QCn
↑ L L x x x x x QA0 QB0 QC0 QD0
↓ L L x x x x x QA0 QB0 QC0 QD0
↓ L H x x x x x QA0 QB0 QC0 QD0
↑ H L x x x x x QA0 QB0 QC0 QD0
↑ H H x x x x x QA0 QB0 QC0 QD0
↑ shifting left requires external connection of QB to A, QC to B and QD to C. Serial data is entered at
input D.
H = High level, L =Low level, x = irrelevant
↓ = transition from high to low level, ↑ = transition from low to high level
a,b,c,d = the level of steady state input at inputs A, B, C, or D, respectively.
QA0, QB0, QC0, QD0 = the level of QA, QB, QC or QD respectively, before the indicated steady state input
conditions were established.QAn, QBn, QCn, QDn = the level of QA, QB, QC or QD respectively, before the
most recent transition of the clock.
 Sequential Circuits 313

The IC 74194 is a 4-bit bi-directional universal

shift register and it has shift-left and shift-right
capability, synchronous parallel and serial data transfer,
asynchronous master reset and can easily expand for
both serial and parallel operation. Pin diagram and logic
symbol of IC 74194 are depicted in Fig.8.29 (a) and (b)
respectively. The functional characteristics are indicated
in the logic diagram as shown in Fig.8.30 and function
table as illustrated in Table 8.3. The registers are fully
synchronous. The synchronous operation of the IC is
determined by the mode select inputs (S0, S1). It is clear
from the mode select table that data can be entered and
shifted from left to right (Q0 → Q1→ Q2, etc.) or, right to
Fig. 8.29 Pin diagram and logic symbol of left (Q3→ Q2→ Q1, etc.) or parallel data can be entered,
74194 loading all 4 bits of the register simultaneously.

When both S0 and S1 are LOW,

existing data is retained in a hold
mode. The first and last stages
provide D-type serial data in-
puts (DSR, DSL) to allow multi-
stage shift right or shift left data
transfers without interfering with
parallel load operation. Mode se-
lect and data inputs are edge-trig-
gered and operate in the LOW-
to-HIGH transition of the clock
pulse. The four bit parallel data
inputs D0 to D3 are D-type inputs.
When S0 and S1 are high, data D0
to D3 will be transferred to the Q0 Fig. 8.30 Logic diagram of 74194
to Q3 outputs respectively after the transition of the clock from LOW-to-HIGH. Figure 8.31 shows the
timing sequences of clear, clear-load, shift-right, shift-left, inhibit and clear operation of 74194.
Table 8.3 Functional table of IC 74194
Operating Modes Inputs Outputs
—R
CP M – S1 S0 DSR DSL Dn Q0 Q1 Q2 Q3
Reset x L x x x x x L L L L
Hold x H l l x x x q0 q1 q2 q3
Shift left ↑ H h l x l x q1 q2 q3 L
↑ H h l x h x q1 q2 q3 H
Shift right ↑ H l h l x x L q0 q1 q2
↑ H l h h x x H q0 q1 q2
Parallel load ↑ H h h x x dn d0 d1 d2 d3
 314 Digital Electronics: Principles and Applications

H = High voltage level, h = High voltage level one set-up time prior to the low to high CP transition
L = low voltage level, l = Low voltage level one set-up time prior to the low to high CP transition
q, d = lower case letters indicate the state of the referenced input one set-up time prior to the low to
high CP transition
x=don’t care , ↑ = Low to high clock pulse transition

Fig. 8.31 Timing sequences of clear, clear-load, shift-right, shift-left, inhibit and clear of 74194

8.13 UNIVERSAL SHIFT REGISTER USING MUX

A universal shift register using
multiplexer is shown in Fig. 8.32. It
has the capability of shift left, shift
right, load and hold. It consists of D
flip-flops and 4:1 multiplexers. The
multiplexer is used to select mode
of operation such as hold, shift left,
shift right and load. The multiplexer
has two common selection variables
S0 and S1. When S1=0 and S0=0, hold
is selected. L is selected when S1=0
and S0=1, R is selected when S1=1
and S0=0. The Load operation is
performed when S1=1 and S0=1. The
mode of operation of the universal
register with respect to mode inputs
is given in Table 8.4. Fig. 8.32 Two bit universal shift register using 4:1MUX
 Sequential Circuits 315

Table 8.4 Actually, the mode select inputs S1 and S0 select shift
Activity Mode Clock Mux gate left, shift right, and load with enabling multiplexer gates
S1 S0 L, R, and Load respectively. This register has tri-state
Hold 0 0 ↑ Hold outputs. The tri-state buffers must be disabled by S1=1
Shift left 0 1 ↑ L S0=1 to float the I/O bus for use as inputs. A bus is a
Shift right 1 0 ↑ R collection of similar signals. The inputs are applied to A,
Load 1 1 ↑ Load and B through pins QA and QB, and routed to the Load
gate in the multiplexers, and on the D inputs of
the FFs. Data is parallel load on application of a
clock pulse.
When S1=0 S0=0, the hold gate enables a path
from the Q output of the flip-flop back to the hold
gate, to the D input of the same flip-flop. As a
result, the output is continuously re-loaded with
each new clock pulse when S1=0, S0=0. In this
Fig. 8.33 Logical symbol of IC 7491 8 bit shift way, data is hold.
register
To read data from outputs QA and QB, the tri-
state buffers must be enabled by O—E2
— = 0, O—E1
— =0
Table 8.5 and mode S1 S0 = 00, or S1 S0 = 01, or S1 S0 = 10. So that mode
S1
—— ——
S0 OE2 OE1 Tristate gate is anything except load for data output as shown in Table 8.5.
x x x 1 Disable For right shifting operation of data, shift right (SR) input
x x 1 x Disable signal is used. Any data shifted out to the right from stage QA
0 0 0 0 Enable to QB via QA and QB. This output is unaffected by the tri-state
0 1 0 0 Enable
1 0 0 0 Enable buffers. The shift right sequence for S1 S0 = 10 is:
1 1 x x Disable SR → QA → QB
Similarly, the left shift operation of data is possible with
shift left (SL) input signal. Any data shifted out to the left from stage QB to QA via QB and QA. This is
also unaffected by the tri-state buffers. The shift left sequence for S1 S0 = 01 is:
SL → QB → QA
Shifting of data may take place with the tri-state buffers disabled by one of O —E2
— or O —E1
—. During
shifting operation, the register contents outputs will not be accessible. The IC 74ALS299 is universal
shift register with tri-state outputs which is commonly used in digital systems.

8.14 APPLICATIONS OF SHIFT REGISTERS

Shift registers can be found in many applications. The list of shift register applications are as follows:
 Timing circuits to produce time delay,
 Shift register counters: Ring counter and Johnson counter,
 Serial to parallel converters,
 Parallel to serial converters,
 Sequence generators
 316 Digital Electronics: Principles and Applications

In this section, time delay generation, Ring counter, Johnson counter and Serial to parallel converters
are explained.

8.14.1 Time Delay

The Serial In-Serial Out shift register can be used to produce time delay as shown in Fig. 8.33. The
number of stages in the register and the clock frequency can control the amount of time delay.
If a data ‘1’ is applied to A and B terminals of eight bit register IC 7491 for clock pulse duration,
it appears on the output of first stage after
applying triggering pulse. Then this data
can be shifted from one stage to other on the
each positive edge triggering of clock pulse.
Therefore, after the eighth clock pulse, data
will appears on output as depicted in Fig. Fig. 8.34 Waveform of shift registers as time delay
8.34. If the clock frequency is 1 KHz, one
cycle time is 1ms. Consequently, 8ms time delay can be generated by this circuit.

8.14.2 Shift Register Counters

Two of the most common types of shift register counters are introduced here: the Ring counter and the
Johnson counter. They are basically shift registers with the serial outputs connected back to the serial
inputs in order to produce particular sequences. These registers are classified as counters because they
exhibit a specified sequence of states.
Ring Counters A Ring counter is a circulating shift register in which the output of the most sig-
nificant stage is fed back to the input
of the least significant stage. The 4-bit
ring counter can be constructed using
D flip-flops as shown in Fig. 8.35. The
sequence table of ring counter is given
in Table 8.6. It is clear from this table
that the output of each stage is shifted
into the next stage on the positive
Fig. 8.35 Ring counter
edge of a clock pulse. Initially, FF0 is
set and all other flip-flops, FF1, FF2 and FF3, are reset. Therefore, Q0 is 1 and Q1, Q2, and Q3 are 0. After
application of clock pulse, output Q0 will be shifted to Q1 and Q1 will
Table 8.6 Counting sequence of
4-bit Ring counter be 1. Similarly, just after the clock pulse-2, output Q2 will be 1 and
Q3 will be 1 after third clock
Clock Q0 Q1 Q2 Q3 pulse. The waveform of four
0 1 0 0 0
bit Ring counter is shown in
1 0 1 0 0
2 0 0 1 0 Fig. 8.36.
3 0 0 0 1 As the count sequence has
4 different states, the counter
can be considered as a mod-4 counter. The Ring counter utilizes Fig. 8.36 Timing diagram of ring
counter
only four of the maximum sixteen states; therefore, Ring counters
 Sequential Circuits 317

are very inefficient in terms of state usage. But the most advantage of a Ring counter over a binary
counter is that it is self-decoding.
Johnson Counters In a Johnson counter, inverted output of the last stage flop-flop is fed back
to the input of the first stage flip-flop. Then a unique sequence is
Table 8.7 Counting sequence of
4-bit Johnson counter
generated due to feedback. Table 8.7 shows the sequence table
of four bit Johnson counter. A four bit Johnson counter has eight
Clock Q0 Q1 Q2 Q3
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1
Fig. 8.37 Four bit Johnson counter
counting sequence and five bit Johnson counter
has ten counting sequence. Therefore ‘n’ bit/stage
Johnson counter should have a count sequence of
length ‘2n’ and it may be called as mod-2n coun-
ter. These counters are also known as twisted ring
counters. Figure 8.37 shows the circuit diagram of
a four bit Johnson counter. The timing diagram of
four bit Johnson counter is depicted in Fig. 8.38 Fig. 8.38 Waveform of four bit Johnson counter
The disadvantage of this counter is that the maximum available states are not fully utilized and only eight
states out of the sixteen states are being used.
8.14.3 Serial Data to Parallel Data Conversion
Serial data transmission is commonly used to transmit data one digital system to other through single line.
If parallel data transmission is used, eight lines are required for this. The microprocessor or computer-
based systems require parallel data. When these systems communicate with external devices, then these
devices send or receive serial data. Therefore, the commonly required incoming data to be converted
into parallel format. Therefore, serial-to-parallel conversion is required. A Serial In - Parallel Out shift
register can be used in serial-to-parallel conversion.
Example 8.4 Draw the logic circuit and waveform of 5 bit Ring counter

� Solution
The logic circuit diagram
of 5 bit ring counter is
shown in Fig. 8.39 and its
timing diagram is depicted
in Fig. 8.40. Initially, first
D flip-flop FF0 is reset
and rest of the flip-flops
are cleared. So Q0 is 1
Fig. 8.39 Five bit Ring counter and Q1=Q2=Q3=Q4=0 after
 318 Digital Electronics: Principles and Applications

the first clock pulse. When the second clock pulse is

applied, Q1 becomes 1 and outputs of other flip-flops
are 0. On the application of third clock pulse, Q2 is
1 and Q0=Q1=Q3=Q4=0. Similarly, Q3=1 when fourth
clock pulse is applied and Q0=Q1=Q2=Q4=0. So that
we can verify that ‘1’ is always retained in the counter
but simply shifting around the ring after application Fig. 8.40 Timing diagram five-bit Ring counter
of each clock pulse.

8.15 COUNTER
When a group of flip-flops are connected in cascade, the counting operation is performed. Then, this
sequential circuit is most commonly used for counting purpose, and this circuit is called as counter. The
counter is also a memory system as any counter circuit must remember its past states and it possesses
data in memory. In this chapter, the connections of flip-flops to make any type of counter and their
operations have been explained. Counters are mostly used in digital computers, digital telephone and
digital instruments. A number of flip-flops are required for different asynchronous and synchronous
counters, divide by ‘n’ counters, and their connection diagram and the numbers of sequential states are
explained. The design of synchronous counters, cascade counters and self-starting and self-correcting
counters are also discussed in this chapter.
8.16 CLASSIFICATION OF COUNTER
There are several types of counters, which are able to count binary numbers. Counters can be classified
based on application of clock, number of flip-flops (stages) and sequential states. According to
application of clock to flip-flops, counter is divided into two broad categories namely asynchronous
and synchronous counters. As per number of flip-flops (stages) counters are 2 bit, 3 bit, 4 bit and n bit.
Counters can also be used as count up or count down based on sequential states.
Asynchronous (Ripple) Counters In asynchronous counter, the external clock pulse clocks
the first flip-flop. Then, the output of first flip-flop (Q or Q–) is connected as clock of the next flip-flop.
–
Similarly, each successive flip-flop is clocked by the Q or Q of the previous one. All flip-flops do not
change states in exact synchronism with the applied clock pulses. There is some propagation delay between
responses of successive flip-flops. The asynchronous counter is also called as ripple counter due to the
way of flip-flop response one after another in a kind of rippling effect. The maximum clock frequency
of an asynchronous counter decreases with the increase of number of flip-flops or bits. Asynchronous
counter can generate glitches in decoding gates due to propagation delays. Therefore, strobing technique
should be used for eliminating the effects of glitches.
Synchronous Counters In synchronous counter, the clock input terminals of all flip-flops are
commonly connected. Therefore, the same clock pulse simultaneously triggers all flip-flops of the counters
and the problem caused by the flip-flop propagation delay has been eliminated in these counters. For a
synchronous counter, the maximum frequency remains same, regardless of the number of bits.
Count Down Counter Synchronous and asynchronous counters are able to count either in increasing or
decreasing order. In count down counter, the counter value sequentially decreases. In a three stage down counter,
the counting sequence is 7, 6, 5, 4, 3, 2, 1, and 0. This counter can be made by J-K or T or D flip-flops.
Count Up Counter In count up counter, the counter value sequentially increases. The counting sequence of
three-stage counter is 0, 1, 2, 3, 4, 5, 6, and 7. This counter can also be designed by J-K or T or D flip-flops.
 Sequential Circuits 319

8.17 ASYNCHRONOUS (RIPPLE) COUNTERS

The sequence of binary counter follows a divide-by-two pattern. This means that the frequency for
each bit, from least significant bit (LSB) to most significant bit (MSB), follows a divide-by-two pattern.
Therefore, the LSB is half of the clock frequency and the highest frequency among all stages. The
frequency of the next bit is one-half the LSB’s frequency. The counter circuit can be designed using T
flip-flops or J-K flip-flops when operate in the toggle mode to count in a binary sequence.
8.17.1 1 bit Ripple Counter
One bit ripple counter using J-K flip-flops is shown in
Fig. 8.41. When J and K inputs are made high, J-K flip-
flop is operating in toggle mode. As a result, after each
positive edge clock pulse, output of flip flop is changed.
Here, the signal A is clock pulse and B represents the
output of J-K flip-flop. The count sequence is from 0 to
1 and 1 to 0. Timing diagram of one bit asynchronous
Fig. 8.41 One bit asynchronous counter counter is depicted in Fig. 8.42.

Fig. 8.42 Timing diagram of one bit asynchronous counter

8.17.2 2-bit Ripple Up Counter

A two-bit asynchronous counter is shown in Fig. 8.43. Usually, all
the CLEAR inputs are connected together, so that a single pulse can
clear all the flip-flops before counting starts. The external clock is
connected to the clock input of the first flip-flop (FF0) only. So, FF0
changes state at the negative edge of each clock pulse, but FF1 changes
only when triggered by the falling edge of the Q output of FF0. Due
to propagation delay the transition of the input clock pulse and a
Fig. 8.43 2-bit ripple counter
transition of the Q output of FF0 can never occur at exactly the same
time. Therefore, all flip-flops cannot be triggered simultaneously
and an asynchronous operation is performed. The transitions of
CLK, Q0, and Q1 are shown in the timing diagram as shown in
Fig. 8.44. Truly, there is some small delay between the CLK, Q0
and Q1 transitions.
Fig. 8.44 Timing diagram of 2-bit The 2-bit ripple cou- Table 8.8 State sequence for 2-bit
Binary up counter nter circuit has four dif- ripple up counter
ferent states as depicted in Table 8.8. The relationship between Clock pulse Q1 Q0
number of bits (flip-flops) and number of states is that a coun- 0 0 0
ter with n flip-flops can have 2n states. The number of states 1 0 1
in a counter is known as its modulo number or mod number. 2 1 0
Accordingly, a 2-bit counter is a mod-4 counter. The timing 3 1 1
 320 Digital Electronics: Principles and Applications

diagram of two bit asynchronous counter is illustrated in

Fig. 8.44 and state transition diagram of 2-bit counter is
depicted in Fig. 8.45.

Fig. 8.45 State transition diagram of

8.17.3 2-bit Ripple Down Counter 2-bit up-counter binary
A two-bit ripple down counter is shown in Fig. 8.46. The
external clock is applied to the clock input of the flip-flop, FF0
only. The output of FF0 is used as clock of FF1. In count down
counter, outputs Q0 and Q1 are taken from complement output
of FF0 and FF1 respectively. Timing diagram of two-bit ripple
down counter is depicted in Fig. 8.47. The state sequence of
counting is 3, 2, 1, and 0 is given in Table 8.9. Figure 8.48
shows the state transition of 2-bit ripple down counter.

Fig. 8.47 Timing own counter diagram 2-bit ripple Fig. 8.48 State transition diagram of 2-bit
binary down counter
Table 8.9 State sequence for 2-bit ripple down counter
Clock pulse Q1 Q0
0 1 1
1 1 0
2 0 1
3 0 0

8.17.4 3-bit Ripple Up Counter

Figure 8.49 shows the 3-bit ripple counter, which is implemented
using three J-K flip-flops. The counter is capable to count up
to 23=8. This counter is also called as module 8 or divide by 8
counters. The truth table of 3-bit counter is given in Table 8.10.
When the clock pulse is applied to the counter, the counter value Fig. 8.49 3-bit ripple up counter
sequentially increases state by state and the output of flip-flops
indicates the count of pulses in counter. Waveform of three-bit
binary ripple counter is shown in Fig. 8.50.
At the positive edge of the first clock pulse, flip-flop FF0 sets
and the output Q0 becomes 1 and this output does not affect on
the output of FF1. So the counter output will be updated to 001 Fig. 8.50 Timing of 3-bit ripple up
from 000 as shown in row 2 of Table 8.10. When the second counter
 Sequential Circuits 321

Table 8.10 Truth table of 3-bit clock pulse, is applied, flip-flop FF0 is reset and the output of FF0
ripple up counter changes from 1 to 0. After the second clock pulse, flip-flop FF1 is
State Q2 Q1 Q0 set and the output of FF1 changes from 0 to 1. Then counter output
0 0 0 0 will be 010 as depicted in third row. When the third clock pulse is
1 0 0 1 applied, FF0 flip-flop sets and output becomes 1. At this time, the
2 0 1 0 state of FF1 and FF2 do not change. At that moment, the output of
3 0 1 1 the counter is 011. If the fourth clock pulse is applied, flip-flop FF0
4 1 0 0 resets and the output of FF0 changes from 1 to 0. In this time flip-
5 1 0 1
6 1 1 0 flop FF1 resets and the output of FF1, Q1 will be 0, which changes
7 1 1 1 the flip-flop FF2 to 1.
As soon as the fifth clock pulse given in FF0, the said flip-flop
sets and output Q0 becomes 1, while the output of flip-flop FF1 and FF2 are not affected. After fifth
pulse, the counter output is 101. In the next pulse, flip-flop FF0 resets and flip-flop FF1 and FF2 are set.
During the 7th pulse, all flip-flops, FF0, FF1, and FF2, are set and the counter output will be 111. When
the eighth pulse is applied, all flip-flops are reset and then counter output is 000. In this way, the counter
counts 0 to 7 sequentially.

8.17.5 3-bit Ripple Down Counter

Figure 8.51 shows the circuit diagram of 3-bit down counter. In up counter, the output Q0, Q1 and Q2 are
taken from output Q of flip-flops FF0, FF1, and FF2 respectively,
–
but in down counter, the complement output Q of flip-flop FF0,
FF1, and FF2 are connected to Q0, Q1 and Q2. Truth table of 3-
bit ripple down counter is shown in Table 8.11.
Initially, consider that all flip-flops are reset and the counter
output will be 111. As soon as the first clock pulse is applied
to the flip-flop FF0, it will be set. The complement output of
Fig. 8.51 3-bit ripple down counter FF0 is 0. The output of FF1 will be 0 and it complement is
1. The output of FF2 will also be 0 and its complement is 1.
Table 8.11 Truth table of 3-bit ripple
down counter
Therefore, the counter output is 110.
After application of second clock pulse, FF0 flip-flop will
State Q 2 Q1 Q 0 be reset. The complement output of FF0 is 1, which affects the
0 1 1 1 FF1flip-flop. So the counter output is 101. Similarly, it is de-
1 1 1 0
picted from table that the counter sequentially decreases one
2 1 0 1
3 1 0 0 by one after applying each clock pulse. After applying sixth
4 0 1 1 clock pulse counter value is 001 and at the end of seventh
5 0 1 0 clock pulse the
6 0 0 1 output of coun-
7 0 0 0 ter is 000. Figure
8.52 shows the waveform of 3-bit ripple down counter.

8.17.6 4-bit Ripple Up Counter

Figure 8.53 shows the circuit diagram of 4-bit ripple up Fig. 8.52 Timing diagram of 3-bit ripple
counter, which is made by four J-K flip-flops. Truth table down counter
 322 Digital Electronics: Principles and Applications

of 4-bit ripple up counter is depicted in Table 8.12. This

counter counts sequentially from 0000 to 1111 like three
bit ripple up counter. The state transition diagram is given
in Fig. 8.54. Figure 8.55 shows the waveform of 4-bit
ripple up counter. It can be viewed that the output of each
Fig. 8.53 4 bit ripple up counter flip-flop divides the input clock frequency by 2.

Fig. 8.54 Waveform of 4-bit Fig. 8.55 State transition diagram of 4-bit ripple up counter
ripple up counter
Table 8.12 Truth table of 4-bit ripple up counter
State Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

8.17.7 4-bit Ripple Down Counter

Figure 8.56 shows the circuit diagram of 4-bit ripple
down counter, which is made by four J-K flip-flops.
Truth table of 4-bit down counter is depicted in
Table 8.13. This counter counts sequentially from
1111 to 0000. The state transition diagram is given
in Figure 8.57. Figure 8.58 shows the waveform of
4-bit ripple down counter. Fig. 8.56 4-bit ripple down counter
 Sequential Circuits 323

Table 8.13 Truth table of 4-bit ripple down counter

State Q3 Q2 Q1 Q0
0 1 1 1 1
1 1 1 1 0
2 1 1 0 1
3 1 1 0 0
4 1 0 1 1
5 1 0 1 0
6 1 0 0 1
7 1 0 0 0
Fig. 8.57 State transition of 4-bit
8 0 1 1 1
ripple down counter
9 0 1 1 0
10 0 1 0 1
11 0 1 0 0
12 0 0 1 1
13 0 0 1 0
14 0 0 0 1
15 0 0 0 0

Fig. 8.58 Timing diagram of 4-bit ripple down

counter

8.18 ASYNCHRONOUS DECADE COUNTERS

The n bit binary counter has two to the power n states. But counter with states less than the number, 2n
is also possible. The counter is designed with flip-flops and logical gates to have the number of states
in sequences. This sequence is called as truncated
sequences. These sequences can be achieved by
using logic gates, which can force the counter to
recycle from any count value. A decade counter
has ten truncated sequences. As there are ten states
from 0 to 9, four flip-flops are required for decade
counter. An implementation of a decade counter is
Fig. 8.59 Decade counter
shown in Fig. 8.59.
Table 8.14 The sequence of the Once the counter counts to ten (1010), all four flip-flops will
decade counter be cleared. Therefore, Q1 and Q3 are used to decode the count
State Q3 Q2 Q1 Q0 of ten. Table 8.14 shows the truth table of decade counter. As
the decade counter has ten states, it is also called as MOD-10
0 0 0 0 0
1 0 0 0 1 counter. This counter can be used to divide the external clock
2 0 0 1 0 input frequency by ten and the output will be available after every
3 0 0 1 1 ten-clock pulses. State transition of decade counter is depicted in
4 0 1 0 0 Fig. 8.60. Recycling of decade counter after counting 9 is possible
5 0 1 0 1 to decode count value (10)10 or (1010)2 using an AND gate and
6 0 1 1 0 the AND gate output is connected with the clear (CLR) inputs of
7 0 1 1 1
8 1 0 0 0 the flip-flops. Therefore, all flip-flops are reset and the counter
9 1 0 0 1 state becomes 0000. Figure 8.61 shows the timing diagram of
asynchronous decade counter.
 324 Digital Electronics: Principles and Applications

It is depicted in Fig. 8.61 that there is a glitch

on the output waveform of Q1. Before decoding the
count value (10)10 or (1010)2, Q1 must be high first.
The counter should stay at count 10 state for several
nano-seconds as the decoding gate requires several
nano-seconds propagation delay to generate output
F. Therefore, the counter should be in 1010 state for
a very short time before return back to 0000 state. In
this way, the glitch is generated on Q1 waveform.
Fig. 8.60 State transition of decade counter

Fig. 8.61 Timing diagram of decade counter Fig. 8.62 Simultaneous up-down counter

8.19 SIMULTANEOUS UP-DOWN COUNTER

Figure 8.62 shows a 4-bit simultaneous up-down counter. When output is taken from Q3, Q2, Q1 and Q0,
it generates a up-counting sequence. If output is taken from Q–3, Q–2, Q–1 and Q–0, it behaves as a down-
counting sequence. In this way the same circuit has the capabilities to operate either up or down counter
–
when outputs taken from Q and Q. Waveforms of four bit up-down counter are depicted in Fig. 8.63 (a)
and (b) respectively.

Fig. 8.63 (a) Wave form of four bit up counter and (b) Waveform of four bit down counter

8.20 ASYNCHRONOUS UP-DOWN COUNTERS

In certain applications, a counter must be able to count both up and down. Fig. 8.64 shows the 3-bit up-
down counter. It counts up or down depending on the status of the control signals UP and DOWN. When
the UP input is at 1 and the DOWN input is at 0, the NAND network between FF0 and FF1 will gate the
non-inverted output (Q) of FF0 into the clock input of FF1. Similarly, Q of FF1 will be gated through the
 Sequential Circuits 325

Fig. 8.64 3-bit asynchronous UP-DOWN counter

other NAND network into the clock input of FF2. Thus, the counter will count in UP direction. The functional
Table 8.15 Functional table of up counter
table of 3-bit up counter is shown in Table 8.15.
When the control input UP is at 0 and DOWN is at 1,
UP Down State FF2 FF1 FF0 the inverted outputs of FF0 and FF1 are gated into the
1 0 0 0 0 0 clock inputs of FF1 and FF2 respectively. If the flip-flops
1 0 1 0 0 1 are initially reset to 0’s, then the counter will go through
1 0 2 0 1 0 the following sequence as given in Table 8.16 when
1 0 3 0 1 1
1 0 4 1 0 0 clock pulses are applied. Then the counter behaves as
1 0 5 1 0 1 DOWN counter. An asynchronous up-down counter is
1 0 6 1 1 0 slower than an up counter or a down counter because
1 0 7 1 1 1 of the additional propagation delay introduced by the
NAND networks.
Table 8.16 Functional table of down counting
UP Down State FF2 FF1 FF0
0 1 0 0 0 0
0 1 1 1 1 1
0 1 2 1 1 0
0 1 3 1 0 1
0 1 4 1 0 0
0 1 5 0 1 1
0 1 6 0 1 0
0 1 7 0 0 1

8.21 PROPAGATION DELAY IN ASYNCHRONOUS COUNTER

The operations of asynchronous counters have been discussed in previous sections. The main
disadvantage of these counters is that they are slow. Asynchronous counters are not very useful at very
high frequencies, particularly for large number of bits. In these counters, each flip-flop is triggered by
the transition of the output of the preceding flip-flop. Due to the inherent propagation delay time tpd,
the first flip-flop output, Q0 will be available after a period of propagation delay tpd when clock pulse is
applied as shown in Fig. 8.65. The second flip-flop responds after 2  tpd. If the counter consists of ‘n’
flip-flops, then nth flip-flop changes state after n  tpd time delay from the input clock pulse. Therefore,
the proper operation of n-bit counter, the time period of clock signal should be greater than n  tpd.
 326 Digital Electronics: Principles and Applications

So Tclock > n  tpd

where, Tclock is the time period of clock,
n is the number of bits or stages and tpd is
propagation delay.
Then the clock frequency of asynchro-
nous counters for reliable operation is
1 1
> n · t pd or > f clock . Therefore,
f clock n · t pd
1
the maximum frequency is f max = . So
n · t pd
the maximum clock frequency for an asyn-
chronous counter fmax decreases as number of
bits increases.
For example, in a four stage asynchronous
counter, the propagation delay of each flip- Fig. 8.65 Waveform of a 3-bit asynchronous counter
with propagation delay tpd=50 ns
flop is 50ns, then the maximum frequency at
which the counter operate properly is
1 1
f max = = = 5 MHz.
n · t pd 4 · 50ns

8.22 ASYNCHRONOUS COUNTER ICS

The operation of asynchronous counters using their proper circuits and waveforms have been explained
in previous section. These counters are designed using flip-flops. Now a days, some asynchronous
counters are available in MSI ICs as shown in Table 8.17. Depending upon the features of counters, ICs
are divided into three different groups A, B and C. All these ICs consist of four master slave flip-flops
and the set, rest and load operations are independent of clock pulse or asynchronous. Before use any
counter ICs, designer should study the manufacturer data sheet of ICs.
Table 8.17 Asynchronous counter ICs
IC Numbers Description Features Group
7490, 74290 BCD counter Set, reset A
7492 Divide by 12 counter Reset B
7493, 74293 4 bit binary counter Reset B
74176, 74196 Presettable BCD counter Reset, Load C
74177, 74197 Presettable 4-bit binary counter Reset, Load C
74390 Dual decade counters Reset B
74393 Dual 4 bit binary counter Reset B
74490 Dual BCD counters Set, reset A

Example 8.5 Each flip-flop of a 3-bit asynchronous counter is positive edge triggered and has a
propagation delay of 10µs. Draw the timing diagram of the counter and determine the
delay time of Q2 after 4th clock pulse.
 Sequential Circuits 327

� Solution
Figure 8.66 shows the positive edge triggered 3-bit
asynchronous counter and it has propagation delay of 10µs.
Figure 8.67 shows the timing diagram of this counter. The
output Q0 has 10µs delay from clock input and output Q1 has
–
delay 10µs from Q0 and 20 µs from clock. The output Q2 has
–
also 10µs delay from Q1. Therefore Q2 has 30µs delay from
clock.
Fig. 8.66 3 bit asynchronous counter

Fig. 8.67 Timing diagram of asynchronous

counter

Example 8.6 How a 4-bit asynchronous counter can count 0000 to 1100?

� Solution
Figure 8.68 shows the 4-bit asynchronous counter to
count 0000 to 1100 and its timing diagram is depicted
in Fig. 8.69. When the counter has reached 1100, the
output of AND gate reset all flip-flops. Therefore, the
counter again starts counting from 0000.

Fig. 8.68 4-bit asynchronous counter to

count 0000 to 1100

Fig. 8.69 Timing diagram of asynchronous counter

to count 0000 to 1100
 328 Digital Electronics: Principles and Applications

8.23 SYNCHRONOUS COUNTERS

The synchronous counter is clocked in such way
that all flip-flops in the counter are triggered
simultaneously and all output bits also change
state simultaneously. This operation can be
performed when the clock is connected to clock
input of all flip-flops so that all flip-flops receive
the same clock pulse at the same time. Figure
8.70 shows that clock inputs of four flip-flops Fig. 8.70 Four flip-flops with same clock signal
are connected together and both J-K inputs are
high. Therefore J-K flip-flops operate in toggle mode and the divide-by-two frequency pattern can be
obtained from the output of each flip-flop. So this circuit cannot function as a counter. To achieve binary
sequence, J-K inputs of flip-flops will be connected to previous stage output directly or with some
special arrangement. In this section, the 2-bit, 3-bit and 4-bit synchronous counters are explained with
circuit diagrams and timing diagrams.
8.23.1 2-bit Synchronous Counter
Figure 8.71 shows the circuit diagram of two bit
synchronous counter. The operation of two bit counter is
given below:
Initially, both flip-flops are in reset condition and the
counter is in the binary 0 state. Therefore, the counter output
is 00. At the positive edge of the first clock pulse, FF0
operates in toggle mode and Q0, output of FF0 is high or 1.
But at the positive edge of first clock pulse CLK1, J and K are
both low as Q0 is connected with J and K inputs of FF1. As a Fig. 8.71 Two bit synchronous counter
result J=0 and K=0 and there is no change in output of FF1.
Hence the output of counter is 01 after CLK1.
At the second clock pulse (CLK2), both FF0 and FF1
operate in toggle mode as J and K inputs of flip-flops are
high. After the positive triggering edge of CLK2, Q0=0 and
Q1=1 and the output of counter is 10. At the leading edge
of CLK3, FF0 will operate in toggle mode and FF1 remains
set, as its J and K inputs are low. Therefore after the third Fig. 8.72 Timing diagram of 2-bit
synchronous counter
clock pulse, counter output Q0=1 and Q1=1. In the forth
clock pulse, again both FF0 and FF1 are in toggle condition. After the leading edge of forth clock pulse
CLK4, Q0=0 and Q1=0. The timing diagram of 2-bit synchronous counter is shown in Fig. 8.72.

8.23.2 3-bit Synchronous Counter

Figure 8.73 shows a three bit synchronous counter.
In this counter, the clock inputs of all three flip-flops
are connected together. Therefore, all the flip-flops
change state simultaneously. The J and K inputs of FF0
are connected to +V. The output of FF0 has connected Fig. 8.73 Three bit synchronous counter
 Sequential Circuits 329

with J and K inputs of FF1. The J and K inputs of FF2 are

connected to the output of an AND gate which has two inputs
Q0 and Q1. The timing diagram of 3-bit synchronous counter
is shown in Fig. 8.74. The sequence of states is also depicted
in Table 8.18.
J and K inputs of FF0 are always high and this flip-flop
Fig. 8.74 Timing diagram of 3- bit operates in toggle mode. The Q0 output changes on each clock
synchronous counter pulse from initial state to final state. FF1 will operate in the
toggle mode when the output of FF0 is high. At CLK2, CLK4,
Table 8.18 State sequence for 3-bit CLK6 and CLK8, FF1operates in toggle mode and will change
synchronous counter state. In CLK1, CLK3, CLK5 and CLK7, Q0 is a 0 and FF1 is in
Clock pulse Q2 Q1 Q0 the no-change mode. Therefore, the output of FF1 will remain
0 0 0 0 in its present state. The output FF2 will change when both Q0
1 0 0 1 and Q1 are high state. This condition is generated by the AND
2 0 1 0 gate and applied to the J and K inputs of FF2.
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0 8.23.3 4 bit Synchronous Counter
7 1 1 1
Figure 8.75 shows the four bit synchronous counter and all
four flip-flops are connected with a common positive edge triggered clock pulse. Therefore, all flip-
flops will be triggered simultaneously. As J and K inputs of FF0 are connected to high, FF0 flip-flip
will operate in toggle mode on each clock pulse.
FF1 flip-flop toggles when Q0 is high. If Q0 and Q1
are high, FF2 flip-flop toggles. When Q0, Q1 and
Q2 are high, FF3 flip-flop also operates in toggle
mode. The timing diagram of 4-bit synchronous
counter is depicted in Fig. 8.76 and sequence of
state of four bit synchronous counter is given in
Fig. 8.75 Four bit synchronous up counter Table 8.19.

This counter is implemented

with positive edge triggered flip-
flops. The operation of first three
flip-flops is same as the three-stage
counter. The fourth stage, FF3
changes only twice in the sequence.
The transitions of FF3 occur only
when Q0, Q1 and Q2 are high. This Fig. 8.76 Timing diagram of 4-bit synchronous up counter
condition is decoded by AND gates
as shown in Fig. 8.75.
 330 Digital Electronics: Principles and Applications

Table 8.19 Truth table of 4-bit synchronous up counter

State Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

8.24 SYNCHRONOUS DOWN

COUNTER
Figure 8.77 shows the four bit synchronous down
counter. FF0 toggles on every clock pulse. FF1 flip-
–
flop toggles only if Q 0 is high. FF2 flip-flop toggles
– –
only if Q 0 and Q 1 are high. FF3 flip-flop toggles only
– – –
if, Q 0, Q 1 and Q 2 are high. The timing diagram of 4- Fig. 8.77 Four bit synchronous down counter
bit synchronous counter is depicted in Fig. 8.78.

Fig. 8.78 Timing diagram of 4-bit synchronous

8.25 SYNCHRONOUS UP-DOWN COUNTERS

8.25.1 3-bit Synchronous Up-down Counter
Figure 8.79 shows the circuit of
a 3-bit synchronous up-down
counter. Similar to an asynchro-
nous up-down counter, a syn-
chronous up-down counter also
has an up - down control input,
which is used to control the di- Fig. 8.79 Three bit UP/DOWN synchronous down counter counter
 Sequential Circuits 331

Table 8.20(a) State sequence for 3-bit synchronous rection of the counter. State sequence of 3-
binary up counter bit synchronous up - down counter is given
———
UP/DOWN Clock pulse Q2 Q1 Q0 in Table 8.20 (a) and (b) respectively.
1 0 0 0 0
It is depicted in the sequence table of
1 1 0 0 1
1 2 0 1 0 three bit UP/DOWN synchronous counter
1 3 0 1 1 that Q0 toggles on every clock pulse for
1 4 1 0 0 both the UP and DOWN sequences. In the
1 5 1 0 1 UP counter, Q1 changes state on the next
1 6 1 1 0
1 7 1 1 1
clock pulse when Q0=1. But in the DOWN
counting sequence, Q1 changes state on the
Table 8.20(b) State sequence for 3-bit synchronous
next clock pulse when Q0=0. Q2 changes state
binary down counter
——— on the next clock pulse when Q0=Q1=1 for
UP/DOWN Clock pulse Q2 Q1 Q0
the UP sequence. In the DOWN sequence,
0 0 1 1 1 Q2 changes state on the next clock pulse
0 1 1 1 0
0 2 1 0 1 when Q0=Q1=0. These characteristics can
0 3 1 0 0 be implemented using AND, OR and NOT
0 4 0 1 1 logic gates as given in Fig. 8.79.
0 5 0 1 0
0 6 0 0 1
0 7 0 0 0

8.25.2 4-bit Synchronous Up-down Counter

——–—
Figure 8.80 shows the four bit synchronous up-down counter. The UP/DOW N control input is used to
enable the counter for counting either upward direction or downward direction with the help of AND
– ——–—
gates to pass the Q/Q outputs to the succeeding stages of flip-flops. When the UP/DOW N control line is in
high state, the top AND gates become
enabled, and the circuit behaves as
synchronous up counter. If the UP/
——–—
DOW N control line is “low,” the
bottom AND gates become enabled,
and the circuit works as synchronous
down counter.
Fig. 8.80 Four bit synchronous up-down counter

8.26 SYNCHRONOUS DECADE

COUNTERS
The synchronous decade counter counts from 0
to 9 and also operates in a truncated sequence.
It does not count 1010 state, but this 1010 state
force the counter to back 0000 state. For this, the
synchronous decade counter operates in truncated Fig. 8.81 Synchronous decade counter
 332 Digital Electronics: Principles and Applications

sequence. Figure 8.81 shows the 4-bit synchronous Table 8.21 State sequence of a synchronous
decade counter. State sequence of decade counter is decade counter
given in Table 8.21. Clock Pulse Q3 Q2 Q1 Q0
It is very clear form the Table 8.21 that Q0 toggles 0 0 0 0 0
on each clock pulse. Consequently the logic equation 1 0 0 0 1
for J and K inputs of FF0 is J=K=1. When Q0=1 and 2 0 0 1 0
Q3=0, Q1 changes on the next clock pulse every time. 3 0 0 1 1
4 0 1 0 0
So the logic equation for J and K inputs of FF1 is 5 0 1 0 1
–
J=K=Q0 Q3. But Q2 changes on the next clock pulse 6 0 1 1 0
each time when Q0=Q1=1. The logic expression for 7 0 1 1 1
J and K inputs of FF2 is J=K=Q0Q1. Q3 changes 8 1 0 0 0
9 1 0 0 1
on the next clock pulse each time when Q0=1 and
Q3=1 for count 9 and Q0=Q1=Q2=1 for count 7.
Therefore the logic expression for J-K inputs of FF3
is J=K=Q0Q1Q2+Q0Q3. These characteristics can be
implemented by using AND, and AND and OR logic
gates as depicted in Fig. 8.81. The timing diagram of
a synchronous decade counter is shown in Fig. 8.82.
8.27 PROPAGATION DELAY IN
Fig. 8.82 Timing diagram of synchronous
SYNCHRONOUS COUNTER decade counter
The propagation delay of asynchronous counters
has been discussed in Section 8.21. The delay time response of a synchronous counter is the time taken
by one flip-flop to toggle and the time for new logic levels to propagate through AND gate to reach the
J-K inputs of the flip-flops. The total delay time of a synchronous counter can be expressed as
Total delay time = Propagation delay of one flip-flop (tpd) + propagation delay of AND gate (tg)
The propagation delay is always constant and it is independent of the total number of flip-flops.
Usually, it will be much lower than propagation delay in asynchronous counters with the same number
of flip-flops. Hence, the speed of operation of synchronous counters is limited by the propagation delays
of AND gates and a single flip-flop. In a there bit synchronous counter, only one AND gate is used.
Therefore, the maximum clock frequency of a there bit synchronous counter for reliable operation is
1
f max =
t pd + t g
where, tpd is propagation delay and tg is the propagation delay of AND gate.
As all three flip-flops of a there bit synchronous counter are connected to a common clock pulse,
glitches can be avoided completely in this counter.
A four bit synchronous counter is known as synchronous counter with parallel carry. In this counter,
the number of stages is four and the number of AND gates also increases to two along with the number
of inputs for the AND gates. This is the disadvantages of this circuit. Then the maximum clock frequency
of a four bit synchronous counter for reliable operation is
1 1
f max = =
t pd + 2 · t g t pd + (n - 2) · t g
 Sequential Circuits 333

where, tpd is propagation delay , tg is the propagation delay of AND gate and n is number of stages
or bits.
For an n bit synchronous counter, the maximum clock frequency can be determined by
1
f max = .
t pd + (n - 2) · t g
For example, in a seven stage synchronous counter, the propagation delay of each flip-flop is 50ns
and propagation delay of AND gate is 10ns, then the maximum clock frequency at which the counter
operate properly is
1 1
f max = = = 50MHz as tpd = 50ns , tg =10ns and n =7.
t pd + (n - 2) · t g 50ns + (7 - 2)10ns
8.28 SYNCHRONOUS COUNTER ICs
The operations of synchronous counters with circuits and waveforms have been explained in previous
sections. Generally, these counters are designed using flip-flops. Presently, some synchronous counters
are available in MSI ICs as shown in Table 8.22. Depending upon the features of counters, ICs are
divided into four different groups A, B, C and D. All these ICs are positive edge triggered and loading,
clearing and change of states take place on the positive edge of input clock pulse. Table 8.22 shows the
synchronous counter ICs and designer should study the manufacturer data sheet of counter ICs before
application of any counter ICs.
Table 8.22 Synchronous counter ICs
IC Numbers Description Features Group
74160 Decade UP counter Synchronous preset and asynchronous clear A
74161 4 bit binary UP counter Synchronous preset and asynchronous clear A
74162 Decade UP counter Synchronous preset and asynchronous clear A
74163 4-bit binary UP counter Synchronous preset and asynchronous clear A
74168 Decade UP/Down counter Synchronous preset and asynchronous clear B
74169 4-bit binary UP counter Synchronous preset and asynchronous clear B
74190 Decade UP/Down counter Synchronous preset and asynchronous clear C
74191 4-bit binary UP counter Synchronous preset and asynchronous clear C
74192 Decade UP/Down counter Synchronous preset and asynchronous clear D
74193 4-bit binary UP counter Synchronous preset and asynchronous clear D

Example 8.7 Figure 8.83 shows the 4-bit synchronous counter. Determine the sequence of counter.

� Solution
Table 8.23 shows the sequence of counter as illustrated in Fig. 8.83.

Fig. 8.83 4-bit synchronous counter

 334 Digital Electronics: Principles and Applications

Table 8.23 Sequence of counter

State Q3 Q2 Q1 Q0
0 1 1 1 1
1 1 1 1 0
2 1 1 0 1
3 1 1 0 0
4 1 0 1 1
5 1 0 1 0
Fig. 8.84 Waveform of 3-bit sequence counters 6 1 0 0 1
7 1 0 0 0
8 0 1 1 1
9 0 1 1 0
10 0 1 0 1
11 0 1 0 0
12 0 0 1 1
13 0 0 1 0
14 0 0 0 1
15 0 0 0 0

Example 8.8 The waveform of 3-bit synchronous binary UP/DOWN counter is shown in Fig. 8.84.
Determine the sequence of counter.
� Solution
Table 8.24 shows the sequence of 3-bit synchronous binary UP/DOWN counters.
Table 8.24 State sequence for 3 bit synchronous binary UP/DOWN counters
———
UP/DOWN Clock pulse Q2 Q1 Q0
1 0 0 0 1
1 1 0 1 0
1 2 0 1 1
1 3 1 0 0
0 4 0 1 1
0 5 0 1 0
0 6 0 0 1
0 7 0 0 0
1 8 0 0 1
1 9 0 1 0
1 10 0 1 1
1 11 1 0 0

Example 8.9 The sequence of 3-bit synchronous binary UP/DOWN counter is shown in Table 8.25.
Draw the timing diagram of counter.
Table 8.25 State sequence for 3 bit synchronous UP/DOWN counter
———
UP/DOWN Clock pulse 2
Q1 Q0
1 0 0 0 1
1 1 0 1 0
1 2 0 1 1
1 3 1 0 0
(Contd...)
 Sequential Circuits 335

Table 8.25 (Contd...)

1 4 1 0 1
1 5 1 1 0
0 6 1 0 1
0 7 1 0 0
0 8 0 1 1
0 9 0 1 0
1 10 0 1 1
1 11 1 0 0
� Solution
Figure 8.85 shows the timing diagram of Table 8.25 for 3-bit synchronous UP/DOWN counters.

Fig. 8.85 Waveform of 3-bit synchronous UP/DOWN counters

8.29 MOD n COUNTER

The counter can be designed in such a way that the counter starts counting any preset value to any required
value. The modulus of counter with four flip-flops in up counting mode for any preset value is 24-N-1. If
the preset state, N is =3, the modulus of counter is 16-3-1=12. In down counting operation, the counter
starts count down from preset state. When the preset state of down counter is (11)10 or 1011, the counter
sequentially counts down from 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, and 0. So the modulus of down counter is
Nmax+1 where, Nmax is the maximum count value which equal to (11)10. If the counter maximum value is
12, the counter will be mod 13. The mod ‘n’ counters can be designed by the counter reset, logic gates
and interconnection of counters. In counter reset method, when the counter completes the desired count,
all flip-flops of counter will be reset and counter start counting from reset state. In some cases, logic
gates are used to generate the counting sequence without the resetting the counter. Counters may also be
connected in cascade to implement
a counter. When mod 2 and mod 8
counters are connected in cascade,
the counter circuit behaves as mod
16 counters. Figure 8.86 shows the
cascade connection of mod-2 and
mod-8 counters. The timing diagram
is shown in Figure 8.87. It is clear
from timing diagram that final
output can be obtained after 16 clock
Fig. 8.86 Cascade connection of mod-2 and mod-8 counters pulses. Hence the overall modulus of
 336 Digital Electronics: Principles and Applications

the cascaded counters

is 2 × 8 =16. This also
called as divide by16
counter.

Fig. 8.87 Timing diagram of mod-16 counter

8.29.1 Mod-3 Counter

Figure 8.88 shows the state transition diagram of mod three counters. As there are three states, two flip-
flops are required to implement it. Table 8.26 shows the truth table of mod-3 counter. The counter counts
0, 1, 2 sequentially. After counting 2 it returns to 0. This is possible,
Table 8.26 Truth table of
when a combinational logic circuit reset all flip-flops at the counter Mod-3 counter
state 3. Figure 8.89 shows the circuit diagram of mod-3 counter. It is
Count Q1 Q0
depicted in figure that output of flip-flop FF0 and FF1 are connected 0 0 0
into an NAND gate and output of NAND gate can be used to reset or 1 0 1
clear flip-flops FF0 and FF1. At the counter state 3, FF0 and FF1 will be 2 1 0
1 and NAND gates output is 0 which reset flip-flops. Then the counter
sequentially counts 0, 1, and 2. The waveform of mod-3 counter is given in Fig. 8.90.

Fig. 8.88 State transition diagram Fig. 8.89 Circuit diagram Fig. 8.90 Waveform of
of mod-3 counter of mod-3 counter mod-3 counter

8.29.2 Mod-5 Counter

The state transition diagram of mod-5 counter is shown in Fig. 8.91.
Three flip-flops are required to implement it. Table 8.27 shows the truth
table of mod-5 counter. The counter counts 0, 1, 2, 3, and 4 sequentially.
After counting 4, it returns to 0. Therefore a combinational logic circuit
is required to reset all flip-flops at the counter state 5. The circuit Fig. 8.91 State transition
diagram of mod-5 counter is depicted in Fig. 8.92. The waveform of diagram of mod-5
mod-5 counter is given in Fig. 8.93. counter
 Sequential Circuits 337

Fig. 8.92 Circuit diagram of mod-5 counter Fig. 8.93 Waveform of mod-5 counter

8.29.3 Mod-12 Counter

Table 8.27 Truth table of
mod-5 counter The state transition diagram of mod-12 counter is shown in Fig. 8.94.
Four flip-flops are required to implement it. Table 8.28 shows the truth
Count Q2 Q1 Q0
table of mod 12 counter. The counter counts 0, 1, 2, 3, 4, 5, 6, 7, 8,
0 0 0 0
1 0 0 1 9, 10 and 11 sequentially. After counting 11 it returns to 0. Therefore
2 0 1 0 a combinational logic circuit is required to reset all flip-flops at the
3 0 1 1 counter state 12. The circuit diagram of mod-12 counter is depicted in
4 1 0 0 Fig. 8.95. The waveform of mod-12 counter is given in Fig. 8.96.

Table 8.28 Truth table of Mod-12 counter

Count Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0 Fig. 8.94 State transition diagram
11 1 0 1 1 of mod 12 counter

8.30 SYNCHRONOUS COUNTER DESIGN STEPS

The basic operation of synchronous counters is already explained in this chapter. In this section, the
design of synchronous counter is explained
below sequentially:
Step-1 Define the counting sequence of
counter and draw the state diagram of the
counter.
Step-2 Develop a truth table of the counter
Fig. 8.95 Circuit diagram of of mod 12 counter with present sate and next state.
 338 Digital Electronics: Principles and Applications

Step-3 The unused state of the counter should be tabulated in the present state and the next state
should be initial count value. But, in practice, the unused states of the counter do not shown
in flip-flop excitation table.
Step-4 Select T or D or J-K or R-S flip-flops for
design a counter and find the number of
flip-flops considering the expression 2n ≥
m, where n is the number of flip-flops and
m is the number of counting sequence.
Step-5 Draw the K-maps for all flip-flop inputs.
Step-6 Derive the simplified expression for all
flip-flop inputs. Fig. 8.96 Waveform of mod-12 counter
Step-7 The implementation circuit diagram of
counter with flip-flops and logic gates.
By using above steps, mod-5 synchronous counter and mod-10 synchronous counter design are
explained in this section.

8.30.1 Mod-5 Synchronous Counter

The counting sequence of mod-5 counter is 0, 1, 2, 3, 4,
0, 1, 2… and Table 8.29 shows the counting sequence of Table 8.29 Sequence of mod-5 counter
mod-5 counter. The state diagram of mod-5 counter is Clock pulse Q2 Q1 Q0
given in Section 8.29.2. To design this counter, three flip- 0 0 0 0
flops are required and all flip-flops are connected with a 1 0 0 1
common clock pulse. To generate the counting sequence, 2 0 1 0
flip-flop inputs are given in flip-flop excitation table as per 3 0 1 1
4 1 0 0
Table 8.30. The initial state of flip-flop FF0 is 0 and its
output will be changed to 1 after applying clock pulse. For that reason, J0 must be 1 and K0 must be 0 or
1 (X). The initial state of flip-flop FF1 is 0 and it’s output will not be unchanged after the clock pulse and
consequently J1 will be 0 and K1 will be 0 or 1 (X). The state of FF2 does not changed after the first clock
pulse and therefore, J2 will be 0 and K2 will be 0 or 1 (X). The other input states of FF0, FF1 and FF2
to develop the sequence are depicted in Table 8.30. The Karnaugh map for J0, K0, J1, K1, J2, and K2 are
shown in Fig. 8.97(a) to Fig. 8.97(f) respectively. The simplified expressions for all flip-flops inputs are
–
J0 = A , K0 =1, J1=C, K1=C, J2=BC, and K2=1. Figure 8.98 shows the implementation of mod-5 counter
using flip-flops and logic gates.
Table 8.30 Flip-flop excitation table of mod-5 counter
Clock pulse Preset state Next state Flip-flop inputs
FF2 FF1 FF0
CLK Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
A B C A B C
0 0 0 0 0 0 1 0 x 0 x 1 x
1 0 0 1 0 1 0 0 x 1 x x 1
2 0 1 0 0 1 1 0 x x 0 1 x
3 0 1 1 1 0 0 1 x x 1 x 1
4 1 0 0 0 0 0 x 1 0 x 0 x
 Sequential Circuits 339

–
Fig. 8.97 (a) K-map for J0= A (b) K-map for K0 ( K0= 1) (c) K-map for J1 (J1= C)

and (d) K-map for K1 (K1= C) (e) K map for J2 (J2=BC) and (f ) K map for K2 (K2=1)

Fig. 8.98 Mod-5 counter

8.30.2 Mod-10 Synchronous Counter
In mod-10 counters the counting sequences are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0….. The state diagram and
sequence table of mod-10 counter are given in Section 8.18. To design this counter, four flip-flops are
required and all flip-flops are connected with a common clock pulse. Assume that J-K flip-flips are
used to design mod-10 counter. To produce the above counting sequence, all flip-flop inputs are given
in flip-flop excitation Table 8.31. The Karnaugh map for J0, K0, J1, K1, J2, K2, J3, and K3 are shown in
–
Fig. 8.99(a) to Fig. 8.99(h) respectively. The simplified expressions for all flip-flops inputs are J0 = Q3
– – – – – – – – – – – – – –
+ Q2 Q1, K 0 = Q3 + Q2 Q1, J1 = Q3 Q0, K1 = Q3 Q0, J2 = Q3Q1Q0, K2 = Q3Q1Q0, J3 = Q3 Q2 Q1 Q0 and K3 = Q2
Q–1Q0. The implementation of mod-10 counter using flip-flops and logic gates is shown in Fig. 8.100.
Table 8.31 Flip-flop excitation table for mod -10 counter
Clock Preset state Next state Flip-flop inputs
pulse FF3 FF2 FF1 FF0
CLK Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 J3 K3 2
K2 J1 K1 J0 K0
0 0 0 0 0 0 0 0 1 0 x 0 x 0 x 1 x
1 0 0 0 1 0 0 1 0 0 x 0 x 1 x x 1
2 0 0 1 0 0 0 1 1 0 x 0 x x 0 1 x
3 0 0 1 1 0 1 0 0 0 x 1 x x 1 x 1
4 0 1 0 0 0 1 0 1 0 x x 0 0 x 1 x
5 0 1 0 1 0 1 1 0 0 x x 0 1 x x 1
6 0 1 1 0 0 1 1 1 0 x x 0 x 0 1 x
7 0 1 1 1 1 0 0 0 1 x x 1 x 1 x 1
8 1 0 0 0 1 0 0 1 x 0 0 x 0 x 1 x
9 1 0 0 1 0 0 0 0 x 1 0 x 0 x 0 x
 340 Digital Electronics: Principles and Applications

– – – – – – –
Fig. 8.99 (a) K map J0 = Q3 + Q2Q1 and (b) K map K0 = Q3 + Q2Q (c ) K map J1 = Q3Q0 and

– – –
(d) K map K1 = Q3Q0 (e) K map J2 = Q3Q1Q0 and (f) K map K2 = Q3Q1Q

– – –
and (g) K map J3 = Q3Q2Q1Q0 (h) K map K3 = Q2Q1Q0

8.31 CASCADE COUNTERS

Counters are connected in cascade to construct higher
mod counters with smaller mod counters. In this counters,
the last stage output of one counter is fed to another
counter. Figure 8.101 shows the cascade connection of
two counters: one is mod-4 counter and other is mod-8
Fig. 8.100 Mod-10 counter
counter. The output of mod-4 counter is connected with
input of clock of mod-8 counter. The overall mod value of counter is determined after multiplication of
individual mod value of counters. So, the mod value is 4 × 8=32. Figure 8.102 shows the timing diagram
of mod-32 counter.

Fig. 8.101 Cascade connection of mod-4 Fig. 8.102 Waveform of mod-32 counter due connec-
and mod-8 counters tion of mod-4 and mod-8 counters to cascade
 Sequential Circuits 341

Synchronous counters can be connected in cascade from. For this count enable (CE) and terminal
count (TC) are used for higher mod counter. Figure 8.103 shows the cascade connection of two mod-
10 counters. When count enable (CE) signal is high, counters start counting. Here, terminal count of
counter -1 is connected to count enable (CE) terminal of counter-2.
When counter-1 does not reach its last count state, the TC signal of counter-1 is low and counter-2 is
inhibited. After completion of first cycle counting of counter-1, TC signal of counter-1 becomes high.
This high enables counter-2 and the counter-2 starts to count and changes to next state. When the first
clock pulse is applied to counter-1, this counter should reaches its last stage of count or terminal count
at 10th clock pulse (CLK10) and counter-2 starts counting from its initial state to next state.
After completion of the second cycle of counter-1, TC of counter -1 is again high and counter-2 is again
enabled and its state changes to next state. This operation continues for ten cycles. After the ten cycle
operations, the counter-2 generates terminal count TC. Therefore, counter-1 generates TC after ten clock
cycles but counter-2 generates TC after 10 × 10=100 clock cycles. In this way, counter-2 will complete one
cycle after 100 clock pulses and the overall mod value of two cascaded Mod-10 counters is 100. This circuit
can be used as frequency divider. When input frequency of clock signal (CLK) is fin, the frequency of TC of
counter-1 is fin/10 and the frequency of TC of counter-2 is fin /100 as shown in Fig. 8.103.
When the mod-10 counters are connected in cascade, the output frequency will be fin/10, where fin is
the input frequency. Figure 8.104 shows the cascade connection of three counters and a 10 MHz clock
frequency has been applied to counter-1. Then output frequencies of three counters are 1 MHz, 100 KHz
and 10 KHz respectively.

Fig. 8.103 Cascade connection of two mod-10 counters

Fig. 8.104 Cascade connection of three mod-10 counters

Example 8.10 Determine the mod value of counter as shown in Fig. 8.105(a) and (b).

Fig. 8.105(a) Fig. 8.105(b)

 342 Digital Electronics: Principles and Applications

� Solution
(a) The mod value of two cascade counters as shown in Fig. 8.105(a) is 2×10=20
(b) In Fig. 8.105(b), three different counter are connected in cascade. The mod value of three cascade
counters is 10×5×8=400
8.32 PROGRAMMABLE OR PRESETTABLE COUNTERS
Generally the up counters start the count sequence from 000..0, but the down counters start counting from
111…1 state. This is done when all the flip-flops are reset or set after completion of each counting cycle. A
counter can also be made to start counting in any desired state using combinational logic circuits. Programmable
counters have the capability to start counting
from any desired state. The Programmable
counters are known as Presettable counters,
which can be preset to any desired starting
count. Presettable counters are two types, such
as asynchronous presetting and synchronous
presetting counters. Asynchronous presetting
is independent of the clock input, while
synchronous presetting occurs on the active
edge of the clock signal. Figure 8.106 shows a
three bit synchronous presetting counter. In this
counter, apply the desired count value to P2,
P1 and P0 inputs. When the preset load (PL) is
low, the count value is loaded into the counter
flip-flops. After that the preset load (PL) input
becomes high, the NAND gates are disabled
and the counter is free to count input clock
pulses starting from the newly entered count Fig. 8.106 Three bit programmable or presettable
value which has been preset into the flip-flops. counter
Most commonly used Presettable counters ICs
are 74ALS190, 74ALS191, 74ALS192, 74ALS193, 74HC190, 74HC191, 74HC192 and 74HC193.
8.33 SELF STARTING AND SELF CORRECTING COUNTERS
The counter already explained in
previous sections always starts
counting sequence from either
000 or 111. In real working en-
vironment, we can not able to
assume that the counter will al-
ways start from this predefined
count value. As soon as the power
switch is ON, the states of the flip-
flops is undefined, they will be set
or reset at random. Therefore, the
counter should not be able to start Fig. 8.107 (a) State transition diagram of self-start counter and
from any predefined state and the (b) State transition diagram of self-start counter
 Sequential Circuits 343

counting states will not be correct. This problem can be eliminated by self starting and self correcting
counters.
In any mod-n counter, all possible states are not present but only required states are present. But in a self-
starting counter
each possible
state are present
through some
states which
–– –– –– are not desired
Fig. 8.108 (a) K map for (D0 = A B + BC + C A ) and (b) K map for
–– – – –
(D1 = A B C + A BC ) and (c) K map for D3 = (D3 = A BC + ABC )
–– count sequence.
The self-start-
ing and self-correcting counters should have a sequence of transitions that eventually leads to a valid counter
state. It is not a matter how the counter starts up, but it eventually enters the proper counter sequence after very
short time.
Figure 8.107(a) shows the state transition diagram of a typical self-starting counter. In this state
transition diagram, the counter should be in sequence after one transition. Fig. 8.107(b) shows the
alternative state transition diagram. In this diagram, counter may require either two transitions or one
transition before entering into the correct sequence. During design, it is necessary to select the counter
sequence as few transitions as possible. Therefore, Fig. 8.107(a) is used for hardware implementation.
As shown in Fig. 8.107(a), the counting sequence is 000→001→011→100→101→000. If at starting
initial count value is either 111 or 110 or 010, then self correcting capability has been added after
incorporating the unused states in counter design. If present state is 111 or 110 then, next transition will
be 000. When present state is 010 then next state transition is 011. When this counter is designed with
D flip-flops, the excitation of D
flip-fops will be the next state.
Flip-flops excitation for self-
start counter is given in Table
8.32. The state transition Table
8.32 is represented by K-maps as
shown in Fig. 8.108(a), (b) and
(c). The excitation function of D
–– – –
flip-flops are D0 = A B + B C +
–– –– – –
A C , D1 = A B C + A BC , and D3 =
– ––
A BC + AB C where A=Q2, B=Q1,
C=Q0. The implementation of
the self-start and self-correcting
counter is shown in Fig. 8.109.
Fig. 8.109 Self-starting counter
In some applications of coun-
ters, self initialisation is an
advantage. It eliminates the need for complex initialisation and guarantees the return to the original state
sequence after a temporary wrong state. The low operating frequency and large areas of the available self-
correcting counters have limitations. Due to the additional hardware required to change state transitions,
the final circuit tends to be slow and large. The self-starting and self-correcting counters have maximum
10 stages.
 344 Digital Electronics: Principles and Applications

Table 8.32 Flip-flops excitation for self start counter

Clock Preset state Next state Flip-flop inputs
pulse FF2 FF1 FF0
CLK Q2 Q1 Q0 Q2 Q1 Q0 D2 D1 D0
A B C A B C
0 0 0 0 0 0 1 0 0 1
1 0 0 1 0 1 1 0 1 1
2 0 1 0 0 1 1 0 1 1
3 0 1 1 1 0 0 1 0 0
4 1 0 0 1 0 1 1 0 1
1 0 1 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0 0

8.34 COUNTER APPLICATIONS

Digital counters are very useful and versatile devices. These devices have many applications such as
frequency measurement, time period measurement, digital clocks, decimal counter, electric organ,
rhythm generators, Atomic clocks, master clocks and world clocks, etc. In this section, only application
of counters in frequency measurement, time period measurement, digital clocks are discussed.
8.34.1 Frequency Measurement Using Counter
The basic block diagram of frequency measurement using counter is shown in Fig. 8.110. The counter
is driven by the output of an AND gate. The AND gate inputs are a known frequency sample pulse and
an unknown frequency signal whose frequency will be measured. When the sample pulse is high, then
only unknown frequency signal are allowed to pass through the AND gate and output of AND gate
is fed into the counter. Then counter counts number of pulses during time interval t1 to t2 as shown in
Fig. 8.111.

Fig. 8.110 Frequency measure- Fig. 8.111 Principle of frequency measure-

ment using counter ment using counter

The counter starts counting at t1 time and the counter stops counting at t2. Thus, the counter counts
the number of pulses that occur during the sampling interval. This is a direct measure of the frequency
of the pulse waveform. Usually, the counter is made by cascaded BCD counters, the decoder and seven
segment display units. The decoder converts the BCD outputs into seven segment form and display in
 Sequential Circuits 345

segment display units.

In this way, the frequency
of a signal is measured. In
this method, frequency mea-
surement is not accurate as
accuracy depends almost en-
tirely on the duration of the
sampling interval, which must
be very accurately controlled.
The most commonly used fre-
quency measurement scheme
Fig. 8.112 Frequency measurement scheme using accurate sam- is shown in Fig. 8.112. This
pling intervals and counter
scheme is very accurate as
crystal controlled oscillator is used to generate a very accurate 100 kHz waveform, which is shaped into
square pulses and fed to a series of decade counters that are being used to successively divide this 100
kHz frequency by 10. The frequencies at the output of each decade counter are as accurate as the crystal
frequency. These decade counters are usually binary counters. The switch is used to select one of the
decade counter output frequencies to be fed to the clock input of a single flip-flop to be divided by 2.

8.34.2 Measurement of Time Period

Using the principle of frequency measurement using counter, the time period of any signal can be
measured. Fig. 8.113 shows the basic block diagram of time period measurement using counter. The
most accurate crystal controlled oscillator 1 MHz reference frequency is applied the AND gate through
a pulse shaper circuit. Input signal is also applied to clock terminal of J-K flip-flops. The output of J-K
flip-flop is for a clock period of input signal. Then known fixed frequency signal passes through AND
gate for time interval Tx only. The output of AND gate is connected with a counter. The counter counts
the fixed frequency signal for the time interval. Then the time period can be measured in terms of count
value and display it in seven segment display section.

Fig. 8.113 Time period measurement using counter

8.34.3 Digital Clocks

The most common application of counters is digital clock. Any digital clock displays the time of day in
hours, minutes and seconds. To construct an accurate digital clock, a very highly controlled basic clock
frequency is required. Generally, a quartz-crystal oscillator is used to generate the basic frequency for
battery-operated digital clocks. Digital Clocks operated from the ac power supply, and then the 50 Hz
 346 Digital Electronics: Principles and Applications

power frequency is uses as the basic clock frequency. In both case, the basic frequency has to be divided
down to a frequency of 1 Hz or pulse of 1 second (pps). The basic block diagram for a digital clock is
shown in Fig. 8.114.
The 50 Hz signal is passes through a pulse shaper circuit to produce square pulses at the rate of
50 pps. Then, 50 pps square waveform is fed into a MOD-50 counter to generate a 1 pps signal. The
1-pps signal is then fed into the SECONDS section. In this section, BCD and MOD-6 counters are
used to count seconds and display seconds from 00 to 59. After counting 60 seconds, the MOD-6
counter generates 1 pulse/minutes and again starts second cycle counting. In minutes section, BCD
and MOD-6 counters are used to count minutes and display seconds from 00 to 59. After counting 60
minutes, MOD-6 counter of minute section sends a pulse, i.e., 1pulse/hour to the hour section. The
Hour section BCD and MOD-2 counters count hours and display 00 to 12. After complete one cycle
operation, the next cycle operation will be started. Hence, Hours, Minutes and Seconds are displayed
in Hour section, Minutes section and Seconds section respectively.

Fig. 8.114 Block diagram of Digital Clocks

 Sequential Circuits 347

SUMMARY
Shift registers are storage devices and used for storing binary data. JK, D and SR flip-flops can construct shift registers.
In shift register, several flip-flops can be cascaded together and are driven by a common clock. In ‘n’ bit shift register,
‘n’ flip-flops are required. In this chapter, four basic types of shift registers: Serial In-Parallel Out, Serial In- Serial Out,
Parallel In-Parallel Out, Serial In- Parallel Out are discussed with examples and ICs. A bi-directional shift register can
move data internally in either left or right direction. In a universal shift register, data can be entered/loaded in serial
and parallel, and data can also be out in serial and parallel. The bi-directional and universal shift register ICs are also
incorporated in this chapter. The Ring and Johnson shift counters are two specialized shift registers used to create
sequential outputs. The Ring counter has ‘n’ states in its sequence but the Johnson counter has ‘2n’ states, where n is
the number of stages.
Counter is a sequential circuit and it can be developed by using flip-flops. Generally, counter has a 2n counter states,
where ‘n’ is the number of flip-flops used in the counter. Counter of any value can be designed by skipping some states
from the natural count. For this feedback signals are taken from some flip-flops and then reset or clear all flip-flops.
In this chapter, operations of asynchronous (ripple) and synchronous counters are explained in detail. The design of
synchronous counters, mod-n counters, and cascade connection of counter are also incorporated. Some asynchronous
and synchronous counters ICs are also included for practical implementation. Cascaded counters, programmable
counters, self-starting and self-correcting counters and applications of counters are also discussed in this chapter.

MULTIPLE CHOICE QUESTIONS

1. Left shifting the contents of a shift register by one bit is equivalent to
(a) dividing the content by 2 (b) dividing the content by 10
(b) multiplying the content by 2 (d) multiplying the content by 10
2. Right shifting the contents of a shift register by one bit is equivalent to
(a) dividing the content by 2 (b) dividing the content by 10
(c) multiplying the content by 2 (d) multiplying the content by 10
3. A 4-bit PISO shift register will receive 4 bits of _____ data and data will shift by _____ position(s)
for each clock pulse.
(a) parallel, one (b) parallel, two (c) serial, one (d) serial, two
4. Parallel loading of the 4-bit register means
(a) left shifting the data in all four flip-flops simultaneously
(b) right shifting the data in all four flip-flops simultaneously
(c) loading data in two of the flip-flops
(d) loading data in all four flip-flops at the same time
5. A n bit shift register can not be used as
(a) module n counter (b) module 2n counter
(c) serial to parallel conversion (d) parallel to serial conversion
6. Generally shift register is constructed by using
(a) T flip-flops (b) D flip-flops (c) J K flip-flips (d) S R flip-flips
7. How many clock pulses are required to completely load serially a 8-bit shift register?
348 Digital Electronics: Principles and Applications

(a) 8 (b) 7 (c) 4 (d) 5

8. The universal shift register can be used as
(a) serial to parallel conversion (b) parallel to serial conversion
(c) serial to serial conversion (d) a, b and c
9. In a ________ shift register data is entered into register one bet at a time and all data outs at a
time
(a) SIPO (b) SISO (c) PISO (d) PIPO
–
10. In a 4-bit shift register, Q of the last flip-flop is connected with the J terminal of first flip-flop and Q
of the last flip-flop is connected with the J terminal of first flip-flop. The shift register acts as
(a) Ring counter (b) Binary counter (c) Shift register (d) None of these.
11. The data can be taken out of a SISO shift register from
(a) the Q output of the first FF. (b) the Q output of the last FF.
(c) all of the Q outputs together. (d) None of these
12. The data can be taken out of a PIPO shift register from
(a) the Q output of the first FF. (b) the Q output of the last FF.
(c) all of the Q outputs together. (d) None of these
13. By adding recirculating lines to a 4-bit Parallel-In, Serial-Out shift register, it becomes
(a) a Parallel-In, Serial and Parallel Out
(b) a Serial-In, Parallel and Serial Out
(c) a Series-Parallel-In, Series and Parallel Out
(d) a bidirectional In, Parallel and Series Out
14. The _________registers have a data is entered in one bit at a time and have all the stored bits shifted
out one bit at a time.
(a) Parallel-In and Parallel-Out (b) Parallel-In and Serial-Out
(c) Serial-In and Parallel-Out (d) Serial-In and Serial-Out
15. A sequence of equally spaced timing pulses may be easily generated by which type of counter cir-
cuit?
(a) Ring shift (b) clock (c) Johnson (d) binary
16. Ring shift and Johnson counters are:
(a) synchronous counters (b) asynchronous counters
(c) binary counters (d) a and c
17. What is the function of preset of a Ring shift counter?
(a) all FFs set to 1 (b) all FFs reset to 0
(c) one FF set to 1, others reset to 0 (d) one FF reset to 0, others set to 1
18. The difference between a Ring counter and a Johnson counter is
(a) Ring counter is faster. (b) The feedback is reversed.
(c) Johnson is faster (d) None of these
19. What is the name of shift register that will accept parallel or a bidirectional serial load and will out
data in parallel or bidirectional serial form?
(a) universal (b) SIPO (c) PISO (d) tristate
 Sequential Circuits 349

20. Why stepper motors are very popular in digital systems?.

(a) low cost
(b) driven by sequential digital signals
(c) can be able to provide repetitive mechanical movement
(d) b and c
21. The number of flip-flops are required for mod-5 counter
(a) 1 (b) 2 (c) 3 (d) 4
22. In design a counter circuit, the most commonly used flip-flop is
(a) D type (b) RS flip-flop (c) Latch (d) JK type
23. The minimum number of flip-flops required for a synchronous decade counter is
(a) 1 (b) 2 (c) 4 (d) 10
24. What is the modulus of 5-bit ripple counter
(a) 16 (b) 32 (c) 5 (d) 64
25. A twisted ring counter consisting of 6 flip-flops, will have
(a) 6 states (b) 12 states (c) 64 states (d) 128 states
26. A mod-2 counter, followed by a mod-5 counter is
(a) mod-5 counter followed by a mod-2 counter
(b) mod-11 counter
(c) mod-9 counter
(d) decade counter
27. A decade counter can be designed by
(a) 4 flip-flop and by pass 6 states (b) 10 flip-flops and by pass 10 states
( c) 4 flip-flop and by pass 5 states (d) 4 flip-flop and by pass 4 states
28. Three mod-5 counters are connected in cascaded. The overall modulus of circuit will be
(a) Mod-10 counter (b) mod-15 counter (c) Mod-125 counter (d) None of these
29. A 3-bit ripple counter will have the counting sequence as
(a) 000,001,010,011,100,101, 110, 111 (b) 000, 001, 011, 111
(c) 111, 110, 101, 100, 011,010, 001, 000 (d) none of these
30. Any sequential logic circuit consist of
(a) only flip-flops
(b) only gates
(c) flip-flops and combinational logic circuits
(d) only combinational logic circuits
31. The waveforms of a counter are shown in Fig. 8.115. This is a
(a) Ring counter (b) twisted ring counter
(c) ripple counter (d) synchronous BCD counter
350 Digital Electronics: Principles and Applications

Fig. 8.115

32. The preset input of a 4-bit preset able UP counter has 1010. The modulus of this counter is
(a) 5 (b) 10 (c) 11 (d) 15
33. The preset input of a 4-bit preset able DOWN counter has 1001. The modulus of this counter is
(a) 11 (b) 10 (c) 9 (d) 8
34. If 100KHz clock pulse is applied to mod-2 counter, the output frequency of symmetrical square
wave will be
(a) 200KHz (b) 100KHz (c) 50KHz (d) None of these
35. If time period of input clock pulse is 10µs, 50µs times period symmetrical square wave can be
generated from
(a) divide by 5
(b) divide by 10
(c) 3-bit binary counter
(d) cascade connection of mod-2 and mod-5
36. The waveforms of a counter are shown in Fig. 8.116. This is a
(a) Asynchronous counter (b) Johnson counter
(c) Ring (d) None of these

Fig. 8.116

37. The waveforms of a counter are shown in Fig. 8.117. This is a

(a) Asynchronous counter (b) Johnson counter
(c) Ring (d) None of these
 Sequential Circuits 351

Fig. 8.117

38. A 4-bit ripple counter requires

(a) 3 (b) 4 (c) 5 (d) 6 flip-flops
39. The minimum propagation delay is possible in
(a) Synchronous counter (b) Asynchronous counter
40. The maximum number of states of 4-bit synchronous counters
(a) 16 (b) 10 (c) 8 (d) 4

REVIEW QUESTIONS
8.1 What is shift register? What are the types of registers? Explain any one-shift register with example.
8.2 Explain the operation of bi-directional shift register with circuit diagram and waveforms.
8.3 What is universal register? Explain its operation.
8.4 Explain the operation of Ring counter with state diagram and waveforms.
8.5 Explain the operation of Johnson counter with state diagram and waveforms. What is difference
between Johnson and Ring counter.
8.6 Write the applications of shift register briefly.
8.7 What is serial data transfer and parallel data transfer? Explain the serial to parallel and parallel to
serial data conversion with circuit diagram.
8.8 Explain the operation of four stages and five stages twisted ring counter with circuit diagram, truth
table and timing diagram.
8.9 Draw the waveforms to enter a serial data 11101into a SIPO shift register.
8.10 Draw the logic circuit diagram of universal shift register and explain its operation with functional
table.
8.11 What is the largest hexadecimal number that can be stored in a ten flip-flops shift register?. Draw a
PIPO shift register which consists of six flip-flops.
8.12 Draw a logic circuit diagram of shift register to produce a 50µs delay and explain briefly.
8.13 Draw the waveform for 4-bit SIPO shift register as shown in Fig .8.118, when data input is 1101.

Fig. 8.118
 352 Digital Electronics: Principles and Applications

— ——
8.14 Draw the timing diagram of the shift register as shown in Fig. 8.119, when LEF T /RIGHT signal is
low for three clock pulses and high for three clock pulses. Consider QA=1, QB=0, and QC=1.

Fig. 8.119
8.15 Draw the output waveform of SISO shift register as shown in Fig. 8.120, serial data 10101011 ap-
plied in A and B is high.

Fig. 8.120
8.16 Show the timing diagram of 4-bit PISO shift register as depicted in Fig. 8.121, if input data is
1101.

Fig. 8.121
8.17 Explain the operation of counter circuit as shown in Fig. 8.122 with truth table and timing dia-
gram.

Fig. 8.122
 Sequential Circuits 353

8.18 Explain the operation of counter circuit as shown in Fig. 8.123 with truth table and timing dia-
gram.

Fig. 8.123
8.19 Draw the logic circuit diagram of a ten bit Ring counter. Show the timing diagram and explain
briefly.
8.20 Figure 8.124 shows the logic diagram of 74194. Explain how it will be used in (i) Serial Input Paral-
lel Output (ii) Parallel In Parallel Out (iii) shift left and (iv) shift right operation.

Fig. 8.124

8.21 Define counter. Explain classification of counter with example.

8.22 Write the count sequence of 3-bit binary ripple counter. Design a 3-bit ripple counter using J-K
flip-flops.
8.23 Draw the timing diagram of 4-bit asynchronous counter and explain briefly.
8.24 Design a 4-bit binary UP/DOWN ripple counter with a control input for UP/DOWN counting.
8.25 Figure 8.125 shows a ripple counter. Draw the timing diagram for first ten clock pulses.
 354 Digital Electronics: Principles and Applications

Fig. 8.125

8.26 Design a 4-bit asynchronous decade counter and draw the timing diagram.
8.27 Draw a logic diagram of 4-bit ripple counter and explain its operation with timing diagram and
sequence table. What modification is required to use as a decade counter.?
8.28 Figure 8.126 shows a asynchronous counter. Draw the waveform of output Q0, Q1 and Q2 outputs
with respect to clock.

Fig. 8.126

8.29 Design the following counters using 7493A.

(a) Divide by 2 (b) Divide by 8 (c) Divide by 16 (d) Divide by 10
8.30 Draw the timing diagram for the following asynchronous counters
(a) 4-bit binary up counter (b) 6 stage binary counter
8.31 What are the disadvantages of ripple counter? How these disadvantages are overcome in synchronous
counter?
8.32 Write the difference between the following counters
(a) Synchronous counter and asynchronous counter
(b) Binary UP and binary DOWN counter
(c) Decade counter and ripple counter
(d) Mod-5 and divide by 5 counters
8.33 Draw the timing diagram of 4-bit synchronous counter and explain with sequence table and logic
diagram.
8.34 Design a 4-bit synchronous UP/DOWN counter.
 Sequential Circuits 355

8.35 Figure 8.127 shows a synchronous counter. Draw the timing diagram for first eight clock pulses.

Fig. 8.127

8.36 Design a 4-bit synchronous decade counter and draw the timing diagram.
8.37 Design a 4-bit synchronous decade counter to count Excess-3 code sequence.
8.38 Design a synchronous decade counter using 74160.
8.39 Define mod ‘n’ counter. Design the following mod counters
(a) mod-5 (b) mod-10 (c) mod-15 (d) mod-12
8.40 Design a counter using JK flip-flops to generate the sequence as shown in Table 8.33.

Table 8.33

Clock pulse Q3 Q2 Q1 Q0
0 0 0 0 1
1 0 0 1 0
2 0 1 0 0
3 1 0 0 0

8.41 Determine the overall modulus of cascade connection of counters as given in (a), (b) & (c ) and also
determine the output frequency. Consider clock frequency is 10KHz

8.42 What is the difference between register and counter? Explain how shift register can be used as a
counter.
8.43 Design a synchronous mod-6 counter using JK flip-flops and draw the timing diagram of this coun-
ter.
8.44 Design the following synchronous counter
(a) divide by 7, (b) divide by 9, (c) divide by 11
8.45 A synchronous counter using JK flip-flops has the following connections
–
(i) In FF0, J = K = HIGH (ii) In FF1, J = K = Q0Q 3
(iii) In FF2, J = K = Q0 Q1 (iv) In FF3, J = K = Q0 Q1 Q2 + Q0Q3
Draw the above synchronous counter and determine its modulus and the count sequence.
 CHAPTER

9
SEQUENTIAL
CIRCUITS DESIGN
9.1 INTRODUCTION
The combinational logic circuits are a part of digital systems and they have many applications such
as decoder, encoder, adder, subtracter, multiplexer, demultiplexer, etc. But when the circuit output not
only depends on the present state but also the previous state, the circuit is known as sequential logic
circuit. Any sequential circuit consists of a combinational logic circuit and memory elements. The
output of combinational logic circuit is stored in memory elements. Memory elements output feedback
into combinational logic circuit and used as input variables. The output of combinational logic circuit
depends upon the external inputs and input from memory elements. A memory element is a device
which can store information in terms of ‘1’ or ‘0’ and its state can be modified by clock signal and data
inputs. A flip-flop is an one bit memory element, which can store ‘1’ or ‘0’. To store ‘n’ bit information,
‘n’ flip-flops are required. Generally, J-K, D and T flip-flops are used in memory elements. In this
chapter, different kinds of sequential logic circuits: synchronous sequential circuits and asynchronous
sequential circuits are discussed.
In fact, a sequential logic circuit is one way of building block of a sequential machine. In any
sequential machine, the output not only depends on the present input to the machine, but also it always
depends on the previous condition of the machine. Sequential machines can be considered as machines,
which have a well organised set of conditions. The conditions are called as states. Therefore, sequential
machines are also called as state machines. The transitions of the machine from one state to the next are
most frequently driven by a clock signal. When the machine is driven by clock signal, it is known as a
synchronous machine. If the machine is not clocked driven, the transitions from one state to the next
state can be decided by the change in input to the machine and it is known as asynchronous machine. As
input changes sequentially, the output of sequential machines may be repeated cyclically through a finite
set of states. Consequently, sequential machines are also called as finite state machines.
A finite state machine is the most general type of digital circuit whose outputs depend upon both
on the present input signals and on the previous input signals. Though the previous inputs of a finite
state machine control the present outputs indirectly by determining the internal state of the machine.
The internal state and the present inputs find out the present output signals. The examples of finite state
machines are latches and flip-flops, which are the simplest types of finite state machines and counters.
The sequential circuits have many applications in digital system design which consists of combinational
 Sequential Circuits Design 357

logic circuits as well as memory elements. Any logic family can be used in combinational logic circuit
and the memory element may be either D flip-flops or J-K flip-flops or T flip-flops. Generally, J-K flip-
flops are used for simpler circuit implementation. In this chapter, the design procedure of sequential
circuits has been discussed with examples.
9.2 SEQUENTIAL CIRCUIT MODEL
Figure 9.1 shows the model for a general sequential circuit which consists of combinational logic circuit
and memory elements. The combinational logic circuit has ‘n’ inputs I1 – In and ‘m’ outputs O1-Om. The
edge triggered flip-flops are used in memory elements. This sequential circuit is driven by a clock signal
and the output can be changed on either positive or negative edge of the clock pulse only.

Fig. 9.1 Block diagram of a general sequential circuit

The present state of the sequential circuit or finite state machine (FSM) is always stored in the
memory elements. Therefore, memory elements must be capable to store the information and to specify
the states of the machine. For example, a sequential circuit or a finite state machine might have four
states specified by the S0, S1, S2, and S3. S0 represents 00, S1 represents 01, S2 represents 10, and S3
represents 11. So that the memory elements can store codes 00, 01, 10 and 11 representing the four states
S0, S1, S2, and S3.
The next state of the finite state machine can be determined by the present state of the machine and by
the inputs. The combinational logic circuit is used to perform the logic operations based on the present
state of the machine and the input to the machine. Then the combinational logic circuit generates the next
state of the machine and fed into the memory. Then next state variables become present state variables and
stored in the memory. This method of changing states is known as a state change. The sequential machine
is a feedback system as the present state of the machine is fed back to the combinational logic circuit.
If there are ‘n’ flip-flops in the memory to store present state, there are 2n possible states. All 2n state are
stored or store only specified states which are needed and used in the design of the circuit. The state of the
circuit can only change on a transition of the clock signal either positive edge or negative edge only.
The output of the machine is determined by the present state of the machine and possibly by the input
to the machine. The output decoder performs the logic operations on the state of the machine and the
input to the machine to generate the output. In some cases, the output is simply the state of the machine
when there is no output decoder. But often the state must be converted into output signal using output
decoder. When the output is a function of the input signals, the input signals will certainly be converted
differently if different output decoder circuits are used for this purpose.
9.3 CLASSIFICATION OF SEQUENTIAL CIRCUITS
The sequential circuits or finite state machines (FSM) are classified depending upon the presence or
absence of a clock signal such as synchronous sequential circuit and asynchronous sequential circuit.
 358 Digital Electronics: Principles and Applications

When a sequential circuit is driven by a clock signal, it is called as synchronous sequential circuit. If
the circuit perform operations with out a clock signal, it is known as asynchronous sequential circuit.
This circuit can also be classified depending on the effect of the present inputs on the present outputs,
such as Moore machine and Melay machine. In Moore machine, the outputs depend directly only on
the state information. But in Melay machine, the outputs directly depend both on the preset inputs
and on the state information. Based on presence or absence of clock, the Moore machine is classified
as synchronous and asynchronous Moore machine. Similarly, the Melay machine is also classified as
synchronous and asynchronous Melay machine.
The behaviour of Moore machine is defined by the equations
Next state = F (Present state, Inputs)
Output = G (Present state)
The configuration of
synchronous and asyn-
chronous Moore machine
is shown in Fig. 9.2 and
Fig. 9.3 respectively. Sim-
ilarly, the behaviour of
Mealy machine is defined Fig. 9.2 Synchronous Moore machine
by the following equa-
tions.
Next state = F (Present state, Inputs)
Output = G (Present state, inputs)
The general structures of synchronous and asyn-
chronous Melay machine are shown in Fig. 9.4 and 9.5 Fig. 9.3 Asynchronous Moore machine
respectively.

Fig. 9.4 Synchronous Melay machine

Fig. 9.5 Asynchronous Melay machine

 Sequential Circuits Design 359

9.4 STATE TABLE

The time diagram of inputs, outputs and flip-flops states of sequence circuits may be listed in a state table.
For the analysis and design of sequential circuits, it is necessary to describe the state transitions of a state
machine in a present state, next state and output table. In this table all possible combinations of inputs and
present states, and the corresponding next state and output for each combination are listed in tabular form.
The state table for a typical sequence circuit is shown in Table 9.1. Assume the following four states
S0→00, S1→01, S2→10, and S3→11. After substituting the states, we obtain the state transition Table 9.2.
It is depicted in Table 9.1 that there are three sections designated as present state, next state and output.
The present state assigns the states of the flip-flops before the applying a clock pulse. The next state
assigns the states of the flip-flops after the application of the clock pulse. The output section shows the
values of the output variables for each combination inputs, present states and next states. The output and
the next state sections have two columns: one for X=0 and the other for X=1.
Table 9.1 State table
Next State Output
Present state
X=0 X=1 X=0 X=1
Q 1 Q0 Q1 Q0 Q1 Q 0 O O
S0 S0 S1 0 0
S1 S1 S3 0 0
S2 S2 S0 0 1
S3 S2 S3 0 0

Table 9.2 State transition table

Present state Next State Output
X=0 X=1 X=0 X=1
Q 1 Q0 Q1 Q0 Q1 Q0 O O
00 00 01 0 0
01 01 11 0 0
10 10 00 0 1
11 10 11 0 0
The analysis of the state table of a typical sequential circuit can be started from any arbitrary state.
Suppose we assume that the initial state is 00. When the present state is S0 or 00 (Q1= 0 and Q0= 0). When
X = 0, the next state output is unchanged means it is S0 state. Similarly, with Q1= 0, Q0= 0 and X = 1, we
find that the next state is S1 or 01(Q1= 0 and Q0= 1). The information about state changes is given in the
first row of the state table.
When the present state is S1 or 01, Q1= 0 and Q0=1. If X = 0, the next state out remain unchanged
means next state is in S1 state. But if X = 1, the next state output is S3 or 11(Q1 = 1 and Q0= 1). The
information is listed in the second row of the state table. In the same way, we can explain the other state
conditions of the state table.
The state table of any sequential circuit can be written by the same procedure. In general, if a sequential
circuit consists of ‘n’ flip-flops and ‘m’ input variables, there will be 2n rows, one for each state. The next
state and output sections should have 2m columns, one for each combination.
9.5 STATE DIAGRAM
The most convenient method to describe any sequential circuit or finite state machine is a state transition
diagram. This is a graphical approach of representing how the finite state machine changes from one
 360 Digital Electronics: Principles and Applications

state to another state. This is also used to depict the output

generated by the finite state machine.
When the information available in the state table is
represented by graphical form, the diagram is known as
state diagram or state transition diagram. The state transition
diagram contains the same information about the transitions
of a state machine which is represented in tabular form. Each
row of the table is directly represented in the state diagram
by considering the inputs and present state to determine the
next state and output.
Figure 9.6 is an example of a state transition diagram for a
synchronous machine in which the transitions are controlled
by a clock. The circle represents the states of the sequential
circuit. The state identification is written within each circle.
In this diagram, there are four states, which are levelled S0,
S1, S2 and S3. Assume the following four states represented by Fig. 9.6 State diagram
binary code S0→00, S1→01, S2→10, and S3→11 respectively.
The transitions between the states are represented by lines with arrows to indicate their directions.
Some of the transitions do not change the states, such as the ones above state S0, above state S1, above
state S2 and also above state S3. All of the transitions in this synchronous machine are controlled by clock
pulse and are written next to the direct arrows representing the transition.
The direct arrows are labelled with two binary numbers, which are separated by a ‘/’. The number
before the ‘/’ stands for the value of the input which changes the state transition. The number after the ‘/’
represents the value of the output during the present state. For example, the direct arrow from the state
00 to 01 represents that the state of sequential circuit changes from 00 state to the next state 01 while
X/Y=1/0. Here X stands for input and Y represents output. When X=1 and after application of the clock
pulse, the state of sequential circuit changes to the next state 01 and output will be 0.
Consequently, if the state of a sequential circuit is known at a time t0, and the inputs are known from time
t0 to time t1, then the state of the sequential circuit can be found at a time t1 from state diagram directly.
Actually, there is no difference between a state table and a state diagram except the way of
representation. When a state diagram of any sequential circuit is given, we can easily develop the state
table from the given state logic diagram. Therefore state diagram directly follows the state table as
illustrated in Table 9.3. The state diagram represents the practical form of the state transitions and so it
is very easy to understand the state diagram.

Table 9.3 State table of state diagram

Present state Next State Output, Y
X=0 X=1 X=0 X=1
AB AB AB O O
00 00 01 0 0
01 10 01 0 0
10 11 10 1 0
11 11 00 0 0
 Sequential Circuits Design 361

9.6 STATE EQUATION

The state equation of a sequential circuit is a boolean expression which represents the conditions of
flip-flop state transition. The state equation can be derived directly from the state table. For example, to
design the sequential circuit as per Table 9.3, the next state of the flip-flop must be derived from inputs,
and present state. From the next state columns of State Table 9.3, we observe that the flip-flop A changes
its state four times: when X = 0 and AB = 01 or 10 or 11 and when X = 1 and AB = 10. Assume the state
of a sequential circuit is known at a time t0, and the inputs are known from time t0 to time t1, then the
state of the sequential circuit can be derived at t1. The change of state can be expressed algebraically in
a state equation as follows:
– – –– – – – – – – –
A(t1) = A BX + AB X + ABX + AB X = A BX + AB (X + X) + ABX
– – – – – – – –
= (A + A)BX + AB (X + X) = BX + AB As (A + A) = (X + X) = 1
Similarly, we find that the flip-flop B goes to 1 state four times: when X = 0 and AB = 10 or AB = 11 and
when X = 1 and AB = 00 or AB=01. This change can also be expressed algebraically in a state equation
as follows: –– – –– – – – – ––
B(t1) = AB X + ABX + A B X + AB X = AB (X + X) + ABX + A B X
– – –– –
= AB + ABX + A B X As (X + X) = 1

9.7 DESIGN PROCEDURE OF SYNCHRONOUS SEQUENTIAL

CIRCUITS
For the design of a sequential circuit having limited number of inputs and outputs, the analysis of
sequential circuit is required. The analysis of sequential circuits, such as operation of different types of
counters is already explained in Chapter 8. The design procedure of any sequential circuit follows the
steps given below:
Step-1 Define the problem with specification.
Step 2 Draw a block diagram for the proposed design with all the inputs and the required outputs.
Step-3 Make a state transition diagram from the specification. Generally, this is the most difficult
part of any sequential circuit design.
Setp-4 Using the state diagram, construct a state table and check for redundant states.
Step-5 Rebuild the state diagram if redundancy has occurred.
Step-6 Make a state assignment.
Step-7 Draw a new state table after removing all redundancies and using the state assignment.
Step-8 Select the flip-flops D or T or J-K which one will be used in memory elements.
Step-9 Derive the excitation equations for the next state inputs to the selected flip-flops with the
help of the reduced state table. Derive the output equations of sequential circuit.
Step-10 Implement the excitation equations and the output equations with the help of logic gates
and flip-flops.
Specification of Sequential Circuit The specification of any sequential circuit consists of
some verbal statements of the problem which is the detailed information about the inputs available and
the required outputs. The specification of the problem is an unambiguous term as it does not state the
very simple relationship between inputs and outputs. Before design a circuit, several discussions between
designer and user are required to resolve the ambiguities. After getting the complete information about
the circuit, designer should start the process of design and implement the circuit properly.
 362 Digital Electronics: Principles and Applications

Block Diagram and Timing Diagram of Sequential Circuit After the detailed
study of the problem specification, designer should construct a block diagram showing all the inputs
and the required outputs. In addition, draw a timing diagram of sequential circuit which represents the
outputs of the specified problem.
The State Diagram The verbal statements of the problem should be expressed in terms of the
internal states of the circuit and draw a state diagram representing all internal states. There are no defined
rules for constructing state diagrams, but it is the ability of the designer which can only be acquired by
experience. For example, we assume the following verbal statements of the problem:
“A sequential logic circuit receives input data serially on an input line. The input data is synchronised
with an external clock signal. When the following combinations 010, 011, 110 and 111 are detected, a 1
will appear at the output. The output must occur when the third bit of the string is present and the third
clock pulse is high”.
Generally, the innovative and inexperienced designer can develop the tree-like structure of the states
as shown in Fig.9.7. Here, the method of approach is that the designer selected a state S0 arbitrarily.
This internal state of the circuit may have a pair of transition paths: one in the left side and other in the
right side. The left side movement or right side movement is selected by the transition signal X. When
the transition signal X=1, internal state change from S0 to S1. If the transition signal X=0, internal state
change from S0 to S2.
Again each of the states S1 and S2 may have a pair of transition paths: one in the left side and other in
the right side. Depending upon the value of the transition signal X, there will be four paths lead to the
four different states S3, S4, S5 and S6 as depicted in Fig. 9.7. In the same way, each of these four states
S3, S4, S5 and S6 has two different paths, but the next transition is that all left and right exist paths return
back to the starting state.

Fig. 9.7 State diagram

The combinations 111 and 110 follow the path S0 S1 S3 S0 through the state diagram as shown in Fig. 9.7
and the output O=1 in state S3. In the same way, the combinations 010 and 011 follow the path S0 S2 S5 S0
through the state diagram and the output O=1 in the state S5. Then remaining two paths of the state diagram
are related with those combinations which are not required to detect.
State Table Corresponding to the state diagram as shown in Fig. 9.7, the state table is developed
and it is depicted in Table 9.4. In this table, each row represents the state of the circuit and each column
stands for every combination of the input signals. Here, there is only one input signal X. Therefore, there
are only two columns in the next state: one for X = 1 and other for X = 0. The next state of the circuit is
 Sequential Circuits Design 363

Table 9.4 State table of Fig. 9.7 Table 9.5 Reduced state table
Present Next state Present Next state
state X=0 X=1 state X= 0 X=1
S0 S2 S1 S0 S2 S1
Output O = 0 Output O = 0 Output O = 0 Output O = 0
S1 S4 S3 S1 S46 S35
Output O = 0 Output O = 0 Output O = 0 Output O = 0
S2 S6 S5 S2 S46 S35
Output O = 0 Output O = 0 Output O = 0 Output O = 0
S3 S0 S0 S35 S0 S0
Output O = 1 Output O = 1 Output O = 1 Output O = 1
S4 S0 S0 S46 S0 S0
Output O = 0 Output O = 0 Output O = 0 Output O = 0
S5 S0 S0 entered in the each of the cells which are produced by the
Output O = 1 Output O = 1
intersection of the rows and columns. The output O of
S6 S0 S0
Output O = 0 Output O = 0
each state is also entered into the cell. For example, when
X = 0 and present is S0, the next state is S2 and output is
0. Similarly, if X = 1 when present state is S0, the next state is S1 and output is 0. In the same way, other
states and outputs are entered in the cells.
State Reduction When large numbers of states are present in the state diagram, the more hardware
is required for the circuit implementation. Therefore, it is required to reduce the number of states if pos-
Table 9.6 Minimal state table sible. The process of the state reduction in sequential
Present Next state circuit design means that the process which can be used
state X=0 X=1 to minimise the combinational logic circuit design.
S0 S12 S12 Usually, the state reduction is done by using Caldwell’s
Output O = 0 Output O = 0 merging procedure which depends upon two equivalent
S12 S46 S35 states. Equivalence of states can be defined by the fol-
Output O = 0 Output O = 0 lowing statements:
S35 S0 S0 “Two states Sp and Sq are equivalent if both have
Output O = 1 Output O = 1
the same next states and both have equal outputs”. It is
S46 S0 S0
Output O = 0 Output O = 0 depicted in Table 9.4 that the rows headed S4 and S6 and
the rows headed S3 and S5 satisfy the above definition
of equivalence of states. Consequently, states S4 and S6
have been merged, the state formed is represented by S46. Whenever
S4 and S6 appear in the table, they are replaced by S46. In the same
way, S3 and S5 are merged and from an equivalent state S35 which
replaces S3 and S5 wherever S3 and S5 appear in the state table. The
reduced state table is shown in Table 9.5. After getting the reduced
table, the designer should try to find out the minimal state table.
For this, again use Caldwell’s merging procedure in the reduced
stable table. It is clear from Table 9.5 that the two rows S1 and S2
are equivalent and can be merged to form the equivalent S12. Then
S12 replaces S1 and S2 wherever S1 and S2 appear in Table 9.6. After
Fig. 9.8 Reduced state diagram that no further reduction is possible. Then the reduced state diagram
can be constructed from the minimal reduced state table. Figure 9.8 shows the reduced state diagram.
 364 Digital Electronics: Principles and Applications

State Assignment After getting the minimum state table, the next step is that the designer should
choose secondary variables properly to locate the variables states. The required numbers of secondary
variables are determined by the total number of states in the reduced state diagram. It is depicted in Fig. 9.8
that there are four states. Therefore, two secondary variables are required to define each state uniquely.
The number of secondary variables which are used to define all states of reduced state diagram is
equal to the number of flip-flops required to implement the sequential circuit. As there are four states
and two secondary variables A and B are required to describe all four states, only two flip-flops are
required to implement the circuit.
Table 9.7 Revised state table of state diagram
Revised State Table Table 9.7 shows
Present Next State Flip-Flop inputs Output
the revised state table of reduced state diagram
state X = 0 X = 1 X=0 X=1 O
as shown in Fig. 9.8 in terms of the secondary AB AB AB D1 D 0 D1 D0
variables A and B. In this table, every possible
00 01 01 0 1 0 1 0
transition of the secondary variables for both 01 10 11 1 0 1 1 0
X = 0 and X = 1 is presented. 10 00 00 0 0 0 0 0
11 00 00 0 0 0 0 1
Flip-Flop Selection To implement the
sequential circuit, the designer should choose any one of the following flip-flops: D, J-K and T flip-flops.
Here, D flip-flops have been selected to implement the next state equations.
The Next State Equations To determine the next state equations, initially we represent the
required inputs of D flip-flops for every transition in the state table. After that, the D-inputs for the
various transitions are mapped on the K - map and find the simplified boolean functions. Figures 9.9(a)
and.9.9(b) show the K-map of D1 and D0 flip-flops respectively. From the K-map for D1 and D0, the next
state equations are derived as follows:

(a) (b)
– –– –
Fig. 9.9 (a) Three variables K-map D1 = A B (b) Three variables K-map D0 = A B + XA

– – –– –
D1 = A B D1 = A B D0 = A B + XA

Output Equations A last column in the

state table as shown in Table 9.7 is the output O.
The output O=1, when A=1 B=1. Then the output
equation is O = AB. If the entry in the state depends
on clock pulse then the output should be written as
O=A.B.CLOCK. The implementation of sequential Fig. 9.10 Implementation of sequential circuit
circuit using D flip-flops is shown in Fig. 9.10. using logic gates and D flif-flops
 Sequential Circuits Design 365

Example 9.1 Design a sequential circuit (finite state machine) for Table 9.8 using D flip-flops.
Assume two inputs are A and B, outputs of the sequential circuit are outputs of D
flip-flops, present state =S, Next State=S*. Consider the four states of the sequential
circuit are S0=00, S1=01, S2=10 and S3=11.
Table 9.8
� Solution
After substituting the following four states S0→00, S1→01, S2→10, and S3→11 in Inputs (AB)
Table 9.8, we get the state transition Table 9.9. As the state information is two bits, Present 00 01 10 11
two flip-flops are required. Q1 and Q0 are the output signals of two flip-flops. Then state (S)
present state of flip-flops are Q1 and Q0 and the next state of flip-flops are Q1* and S0 S1 S0 S0 S1
Q0*. When the memory element of the sequential circuit (finite state machine) is S1 S2 S0 S0 S2
implemented with D-type flip-flops, then the excitation table of the D flip-flops is S2 S3 S0 S0 S3
shown in Table 9.10. S3 S1 S0 S0 S1
Next State (S*)
Table 9.9 The state transition table Table 9.10 The excitation table of D flip-flops
Inputs (AB) Inputs (AB)
Present state 00 01 10 11 Present state 00 01 10 11
(Q1Q0) (Q1Q0)
00 01 00 00 01 00 01 00 00 01
01 10 00 00 10 01 10 00 00 10
10 11 00 00 11 10 11 00 00 11
11 01 00 00 01 11 01 00 00 01
Next State (Q1* Q0*) Inputs of flip-flops D1 D0

Two K-maps can be drawn from the excitation Table 9.10. Figure 9.11 shows the K-map for D1 and D0.
Based on the K-map as shown in Fig. 9.11, the following excitation equations can be derived.

Fig. 9.11 K-map for D1 and D0

—–– — –– — — –——
D1 = Q1* = QQ0A B + Q1Q0A B + Q1Q0AB + Q1Q0AB = (A B ) (Q1  Q0)
–– ––— — –—— —
D0 = Q0* = A B Q1 + ABQ1 + A B Q0 + ABQ0 = (A B ) (Q1  Q 0)
The implementation of the sequential circuit using D flip-flops and combinational logic circuit elements is
shown in Fig. 9.12.
 366 Digital Electronics: Principles and Applications

Fig. 9.12 Implementation of sequential circuit using D-flip-flops

Example 9.2 The state diagram of a sequential circuit is given in Fig. 9.13. Draw the state table for
Fig. 9.13. Assume two inputs are A and B, output is O.

Fig. 9.13 State diagram of a typical sequential circuit

� Solution
It is depicted in Fig.9.13 that there are four states of the sequential circuit S0, S1, S2 and S3, and two inputs A
and B. The state table of state diagram as depicted in Fig. 9.13 is shown in Table 9.11 representing present
state, next state and inputs. When S0= 00, S1= 01, S2= 10 and S3= 11 are inserted in the Table 9.11 and output
is also incorporated in this table, we get the complete state transition table as shown in Table 9.12.

Table 9.11 State table Table 9.12 State table with output
Inputs (AB) Inputs (AB)
Present state 00 01 10 11 Present state 00 01 10 11
(S) (Q1Q0)
S0 S1 S0 S0 S1 00 01/1 00/1 00/1 01/1
S1 S2 S0 S0 S2 01 10/0 00/0 00/0 10/0
S2 S3 S0 S0 S3 10 11/0 00/0 00/0 11/0
S3 S1 S0 S0 S1 11 01/1 00/1 00/1 01/1
Next State ( S*) Next State (Q1* Q0*)/Output(O)
 Sequential Circuits Design 367

Example 9.3 Design a sequential circuit for the state Table 9.13 using D flip-flops. Assume two
inputs are A and B, output of the sequential circuit is O, present state of D flip-flops
= Q1 Q0, Next State of D flip-flops = (Q1* Q0*).
Table 9.13
Inputs (AB)
Present 00 01 10 11
state(Q1Q0)
00 01/0 00/0 00/0 01/0
01 10/1 00/1 00/1 10/1
10 11/0 00/0 00/0 11/0
11 01/1 00/1 00/1 01/1
Next State (Q1* Q0*)/Output(O)
� Solution
As the memory element of the sequential circuit is implemented with D-type flip-flops, then the excitation table
of the D flip-flops is given in Table 9.14. The K-map for D1 and D0 is shown in Fig. 9.11. Based on the K-map
as shown in Fig. 9.11, the excitation equations of D1 and D0 flip-flops can be derived as given below:
—–– — –– — — –——
D1 = Q1* = QQ0A B + Q1Q0A B + Q1Q0AB + Q1Q0AB = (A B ) (Q1  Q0)
–– ––— — –—— –
D0 = Q0* = A B Q1 + ABQ1 + A B Q0 + ABQ0 = (A B ) (Q1 + Q0)
As output depends on the current state only, this sequential circuit is a synchronous Moore machine. The
—
output function O can be easily determined as Q1Q0 + Q1Q0. The implementation of the sequential circuit
using D flip-flops and combinational logic circuit elements is shown in Fig. 9.14.
Table 9.14 The excitation table of D flip-flops
Inputs (AB)
Present state 00 01 10 11
(Q1Q0)
00 01/0 00/0 00/0 01/0
01 10/1 00/1 00/1 10/1
10 11/0 00/0 00/0 11/0
11 01/1 00/1 00/1 01/1
Inputs of flip-flops (D1 D0 )/ Output(O)

Fig. 9.14 Implementation of sequential circuit using D flip-flops

 368 Digital Electronics: Principles and Applications

Example 9.4 Design a finite state machine for the state Table 9.15 using T flip-flops.
� Solution Table 9.15 The state table
When Table 9.15 is implemented by T flip-flops instead of Inputs (AB)
D flip-flops, the excitation table will be different. Table 9.16 Present state 00 01 10 11
shows the excitation table when the finite state machine is (Q1Q0)
implemented by using two T flip-flops. Construct the K- 00 01 00 00 01
map for the excitation Table 9.16 and derive the minimised 01 10 00 00 10
10 11 00 00 11
boolean function from the K-map as shown in Fig. 9.15. The
11 01 00 00 01
minimised Boolean excitation functions of T flip-flops are Next State (Q1* Q0*)
as follows:
–– – – Table 9.16 The excitation table of T
T1= Q1Q0 + A B Q0 + A BQ1 + ABQ0 + AB Q1 flip-flops
––
= Q1Q0 + A B Q0 + (A  B)Q1 + ABQ0
— – – — –– — — — – – Inputs (AB)
T0= Q1Q0 + A B Q 1 + A B Q 0 + ABQ 1 + ABQ 0 + A BQ0 + AB Q0 Present state 00 01 10 11
— ––— — –– — — – –
= Q1Q0 + A B Q 1 + ABQ 1 + A B Q 0 + ABQ 0 + A BQ0 + AB Q0 (Q Q )
— –– — –– — – – 1 0
= Q1Q0 + (A B + AB)Q 1 + (A B + AB)Q 0 + (A B + AB )Q0 00 01 00 00 01
— –—— — –—— —
= Q1Q0 + (A B ) Q 1 + (A B ) Q 0 + (A  B)Q0 01 11 01 01 11
— –—— — —
= Q1Q0 + (A B ) (Q 1 + Q 0) + (A  B)Q0 10 01 10 10 01
The implementation of the sequential circuit using T flip-flops 11 10 11 11 10
Inputs of Flip-flops T1 T0
and combinational logic circuit elements is shown in Fig. 9.16.

Fig. 9.15 K- map of the transition Table.5.16 for T1 and T0

Fig. 9.16 Implementation of sequential circuit using T flip-flops

 Sequential Circuits Design 369

Example 9.5 Design a finite state machine for the state Table 9.17 using J-K flip-flops.

� Solution
When J-K flip flops are used to implement the Table 9.17, the excitation table consists of four bits in each
cell as there are two inputs of each J-K flip-flops. Table 9.18 shows the excitation table when the finite state
machine is implemented by using two J-K flip-flops. Construct the K-map for the excitation table as shown
in Fig. 9.17 and derive the minimised excitation function. The excitation functions of the sequential circuit
are as follows:
–——
J1 = A B Q0 K1 = (A  B) + Q0
–—— —
J0 = (A B ) K0 = A  B + Q1
The implementation of the sequential circuit using J-K flip-flops and combinational logic circuit elements
is shown in Fig. 9.18.
Table 9.17 The state table Table 9.18 The excitation table of JK flip-flops

Inputs (AB) Inputs (AB)

Present state 00 01 10 11 Present state 00 01 10 11
(Q1Q0) (Q1Q0)
00 01 00 00 01 00 0X 1X 0X 0X 0X 0X 0X 1X
01 10 00 00 10 01 1X X1 0X X1 0X X1 1X X1
10 11 00 00 11 10 X0 1X X1 0X X1 0X X0 1X
11 01 00 00 01 11 X1 X0 X1 X1 X1 X1 X1 X0
Next State (Q1* Q0*) Inputs of flip-flops J1 K1 J0 K0

Fig. 9.17 K-map of the transition Table.5.18

 370 Digital Electronics: Principles and Applications

Fig. 9.18 Implementation of sequential circuit J-K flip-flops

Example 9.6 Design a up-down counter for the State diagram 9.19 using T-flip-flops. Assume ‘En’
stands for counter enable and ‘dir’ represents direction of up-down counter. Consider
four states S0=00, S1=01, S2=10 and S3=11 and two outputs O1 and O0.

Fig. 9.19
� Solution
Consider A=‘En’ stands for counter enable and B=‘dir’ represents direction of up-down counter. The memory
element of sequential circuit consists of two T flip-flops and the sate transition table is given in Table 9.19.
The excitation Table is illustrated in Table 9.20. The K-map for the excitation table is shown in Fig. 9.20.
Then the excitation functions are as follows
–— –—
T1 = ABQ0 + AB Q0 = A(BQ0 + B Q0) = A B  Q0
T0 = A
Based on the output table as given in Table 9.21, the output functions are
O1 = AQ1
O0 = AQ0
The implementation of the sequential circuit using T-flip-flops and combinational logic circuit elements is
shown in Fig. 9.21.
 Sequential Circuits Design 371

Table 9.19 The state table Table 9.20 The excitation table of T-flip-flops
Inputs (AB) Inputs (AB)
Present state 00 01 10 11
Present state (Q1Q0) 00 01 10 11
(Q1Q0)
00 00 00 11 01 00 00 00 11 01
01 01 01 00 10 01 00 00 01 11
10 10 10 01 11 10 00 00 11 01
11 11 11 10 00
Next State (Q1* Q0*) 11 00 00 01 11
Inputs of flip-flops T1 T0

Fig. 9.20 K-map of the transition Table.5.20 for T1 and T0

Table 9.21 State transition table with outputs

Inputs (AB)
Present state 00 01 10 11
(Q1Q0)
00 00/00 00/00 11/11 01/01
01 01/00 01/00 00/00 10/10
10 10/00 10/00 01/01 11/11
11 11/00 11/00 10/10 00/00
Next State(Q1* Q0*)/Output(O1,O0)
Fig. 9.21 Implementation of sequential circuit
J-K flip-flops

Example 9.7 Implement the State Table 9.22 using D flip flops

Table 9.22
Present Next state Flip-flop inputs Output
state X=0 X=1 X=0 X=1
AB AB AB D1 D0 D1 D0 O
00 01 01 0 1 0 1 1
01 10 11 1 0 1 1 1
10 00 00 0 0 0 0 1
11 00 00 0 0 0 0 0
 372 Digital Electronics: Principles and Applications

� Solution
Initially we construct the K-map of Table 9.22 and derive the excitation functions of D flip-flop inputs D1 and
D0. Fig.9.22 shows the K-map of the excitation Table 9.22. The minimised Boolean functions are obtained
form Fig.9.22 as follows
–
D1 = A B
–– –
D0 = A B + XA
––
The output equation is A B . The implementation of the sequential circuit using D flip-flops and combinational
logic circuit elements is shown in Fig. 9.23.

(a) (b)
– –– –
Fig. 9.22 (a) Three variables K-map D1 = AB (b) Three variables K-map D0 = AB + XA

Fig. 9.23 Implementation of sequential circuit using D flip-flops

Example 9.8 Design a sequence detector as per State Table 9.23 and implement using D flip flops.

Table 9.23 State Table

Present state Next state Flip-flop inputs Output

X=0 X=1 X=0 X=1 X=0 X=1
AB AB AB D1 D0 D1 D0 O1 O0
00 00 01 0 0 0 1 1 0
01 11 01 1 1 0 1 0 0
10 11 01 1 1 0 1 0 0
11 00 10 0 0 1 0 0 1
 Sequential Circuits Design 373

� Solution
Draw the K-map of Table 9.23 and derive the excitation function of D flip-flop inputs D1 and D0. Fig. 9.24
shows the K-map of the excitation Table 9.23. The minimised Boolean functions are obtained as follows
–– – –
D1 = X A B + X AB + XAB
– – –
D0 = XA + AB + AB
––
The output equations are O1 = A B and O0 = AB. The implementation of the sequence detector circuit using
D flip-flops and combinational logic circuit elements is shown in Fig.9.25.

Fig. 9.24 (a) Three variables K-map Fig. 9.24 (b) Three variables K-map
–– – – – – –
D1 = X A B + X AB + XAB D0 = XA + AB + AB

Fig. 9.25 Implementation of sequence detector circuit using D flip-flops

 374 Digital Electronics: Principles and Applications

9.8 STATE REDUCTION OF SYNCHRONOUS SEQUENTIAL CIRCUITS

Usually synchronous sequential circuits are represented by state table and state diagram. When the state
table is directly used to implement the sequential circuit, more hardware is required. To reduce the hardware
requirement, the sequential circuit must be optimised by state reduction. There are three different methods of
state reduction to find equivalent states of any specified state table. These methods are inspection, partitioning
and implication table. The method of state reducing using inspection is already explained in Section 9.7. In
this method, the two states Sm and Sn will be equivalent if and only if, each possible input sequence produces
identical output sequence irrespective of initial state whether Sm or Sn. For this, all possible input sequences
are represented in tabular from incorporating all corresponding output sequences of the sequential circuit.
This method will be very tedious when the circuit consists of large number of input signals and very large
number of states. Consequently, the other two methods, such as partitioning and implication table are used
as these methods are simple and non-tedious for state reduction. In this section, portioning and implication
table methods of state reduction are discussed with examples.
9.8.1 Partitioning Table 9.24 State table
Table 9.24 shows a typical state table of a state Present Next state
diagram mentioning all states and a single input X state X=0 X=1
and a single output O. Initially, the first partition S0 S5 S4
can be made by placing all those present states in Output O = 1 Output O = 0
the same section of partition, when the outputs S1 S0 S2
Output O = 0 Output O = 1
are identical for all possible inputs. It is depicted
S2 S0 S3
in Table 9.24 that the present state S0, the two Output O = 0 Output O = 0
possible inputs X=0 and X=1 and the corresponding S3 S5 S6
outputs are O = 1 and O = 0. In the same way, if Output O = 0 Output O = 1
the present state is, either S4 or S5, the output O = 1, S4 S4 S2
when input X = 0 and the output O=0, while input Output O = 1 Output O=0
S5 S5 S4
X = 1. As the outputs are identical, the three states Output O = 1 Output O = 0
S0, S4 and S5 are equivalent states. Similarly, S1 and S6 S0 S3
S3 are equivalent and S2, S6 are also equivalent. Output O = 0 Output O = 0
Therefore, the first partition is
P1= (S0, S4, S5)(S1, S3)(S2, S6)
Table 9.25 Reduced state table
In the first partition, when X = 0, the next states for
S0, S4 and S5 are all in the same section of P1. While X=1, Present Next state
state X=0 X=1
the next states for S0, S4, S5 are S4, S2 and S4 respectively.
S05 S05 S4
As next state of S4 is different from others, the state S4 Output O = 1 Output O = 0
lies in a different section of partition. Therefore, first S13 S05 S26
section of partition P1 can be divided into two different Output O = 0 Output O = 1
sections. The first section consists of S0 and S5, and S26 S05 S13
the second section has only one state S4. Then the new Output O = 0 Output O = 0
partition is P2 = (S0, S5) (S4) (S1, S3) (S2, S 6). S4 S4 S26
After that, we again try to find out the existence of Output O = 1 Output O = 0
new partition using the same procedure. As there is no
further partition, the reduced state table is shown in Table 9.25.
 Sequential Circuits Design 375

Table 9.26 State table

9.8.2 Implication Table
The last method of state reduction is implication table. Table
Present Next state
state X=0 X=1 9.26 shows a state table of a typical sequential circuit. The
S0 S0 S2 implication table may be constructed by listing all the states
Output O = 0 Output O = 1 vertically except the first one and all the states horizontally
S1 S3 S0 except the last one. Figure 9.26 shows the implication table of
Output O = 1 Output O = 1 state Table 9.26. The implication table represents all possible
S2 S5 S5
combinations of state pairs and each cell of implication table
Output O = 0 Output O = 1
S3 S4 S1 is used as the testing ground for equivalent of a state pair.
Output O = 1 Output O = 1 For example, the first down left-hand cell at the intersection
S4 S6 S4 of S0 and S7 is the place where these two states are test for
Output O = 1 Output O = 1 equivalence.
S5 S2 S2 For testing the equivalence, there are two different condi-
Output O = 0 Output O = 1
S6 S1 S7
tions. The first condition is that the next state outputs of a
Output O = 1 Output O = 1 pair of states must be identical. Applying this condition, all
S7 S7 S2 the cells which can not be equivalent should be cross marked
Output O = 0 Output O = 1 on the implication table. For example, S0 and S1 may not be
equivalent as the next states outputs are 0, 1 and 1, 1 respec-
tively. Consequently, the cell at the intersection of S0 and S1
are cross marked. In the same way, all non-equivalent states
pairs are cross marked as shown in Fig. 9.27.
After that, place all implied pairs of equivalent states
in all empty cells of Fig. 9.27. For example, the cell at the
intersection S0 and S7 should consist of the implication of
both S0 and S7 as S0 and S7 are equivalent states. Similarly,
other equivalent implications must be entered in the other
empty cells as depicted in Fig. 9.28.

Fig. 9.26 Implication table

Fig. 9.27 Elimination of non-

equivalent states pair Fig. 9.28 Insertion of all implied pairs
 376 Digital Electronics: Principles and Applications

When the next states of the two states

are the same state for a given input, then
the two states are equivalent and put a trick
mark inside the cell which represents the
said states. For example, at the intersection
of S0 and S7, and at the intersection of S2
and S5, we can apply this rule and put a
tick mark on these two cells.
It is clear from the state Table 9.26
that S2 and S5 states are a pair of lock –in
states. S5 can be entered from S2 after
receiving a clock pulse. Similarly, S2
can be entered from S5 on the receipt of
clock pulse. But, there is no way to exist
from these states. Therefore, these two
states may be merged and after receiving
a clock pulse the sequential circuit must Fig. 9.29 The complete implication table after inserting
be stay in the merged state. This is called tick and cross marked
lock-in states. To leave these lock-in
states, a reset signal is required.
After that, we start testing the implication table row by row, starting
from the bottom right hand cell. A cross mark may be entered into a cell
which contains implied pairs when either of the implied pairs have already
crossed. The cell at the intersection of S4 and S6 should be cross marked as
the cell associated with the implied pairs S6 and S7, which are already cross
marked. This process will be repeated until no other cells can be crossed
out and finally we can get the final from of the implication table as depicted
in Fig. 9.29. Figure 9.30 shows the partition listing. Then implication table Fig. 9.30 Partition listing
should be examined column by column from right
to left to find if there any cells which have not been Table 9.27 Redusced state table
crossed out. Present Next state
In the first column of the implication table, the state X=0 X=1
first single cell at the intersection of S6 and S7 is
S0257 S0257 S0257
crossed out. Therefore, there will be no entry in Output O = 0 Output O = 1
the partition listing of S6. In the second column, the
S1 S3 S0257
state pair at the intersection of S5 and S7 have not
Output O = 1 Output O = 1
cross marked. Therefore, they are equivalent states
S3 S4 S1
and are entered in partition listing of S5. As there
Output O = 1 Output O = 1
is no uncrossed entries in the Column 3 and 4, the
S4 S6 S4
entry S5, S7 will be repeated for partition listing S3
Output O = 1 Output O = 1
and S4.
S6 S1 S0257
We can see in the fifth column that there are
Output O = 1 Output O = 1
two uncrossed cells which are intersection of S2, S7
 Sequential Circuits Design 377

and S2, S5 respectively. These two cells are equivalent. In the last column, we find that there are three
uncrossed cells S0, S7; S0, S5; and S0, S2. These three cells are also equivalent. Therefore, the final partition
listing will be P = (S0 S2 S5 S7) (S6) (S4) (S3) (S1). Table 9.27 shows the reduced state table.

Example 9.9 Determine the minimal state table for a synchronous sequential circuits as
given in Table 9.28 using (a) Caldwell’s merging rules and (b) Partitioning
Table 9.28 State table
Present Next state
state X=0 X=1
S0 S1 S2
Output O = 1 Output O = 1
S1 S3 S4
Output O = 1 Output O = 1
S2 S5 S6
Output O = 1 Output O = 1
S3 S0 S0
Output O = 1 Output O = 0
S4 S0 S0
Output O = 1 Output O = 1
S5 S0 S0
Output O = 1 Output O = 1
S6 S0 S0
Output O = 0 Output O = 1

� Solution
(a) In Caldwell’s merging rules, the equivalence of states can
Table 9.29 Minimal State Table be defined by the statement that “Two states Sm and Sn are
Present Next state equivalent if both have the same next states and also both have
state X=0 X=1 equal outputs”. It is depicted in Table 9.28 that states outputs
S0 S1 S2 for S0, S1, S2, S4 and S5 are equal but the next states are unequal.
Output O = 1 Output O = 1 Consequently, S0, S1, S2, S4 and S5 can not be merged together.
S1 S3 S45 But, only states S4 and S5 can be merged as both have the same
Output O = 1 Output O = 1 next states and also both have equal outputs. After merging
S2 S45 S6 S4 and S5 states, we find the minimal state table as shown in
Output O = 1 Output O = 1 Table 9.29.
S3 S0 S0
Output O = 1 Output O = 0 (b) In partitioning method, the first partition is made by placing
S45 S0 S0 all those present states in the same section of partition, when
Output O = 1 Output O = 1 the outputs are identical for all possible inputs. The states
S6 S0 S0 outputs for S0, S1, S2, S4 and S5 are equal and these states are
Output O = 0 Output O = 1 put in the same section. Outputs of state S3 and S6 are different
and they are placed in two different sections of partition.
Therefore, the first partition is
P1= (S0, S1, S2, S4, S5) (S3) (S6)
In the first partition, when X = 0 or X = 1, the next states for S4, and S5 are all in the same section of P1. But
when X = 0, the next states for S0, S1, S2 are S1, S3 and S5 respectively. As next states are different, the state S0,
 378 Digital Electronics: Principles and Applications

S1, and S2 must be in a different section of partition. Then the final partition is
P2 = (S0) (S1) (S2) (S4, S5) (S3) (S6) and the minimal state table is shown in Table 9.29.

9.9 ASYNCHRONOUS SEQUENTIAL CIRCUITS

Just like synchronous sequential circuits, the asynchronous sequential circuits are also feedback circuits.
The difference between synchronous and asynchronous sequential circuits is that there is no memory
element in the asynchronous sequential circuits and they are not clock driven. Due to the absence of
memory element, the implementation of the excitation Boolean function must be hazard free. If the
designer design the circuit based on the minimised Boolean functions, there will be some possibility of
static hazard in the circuit. Therefore, during the implementation of any asynchronous sequential circuit,
the designer should design the circuit in hazard-free form.
The block diagram of asynchronous sequential circuit is shown in Fig. 9.31. This block diagram
consists of a combinational logic circuit, n input variables X1 X2 …..Xn, m output variables O1 O2…Om, k
internal states y1 y2 …yk, and delay elements on feedback paths. The delay element is a gate circuit which
can provide propagation delay. The present state and next state variables in asynchronous sequential
circuit are known as secondary variables and excitation variables respectively. y1 y2 …yk are present state
(secondary) variables and Y1 Y2 ….Yk are next state (excitation) variables.

Fig. 9.31 Block diagram of asynchronous sequential circuit

The main characteristic of asynchronous sequential circuit is that only one input is allowed to change
at any particular instant. Simultaneous changes of two or more input variables are prohibited. This is
obviously different from the behaviour of a synchronous sequential circuit, where the change of input
variables are allowed arbitrarily and state changes are activated by the repetitive clock pulse.
There are two different conditions of any asynchronous sequential circuit, namely stable and unstable
states. At any instant, the state of the circuit is defined by the logical values of the input variables and the
present state of the circuit. When the next state is same as the present state, the circuit is in a stable state.
For a set of input variables, the circuit will be in stable state, if yi = Yi , where i = 1, 2…..k. Therefore,
circuit is stable only when the present state is equivalent to the next state. When the circuit is in stable
state, there is a change in the input variable which forces the combinational logic circuit to generate the
new set of next variables. Hence, yi ≠ Yi and the circuit operate in unstable state for time being. After
certain time delay, yi becomes Yi and the circuit again operates in the next stable state.
 Sequential Circuits Design 379

Therefore, due to change an input variable, the circuit, can move to an unstable sate and after some
time, the state variables are updated with their new values so that the next state has become the present
state and stability must be restored. Consequently, transition of asynchronous sequential circuit from
one state to next state takes place only in response to the change in input signals one at a time and only
when the circuit operate in stable state. This type of operation is called as fundamental mode. During
design of asynchronous sequential circuits, the designer should take care of static hazards, dynamic
hazards, and races, in order to avoid circuit malfunction.

9.10 DESIGN PROCEDURE OF ASYNCHRONOUS SEQUENTIAL

CIRCUITS
The design procedure of asynchronous sequential circuits is difficult than that of synchronous sequential
circuits as the timing problems are involved in the feedback (delay) path. In any synchronous sequential
circuit, timing problems are eliminated by triggering all flip-flops with the positive edge or negative edge
of clock pulse. The asynchronous sequential circuits are not clock driven and the state of asynchronous
sequential circuits is allowed to change instantaneously after the input changes. Therefore, during deign
of asynchronous sequential circuits, the designer should take care of that the input signals change one at a
time when the circuit in a stable state only. The main aim of design is that to develop hazard-free next state
functions and output equations. The design steps of asynchronous sequential circuits are given below:
Step-1 Define the problem with proper specification.
Step-2 Draw a block diagram for the proposed design with mention all the inputs and outputs.
Step-3 Draw a state transition diagram from the specification.
Step-4 Draw state table and state transition table.
Step-5 Plot the K -map for next state variables and outputs using present state variables and other
inputs.
Step-6 Derive the Boolean expressions for the excitation variables and outputs as a function of the
input and secondary variables.
Step-7 Implement the excitation equations and the output equations with the help of logic gates.
For example, consider a D latch with two inputs: one is DATA and other is LOAD. The D latch has
also one output O. Figure 9.32 shows the state diagram of D latch. Table 9.30 is state table of Fig. 9.32.
After substituting the following two states S0→0, and S1→1 in Table 9.30, we obtain the transition
Table 9.31.
The K-map of the excitation Table 9.31 is shown in Fig. 9.33. Based on the K-map as shown in Fig.
9.33, we can find the excitation equation and output equation. The excitation equation is
Q* = LOAD.Q + DATA.Q + LOAD.DATA
and the output equation is O=Q. The implementation of D latch is illustrated in Fig. 9.34.
Table 9.30 State table of D latch Table 9.31 Excitation table of D latch
Inputs (LOAD, DATA) Inputs (LOAD, DATA)
Present 00 01 10 11 Present 00 01 10 11
state (S) state (Q)
S0 S0 S0 S0 S1 0 0 0 0 1
S1 S1 S1 S0 S1 1 1 1 0 1
Next State (S*) Next State (Q*)
 380 Digital Electronics: Principles and Applications

Fig. 9.32 The state diagram of D latch

Fig. 9.33 K-map of Table 9.31 Fig. 9.34 D latch

Example 9.10 Design an asynchronous sequential circuit as shown in Fig. 9.35. The circuit has two
inputs A B, present state Q, next state Q* and one output O. The excitation table of
the circuit is illustrated in Table 9.32.

Fig. 9.35 Block diagram of asynchronous

sequential circuit
� Solution
The K-map for next state Q* and output O are depicted in Fig. 9.36 (a) and (b) respectively. Based on the
–
K-maps, we can find the excitation function and output equation. The excitation equation is Q* = AB + A Q
– –
and the output equation is O = A B + A Q. The implementation of excitation function and output equation is
shown in Fig. 9.37.

(a) (b)
Fig. 9.36 (a) K-map for Q* (b) K-map for O
 Sequential Circuits Design 381

Fig. 9.37 Logic diagram of asynchronous sequential circuit

Example 9.11 Design an asynchronous sequential circuit for the following behaviour
The circuit has two inputs A and B and two outputs O0 and O1. When both inputs are 0, outputs O0, O1 are 0
and Q* = Q. When both inputs are 1, outputs O0, O1 are 1 and Q* = Q. If Q = 0, either A = 1 or B = 1, output O0=
– –
0 and O1= 1 and Q* = Q. If Q = 1, either A = 1 or B = 1, output O0= 1 and O1= 0 and Q*= Q.
� Solution
The block diagram of asynchronous sequential circuit is shown
in Fig. 9.38. Table 9.33 shows the present state, next state and
outputs of the asynchronous sequential circuit according to circuit
behaviour. The K-map for next state Q* , outputs O1 and O0 are
depicted in Fig. 9.39 (a), (b) and (c) respectively. The excitation
function and output equations can be obtained from the K-map. The
– – –
excitation function is Q* = BQ + B Q, output equations are O1= AB
– –
+ BQ, and O0 = AB + BQ. Figure 9.40 shows the implementation
Fig. 9.38 Block diagram of asynchronous sequential circuit by using logic gates.

Table 9.32 The state table with output Table 9.33 The state transition table with outputs
Inputs (A, B) Inputs (AB)
Present 00 01 10 11 Present 00 01 10 11
state (Q) state (Q)
0 0/0 0/1 0/0 1/0 00 0/00 1/10 01/0 10/0
1 1/1 1/1 0/0 1/0 01 1/00 0/01 0/01 1/11
Next State/Output (Q*/O) Next State(Q1* Q0*)/Output(O)

Table 9.34 The state table with output

Inputs (AB)
Present 00 01 10 11
state (Q1Q0)
00 00/0 00/0 01/0 10/0
01 01/1 11/1 01/1 11/1
10 00/1 00/1 XX/1 11/1
11 10/0 10/0 11/0 11/0
Next State(Q1* Q0*)/Output(O)
382 Digital Electronics: Principles and Applications

Fig. 9.39 (a) K-map for Q* (b) K-map for O1 (c)-K map for O0

Fig. 9.40 Logic diagram

Example 9.12 Design an asynchronous sequential circuit for the state diagram as shown in Fig. 9.41.
Consider four states S0=00, S1=01, S2=10 and S3=11. Assume two inputs A and B and one output O.
 Sequential Circuits Design 383

Fig. 9.41 State diagram

� Solution
The state table of state diagram as shown in Fig. 9.41 is given in Table 9.34. The K-map the state table is
shown in Fig. 9.42. Then derive the excitation functions and output equation are as follows
Q*1 = AB + Q1Q0 + BQ0
– —
Q*0 = AB + Q1Q0 + AQ1 + AQ0
— —
O = Q1Q0 + Q1Q0 = Q1  Q0
The implementation of the asynchronous sequential circuit using combinational logic circuit elements is
shown in Fig. 9.43.

Fig. 9.42 K- Map of the transition Table 9.32

 384 Digital Electronics: Principles and Applications

Fig. 9.43 Implementation of asynchronous sequential circuit

9.11 ALGORITHMIC STATE MACHINES (ASM)

In any digital system, digital data are manipulated to perform arithmetic and logic operations, shifting,
counting and other data processing operations. Generally, these operations are practically implemented
using adders, decoders, multiplexers, registers, shift registers and counters ICs. The logic design of
digital circuits consists of controller and datapath. The datapath is related with the design of digital
circuits which performs the data-processing operations. The controller design is also related with control
circuit which generate control command signals as per requirement of digital circuit. Figure 9.44 shows
the block diagram of a digital system which indicates the relationship between controller and datapath.
Usually the control logic generates the signals for sequencing the operations in the datapath, where data is
processed sequentially. Initialisation commands
are generated from controller to reset the digital
system. After that, when external input and
status control signals are applied, the digital
system changes its present state to next state and
perform other specified operations.
The operations of controller and data
processing unit (datapath) of any digital system
can be represented by algorithm. Any algorithm
should have finite number of procedural steps
through which the problem will be implemented
using digital ICs. A flow chart of any algorithm
for hardware implementation can convert the Fig. 9.44 Controller and data-path interaction
 Sequential Circuits Design 385

statement into an information diagram which specifies the sequence of operations incorporating with all
necessary conditions for excitation. The special flow chart which can be developed specifically to explain
algorithms of digital system for hardware implementation is called an algorithmic state machine. Hence,
the alternative method of sequential circuit design is known as the algorithmic state machine (ASM).
While this technique is used to design any digital electronics circuit, the state diagram is constructed
in the form of a flow chart. In this section ASM can be explained with a sequence of actions which are
designed to initiate a set of state transitions and outputs for specified data inputs.

9.11.1 ASM Chart

Usually the flow chart is the simplest way to represent the sequence of operations and necessary
conditions for an algorithm graphically. A conventional flow chart explains the sequence of procedural
steps and decision paths for an algorithm without concern for their relationship but the ASM chart
describes the sequence of events. The ASM chart is adapted to specify the control sequence and data
processing operations in a digital system. If we compare between state diagram and ASM chart, we
find that ASM charts are slightly longer than state diagram. State diagrams are compact but difficult to
understand. Actually, ASM charts describe the sequential operations simply compared to state diagrams.
As the structured approach is followed in the construction of ASM chart, it is very easy to represent the
complex digital systems compared to state diagram representation. The three basic elements of the ASM
chart are state box, decision box and conditional output box as depicted in Fig. 9.45. The operation of
state box, decision box and conditional output box are explained in this section.

State Box In ASM, the rectangular box is used to represent each state for a period of one state time
which may be for one clock period or for an integral number of clock periods in a clock driven machine.
The state is identified by a binary code which is a unique combination of the state variables. Each state
should have a name or number for proper identification. There is one entry path and one exit path for each
state. The exit path may be connected directly to another state box or to one or more decision boxes. The
output is independent of the inputs and simply depends on the present state of the circuit. The outputs are
indicated in the rectangular box. The state output is active while the machine remains in the state, and is
present for the period of the state time. Figure 9.46 (a) shows an example of state box. This state has a
symbolic name S1 and the binary code is assigned to it is 001. Inside the box, it is written R ←0 which
represents the register R will be cleared to 0. The START_OP name inside the Box represents an output
signal which starts any specified operation. The register performs storage data, shift registers, counters,
increment, set and reset flip-flop, clear, 3 decrement, addition, and data transfer operations. The symbolic
notation of register operations is depicted in Table 9.35.
Table 9.35 Different register operations
Description Symbolic Notation
Clear register R R←0
Transfer the content of register A into Register B B←A
Increment register A by 1 A ←A+1
Decrement register A by 1 A ←A–1
Addition of resister A and B A ←A+B
Subtract the content of B from A A ←A–B
Set flip-flop F to1 F ←1
 386 Digital Electronics: Principles and Applications

Decision Box The decision box consists of a Boolean expression which generates a conditional
output based on the machine inputs. The ASM decision box is illustrated in Fig. 9.45(b) which has one
input path and three exit paths which will link to other state boxes. When the logical value of the condition
is 1, the true exit path is followed by ASM as shown in Fig. 9.46(b). If the logical value of the condition
is 0, the false exit path is followed. These two paths can be identified by 1 and 0 as shown in Fig. 9.46(b).
The exit paths of decision box can lead directly to another state box or to one or more decision boxes.

Fig. 9.45 ASM chart (a) state box (b) decision box (c) condition box

Fig. 9.46 Example of ASM chart (a) state box (b) decision box (c) condition box

Conditional Output Box The output depends on the present state of the circuit and the input
signals. This is represented by round-ended rectangle boxes. Actually, the round corners can differenti-
ate the conditional output box from the state box. The input path to a conditional output box is always
comes from the output of a decision box and the condition required to generate an active output must be
specified. The example of conditional output box is depicted in Fig. 9.46(c). If A is 0, register R will be
cleared. While A = 1, R will be unchanged. Either A = 0 or A = 1, the next state is S2 which is represented
by binary code 010 and the content register B will be transferred to register C.

9.11.2 ASM Block

The ASM block consists of at least one state box, and one or more decision boxes and conditional output
boxes which are connected with the exit path of decision box. Each ASM block should have one entry path
and more number of exit paths which are represented by the structure of the decision boxes. Figure 9.47 shows
a typical ASM chart which consists of one state box, two decision boxes and one conditional output box.
 Sequential Circuits Design 387

Initially, the ASM will stay at state S1 and it is represented by binary code 001. The output in this state
is A=A+1. The output of state box is associated with two decision boxes and one conditional output box
as depicted in Fig. 9.47. Any ASM block without any decision or conditional output boxes can form a
simple block. The operations within the state, decision boxes and conditional output boxes are executed
with in a clock pulse while the system is in S1 state. After the clock pulse, the system controller transfers
the sate S1 to any one of the next states such as S2, S3, and S4. The binary code of states S2, S3, and S4 are
represented by 010, 011, and 100. When B = 0, the register C will be cleared and the state of system will
be 100. If B = 1 and D = 0, the system operates in S3 state other wise output state will be S2.

Fig. 9.47 ASM block

9.11.3 Algorithmic State Machines Design

Any algorithm state machine should have finite number of steps and each step must be properly defined.
All steps should be represented in such a order that the sequential machine flow chart states the overall
behaviour of sequential machine. The ASM design of any digital problem can be done by the following
steps:
• Write the design specification.
• Convert the problem statement into algorithmic flow chart.
• Draw K-map.
• Find minimised next state and output functions.
• Implementation of digital circuit.

Example 9.13 Design a mod-7 counter using ASM.

� Solution
The counting sequence of mod-7 counter is 000, 001, 010, 011, 100, 101 and 110. The ASM chart for mod-
7 counter is shown in Fig. 9.48. There are seven steps assigned by state names S0, S1, S2, S3, S4, S5 and S6
388 Digital Electronics: Principles and Applications

respectively. Table 9.36 shows the present state and next state of mod-7
counter. Assume that the present state variables are A, B, and C and the next
state variables are Z3, Z2 and Z1. Figure 9.49 shows the K-map which is used
to derive the next- state functions. The expressions for Z1, Z2 and Z3 are Z1 =
–– –– – – – – –
A C + BC , Z2 = A BC + BC and Z3 = AB + A BC. The implementation of mod-7
counter using ASM is illustrated in Fig. 9.50.

Table 9.36 Present state and next state of mod-7 counter

Present state Next state
A B C Z3 Z2 Z1
0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 0 0 0

Fig. 9.48 ASM chart of

mod-7 counter

Fig. 9. 49 (a) K-map for Z1 (b) K-map for Z2 (c) K-map for Z3
 Sequential Circuits Design 389

Fig. 9.50 Logic diagram of mod-7 counter

Example 9.14 Design a 2-bit synchronous up/down counter

� Solution
It can be assumed that initial count value of the counter is 00. When the 2-bit
synchronous UP/Down counter control input (UP) is high, the counter should
count upward direction on every clock pulse and the counting sequence will
be 00, 01, 10, 11, and 00. If the UP/Down counter control input (UP) is low,
the counter starts counting in down ward direction on every clock pulse
such as 00, 11, 10, 01,00. To develop the ASM chart, the detail sequence
of counter operations must be represented sequentially. Figure 9.51 shows
the ASM chart for 2-bit synchronous UP/Down counters. Present state and
next state of 2-bit UP/Down counter are illustrated in Table 9.37 where the
present state variables are A and B, and the next state variables are Z2 and
Z1. Figure 9.52(a) and (b) show the K-map for Z1 and Z2 respectively. The
expressions for Z1 and Z2 are as follows
–
Z1 = B and
– – —– –– – – –– –— – –
Z2 = A B U P + ABUP + A BUP + ABUP = (A B + AB)UP + (A B + AB)UP =
––—– — —
A  B UP + (A  B)UP.

The implementation of 2-bit synchronous Up/Down counter using ASM is

illustrated in Fig. 9.53.

Table 9.37 Present state and next state of 2-bit UP/Down counter
Present State Next State when UP=1 Next State when UP=0
A B Z2 Z1 Z2 Z1
0 0 0 1 1 1
0 1 1 0 0 0
1 0 1 1 0 1 Fig. 9.51 ASM chart for
1 1 0 0 1 0 2-bit UP/Down counter
 390 Digital Electronics: Principles and Applications

Fig. 9.52 (a) K-map for Z1 (b) K-map for Z2

Fig. 9.53 2-bit synchronous UP/Down counter

Example 9.15 Draw ASM chart of a 4:1 multiplexer.

� Solution
Figure 9.54 shows the symbolic representation of 4:1 multiplexer,
which has two select lines S1 and S0 and four inputs X1, X2, X3
and X4 and one output F. The functional table of 4:1 Mux is
illustrated in Table 9.38. When S1= 0 and S0 = 0, output F = X1.
Similarly, depending upon the select inputs, output is available
at output F. The ASM chart of 4:1 multiplexer is depicted in
Fig. 9.55.

Table 9.38 Functional Table of 4:1 MUX Fig. 9.54 Symbol of 4:1 MUX

S1 S0 Output
0 0 F=X1
0 1 F=X2
1 0 F=X3
1 1 F=X4
 Sequential Circuits Design 391

Fig. 9.55 ASM chart for 4:1 MUX

Example 9.16 Draw ASM chart of full adder.

Table 9.39 Full adder � Solution

Inputs Outputs The full adder is used for adding two binary
A B Cin F Cout digits A and B with carry input Cin. There are
0 0 0 0 0 eight combinations of A, B and Cin as given in
0 0 1 1 0 Table 9.39. After addition, the outputs are sum
0 1 0 1 0 F and carry output Cout. Figure 9.56 shows the
0 1 1 0 1 ASM chart of full adder.
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Fig. 9.56 ASM chart of full adder

 392 Digital Electronics: Principles and Applications

Example 9.17 Develop ASM chart for the following conditions of a digital circuit:
The output of digital circuit depends upon the trigger pulse as well as inputs X1 and X2. Assume that after
application of first trigger pulse, output =1
which is independent of inputs X1 and X2.
If X1 X2 = 00, 01, and 10, output = 0 after
application of second positive edge trigger
pulse. When X1 X2 = 11 and second positive
edge trigger pulse is applied, output =1.

� Solution
The transition from one state to the other
state takes place at rising or positive edge
of the clock pulse. After the first rising edge
of the clock pulse, the output is high. As the
output does not depend on input signals, the
first rectangle-box has a value Z=1. The out-
put is low after the second rising edge of the
clock pulse when X1 X2 = 00, 01, and 10 and
the output is high for the condition X1 X2 =
11. The ASM chart for the above operations Fig. 9.57 ASM chart
is shown in Fig. 9.57. This block diagram can be represented in the ASM chart by drawing a decision box
which ANDs both the inputs. When the result of ANDing X1 and X2 is 1, the output is high and rectangle-box
contains Z=1. If ANDing X1 and X2 is 0, output is low and rectangle-box contains Z=0.

SUMMARY
Generally, any sequential circuit consists of a combinational logic circuit and memory elements. The output of
combinational logic circuit is stored in memory elements. Memory elements output feedback into combinational
logic circuit and used as input variables. The output of combinational logic circuit is function of the external inputs
and inputs from memory elements. In this chapter, the modeling and classification of sequential circuits has been
discussed. The operation of Mealy machines and Moore machines, function of state table, state diagram and state
equations are also incorporated. Designs of synchronous and asynchronous sequential circuits with examples are
discussed elaborately. In this chapter, the operation of algorithmic state machines (ASM) are also incorporated with
some examples.

MULTIPLE CHOICE QUESTIONS

1. The sequential circuits consists of combinational logic as well as memory elements
(a) Combinational logic as well as memory elements
(b) Combinational logic only
(c) Memory elements only
(d) None of these
2. The example of sequential circuit is
 Sequential Circuits Design 393

(a) Counter (c) Combinational logic circuit

(b) Shift register (d) 7- segment display
3. The sequential machine is a
(a) Feedback system (c) Feedback and non-feedback system
(b) Non-feedback system (d) None of these
4. The Moore machine is defined by the equations
(a) Next state = F (Present state, Inputs) and Output = G (Present state)
(b) Next state = F (Inputs) and Output = G (Present state)
(c) Next state = F (Present state) and Output = G (Present state)
(d) Next state = F (Present state, Inputs)
5. The Mealy machine is defined by the following equations.
(a) Next state = F (Present state, Inputs) and Output = G (Present state, inputs)
(b) Next state = F (Present state) and Output = G (Present state, inputs)
(c) Next state = F (Present state, Inputs) and Output = G (inputs)
(d) Next state = F (Inputs) and Output = G (Present state, inputs)
6. A synchronous Melay machine has
(a) An input decoder, memory elements and an output decoder
(b) An memory elements and an output decoder
(c) An input decoder and an output decoder
(d) An input decoder and memory elements
7. The asynchronous Melay machine consists of
(a) An input decoder and an output decoder
(b) An input decoder, memory elements and an output decoder
(c) Memory elements and an output decoder
(d) An input decoder and memory elements
8. A synchronous Moore machine has
(a) An input decoder, memory elements and an output decoder
(b) A memory elements and an output decoder
(c) An input decoder and an output decoder
(d) An input decoder and memory elements
9. The asynchronous Moore machine consists of
(a) An input decoder and an output decoder
(b) An input decoder, memory elements and an output decoder
(c) Memory elements and an output decoder
(d) An input decoder and memory elements
10. Reduced state diagram of any state table can obtained from
(a) Inspection (b) partitioning (c) implication table (d) all of these
11. A sequential circuit can be designed with the help of
(a) State Table (b) State diagram (c) K-maps (d) all of these
 394 Digital Electronics: Principles and Applications

12. When the output of a sequential circuit depends on the present input as well as previous output states,
the circuit is called
(a) Moore machine (b) Mealey machine (c) Sequential circuit (d) all of these

REVIEW QUESTIONS
9.1 (a) Define sequential circuit.
(b) Discuss the classification of sequential circuit with examples
(c ) Write difference between synchronous and asynchronous sequential circuit
9.2 (a) Explain Mealy and Moore machines.
(b) Write difference between Mealy and Moore machines
9.3 (a) Discuss state table, state diagram and state equations of a finite state machine with example.
(b) Write design procedure of a finite state machine.
9.4 A sequential circuit has two inputs X and CLOCK and one output O. Incoming data are examined
in consecutive groups of three digits and the output O=1 for the following three input sequences
000, 010 and 111. Draw a state diagram and implement the sequential circuit using D, T and J-K
flip-flops.
9.5 Find the minimal state table for sequential machines as given in Table 9.40.
Table 9.40 State Table
Present state Next state
X=0 X=1
S0 S0 S1
Output O = 0 Output O = 0
S1 S3 S2
Output O = 0 Output O = 1
S2 S0 S3
Output O = 0 Output O = 0
S3 S5 S4
Output O = 0 Output O = 1
S4 S1 S2
Output O = 1 Output O = 0
S5 S5 S4
Output O = 0 Output O = 1
S6 S0 S1
Output O = 0 Output O = 0
9.6 Design a sequential circuit for
the state Table 9.41 using J-K Table 9.41
flip-flops. Assume two inputs are
Present state Inputs (AB)
A and B, output of the sequential 00 01 10 11
(Q1Q0)
circuit is O, present state of J-K
00 01/1 00/0 00/1 01/0
flip-flops = Q1Q0 , Next State of
J-K flip-flops = Q1* Q0*. 01 10/1 00/1 00/0 10/1
10 11/0 00/0 00/1 11/0
11 01/0 00/1 00/1 01/1
Next State (Q1* Q0*)/Output(O)
 Sequential Circuits Design 395

9.7 The state diagram of a sequential circuit is given in Fig. 9.58. Draw the state table for Fig. 9.58 and
implement using T flip-flops. Assume two inputs are A and B, output is O.

Fig. 9.58

9.8 The state diagrams of sequential circuits are given in Fig. 9.59 and Fig. 9.60. Design the sequential
circuits using flip-flops and combinational logic circuit.

Fig. 9.59 Fig. 9.60

9.9 Draw the state diagram and state table of a up-down counter. Design the Up-Down counter using T
flip-flops.
9.10 A sequential circuit has one input and one output. The state diagram is shown in Fig. 9.61. Design
the circuit with J-K, D and T flip-flops.
 396 Digital Electronics: Principles and Applications

Fig. 9.61

9.11 Design a 5 state sequential machine whose sequential states are: 000, 001, 010, 110, 111, 000…..
Assume initial state is 000.
9.12 Why state reduction is necessary in sequential circuit design? What are the different methods of
state reduction? Explain implication table method of state reduction with an example.
9.13 Explain algorithmic state machines with examples. Discuss how the ASM chart differs from a con-
ventional flow chart. Draw the ASM chart of (a) 8:1 Multiplexer and (b) 4-bit synchronous Up/Down
counter.
9.14 A synchronous counter is controlled by two input signals A and B. The counter does not operate, if
A = 0 and B = 0. When A = 0 and B = 1, the counter operates as a mod four counter. If A=1 and B=0 the
counter operates as a mod eight counter. Draw an ASM chart and design a circuit using D flip-flops
and NAND gates to satisfy the above specification.
9.15 A sequential circuit waveform generator generates four output waveforms which are controlled by
input signals X1 and X2. If X1= 0 and X2= 0, the output wave form is high for a period of three clock
cycles and low for a period of one clock cycle. When X1= 1 and X2= 0, the output wave form is high
for a period of two clock cycles and low for a period of two clock cycles. If X1= 0 and X2= 1, the
output wave form is low for a period of three clock cycles and high for a period of one clock cycle.
When X1=1 and X2=1, the output wave form is high for a period of one clock cycle and low for a
period of three clock cycles. Develop an ASM chart for the waveform generator. Draw a state table
and implement the waveform generator using D flip-flops.
 CHAPTER

10
MULTIVIBRATORS
10.1 INTRODUCTION
The output of sequential logic circuits depends on the present input states and previous history. The logic
circuits operation can be controlled by a train of clock pulses. When the clock pulses are applied, the
outputs of sequential logic circuit changes from one state to next state. These clock pulses are generated
by clock generators or oscillators. The clock generators are frequently called as astable or free running
multivibrator. In this chapter, clock oscillators using TTL and CMOS, astable, monostable, bistable
multivibrators and their applications, operation of 555 timer and its applications have been explained.
The operation of 556 timer IC, non-retriggerable monostable multivibrator IC 74121, retriggerable
monostable multivibrator IC 74122 and IC 74123 are also incorporated.
10.2 CLASSIFICATION OF MULTIVIBRATORS
There are three types multivibrators, namely astable multivibrator, monostable multivibrator, and
bistable multivibrator. These multivibrators are most commonly used in timing applications.
Astable Multivibrator Astable multivibrator is known as free running multivibrator. It has
two quasi-stable states and it continues to oscillate between two stable states. This multivibrator has no
stable state and external trigger pulses are not required to change
the states. This device can be used to generate square wave and the
time duration depends upon circuit parameters. The continuously
generated pulses are used as clock pulses in flip-flops, registers,
counters and other digital circuits where the clock pulse is required
for operation. Figure 10.1 shows the output voltage waveform of an
astable multivibrator which oscillate between 0V and 5V without
Fig. 10.1 Astable multivibrator application of any trigger pulse.

Monostable Multivibrator Monostable multivibrator has a single stable state and a quasi-stable
state. In this multivibrator, trigger signal is applied to switch from stable state to quasi-stable state. After
a short time, the circuit reverts back to its stable state. Hence, a single output pulsed is generated when
a trigger pulse is applied to it. Therefore, it is known as one shot or single shot multivibrator circuit.
The output pulse width can be controlled by internal circuit parameters and trigger pulse has no control
over the pulse width of output waveform. As a result, a small pulse width or a sharp trigger pulse can
be converted into an output of longer pulse width. So, this multivibrator is also called as pulse stretcher.
Figure 10.2 shows the output voltage waveform and trigger signal of a monostable multivibrator. At time
 398 Digital Electronics: Principles and Applications

t1, when the trigger pulse is applied, output of monostable multivibrator changes from 0V to 5V and its
output stay at 5V for certain time T1 depending on circuit parameters. After T1 time, output changes from
5V to 0V without application of any trigger pulse.

Fig. 10.2 Monostable multivibrator

Bistable Multivibrator A bistable multivibrator has two stable states. When external trigger
pulses are applied, the multivibrator changes one stable state to other stable state. Therefore, two exter-
nal triggers are required for this multivibrator and bistable multivibrator is not an oscillator. The output
voltage waveform and trigger signal of a monostable multivibrator are illustrated in Fig. 10.3. Assume
the two stable states are 0V and 5V and initially multivibrator output is 0V. At time t1, when the trigger
pulse is applied, output of bistable multivibrator changes from 0V to 5V and its output continue at 5V
for T1 time depending on the next trigger pulse. At time t2, if the next trigger pulse is applied, output
changes from 5V to 0V.

Fig. 10.3 Bistable multivibrator

Figure 10.4 shows the block diagram of a multivibrator,
which consists of two inverting amplifiers A1 and A2 and
two networks N1 and N2, which are used to develop a
regenerative feedback loop. The type of multivibrator
depends on the nature of coupling used in network. If the
circuit behaves as bistable multivibrator, N1 and N2 will
be resistance. In monostable multivibrator N1 or N2 will
be capacitance. But in astable multivibrator N1 and N2 are
capacitance. The operation of astable, monostable and Fig. 10.4 Block diagram of multivibrator
bistable multivibrators are explained in this chapter.
10.3 CLOCK OSCILLATOR USING BJTs
Generally, clock oscillator is a two stage switching circuit in which the output of the first stage is fed to
the input of the second stage and vice versa. The outputs of both the stages are complementary. Figure
 Multivibrators 399

10.5 shows the clock oscillator using NPN transis-

tors. This free running oscillator generate square
wave without any external triggering pulse. The
circuit has two states and switches back and forth
from one state to another. The switch should re-
main in each state for a time depending upon the
discharging of capacitor through a resistance.
Hence, clock oscillators are used to generate
clock pulses.
The circuit as depicted in Fig.10.5 also behaves
as a simple astable circuit. The working principle
as follows:
Consider that T1 is turned on and T2 is off.
The collector voltage of T1 will be approximately
zero, and C1 is charging through R1 and collector- Fig. 10.5 Clock oscillator using NPN transistors
emitter of T1. The charge on C1 will be increased
and the voltage at the base of T2 will also be increased. As T2 is not conducting, the capacitor C2 will
charge through R4 and the base-emitter of T1. The charging of C2 will be very fast due to small R4.
Consequently, the collector voltage of T2 will be +Vcc with respect to the base of T1 at the end of
charging C2. While the base voltage of T2 is more than 0.6 volts, the transistor T2 switch becomes on.
The voltage at the collector of T2 will be approximately zero. Therefore, one end of C2 is 0 volts and the
other end is a voltage -Vcc due to capacitor charging. Then T1 switches off.
After that, capacitor C2 starts charging through R2 and the collector-emitter of T2 and its voltage changes
from negative to zero and then positive. When C2 charges about 0.6V, T1 will switch on and again the cycle
continues. The charging and discharging of C1 and C2 are shown in Fig.10.6 when T1 is turned on and T2 is
off. Figure 10.7 shows charging and discharging of C1 and C2 when T1 is off and T2 is turned on.

Fig. 10.6 Charging and discharging of Fig. 10.7 Charging and discharging of
C1 and C2 when T1 is turned C1 and C2 when T1 is off and T2
on and T2 is off turned on
The voltage across capacitor, C and resistor, R must be equal to the applied voltage, Vcc. The
mathematical relationship as given below:
Q
Vcc = IR +
C
 400 Digital Electronics: Principles and Applications

dQ Q dQ
Vcc = R + where, Q is charge and I =
dt C , dt
After integrating the above expression, the voltage across the capacitor can be expressed as
V(t) = VCC – (VCC – V0) e-t/RC.
where, V0 is the voltage across the capacitor at t = 0. In this case, the initial voltage V0 = –Vcc. If t = log2
× RC = 0.693RC, V(t)=0V . In this oscillator, when T1 is on, T2 is
OFF and when T1 is off and T2 is ON. The on time and off time are
calculated by the following expressions as given below:
t1=0.693 R1 C1 and t2 = 0.693 R2 C2.
Fig. 10. 8 Wave form of astable The total time period, T = t1+ t2 = 0.693(R1 C1 + R2 C2)
multivibrator
If R1=R2=R and C1=C2=C
T=1.386 RC and the clock frequency, f = 1/T =
0.721/RC.
The cyclic switching of T1 and T2 produces a
square wave at the collectors of transistors T1 and T2.
The waveform of collector of T1 and T2 is shown in
Fig. 10.8. The output of transistor T1 is complement
of T2. Therefore this circuit is called as astable
multivibrator. The astable multivibrator using PNP
transistor is depicted in Fig. 10.9.

Fig. 10.9 Clock oscillator using PNP transistors

Example 10.1 In an astable multivibrator using NPN transistors as shown in Fig. 10.5, the resistance
R1=R2=10K and C1=C2=0.01µF and R3=R4=1Kohm, determine the clock frequency.
� Solution
t1=0.693 R1 C1=69.3 ms and t2=0.693 R2 C2=69.3 µs.
Total time period, T= t1+t2=69.3µs +69.3µs=138.6µs
1
The clock frequency, f = =1/138.6µs =7. 215 KHz
t1 + t2

10.4 MONOSTABLE MULTIVIBRATOR USING BJTs

Figure 10.10 shows the monostable multivibrator using BJTs. It has one stable state when T1 is in cut-
off and T2 operates in saturation. If the trigger pulse is applied, T2 cut-off and T1 saturation and output
will be quasi-stable. After some time, the circuit returns back to stable state. The detail circuit operation
explained below:
Just after switch on the power supply, the circuit operates in stable state until a trigger pulse is applied
as T1 cut-off and T2 saturation. To operate in saturation, R1 value is selected in such a way that can supply
 Multivibrators 401

required base current. The capacitor is charging through R1 and base emitter junction of transistor T2.
When T2 is in saturation, the collector output voltage of T2 will be 0V.
When a negative trigger pulse is applied, C2 act as short circuit, diode D is forward biased and conducting.
Then the voltage at base of transistor T2 will be reduced. Then transistor T2 will operate in cut-off. The
collector voltage of T2 increases to +VCC and the base current of T1 increases. The collector potential will
be reduced and capacitor C2 starts to discharge through T1. Then T1 is in saturation and T2 is in cutoff. After
completely discharged capacitor C2, it starts to charge in the opposite direction through R2. Therefore,
potential at the base of T2 starts to increase. When it is 0.7V, T2 starts conducting. So T2 operates in saturation
and T1 is in cut-off. Then the circuit again operates in stable state. Figure 10.11 shows the waveform of
monostable multivibrator. The duration of pulse width is equal to T = 0.7 RC approximately.

Fig. 10.10 Monostable multivibrator Fig. 10.11 Waveform of monostable

using BJTs multivibrator

10.5 BISTABLE MULTIVIBRATOR USING BJTs

Figure 10.12 shows the Schmitt trigger circuit. Schmitt
Trigger is also called an emitter coupled binary trigger
circuit. It has two stable states that happened when
transistor T1 may be ON and T2 OFF or vice versa.
When input voltage does not applied to transistor T1,
the voltage divider network R3 and R4 along with R2
maintains the base of T2 at a slightly positive potential
with respect to emitter. Therefore, T2 operates in the
saturation region. Due to the current flow in T2, the
voltage developed across the common emitter resistor,
and T1 is at cut-off. As the base of T1 is at ground
potential, it is negative with respect to the emitter. In
this way, the circuit operates in a stable state when
Fig. 10.12 Schmitt trigger (bistable multivi-
input signal is absent and T2 ON and T1 OFF. The output brator) using BJTs
voltage is in the low state. Raising or lowering the bias
on T1, it may start the switching action.
When a time varying input voltage is applied, as soon as the input voltage reaches a value equal to the
sum of the voltages across R3 and R6, T1 will be turns ON as its base is more positive with respect to the
 402 Digital Electronics: Principles and Applications

emitter. T1 is switched ON and operates

in the saturation region. The collector
voltage of T1 decreases, which interns
the base voltage of T2 is also decreases.
Hence, T2 is driven to cut-off until the
input voltage is greater than the sum of
the voltages across R3 and R4. When T2 is
in cut-off, output voltage switches to the
difference between Vcc and the voltage
across R5.
If the input voltage drops below the
sum of the voltages across R1 and R6, T1
turns OFF and T2 again turns ON due to
Fig. 10.13 Waveform of Schmitt trigger (bistable multi- regenerative action. Then output voltage
vibrator): Vi = input signal and returns to the sum of the voltages across
VT2=output signal R6 and the saturation voltage of T2. Thus,
a square wave is produced. The turn ON voltage is usually called the upper trigger point or UTP. The
turn OFF voltage is also called lower trigger point or LTP. UTP is always greater than LTP. The UTP
= IC(sat) R6 + VBE(ON) and LTP=VBE + IE R6 . If Vcc=12V, UTP=5V, LTP=3V and input voltage is varied in
sinusoidal manner, the output waveform of bistable multivibrator is shown in Fig. 10.13.

10.6 ASTABLE MULTRIVIBRATOR USING NOT GATES

Figure 10.14 shows the astable multivibrator or clock oscillator using
NOT gates. It consists of two inverters, which are connected, in cascade.
Inverter provides a phase shift of 180° between input and output. When
a square wave signal is used as input, an inverter output signal will be
obtained with 180° phase shift after a very small propagation delay. The
Fig. 10.14 Cascade con- propagation delay varies in between 4ns to 60 ns for different TTL ICs.
nection of two inverters If propagation delay of each TTL NOT gate is tpd=25ns, then a total time
delay = 2 tpd = 2 × 25=50ns will be achieved. When output is used as input
V1, then positive feedback is achieved and
circuit behaves as feedback oscillators.
Then time period will be 2 × 50=100ns
for 360° phase shift and frequency of
oscillation =1/100 ns=10 MHz. Figure
10.15 shows the waveform of V1, V2 and
V0 for two cascade connected inverters.
Similarly, astable multivibrator using
three and five NOT gates are shown in
Fig. 10.16 and Fig. 10.18 respectively
and its waveforms are also depicted in
Fig. 10.17 and Fig. 10.19. In these cir-
Fig. 10.15 Waveform of V1, V2 and V0 cuits, NOT gates are connected in cas-
 Multivibrators 403

cade and the output of third and fifth NOT gate are used
as input of first NOT gate which forms a closed loop
system. If propagation delay of each NOT gate is 25ns,
then a total 3 × 25=75ns time delay can be achieved for
Fig.10.17 and 5 × 25=125ns for Fig. 10.19. Then time
Fig. 10.16 Cascade connection three period will be 150ns and 250ns and oscillation frequen-
inverters (NOT gates) cy =1/150ns=6.666 MHz for Fig. 10.17 and f=1/250ns=
4 MHz for Fig. 10.19.
The disadvantage of these circuits is that
the frequency of output waveform cannot
be controlled externally. Actually, external
circuits cannot control propagation delay
and therefore frequency is uncontrolled.
Figure 10.20 shows the modification of
astable multivibrator circuit using inverters,
R and C elements. When the resistance and
capacitance are incorporated in the circuit,
there will be some control in frequency.
When the power is switched on C2 begins
Fig. 10.17 Waveforms of three cascaded inverters
(NOT gates): V1, V2 and V3
to charge through R2, the input voltage
of inverter-2 begins to rise, the output
will stay high till the input voltage
to the inverter INV2 reaches a high
logic level voltage. The duration of
high output voltage depends upon
Fig. 10.18 Cascade connection of five inverters the time constant C2R2. When input
(NOT gates) voltage of INV2 arrives at the high
logic level voltage, inverter output
changes from high to low.
Then capacitor C1 start to charge through R1 and input voltage of INV1 increases. The output of INV1
will be high till the input voltage of INV1 reaches a high logic level voltage. The inverter output voltage
changes from high to low when input voltage of INV1 arrive at high logic level voltage. The time period
of output voltage depends upon the time constant R1C1.Therefore, alternately capacitors C1 and C2 will
be charged. As a result, clock pulses will be produced. The frequency of clock pulse is
1 1 1
f = = =
t1 + t2 0.7 R1C1 + 0.7 R2C2 0.7( R1C1 + R2C2 )
where t1 = 0.7R1C1 and t2 = 0.7R2C2
1
if R1 = R2 = R and C1 = C2 = C, frequency f =
1.4 RC
As frequency depends on the circuit parameters such as resistances and capacitances, the frequency
stability is not good. To increase frequency stability, quartz crystal is used as shown in Fig. 10.21.
The oscillator frequency is same as the quartz crystal. The oscillation frequency can be expressed as
f = 1/2RC. When the frequency is known, the value of R and C can be determined from this expression.
 404 Digital Electronics: Principles and Applications

Fig. 10.19 Output waveform of multivibrator using cascade connection of five inverters,
V1= V0, V2, V3 and V4
When CMOS inverters replace TTL inverters, the
Fig.10.20 and Fig.10.21 also behave as oscillator or
astable multivibrator. Due to different propagation delay
of CMOS ICs, the frequency of this oscillator will be
different. The output frequency depends on the supply
voltage and temperature, but this variation is very narrow
range. Therefore, this circuit has very little control over
the output frequency. The frequency control range can
Fig. 10.20 Modified TTL clock oscillator
be increased by using resistances and capacitance as
shown in Fig.10.22 and the oscillation frequency can be
determined from the expression f = 0.559/RC.
Figure 10.23 shows the astable multivibrator using AND
and NOT gate. Initially, consider the capacitor is uncharged
and VC = 0V. After switch on the power supply, VC = 0V. So
the input voltage of inverter is low, inverter output voltage is
high. This high voltage fed to AND gate as input. Then output
of AND is high and this voltage applied across the RC circuit
and capacitor voltage starts increasing due to charging. The
output of inverter will be high till capacitor voltage reaches Fig. 10.21 TTL clock oscillator with
the high logic level voltage (VH). When VC cross the high crystal control
logic level voltage VH at time t1, inverter output changes from
high to low. Then AND gate output will be low and capacitor
starts discharging. The inverter output voltage will be low
till capacitor voltage reaches the low logic level voltage (VL).
When VC arrives the low logic level voltage VL at time t2, Fig. 10.22 CMOS oscillator
 Multivibrators 405

inverter output changes from low to high and the next cycle of operation begins. The voltage across the
capacitor VC and output voltage VO are shown in Fig. 10.24.

Fig. 10.23 Astable multivibrator

using AND and NOT gates

Fig. 10.24 Voltage across capacitor VC and output voltage VO

10.7 MONOSTABLE MULTRIVIBRATOR USING NAND GATES

Figure 10.25 shows the monostable mul-
tivibrator using two NAND gates. Trigger
pulse is connected with one terminal of
first NAND gate and other input terminal
is used for feedback. Output of this NAND
gate is applied to RC circuit. The second
NAND is used as a NOT gate. Therefore,
both input terminals are shorted and volt-
age across resistance is applied as input of
Fig. 10.25 Monostable multivibrator using NAND gates the second NAND gate.
The negative trigger pulse is applied at
t=t0, output of Gate-1 changes from low to high. Then high voltage applied across RC and capacitor starts
to charge. The voltage across resistance and capacitance is shown in Fig. 10.26. At t=t1, trigger pulse
changes from low to high and then terminal 1 becomes high but terminal 2 is low. Then output voltage
of Gate-1 is high. As output voltage is high, the capacitor continuously charged through resistance. At
t=t2, capacitor is fully charged and the voltage across resistance becomes zero. Consequently, the output
of Gate-2 will be high. Therefore, during t2– t0, the output of multivibrator is low.

10.8 MULTIVIBRATOR USING OP AMPs

The operational amplifier is generally known as OP AMP which is most commonly used to perform
mathematical operations such as addition, subtraction, integration and differentiation etc. This is also
used in analog computers. The op-amp is a linear amplifier and its dc open-loop voltage gain is very
high in the range of 103 to 106. The op-amp is constructed from several transistor stages namely dif-
ferential-input stage, an intermediate-gain stage and a push-pull output stage. The differential amplifier
consists of a pair of bipolar transistors or FETs. The push-pull amplifier transmits a large current to the
 406 Digital Electronics: Principles and Applications

load and hence has small output impedance. An

ideal amplifier has following properties: large in-
put impedance Zin→∞, small output impedance
Zout→0, wide bandwidth, infinite gain A→∞, and
infinite CMRR (common mode rejection ratio).
741 operational amplifier ICs are readily
available in market and most commonly used
in analog circuits. This device operates from
DC to about 20 KHz, but the high-performance
operational amplifiers operate up to 50 MHz.
Figure 10.27 shows the symbol of an
operational amplifier. It has two inputs namely
inverting (-) and non-inverting (+) and one
output terminal V0. Input voltages V1 and V2 are
applied between inverting terminal and ground,
and between non-inverting terminal and ground
respectively. The output voltage VO is measured
in between output terminal and ground. The
input terminals are known as differential inputs
and the output is single ended. The output
voltage VO can be expressed as
V0 = A Vi, where A = the voltage gain Fig. 10.26 Waveforms of monostable multivibrator
of the amplifier and Vi= V1– V2.
As A is extremely high, about 200,000, the differential input voltage
Vi is very small (Vi →0) and output voltage will be varied between
positive and negative saturation voltages +VCC and –VCC respectively.
In this diagram, +VCC =+15V (DC) and -VCC=-15V (DC). The positive
and negative voltages are necessary to allow the amplification of both
positive and negative signals without special biasing.
Fig. 10.27 Symbol of
10.8.1 OP AMPs as Comparators operational amplifier
A comparator compares the
value of input signal to a ref-
erence voltage. If the input
signal voltage is larger than
the reference voltage, com-
parator output will be HIGH.
If the input signal voltage is
smaller than the reference
voltage, comparator output Fig. 10.28 (a) Comparator circuit (b) Characteristics of comparator
will be LOW. when Vref=0V
Figure 10.28 shows the (c) Characteristics of comparator when Vref=+ve
comparator circuit using an ideal operational amplifier. Since the open-loop gain of the ideal operational
amplifier is infinite, the following equations can be expressed.
 Multivibrators 407

Vi>Vref, then Vd>0 and Vo= +VCC

Vi<Vref, then Vd<0 and Vo= -VCC

The operational amplifier compares the input signal with the reference voltage. If Vref = 0 and Vi > 0,
the Vd is positive, the operational amplifier output will be high or V0 = +VCC. If Vref = 0 and Vi < 0, the Vd
is negative, the operational amplifier output will be low or Vo= -VCC. When +VCC =15 V and -VCC = –15,
the output voltage will be either +15V or –15V. Figure 10.28 (b) shows the output characteristics when
Vref = 0V.

When Vref = +ve, the output characteristics of comparator is depicted in Fig. 10.28 (c). The output
characteristics can be reversed when Vref and Vi are interchanged as shown in Fig. 10.29(a) and its
characteristics are shown in Fig. 10.29(b). When Vref = + ve, the output characteristics can be expressed
as

Vi>Vref, then Vd<0 and Vo= – VCC

Vi<Vref, then Vd>0 and Vo= +VCC

Fig. 10.29 (a) Comparator circuit

(b) Characteristics of comparator when Vref = +ve

Example 10.2 If Vref = 2V and Vi = 10 sin ωt in Fig. 10.28 and Fig. 10.29, draw the output
waveforms.
Assume f = 50Hz.

� Solution
Figure 10.30 shows the output voltage waveform, when Vref=2V and Vi=10 sin ωt in Fig. 10.28. When input
voltage Vi is greater than Vref=2V, output voltage is 10V. While input voltage Vi is less than Vref=2V, output
voltage is -10V. Figure 10.31 shows the output voltage waveform, when Vref = 2V and Vi=10 sin ωt in Fig.
10.29. If input voltage Vi is less than Vref = 2V, output voltage is 10V. When input voltage Vi is greater than
Vref =2V, output voltage is –10V.
 408 Digital Electronics: Principles and Applications

Fig. 10.30 Input and output voltage waveforms

Fig. 10.31 Output voltage waveform

10.8.2 OP AMPs as BISTABLE

Figure 10.32 shows the bistable circuit using operational amplifier.
This circuit has +ve feedback as the output of operational amplifier is
connected to the non-inverting terminal. The virtual short principle
between inverting and non-inverting terminals will not be applied
due to absence of negative feedback and V+ ≠ V-.
In this operational amplifier circuit, R1 and R2 behave as voltage
dividers. The voltage at non-inverting terminal will be
R2 R2 Fig. 10.32 Bistable circuit
V+ = V0 = bV0 , where b =
R1 + R2 R1 + R2
 Multivibrators 409

If the output of circuit is +VCC or V0 = VCC, then V+ = bV0. As long as Vd = (V+ – V–)> 0, circuit output
will be +VCC. If Vi is increasing, after some time V+ = V– = bVCC. As Vi is continuously increasing, when
Vi is greater than V+, Vd = ( V+ – V–)<0 or becomes negative. Then output of operational amplifier will
be changed from +VCC to –VCC. Then V+ = –bV0 = –bVCC. As V+ becomes negative and force the output
of operational amplifier to become negative. This is continuing until operational amplifier is saturated.
Then output voltage is V0 = –VCC. Figure 10.33 shows the transfer characteristics of circuit.

Fig. 10.33 Input-output characteristics (a) increasing Vi (b) decreasing Vi

(c) complete characteristics

The transfer characteristics of the bistable circuit is hysteresis as the output changes state at different
values of Vi depending on whether Vi is decreasing or increasing. The bistable circuit has two switching
points: + bVCC and –bVCC. The operation of the bistable circuit are shown in Fig. 10.33 (a) and (b). The
complete operation is also shown in Fig. 10.33(c). When Vi in between + bV0 and – bV0, the circuit
will be in one of its two possible states. The output state of the circuit can be changed by applying an
input signal Vi > bVCC to the circuit. This input pulse can be of a very short duration. This input signal is
referred to as a trigger signal. On the other hand, the state of the circuit can also be changed by applying
a negative pulse with Vi < –bVCC.
The center of the hysteresis band can be shifted at different voltage by adding a reference voltage
to the circuit as shown in Fig. 10.34. This circuit is also called a Schmitt Trigger. The operation of
the circuit is explained in this section. Consider the initial state output is V0. Determine V+ and find
the range of Vi for which Vd is positive. When Vi in this range, the comparator output state cannot be
changed. When Vi is out of range, the sign of Vd changes from positive to negative. Then only the
comparator output changes.

Fig. 10.34 (a) Bistable circuit with Vref (b) Complete input-output transfer characteristics
 410 Digital Electronics: Principles and Applications

Here Vd = V+ – V– = V+ – Vi
V0 - Vref
The current through R1 and R2 is i =
R1 + R2
R2 R2 R1
Then V+ - Vref = iR2 = (V0 - Vref ) and we get V+ = V0 + Vref
R1 + R2 R1 + R2 R1 + R2
If V0 = VCC and Vd>0; Vd = V+ – V– = V+ – Vi >0, and the range of Vi for the Schmitt trigger will
R2 R1
remain in this state, can be determined form Vi <V+ where, V+ = VCC + Vref
R1 + R2 R1 + R2
Therefore, the comparator output is in the high state and it stays in the high state until the condition
of Vi < VTH is violated. The transfer characteristic is shown in Fig. 10.34(b).
–
Consider V0 = Vs = –VCC and Vd<0
R2 R1
Then V+ = Vs- + Vref
R1 + R2 R1 + R2
As Vd = V+ – V– = V+ – Vi < 0, the range of Vi for the Schmitt trigger will stay in the current state can
be determined from Vi > V+.
R2 R1
Vi > VTL = V+ = Vs- + Vref
R1 + R2 R1 + R2
As a result, the comparator is in the low state and stays in the same state until Vi >VTL .
The range of Vi is VTL < Vi < VTH

R2 R1 R2 R1
or Vs- + Vref < Vi < Vs+ + Vref – +
Where Vs = –VCC and V s = VCC
R1 + R2 R1 + R2 R1 + R2 R1 + R2
The range of Vi is called the dead band. The input signal should pass completely through this band
– +
before the output of trigger switches from one state to another. The value of Vs and V s are always chosen
based on the desired value of the comparator output voltages.

Example 10.3 In Fig. 10.34, Vref = 4V and a Vi = 10 sin w t, determine VTL and VTH. Draw the output
voltage waveform. Consider R1=R2=1 K ohm.

� Solution
The VTL and VTH voltages can be expressed as
R2 R1 R2 R1
VTL = VS- + Vref ; VTH = VS+ + Vref
R1 + R2 R1 + R2 R1 + R2 R1 + R2
– +
As R1=R2=1 Kohm, VS = –10V , VS = +10V and Vref = 4V
10 4 10 4
VTL = - + = - 3V : VTH = + = 7V .
2 2 2 2
Figure 10.35 shows the output waveform when Vref = 4V and a Vi = 10 sinwt
 Multivibrators 411

Fig. 10.35

10.8.3 OP AMPs as ASTABLE Multivibrator

Fig. 10.36 Bistable circuit with RC feedback Fig. 10.37 Astable multivibrator

Figure 10.36 shows astable multivibrator which consists of bistable circuit and a RC feedback loop. This
circuit can be used to generate square waveform. The operation of the circuit is explained below:
The bistable circuit has two states +VCC and –VCC. Initially, consider the output of bistable circuit is
+VCC. Then the capacitor is charged through resistance and the voltage across the capacitor increases
 412 Digital Electronics: Principles and Applications

with a time constant RC. The voltage of capacitor moves toward +VCC. The capacitor voltage is used as
input of bistable circuit. When the capacitor voltage is more than the threshold voltage, VTH, the bistable
circuit is triggered and its output voltage changes from +VCC to –VCC. As –VCC is applied to the capacitor,
the capacitor discharges with the constant RC. Then the voltage of capacitor moves toward –VCC. As
soon as the voltage across the capacitor is VTL, the bistable is triggered again and output changes from
–VCC to +VCC. In this way, the switching takes place and a square wave will be generated at the output
of the bistable circuit. As this circuit has no stable state, it is called astable multivibrator. Therefore, an
astable multivibrator is a combination of a Schmidt trigger and an RC circuit. Figure 10.37 shows the
astable circuit. This circuit has both negative and positive feedback.
In Fig.10.37, resistance R2 and R3 act as a voltage divider. Therefore, the voltage at non-inverting
R2
terminal is V+ = V0
R2 + R3
The current input to inverting and non-inverting terminals is zero (i+=i–=0). So, RC part of the circuit
acts independently. Initial voltage across the capacitor is Vc(t0) at t = t0. When voltage Vo is applied to this
circuit, the voltage across the capacitor at time t will be
t - t0
-
Vc (t ) = V0 + [Vc (t0 ) - V0 ]e t as capacitor is charging.
where t = R1C the time constant of the RC circuit.
If Vd>0, V0 = Vs+. The RC circuit and voltage
divider R2 and R3 operate differently. So, sudden
change in output voltage can effect on sudden
change in V+ . But V– cannot changes suddenly
as the voltage across the capacitor has to be
continuously charged or discharged. There
is some delay in the response of RC circuit.
Actually this delay is used to generate the square
wave output. The voltage across capacitor VC
and output voltage VO are depicted in Fig.10.38.
At t0=0, Vc(t0)=0 and V0 = Vs+ = VCC, the
voltage across capacitor can be expressed as Fig. 10.38 Output voltage and capacitor voltage
t
-
V- = Vc (t ) = Vs - Vs e t

At time t = 0, V– = 0. When time increases, V– increases. At time t1, capacitor voltage will exceed
R2
V+ = Vs+ . Then Vd is negative and it forces the comparator output to become Vs–(–VCC).
R2 + R3
The time period of square wave is T=2(t2-t1) and its expression can be derived as follows:
t - t1
R2 - 2
V- (t2 ) = VC (t2 ) = - VCC + (VCC + VCC )e t
R2 + R3
R2
V+ (t2- ) = - VCC
R2 + R3
 Multivibrators 413

–
Where t2 is the time very close to t2 but smaller than t2. The comparator switches to other
state if V–(t2) = V+(t2–). After equating the above equations for V–(t2) and V+(t2–), we get
t - t1
R2 - 2 R2
-VCC + (VCC + VCC )e t = - VCC
R2 + R3 R2 + R3

t - t1
R2 - 2 R2 R3
Or ( + 1)e t =1- =
R2 + R3 R2 + R3 R2 + R3
t -t
- 2 1 R3 t2 - t1 2 R + R3
Or e t = Or = ln 2
2 R2 + R3 t R3

Ê 2 R2 ˆ
Therefore, T = 2(t2 – t1) = 2t ln Á + 1˜ where t = RC
Ë R3 ¯

In this way, a square-wave is generated by the circuit. The

amplitude of the square wave is set by the saturation voltage of
the Op Amp (Vs+ and Vs–) and a period T can be determined by
the above formula. The period of this oscillator is controlled by
R2 and R3. Generally, R2 and R3 are chosen in the range of tens
of K ohm.
When two zener diodes (VZ1 and VZ2) are connected back
to back across the output, the output voltage will be depend
on forward biased and reverse biased voltage of zener diodes
as shown in Fig.10.39. When V+ is greater than V-, the output
voltage is positive and can be expressed as V0 = VD + VZ. When
Fig. 10.39 Astable multivibrator V+ is less than V-, the output voltage will be negative and can
using operational amplifier with be expressed as V0 = –(VD + VZ) where VD is the voltage across
output voltage limiter, Zener diode forward bias zener diode and VZ is the Zener voltage.

10.8.4 OP AMPs as MONOS-

TABLE Multivibrator
Figure 10.40 shows the monostable multi-
vibrator using operational amplifier. This circuit
has one stable state (HIGH) and one quasi stable
state (LOW). When external trigger pulse is
applied, the output changes states from stable
state to quasi-stable state or HIGH to LOW and
after certain time depending upon the circuit
parameters, output return back to stable state.
When no trigger pulse is applied, the input
Fig. 10.40 Monostable multivibrator using
voltage V+ is greater than V- and output is V0, operational amplifier
 414 Digital Electronics: Principles and Applications

i.e., positive and the circuit is under steady state condition. In this case, the capacitor C charges through
R1, but the capacitor voltage can not able to increase than the forward voltage drop across D1 (VD). The
resistance values are selected
in such a way that V+ is greater
than VD.
As soon as a negative trigger
pulse is applied, the non-invert-
ing input voltage, V+ becomes
less than inverting voltage,
V- and output voltage changes
from +V0 to –V0 . The capaci-
tor C stars to charge through R1
and moves towards –V0. In this
condition, diode D1 is reverse
biased and acts as open cir-
cuit. After some time, the volt-
age across capacitor C, (VC)
or V- becomes more negative
than V+, then the output again
Fig. 10.41 Waveforms of monostable multivibrator
changes from low quasi-stable
state to high stable state. Figure 10.41 shows the waveform of the monostable multivibator.
The voltage across the capacitor can be expressed as
t
-
VC = - V0 + (V0 + VD )e t

where, t = R1C
At time t = t1, VC = –bV0
The pulse width duration is T and can be expressed as
Ê 1 + VD / V0 ˆ
T = t ln Á
Ë 1 - b ˜¯
where, VD is the forward bias voltage drop across diode D1 and V0 is the output voltage
R3
and b =
R3 + R2
As V0 >>VD, and if R1=R2, the time period can be expressed as
Ê ˆ
Á 1 ˜ 1
T = t ln Á ˜ , as VD / V0 = 0 and b =
1 2
Á1 - ˜
Ë 2¯
T = 0.69R1C
 Multivibrators 415

Example 10.4 Figure 10.40 shows monostable multivibrator. Determine the circuit elements for
T = 10µs and draw the voltage across capacitor and output voltage waveform. As-
sume VD= 0.6V and VZ = 9V.

� Solution
Ê 1 + VD / V0 ˆ
We know that T = t ln Á
Ë 1 - b ˜¯
R3 1
and b = = as R2=R3=10 K ohms
R3 + R2 2
After substituting VD= 0.6V and VZ=9V=VO , we get
Ê ˆ
Á 1 + 0.6 / 9 ˜ Ê 1.0667 ˆ
T = t ln Á = t ln Á = 0.7576t = 0.757
76 R1C
1 ˜ Ë 0.5 ˜¯
Á 1 - ˜
Ë 2 ¯
As T=10s , 10s = 0.7576R1C
If C=10pF, R1=1.32K ohm.
Figure 10.42 shows the voltage across the capacitor and output voltage.

Fig. 10.42 Voltage across capacitor and output voltage

10.9 555 TIMER

The pin diagram IC 555 is shown in Fig.10.43. Figure 10.44
shows the block diagram of 555 timers. The 555 timers consist
of two voltage comparators, a bistable flip-flop, a discharge
transistor, and a resistor divider network. The resistive divider
network is used to set the comparator levels. Since all three
resistors are of equal value, the threshold comparator (COMP-
1) is referenced internally at 2/3 of supply voltage level and the
Fig. 10.43 Pin diagram of 555 IC trigger comparator (COMP-2) is referenced at 1/3 of supply
 416 Digital Electronics: Principles and Applications

voltage. The outputs of the comparators are tied to the bistable flip-flop. When the trigger voltage is
moved below 1/3 of the supply, the comparator - 2 changes state and sets the flip-flop driving the output
to a high state. The threshold pin normally monitors the capacitor voltage of the RC timing network.
When the capacitor voltage exceeds 2/3 of the supply, the threshold comparator (COMP-1) resets the
flip-flop, which in turn drives the output to a low state. When the output is in a low state, the discharge
transistor is “on”, in that way discharging the external timing capacitor. Once the capacitor is discharged
to 1/3 of supply voltage, the timer will again triggered and the next timing cycle will be started.

Fig. 10.44 Block diagram of 555 timer IC

10.9.1 Astable Operation Of 555 Timer

Figure 10.45 shows the 555 timers IC that is operate in astable mode. Here, pin 5 is not used. The three
internal resistances (R’s) divide the voltage into three parts. Therefore, V7=2VCC/3 and V2=VCC/3. While the
capacitor is charging and the capacitor voltage is between
2VCC/3 and VCC/3, the output of neither of the comparator
undergoes a change in the sign of their output, which is
negative and therefore logic 0. If the capacitor is charging
and its voltage tends to rise above 2VCC/3, the comparator-
1 (COMP-1) output jumps to positive saturation value, i.e.
it is logic 1 at R input of flip-flop. Similarly, when the
capacitor is discharging and its voltage tends to fall below
VCC/3 and the comparator-2 (COMP-2) output jumps to
positive saturation value or logic 1 at S input of flip-flop.
Initially, consider R=S=0 and the capacitor voltage
–
must be VCC/3 <VC <2VCC/3. The flip-flop output Q = 0
and Q=1. As voltage applied to the base of transistor is 0, Fig. 10.45 Astable operation of 555
timer IC
it is in OFF state. Therefore, the capacitor continuously
charging through resistance R1 and R2. Then output voltage V0 is high.
When the capacitor voltage reaches 2VCC/3, output of comparator -1 (COMP-1) changes from 0 to 1.
–
Hence R=1, S=0 and Q =1. As a result, the transistor goes ON and output voltage Vo becomes low. Then
capacitor starts to discharges towards 0V through the resistance R2. Hence capacitor voltage starts to
 Multivibrators 417

decrease. As the capacitor voltage decreases, the output of comparator-1 (COMP-1) changes from 1 to
–
0. In this time, R=0, S=0. and the flip-flop output Q=0 and Q =1.
As soon as the capacitor voltage becomes less than VCC/3, the comparator-2 (COMP-2) output goes
–
to 1. Then R=0, S=1 and the flip-flop output Q is equal to 0. Consequently, the transistor goes OFF and
output voltage V0 becomes high. After that, next cycle of operation is started again. Figure10.46 shows
the output voltage V0 and capacitor voltage VC waveforms.

Fig. 10. 46 Capacitor voltage waveform VC as shown as A and

Output voltage waveform Vo as shown as B
When the capacitor is charging, voltage may be expressed as
2 1
VC (t ) = VCC (1 - e- t /( R1 + R2 )C ) + VCC
3 3
2
At a time t = T1 VC = VCC
3
2
After substituting t = T1 and VC = VCC in the above equation, we get
3
T1=C(R1+R2). ln 2 = 0.693C (R1+R2)
During discharging the capacitor voltage is
2
VC (t ) = VCC e- t / R2C
3
1
At t = T2 , capacitor voltage VC = VCC
3
1
After substituting t = T2 and VC = VCC in the above equation, we find T2 = R2C ln2=0.693CR2
3
The total time period T= T1+T2= 0.693(R1+2R2) C
1 1
Output frequency, f = =
T1 + T2 0.693C ( R1 + 2 R2 )
T1
Duty cycle, D =
T1 + T2
 418 Digital Electronics: Principles and Applications

As the capacitor charges through resistors R1 and R2

and discharges through resistor R2 only, the charging
and discharging times are not equal. As a consequence,
the output is not a symmetrical square wave. This is
possible if R1 is nearly zero. But it is not possible. To
obtain an square wave output, R1 will be very small
compared to R2. Then charging and discharging times
depends on R2 and C. The frequency of the square wave
is approximately 1/0.693(R1+2R2)C.
The other alternative method to generate a
square waveform is that the charging path of astable
multivibrator is independent of R2 as shown in
Fig.10.47. Then charging and discharging time can be
expressed as given below:
Fig. 10.47 Duty cycle reduction of 555IC
Charging time T1=0.693R1C and discharging time
T2=0.693R2C
When R1=R2 , T1 is equal to T2
To achieve a square waveform, two diodes are connected as shown in Fig. 10.48. There is independent
control of the charge and discharge times. The timing capacitor charges through D1 and R1 and discharges
through R2 and D2.
The total time period=T1+T2=1.386 R2C
1 0.722
Output frequency f = =
T R2C
To get a absolutely symmetrical square wave, the timer output is to connect to a toggle flip-flop.

Fig. 10.48 Improved square wave using 555 timer

Voltage Controlled Oscillations

To vary the frequency of astable multivibrator output, the control terminal pin - 5 of the 555 timers IC is
used. Consider pin - 5 is connected to V volts and VCC ≥ V. Then threshold voltage of the comparators 1
 Multivibrators 419

and 2 are +V and +V/2 respectively. The output voltage and capacitor voltage waveforms are shown in
Fig. 10.49 when for 2VCC/3 >V. Then charging and discharging time as follows
È V ˘
Í1 - 2V ˙
CC ˙
T1 = C ( R1 + R2 ) ln Í
Í 1- V ˙
ÍÎ VCC ˙˚
T2=CR2ln2.
It is clear from the charging time equation that
the charging time is reduced but discharging time
does not affected. Therefore, controlling voltage at
pin 5 can vary the oscillator frequency.
Fig. 10.49 Voltage control oscillator wave- The square wave with different frequency can be
forms when pin 5 used to control generated by proper selection of R1, R2 and C. R1 and
frequency
R2 can be varied widely and its range is 1Kohm to
1Mohm. But the capacitance choice is very limited as capacitance is available in few ranges. Therefore,
during the design of multivibrator, initially choose the capacitance value. The different values of C
are 0.001µF, 0.01µF, 0.1µF, 1µF, and 10µF. Then determine the resistance value using the following
expression
0.7
R2 = , when R1 is smaller than R2.
fC

If the required on time is greater than off time, choose resistance R1 which will be approximately ten
times of R2. During the selection of variable resistance, it is best if R2 is variable. If R1 is variable, a fixed
resistance about fraction of 1Kohm is connected in series with variable resistance. Table 10.1 shows the
frequency of astable multivibrator at different value of capacitance and resistances.
Table 10.1 Frequency of astable multivibrator 555

Capacitance C R1=1K, R1=5K, R1=10K, R1=5K, R1=100K,

R2=10K R2=50K R2=100K R2=500K R2=1M
0.001µF 68 kHz 13.7 kHz 6.8kHz 1.37 kHz 680Hz
0.01µF 6.8 kHz 1.37 kHz 680Hz 137 Hz 68Hz
0.1µF 680Hz 137 kHz 68Hz 13.7Hz 6.8Hz
1µF 68Hz 13.7 Hz 6.8Hz 1.37 Hz 0.68Hz
10µF 6.8Hz 1.37 Hz 0.68Hz .137 Hz 0.068Hz
The application of astable multivibrator is the clock signal of flip-flops registers and counters. The
low frequency astable multivibrator (f<10Hz) can be used to turn on and off LED and develop flash.
The audio frequency astable multivibrator (20KHz ≥ f ≥ 20Hz) can be used to develop sounds from a
speaker or a piezo transducer.

Example 10.5 Calculate the frequency and duty cycle of the output of an astable multivibrator-
using timer 555. Assume R1=25K ohm, R2=50Kohm and C=0.1µF.
 420 Digital Electronics: Principles and Applications

� Solution
The frequency is equal to
1 1.443 1.443
f = = = KHz = 0.1154KHz
0.693( R1 + 2 R2 )C ( R1 + 2 R2 )C (25 + 2 ¥ 50) ¥ 0.1
R1 + R2 25 + 50
and Duty cycle = = = 0.6 = 60%
R1 + 2 R2 25 + 2 ¥ 50

Example 10.6 An astable is shown in Fig. 10.45. It has output frequency 10KHz with duty ratio
60%. Calculate the value of R2 and C if R1=3K ohm.

� Solution
1 1
Time period=T=T1+T2=0.693(R1+2R2) C = = ms
f 10
Choose C= 0.01µF
Therefore (R1+2R2)=14.43Kohms
As R1=3K ohm , R2 will be 5.7 K ohms
R + R2 3 + 5.7
Duty ratio, D = 1 = = .6029 = 60%
R1 + 2 R2 14.43

Example 10.7 The clock output frequency of an astable oscillator is 100KHz , R1 is 2K and R2 is 5K.
Determine the timing capacitor required for the astable oscillator.

� Solution
The capacitor value is equal to
1.443 1.433
C= = F =0012F
f ( R1 + 2 R2 ) 100(2 + 2 ¥ 5)

10.9.2 Monostable Operation Of 555 Timer

The monostable multivibrator has a stable and a
quasi-stable state. Therefore, it is also called as
one shot. When the output Q is logic 0, flip-flop
is in reset state. If the trigger pulse is applied, the
output will be high state or Q=1 and it will return
to low state after a fixed duration of time. The
duration of the pulse is called the time period (T)
and this can be determined by using resistor R1
and capacitor C.
Figure 10.50 shows the monostable multi-
vibrator using 555 timer IC. Initially, consider
the trigger voltage is more than VCC/3 and output Fig. 10.50 Monostable multivibrator
 Multivibrators 421

– –
voltage V0 is low as Q=0 and Q =1. As Q =1, the transistor Q1 is ON and the capacitor will be fully
discharged. The threshold and trigger comparator outputs are low. Hence R=0 and S=0. The monostable
multivibrator can be triggered when the trigger input is less than VCC/3.
After the trigger applied, the trigger comparator output momentarily changes from low to high and
–
flip-flops inputs are R=0, S=1. Accordingly, Q=1 and Q =0, the transistor Q1 will be OFF and capacitor
starts to charge towards VCC through R1.
When capacitor voltage VC reaches
the value of 2VCC/3, the threshold
comparator output will be high and
flip-flops inputs will be R=1,S=0.
Then output voltage V0 becomes low
–
as Q=0 and Q =1. The transistor Q1 is
–
ON due to Q =1 and the capacitor is
fully discharged very firstly as turn
on resistance of the transistor is small.
In this way, cycle will be completed
Fig. 10.51 Waveform of monostable multivibrator
and the capacitor is ready for the
next trigger. Figure 10.51 shows the capacitor voltage and output voltage waveforms of monostable
multivibrator.
The capacitor voltage during charging can be expressed as
È t ˘
-
VC (t ) = VCC Í1 - e R1C ˙
Í ˙
Î ˚
At t = T1 , capacitor voltage VC=2VCC/3.
So, T1=R1 C ln 3=1.1R1C
Time period of the pulse is T1=1.1R1C.
The pulse width of monostable multivibrator output can be varied by using the control pin - 5. If
a positive voltage V is applied to pin no. - 5,
the threshold of the comparator will be changed
from 2VCC/3 to V volts. Therefore, the pulse
width of the waveform will be changed to T '1
which can be determined by the expression
given below:
È V ˘
T1¢= R1C ln Í CC ˙
Î VCC - V ˚
10.9.3 Bistable (Flip-flop) Op-
eration Of 555 Timer
Figure 10.52 shows the bistable multivibrator
using 555 timer and it has two stable states:
output high and output low. Therefore, it is also
called as flip-flop. This circuit has two inputs:
trigger and reset. Initially, output is low. Tigger Fig. 10.52 Bistable multivibrator using 555 timer
 422 Digital Electronics: Principles and Applications

makes the output high when trigger input voltage less than VCC/3, 555-timer output will be changed from
low to high. Reset makes the output low when reset pin voltage less than 0.7VCC, output will be changed
from high to low.

Example 10.8 Determine the pulse width of the output waveform of a monostable multivibrator as
shown in Fig. 10.50 if R1=100K and C=0.1F

� Solution
Pulse width of the output waveform is T=1.1R1C= 1.1×100×0.1 ms=11ms

10.10 APPLICATIONS OF 555 TIMER

The 555 timers can be used in electronic circuits in different ways. The basic broad use of the 555 timer
circuit is either monostable or astable multivibrator. The other applications are missing pulse detector,
precision timing, pulse generation, sequential timing, time delay generation, pulse width modulation,
pulse position modulation, linear ramp
generator, dark detector, power alarm,
electric eye alarm, tilt switch, metro-
nome, 10-minute timer, continuous
wave oscillator, Schmitt trigger, etc.
Some of the above applications are
explained below.

Missing Pulse Detector Fig-

ure 10.53 shows the missing pulse
detector. This circuit is one shot and
it is continuously retriggered by the
input pulse train. A missing pulse can
prevents retriggering before comple-
tion of the timing cycle. Then output Fig. 10.53 Missing pulse detector
will be low till a new input pulse ar-
rives and continuous alarms will be
developed for a missing pulse.

Electric Eye Alarm Figure

10.54 shows the electric eye alarm. A
light dependent resistance (LDR) is
used to sense light. When light falls
on the LDR, it will be shorted and the
timer circuit will be reset. The pitch of
speaker can be controlled by varying
resistance R2.

Fig. 10.54 Electric eye alarm

 Multivibrators 423

Dark Detector Dark detector circuit is shown in Fig. 10.55. It is used to detect darkness all of a sud-
den. The light dependent resistance (LDR) is used to detect darkness or illumination below a limit value.
Due to absence of light, LDR will be short and circuit will be reset. Then speaker develop the alarm.
Metronome Metronome is used in the music industry to produce the rhythm by a ‘toc-toc’ sound.
The speed of sound can be adjusted by the potentiometer R1 as shown in Fig.10.56.

Fig. 10.55 Dark detector Fig. 10.56 Metronome

10-minute Timer Figure 10.57

shows the 10-minute timer circuit. This
circuit can be used as a time-out warn-
ing at every ten minutes. It is difficult to
keep track of time for longer duration.
When the reset switch is pressed, the
green light (D2) ON and time cycle will
start. After 10 minutes, Red light (D1)
Fig. 10.57 The 10-minute timer will be ON to warn the operator for
specific operation.

Schmitt Trigger Figure 10.58 shows Schmitt

trigger. It removes any noise signal in input and
square wave is output signal. The output frequency
is input frequency divide by 2.

Pulse Sequencer Sometimes, the sequence

of pulses are required in certain digital circuits. The
pulse widths may be equal width or unequal width,
but they must comes one after the other. Gener-
ally, pulse sequencer is used to generate a series of
Fig. 10.58 Schmitt trigger pulses in time sequence. Figure 10.59 shows a pulse
 424 Digital Electronics: Principles and Applications

sequencer circuit, which is actually cascade connection of monostable multivibrators. Here, only two
pulses A and B are sequentially generated as shown Fig.10.60.

Fig. 10.60 Pulse

sequencer output
Fig. 10.59 Pulse sequencer circuit waveform

The sequence starts with the falling edge of the trigger pulse. The first monostable multivibrator is
edge triggered and output A changes from low to high. Output A will remain high for certain duration
depending upon the circuit parameters and then return back to low state. At that time, the next monostable
multivibrator will be triggered and output B changes from low to high. Then output B will remain high
for certain duration depending upon resistance and capacitance and again return back to low state. In
this way, two sequence pulses are generated. At the end of the output B, the sequence is completed and
all timers again wait for the next triggering signal.

10.11 556 TIMER

The LM556 dual timing circuit is a highly stable controller capable of producing accurate time delays or
oscillation. The 556 is a dual 555 timer as
shown in Fig.10.61. Timing is provided
by an external resistor and capacitor for
each timing function. The two timers
operate independently of each other
sharing only VCC and ground. The circuits
may be triggered and reset on falling
waveforms. The output structures may
sink or source 200mA. It has following
features
• Direct replacement for SE556/
NE556
• Timing from microseconds through
hours
• Operates in both astable and monos-
table modes
• Replaces two 555 timers Fig. 10.61 Pin diagram 556 timer
• Adjustable duty cycle
 Multivibrators 425

• Output can source or sink 200mA

• Output is TTL compatible
• Temperature stability better than 0.005% per °C

Example 10.9 Figure 10.62 shows the connection of 556. Draw the output waveform and deter-
mine the pulse width of the output waveforms. Consider R1=1K ohm , R3=10K ohm
and C1=0.1F

Fig. 10.62

� Solution
Figure 10.63 shows the output waveform at A and B.
Pulse width of the output waveform A is TA=1.1R1C1= 1.1×1×0.1ms=0.11ms
Pulse width of the output waveform B is TB=1.1R3C1= 1.1×10×0.1ms=1.1ms

Fig. 10.63 Output waveform at A and B

Example 10.10 Draw a circuit diagram to control speed of a DC motor using 555 timer.

� Solution
Figure 10.64 shows the speed control of DC motor using 555 timer. Here, the motor speed can be controlled
by varying resistance R2.
 426 Digital Electronics: Principles and Applications

Fig. 10.64 Speed control of DC motor using 555 timer

10.12 74121 MONOSTABLE MULTIVIBRATOR

The pin diagram of 74121 IC is shown in Fig.10.65.This IC has three trigger inputs: two negative edge-
— —
triggering inputs A1 and A2 , and one positive edge schmitt-triggering input B. This 74121 IC is a non-
retriggerable one shot. It will respond to a trigger input only when it is in its stable state. The output of
the monostable multivibrator will return to the low state after a certain period, which can be determined
by the values of external resistance (REXT ) and capacitance ( CEXT).
— — — —
Table 10.2 shows the functional table of IC 74121. When A1 is low or A2 is low or both A1 and A2 are low
and B have a transition form low to high (↑), multivibrator
will be triggered. The other method of triggering is that B
— —
is high, any one of A1 and A 2 has a transition from high
to low (↓). The duration of output pulse will depend on
the values of the resistor and capacitor in the circuit. An
initial resistor RINT of 2K ohm is built into the IC and it can
be made effective by connecting pin 9 to pin 14, +VCC. If
only the internal resistance is used without any external
capacitor, a minimum pulse width of about 35 ns may be
obtained. If an external resistance and capacitance are used,
pulse width depends on REXT and CEXT. Generally, REXT can
be varied from 1.4K to 40K ohm and CEXT may have a value Fig. 10.65 Pin diagram of 74121 IC
up to 1000µF. A maximum pulse width of about 28 s may be achieved with proper choice of REXT and
CEXT. Pulse width can be calculated from Tw=0.693 REXT CEXT.
The schematic diagram of monostable multivibrator using IC 74121 is shown in Fig.10.66. Here, pin 5
(B) is used for the input trigger signal and the IC will be triggered on a positive input pulse. When a trigger
input activates the device, the Q output will be HIGH as depicted in the timing diagram, Figure 10.67. The
length of the pulse width (Tw) can be determined using the formula Tw =0.693 REXT CEXT.
 Multivibrators 427

Table 10.2 Functional table of IC 74121

— Inputs
— Outputs –
A1 A2 B Q Q
L X H L H
X L H L H
X X L L H
H H X L H
H ↓ H
↓ H H
↓ ↓ H
L X ↑
X L ↑

Fig. 10.66 One shot trigger of monostable Fig. 10.67 Timing diagram of monostable
multivibrator IC 74121 multivibrator IC 74121

IC74121 is a non-retriggerable monostable multivibrator and it responses to a positive trigger pulse when it
is in stable state. When it is in quasi stable state after triggering, it will not respond to next trigger pulse until it
returns back to stable state. Therefore, this circuit is known as non-retriggerable IC. Figure 10.68(a) shows the
waveform of non-retrigger-
able monostable multivibra-
tor 74121 when interval of
triggering pulses are greater
than output pulse width Tw.
In Fig.10.68(b), interval of
triggering pulses are less than
output pulse width Tw but ad-
ditional pulses does not af-
fect in output as these extra
Fig. 10.68 Timing diagram of non retriggerable one shot multivibrator pulses are always ignored.
 428 Digital Electronics: Principles and Applications

Example 10.11 Determine the pulse width of monostable multivibrator output as shown in
Fig. 10.66 if REXT = 100K and CEXT = 0.01µF

� Solution
Pulse width of monostable multivibrator output Tw =0.693 REXT CEXT =0.693×100×0.01ms=0.693ms.

Example 10.12 A pulse with 100 µs pulse width will be generated from IC74121. Determine the
resistance and capacitance values, which are used in IC 74121 circuit.

� Solution
Pulse width of monostable multivibrator output Tw =0.693 REXT CEXT = 100µs
Consider CEXT =0.01µF
100
Then REXT = ohms=14.43K ohm
0.693 ¥ 0.01

10.13 74122 RETRIGGERABLE MONOSTABLE MULTIVIBRATOR

When the monostable multivibrator is in quasi-stable state and responses to a trigger pulse, the circuit
is called as retriggerable IC. Figure 10.69(a) shows the waveform of a retriggerable monostable
multivibrator when interval of triggering pulses are greater than output pulse width Tw. This output will
be same as non-retriggerable monostable multivibrator. If the interval of triggering pulses are less than
output pulse width Tw , monostable multivibrator will retriggered and pulse width will be extended as
depicted in Fig. 10.69(b).

Fig. 10.70 Pin diagram of 74122

Fig. 10.69 Timing diagram of retriggerable
monostable multivibrator Table 10.3 Functions of Pins

IC 74122 is a retriggerable monostable multivibrator Pins Description

as shown in Fig.10.70. Logic diagram and logic — —
A1 and A 2 Trigger (active LOW) inputs
symbol of IC 74122 are depicted in Fig.10.71 and B1 B2 Trigger (active HIGH) inputs
Fig.10.72 respectively. Table 10.3 shows the function —
RD Direct reset (active LOW) input
of pins. This monostable multivibrator has one more
Q Pulse(active HIGH) output
active high trigger input, and an asynchronous –
— — Q Pulse(active LOW) output
CLEAR input compare to IC74121. Inputs A1 and A 2
 Multivibrators 429

are negative edge trigger, while B1 and B2 are positive edge trigger. Table 10.4 shows the functional
— —
table of monostable multivibrator. If A1 and A 2 are grounded and B2 is high, B1 can trigger the monostabe
IC when its voltage changes from low to high. Then device output will be high for some time duration
depending upon the circuit resistance and capacitance. If B1 and B2 are high, the monostabe IC can also
— —
be triggered when A1 and A 2 inputs changes from high to low transition. If the CLEAR input is activate
by making it low, the output will go low at the same time and will stay low. When the clear input is low,
the IC will not respond to negative edge triggering as well as positive edge triggering.

Fig. 10.71 Logic diagram of 74122

Fig. 10.72 Logic symbol of 74122

Table 10.4 Functional table of IC 74122

— — Inputs Outputs –
CLEAR A1 A2 B1 B2 Q Q
L X X X X L H
X H H X X L H
X X X L X L H
X X X X L L H
H L X ↑ H
H L X H ↑
H X L ↑ H
H X L H ↑
H H ↓ H H
(Contd...)
 430 Digital Electronics: Principles and Applications

Table 10.4 (Contd.)

H ↓ ↓ H H
H ↓ H H H
↑ L X H H
↑ X L H H

Figure 10.69(a) shows the retriggering action of 74122 when the interval between trigger pulses
is greater than the plush width output. Using 74122 pulse width can be extended. In Fig.10.69(b), the
device is triggered by the first triggering pulse and output will be high. After very short time interval,
another trigger pulses arrives and the
device again triggered. Therefore,
output pulse width can be extended as
shown in the timing diagram.
An external timing capacitor is
connected between Cext and Rext/Cext. To
use the internal timing resistance, Rint
is connected to VCC. To improve pulse
duration accuracy and repeatability, an
external resistor is connected between
Rext/Cext and VCC with Rint open circuited.
To get variable durations, an external
variable resistance may be connected
between Rint or Rext/Cext and VCC.
Internal timing resistance, Rint of
74122 is about 10K ohm and Rext may Fig. 10.73 Graph between pulse width (tw )vs Rext and Cext
be varied from 5 to 50K ohms. There
is no limitation on the maximum value of Cext. The output pulse width duration depends on the values
of Rext and Cext. When the external timing capacitor is smaller than 1000pf, the pulse width should be
determined using the timing chart as shown in Fig. 10.73. If the value of the external timing capacitor is
greater than 1000pF, the pulse width duration can be expressed as

Ê 0.7 ˆ
Pulse width, Tw = KRext Cext Á1 +
Ë Rext ˜¯

where, Rext is in Kilo-ohm

Cext is in pico Farad
TW is in nano second
K = 0.28 approximate value and usually given in manufacturer data sheet
 Multivibrators 431

Example 10.13 Calculate the Rext and Cext of 74122 multivibrator to generate a 20µs pulse width.

� Solution
Ê 0.7 ˆ
Pulse width , Tw = KRext Cext Á1 + ˜
Ë Rext ¯

0.7
= KRext Cext + KRext Cext = KRext Cext + 0.7 KCext
Rext
The external resistance in terms of capacitance can be expressed as
T
Rext = (TW – 0.7KCext)/KCext = W - 0.7
KCext
The duration of pulse width Tw=20s
Choose Cext = 0.01µF
From manufacturer data sheet, we get K=0.30
T 20
Therefore, Rext = W - 0.7 = Kohms - 0.7 = 6.66Kohms
KCext 0.3 ¥ 0.01

10.14 RETRIGGERABLE MONOSTABLE MULTIVIBRATOR IC 74123

IC 74123 has two retriggerable monostable multivibrators in one package, but it operates like 74122.
The difference between IC 74122 and IC 74123 is that there is no internal timing resistor in IC 74123.
–
Each retriggerable monostable multivibrator has three inputs: A , B and CLR . This device can be used
–
either positive edge or negative edge triggering. Pin A is an active-LOW transition (negative edge)
trigger input and pin B is an active-HIGH transition (positive edge) trigger input. When CLR input
terminal is low, the device terminates the output pulse. This device has the capability of generating
output pulses from a few nano-seconds to extremely long duration up to 100% duty cycle. Figure 10.74
shows the pin configuration of IC 74123. The logic symbol of IC 74123 is given in Fig. 10.75. The
functional operation of this device is illustrated in Table 10.5.
The output pulse width can be varied by proper selection of an external resistance (REXT) and capacitor
(CEXT). When the device is already triggered once, retriggering using the active-LOW transition (negative
edge) or active-HIGH transition (positive edge) inputs may extend the pulse width as depicted in Fig.
10.76(a). The pulse width can be reduced by using the active-LOW transition clear input as shown in
Fig. 10.76(b). When a train of trigger pulse is applied and cycle time of trigger pulse is shorter than the
output cycle, 100% duty cycle is possible by retriggering as shown in Fig. 10.76(c).
Table 10.5 Functional table of IC 74123

– Inputs Outputs –
A B CLR Q Q
↓ H H
L ↑ H
L H ↑
X X L
X X ↓
432 Digital Electronics: Principles and Applications

Fig. 10.74 Pin diagram of IC 74123

Fig. 10.75 IEEE logic symbol of IC 74123

Fig. 10.76(a)
 Multivibrators 433

Fig. 10.76(b)

Fig.10.76(c)
Figure 10.76 Timing diagram of retriggerable monostable multivibrator using 74123 (a) retriggered
to extend pulse width (b) reduce pulse width with CLEAR (c) 100% pulse width with retriggering

SUMMARY
Clock pulses are required to drive sequential logic circuits and these clock pulses are generated from timing circuits
namely oscillators and multivibrators. In this chapter, clock oscillator-using BJT is explained. The astable multivibrator
has no stable states and it is used as an oscillator to produce a train of rectangular pulses. The monostable multivibrator
has one stable state and it is also called as one shot. This circuit is used to generate a pulse of predefined period
in response to a trigger pulse. The bistable multivibrator has two stable states. This multivibrator output changes
from one stable state to other stable state when trigger pulses are applied. Schmitt trigger circuit is used to convert
irregularly varying signals into rectangular pulses. The astable, monostable and bistable multivibrators using logic
gates, operational amplifiers and 555 timer circuits are incorporated in this chapter. The most commonly used ICs 55
timer, 556 timer, 74121 nonretriggerable one shot, 74122 retriggerable one shot, and 74123 retriggerable one shot are
also explained in this chapter. These ICs are used to generate timing pulses as these are cheap, occupy very little space
and very much reliable.

MULTIPLE CHOICE QUESTIONS

1. An astable multivibrator has
(a) One stable state (c) One quasi-stable state
(b) Two stable state (d) Two quasi-stable state
2. An monostable multivibrator has
(a) One stable state (c) One quasi-stable state
(b) Two stable state (d) Two quasi-stable state
434 Digital Electronics: Principles and Applications

3. An bistable multivibrator has

(a) One stable state (c) One quasi-stable state
(b) Two stable state (d) Two quasi-stable state
4. If an multivibrator has one stable and one quasi-stable, the circuit is called as
(a) Astable multivibrator (c) Bi-stable multivibrator
(b) Monostable multivibrator (d) None of these
5. Pulse stretches is the alternative name of
(a) Monostable multivibrator (c) 555 timer
(b) Flip-flop (d) Schmitt-trigger
6. A 555 timer consists of
(a) Two comparator, one flip-flop and one transistor
(b) Only operational amplifiers
(c) One comparator, one flip-flop
(d) None of these
7. Which multivibraor can able to convert 10µs pulse into a 10ms pulse?
(a) Astable multivibrator (c) Bi-stable multivibrator
(b) Monostable multivibrator (d) None of these
8. A 556 timer IC consists of
(a) Two 555 timer (b) Three 555 timer (c) Four 555 timer (d) None of these
9. A monostable multivibrator consists of
(a) Operational amplifiers (c) 555 timer
(b) Logic gates (d) All of these
10. A Schmitt trigger circuit is a
(a) Monostable multivibrator (c) Free-running multivibrators
(b) Bi-stable multivibrator (d) None of these
11. Which multivibraor IC is non-triggerable ?
(a) 74121 (b) 74122 (c) 74123 (d) None of these
12. 74123 IC is a
(a) Non-retriggerable multivibrator (c) Single triggered monostable multivibrator
(b) Re-triggerable monostable (d) None of these
13. An astable multivibrator can be triggered
(a) When output is high (c) When output is high
(b) When output is low (d) Triggering pulse is not requird
14. The pulse width of retriggerable monostable multivibrator can be controlled
(a) Frequency of trigger pulse (c) Amplitude of trigger pulse
(b) External resistance and capacitor (d) None of these
15. An non-retriggerable monostable multivibrator(one shot) can be triggered
—
(a) When A1 is low and B is low to high (↑)
—
(b) When A2 is low and B is low to high (↑)
— —
(c) When A1 and A2 are low and B is low to high (↑)
(d) All of these
 Multivibrators 435

16. An retriggerable monostable multivibrator can be triggered

— —
(a) When A1 and A2 are grounded and B2 is high, B1 is low to high
— —
(b) When A1 and A2 are +VCC and B2 is high, B1 is low to high
— —
(c) When A1 is grounded, A2 is +VCC and B2 is high, B1 is low to high
(d) None of these
17. A non-retriggerable monostable multivibrator has Rext=10K and Cext=0.01µF. It’s pulse-width will
be
(a) 0.7ms (b) 0.6ms (c) 0.07ms (d) 0.06ms
18. In a IC 555 timer, it will be triggered when trigger input voltage connected is
(a) Less than VCC/3 (c) Greater than VCC/3
(b) Less than 2VCC/3 Between (d) None of these

REVIEW QUESTIONS
10.1 Define multivibrator. What are the types of multivibrator? Explain any one multivibrator with circuit
diagram and waveforms.
10.2 Draw the circuit diagram of monostable multivibrator using BJT and explain its operation.
10.3 Justify that Fig.10.77 behaves as an monostable multivibrator

Fig. 10.77
10.4 Verify that Fig.10.78 behaves as an astable multivibrator

Fig. 10.78
10.5 Explain application of operational amplifier in monostable multivibrator circuit. Why Zener diodes
are used in this circuit?
10.6 Draw the functional block diagram of 555 timer. Explain the operation of different section of 555 timer.
10.7 Describe the monostable operation of 555 timer. Derive a expression to determine the pulse width.
10.8 Draw the voltage waveforms of the Fig. 10.79 at A and B.
 436 Digital Electronics: Principles and Applications

Fig. 10.79
10.9 What are the applications of 555 timer? Explain any two applications briefly.
10.10 What is pulse sequencer? Draw a pulse sequencer circuit and explain it’s operation.
10.11 Consider IC 555 timer is operating in stable mode with R1= 4.7K ohms and R2= 2.2 K ohms. If the
timing capacitor is 0.47F, determine the frequency of oscillations of the multivibrator circuit
10.12 If IC 555 timer is operating as an monostable multivibrator to generate a pulse width of 25µs, give
details of the circuit.
10.13 What are the advantages of Schmitt trigger circuit? Explain the operation of a schmitt trigger circuit
using operational amplifier.
10.14 What is the difference between non-triggerable and re-triggerable monostable multivibrator circuit?
Explain with necessary diagram.
10.15 Draw the logic diagram, truth table and typical waveforms.
(a) 74121 non-triggerable monostable
(b) 74122 retriggerable monostable
(c) 74123 retriggerable monostable
10.16 Determine the frequency and duty cycle of the output of an astable multivibrator-using timer 555 if
R1= 205K ohm, R2= 40K ohm and C = 0.1F.
10.17 Determine the timing capacitor of an astable oscillator when the clock output frequency is 50KHz.
Assume resistance R1 and R2 as per requirement.
10.18 If Vref =-2V and Vi=5 sin ωt in Fig. 10.80, draw the output waveform.

Fig. 10.80

10.19 Calculate the Rext and Cext of 74122 multivibrator to generate a 100µs pulse width.
10.20 A pulse width 10µs pulse width is generated from IC74121. Determine the resistance and capacitance
values, which are used in IC 74121 circuit.
 CHAPTER

11
ANALOG DIGITAL
CONVERSION
11.1 INTRODUCTION
Sensors are used to measure physical quantities, such as temperature, pressure, voltage etc. If the output
of the sensor is digital, the digital circuits can be directly connected to sensor devices as the sensor
devices are intrinsically digital themselves. Then digital circuits directly connected with computer to
store data for further processing. In this way, sensors are used to monitor any physical changes, namely
temperature, pressure, etc. When the output of sensors is analog, the interfacing between computer and
sensor becomes complex. Then it is required to electronically translate analog signals into digital signals.
An analog-to-digital converter (ADC) performs the required task while a digital-to-analog converter
(DAC) performs the reverse operation of ADC. For computer added monitoring signals of analog
sensors, the output of analog sensors are converted from analog to digital. Input signals of ADC are
analog electrical signals such as voltage
or current and outputs of ADC is a binary.
Figures 11.1 (a) and (b)show the analog
signal and digital signals respectively.
Figure.11.2 (a) shows the block
diagram of ADC. The input signal of
ADC is either analog voltage or current
signal but output is digital. In a DAC,
inputs are binary form and output is an
analog voltage or current. Figure.11.2 (b)
shows the block diagram of DAC. Fig. 11.1 (a) Analog Signal (b) Digital Signal

In feed back control system, ADC and

DAC are commonly used to provide complete
interface with analog sensors, computers and
output devices for controlling the system. One
example of control system is speed control
of dc motor. In speed control of dc motor,
Fig. 11.2 (a) ADC Converter and (b) DAC converter
 438 Digital Electronics: Principles and Applications

feedback speed signal is fed to a ADC and output of ADC are connected with computer. In computer, the
required reference speed is compared with feed back speed and generates a digital command signal to
run the motor at reference speed. As the output command of computer is digital one, it is converted into
analog signal by using DAC. Then the output of DAC signal actually controls motor speed. Figure.11.3
shows the block diagram of computer aided
control system using ADC and DAC. It is
very easy to understand the conversion
from digital signal into an analog signal
than from analog to digital. The conversion
of DAC and ADC are explained in Section
11.6 to 11.14.
Fig. 11.3 Computer aided control using ADC and DAC

11.2 SAMPLE AND HOLD CIRCUIT

The analog voltage or current output signal of sensors is continuously
varied with respect of time and there is no break in waveforms of voltage
or current so that every point of time the voltage or current signal
should have an exact value. X-axis stands for time and Y-axis stands
for magnitude of signals. When X-axis is resolved into large number
of small increments, the Y-axis also be same number of divisions. For
each time division, the signal should have a magnitude. Figure.11.4
shows the continuous signal is divided into eight equal parts by
resolving both X and Y co-ordinates into eight equal parts. When
time division is T1, output voltage V1=0. At time division T2, output Fig. 11.4
voltage is equal to V2. Similarly, for time divisions T3, T4 …T8, output
voltages are V3, V4 …… V8 respectively. It is clear from Fig.11.4 that analog voltage signal is converted
into stair case ramp or step signal and this conversion can be done through sample and hold circuit.
A sample and hold circuit samples the input signal at the required instant and then holds it when
analog to digital conversion process is going
on. This circuit operates in two basic modes:
SAMPLE and HOLD. In sample mode, output
follows the input and in hold mode, output
will be constant. Sometimes sample and hold
circuits are also built within ADC ICs.
Figure 11.5 shows the block diagram of Fig. 11.5 Block diagram of Sample and Hold circuit
sample and hold circuit. In this circuit signal
is analog input signal and it is converted into sampled
output by using control signal. Generally in a sample
and hold circuit, switch and capacitor are used as
depicted in Fig.11.6. Here, the capacitor is used as
the storage element. The sampling of analog signal
is shown in Fig.11.7 when a pulse of T1 duration is
applied to transistor switch, transistor will be ON
and allow the sampled analog signal only for T1
duration. After T1 duration, transistor will be OFF Fig. 11.6 Sampling of analog signal
 Analog Digital Conversion 439

for T2 duration. T1 and T2 are called sampling

time and holding time respectively. During
the sampling time, the sample and hold output
follows the analog input signal. It stays at the
final value during the hold period. The simplest
way of making a sample and hold is to use a
capacitor. During the sample time, the capacitor
switches to connect to the analog input voltage.
After that, it connects to the analog to digital
converter during the hold period. This circuit
does not work very effectively, since the ADC Fig. 11.7 Analog input, sampled output and control
is likely to discharge the capacitor rapidly. To signals
improve the performance, a high impedance
buffer is used between the capacitor and the
ADC. Then the capacitor stays charged during
the hold period but there will be a slight drop in
sampled output voltage during the hold period.
If low acquisition time is required, the capacitor
value will be chosen in some pF and in this
case, physical size will be small and slew rate
is high. For low droop and low pedestal error,
the capacitor value will be selected in some
mF.
There are two types of sample and hold cir- Fig. 11.8 Open loop sample and hold circuit
cuits: open loop without feedback and closed
loop with feed back sample hold circuits. Figure 11.8 shows the most simple and fast sample and hold
circuit. The capacitor is charged when the switch is ON. The circuit time constant is RC, where R is sum
of source resistance of analog input voltage Vi and the switch ON resistance. Here, the source voltage Vi
only supplies the necessary charging current of capacitor. The output signal is obtained from unity gain
operational amplifier. Actually, unity gain operational amplifier is used to buffer the voltage across the
capacitor. The operational amplifier is also protecting the voltage from leaking off capacitor.
Figure 11.9 shows the closed loop configuration of sample and hold circuit. This closed loop
configuration improves accuracy at the expense of speed. The input operational amplifier provides quick
charging and discharging of capacitor. The unit gain operational amplifier is used to buffer the voltage
across the capacitor. The ideal operation of
sample and hold circuit is shown in Fig.11.10.
In sample mode, the switch is ON and the
analog signal is sampled on a capacitor. During
hold mode operation, the capacitor voltage is
available at output of operational amplifier. Fig. 11.9 Closed loop sample and hold circuit

Before point A, control signal is high, output voltage follows analog input voltage. At the instant of
point A, control signal changes from high to low, but the switch does not opened momentarily due to
propagation delay. At instant B, switch starts to open and output voltage will be equal to input voltage at
 440 Digital Electronics: Principles and Applications

that point. At point C, switch is completely opened and output voltage does not follows input voltage but
output voltage will be fixed and hold this fixed voltage till the control signal becomes high and switch is
closed. At instant D, control signal becomes high from low, but switch will not be ON momentarily as there
is some ON time delay. Therefore, after certain time delay, switch will be ON and output signal follows
input signal from point E.
In practice, the sampled
signal takes some time to
track to the input signal.
This is known as the ac-
quisition time. The sam-
pled output continues to
track the input signal for
a short period after switch
over. This is known as
the aperture time. Despite
the high impedance of
the buffer, there is an in-
evitable droop in sampled
voltage during the hold
period. These values are
highly exaggerated in this
Fig. 11.10 Operation of sample and hold circuit
section.

Acquisition time (ta )

The time required following a “sample” command, for the output to reach its final value within specified error
± 0.1% or ± 0.01% as illustrated in Fig. 11.10 (c). The time duration DE is actually acquisition time (ta).

Aperture time
The time is required for the sample-and-hold switch to open, and it is independent of delays through
the switch driver and input amplifier circuitry. The switch opening time is that interval between the
conditions of 10% open and 90% open. During the time interval between the sample and hold, switch is
opened and output is settled with in specified error. This time interval is called as aperture time. The time
duration BC is actually aperture time as shown in Fig.11.10. Aperture time is required for the sampling
switch to open after the sample and hold command has switched from sample to hold.

Settling time
The settling time is the time interval between the transition of sample and hold command and the time
when output is settled within a specified error. In Fig 11.10, the time duration AC is known as settling
time (ts) .
The minimum sample and hold time is summation of acquisition time (ta) and settling time (ts).
T=ts+ta
Therefore, the maximum sampling frequency is equal to
 Analog Digital Conversion 441

I 1
f = =
T ta + t s

Effective Aperture Delay Time (EADT)

Effective Aperture Delay Time (EADT) is the difference between the digital delay time from the Hold
command to the opening of the S/H switch, and the propagation time from the analog input to the switch.
EADT may be positive, negative or zero. If zero, the S/H amplifier will generate an output voltage equal
to Vi at the instant the Hold command was received. For negative EADT, the output in Hold (exclusive of
pedestal and droop errors) will correspond to a value of Vi that occurred before the Hold command.
Aperture Uncertainty
It is the range of variation in effective aperture delay time (EADT) due to clock variation and noise.
Aperture uncertainty is also called as aperture delay uncertainty or aperture jitter. It sets a limit on the
accuracy with which a waveform can be reconstructed from sample data.
Drift Current
Drift current is the net leakage current from the hold capacitor during the hold mode. Drift current can
be calculated from the droop rate using the formula as given below:
DV
I D ( pA) = C ( pF ) ¥ (V / s )
Dt
Performance of a sample-and-hold circuit can be measured like other monolithic, hybrid, modular,
and discrete integrated circuits. In this circuit, accuracy 0.01% can be achieved over the wide temperature
range. Fast acquisition is coupled with superior droop characteristics, even at high temperatures. High
slew rate, wide bandwidth, and low acquisition time generate excellent dynamic characteristics. The
sample and hold circuit has ability to operate at gains greater than 1 frequently. Therefore, the need for
external scaling amplifiers can be eliminated.

11.3 QUANTISATION
The quantisation of analog signal is to divide the complete amplitude range of analog signal into a
number of equal intervals. Binary equivalent number can represent each interval. This operation can
be performed by analog to digital converter. To get better resolution, large number of bits is used to
represent a analog signal. If four-bit analog to digital converter is used, the reference voltage is divided
into 16 parts. When reference voltage 15 is divided into sixteen equal divisions, each division represents
15/16 V. Resolution is the measure of the smallest change in output voltage which is the fraction of full
scale range of analog to digital converter. When ‘n’ is the number of bits, the percentage of resolution
1
of ADC is n ¥ 100 .
2 -1
1
If n = 8, the percentage resolution of ADC is 8 ¥ 100 = 100 / 255 = 0.392. When ADC converter
2 -1
resolution is very high, noise voltage is generated in ADC converter circuit. If noise voltage is greater
than the resolution of the A/D converter, the signal and noise cannot be distinguished. Table 11.1 shows
the resolution of DAC and ADC.
 442 Digital Electronics: Principles and Applications

Table 11.1 Resolution of DAC and ADC

Number of bits Percentage of resolution

1
n=4 ¥ 100 = 6.67
2 -1 4

1
n=8 ¥ 100 = 0.392
2 -18

1
n=10 ¥ 100 = 0.976
2 -1
10

1
n=12 ¥ 100 = 0.0244
2 -1
12

1
n=16 ¥ 100 = 0.00153
2 -1
16

11.4 BINARY DIGIT WEIGHT

Table11.2 shows binary digit, digit value and binary equivalent weight. In 4 bit binary system, the
weight of LSB is 1/(24-1)=1/15. The binary equivalent weights of all binary numbers are given in this
table. If the reference voltage is 15V, the resolution is 1/15V. The corresponding binary equivalent
output voltage is depicted in Table 11.3.
Table 11.2 Binary digit, digit value and binary equivalent weight

Binary digit 23 22 21 20
Digit value 8 4 2 1
Binary equivalent weight 8/15 4/15 2/15 1/15
Table 11.3

Binary Binary Output

b3 b2 b1 b0 equivalent voltage
weight
0 0 0 0 0/15 0
0 0 0 1 1/15 1
0 0 1 0 2/15 2
0 0 1 1 3/15 3
0 1 0 0 4/15 4
0 1 0 1 5/15 5
0 1 1 0 6/15 6
0 1 1 1 7/15 7
1 0 0 0 8/15 8
1 0 0 1 9/15 9
1 0 1 0 10/15 10
(Contd.)
 Analog Digital Conversion 443

Table 11.3 (Contd.)

1 0 1 1 11/15 11
1 1 0 0 12/15 12
1 1 0 1 13/15 13
1 1 1 0 14/15 14
1 1 1 1 15/15 15

11.5 OPERATIONAL AMPLIFIERS

Operational amplifiers are already explained briefly in Chapter 10. Generally, current summing
operational amplifiers are used in digital to analog converter for summing all currents of binary input
bits. Figure.11.11 shows the current summing circuit. There are three inputs in the circuit. For this
simple inverting summer circuit, all resistors are equal values. Then current in all three branches are I1,
I2 and I3 and can be expressed as
I1=V1/R, I2=V2/R, and I3= V3/R.
The summation of all currents is equal to I=I1+I2 +I3
The output voltage can be determined as follows:
Vout V1 V2 V3
- = + +
R R R R
Therefore, output voltage Vout = –(V1 + V2 + )
3 Fig. 11.11 Inverting summation amplifier

Example 11.1 What is the output voltage of current summer as shown in Fig.11.12 ?.
Consider R1 = R2= R3= R4= Rf =1K ohm, V1= V2= V3=10 V, and V4=0V.

� Solution
The currents I1, I2, I3 and I4 are
V1 10V V 10V
I1 = = = 10mA, I 2 = 2 = = 10mA,
R1 1Kohm R2 1Komh

V3 10V V 0V
I3 = = = 10mA, I 4 = 4 = = 0mA
R3 1Komh R4 1Komh

The If current is equal to

Fig. 11.12
If = I1 + I2 + I3 + I4 = (10 +10 + 10 + 0)mA=30mA
The output voltage is Vout = – If Rf = – 30 mA×1K ohm = – 30V

11.6 DIGITAL TO ANALOG CONVERTERS (DAC)

The digital to analog converter has ability to convert digital signals to analog signals. The digital-to-
analog conversion is a process in which digital words are applied to the input of the DAC and an analog
output signal is generated to represent the respective digital input. In this conversion process, an ‘N’-bit
 444 Digital Electronics: Principles and Applications

digital data can be mapped into a single analog output voltage. Therefore, the analog output of the DAC
is a voltage that is some fraction of a reference voltage.
So, VOut = K×VRef.
where, VOut is the analog voltage output, VRef is the reference voltage and K is the fraction.
Figure.11.13 shows the block diagram of a DAC converter. When a DAC has ‘N’-bits digital inputs
b0, b1, b2, b3… bN-1) and a reference voltage, VRef. The voltage output, VOut of an N bits straight binary
DAC can be expressed as
VOut = K × VRef × Digital inputs
Where, K is scaling factor
Digital input = 2N–1bN–1+2N–2bN-2 +
2N–3bN–3 +………+22b2 + 21b1 + 20b0
N = number of bits
bN–1 - Most significant bit
Fig.11.13 Block diagram of a digital to analog
b0 - Least significant bit converter

The basic architecture of ADC converter without S/H circuit is shown in Fig.11.14. It consists of
binary switches, scaling network and output amplifier. The reference voltage, binary switches and
scaling network convert digital inputs into voltage or current or charge signals. The output amplifier
amplifies the output of scaling network to a desired measurable value.

Fig.11.14 Basic architecture of a digital to analog converter without S/H circuit.

11.6.1 Characteristics of DACs

The characteristics of digital to analog converter are very useful to understand its operation. There are
two types of characteristics: static characteristics and dynamic characteristics.

STATIC CHARACTERISTICS
The static characteristics of DAC are full-scale value (FS), dynamic range (DR), integral non-
linearity(INL), differential non-linearity (DNL), resolution, signal to noise ratio. These characteristics
are not time dependent.
Full-scale value
The input and output characteristics of 3-bit unipolar and bipolar DAC are shown in Fig.11.15(a) and
(b) respectively . The eight possible digits would have unique analog voltage. The analog equivalent of
 Analog Digital Conversion 445

LSB is VRef /2N. As resolution of DAC is finite, the maximum analog output voltage will not be equal to
VRef. This characteristic can be explained by full-scale value. The full-scale value or range (FSR) means
the difference between analog output voltage for the MSB and analog output voltage for LSB. The full
scale of DAC may be expressed

Fig.11.15 (a) Ideal input output characteristics of 3-bit unipolar DAC and
(b) Ideal input output characteristics of 3-bit bipolar DAC

FSR = VRef – LSB = (VRef – VRef /2N ) = VRef (1-1/2N)

When ‘N’ towards infinity, the full scale
value is equal to VRef.
Dynamic range (DR)
The dynamic range (DR) of a DAC is the ratio of
the full scale value/range to the smallest analog
output value, LSB and it can be expressed as
DR=Full scale value /LSB= VRef (1-1/2N)/(VRef/
2N)=2 N –1 . The dynamic range in decibels is
DR=20 log (2N – 1)dB.
Integral non-linearity (INL)
It is the maximum difference between the data
converter outputs with actual finite resolution
and the data converter outputs with ideal finite
resolution. Actually integral non-linearity de-
fines the linearity of the input output character-
istics of DAC and it can be expressed as Fig.11.16 Differential nonlinearity of 3-bit
unipolar DAC
 446 Digital Electronics: Principles and Applications

INLn = (DAC output value for input code with actual finite resolution - DAC output value for input
code with ideal finite resolution)
Differential nonlinearity (DNL)
Differential non-linearity is measured from bit to bit deviations or the difference between two adjacent
levels. Actually, it measures bit-to-bit deviations from ideal DAC output value rather than the entire
range of output. Differential non-linearity of a DAC is depicted in Fig.11.16.
Monotonicity means that the digital input to the converter increases over its full-scale range. The
slope of the transfer characteristics is never negative in monotonic converter.
Resolution It is defined as the smallest change in the analog output voltage with respect to the value
of reference voltage.
Offset Offset of the DAC is defined as the amount of shift in the input-output characteristics when
digital input is 000. This is similar to the operational amplifier’s offset voltage. Figure 11.17 shows the
offset error of a DAC

11.6.2 Dynamic Characteristics

Time independent characteristics of DAC are static
characteristics but the dynamic characteristics
are time dependent. The dynamic characteristic
of DAC is also very important as this parameter
is varying with time. Conversion speed is one
of the dynamic characteristics of DAC. The
conversion speed is the time taken by DAC to
convert digital input into equivalent analog
output. Generally, the conversion time is in the
range of few milliseconds to some nanoseconds
and it depends on type of DAC. Actually, the
speed of DAC depends upon parasitic capacitors,
gain bandwidth and slew rate of operational
amplifiers.
The operational amplifier can affect the
dynamic performance of DAC. The gain error of Fig. 11.17 Offset error of 3-bit unipolar DAC
an operational amplifier is the difference between
the reference voltage and actual voltage due to finite value of gain. Due to gain error of operational
amplifiers, gain error also exists in DAC. The gain error of DAC is defined as the difference between
the ideal slope and the actual slope of the input-output characteristics. It can be described as Gain error
= Ideal slope - Actual slope, as illustrated in Fig. 11.18.

11.6.3 Binary Weighted or R/2NR DAC

Weighted binary DAC and R-2R ladder are the two types of DAC. Each DAC converter input is a
multi-bit digital signal, and generates an analog output signal equivalent to digital. Each bit of the signal
 Analog Digital Conversion 447

has different binary weight. The bit is multiplied

by its weighting factor to give its contribution to
the whole. The contribution from each bit is then
summed, to give the analog equivalent.
The binary-weighted-input DAC circuit is
a variation on the inverting summer op-amp
circuit. The classic inverting summer circuit is
an operational amplifier using negative feedback
for controlled gain, with several voltage inputs
and one voltage output. The output voltage is the
inverted sum of all input voltages when all equal
resistances are used in the circuit.
If any of the input resistors were different, the
input voltages would have different degrees of
effect on the output, and the output voltage would
not be a true sum. Assume the input resistor values Fig. 11.18 Gain error of 3-bit unipolar DAC
are multiple powers of two: R, 2R, and 4R, instead
of all the same value, R as shown in Fig. 11.19.
Then currents are applied to operational amplifier to develop output voltage Vout. The output voltage
can be expressed as
Vout = - R(I1+I2+I3)
where I1, I2 and I3 are binary weighted currents as given
below:
I1=V1/R, I2 =V2/2R, and I3=V3/4R
After substituting I1, I2 and I3 in the above equation, the output
Ê V V3 ˆ Fig.11.19 Inverting amplifier
voltage can be expressed as Vout = - ÁV1 + 2 + ˜ The input
Ë 2 4¯
voltage V1 has a 1:1 effect on the output voltage. The input voltage
V2 has exactly half the effect on the output, but V3 has one-fourth effect on output. When the inputs are either
0 volts or +VCC, the output voltage represents the corresponding analog voltage equivalent of three bits binary.
The output voltages for all eight combinations of binary bits from 000 to 111 input to the circuit, are represented
in Table 11.4. It is clear from Table 11.4 that each step
in the binary count sequence has a 1.25 volt change in
the output. When R1=1K, R2=2K and R3=4K and Rf=1K
as depicted in Fig. 11.20, the Table 11.4 will be satisfied.
If the feed back resistance is adjusted to 800Ω as
given in Fig. 11.21, the output voltages will be directly
corresponding to the binary input. For example when the
binary input 001, DAC output will be 1 volt. Similarly,
7 volts DAC output for the binary input 111 as shown in
Table 11.5. Fig.11.20 Binary weighted DAC
 448 Digital Electronics: Principles and Applications

Fig. 11.21 3-bit binary weighted DAC Fig. 11.22 Weighted 4-bit binary DAC

Figure 11.22 shows the circuit diagram of weighted 4-bit binary DAC. The analog output voltage of
a 4-bit weighted DAC can be expressed as follows:
Four input currents I1, I2, I3, I4 and feed back current If are determined from the following
expressions

Table 11.4 Binary input and analog output Table 11.5 Binary input and analog output
voltage
Binary Input Output Voltage
Binary Input Output Voltage 000 0.00 V
000 0.00 V 001 −1.00 V
001 −1.25 V 010 −2.00 V
010 −2.50 V 011 −3.00 V
011 −3.75 V 100 −4.00 V
100 −5.00 V 101 −5.00 V
101 −6.25 V 110 −6.00 V
110 −7.50 V 111 −7.00 V
111 −8.75 V

I1=V1/R1, I2=V2/R2, I3=V3/R3, I4=V4/R4 and If = − Vout/Rf

The sum of the input currents is equal to feedback current If
If = I1 + 12 + I3 + I4
After substituting all current values in the above expressions,
Vout V1 V2 V3 V4 Rf Rf Rf Rf
- = + + + or, - Vout = V1 + V2 + V3 + V4
Rf R1 R2 R3 R4 R1 R2 R3 R4
Rf Rf Rf Rf
when = 8, = 4, = 2, = 1, V1= b3, V2= b2, V3= b1 and V4= b0 the output voltage can be
R1 R2 R3 R4
expressed as
–Vout = 8b3 + 4b2 + 2b1 + b0 or, –Vout = 23b3 + 22b2 + 21b1 + 20b0
The weighting of bits b0, b1, b2 and b3 is 1, 2, 4 and 8 respectively. For this weighting R4 must be
the largest resistor value, but the others resistances are half the value of the previous resistance. If 4-
 Analog Digital Conversion 449

bit DAC has the following input resistances

R1= 1K, R2= 2K, R3= 4K , R4=8K and feedback
resistor Rf = 8K, the analog output voltage
for 1011 binary inputs is 11V. To reduce the
resolution of DAC, number of input bits will
be increased. The circuit configuration of 6-
bit input DAC is shown in Fig.11.23.
The current flows through feedback resis-
tance Rf is
If = I1 + I2 + I3 + I4 + I5 + I6
where I1, I2, I3, I4, I5, I6 are the current flows
through weighted resistances due to V1, V2, V3, Fig. 11.23 6-bit binary weighted DAC
V4, V5, V6 respectively.
The output voltage Vout = – Rf If = −Rf (I1 +
I2 + I3 + I4 + I5 + I6)
The ‘N’ bit binary weighted DAC is given in Fig. 11.24. The operational amplifier feedback resistance
Rf can be selected to get the proper scale. Here, Rf = KR/2. The analog output voltage can be written as
follows:
For ‘N’ bit binary inputs, current flows through feedback resistance Rf is
If = –(IN – 1 + IN – 2 + IN – 3 + ................. + I2 + I1 + I0)
After substituting all current values in the above equation, we get
bN - 1 bN - 2 bN - 3 b2 b1 b0
I f = - VRef ( + + + ◊◊◊◊◊◊◊◊◊ + N -3
+ N -2
+ N -1
)
R 2R 4R 2 R 2 R 2 R

VRef
If = - N -1
(2 N - 1 bN - 1 + 2 N - 2 bN - 2 + 2 N - 3 bN - 3 + ◊◊◊◊◊◊◊◊◊ + 22 b2 + 21 b1 + 20 b0 )
2 R

Fig. 11.24 N bit weighted DAC

 450 Digital Electronics: Principles and Applications

The output voltage Vout is

Vout = –If Rf
VRef R f
- I f Rf = - (2 N - 1 bN - 1 + 2 N - 2 bN - 2 + 2 N - 3 bN - 3 + ◊◊◊◊◊◊◊◊◊ + 22 b2 + 21 b1 + 20 b0 )
2N - 1 R
An offset voltage is applied in a DAC as shown in Fig. 11.25. The output voltage can be expressed as
Rf
Vout = - Voff - I f R f
Roff

Rf VRef R f
Vout = - Voff - N -1
(2 N - 1 bN - 1 + 2 N - 2 bN - 2 + 2 N - 3 bN - 3 + ........... + 22 b2 + 21 b1 + 20 b0 )
Rout 2 R

The resistance ratio of MSB and LSB is

Resistance of MSB / Resistance of LSB
R 1
= N -1 = N -1
2 R 2
When N = 8, this ratio will be 1/128. The larger
component range creates problems for proper
resistance matching and consequently the binary-
weighted resistance DAC is nonmonotonic.
Binary weighted DAC is the simplest design
in concept. This DAC circuit uses an operational
amplifier connected as a summing amplifier. Each
bit is connected with one of the inputs, and is Fig. 11.25 N bit DAC with offset input voltage
weighted by the ratio of the feedback resistor to the
input resistor. For ‘N’ bit DAC, the variation of input resistance is R to 2N–1 R. If N is 16, then R=1K
ohm to 216–1 K ohms or 32768 K ohms. Therefore, resistance variation is very wide range. Therefore,
Binary weighted DAC is not very practical to build,
particularly in integrated circuit form.
Figure 11.26 shows the extended capacity of a
4-bit DAC and this is an eight bit DAC. Here, input
resistances are divided into group of four resistances
namely least significant group (b0 to b3) and most
significant group (b4 to b7). The most significant group
resistances are directly connected with operational
amplifier. The least significant group resistances
are connected with operational amplifier through an
extra resistance Rex. The value of Rex is such that the
relationship between inputs of two groups will be
Fig. 11.26 8-bit DAC
 Analog Digital Conversion 451

b7 b6 b5 b4
= = = = 10
b3 b2 b1 b0
When Rex is equal to 8R, the above relationship will be exist only.
11.6.4 BCD D/A Converter
Figure 11.27 shows the BCD D/A converter. Weighted resistances are used in this DAC. A group of
four resistances is used for least significant digit and the other group of four resistances is for most
significant digit. The weight of one group resistance is ten times of another group resistance. Therefore,
the large spread resistances create problems. The extended capacity DAC can also be used in BCD D/A
converter as depicted in Fig. 11.28. The least significant digit is represented by b0, b1, b2, and b3 and the
most significant digit is represented by b4, b5, b6 and b7. When Rex= 4.8R, the most significant digits to
least significant digits ratio will be
b7 b6 b5 b4
= = = = 10
b3 b2 b1 b0

Fig. 11.27 Two digits BCD D/A converter Fig. 11.28 Improved two digits BCD D/A converter

11.6.5 R-2R Ladder Circuit

R-2R ladder circuit can eliminate the larger component spread in binary weighted DAC. The R-2R
ladder circuit for converting digital to analog converter uses only resistances of R and 2R as shown
in Fig. 11.29(a). Mathematically analysing this
ladder network is little bit difficult than weighted
resistance DAC. In weighted resistance DAC,
each bit effect on output is very easily calculated.
But in R-2R ladder network, each binary inputs
effect on output can be determined using
Thevenin’s theorem for each binary input.
The effect of b0, b1, b2 are determined as
follows:
Figure 11.29(b) shows the R-2R ladder circuit Fig. 11.29 (a) R-2R ladder circuit of 3-bit DAC
of 3-bit DAC when digital input is 001. As b0=1,
b1=0, b2= 0, the Thevenin’s equivalent resistance and voltage can be determined.
 452 Digital Electronics: Principles and Applications

Looking from Section A -A′, we find that resistance 2R is parallel with 2R resistance (2R||2R). Then
V
the equivalent resistance=R and equivalent voltage is REF ◊
2
Looking from Section B -B′, R is series with R and sum of these resistances parallel with 2R. Then
V
equivalent resistance=R and equivalent voltage is REF ◊
22
Looking from Section C -C ′, R is series with R and sum of these resistances parallel with 2R.
V
Subsequently, the equivalent resistance is equal to R and equivalent voltage is REF ◊
23
V
Then the equivalent resistance of circuit is R + 2R = 3R while b0 = 1, b1 = 0, b2 = 0. Hence REF
3
is
applied to an operational amplifier through resistance 3R. 2

V
Similarly, the equivalent circuit for b1 is Requ= 3R and Vin = REF and the equivalent circuit for b2 is Requ
VREF 22
= 3R and Vin = ◊. The complete equivalent circuit of Fig. 11.29 is shown in Fig. 11.30(d).
2
R-2R ladder circuit works on the fact that the current reduced by a factor of 2 for each digital input
from LSB to MSB. The I0, I1, and I2 currents are as follows:

Fig. 11.30 Equivalent circuit of R-2R ladder DAC

VREF V V
I0 = , I1 = 2 REF , I 2 = REF
2 ¥ 3R
3
2 ¥ 3R 2 ¥ 3R
When all bits are 1, the currents flow into the operational amplifier and produce an output voltage
Vout as given below:
 Analog Digital Conversion 453

Ê ˆ
Vout = – (I2 + I1 + I0)Rf = - VREF b2 + VREF b1 + VREF b0 R f
Á 2 ¥ 3R 2 2 ¥ 3R 23 ¥ 3R ˜¯
Ë
V Rf
= - REF3
(4b2 + 2b1 + 1b0 ) = - K (4b2 + 2b1 + 1b0 )
2 3R
VREF R f
where, K = - 3
2 3R
In this way, the larger component spread problem has been eliminated and current flows through the
resistance can not changed due to switching and behave as constant voltage source. This DAC is as fast
as the binary weighted resistance DAC.
Figure 11.31 shows the ‘N’ bit R-2R ladder circuit and its equivalent circuit is depicted in Fig. 11.32.
The output voltage of ‘N’ bit R-2R circuit can be expressed as
Vout = –(IN – 1 + IN – 2 + ....... + I2 + I1 + I0)R f
V Rf N -1
= - REFN
(2 bN - 1 + 2 N - 2 bN - 2 + 2 N - 3 bN - 3 + 22 b2 + 21 b1 + 20 b0 )
2 3R

Fig. 11.31 N bit R-2R ladder circuit Fig. 11.32 Equivalent circuit of N bit
R-2R ladder circuit

Example 11.2 Determine the output voltage of the circuit as shown in Fig. 11.33 when digital
inputs are 0010 and 1010.
� Solution
The output of a 4-bit R-2R ladder circuit is
V Rf
= - REF
4
(8b3 + 4b2 + 2b1 + 1b0 )
2 3 R
Given data are VREF =12V, Rf=10K and
R = 5K
If b3= 0, b2= 0, b1= 1, b0= 0,
the output voltage Vout
Fig. 11.33
12 10
=- 4 ¥ (8 ¥ 0 + 4 ¥ 0 + 2 ¥ 1 + 1 ¥ 0) = -1V
2 3¥5
When b3= 1, b2= 0, b1= 1, b0= 0,
12 10
the output voltage Vout = - ¥ (8 ¥ 1 + 4 ¥ 0 + 2 ¥ 1 + 1 ¥ 0) = –5V
2 4
3¥5
 454 Digital Electronics: Principles and Applications

11.7 EXTENDED CAPACITY OF DAC

In a 4-bit binary weighted DAC and R-2R ladder DAC, the resolution is large and the ratio between MSB/
LSB is also large. Due to large resolution the accuracy of DAC is very less. To improve accuracy, different
approaches are used. The first approach is that two or more DAC can be combined. In this case each DAC
can be combined by appropriately dividing the analog outputs of each DAC. After summation of all DAC
outputs, the actual output voltage can be obtained. The other method is that the reference voltage of each
sub DAC is different. When sum up all analog outputs, we find the actual output. In this method different
scaling DACs are combined to reduce resolution and correspondingly increase accuracy.
11.7.1 Combination of Similar Scale DAC
Figure.11.34 shows the extending capacity of DACs which combines a ‘m’ bit DAC and a ‘n’ bit DAC.
The first DAC convert ‘m’ bit digital data into analog output voltage and the other DAC convert ‘n’ bit
digital data into analog form. The exact output voltage is summation of output of ‘m’ bit DAC and ‘n’
bit DAC. The output voltage can be expressed as
Vout = KV REF [2m–1bm–1 + 2m–2bm–2 + 2m–3bm–3 + ............ + 21b1 + 20b0] +
KV REF [2n–1bm + n – 1 + 2n–2bm+n–2 + ............ + 20bm]2m
The above equation can also be expressed as

Vout = KV REF[2m + n + 1 bm + n – 1 + 2m + n – 2 bm + n – 2 + ............ + 2mbm] + KV REF [2m – 1 bm – 1 + 2m – 2 bm – 2

+ 2m – 3 bm – 3 + ............ + 21b1 + 20b0]
= KV REF[2m + n + 1 bm + n – 1 + 2m + n – 2 b m + n – 2 + ............ + 2mbm + 2m – 1 bm – 1 + 2m – 2 bm – 2 + 2m – 3 bm – 3
+ ............ + 21 b1 + 20 b0]

11.7.2 Combination of Differ-

ent Scale DAC
When the reference voltages of DACs are
different and combination of different scale
DACs can also develop an analog output. The
method of combining the DACs is called sub-
ranging. Fig. 11.35 shows the combination of
a ‘m bit DAC and a ‘n’ bit DAC with different
reference voltage. The exact analog output Fig. 11.34 Combination of m-bit and n-bit DACs
voltage of sub-ranging DAC is as follows:
V out = K V REF [ 2 m–1b m–1 + 2 m–2b m–2 + 2 m–3b m–3 + . . . . . . . . . . . . + 2 1b 1 + 2 0b 0] +
K2m VREF [2n – 1bm + n – 1 + 2n – 2bm + n – 2 + ............ + 20bm]
The above output voltage equation can also be expressed as
Vout = KVREF [2m + n – 1 bm + n – 1 +2m + n – 2 bm + n – 2 + ............ + 2mbm] +
KVREF [2m – 1 bm – 1 + 2m – 2 bm – 2 + 2m – 3 bm – 3 + ............ + 21b1 + 20b0]
= KV REF[2m + n – 1 bm + n – 1 2m + n – 2 bm + n – 2 + ............ + 2mbm + 2m – 1 bm – 1 + 2m – 2 bm – 2 + 2m – 3 bm – 3 +
............ + 21 b1 + 20 b0]
 Analog Digital Conversion 455

11.8 CURRENT MODE DAC

The voltage mode binary weighted resistor
DACs are discussed in Section 11.7 and
11.10. These DACs are the simplest type
DAC circuits. These DACs are not inherently
monotonic and actually it is quite hard to
manufacture these DACs at high resolutions.
The output impedance of the voltage mode
binary DAC changes with digital inputs.
These problems can be eliminated by current
mode DAC.
Figure 11.36(a) shows resistor based Fig. 11.35 Sub-ranging DACs
current mode binary DAC and Fig. 11.36(b)
shows current source based current mode 4-bit binary DAC. The maximum current output Iout is sum of
I0, I1, I2 and I3. So Iout=I0+I1+I2+I3. The maximum analog output voltage is VO=-Iout Rf.

(a) (b)
Fig. 11.36 (a) Current mode binary weighted DAC with resistor based and (b) Current
mode binary weighted DAC with current source based
The current mode DAC generally converts the reference voltage into a set of binary weighted
currents. Then these currents are applied to an OP AMP in the inverting configuration and generate the
output voltage Vo. Figure 11.37 shows the generalised current mode DAC. The output voltage Vo can be
expressed as
Vo = –Rf (I0 + I1 + I2 + ............ + IN – 1)

Fig. 11.37 (a) Generalised current mode DAC and (b) Generalised current mode DAC

where, I0, I1, I2,......IN – 1 are binary weighted currents

 456 Digital Electronics: Principles and Applications

The ‘N’ bit binary DAC consists of ‘N’ weighted current sources in the ratio 1:2:4: ….. 2N – 1. The MSB
switches the current 1 and the LSB switches the current 2N – 1. Theoretically, the basic concept is simple but
this current mode DAC has practical limitations as manufacturing an economical size current ratio 1:128 for
a 8-bit DAC is very difficult. This circuit is enormous and they should match temperature coefficients.
This type of DAC requires precision current sources. When all the digital inputs are zero, not a single
current source is connected with operational amplifier. Then output current iout = 0. The binary input
signals control whether the current sources are connected to either non-inverting terminal of OP-AMP
or ground. The output current iout varies in the range of

 0 + I1 + I2...IN – 1 ≥ iout ≥ 0

I
The advantage of the current mode DACs is the high current drive inherent in the system. But the
precision current sources are required to generate a high resolution which is dependent on how well the
current sources can be matched with the binary weight. The other problem associated with this current
mode DACs is the error due to the switching.

11.9 SWITCHED CAPACITOR DAC

Charge scaling DACs operate by binary weighted division the total charge applied to a capacitor array.
These converters circuit configuration are extremely simple and are in effect a digitally controlled
voltage attenuator. The advantage of charge scaling DAC is that it is compatible with switched capacitor
circuits. Figure 11.38 shows a simple 3-bit switched capacitor DAC. An array of capacitors is connected
to switches in parallel as depicted in Fig.11.38. The capacitors share one common electrode which
is connected to the inverting terminal of operational amplifier. It is depicted in Fig. 11.38 that the
capacitors are binary weighted which means that C, 2C, 4C capacitances are used. The capacitor array
totals 2NC where N is the number of bits. B0, B1 and B2 are three bits. The operation of 3-bit switched
capacitor DAC is explained as follows.
Initially, all capacitors are discharged when the Reset switch is connected to the ground. There after Reset
switch is disconnected. After the initialisation, the digital switches B0, B1, and B2 connect each capacitor to
Vref or ground according to the digital inputs. The output voltage Vo is then a function of the voltage division
between capacitors. For example, if the digital input is 011, B2 is connected to ground, B0 and B1 are connected
to Vref. The equivalent capacitor divider corresponds to a value of the output equal to 5/8 Vref as shown in Fig.
11.39. The conversion Table 11.6 provides the value of output voltage V0 with respect to digital inputs.

Fig. 11.38 3-bit switched capacitor DAC Fig. 11.39 Capacitor divider
 Analog Digital Conversion 457

Table 11.6 Digital inputs and analog output

Digital Inputs Analog output Analog output
B2 B1 B0 Vo/Vref
0 0 1 7/8
0 1 0 6/8
0 1 1 5/8
1 0 0 4/8
1 0 1 3/8
1 1 0 2/8
1 1 1 1/8

The generalised charge scaling N bit DAC

is shown in Fig.11.40 In this figure, a parallel
array of the binary weighted capacitors 2N-1 C is
connected to the OP-AMP, where C is the unit
capacitance of any value and N is the number of
bits. After initially being discharged, the input
digital signal switches each capacitor to either
Vref or ground. Then the output voltage VO is a
function of the voltage division between the Fig. 11.40 N-bit switched capacitor DAC
capacitors. The output voltage can be expressed
as
N -1
VO = Â bk 2k - N VRef where, k = 0, 1 ….N-1
k =0
= [b0 2–N + b1 21 – N + b2 22 –N ............ + bN – 1 2–1]VRef

11.10 D/A CONVERTER SPECIFICATION

The performance of D/A converter is measured based on the following parameters: Resolution,
Accuracy, Linearity, Settling time, Temperature sensitivity. These parameters are generally specified by
the manufacturers in data sheets.

Resolution The resolution of D/A converter refers to the smallest change in the analog output volt-
age. It is equivalent to the value of the Least Significant Bit (LSB). For a N-bit D/A converter, maximum
number of steps is 2N - 1. When the reference voltage is V, the Least Significant Bit (LSB) value is
Reference Voltage V
Resolution = = N
Number of Steps 2 −1
For an-8 bit D/A converter with a full scale output of 10V, the resolution is equal to
10 10
= = 39.2 mV
2 -1
8
255
 458 Digital Electronics: Principles and Applications

Accuracy The output voltage of D/A con-

verter is different from ideal case. Therefore,
there is always some error. The accuracy is mea-
sured from the difference actual output voltage
and voltage for ideal case. When the accuracy
of D/A converter is ±0.25 percent, the error of
converter is about 0.25 × 12/100 = 0.03V for
full-scale voltage V =12 V.
Offset/Zero Scale Error An input code
of zero may be expected to give 0V output. But
a small offset may be present in output and the
transfer characteristic of DAC does not pass
through the origin. The offset error of D/A con-
verter is depicted in Fig. 11.41.
Linearity Figure 11.41 shows the input-out-
put characteristics of a D/A converter. Zero offset
and gain errors can develop the ideal input-output
Fig. 11.41
characteristic, which passes through the origin
and full-scale points. But it is not sure that intermediate points will always be lie on a straight line. A
very small error in the weighting factor for a fraction of LSB will cause non-linearity. Linearity can be
expressed by deviation from the ideal line as a percentage, or a fraction of LSB. It is generally specified
1 1
as ± LSB or e < D
2 2
Settling time This is usually expressed as the time taken to settle within half LSB. Generally
settling time of DACs will be about 500ns.
Temperature Sensitivity The D/A converters are temperature sensitive. When the digital inputs
are fixed, the analog output may be varied with temperature due to the temperature sensitivities of the
reference voltages, the operational amplifier and converter circuit resistances etc. Generally, temperature
sensitivity of DACs is about ± 50 ppm/°C in general-purpose converters.

Example 11.3 When digital input of a 4-bit DAC is 1111, analog output voltage of DAC is 12V.
What will be the output voltage for digital input 1001?
� Solution
Analog output voltage = K × digital input
Here analog output of DAC is 12V. Therefore, 12=K × 15
12
So, K =
15
When the digital input= (1001)2= 9, anlog output voltage of DAC is equal to K × digital input
12
= ¥ 9 = 7 ◊ 2V
15
 Analog Digital Conversion 459

Example 11.4 What is the step size/resolution of DAC of Example 10.2?.

� Solution
V 12
Resolution = = 4 = 0 ◊ 8V as V = 12V and N = 4.
2 -1 2 -1
N

Example 11.5 What is the percentage resolution of 10-bit DAC?.

� Solution
1
Percentage resolution of 10-bit DAC = ¥ 100 = 0 ◊ 976%
210 - 1
Example 11.6 Determine the output voltage of the circuit as shown in Fig. 11.42, when
Roff = 1 K ohm, Voff = –2V and binary input is 101.

� Solution
The output voltage can be expressed as
Rf Rf Rf Rf
Vout = - ( V1 + V2 + V3 ) - Voff
R1 R2 R3 Roff
Ê Rf Rf Rf ˆ Rf
= -Á b2 + b1 + b0 ˜ V - Vof
Ë R1 R2 R3 ¯ Roff
When Roff =1Kohm , Voff = -2V and binary
input = 101, the output voltage is equal to
Fig. 11.42
Ê4 4 4 ˆ 4
Vout = - Á ¥ 1 + ¥ 0 + ¥ 1˜ ¥ 5 - ¥ ( -2) = -12 V
Ë1 2 4 ¯ 1

11.11 DAC ICs

Most commonly DAC ICs are 8-bit DAC0800, 12-bit DAC80, 16-bit PCM54 and PCM55 etc.
The DAC0800 ICs are monolithic 8-bit high-speed current output digital to analog converters with
typical settling times of 100ns. When used as a
multiplying DAC, monotonic performance over
a 40 to 1 reference current range is possible.
These ICs have high compliance complementary
current outputs to allow differential output
voltages of 20Vp-p with simple resistance
load as depicted in Fig.11.43. The features of
DAC0800 ICs are given below:
• Fast settling output current 100ns
• Full-scale error ±1LSB
• Non-linearity over temperature ±0.1%
• Full-scale current drift ±100ppm/C
• High output compliance –10V to +18V Fig. 11.43 8-bit DAC0800
 460 Digital Electronics: Principles and Applications

• Complementary current outputs

• Interface ability with TTL, CMOS, PMOS etc.
• 2 quadrant wide range multiplying capability
• Power supply range ±4.5V to ±18V
• Low power consumption 33mW at ±5V and
• Low cost.

Fig. 11.44 Functional block diagram and pin assignments of 12-bit DAC80
The monolithic digital-to-analog converter IC DAC80 is a 12-bit D/A converter. It consists of 12-bit resistor
ladder network, current switches, reference control circuits and output amplifier as shown in Fig. 11.44 and
provides a highly stable reference capable of supplying up to 2.5mA to an external load without degradation
of D/A performance. This IC can be able to provide accurate and reliable performance over temperature and
power supply variations. The use of a zener diode as the basis for the internal reference contributes to the
high stability and low noise of the device. The DAC80 can be operating at supply voltages as low as ±11.4V
without loss in performance or accuracy over any range of output voltage. The reliability of the monolithic
DAC80 is improved by using ceramic package. This IC also operates in wide temperature range. The offset
and gain error of DAC80 can be adjusted by external offset adjustment and gain adjustment resistance e-
brazed ceramic and low-cost molded plastic.

Fig. 11.45 External adjustment connection diagram of 12-bit DAC80

 Analog Digital Conversion 461

The PCM54 and PCM55 are parallel input, fully monotonic, 16-bit digital-to-analog converters that
are designed and specified for digital audio applications. The PCM54 is packaged in 28-pin plastic DIP
package and the PCM55 is available in a 24-lead plastic miniflat pak. These devices employ ultra-stable
nichrome thin-film resistors to provide monotonicity, low distortion, and low differential linearity error
over long periods of time and over the full operating temperature. These converters consist of a stable,
low noise, internal, zener voltage reference, high speed current switches, a resistor ladder network, and
a fast settling, low noise output operational amplifier all on a single monolithic chip. The converters
are operated in the voltage range from ±5V to ±12V. Power dissipation with ±5V supplies is less than
200mW. A current output option is provided in this DAC. This output typically settles to within ±
0.006% of FSR final value in 350ns. Figure 11.46 shows the connection diagram of 16-bit D/A converter
PCM54 and PCM55. These devices have the following features:

Fig. 11.46 Connection diagram of (a) PCM54 (b) PCM 55

11.12 ADC CONVERTER

The analog to digital conversion (ADC) is the reverse operation of digital to analog conversion (DAC).
Figure 11.47 shows the block diagram of ADC, which consists of filter, sample & hold, quantiser and
digital processor. The filter circuit is used to avoid the aliasing of high frequency signals and passes
the base band frequency signal of ADC. Sometimes, this filter is also called antialiasing filter. After the
filter, a sample and hold circuit is used to maintain constant the analog input voltage of ADC during the
period when the analog signal is converted into digital. This time period is also called as conversion
time of ADC. The quantiser circuit is used after sample and hold to segment the reference voltage into
different ranges. If ‘N’ number of digital bits represents analog voltage, there are 2N possible subranges.
The quantiser determines the specified subranges corresponding to an analog input voltage. The
digital processor can encode the corresponding digital output. There are different types of ADCs. The
classifications of ADC architectures based on speed are slow speed ADCs, medium speed ADCs and
 462 Digital Electronics: Principles and Applications

fast speed ADCs. Single slope and duel slope serial ADCs are slow speed type and its resolution is very
high and accuracy is very good. Medium speed ADCs are successive approximation ADCs and Parallel
or flash ADCs is high speed ADCs. Resolution is moderate for medium speed ADCs and resolution is
low for flash ADCs. Accuracy of medium speed ADCs is good but flash ADCs has limited accuracy.

Fig. 11.47 Block diagram of ADC

11.12.1 Static Characteristics of ADCs

Analog input variables of ADCs are either voltages or currents and continuously time varying. The input -
output characteristics of an ideal 3-bit unipolar ADC is shown in Fig.11.48. It is clear form this figure that
analog input is quantised and output is a digital code. This
transfer characteristic has eight horizontal steps. With in a
range of analog input voltage, ADC generates a code. This
range of voltage is called as quantisation uncertainty or
quantisation error and it is equal to LSB. In ideal case, the
width of the transition regions between adjacent codes is
zero. But practically the width is not zero due to transition
noise. Therefore, analog input for a digital output code
has a code center, which lies in between two adjacent
transition regions. The first transition is occurred at ½ LSB
and the full-scale analog input voltage is equal to 7/8 LSB.
The ideal step change occurs at analog input voltage ½
(2i–1)LSB, where i = 1 to 2N–1 for an N-bit converter. The
quantisation error is a function of time and it is actually
a saw truth waveform as depicted in Fig. 11.49. The
maximum error of an ideal converter is ±½ LSB. Fig. 11.48 Input–output characteristics of
unipolar ADC
The primary static characteristics of A/D converters are
resolution, non-monotonicity, differential nonlinearity (DNL), integral nonlinearity (INL), offset error, and
gain error. The resolution is the smallest
analog input voltage change, which can be
distinguished by an A/D converter. It can be
expressed as
Resolution = Full scale voltage/(2N-1)
where N = number of bits of A/D Con-
verter. Fig. 11.49 Quantisation noise of unipolar ADC
Non-monotonicity occurs in an ADC if the vertical step change is negative during transition from one
state to another. In general the vertical jump is LSB. If the jump is 2 LSBs or grater than 2LSB, missing
output codes appear in transfer characteristics. If vertical jump less than 0 LSB, the ADC is nonmonotonic.
Figure 11.50 shows the wide code, non-monotonic and missing code characteristics of ADC.
 Analog Digital Conversion 463

Differential non-linearity (DNL) of ADC is the difference between two adjacent codes at each vertical
step and it always expressed in terms of LSBs. The differential nonlinearity of an A/D converter is DNL=(D-
1) LSBs, where D is the actual vertical step. Fig. 11.51 shows the differential non-linearity of a 3-bit ADC.
The integral nonlinearity (INL) of an ADC is the maximum difference between the ideal finite resolution
characteristics and the actual finite resolution characteristics. It is also measured in terms of LSBs. If INL
is less than 1 LSB in a measuring instrument, it will be acceptable. Sometimes, in ADCs the actual input-
output characteristics is shifted horizontally from the ideal input-output characteristics with some offset.
The offset error is actually the horizontal difference between the actual and ideal characteristics as depicted
in Fig. 11.52. Gain error is a difference between the actual characteristics and ideal characteristics and it is
directly proportional to the magnitude of the analog input voltage as shown in Fig. 11.53.

Fig. 11.50 Non-monotonic ADC with missing Fig. 11.51 Differential non-linearity of ADC
code and wide code code

Fig. 11.52 Offset error of ADC Fig. 11.53 Gain error of ADC
 464 Digital Electronics: Principles and Applications

11.12.2 Dynamic Characteristics of ADCs

Generally, parasicitic capacitors, operational amplifiers and switches are used in sample and hold circuit.
The comparator is also used to detect whether the analog input voltage is greater or less than a voltage.
The dynamic characteristics of ADCs depend on the performance of parasicitic capacitors, operational
amplifiers and comparators. The dynamic performances of ADCs are conversion speed, aperture time,
acquisition time, and settling time which are already explained in Section 11.2.

11.12.3 Counting A/D Converter

Counting type ADCs are two types such as single slope serial ADC and duel slope serial ADC. The
operations of counting A/D converters are explained in this section.

Single Slope Serial ADC

The principle of operation of single slope serial ADC is to generate a ramp voltage using DAC, which
is compared with the analog input voltage. At the start of the ramp, the counter is started to count from
it’s initial value. When the ramp reaches the analog input voltage, the counter is stopped. The digital
value in the counter is directly related to the input voltage. This converter takes longer time to convert
a large voltage than a small one and some control signals are required for the start of conversions and
end of conversions. The maximum conversion time is 2NT, when 2N clock pulses are required to convert,
where N is number of bits and T is the clock period. The disadvantage of this ADC is that it is unipolar
due to single slope ramp generator.
Figure 11.54 shows the block diagram of single slope analog to digital converter. This converter consists
of ramp generator, binary counter, comparator, and AND gate. Here, the counter is used to generate digital
output. Initially analog input
is sampled and holds and then
applied to positive terminal of
the comparator. The counter
is in reset condition and
clock is applied to counter
through an AND gate.
When the first clock pulse is
applied, the ramp generator
starts to integrate a reference
voltage V. When analog input
voltage Vin is greater than the Fig. 11.54 Block diagram of single slope serial ADC
output of ramp generator, the
comparator output is high and clock pulse is applied to counter to count clock pulses. If the output of
ramp generator is equal to Vin, the comparator output becomes low and the counter stop counting. The
output of counter is the desired digital output of analog voltage. Single slope serial ADC with start of
conversion (SC) and end of conversion (EC) is illustrated in Figure 11.55. The conversion sequence of
single slope ADC is given below:
i. Start of conversion signal resets the counter to zero and enables the gate, to allow clock pulses to
be counted in counter.
 Analog Digital Conversion 465

ii. The counter outputs are fed into a DAC to generate a ramp output.

Fig. 11.55 Single slope serial ADC

with SC and EC signals

iii. Then ramp output is compared with

the sampled input signal. The gate
output is high till the ramp voltage
equals the input signal.
iv. When the ramp output voltage is
equal the input signal, the gate output
becomes low and counting stops.
v. Then gate-disabled signal can be
used to indicate the end of conver-
sion.
Figure 11.56 shows the timing diagram
of single slope ADC. In this system the
Fig. 11.56 Waveforms of single slope serial ADC with
counter resets for each conversion, and SC and EC signals
counting begins at zero as depicted in
Fig. 11.57. If a large signal is changing relatively slowly, each conversion would take a long time but
the values be little changed from each other.
An improvement on this basic system is to
use an Up/Down counter to track changes in
input voltage.

Dual Slope Serial ADC Figure 11.58

shows the block diagram of dual slope analog
to digital converter. This converter consists
of Up/Down counter, comparator and a DAC.
When analog input voltage is greater than
DAC output, comparator output will be high
and counter operates in up counting mode.
When DAC output exceeds the analog input Fig. 11.57 Waveforms of single slope serial ADC
voltage, comparator output will be low and
 466 Digital Electronics: Principles and Applications

counter operates in down counting mode. Therefore, the DAC output always counts in the proper direc-
tion to track the input signal and the counter’s output updated on each clock pulse. The advantage of this
converter is high speed as the counter never reset. It is much faster update than single slope ADC. Figure
11.59 shows the digital output to track an analog input voltage. Initially, counter catch up the analog input
voltage. In dual slope serial ADC the rate of change of output is identical to the first counting ADC.

Fig. 11.58 Dual slope analog to digital converter Fig. 11.59 Digital output of dual slope ADC
to track an analog input voltage.

A drawback of dual slope DAC is that the

binary output is never stable and it changes on every clock pulse even with a stable analog input signal.
This is known as bit bobble phenomenon and it sometimes creates problems in digital systems.

11.12.4 Dual-Slope Integration ADC

The dual-slope ADC is most commonly used in instrumentation, particularly in digital voltmeters and
multimeters. It is a low cost converter but its speed relatively slow. Figure 11.60 shows the block diagram
of dual-slope ADC in schematic form. Operational amplifiers are used as an integrator and a comparator in
this circuit. The output of comparator controls the gating of pulses from the clock into the counter. The logic
circuit controls the two switches S1 and S2
and reset the counter. The analog to digital
conversion sequence is as follows:
Initially, switch S2 is normally closed
to discharge the capacitor C. The sample
and hold circuit captures a value for
the input voltage and it will be remains
constant during the conversion sequence.
The counter is also reset.
Consider switch S1 is connected
with the analog input voltage to the
integrator and switch S2 is opened. Then
analog input voltage acts as the charging
voltage of capacitor and capacitor is
charged. The output of the integrator Fig. 11.60 Block diagram of duel slope integration ADC
will be
 Analog Digital Conversion 467

1 t Vi
VO = - Ú Vi dt = - t
RC 0 RC
This output VO feeds to the comparator and it is compared with reference voltage 0V. Therefore, the
comparator output is high and fed to the AND gate. Then clock pulses are gated into the counter. The counter
counts from 0000…00 to 1111..11 when 2N –1 clock
pulses are applied. When the next clock pulse is applied,
the counter is reset and the switch S1 will be connected to
reference voltage -VR. As a result the capacitor starts to
discharge. The output of the integrator now goes up at a
fixed rate, as VR, R and C are all constant values. Figure
11.61 shows the waveform of integrator voltage VO and
comparator voltage VC.
If the comparator voltage is high, counter continu-
ously counts till Vo<0. When the integrator voltage
reaches 0V, the comparator output goes LOW. Then
clock pulses are no longer gated into the counter and
the counter stops counting. It is clear from Fig.11.61
that the capacitor is charging during the time interval
0 to T1 and the capacitor discharges during T1 to T2.
The counter output is directly proportional to (T2 - T1). Fig. 11.61 Waveform of Vo and VC
Actually, this time interval is measured to determine
the input voltage.
V
At t = T1, the output voltage VO = - i T1 and the capacitor starts to discharge.
RC
At this instant, output voltage Vo can be expressed as
V V
VO = - i T1 + R (t - T1 )
RC RC
At t = T2 , the capacitor is fully discharged and output voltage Vo= 0V.
Therefore,
V V VR V V
0 = - i T1 + R (T2 - T1 ) or, (T2 - T1 ) = i T1 or, (T2 - T1 ) = i T1
RC RC RC RC VR
N
If the clock time period is Tp and T1 = 2 Tp , the time interval T2-T1 can be determined by
V
(T2 - T1 ) = i 2 N Tp
VR
Vi N
Consider the counter value is N1 at the instant T2. Accordingly (T2 - T1 ) = N1Tp = 2 Tp
Vi N VR
N1 = 2
VR
It is clear from the above equation; the count vale N1 is directly proportional to analog input voltage
Vi. When VR=2N, the counter value is numerically equal to analog voltage, N1=Vi.
 468 Digital Electronics: Principles and Applications

The accuracy of the duel slope integration ADC output depends on the reference voltage, VR and
clock frequency fp. These parameters can be made very stable. Therefore this circuit needs little
maintenance, and this circuit has also good accuracy and low cost. This type of ADC most commonly
used in instrumentation where signal changes slowly and rapid conversion is not required.

11.12.5 ADC Using Voltage to Frequency Converter

Figure 11.62 shows the voltage to fre-
quency converter. This circuit consists of
sample and hold circuit, an integrator, a
comparator and a monostable multivibra-
tor. In this converter, analog input voltage
is sampled and holds it till the conversion
is complete. The output of sample and
hold is fed to the integrator and capaci-
tor will be charged. The integrator output
voltage is connected to the comparator.
Initially switch is open and Vo decreases Fig. 11.62 Voltage to frequency converter
linearly with time. The output voltage Vo
can be expressed as
Vi
VO = - t where Vi is the input voltage.
RC
When integrator output voltage Vo is greater
than reference voltage –VR, the comparator output
is low. As Vo continuously decreases, at time t =
T1, Vo will be less than –VR and the comparator
output will be high. Then the switch S is closed
for T2 duration and capacitor is completely
discharged. Monostable multivibrator controls
the time interval T2. Figure 11.63 shows the
Fig. 11.63 Waveform of integrator output voltage
waveform of integrator output voltage Vo and Vo and comparator output VC
comparator output VC. The frequency of output
waveform is
1 1 Vi
f = = when T2<<T1
T1 + T2 RC VR
Therefore, output frequency is directly proportional to the analog input voltage.
Figure 11.64 shows the analog to digital converter using voltage to frequency converter. The output
of voltage to frequency converter used as clock of the counter for a fixed time interval T. If the counter
value is N at t=T, the relationship between N and T is
N 1 Vi
= T Or, N = fT = T
f RC VR
 Analog Digital Conversion 469

Fig. 11.64 Analog to digital converter using voltage to frequency converter

11.12.6 ADC Using Voltage To Time Conversion

The operating principle of ADC using voltage to time conversion is that firstly analog input voltage is
converted into time interval and then a fixed frequency clock pulse is counted in the same time interval to
generate digital value of input voltage. Figure 11.65 shows the ADC using voltage to time conversion. It
consists of sample and hold, integrator comparator, AND gate and counter. A negative reference voltage
–VR is applied to an integrator to
generate ramp output voltage.
Initially, switch S1 is closed and
output of integrator Vo is 0V. At
the starting of conversion, the
switch S1 is off and integrator
start to generate a ramp output
voltage. The output of the
integrator operational amplifier
is connected with the inverting
terminal of comparator. Then
Fig. 11.65 Analog to digital converter using voltage to time con- comparator output will be high
verter if the integrator output voltage
V0 is less than the analog input
voltage Vi. A three input AND gate is used to allow clock pulses to the binary counter. Then binary
counter starts counting at t = 0 as V0 = 0, VC = 1 and VCON = 0. The counter continiously counting until
VO=Vi. When VO is equal to Vi, counter stops counting as no clock pulses are applied to counter. Then
output of counter will be digital equivalent of analog input voltage Vi. Figure 11.66 shows the waveforms
of A/D converter using voltage to time conversion.
The time interval T is
t
T= Vi where τ = RC
VR

If the count value is N, it can be expressed as

t
N = f cT = f c Vi
VR
where fc is the clock frequency.
It is clear from above expression that the counter output is directly proportional to analog input
voltage.
 470 Digital Electronics: Principles and Applications

Fig. 11.66 Waveforms of integrator output voltage Vo and comparator output VC

11.13 MEDIUM SPEED ANALOG TO DIGITAL CONVERTERS

The medium speed A/D converters require N clock pulses for an N bit ADC. Therefore, the conversion
time less than serial type A/D converters. Successive approximation type ADC is the medium speed
ADC. The operating principle of successive approximation type ADCs are explained in this section.

11.13.1 Successive Approximation ADC

The major draw back of single slope and duel slope ramp and counter types of ADC is that the length of
conversion time is very high. The maximum conversion time is 2N clock cycles, where ‘N’ is the number
of bits. To reduce the conversion time, successive approximation type ADC is very much useful. This
converter is similar to counter type ADC, but this converter uses a pattern generator rather than a clock
to obtain digital equivalent value. The pattern generator simply sets one bit at a time starting with the
MSB. Therefore, the approximation starts by placing logic 1 on the most significant bit (MSB). Then
output of the DAC is compared with the sampled input signal. If the output of the DAC is too high, MSB
is reset to logic 0, but if it is too low it is left at logic 1 and the next bit is set. This process is repeated
until all bits are at the correct logic levels in sequence. Consequently, an N-bit ADC will only need
‘N’ attempts before all the bits are corrected. Therefore, conversion time independent of the size of the
analog voltage but it depends upon
number of bits.
Figure 11.67 shows the succes-
sive approximation type ADC con-
verter. This converter consists of a
comparator, a DAC, digital control
logic and successive approximation
register (SAR). The function of the
digital control logic is to determine
the value of each bit in a sequen-
tial manner based on the output of Fig. 11.67 Successive approximation type ADC
 Analog Digital Conversion 471

the comparator. The conversion processes starts with

sampling and hold the analog voltage when the start
of conversion signal is given. The digital control logic
set the MSB and reset all other bits. This digital data
is fed to DAC, which generates analog voltage Vref/2
and applied to comparator to compare with the input
voltage Vin. When the comparator output is high, then
the digital control logic makes the MSB 1. If the com-
parator output is low, the digital control logic makes
the MSB 0. After completion of this step, the next
MSB is 1 and other bits are 0. Again the sampled in-
put is compared to the output of the DAC with this
digital data. When the comparator is high, the second
bit is proven to be 1. If the comparator is low, the
second bit is 0. In this way, the process will continue
until all bits of digital data have not checked by suc-
cessive approximation. The successive approximation
process for converging to the analog output voltage of
DAC is shown in Fig. 11.68 (a) and (b). Flow chart
of the successive approximation process is depicted
in Fig.11.69 and the timing diagram is given in Fig.
Fig. 11.68(a) Successive approximation 11.70. The number of cycles for conversion of N-bit
process of ADC ADC is ‘N’. The bipolar analog to digital conversion
can be achieved by using a sign bit either +V or –V.

Fig. 11.68(b) Successive approximation ADC for an analog input voltage

 472 Digital Electronics: Principles and Applications

Fig. 11.69 Flow chart of successive approximation

Fig. 11.70 Timing diagram of ADC

11.14 HIGH SPEED ANALOG TO DIGITAL CONVERTERS

Sometimes, very fast analog to digital converter is required in specific applications. Consequently, high
speed ADCs have been developed using parallel technique. The maximum conversion speed is one
clock period. This high speed ADC is also known as parallel or flash ADC. In this section the operating
principle of parallel or flash A type ADCs are explained.

11.14.1 Parallel or Flash Converter

Figure 11.71 shows the flash type ADC. In case of three bit flash ADC, reference voltage V is divided
V 3 5 7 9 11 13
into eight different voltages , V , V , V , V , V , V , and V. Each voltage is applied to the
14 14 14 14 14 14 14
 Analog Digital Conversion 473

inverting terminal of a comparator and analog input voltage is also applied to the noninverting terminal
of all comparators . The outputs of comparators are fed to encoder through latches and the encoder
output is the digital data of analog input. When Vi is 0.7V, the output of comparator C7 and C6 are low
or logic level ‘0’ and other comparator C5, C4, C3, C2, C1 are high or logic level ‘1’ . In this case the
digital output of encoder is 101, which is equivalent to analog input voltage. In this way flash type ADC
converter converts analog input voltage into digital output with in one clock pulse but in two phases. In
the first phase, the analog input voltage is sampled and applied to the comparator inputs. In the second
phase, digital encoder determines the correct digital output and stores it in a register. Flash ADC can
be used as bipolar converter when weighted resistances are connected between +V and –V. Table 11.7
shows the analog input voltage, comparator outputs, and digital output of flash type ADC.
Advantage of flash converter is high speed but many comparators are required. For a three bit flash
converter, 7 comparators are required and 8-bit flash converter requires 255 comparators on a chip.
Therefore, power dissipation is very large.

Fig. 11.71 Flash ADC

Table 11.7 Analog input, comparator output and digital output of flash converter

Analog input voltage Comparator outputs Digital output

Vi C7 C6 C5 C4 C3 C2 C1 b2 b1 b0
0 ≤Vi<V/14 0 0 0 0 0 0 0 0 0 0
V/14<Vi<3V/14 0 0 0 0 0 0 1 0 0 1
3V/14<Vi<5V/14 0 0 0 0 0 1 1 0 1 0
5V/14<Vi<7V/14 0 0 0 0 1 1 1 0 1 1
7V/14<Vi<9V/14 0 0 0 1 1 1 1 1 0 0
9V/14<Vi<11V/14 0 0 1 1 1 1 1 1 0 1
11V/14<Vi<13V/14 0 1 1 1 1 1 1 1 1 0
13V/14<Vi ≤V 1 1 1 1 1 1 1 1 1 1
 474 Digital Electronics: Principles and Applications

11.15 SPECIFICATION OF ADC

Generally, manufacturers use the following specifications of analog to digital converter:
• Analog input voltage range
• Input impedance • Accuracy
• Quantisation error • Resolution
• Conversion time • Format of digital output
• T emperature stability
Analog Input Voltage Range It is the maximum allowable input-voltage range in which ADC
will operate properly. Actually it is the difference between the smallest and largest analog input voltages
to use the full range of digital outputs. Typical values are 0 to 10V, 0 to 12V, ±5V, ± 10V, and ±12V.
Input Impedance The input impedance of ADC varies from 1K ohm to 1M ohm, depending on
type of ADC. Input capacitance of ADC is approximately some pico-farads.
Quantisation Error The full-scale range of analog input voltage is quantised for conversion to
a finite number of steps. The error is process of quantisation is called as quantisation error. Generally,
the quantisation error is specified as ½ LSB.
Accuracy The accuracy of an ADC depends on quantisation error, digital system noise, gain error,
offset error, and deviation from linearity etc. Usually accuracy is determined form sum of all types of
errors. Typical values of accuracy are ±0.001%, ±0.01%, ±0.02%, and ±0.04% of full-scale value.
Resolution The resolution is defined by the ratio of reference voltage to number of output states.
Actually, it is smallest change in analog voltage for LSB.
Resolution=Reference voltage/(2N-1) where N= number of bits of the ADC.
Conversion time The conversion time of medium speed ADC is about 50µs and high speed ADC’s
conversion time is about few ns. Therefore, conversion time varies from 50µs to few ns for slow/medium
speed to high speed ADC.
Format of Digital Output Generally, ADC always use any standard code namely unipolar
binary, bipolar binary, offset binary, ones complement and twos complement etc.
Temperature Stability Accuracy of A/D converter depends on temperature variation. Typical
temperature coefficients of error are 30 ppm/°C.

Example 11.7 Design a 3-bit parallel comparator A/D converter in 2’s complement format.

� Solution
Let the analog input voltage range from 0 to V. Figure 11.72 shows the 3-bit parallel comparator A/D converter
in which reference voltage divided into eight intervals. For a particular input voltage, the comparator output
follows the Table11.8. Then comparator outputs are converted into 2’s complement format using decoder.
 Analog Digital Conversion 475

Fig. 11.72 3-bit parallel comparator A/D converter

Table 11.8 Analog input voltage, comparator outputs and 2’s complement
digital output of flash converter

Analog input voltage Comparator outputs 2’s complement digital output

Vi C7 C6 C5 C4 C3 C2 C1 b2 b1 b0
0 ≤Vi<V/14 0 0 0 0 0 0 0 1 0 0
V/14<Vi<3V/14 0 0 0 0 0 0 1 1 0 1
3V/14<Vi<5V/14 0 0 0 0 0 1 1 1 1 0
5V/14<Vi<7V/14 0 0 0 0 1 1 1 1 1 1
7V/14<Vi<9V/14 0 0 0 1 1 1 1 0 0 0
9V/14<Vi<11V/14 0 0 1 1 1 1 1 0 0 1
11V/14<Vi<13V/14 0 1 1 1 1 1 1 0 1 0
13V/14<Vi≤V 1 1 1 1 1 1 1 0 1 1

Example 11.8 How many comparators are required to design a 12 bit flash type ADC?.

� Solution
Number of comparators are required to design a 12 bit flash type ADC=2N–1=212–1=4096–1=4095
where N=Number of bits=12
 476 Digital Electronics: Principles and Applications

Example 11.9 Determine the conversion time of a duel slope 8-bit A/D converter. Assume analog
input voltage is 5V, reference voltage is 10V and clock frequency is 50KHz. What is
the maximum sampling frequency of the converter?.
� Solution
V
(a) Conversion time of A/D converter is t = 2 N Tp + i 2 N Tp
VR
where number of bits N = 8
analog input voltage Vi = 5V
reference voltage VR = 10 V
clock frequency fp = 50 kHz
1 5 1
Then conversion time t = 28 ¥ + ¥ 28 ¥ = 7 ◊ 68ms
50 ¥ 1000 10 50 ¥ 1000
(b) To determine the maximum sampling frequency, consider Vi = VR
V
conversion time t = 2 N Tp + i 2 N Tp = 2NTp+ 2NTp = 2N+1Tp
VR
1 1 f 50 ¥ 1000
The maximum sampling frequency f < = N + 1 = N p+ 1 = = 97 ◊ 65 Hz
t 2 Tp 2 29
11.16 ADC ICS
Commonly available ADC ICs are single channel 8-bit A/D converter ADC0800, eight channels 8-bit A/
D converter ADC 0808/0809, twe-
lve channels 8-bit A/D converter
ADC0816/0817, and 12-bit A/D
converter ADC80. The ADC0800 is
an 8-bit monolithic A/D converter
using P channel ion-implanted MOS
technology. It consists of a high input
impedance comparator, 256 series
resistors and analog switches, control
logic and output latches as shown in
Fig. 11.73. Conversion is performed
using a successive approximation
technique where the unknown analog
voltage is compared to the voltage
of R network using analog switches.
When the appropriate R network
voltage matches the unknown volt-
age, conversion is complete and the
digital outputs will be an 8-bit com-
plementary binary word correspond-
ing to the unknown voltage. Figure
11.74 shows the timing diagram of Fig. 11.73 Logic diagram of ADC0800
this converter. The features of the
 Analog Digital Conversion 477

ADC0800 are low cost, input ranges ±5V to ±10V, no missing codes, ratio-metric conversion, TRI-STATE
outputs, contains output latches, TTL compatible, supply voltages 5 VDC and 12 VDC, resolution 8 bits,
linearity ±1 LSB, conversion speed 40 clock periods, and clock range 50 to 800 kHz. Table 11.9 shows the
maximum values of ADC’s performance characteristics.
Table 11.9 Performance characteristics of ADC0800

Parameters Maximum value

Non-Linearity ±2 LSB
Differential Non-Linearity ±½ LSB
Zero Error ±2 LSB
Zero Error Temperature Coefficient 0.01 %/ºC
Full-Scale Error ±2 LSB
Full-Scale Error Temperature Coefficient 0.01 %/ºC
Input Leakage current 1 µA
Clock Frequency 800 KHz
Clock Pulse Duty Cycle 60 %
TRI-STATE Enable/Disable Time 1 µs
Start Conversion Pulse 3½ clock pulse
Power Supply Current 20 mA

Fig. 11.74 Timing diagram of ADC0800

The ADC80 is a 12- bit successive approximation type A/D converter. It is available in 32 pin DIP.
The important performance characteristics of ADC80 are given in Table 11.10.

Table 11.10 Performance characteristics of ADC80

Parameters Maximum value

Linearity error ±0.012%
Differential Non-Linearity ±½ LSB
Full-Scale Error Temperature 30ppm/ºC
Coefficient
Conversion time 25 µs
Analog input voltage ±2.5V, ±5V, ±10V, 0 to 5V, 0 to10V
Digital output format Unipolar and bipolar
Power loss 800mW
 478 Digital Electronics: Principles and Applications

11.17 BIPOLAR DAC AND ADC

Data converters convert data one form to another form. There are two types of Data converters such
as analog to digital converters (ADCs) and digital to analog converters (DACs). The analog to digital
converters (ADCs) convert analog quantities into digital form and used in signal processing, computing,
data transmission and control system etc. Digital to analog converters (DACs) are used to convert
transmitted or stored digital data into analog form for control, analog display and analog signal processing
etc. Some systems operate with single polarity analog voltage either positive or negative. But most of the
systems operate with positive as well as negative polarity analog voltage. Based on the polarity of analog
voltage, data converters are also classified as unipolar converters and bipolar converters. Fig.11.75 shows
the unipolar converters where analog voltage has only one polarity. These are the simplest type data
converters. The bipolar data converters are generally used in real environment. There are two types of bipolar
converters such as offset bipolar
and sign magnitude bipolar. The
offset bipolar is simplest one and
it is a unipolar converter with
an accurate 1MSB of negative
offset. The sign magnitude
converters are complex and it
has n-bits to represent about
the amplitude of voltage and an
additional bit which is used to
represent the sign of the analog
signal. Sign magnitude DACs
are very rarely used, but mostly
used in digital multimeters. The Fig. 11.75 (a) Unipolar converter (b) Offset bipolar converter and
unipolar and bipolar converters (c) Sign magnitude bipolar converter
are shown in Fig. 11.75.
In any bipolar data converter, offset error and gain error are present. Offset and gain errors are
analogous to offset and gain errors
in amplifiers. Figure 11.76 shows
the offset error and gain error of
bipolar data converter. The transfer
characteristics of data converters
(DAC and ADC) can be expressed by
a straight line which is represented
by D = K + GA, where D is the digital
code, A is the analog input voltage,
K and G are constants. In a unipolar
converter, the ideal value of K is
zero. In an offset bipolar converter,
K= –MSB. The offset error is the Fig. 11.76 (a) Offset and (b) Gain error of bipolar converter
amount by which the actual value of K differs from its ideal value. The gain error is generated due to the
difference between ideal value and actual value of G.
 Analog Digital Conversion 479

In various digital control systems, it is very useful to represent both positive and negative analog
quantities with binary codes. The most commonly used digital codes for analog to digital data
converters are straight binary, offset binary, two’s complement, ones complement and sign magnitude
codes. But offset binary and two’s complement are the most popular code for data converters. The
relationships between offset binary, two’s complement, ones complement and sign magnitude codes
for a 4-bit bipolar converter system is shown in Table 11.11. Assume that the ±5V is the full scale
input and output voltage range.

Table 11.11 Bipolar codes of a 4-bit converter

Number Scale Full scale Offset Two’s Com- One’s Sign

Base10 ±5V Binary plement Complement Magnitude
–7 –7/8 FS(+FS-LSB) –4.375 0001 1001 1000 –
–6 –6/8 FS –3.75 0010 1010 1001 1110
–5 –5/8 FS –3.125 0011 1011 1010 1101
–4 –4/8 FS –2.5 0100 1100 1011 1100
–3 –3/8 FS –1.875 0101 1101 1100 1011
–2 –2/8 FS –1.250 0110 1110 1101 1010
–1 –1/8 FS –0.625 0111 1111 1110 1001
–0 0 0.00 1000 0000 0000 1000
+1 + 1/8 FS +0.625 1001 0001 0001 0001
+2 + 2/8 FS +1.250 1010 0010 0010 0010
+3 + 3/8 FS +1.875 1011 0011 0011 0011
+4 + 4/8 FS +2.5 1100 0100 0100 0100
+5 + 5/8 FS +3.125 1101 0101 0101 0101
+6 + 6/8 FS +3.75 1110 0110 0110 0110
+7 + 7/8 FS(-FS+LSB) +4.375 1111 0111 0111 0111

In offset binary code, the zero signal value is assigned to the code 1000 and the sequence of codes
is identical to straight binary code. But the difference between a straight binary code and offset
binary code system is the half–scale offset associated with analog signal. The most negative value,
–FS + LSB is allocated for the code 0001 and the most positive value, +FS - LSB is assigned for the
code 1111.
A bipolar DAC is one that can generate both positive and negative output voltages according to
the sign of its digital input. The relationship between the offset binary code and the analog output
voltage of a 3-bit bipolar DAC is shown in Fig. 11.77. The analog output voltage of the DAC is zero
for the digital input code 100. The most negative output voltage is generally represented by the code
001 and the most positive output voltage is also represented by the code 111. The output voltage for
the digital input code 000 is also available for use whenever required.
The offset binary code for a 3-bit bipolar ADC is shown in Fig. 11.78. The digital output of ADC is
a function of its analog input voltage. It is depicted in Fig. 11.78 that zero analog represents the center
of the mid-scale code 100. The most negative input voltage is generally represented by digital code
 480 Digital Electronics: Principles and Applications

001 and most positive input voltage is

generally represented by digital code 111.
The digital output code 000 is available
for use if desired.
Two’s complement is equivalent to
offset binary with the most significant bit
is complemented. Usually it is very easy
to accomplish two’s complement code in
a data converter using a simple inverter.
The popularity of two’s complement
coding lies in the ease with which
mathematical purposes, consists of a
binary code for positive magnitude and
the two’s complement of each positive
number to represent it’s negative. The twos
complement is formed arithmetically by
complementing the number and adding 1. Fig. 11.77 Transfer function of ideal bipolar 3-bit DAC
For example, -7/8FS is obtained by taking
the two’s complement of +7/8 FS. This is done by
first complementing +7/8FS, 0111 obtaining 1000.
After adding 1 with 1000, we obtain 1001.
Usually one’s complement code is used to represent
negative numbers, although it is less popular than
two’s complement code and very rarely used. The
one’s complement of a number can be obtained by
simply complementing all binary bits of a positive
number. For example, the one’s complement of +3/8
FS, 0011 is -3/8 FS 1100. Therefore, one’s complement
code can be formed by complementing each positive
value to obtain it’s corresponding negative value.
The one’s complement code includes zero, which is
represented by either of two codes, 000 or 111. Then
ambiguity must be arise to represent zero as there is
always a single code which represents zero for ADCs Fig. 11.78 Transfer function of ideal
and DACs. bipolar 3-bit ADC
The sign-magnitude representation is the most straightforward way to express signed analog quantities
digitally. In this code simply determine the appropriate digital code for the magnitude of analog voltage
and then add a polarity bit. Sign magnitude BCD is popular in bipolar digital voltmeters, but has two
codes for zero which creates the problem. Therefore, sign-magnitude representation is unpopular for
most applications relating ADCs or DACs.
 Analog Digital Conversion 481

11.18 APPLICATIONS OF DAC AND ADC

An example of the use of a DAC can be seen in a CD player. Data stored in binary patterns on the surface
of the disc are converted to analog voltages to drive a loudspeaker. The main requirements of the DAC
are speed of operation, linearity and high resolution. Resolution is guaranteed by using multiple bit
inputs. Linearity is required to ensure accurate reproduction of the required sounds, to avoid distortion.
The rate at which inputs are fed to the DAC must be controlled using a microprocessor, or application
specific micro-controller.
AD converters are virtually used everywhere where an analog signal has to be processed, stored, or
transmitted in digital form. ADCs are used in fast video like TV tuner card. On-chip 8-bit, 10-bit, 12-bit
and 16-bit ADCs are commonly used in microprocessors and microcontrollers for digital data processing
and controlling the system like speed control of motor and temperature control of boiler etc. Very fast
ADCs are required in digital oscilloscopes and some crucial applications like software defined radio.
ADCs are used in data acquisition system, modem, and space applications like digital communication.
ADCs are also used in music and video recording. Commercial analog-to-digital converters are
usually available integrated circuit forms. Generally, A/D converters with 8 to 24 bits of resolution are
used and its sample frequency is about some KHz. The mega-sample (MHz) and giga-sample (GHz)
A/D converters are also available. Mega-sample converters are needed in digital video cameras, video
capture cards for converting analog video into digital video. Error of commercial converters usually is
about ±0.5LSB to ±1.5 LSB.

SUMMARY
In this chapter, different types of analog to digital and digital to analog converters are explained with diagrams. To
increase number of bits, D/A converters are connected in cascade. The slow speed A/D converters are single slope
serial ADC, dual slope integrating ADC, ADC using voltage to frequency converter and ADC using voltage to time
conversion. The medium speed A/D converter is successive approximation type and Parallel/flash converter is high
speed ADC. All these converters are incorporated with their merits, demerits and limitations. The parallel comparator
type is the fastest one but numbers of comparators are required more with number of bits. Therefore, successive
approximation type ADC is most commonly used, as it requires less hardware. Dual slope A/D converter is also very
popular in specified applications, namely digital instruments measuring voltage, current, etc. where speed is not very
important parameter. The static and dynamic characteristics of DAC and ADC have been discussed in this chapter.
The A/D and D/A converter ICs are also discussed in this chapter. The output of ADC and DAC ICs are compatible
with TTL, CMOS etc. logic families.

MULTIPLE CHOICE QUESTIONS

1. A digital instrument is used to measure analog voltage and display it in 7 segment display devices.
The instrument has
(a) An ADC at the input and a DAC at the output (c) A DAC at the input
(b) An ADC at the input (d) An ADC at the output
2. Sample and hold circuit is used in
(a) ADC (b) DAC (c) ADC and DAC (d) None of these
482 Digital Electronics: Principles and Applications

3. Resolution of a ‘N’ DAC is

(a) Full scale value/2N (c) Full scale value/(2N-1)
N
(b) Full scale value/(2 -1) (d) None of these
4. The minimum number of resistances are required for a 8-bit weighted-resistor type DAC is
(a) 8 (b) 9 (c) 15 (d) 16
5. In a 8 bit weighted resistor type DAC, the resistance value corresponding to MSB is 1 Kohm The
resistance value for LSB will be
(a) 16K (b) 32K (c) 64K (d) 256K
6. The resolution of a D/A converter is o.4 percent of full scale range. It is a
(a) 8 bit converter (b) 10 bit converter (c) 12 bit converter (d) 16 bit converter
7. The input resistance of an R-2R ladder D/A converter is
(a) R for each digital input (c) 3 R for each digital input
(b) 2R for each digital input (d) None of these
8. A D/A converter’s full scale output voltage is 10V and it’s accuracy is +0.4%. The maximum error
of DAC will be
(a) 20mv (b) 30mV (c) 40mV (d) None of these
9. Dynamic characteristics of DAC is
(a) Dynamic nonlinearity(DNL) (c) Offset error
(b) Gain error (d) Conversion speed

10. The speed of conversion is maximum in

(a) Successive approximation ADC (c) Single slop serial ADC
(b) Flash ADC (d) Dual slope ADC
11. An A/D converter consists of
(a) Only a DAC
(b) A DAC and a counter
(c) DAC, comparator, logic gates and a counter
(d) DAC and logic gates
12. In a 4-bit ADC, the full-scale analog input voltage 16V is divided into
(a) Sixteen equal intervals (c) Eight intervals
(b) Fifteen intervals (d) None of these.
13. The quantisation error of a 3 bit ADC is
(a) 0 (b) V/7 (c) V/14 (d) V
14. In a N bit flash converter, the number of comparators needed is
(a) 2N-1 (b) 2N (c) 2N +1 (d) None of these
15. In a N-bit single slop serial ADC, the number of clock pulses needed is
(a) 2N-1 (b) 2N (c) 2N+1 (d) None of these
16. The N bit successive approximation ADC requires
(a) 2N-1 clock pulses (b) 2N clock pulses (c) N clock pulses (d) None of these
 Analog Digital Conversion 483

17. A 12-bit A/D converter has the input voltage signal from 0V to +10V. The voltage equivalent to 1
LSB will be
(a) 0 (b) 1.2mV (c) 2.4mV (d) 0.833V
18. The number of comparators used in 3 bit parallel converter is
(a) 7 (b) 8 (c) 6 (d) None of these
19. An offset voltage ½ LSB is adder to the successive approximation ADC
(a) Improve the conversion speed (c) Reduce the maximum quantisation error
(b) Increase accuracy (d) None of these
20. Static characteristics of DAC is
(a) Conversion speed (c) Aperture time
(b) Acquisition time (d) Dynamic non-linearity (DNL)

REVIEW QUESTIONS
11.1 What is DAC? Write few applications of DAC.
11.2 Explain static and dynamic characteristics of DAC with examples.
11.3 Define resolution, accuracy, settling time, dynamic non-linearity of DAC.
11.4 Draw the N bit binary weight DAC and explain its operation. What are the disadvantages of binary
weight DAC? What is the difference between binary weight DAC and R-2R ladder DAC?
11.5 A 8 bit D/A converter has a full scale analog output of 10V. What is the analog voltage for each
step?
11.6 Draw R-2R ladder circuit for 3 bits and 6 bits. Explain their operation using equivanlent circuits.
11.7 Calculate the resolution the following DACs
(a) 4 bit (b) 8 bit (c) 12 bit (d) 16 bit
11.8 Explain the operation of sample and hold circuit with diagram. Why sample and hold circuit is used
in ADC? What is acquisition time, aperture time, and aperture jitter?
11.9 Define resolution of DAC. How will you improve it? Determine the resolution of 16 bit DAC in
percentage.
11.10 Define ADC. What are the types of ADC? Write some applications of ADCs.
11.11 List the slow speed ADCs. Write the operating principle of single slope serial ADC with diagrams.
What are the disadvantages of single slope serial ADC?
11.12 Explain the counting type ADC with a suitable diagram. What are the limitations of this converter?
How you can improve the performance of ADC?
11.13 Draw a dual slope integrating ADC and explain it’s working principle.
11.14 Explain the successive approximation ADC with a suitable diagram. Compare dual slope ADC and
successive approximation ADC in terms of accuracy, conversion speed and resolution. What is the
resolution of 12 bit successive approximation ADC.
11.15 Explain the operation of flash type ADC with a suitable diagram. What are the limitations of this
converter? Compare flash type ADC and successive approximation ADC in terms of accuracy,
conversion speed and resolution.
11.16 What is the difference between ADC using voltage to frequency converter and ADC using voltage
to time converter?.
 484 Digital Electronics: Principles and Applications

If the clock frequency is 100 KHz and the converter has a resolution of 10 bits, what is the maximum
sampling frequency?
11.17 Design a 3-bit parallel-comparator A/D converter for 2’s complement format.
11.18 How many bits of ADC will be required if resolution is 25mV and full-scale voltage is 10V?
11.19 What is extended capacity of DAC? Design a two digit BCD DAC using 4 bit DAC.
11.20 In a 8 bit DAC, the weight of LSB is 0.10V. What is the voltage for the following words?
(a) 1111 1111 (b) 1111 0000 (c) 1000 1000 (d) 1001 1001
11.21 In a 8 bit R-2R ladder type DAC, the 100mA current is supplied by the MSB. What will be the cur-
rent supplied by LSB for this converter?.
11.22 Draw a table for successive approximation type 4bit ADC. What will be the digital equivalent of
analog voltage 5V?.
11.23 Time constant of a dual slope A/D converter is 100µs. Determine the rate of capacitor charging when
input voltage is 10V. What is the complete charging time of capacitor, T1?.
11.24 Justify the following statements
(a) N bit successive approximation ADC requires only N clock pulses for complete conversion
(b) Successive approximation ADC is faster than counting type ADC
(c) Quantisation error is ±½ LSB
(d) N bit flash comparator requires 2N-1 comparators.
11.25 Why 2N-1 comparators are required for an N-bit flash ADC? Draw the logic circuit diagram of an
N-bit flash ADC and explain it’s operation.
11.26 12-bit DAC provides maximum analog output voltage 10V. What is the resolution of DAC?
11.27 How many bits DAC are required when full scale output voltage is 10 V and its resolution is
10mV?
11.28 Design the circuit of a DAC, to convert digital signals in 1’s complement from to analog output
voltage.
11.29 Find the output voltage of the circuit as shown in Fig.11.79, when Roff =5Kohm, Voff = -5V and binary
input is 101.

Fig. 11.79
11.30 In a Voltage to frequency converter, the range of analog input voltage is 0 to 12V and the corre-
sponding frequency range is 0 to 10KHz. When this Voltage to frequency converter is used in a A/D
converter with a resolution of 8-bits, determine the digital output for 5V analog input voltage.
 CHAPTER

12
SEMICONDUCTOR MEMORIES
12.1 INTRODUCTION
Data can be stored either in analog or digital form. In analog form, the magnitude of a voltage signal is
stored in a magnetic material by means of magnetisation. In audio and video technology, a thin plastic
tape made by particles of iron-oxide material can be magnetised or demagnetised by the application of
an electromagnetic field from an electromagnet coil. The data can also be retrieved from the magnetised
tape by moving the tape through another electromagnet coil. During retrieving the data, a voltage will
be induced across the coil due to the magnetised spots. The strength of magnetisation changes with time
means degrading of magnetisation. Therefore, analog signal reproduced from magnetic tape will be less
magnitude. In the same tape, data can also be stored in digital form. When the same tape is used to store
data in digital form, the strength of magnetisation on the tape should have two discrete levels high or low. If
the tape is exposed to artificial magnetic fields, some memory locations on the tape will be slight alteration
of magnetic field strength. Though the magnetic tape signal degraded or altered, no data corruption is
possible. Therefore, the most evident advantage of digital data storage is the resistance to corruption. But
sometimes the alterations or degradation will be very extreme that data on the tape will be corrupted but
the parity and checksum error detection techniques can be used to protect against data corruption.
Generally, memory devices are used to store digital information. The simplest type of digital memory
device is flip-flop, which is capable for storing single bit data, and is volatile and very fast. This device
is generally used to store data in form of registers. Registers are also used as main memory of computers
for internal computational operations. The basic goal of digital memory is to store and access binary
data, which is a sequence of 1’s and 0’s.
A memory cell unit is used to store a single bit
of information. A flip-flop, a charged capacitor, and
a single spot on a magnetic disk are examples of
memory cells. Figure 12.1 shows a memory cell
unit. This digital memory cell has three terminals
—
namely read/write (R/W ), address enable (AE) and
data in/data out and consists of D flip-flop, two
buffer, two AND gate and one inverter as depicted
in Fig.12.1. The data in and data out use a common
bus line by connecting two tristate buffers such as
input buffer and output buffer. The enable terminals
of buffer are connected with the output of AND Fig. 12.1 Memory cell unit
 486 Digital Electronics: Principles and Applications

gates. When address enable AE = 0, both tristate buffer are disabled and they will be in high impedance
—
state. When address enable AE = 1, data read or data write operation will be performed based on R/W
signal. If R = 1 and AE = 1, output buffer will be enabled and read operation will be performed. When
—
W = 0 and AE = 1, input buffer will be enabled write operation can be performed.
A group of memory cells are used to represent data or program instructions. The actual information
being stored in the memory device is called as the data. The memory data size is variable depending
on the digital system. Typical data sizes are 4, 8, 16, 32, and 64 bits. A special term ‘word’ is used to
refer to a group of 8-bits or one byte. An 8-bit word contains 1 byte, and a 16-bit word contains 2 bytes,
etc. The total number of bits of a memory device is known as memory capacity. The more number of
bits in a device means the higher it’s density or capacity. Each word in a memory device or memory
system has a unique address. The location of this data within the storage device is typically called the
address. Memories are self-available in the form of integrated circuits so that it can hold information.
The memory chips also store information in binary from, which consists of 1’s and 0’s. In this chapter,
types of memory, memory organisation and it’s operation, programming of memory and memory ICs
have been discussed.
12.2 CLASSIFICATION OF MEMORY
There are two types of semiconductor memories, namely ROM and RAM. The ROM stands for read only
memory and data are permanently stored in memory cells. We can able to read data from the memory.
ROM cannot be reprogrammed. This memory is nonvolatile and data retain when power is switched
off. But the data contents of ROM are accessed randomly just like the volatile memory circuits. Vinyl
records and compact audio disks are typically referred as read - only memory or ROM in the digital
systems. The RAM stands for random access memory, which means that any storage memory location
can be accessed to read or write operation. RAM is volatile memory, so data will be lost if power is
switched off. In this section, classification of ROM and RAM are explained.
12.2.1 Classification of ROM
ROMs are manufactured with bipolar technology and MOS technology. Figure 12.2 shows the classifi-
cation of ROM. The different features of ROM, PROM, EPROM and EEPROM are explained below:
ROM (Read Only Memory) The data
is permanently stored in the memory and these
devices are mask programmed during manu-
facturing. ROMs cannot be reprogrammed and
nonvolatile type. These devices are cheaper
than programmable memory devices. The
applications of ROM are fixed programmed
instructions, look-up tables, conversions, and
Fig. 12.2 Classification of ROM
some specific operations.
PROM (Programmable Read Only) The data can be electrically stored. It can be programmed
by blowing built-in fuses and can be reprogrammed and nonvolatile type. These memory devices are
very low memory density and occupy more space.
EPROM (Erasable Programmable Read Only Memory) These are strictly a MOS device
and programmed by storing charge on insulated gates. These devices are erasable with ultraviolet rays
and reprogrammable after erasing. These memory devices are non-volatile type.
 Semiconductor Memories 487

EEPROM (Electrically Erasable Programmable Read Only Memory) These

memory devices are electrically programmable by the programmer and the stored data can be erased by
electrical means. This is nonvolatile type. This is also called as electrically alterable programmable read
only memory (EAPROM).
12.2.2 Classification of RAM
Read only memory is used only for reading data which is already stored in the memory. ROMs can be
programmed only once and data once recorded cannot be erased. In a RAM, data can be written into it’s
memory as often as desired and the data stored in a RAM can be read without destroying the contents
of the memory.
Data can be written into and read from a RAM at any selected address in any sequence. When data
are written into a given address in the RAM, the data previously stored at that address are destroyed and
replaced by the new data. When data are read from a given address in the RAM, the data at that address
are not destroyed. The non-destructive read operation can be thought of as copying the contents of an
address while leaving the content intact. A vinyl record platter is an example of a random-access device.
RAM memory is typically randomly accessed and it is actually virtual or volatile memory.
There are two types of RAMs, such as, static RAM and dynamic RAM. The basic memory cell in a
static RAM is a flip-flop, bipolar or MOS. After a bit has been stored in the flip-flop of a memory cell,
it will remain there while power is available. Dynamic RAMs called DRAMs are based on charge,
which is stored by using MOS devices. Since this charge is dissipated by passage of time, DRAMs
need periodical recharging or refreshing. Static RAMs and Dynamic RAMs are volatile devices. The
comparison between different memories based on category, erasing property, writing mechanism and
volatility is illustrated in Table 12.1.
Table 12.1 Comparison of memories
Types of Memory Category Erasing property Writing mechanism Volatility
Read only Read only Not possible Masks Nonvolatile
Memory(ROM) Memory
Programmable Read only Not possible Electrically Nonvolatile
ROM(PROM) Memory
Erasable Read only Ultra violet light and Electrically Nonvolatile
PROM(EPROM) Memory chip level
Electrically Erasable Read only Electrically and byte Electrically Nonvolatile
PROM(EPROM) Memory level
Flash memory Read only Electrically and Electrically Nonvolatile
Memory block level
Random access Read and write Electrically and byte Electrically Volatile
memory(RAM) memory level

Generally, RAMs are also manufactured with

bipolar technology and MOS technology. The bipolar
RAMs are static RAMs but MOS RAMs are static and
dynamic types. Figure 12.3 shows the classification
of RAM. The different features of static and dynamic
RAM are explained in this section.
Static RAMs These RAMs are built with static or
dynamic cells. Five or six t ransistors are used to store a Fig. 12.3 Classification of RAM
 488 Digital Electronics: Principles and Applications

single bit. Data can be written and read with in nanoseconds. Usually TTL, ECL, NMOS and CMOS tech-
nology are used to manufacture static RAMs. When the power is shut off, data stored in cells can be lost.
Dynamic RAMs In a dynamic memory, data can be stored on capacitors and to retain data every
cell has to be refreshed periodically. One transistor is used to build memory cell and required less space.
These memories consume less power compared to static RAMs.

12.3 MEMORY ORGANISATION

Figure 12.4 shows the block diagram of a M × K bits memory structure. It has N bit input lines to locate
an address of memory and each address line can
store K bits. So the total number of bits in the
memory is M × K bits. Each memory location
is represented by address lines to locate ‘M ’ ad-
dress locations. Here, ‘N ’ bits inputs are required
to locate ‘M’ address locations. The relationship
between address locations and input lines is 2 N =
M. To generate an address line, a ‘N ’ lines to ‘M ’
lines decoder is used. Actually decoder decodes
‘M ’ locations depending upon inputs. The num-
Fig. 12.4 Block diagram M × K bits Memory ber of locations and number of bits may be varied
Table 12.2 for different memories. When ‘M ’ number of lo-
Address Range of memory Total number of
cations is present in memory and ‘K’ the number
inputs locations memory locations
of bits are present in each location, the size of
2 00-03 4 bits the memory is M × K bits. Table 12.2 shows the
4 00-0F 16 bits relationship between number of address lines and
6 00-3F 64 bits memory locations. The size of commonly used
8 00-FF 256 bits memory devices are 64 bits, 256 bits, 512 bits,
10 000-3FF 1024 (1KB) 1024 (1KB), 2048 (2KB), 4096(4KB), 16384
12 000-FFF 4096 (4KB) (16KB) but the common values of word size are
14 0000-3FFF 16384 (16KB)
16 0000-FFFF 65536 (64KB)
1, 2, 4, 8, 12, and 16 bits etc. The chip enable
18 00000-3FFFF 262144 (256KB) (CE) signal is used to enable the address lines for
20 00000-FFFFF 1048576 (1MB) selecting a bit or a group of bits.

12.4 MEMORY
OPERATION
Memories can be building
up by flip-flops or capacitors
in semiconductor memories
and magnetism in magnetic
storage. The storage element
is called a cell. Each storage
element can store either logic
‘1’ or logic ‘0’. The simplified Fig. 12.5 Write data in address 0
 Semiconductor Memories 489

concept of memory writes operation with proper

memory addressing and 8-bits storage capacity
of memory is shown in Fig. 12.5. Each memory
location can store one or more than one bits. The
total number of bits, which can store in a memory,
is called as memory capacity. As there are eight
memory addresses from 0 to 7 and 8-bits data
can store in each memory location, then memory
capacity is 8 × 8 = 64-bits. It is depicted in Fig. 12.6
that eight numbers of bits or one byte are already
stored in one address-0 of memory. When memory
read operation is performed, the stored information Fig. 12.6 Read data from address 0
11101111 will be read from address-0.
The memory operation can be explained with the help of control bus, data bus and address bus. The
control bus contains the signals
which tell the memory, whether
data will be read from memory
through data bus or data will be
written on the memory through
data bus when the memory
address is specified by the address
bus information. The data bus is
usually a bi-directional tri-state
bus that interfaces with many of Fig. 12.7 Memory devices with address bus, data bus and
the computer functional areas. control bus
The address and control busses are usually unidirectional busses. Figure 12.7 shows the block diagram
of memory devices with address bus, data bus and control bus. The memory read and writes operations
are explained below:

Memory Read Operation

To transfer data from the memory to the
microprocessor through memory read
operation, 16-bit address bus is used
to read from memory. This address is
loaded into address buffer and put on
the address bus. Once address code is
on the bus, the microprocessor control
unit sends a read signal to the memory.
At the memory, the address bits are Fig. 12.8 Memory read operation
decoded and the desired memory
location is selected. Then read signal causes the contents of the selected address to be put on the data
bus. The data byte is then loaded into the data register. Figure 12.8 shows the memory read operation.
The steps of memory read operation are:
 490 Digital Electronics: Principles and Applications

• Address put on the address bus.

• Read signal applied.
• Content of address in the memory put on data register.

Memory Write Operation

To transfer data from data bus to memory, a memory write operation is required. Figure 12.9 shows the
memory write operation. The memory can be addressed in the same way as memory read operation. A
data byte will be stored in data register, which is put on the data bus. After that, send the memory write
signal. This causes the byte on the data
bus to be stored at the selected location
in the memory as specified by the 16-bit
address code. Then content of the memory
location are replaced by the new data. The
steps of memory write operation are as
follows:
• Address put on address bus.
Fig. 12.9 Memory write operation
• Data put on data bus.
• Write signal causes data to be stored.

12.5 SEMICONDUCTOR READ-ONLY MEMORIES

There are five types of read-only memories (ROM), namely mask-programmable ROM, programmable
ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM
(EEPROM) and flash memory. All five types of ROM are non-volatile but each has advantages and disad-
vantages relative to the others.
These memories are used in a
read-only mode during nor-
mal operation. The process of
writing information into these
devices is usually referred to
as the programming operation.
ROM contains permanently
stored digital data. ROMs are
used repeatedly in system ap-
plications, like look up tables,
programmed instructions, and
code conversion from one
system to other.

Fig. 12.10 Internal structure 256¥4 ROM

 Semiconductor Memories 491

12.5.1 ROM Structure

A ROM is an encoder, which has ‘n’ inputs and ‘m’ outputs. Any one channel will be selected at a time
and output will be available in all output lines. Internal structures of ROM ICs are very complex. Figure
12.10 shows the memory organisation of 256 × 4 ROM. In this device, there are 256 rows and 4
columns in the memory array. When any one of 256 binary codes is applied to the address inputs, four
bits appears on the outputs if the chip-select inputs are low. This memory cell array is an array which is
actually represented by 32 ×32 matrix. This memory array has 32 rows and 32 columns.
Figure 12.11 shows the memory organisation of 32 × 32 ROM. It has 32 rows and 32 columns. 5-bit
address lines control the Rows and three bit address lines select the column. The address lines and output
lines are buffered. Five-address lines A0, A1, A2, A3 and A4 are decoded by the row decoder to select any
one of the 32 rows. The three address lines A5, A6 and A7 are decoded by the column decoder to select
four of the 32 columns. The decoder consists of four 3 line to 8 line decoders. When eight-bit address
code A0–A7 is applied, a four bit data appears on the data outputs when chip select lines are low to enable
the output buffers. When a binary address code is applied to the address input, the corresponding row
line goes high. This high is connecting to the column lines through transistors at each junction where a
‘1’ is stored. At each cell where ‘0’ is stored, the column lines form the data output. The eight data bits
stored in the selected row appear on the output lines.

Fig. 12.11 Internal structure of typical ROM 32×32 memory array

12.5.2 ROM Expansions

ROMs are available in one-bit, four-bit, eight-bit word configurations. Sixteen bit and more than sixteen
bit ROMs are also used in some applications. Therefore, expansion memory chips are required to
increase word size and word capacity.

Expansion of Word Size

When the word size in the available ROM is M and the required word size is N, M/N number of memory
ICs are required. In this case, the memory ICs should be connected as follows:
 492 Digital Electronics: Principles and Applications

• The corresponding address input lines of the ICs must be connected together. So that memory
size is fixed byte.
• The chip enable (CE) or chip select (CS) inputs of the ICs must be connected together.
• The number of output lines will be equal to the word size of each IC × the number of ICs used.
Suppose 1K × 1 memory can be used to develop 1K × 2 memory after connecting two 1K memory
ICs. Here memory size is fixed byte; word size is increased from 1 bit to 2 bit. Figure 12.12 shows the
connection diagram of two 1K × 1 ROMs expanded to 1K × 2 ROM. Another example is that four 1K
× 1 ROMs have been expanded to 1K ×4 ROM as depicted in Fig. 12.13.

Fig. 12.12 Two 1K ¥ 1 ROM expanded to 1K ¥ 2 ROM

Fig. 12.13 Four 1K ¥ 1 ROM expanded to 1K ¥ 4 ROM

Expansion of Word Capacity

When the memory requirement is M words and the available memory IC capacity is N words, M/N
numbers of ICs are required to fulfill the requirement. Similar with expansion of word size, ICs should
be connected as follows:
• The corresponding lower order address input lines are connected together, so that the A inputs are
connected together.
 Semiconductor Memories 493

• While two ICs are used, the chip enable (CE) or chip select (CS) input of one IC is connected with
MSB and the enable input of the other IC is connected with MSB through an inverter. Therefore,
only one of the ICs is enabled at a time.
• When more than two ICs are used in memory expansion, a decoder should be used to enable the
ICs, so that only one IC must be enabled at a time.
• The corresponding output lines
of the ICs should be connected
together.
Figure 12.14 shows the expansion
of memory to increase word capacity.
A 256×4 memory has 256 word
capacity and can store 256 × 4 =1024
bits. To expand the memory size from
1024 bits to 2048 bits, the above figure
will be used. Eight-address lines,
A0 to A7, are directly connected with
memory IC terminals. The chip select Fig. 12.14 Two 256 × 4 ROM expanded to 512×4 ROM
line is connected with most significant
bit address line and inverted MSB is connected with chip select line of the next IC. Therefore,
memory addresses from 0 to 255 are located first memory IC1 and memory addresses from 256 to
511 are also located in memory IC2. One memory will be selected at a time and data out from one
memory only. The corresponding output terminals are connected together for output. Figure 12.15
shows the connection of four 256 × 4 ROM to develop a 1024 × 4 ROM using 256 × 4 ROMs.

Fig. 12.15 Four 256 ¥ 4 ROM expanded to1024 ¥ 4 ROM

12.5.3 ROM Access Time

The propagation delay between address inputs and data outputs of a ROM always exist in each READ
operation of ROM. Figure 12.16 shows the timing diagram for READ operation of ROM. The propa-
 494 Digital Electronics: Principles and Applications

gation delay time from the applica-

tion of a valid address on the inputs
of ROM to the appearance of a valid
output at output terminals of ROM is
represented by tAA. tAA is also called as
access time. The range of access time
is about 35–70ns. tOE is the propaga-
tion delay from chip enable to valid
data output. It is known as output en-
able time. Usually the range of out-
Fig. 12.16 Timing diagram for READ operation of ROM
put enable time is about 20-30ns.

Example 12.1 Draw the diode ROM architecture for Table 12.3.

Table 12.3

Inputs Outputs
A B C F0 F1 F2 F3 F4
0 0 0 1 1 0 1 0
0 0 1 1 1 1 0 0
0 1 0 0 0 0 0 1
0 1 1 1 1 1 0 1
1 0 0 0 1 0 1 0
1 0 1 0 1 1 1 1
1 1 0 1 0 1 0 1
1 1 1 1 1 0 1 0

� Solution
Table 12.3 shows the truth table
of five output functions F0, F1,
F2, F3 and F4. The implementa-
tion of Table 12.3 using Diode
ROM is depicted in Fig. 12.17.
Here, three address inputs A,
B, C are fed to a 3-line to 8-line
address decoder. Based on the
address inputs, a particular row
will be selected and output will
be obtained at output lines. For
example, when A=B=C=0, the
first row will be selected and
output 11010 will be available
at output lines F0, F1, F2, F3
and F4. Fig. 12.17 Diode ROM implementation of Table12.3
 Semiconductor Memories 495

Example 12.2 Implement the BCD to Excess-3 code conversion using ROM

� Solution
Table 12.4 show the BCD to excess-3 code conversion table. Figure 12.18 shows the implementation of
BCD to excess-3 converter using diode ROM. For a BCD code on address inputs, a particular row will be
selected and its equivalent gray code will be output at output lines of all columns. For example, excess-3
code of BCD input 0 (0000) is 3 (0011). If A=B=C=D=0 is applied to address decoder, the first row will be
selected and output 0011will be obtained at output lines D3 D2 D1 D0.
Table 12.4 Binary to Excess-3 converter

BCD Gray
A B C D D3 D2 D1 D0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0

Fig. 12.18 Diode ROM for BCD to excess-3 code conversion

 496 Digital Electronics: Principles and Applications

Example 12.3 Draw a basic ROM array for four-bit binary–to-gray conversion.

� Solution Table 12.5 Binary to Gray converter

The binary to gray code conversion table is Binary Gray
given in Table 12.5. Figure 12.19 shows the
implementation of binary to gray converter-using A B C D G3 G2 G1 G0
diode ROM. For a binary code on address inputs, 0 0 0 0 0 0 0 0
a particular row will be selected and its equivalent 0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
gray code will be output at output lines of all 0 0 1 1 0 0 1 0
columns. Here four bits binary address inputs 0 1 0 0 0 1 1 0
A, B, C, and D are applied to a 4-line to 16-line 0 1 0 1 0 1 1 1
address decoder. When A=B=C=0 and D=1, the 0 1 1 0 0 1 0 1
second row will be selected and output 0001 will 0 1 1 1 0 1 0 0
be available at output lines G3 G2 G1G0. 1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
12.5.4 Mask-Programmable 1 0 1 1 1 1 1 0
ROM 1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
The mask ROM is the simplest ROM. It is per- 1 1 1 0 1 0 0 1
manently programmed during the manufactur- 1 1 1 1 1 0 0 0
ing. Some specified functions are
only stored in ROM. After the
programming, the data stored in
ROMs cannot be changed. Since
the ROM program is part of the
manufacturing process, this type of
ROM is very inflexible and expen-
sive to produce unless a large num-
ber of identical devices are needed.
An array of semiconductor memo-
ry ROM devices can be developed
by using diodes, transistors, and
field effect transistors. Presence
or absence of diodes, transistors,
field effect transistors at the con-
nection of row/column junction
represents either ‘1’ or ‘0’. Figure
12.20 shows the diode ROM cells.
If diode is connected between row
and column, 1 is stored. When di-
ode is not presence between row
and column, 0 is stored. The bipo-
lar transistor ROM cell is depicted
in Fig. 12.21. When the row line is Fig. 12.19 Diode ROM for binary to gray conversion
 Semiconductor Memories 497

connected with the base of a transistor, 1

stored in cell. If the row line is high, all
transistors, which are connected to row
line, turn on and connected the high to the
associated column lines. If the row/column
is connected with the base of transistor, the
column line will be low or 0 though row Fig. 12.20 Diode ROM (a) storing 1 (b) storing 0
is addressed. Figure 12.22 shows field ef-
fect ROM cells. The operation is same as
bipolar ROM. The presence or absence of
MOS gate at junction of row and column
can store ‘1’ or ‘0’.
A 4 × 4 bit ROM array using diode,
bipolar transistor, and MOSFET are
illustrated in Fig. 12.23, 12.24, and 12.25 Fig. 12.21 Bipolar ROM (a) storing 1 (b) storing 0
respectively. A particular address input
applied to decoder, a row line will be
selected. The column line is connected
with row line through diode or transistor
or MOSFET. The stored data will be
available at output. Here, A and B are
address inputs of 2 line to 4 line address
decoder to select any one ROW and four
output signals F0, F1, F2, and F3. When Fig. 12.22 MOS ROM (a) storing 1 (b) storing 0
A=0, B=0, ROW 0 will be selected and the output signals will be F0=1, F1 =1, F2=0, and F3=1. Similarly,
for other values of input signals, output will be available at F0, F1, F2 and F3.

Fig. 12.23 4 ¥ 4 Diode ROM array

 498 Digital Electronics: Principles and Applications

Fig. 12.24 4¥4 Bipolar transistor ROM array

Fig. 12.25 4¥4 Field effect transistor ROM array

12.5.5 Programmable ROM (PROM)

The programmable ROM (PROM) is similar to the mask-programmable ROM except that the
interconnections between ROW and COLUMN are fusible links that are user programmable. Generally,
PROMs are available in bipolar and MOS technology with four bit or 8 bit outputs. Usually PROMs
are used the fusing process to store bits. When a memory link fused is opened or connected, data ‘0’
or ‘1’ will be stored in the memory cell. This fusing process is not reversible. Once PROM devices are
programmed, reprogramming is not possible. The fuse links are manufactured into the PROM between
the intersection of row lines and column lines as depicted in Fig. 12.26 and Fig. 12.27. A PROM is
 Semiconductor Memories 499

manufactured with all of it’s transistors connected. The PROM is programmed by placing it into a
special instrument called as PROM programmer or PROM burner. The original chip is blank, and the
programmer burns in specific instructions. The programmer provides sufficient voltage and current in
the programming mode to burn out the desired fusible links and store 0. If the link is left as it is or intact,
the data 1 is stored. Initially, select the link using the PROM’s address and data lines, and then applying
a high voltage pulse to the device through a special input pin vaporizes the link. The advantage of the
PROM is user programmable but it can only be programmed once. Usually metal links, silicon links and
pn junctions are used to manufacture fuses.

Fig. 12.26 Bipolar transistor PROM with fusible links

Fig. 12.27 MOS PROM with fusible links

 500 Digital Electronics: Principles and Applications

Metal Links Metal links are made of nichrome material. Each bit in the memory array is represented
by a very thin layer link, which is connected between row lines and column lines. During programming,
this thin layer link is either blown off or left intact. The memory cell will be selected by address lines
and then passing about 20–50 mA current through the link to blown off.

Silicon Links These links are developed by a thin layer polycrystalline silicon fuse. Programming
of polycrystalline silicon fuses is done by passing a sufficient amount of current 20–30mA. Due to flow
of current, a high temperature is developed at the fuse location and then the silicon oxidises and forms
an insulation material. Therefore, the link will be opened.

Shorted Junction In shorted junction technology, two

p-n junctions are connected back to back in between the inter-
section of row and column as depicted in Fig.12.28. One of the
diode junctions is avalanched in programming process. If the
diode D1 is reversed biased, heavy flow of electrons in reverse
causes aluminum ions to migrate and short the junction. Then
the junction can be used as a forward-biased diode to represent Fig. 12.28 Shorted junction using
a data bit ‘1’. two P-N junctions

Example 12.4 Implement the truth Table 12.6 using bipolar transistor PROM with fusible links

� Solution Table 12.6

Table 12.6 shows the truth table of two binary inputs Binary Output
A, B and four output functions F0, F1, F2 and F3. The
A B F3 F2 F1 F0
implementation of Table 12.6 using bipolar transistor
0 0 1 0 1 0
PROM with fusible links is illustrated in Fig.12.29. This
0 1 0 1 0 1
PROM has two address inputs A and B, which are fed to a 1 0 1 0 1 1
2-line to 4-line address decoder and four output functions 1 1 1 0 0 1
F0, F1, F2 and F3. When A=0 and B=0 on the address
inputs, ROW 0 will be selected and the output F3=1, F2=0, F1=1, F0=0 are obtained as the memory cell (0,0)
and (0,2) are fused for storing 0 and other memory cells of ROW 0 are intact for storing 1. Similarly, output
for other rows can be verified.

12.5.6 Erasable Pro-

grammable ROM
(EPROM)
To fulfill the user desire that reprogram-
ming of the ROM, the erasable pro-
grammable ROM (EPROM) has been
developed. It is programmed just like
a PROM. In the EPROM, the transistor
and fusible link of the PROM are re-
placed with a transistor. Each transistor
has two gates: floating and non-floating. Fig. 12.29 Implementation of F1,F2,F3, and F4 using PROM
 Semiconductor Memories 501

The floating gate is unconnected and it is enclosed by high–impedance-insulating materials. During

programming of EPROM, the programmer applies a high voltage to the non-floating gate. Then the
insulating material will be breakdown and allows a negative charge to accumulate on the floating gate
of the transistor, which turns the transistor on, yielding a LOW at the output. When high voltage is
removed, the trapped charge remains forever even with power turned off. During read operation, the
negative charge prevents the transistor from turning on. When it is exposed to ultra violet light with a
certain wave-length, the insulating material around the floating gate will behave conductive. Therefore,
the EPROM device is erased by exposing the chip to ultra violet light for 5–20 minutes. Actually, all
trapped charges are removed and turn all of the transistors off yielding HIGH states for every cell. The
EPROM is programmed like the PROM by keeping it in a special EPROM programmer.
Due to the elimination of the fusible link in EPROM, memory density will be increased with respect to
PROM but a decrease in speed because of applications of the floating gate type transistors. The ultimate
goal for ROM’s is to develop a ROM device, which can be used to write and erased with electrical
signals. Then the new development is the electrically erasable programmable ROM (EEPROM).
Consequently, there are two basic types of erasable PROMs: ultraviolet light erasable PROM (UV
EPROMs) and electrically erasable PROM (EEPROM). Both types of EPROMs use capacitive charge
MOSFET devices to latch on or off.
Ultraviolet light erasable PROM (UV EPROMs) is easy to identify as these devices have a transparent
glass window, which is used to expose the silicon chip material to ultraviolet light. After programming,
the glass window must be covered with tape to prevent ambient light and also degrading the data over
long time.
Figure 12.30 shows the floating gate EPROM cell. The operation of this cell depends on the movement
of charge from either source or drain to the floating gate by avalanche injection of electrons. For charge
movement, generally high voltage about 20V to 30V is applied across the transistor. The amount of
charge transfer to floating gate is directly proportional to amplitude of applied voltage and its time
duration. The avalanche injection of EPROM cell is depicted in Fig.12.30 (a).
After removing the applied voltage, the charge trapped in the floating gate and retained for long time,
as there is no discharge path for the accumulated electrons. Then the binary data ‘1’ is stored in EPROM
cell as given in Fig.12.30 (b).

Fig. 12.30 EPROM Cell (a) avalanche injection (b) removing programming voltage
leaves charge trapped
The accumulated charge on the floating gate can be removed by ultraviolet light. Due to flow of
photo current from floating gate to the silicon substrate, the gate return back to initial condition after
discharging. In this case, EPROM cell will be off and will be at logic ‘0’. Figure 12.31 shows the
ultraviolet erasable PROM.
 502 Digital Electronics: Principles and Applications

2732A is a 32K (4kb × 8) NMOS EPROM and its

access time is about 250ns. EPROMs in the 2732A series
are available with very large storage capacities up to
524288 bits. All EPROMs in this series have 8-bit wide
Transparent
outputs and are available with different access times. glass window
EPROM 2732A has 32,768 bits and its organisation
is 4096 × 8 and is ultraviolet erasable. Pin diagram of
2732A is shown in Fig. 12.32 and the pin description
is given in Table 12.7. The block diagram of 2732A is
depicted in Fig. 12.33. It has 12 address inputs to access Fig. 12.31 Ultraviolet erasable PROM
4096 × 8 bit words in the memory.The output enable/
—–
power supply (O E /VPP) is used to perform read as well as write
operation. The 12-bit address lines can select one of the 4096
words in the memory. The selected word will be obtained at the
—– —–
output terminals if the chip enable C E and output enable O E /VPP
are low. Figure 12.34 shows the timing diagram of EPROM read
operation. Address access time (tACC) is equal to the propagation
delay from address to output and it varies in between 250–350
ns. Valid data is available at the outputs with a tOE delay from
—–
the falling edge of O E and the range of tOE delay time is about
—–
100–120 ns. The delay from C E to output is tCE and it’s value is
approximately 250–350 ns assuming that CE has been low and
addresses have been stable for at least tACC ± tOE.
During data writing or programming into the EPROM, the out-
—–
put enable pin OE /V PP should be connected to supply voltage.
The data is selectively written into specified address locations by
writing in ones. The data to be written into memory is applied to
the data output pins O0 through O7. When the address and data Fig. 12.32 Pin diagram of
2732A EPROM IC
are stable, a short duration TTL low-level pulse is applied at the
—–
CE input. A program pulse must be applied at each address location to be programmed. Any location
may be programmed at any time individually, sequentially, or at random. Figure 12.35 shows the timing
diagram of EPROM programming.
Table 12.7 Pin description of 2732A EPROM
Pin Number Description Pin Number Description
1 A7 - Address Input 13 Q3 - Data Input
2 A6 - Address Input 14 Q4 - Data Input
3 A5 - Address Input 15 Q5 - Data Input
4 A4 - Address Input 16 Q6 - Data Input
5 A3 - Address Input 17 Q7 - Data Input
6 A2 - Address Input 18 E - Enable
7 A1 - Address Input 19 A10 - Address Input
8 A0 - Address Input 20 G - Output Enable/Program Supply
9 Q0 - Data Input 21 A11 - Address Input
10 Q1 - Data Input 22 A9 - Address Input
11 Q2 - Data Input 23 A8 - Address Input
12 Vss - Ground 24 Vcc - Positive Power Supply
 Semiconductor Memories 503

Fig. 12.34 Timing diagram of EPROM read

Fig. 12.33 Block diagram of 2732A EPROM IC operation

12.5.7 Electrically Erasable PROM (EEPROM)

The EEPROM technology adds a second transistor to each cell and allows writing and erasing electrically
on a bit by bit or word-by-word basis. Since the writing and erasing operations are done by electrical
signals, there is no need to remove the
device from the circuit for reprogramming.
Due to additional transistor in the device
to confer the electrical writing and erasing,
the density of the EEPROM is significantly
lower than the EPROM and the device
cost is high. The programming and erasing
speed of the EEPROM is very faster than
EPROM. This type of device is also known
as electrically alterable ROM (EAROM).
There are two types of EEPROM, namely
floating gate MOS and metal-nitride-oxide-
silicon (MNOS). When a voltage is applied
on the control gate in the floating gate
structure, the charge will be stored in the
floating gate during writing and the stored Fig. 12.35 Timing diagram of EPROM programming
charge will be removed from the floating which indicates Address setup time (tAS), Data setup
time (tDS), VCC setup time (tVCS), VPP setup time (tVPS), Pro-
gate in erasing mode. gram pulse width (t ), OE setup time (t ), Data hold
PW OES
time (tDH)
12.5.8 Flash Memory
EEPROMs are lower density and higher cost than EPROMs. Therefore, the flash memory with EEPROMs
features has been developed. This type of memory is basically identical to EEPROM technology except
that the whole memory, or a sector of the memory can be erased at one time. This memory uses 5 volts
to read or write operation and 12 volts to erase. Here memory is written in blocks and can provide faster
 504 Digital Electronics: Principles and Applications

changes than EEPROM. It is changeable many 100s of thousands of times but slower than RAM to
access.
Flash memory uses a single transistor cell like the EPROM but the structure of the transistor is
different and slightly larger and allows for electrical erasing. Flash memory gets its name because of its
rapid erase and writes times. It is slightly more expensive than EPROM but much less expensive than
EEPROM. The advantage is that a higher density much closer to the EPROM is achieved and therefore
the price per bit is cheaper. Flash memory is typically erased in sectors rather than on an individual word
basis, which makes it less flexible than EEPROM. Another advantage of flash memory over EPROM
is that it can be reprogrammed while residing on board. Typical applications are solid-state disks and
firmware memory. The non-volatility, density, speed, and low power requirements of flash memory
make it an excellent substitute for replacing hard disks in low power computer systems.

12.5.9 ROM ICs

The organisation and operation of 2732A EPROM IC are already explained briefly in Section 12.5.6
Most commonly used ROM ICs are given in Table 12.8 with their category, organisation, package,
access time, technology and power dissipation, etc.

Table 12.8 Commonly used ROM ICs

IC No. Category Package Organisation Technology Access Power

time dissipation
6206D Mask PROM 16 pin DIP Package 512 × 4 Bipolar 60ns 625mW
23C1010 MASK ROM 32-PIN DIP/PDIP/SOP/ 128K × 8 MOS 45ns 250mW
PLCC/TSOP Package
23C2000 MASK ROM 32 pin PDIP/ PLCC/SOP/ 256K × 8 MOS 70ns 250mW
TSOP Package
23C4000 MASK ROM 32 pin PDIP/ PLCC/ SOP/ 512K × 8 MOS 90ns 210mW
TSOP Package
23C6410 Mask ROM 44 pin SOP and 48 pin 8M × 8 4M × 16 MOS 100ns 420mW
TSOP Package
Am1702A PROM 24 pin duel in-line her- 256 × 8 MOS 550ns 1000mW
metic cerdip package
3602A PROM 16 pin DIP package 512 x 4 Bipolar 70ns 750mW
3605 PROM 18pin DIP package 1024 x 4 Bipolar 70ns 800mW
27C256 EPROM 28-pin DIP package and a 32,768 x 8 Low-power 250 ns 55 mW
32-pin windowed LCC CMOS
2716 EPROM 24-pin DIP package 2048 x 8 MOS 450ns 525mW
2732A EPROM 24-pin DIP package 4096 x 8 MOS 250 ns 790mW
2764 EPROM 28-pin DIP package 8192 x 8 MOS 250 ns 790mW
24AA00/ Serial EE- 8L DIP, SOIC, TSSOP 16 bytes x 8 bits Low-power 1000ns 10mW
24LC00/ PROM and 5L SOT-23 packages CMOS
24C00
 Semiconductor Memories 505

12.5.10 ROM Applications

ROMs have a lot of applications in digital
system. Any arbitrary truth table can be
realised through ROM. The implementation of
any input and output relationship using ROM
will be economical in size, cost and weight.
ROMs can be used in code conversion and
display alphanumeric characters. This can also
be used in a sequence of arithmetic operations
addition, multiplication and division.
ROMs can be used to store the tables of
mathematical functions, namely sine, cos, tan,
square, cube, square root, etc., logarithmic
tables, conversions from one number system
to others. For example, IC74184 ROM IC is
used to program a BCD to binary converter and
the 74185 ROM devices can be programmed
as a binary to BCD converter. Figure 12.36
and 12.37 show the logic symbol of BCD to Fig. 12.36 BCD to binary conversion
binary and binary to BCD conversions using
74184 and 74185 respectively. ROMs can also be used for
multi-digit BCD numbers to binary numbers.
ROM Multiplier Generally, multiplication can be per-
formed by sequence of shifting and addition operations. But
in ROM multiplier, a multiplication table as a truth table can
be stored in a ROM. When a set of data inputs are applied to
ROM, based on data inputs - the multiplication outputs will
be obtained from the look up table and will be available at
output terminals.
Function Generator A function generator produces
different signals like sine wave, cosine wave, saw tooth wave
and square wave etc. Figure 12.38 shows the application
Fig. 12.37 Six-bit binary to BCD
of ROM as a function generator. This circuit consists of a conversion
counter, ROM, and D/A converter. Initially, the lookup table
of any particular function is stored in ROM. When clock pulse is applied to counter, the counter output
fed to ROM. Actually, the counter output will be used to locate the content of ROM. Therefore digital
data will be available at the output terminals
of ROM and fed to D/A converter for analog
output. If clock pulse is applied periodically, a
sequence of ROM output fed to D/A converter.
Consequently the particular will be obtained
from D/A converter and display it in CRO. Fig. 12.38 Application of ROM in function generator
 506 Digital Electronics: Principles and Applications

Combinational Logic Implementation ROMs can be used any combinational logic func-
tion.Firmware: Programs and data that must be available on power up in microprocessors and micro-
controllers.
Bootstrap Memory A small program can be stored in ROM that directs a computer to load its
operating system from disk.
Data Converter Conversion from one data code to another is easily accomplished with a lookup
table in ROM.
State Machine Design The ROM can be used to design state machines.

12.6 RANDOM-ACCESS MEMORY (RAM)

Read only memories (ROMs) are only used to read stored data in the memory and ROMs can be
programmed only once. When data is recorded in ROMs, it cannot be erased. But in a random-access
memory (RAM), data can be written into memory whenever required. The data stored in a RAM can
also be read without destroying the contents of the memory. Actually, RAM is temporary (volatile)
storage of data and programs and data can be written into and read from memory at any location and in
any sequence. When data are written into a specified location of RAM, the previously stored data at that
location will be erased and the new data will be stored.
Usually, RAMs are two types, namely static RAM (SRAM) and dynamic RAM (DRAM). The static
RAM cell is a bipolar or MOS flip-flop. Once data has been stored in the flip-flop of a RAM cell, the
stored data will be available until power supply is off. Dynamic RAMs (DRAMs) are developed to
increase the density as small capacitors are used as this memory cell. In DRAM, capacitor is used
to store data as charge and this charge is dissipated by passage of time. Therefore, DRAMs must be
periodically refreshed.

12.6.1 Static RAM (SRAM)

A static RAM memory cell consists of flip-
flops. Flip-flops are set or reset and retain the
data until its charge or power is removed. Static
RAMs are manufactured by using bipolar
transistors, MOS and integrated injected logic
circuitry. Bipolar static RAM are fast and its
access time about 20ns. Static RAMs using
MOS are slower than bipolar static RAM and
its access time is about 200ns. But the MOS
RAMs have less power consumption and higher
packing density over bipolar static RAM.
The block diagram of a RAM memory unit
is shown in Fig. 12.39. It has N address input
lines, which are used to select one of the 2N
memory cells in the array. Each memory cell of Fig. 12.39 Block diagram of a RAM memory unit
 Semiconductor Memories 507

RAM can store one bit data. In this figure, address lines select one M bit word out of 2N word. When the
—– —
chip enable input (CE ) is low, the chip will be enabled for read and write operation. The R/W inputs are
—
used as control signal of read and write operation. The R/W input is held at logic ‘1’ for read operation
and at logic ‘0’ for write operation. The timing diagrams of read and write operations of static RAM are
explained below.
— —–
READ Cycle Figure 12.40 shows the static RAM read cycle with address inputs, R/W , CE and
data output signals. Initially address inputs are applied to locate the address from which data will be read
—
and R/W =1 for memory read operation.
—–
As chip enable CE =1, the chip is not
active for read operation. When chip
enable signal is low, the memory chip
is activated. After certain propagation
delay, data will be available at output
terminals. This propagation delay var-
ies in between 30ns to 50ns. tAA is the
RAM access time which is the delay
time between the application of new
address and the output of valid data.
tOE is the time between the activation of
chip enable signal and the appearance Fig. 12.40 Timing diagr am of memory read operation
of valid output data. of static RAM

WRITE Cycle Firstly, address

inputs are applied into the memory
to locate the memory location where
data will be written and the memory
chip enable signal is low in memory
write operation. The next step is that
—
the control signal R/W becomes low
for write operation and data input
to the data input lines. After certain
delay time, the input data will be
written in the memory. Figure 12.41
Fig. 12.41 Timing diagram of memory write operation
shows memory write operation. The of static RAM
different time parameters namely ad-
dress set up time (tAS), write time interval (tW), address hold time (tAH), data set up time (tSU) and data hold
time (tH) are depicted in this figure. Address set up time (tAS) is the time interval between the addresses
—
gets stabilized and R/W becomes low. The write time interval (tW) is the minimum time period for which
—
R/W should be held low to write data in the memory. This time is about 40ns. Address hold time (tAH) is
—
the minimum period of time for the address input to remain stable after R/W becomes high. This time is
around 5ns. Data set up time (tSU) is the time interval between the point when the data becomes stable up
—
to the point when R/W goes high. Data hold time (tH) is the time for which the data must remain stable
—
for a period after R/W becomes high. This time is approximately 5ns.
 508 Digital Electronics: Principles and Applications

12.6.2 Static RAM Cell

RAM like ROM is arranged in an array of cells represented by rows and columns. Each row represents
a word in memory and each column represents a bit in the words. The addressing structure of RAM is
that each row of memory cells or word is selected by decoding the address decoder. To expand the RAM
chips capacity, a chip select function is provided. The same address can also be applied to a number of
chips and the chip select or chip enable function is used to select which chip is to respond to the address.
—
For the read/write operation, a R/W control signal is provided in RAM.
Each static RAM memory cell is an SR latch as depicted in Fig. 12.42. The logic diagram of the
above memory cell consists of SR latch, AND gates and inverters. In this memory cell, data is applied
—
to both S and R. The select terminal enables the memory operation and R/W enables memory read or
write operation, but not both. Figure 12.42 (b) shows the block diagram of a memory cell (MC). Each
— —
memory cell can able to store one bit information. When R/W = 0, input data will be stored. If R/W =
1, the stored data in memory cell will be output at output terminal.

Fig. 12.42 (a) Logic diagram of RAM memory cell (b) block diagram of RAM memory cell

12.6.3 SRAM Structure

The structure of RAM is same as
ROM but the difference between the
structures of RAM and ROM is that
RAM has data inputs and a read/write
control signal. The organisation of 4×4
static RAM is depicted in Fig. 12.43. It
has two address inputs A1 A0 to select
any one of the four word lines and
it consists of sixteen-memory cells.
Memory cell (0,0) stores the first bit
information of word 0 and second bit of
word 0 is stored in memory cell (0,1).
When both address inputs A1 and A0 are
0 0, the first word 0 will be addressed.
For this a 2 line to 4-line decoder is
used. In this memory organisation, Fig. 12.43 Structure of a 4¥4 Static RAM
 Semiconductor Memories 509

4-bit word information is stored in each memory location. All first column cells are connected with
common data input line D0. Similarly second, third and fourth column cells are connected with data
input lines D1, D2 and D3 respectively. In the same way all first, second, third and fourth column cells
—
data output lines are connected with OR gates as depicted in Fig.12.43 for output. When R/W = 0, input
—
data D3–D0 will be stored in memory location addressed by A1 A0. If R/W = 1, the stored data in the
memory location addressed by A1 A0 will be available at output terminals Q3 – Q0. If each memory cell
individually accessible, the memory can store 16 bit information, but output will be one bit only. For
this operation, the organisation of 4 × 4 RAM must be modified using another 2 line to 4 line decoder to
select particular column matrix. Then row decoder and column decoder decode one row and one column
every time. Therefore, the cell at the intersection of row and column will be selected for read as well as
write operation.

Fig. 12.44 Structure of a 32¥32 static RAM

The basic structure of a 32x32 static RAM memory is illustrated in Fig. 12.44. This static RAM has
eight address lines. Five of the eight address lines (A4 – A0) are used for the row decoder to select one
of the 32 rows and three of the address lines (A7 – A5) are used for the output column decoder. During
memory write operation, the input buffers are enabled and four bits input data D3-D0 are routed through
 510 Digital Electronics: Principles and Applications

the input data selector by the address bits A7 A6 A5 and stored into the selected address by the address
bits A4-A0. In the memory read operation, the output buffers are enabled and four data bits from the
—–
selected address come out on the data outputs Q3 – Q0. The chip enable (CE ) must be low for read and
write operation. The advantage of SRAM is that it is easy to use but the disadvantage is the size of the
memory cell, which reduces the density and increases the cost.

12.6.4 Static Bipolar RAM Cell

Figure 12.45 shows the basic structure of a typical
bipolar RAM memory cell using multiple emitter
transistors. The bipolar RAM storage cell is a flip-flop.
Here, multiple emitter transistors T1 and T2 act as a
flip-flop for storing one bit data. In the multi-emitter
transistors, addressing cell row selection line RX and
column selection line RY are the two input terminals
and other input terminal is DATA line. In this memory
cell, one transistor will be ON at a time. When one
Fig. 12.45 Bipolar RAM cell
transistor is forced to ON by external signals
RX, RY and DATA line, data will be stored in
RAM cell.
Data can be written into the memory cell
and be read from the memory cell. For this,
some additional circuit will be incorporated
with Fig.12.45. The bipolar RAM cell with
features addressing the cell, writing data into it
and read data from it is depicted in Fig.12.46.
Here, row addressing of cell is represented by
RX and column addressing is also represented
by RY. The cell will be addressed for reading
and writing when RX =1 and RY=1.
Let RX and RY be at logic level ‘0’ and read/
write be at logic level ‘0’. When outputs of
gate G1 and G2 are at logic level ‘1’, transistors
T3 and T4 will be ON. Then collector voltages
of transistors T3 and T4 are at logic level ‘0’.
So that diodes D1 and D2 do not conduct.
Consider the state of the flip-flop is such
that T1 is in conduction and T2 is OFF. Then
emitter current will flow through ERX and ERY.
Since +0.5 V bias voltage is applied through Fig. 12.46 Bipolar RAM cell
 Semiconductor Memories 511

the resistance R3 to emitter ED, ED is more positive than ERX and ERY and ED does not conduct. Therefore,
transistors T5 and T6 are not conducting and they are OFF. So DATA signal is at logic level ‘1’ and retain
in this state independently of the state of the flip-flop.
When the cell is addressed by raising both RX and RY to logic level ‘1’, the currents through ERX and
ERY can be diverted to ED. Therefore part of ED current will flow into the base of transistor T5 and DATA
output signal will be the same logic level of T1. Hence, with the read/write at logic level ‘0’, both G1 and
G2 gates are disabled and read operation is performed by proper addressing the cell.
Now, let RX=1, RY=1 and read-write line at logic 1. When data input line is at logic level 1, gates G1
and G2 are enabled. The output of G1 is logic level ‘1’ and output of G2 is logic level ‘0’. Then T3 will be
remain ON but T4 will be turn OFF. The collector of T4 will increases, D2 starts conducting and increases
the emitter voltage ED of T2. Therefore, T2 does not conduct. Hence, the logic level at the collector of
transistor T2 will be the logic level of the data input. When the cell does not addressed, ED and ED– would
not carry any current and the flip-flop will not responded to the writing operation.

12.6.5 Static MOS RAMs

The structure of a static MOS memory cell using six-transistors is depicted in Fig. 12.47. This memory
cell consists of two cross-coupled MOS inverters. Transistors T1 and T2 are the driver and load of one
inverter. Similarly, transistors T3 and T4 are for the other inverter.

Fig. 12.47 Six transistor MOS memory cell

The memory cell is addressed by setting RX and CY to logic level ‘1’. When RX is at logic level ‘1’,
the memory cell is connected with the DATA line and the DATA line. During write operation of memory
cell, W = l and transistor T9 becomes ON. If CY is at logic level ‘1’, transistors T7 and T8 are ON. When
the DATA input is at logic level 1, the voltage at D will be logic level 1 and applied to the gate of T3.
 512 Digital Electronics: Principles and Applications

–
Therefore T3 is ON and the logic level at D will be 0. If the DATA input is at logic level 0, T3 will be OFF
–
and D will be at logic level 1. For read operation of memory cell, RX is at logic level 1. Then the DATA
–
output terminal is connected to D as T6, T8 and T10 are ON. Hence, the complement of data written into
the cell will be read and available at DATA output terminal.

12.6.6 Dynamic RAM

DRAMs use a small capacitor as the memory cell rather than a latch,
which drastically reduces the cell size. To store one bit data based on
charge storage technology, a single capacitor is sufficient. Figure 12.48
shows the DRAM cell, which consists of a transistor and a capacitor.
A charge is placed on the capacitor to represent a HIGH and the charge
is removed to represent a LOW. The advantage of this cell is that it’s
construction is very simple and very large array can be constructed in a
IC at very low cost with respect to SRAM. But the disadvantage of the
simple one-transistor cell is that the storage capacitor C will discharge
into the data line during read operation and can not hold its charge over Fig. 12.48 Dynamic MOS
a long period. Therefore, the storage capacitor must be large; otherwise RAM cell
the read operation may be destructive. The stored data will be lost
unless the capacitor is refreshed from time to time. The process of recharging the capacitors is called
refreshing. The refresh operation usually needs to occur every 2ms to 8 ms. In memory write operation,
the large capacitor requires longer time duration to charge properly. Consequently, some additional circuit
will be connected with this circuit to perform read, write, and refresh operations. The comparison between
SRAM and DRAM is given in Table 12.9.
DRAMs are developed continuously. Presently, there are four types DRAMs, namely FPM (First
page mode) DRAM, ECC (Error correcting code) DRAM, EDO (Extended data output) DRAM, and
SDRAM (Synchronous Dynamic RAM). FPM (First page mode) DRAM allows faster access due to
address multiplexing of memory. It is used in PCs before the development of EDO. It is available in
SIMM modules of 1, 2, 4, 8, 16 MB. Usually, access time is in the range of 60ns–70ns.
Table 12.9 Comparison between SRAM and DRAM
SRAM DRAM
1. Static RAM (SRAM) is a digital device and uses 1. Dynamic RAM (DRAM) stores charges on
a flip-flop to store 1 and 0. capacitors to represent logic 1 and logic 0
2. Larger cell, lower density, higher cost per bit 2. Smaller cell, higher density, lower cost per bit
3. No refresh required 3. Needs periodic refresh
4. Simple read and faster access 4. Complex read and longer access time
5. Manufactured by standard IC process and natu- 5. Manufactured by special IC process and dif-
ral integration with logic circuits ficult to integrate with logic circuits

EDO (Extended data output) DRAM is an improvement of FPM (First page mode) DRAM. Extended
Data Output DRAM latches the data output. While the current address is being read, the memory
controller can be setting up the next address. This memory device can able to access more rapidly as the
addressing and reading are done concurrently. The access time varies from 50ns – 60ns.
 Semiconductor Memories 513

ECC (Error correcting code) DRAM is a special type error correcting RAM. This memory device is
commonly used in computer server.
SDRAM (Synchronous Dynamic RAM) are synchronised with the clock speed. The speed of SDRAM
is expressed in MHz. This arranges memory in two banks and uses the system clock for data output
alternating the two banks. This allocates one bank to be setup while the other bank is being read. Double
Data Rate SDRAM (DDRSDRAM) is an improvement over SDRAM and operates from a synchronous
clock but transfers data on both edges of the clock. Synchronous-Link DRAM (SLDRAM) is also
another improvement over DDRSDRAM that runs at potentially higher speeds.
Rambus DRAM (RDRAM) is a proprietary chip. This memory device has more control integrated
into the memory to increase speed and flexibility. RDRAM can be able to transfer approximately
1.6 billion bytes per second. RDRAM consists of RAM controller, the bus for connecting RAM and
digital system or processor.

12.6.7 Dynamic RAM Structure

The size of the DRAM memory cell is smaller than SRAM cell. With the reduction of size of the
memory cell, the density of DRAM chips has been increased in many folds. Once the number of bits in
a package increases, the number of address lines will be increased. Therefore, the package size increases
which has reverse effect on reducing the chip size. Hence, to reduce chip size, address multiplexing
technique is used by the chip manufactures. In this technique, chip addresses are divided into row as
well as column format and row select strobe and column select strobe are incorporated in DRAM ICs.
But due to use of address multiplexing, the access time of the memory increases.
When the size of DRAM ICs increases, the refresh cycle also is increased. Assume a 1M × 1 DRAM
IC which has 1,048,576 cells. If all memory cells were refreshed one at a time, it takes about 4 ms. But
the time required for read operation approximately 4ns. Therefore, most of the time will be passed for
refreshing operation as refreshing operation not fast enough so that usually refresh operations on high-
density memory chips is performed on a sector of cells all at once and the address multiplexing is used
for the sectors in which an entire row is refreshed at one time. Thus, the number of refresh operations will
be reduced to 1024 times. This type of refresh operation is known as burst mode refresh operation.
Generally, dynamic RAMs use address-multiplexing technique to reduce the number of address lines
and thus the number of input/output pins on the package. The block diagram of a typical 16Kx1dynamic
RAM is shown in Fig.12.49. This has 16384 memory cells, which can be able to store 16384 bits data.
The memory cells are organised in a square array with 128 rows and 128 columns.
This dynamic RAM use address multiplexing. There are fourteen address lines A13 – A0 but seven
address lines are applied at a time. Initially, the seven bit row address lines A6 – A0 are applied to row
address buffer. The row address strobe (RAS ) is also applied to row address buffer and then the column
address lines A13 –A7 and column address strobe (CAS ) are applied to column address buffer. When RAS
is at logic level 0, the row address decoder select a row out of 128 rows. Subsequently, CAS is at logic
0, the seven-bit column decoder select any particular column of the 128 columns for read or writes
operation. The timing diagram of read and writes operations are depicted in Fig.12.50 and Fig.12.51
respectively.
514 Digital Electronics: Principles and Applications

Fig. 12.49 Block diagram of 16K ×1 DRAM

Fig. 12.50 Timing diagram of memory read operation

Fig. 12.51 Timing diagram of memory write operation

 Semiconductor Memories 515

All memory cells of dynamic RAM must be refreshed periodically after every 2 to 4 ms. The bock
diagram of a 16K×1 dynamic RAM organisation with refresh facility is illustrated in Fig. 12.52. In
refresh operation of dynamic memory, each row is refreshed sequentially. During refresh mode operation,
read and write operation cannot be performed. The output of refresh counter fed into the MUX. When
the refresh control signal S is low, address will be applied to row decoder.

Fig. 12.52 Block diagram of a typical 16K ×1 DRAM with refresh control
The refresh counter output is 0 to 127 sequentially. Therefore, each row will be selected sequentially
and all cells of each row will be refreshed at a time. During refresh operation, the CAS is at logic level
1 and no data is placed on the external data line. After completions of refresh operation, the refresh
mode must be terminated. Then again memory read or writes operation can be performed. Most DRAM
manufacturers supply one-chip DRAM controllers, which encapsulates the refresh and other functions.

12.6.8 Four-Transistor Dynamic MOS RAM

The structure of a four transistor dynamic RAM memory cell is depicted in Fig. 12.53. This is consists
of four transistors T1, T3, T5 and T6. As memory cell use four transistors in place of six transistors, power
 516 Digital Electronics: Principles and Applications

consumption as well as size will be reduced. Transistors T5, T6, T7, and T8 are common in four transistor
and six transistor dynamic RAM memory cells. The stray capacitances C1 and C2, are present in circuit
to store the data bit logic level ‘1’ or logic level ‘0’. These capacitances are accessible. When the RX and
CY are at logic level ‘1’, transistors T5 and T6 as well as T7 and T8 are ON.

Fig. 12.53 Four transistor dynamic MOS RAM

This memory cell can store either logic level 1 or logic level 0. When the voltage across C1 is larger
than the threshold voltage of T1, and T1 will be ON. Consequently, C2 becomes zero voltage and T3 is OFF.
If the voltage across C1 is at logic level 0 and the voltage across C2 is logic level 1, the conducting state
of T1 and T3 are reversed. This RAM memory cell can be operate in read and write mode. In read mode
operation, R=1 and in write mode operation W=1.
When read and write operation do not performed for longer time duration, the capacitor charge of the
cell may be lost due to leakage of capacitor charge. Therefore, it is required to refresh the memory cell
periodically. This refreshing operation is performed by allowing brief access from the supply voltage
VDD to the memory cell.
When RX=1, and Refresh=1, T5 and T6 as well as T12 are ON. Consider T1 is ON and T3 is OFF. The
voltage across C1 is greater than threshold voltage of transistor and the voltage across C2=0. In refresh
mode, operation VDD is applied through TI2 and T6 to C1. As T3 is OFF, all current from VDD will passes
through C1. So that C1 will be recharged if any charge is lost due to leakage. As T1 is ON, C2 will not be
charged as fast as C1.
 Semiconductor Memories 517

In the same way, VDD is applied to C2 when T1 is OFF and T3 is ON. In refresh mode, T6 and T12 act as
a load of transistor T3. Similarly, T5 and T11 act as load of T1. The memory cell behaves as conventional
flip-flop which consists of two cross-coupled inverters during the refresh time interval. In this way, the
initial state of memory cell is reinforced.

12.6.9 Three-Transistor Dynamic MOS RAM

The dynamic memory cell using three transistors is illustrated in Fig. 12.54. This circuit consists of
transistors T1, T2, T3. Transistor T1 is used for write operation, but transistors T2 and T3 are used to read
the logic state of capacitor C. As capacitor is connected with the gate of T2, it is isolated from the output
data line. The charge of capacitor C is always leakage through transistor T1. Therefore a refresh circuit
is required to refresh capacitor periodically. Here refreshing circuit consists of transmission gate T9,
inverter amplifier and transistors T10 and T11.
To access the memory cell, RX and CY are at logic 1. During write mode operation, the refresh circuit
must be disconnected by P = 0. To write into the cell, W = 1. The input data line is connected with
capacitor C as T7, T4, and Tl are ON. Then capacitor C is charged to logic 1, i.e., the state of the data
input. For read operation of the cell, R=1, W = 0 and T5, T3, T6 and T8 are ON. The DATA output line is
connected with the DATA output. The complement of the charge capacitor, C is read and available at
output DATA line. Transistor T6 acts as a load for T2 during the read operation.

Fig. 12.54 Three transistor dynamic MOS RAM

 518 Digital Electronics: Principles and Applications

In refresh mode operation, CY = 0, RX = 1, P =1, and R =1. Then data-input and the data-output
terminals are disconnected from all the memory cells.
After that the complement of the logic level of capacitor C has been transferred through T9, and has
been stored on capacitor CR. The input terminal P is known as precharge input terminal, which connects
with CR and the output DATA line. If P = 1, CR precharges to the complement of voltage level of C.
After completion of precharge, R=0 and W = 1. Then output of inverter, T10, T11 refreshes the charge of
capacitor C.
Initially the refresh-amplifier output is disconnected from T1 and capacitor C. Therefore, T11 does not
initially load capacitor C until after CR is precharged to the proper level. If this precaution does not taken
care, capacitor C may be discharged erroneously.

12.6.10 RAM Expansions

Generally, RAMs are available in one-bit, and four-bit word configurations. Eight bit, sixteen bit and
more than sixteen bit RAMs are also used in some applications. Therefore, it is required to increase
word size and word capacity of RAMs. The expansion of RAMs in word size and word capacity is
illustrated in Example 12.5 and Example 12.6.

Example 12.5 Design a 1024 × 8 bit RAM using 1024 × 4 bit RAM

� Solution
To design a 1024 × 8 bit RAM using 1024 × 4 bit RAM IC, two 1024 × 4 bit RAM ICs are required. Here,
memory size is fixed byte but word size is increased from 4 bit to 8 bit. Figure 12.55 shows the connection
diagram of two 1K × 4 RAM ICs to develop 1024 × 8 bit RAM. The address input lines of the ICs are
—
connected together. The chip enable (CE), RAS, CAS and R/W inputs of the ICs are also connected together.
Then number of output lines will be equal to the word size of each IC × the number of ICs used = 4 × 2 = 8.

Fig. 12.55 Two 1024 ¥ 4 RAMs expanded to design a 1024 ¥ 8RAMs

 Semiconductor Memories 519

Example 12.6 Design a 2048 × 4 bit RAM using 1024 × 4 bit RAM.

� Solution
In a 1024 × 4 memory
has 1024 word capacity
and it can store 1024 × 4
= 4096 bits. To expand
the memory size from
1024 × 4 bits to 2048 × 4
bits, two 1024 × 4 RAM
ICs are required. Figure
12.56 shows the con-
nection of two 1024 × 4
RAM to develop a
2048 × 4 RAM. Ten-ad-
dress lines A0 to A9 are
directly connected with
memory IC terminals.
The chip select line is
connected with most
Fig. 12.56 Two 1024¥4 RAMs expanded to design a 2048¥4 RAMs
significant bit address
line A10 and inverted MSB is connected with chip select line of the next IC. So that memory addresses from
0 to 1023 are located first memory IC1 and memory addresses from 1024 to 2047 are also located in memory
IC2. One memory will be selected at a time and data out from one memory only. Therefore, corresponding
output terminals are connected together for output.

12.6.11 RAM ICs

Most commonly used RAM ICs are given in Table 12.10 with their category, organisation, package,
access time, technology and power dissipation, etc.
Table 12.10 Commonly used RAM ICs
IC Category Package Organisation Technology Access Power
No. time dissipation
7489 Static RAM 16 pin DIP Package 16 × 4 Bipolar 33ns 500mW
2114 Static RAM 18-PIN DIP Package 2K × 4 MOS 200ns 300mW
74189 Static RAM 16 pin 16 × 4 Bipolar 50ns 550mW
74289 Static RAM DIP Package 16 × 4 Bipolar 35ns 250mW
6116 Dynamic RAM 24-pin DIP, Thin Dip, 2K × 4 CMOS 15ns 4µW
SOIC and SOJ package
4166 Dynamic RAM 16 pin DIP Package 16384 × 1 NMOS 200ns 460mW
2104A Dynamic RAM 16 pin DIP Package 4096 × 1 MOS 150ns 420mW
2164 16 pin DIP Package 64K × 1 MOS 450ns 330mW
 520 Digital Electronics: Principles and Applications

12.7 SEQUENTIAL MEMORY

In sequential memory, data can be written and read sequentially. Shift register is an example of sequential
memory. In random access memory, any location data can be read and data may be written at any location
within very few access times. But in this memory to locate any intermediate memory location, a lot of
time is required as data are accessed in sequence. Therefore, access time is not equal for all locations.
Figure 12.57 shows a shift-register sequential memory. This memory has N shift registers and each
shift register consists of M bits. So each register holds a M bit word. After application of clock pulse the
stored words will be output sequentially at the output terminals Q0, Q1…. QN-2 and QN-1. During the read
operation of this sequential memory, the output of register may be returned back to the leftmost register
position to work as a recirculation shift register. Therefore, after the M clock pulses the entire sequence
of words has appeared at the memory output terminals and the same sequence will be stored in shift
register so that register content may be recirculated endlessly.
When write enable is set at logic level 1, the recirculation path of shift register will be broken. Data
inputs are applied to data lines D0 D1 … DN-1, which are synchronised with clock and write signals in
register. Then register content will be erased and replaced by new data with each clock pulse. The first
word written into shift registers will be appeared at the output terminals during memory read operation.
Consequently, this memory is known as first in first out (FIFO) sequential memory. In FIFO sequential
memory, the word may be transferred back to the left most register position. Therefore, it is known as
circulating shift register.
Usually shift registers are used as sequential memory. The static shift register can be implemented
with flip-flops and data can be loaded into shift register or read from it in sequence. The read and write
process of shift registers are done in synchronisation with clock pulses. Data will be stored in the

Fig. 12.57 A typical N × M sequential memory

 Semiconductor Memories 521

register as long as power supply is applied to memory devices. Generally, bipolar and MOS devices are
used to implement static shift registers. These registers require large power and large area for fabrication
of higher capacity. Therefore, dynamic shift registers are fabricated using MOS. In this section, the
operation of dynamic MOS registers are explained.

12.7.1 Dynamic MOS Register

The advantage of MOS technology in large-scale integration (LSI) ICs is that MOS devices require too
much less space in a silicon chip than comparable bipolar devices. Therefore, MOS devices are widely
used in the large-capacity memories of
shift registers. Shift registers are formed
by cascade connection of simple flip-
flops or master slave flip-flops. Each
flip-flop stores one bit data either 1 or 0
and always responses with clock pulse.
When clock pulse is applied, output will
be available at output terminals based
on input data. MOS shift register is
also cascade connection of master slave
flip-flops and the operation of MOS
shift register is explained with circuit
diagram in this section.
Figure 12.58 shows the MOS inverter Fig. 12.58 One bit dynamic MOS cell
circuit. This circuit behaves as a dynamic
NMOS cell. The supply voltage VDD is
positive, and the NMOS transistor will
be conducting when its gate voltage is
positive and will be OFF while the gate
voltage is at ground potential. Figure
12.59 shows the clock waveform of
transistor T1, f. The gate voltage of T1
is at logic level 1 at t=t1. Then T1 will be Fig. 12.59 Clock waveform of one bit dynamic MOS cell
turned ON and the capacitor C will be
charged to the logic level of DATA input voltage. The transistor T1 is known as transmission gate to the
capacitor C to the DATA input. During the time interval (t2 – t1), input data can be transmitted to C.
At time t2, gate voltage f becomes 0 and transistor T1 is turned off and the input data will be stored
in C. In the time interval (t3 – t2), no gate voltage f is applied and the stored data on capacitance C will
be transferred to output terminal. T2 and T3 act as an inverter response to stored charge of C. When C is
charge to at logic level 1, output voltage is at logic level 0. If capacitor is at logic level 0, output voltage
will be at logic level 1. This circuit behaves as flip-flop as this dynamic NMOS cell store one bit data
either 1 or 0. Generally, capacitance value is about 0.5pF. Since the charge stored in the capacitor C will
leak-off continuously, the limitation of this circuit is that memory is short-lived. Therefore, capacitors
must be able to hold the charge about 1ms for transferring data to output terminal.
 522 Digital Electronics: Principles and Applications

12.7.2 Two Phase Ratio Dynamic MOS Register

Figure 12.60 shows the NMOS dynamic shift register using cascade connection of two inverter stages.
This circuit acts as a master slave-flip flop. Clock waveform for the master and slave are complementary
waveforms. It has two transmission gates T1 and T4, which are not simultaneously ON.

Fig. 12.60 One bit dynamic MOS cell

The clock waveforms of T1 and T4 are depicted in Fig.12.61. If f1=1 and f2=0, the input data can
be transferred to C1 and the voltage level of C2 is transferred to storage capacitor of the next stage
register, C'1. After t2, T1 will be OFF, but the input data will be stored in C1. When f1=0 and f2=0 in
the time interval (t3−t2), both transistors T1 and T4 are OFF, but T2 becomes ON. The complement of
the bit logic level C1 is at T2. At t=t3, f2 becomes 1, and the complement of the bit logic level C1 at T2
can be transferred to C2 as transistor T4 is ON. In this way the circuit as shown in Fig. 12.60 behaves
as a master-slave flip-flop. Transistors T1, T2, T3 and
capacitor C1 act as a master flip-flop in the first stage
inverter. In the second stage, inverter transistors T4,
T5, T6 and capacitor C2 behaves as a slave flip-flop.
The limitation of this circuit is that two-phase clock
waveforms are required.
The charge stored in the capacitor C1 will leak-
off continuously. Therefore, shift registers must be
operate dynamically and the time period of f1 and f2
must be less than 1ms. As a result, this MOS register
is called as dynamic shift register.
In the above circuit, when the stored voltage of C1 is
at logic 1, T2 and T3 will be conducting for the complete
clock cycle, (t5 – t1) and continuously dissipating power, Fig. 12.61 Two phase Clock waveform of
and drawing current from supply voltage. If C1 is at one bit dynamic MOS cell
 Semiconductor Memories 523

logic 0, T2 is OFF during the complete cycle. Similarly, T5 and T6 will be conducting for an interval equal
to clock cycle and dissipate power when the capacitor C2 is at logic 1. If C2 is at logic 0, T5 will be OFF
during the complete cycle. Therefore, power dissipation will be more. To reduce the power dissipation
significantly, the circuit must be modified. The modified circuits are Fig. 12.62 and Fig. 12.63.
Figure 12.62 shows the clocked load register stage. In this circuit configuration, gate of transistors T1
and T3 are connected with the clock f1 and the clock f2 is applied to the gate of transistors T4 and T6. In
place of two capacitors in stage-1 as depicted in Fig. 12.60, four capacitors C1, C2, C3 and C4 are used in
stage-1. When the clock f1 =1, the input data will be transferred to C1 and the complement of capacitor
voltage C1 is transferred to C2. While f2 =1, the stored voltage level in C2 is transferred to C3 and its
complement to C4. In this way, the input data will be transferred from C1 to C4, which will be used as
input data of next stage shift register.

Fig. 12.62 MOS dynamic shift register with load-transistor

The C2 is used to transfer the input data through first stage inverter and transmission gate T4 to C3.
Consider input data is at logic 0 and C2 does not present. If f1 is at logic level 1, the complement of
the input data will be available at output of the inverter. When f1 becomes 0, both T2 and T3 are OFF
and inverter output is isolated from input. When C3 is present in the circuit, C3 can be able to store the
complement of input data. After that f2=1, the logic voltage of C2 will be transferred to C3 as T4 is ON.
For this, C2 must be able to charge C3 and maintain the voltage at logic 1 for sufficient time period.
Therefore, C2 must be very large compared to C3. While input data is at logic 1, C2 may be neglected.
Figure 12.63 shows the MOS dynamic shift register with load-transistor clocking. This is also a
modified circuit of Fig. 12.60. Two-phase clock waveforms of this MOS dynamic shift register are
illustrated in Fig. 12.64. Here, the gate of transistor T3 is connected with clock f2 and clock f1 is applied
to the gate of T6. When data bit stored in C1 or C2 is at logic 0, the corresponding inverter will not conduct.
If data bit 1 is stored in C1 or C2, the corresponding inverter will conduct. When the clock waveforms f1
and f2 are at logic 1 for specified time duration, capacitors C1 and C2 must be charged adequately. The
charging time must be much less than cycle time. As the conduction period of transistors T2, T3, T5 and
T6 are significantly reduced; this clocked load circuit configuration reduces the power dissipation. In this
case, external clock becomes loaded. Due to this, clock driver must be incorporated in circuit.
 524 Digital Electronics: Principles and Applications

Fig. 12.63 MOS dynamic shift register with load-transistor clocking

The above shift registers are simply cascade connections of inverter stages. In this circuit, one transistor
is used as a driver and the other transistor is used as load. Therefore, the ratio between the channel resistance
of the driver and the channel resistance of the load must be very large or (W/L)D>>(W/L)L. Therefore the
load device require large area on chip than the area required by the driver. As the resistance of load
channel is high, the speed of operation of the inverter is limited. The disadvantages of ratio type shift
register are limited operating speed and large area required on chip. To improve the performance of shift
registers, two-phase ratio less dynamic shift register has been developed.

Fig. 12.64 Two phase Clock waveform of MOS dynamic shift register

12.7.3 Two Phase Ratioless Dynamic MOS Register

Figure 12.65 shows a ratio less shift register stage. Here both supply voltage and ground are connected
to the clock pulses. At f = 0, clock is at logic 0 or 0V. When f =1, supply voltage as well as clock are
 Semiconductor Memories 525

at logic 1 or VDD. In the similar way of Fig. 12.60, input data will be transferred from one register stage
to other register stage.
At time t = t1, f1=VDD and input voltage is at logic 1, capacitor C1 will be charged to VDD. T3 will be ON
and capacitor C2 will be charged to VDD. During the charging of C2, T2 will be OFF as the gate voltage
of T2 does not exceed the source voltage by the threshold voltage VT . So transistor T2 and T3 do not act
as an inverter.

Fig. 12.65 Two phase ratio less shift register

When f1 becomes 0V, T3 will be OFF. T2 becomes ON, as the charge stored on C1 is geater than
the threshold voltage VT . Then C2 discharges through T2, and the capacitor C2 voltage will be at logic
0. Hence after the clock pulse interval (t2 – t1), C2 has returned to 0V, that is the complement of the
input bit. Consequently the overall effect is that the circuit also behaves as an inverter like ratio shift
register. Similarly, when f2 changes from logic level 0 to logic level 1 and returns back to logic level
0, the complement of stored charge capacitor C3 will be transferred to C4. In this circuit, configuration
capacitor is burden on the clock input signal, and the capacitor charging current must be supplied from
clock.

12.7.4 Four Phase Ratioless Register Stage

In the two-phase ratio less shift register as depicted in Fig. 12.65, the capacitance C2 charges capacitor
C3. Therefore, the capacitor C2 must be greater than C3. Due to large capacitance C2, the speed
of operation is degraded and it requires relatively large area on ICs. These disadvantages can be
overcome by using four-phase ratio less register stage as depicted in Fig. 12.66. The clock waveforms
are illustrated in Fig. 12.67. When f1=1, transistor T3 is ON and C1 charges to logic level 1. After f1
return back to logic level 0, capacitance C1 retain its charge at logic level 1. Consider that input is at
logic level 1. Afterward f2=1, T1 and T2 are turn on and C1 discharges to logic level 0 through T1 and
T2. As a result C1 store the complement of the input data. When input is at logic level 0, T1 is in cut-off
and the stored charge of C1 will not be change. So that capacitor C1 retain at logic level 1, which is the
complement of the input data.
 526 Digital Electronics: Principles and Applications

If f3=1, transistor T4 is ON and

C2 charges to logic level 1. When f3
return back to logic 0, capacitance
C2 retain its charge at logic level
1. When f4 is at logic level 1, T5
becomes ON and T6 will be ON if
input data is in logic 0 and C1 is at
logic level 1. Then capacitor C2 will
be discharged through T5 and T6 and
capacitor C2 logic level changes
from logic level 1 to logic level 0.
Similarly, when input data is in logic
level 1 and C1 is at logic level 0, the
capacitor C2 has no discharging path
as T5 is ON and T6 is OFF. Then the
capacitor C2 retain in logic level 1
and output data will be logic level 1. Fig. 12.66 Four-phase ratio less register stage
In this way input will be transferred
to output for using as input of next stage
register.
In this circuit, one capacitor does not supply
charging current to other capacitor. But the
disadvantage of this circuit is that a four-phase
clock waveform is required and f1 must supply
the charging current of C1 and f3 also must
supply the charging current of C2.

12.7.5 CMOS Shift Register

Stage
A CMOS shift register is depicted in Fig. 12.68.
This circuit consists of two transmission gates
G1 and G2, two inverters I1 and I2 and two
capacitors C1 and C2. This CMOS shift register
operates like an MOS dynamic shift register
as shown in Fig. 12.60. The advantages of this
circuit is that it is ratio less and does not draw
a steady current from supply and consequently
power loss is less. But CMOS gate and inverters
require more space on CMOS IC compared to
MOS gate and inverters on MOS IC.
Fig. 12.67 Clock waveforms of four-phase
ratio less register stage
 Semiconductor Memories 527

Fig. 12.68 CMOS shift register stage

12.8 CHARGE-COUPLED DEVICE (CCD)

In late 1960s, Willard Boyle and George Smith have developed the charge-coupled devices(CCD) at
Bell laboratory to store digital information. This is actually an array of MOS dynamic shift register
sequential memory. These devices are low cost, very simple construction and versatile. The fabrication
procedure of CCD on a semiconductor substrate involves very few operations than MOSFET and
bipolar technology. The CCD memory will dissipate low power and can be manufactured with three-
fold density compared to MOS memories. In 1974, Fairchild electronics developed the first imaging
CCD with a format 100 × 100 pixels and the first CCD TV cameras were manufactured for commercial
use in 1975. In late seventies, the first CCD flatbed scanner was introduced using the first integrated
chip, which consists of 500 linear arrays and in 1982, the first solid-state CCD camera was introduced
for video-laparoscopy.
Figure 12.69 shows the structure of charged coupled devices. These devices are based on MOS
technology and consist of n–type or p-type silicon substrate. A thin silicon dioxide (SiO2) layer has been
used to cover the substrate. An array of closely spread metal electrodes is placed on the oxide layer.
The metallic electrode and the substrate act as a capacitor i.e. stored charge. Here, the semiconductor
material is n-type substrate. Assume that the bottom of the substrate is connected with ground or 0V
and all metal electrodes potential are also at 0V. Then majority current carriers are evenly distributed
in the n-type substrate due to absent negative voltage at the electrodes. Figure 12.70 shows the evenly
distribution of majority carriers, when there is no negative potential at metal electrodes.

Fig. 12.69 Typical structure of a charged coupled device

 528 Digital Electronics: Principles and Applications

Then all electrodes are maintained at

the fixed negative voltage – 4V. When
applied voltage (–V) is more than the
threshold voltage VT of the substrate, a
depletion layer will be developed. Due
to the negative bias voltage – 4V of the
electrodes, a depletion layer will be de-
veloped just below the silicon dioxide
layer. A depletion layer is created almost Fig.12.70 Transfer of charge between gates of CCD
evenly in the presence of negative volt- when majority carriers are evenly distributed
age at electrodes. Figure 12.71 shows due to absence of negative potential
the depletion layer, which is developed
by the fixed negative – 4V at all elec-
trodes. Actually, the depletion region is
the region from which electrons have
been removed. In this case, minority
holes present with in the substrate and
majority electrons have been pushed
from the surface. As the negative charg-
Fig. 12.71 Transfer of charge between gates of
es are remov on region with in substrate CCD when –4V is applied
when electrodes voltages are V1 = –4V, to all electrodes
V2 = – 8V, and V3= – 12V. The voltage
at electrode-3 is more negative than the
voltages of other electrodes. Therefore,
higher voltage at electrode-3 develops
deeper potential well under electrode-
3 and the minority carriers shift to the
right under this electrode.

Fig. 12.72 Transfer of charge between gates of CCD

when electrodes voltages are
V1= − 4V, V2= − 8V, and V3= − 4V

Fig. 12.73 Transfer of charge between gates of

CCD when electrodes voltages are
V1= –4V, V2= –8V, and V3=–12V .
 Semiconductor Memories 529

12.8.1 Operation of CCD

The structure of a 3-phase charge coupled device (CCD) shift register is shown in Fig. 12.73. The dif-
ference between Fig. 12.69 and Fig. 12.73 is that clock pulses replace voltage sources. Here, the three
clock waveforms f1, f2, and f3 are used to drive the CCD shift register. The composite clock waveforms
of f1, f2, and f3 and the lateral charge transfer in the CCD are depicted in Fig. 12.74 and Fig. 12.75 re-
spectively. This figure consists of an array of metal electrodes. All f1 electrodes are connected together.
Similarly all corresponding f2 and f3 electrodes are connected together. This 3-phase CCD works as a
dynamic flip-flop with features of a master-slave flip-flop. So that data can be moved in one direction
only.

Fig. 12.74 Connection of a three phase clocking to the electrodes of a CCD

Fig. 12.75 The potential distribution of electrodes at t0, t1, t2, and t3

During the time interval t0, only f1 is at a negative voltage, so that depletion regions are formed
only under f1 gates because the clock f1 becomes negative. The charge in depletion regions under f1
is injected from an external source or from the preceding gate f3 gate. In the time interval t1, the clock
 530 Digital Electronics: Principles and Applications

Fig. 12.76 Three phase clocking waveforms of the CDD

f2 also becomes negative while the clock f1 is held negative and the clock f3 is positive. Therefore,
depletion regions are extended from the f1 gate to f2 gate. As a result, the charge is able to spread
throughout the extended region. During the interval t2, the clock f3 becomes negative and the clock
f2 is still negative. But f1 goes positive, thereby the depletion regions under the f1 gate are eliminated
and the new depletion regions under the f3 gate are developed. Consequently, depletion regions are
extended from the f2 gate to f3 gate. Similarly, during the interval t3, the depletion regions under f2 gates
are eliminated and the charge originally under the f2 gate is pushed to the right under the f3 gates. In
this way, the cycle has been completed; charge will be transferred from one region to next region three
electrodes away. After that, the above logic cycle from time interval t0 to t3 will be repeated sequentially.
In this way, three electrodes are used for storage as well as transfer of data in CCD.
An example of CCD memory is Intel 2416 memory IC. This memory is organised as 16384 × 1
bit serial memory and it has 64 recirculating shift registers each of 256 bits. Any one register can be
accessed by 6 bit address inputs and a 1: 64 decoder. In this IC, a four-phase clock waveform is used and
data can be shifted in synchronisation with clock pulses. In this memory, the data cannot be stored in one
position for indefinite time due to gradual disappearance of depletion regions. Therefore, a minimum
time between shifts of data must be present. In Intel 2416, the minimum time is about 9μs. Another
example of CCD memory IC is Intel 2464. The Intel 2464 CCD IC is a 64 K bits of memory on a single
die and it is organised with 256 independent circulating registers of 256 bits each. It is noted that, due
to their low cost, high density, and high reliability, CCDs are very useful for numerous bulk storage
applications.

12.9 MAGNETIC DISKS MEMORY

ROMs, EPROMs, EPROMs and RAMs, etc. are used to store data when the memory size is small.
These devices are known as internal storage memory devices. If large amount of data is required to be
stored in digital systems, then external memory devices are required. Most commonly used external
devices are magnetic disks. Magnetic disk memory is a established conventional type of electronic
data storage. The different magnetic diskettes, such as Hard Disks, Floppy Disks, IDE (Integrated
Drive Electronics) Disks, EIDE (Extended IDE) Disks, SCSI (Small computer system interface) Disks
and RAID (Redundant Array of Inexpensive Disks), Optical disks: CD-ROM, CD-Recordables, CD-
 Semiconductor Memories 531

Rewriteables, and DVD are commercially available for used in computer. Magnetic disks are the current
workhorse for permanent storage. In this section, the Hard Disks, Floppy Disks and Optical disks are
explained briefly.
Magnetic disks are the most popular medium for storing digital data and these disks are direct access
type secondary data storage. In a magnetic disk, ferromagnetic metals or metal oxides are used for
recording and saving data. The ferromagnetism is a permanent alignment of magnetic moments, which
creates a magnetic field emanating from the ferromagnetic particle area. A magnetic disk is made of
metallic film, called platters and is coated with ferromagnetic materials.
The disk or platter surface is sub-divided into concentric circles called tracks. Digital data are
organised into tracks. Each track on the disk has the same total storage capacity. Inner tracks are shorter
and recording density of data is higher on tracks nearer the center and smaller than the tracks near the
outer edge. Then each track is subdivided into different sectors and each sector provides a fixed storage
capacity in number of bytes. Generally, disks are available in the following size 8 inches, 5 ¼ inches,
and 3 ½ inches. Figure 12.77 shows a typical magnetic disk with 64 sectors and 1024 tracks.
A magnetic hard disk may be consists of one or more aluminum platters with a magnetisable coating.
Figure 12.78 shows a typical hard disk with four platters. Here four platters are packed vertically one
over the other called disk pack. In the disk pack, digital data is stored on the both the surfaces of each
disk platter except the upper surface of the top platter and lower surface of the bottom platter as these
surfaces have some tendency to collect dust and other forms of contaminations. Consequently, the disk
pack with 4 individual disks has eight storage surfaces and each surface has a read/write head. The
capacity of disk pack in total number of bytes stored is = number of bytes per sector × number of sectors
per track × number of tracks per surface x number of surfaces. The capacity can also be expressed as
bytes sectors tracks
Capacity = No. of Surfacce
sector track surface

Fig. 12.77 A typical magnetic disk

 532 Digital Electronics: Principles and Applications

Fig. 12.78 A hard disk drive with four platters

The disk is mounted on a vertical

shaft, which rotates at a high and constant
speed. An access mechanism moves the
read/ write head to the desired location
of data and provide direct access of data.
Both surfaces of the disk are available
for storage and each surface has a read/
write head. The disk head containing an
induction coil floats just over the surface,
and resting on a cushion of air. The cir- Fig. 12.79(a) Longitudinal write operation of head
cuit diagrams of read and write
operation of head are depicted in
Fig. 12.79(a) and Fig. 12.79(b)
respectively. The block diagram
representation of the read/write
operation of head is also depicted
in Fig.12.79(c). When a current
passes through the head, it mag-
netises the surface just beneath
the head and data will be stored
in the surface. If the head passes
over a magnetised area of platter
surface, a current is induced in Fig. 12.79(b) Perpendicular read and writes operation of head
the head and the previously stored bits will be read with the help of MR sensor. In this way, when the
 Semiconductor Memories 533

platter rotates under the head, a stream

of bits can be written and later read
back also.
The ferromagnetic material is de-
posited onto one or more aluminum
or glass platters with the magnetic
domains separated at evenly spaced
intervals. The magnetic domains on
the platters are induced to be spin up
or down using a small powerful fer-
romagnetic read/write head that looks
like a record player arm. One region
on the magnetic platters is reserved
as an index to the location of all data
files stored on the disks. If this index is Fig. 12.79(c) Read and write operation of head
damaged, then a lot of problems will be
come up. Recording is done by two ways namely longitudinal recording and perpendicular recording.
In perpendicular recording, the coherent magnetic field coming from a single domain can be induced to
point a spin up or spin down direction. The spin up stands for logic 0 and the spin down stands for logic
1. During read operation, recording data in digital format will be back again.
Each hard disk drive consists of a motor to rotate the disk pack at speed about 2400 to 3600 revolutions
per minute about its axis. Therefore, all platters of a disk pack move simultaneously in the same direction
and at same speed. This drive has a set of read/write heads mounted on arms. There is enough space
in between the disks to allow access arms and to locate the data; read/write heads will be move to any
track/sector of any surface. A disk controller is associated with each drive. Actually, this is a chip that
controls the drive. The operation of controllers is that accepting commands from the software, such as
read, write and format, controlling the arm motion, detecting and correcting errors.

12.9.1 Floppy Disks

With the advent of the personal computer, the diskette or floppy disk has been developed to distribute
softwares. The floppy disk is very popular to use as auxiliary storage. These disks are very thin, circular
and permanently enclosed in a plastic jacket. Figure.12.80 shows a typical floppy diskette. These disks
are made of very thin plastic material (mylar) and are coated with a layer of magnetic metal oxides.
Generally, disks are coated on both sides. As the used material is not a hard plate but in a flexible tape,
it is called as floppy disk. The difference between hard disks and floppy disks is that the heads float just
above the surface on a cushion of rapidly moving air in hard disks, but in floppy disks, heads actually
touch the diskettes. As a result, both the media and the heads quickly wear out. To reduce wear and tear,
the personal computers retract the heads and stop the rotation when a drive is not reading or writing.
Floppy disks are normally available in 5.25 inch, 3.5 inch and 8.5 inch. The 5.25 inch and 8.5 inch disks
become obsolete. The 3.5-inch diskettes come in a rigid jacket for protection. Presently, 3.5 inches
floppy disks are used in the standard personal computer systems.
 534 Digital Electronics: Principles and Applications

Fig. 12.80 A typical floppy diskette

12.9.2 Optical Disks

Optical disk is the latest development in secondary storage. These disks have much higher recording
densities than conventional magnetic disks. They consist of a rotating disk, which is collated with highly
reflective material. Data is physically stored on the surface of disk as a series of depressions called pits
and unburned areas between the pits called lands. Actually, the data are written by focusing high power
laser beam on the surface of the spinning disk in the form of small pits and land. A pit/land transition
represents 1, and its absence is 0. The storage capacity of optical disks is remarkable in comparison to
magnetic disks and the storage cost per bit is very low. The comparison of magnetic disk drive, floppy
disk drive and optical disk drive are given in Table 12.11. There are different types of optical disks
namely CD-ROM, CD –R, CD RW. CD-ROM stands for Compact Disk – Read Only Memory, CD–R
stands for Compact Disk -Recorder and CD-RW stands for Compact Disk –Rewriteable.

Table 12.11 Comparison of magnetic disk drive, floppy disk drive and optical disk drive

Parameters Magnetic disk drive Floppy disk drive Optical disk drive
Storage media Magnetic disk, Disk pack, Magnetic diskette 5.25 inch, Optical disk, CD-ROM
fixed disk 3.5 inch and 8.5 inch
Access time 10–100 milisecond 100-600 milisecond 30–100 milisecond
Data transfer 200,000 to million bytes per 10,000 to 30,000 bytes per 150,000 to 500,000 bytes per
second second second
Capacity 10 million to 15 billion bytes 360,000 to several million 700 million to few billion bytes
per drive bytes per drive per drive
Advantages and Large capacity, Fast direct ac- Small, slower and smaller Large capacity, high quality
disadvantages cess but relatively expensive capacity but less expensive storage of data Fast direct ac-
cess but relatively expensive
 Semiconductor Memories 535

CD-ROM CD-ROM is one type of Optical

disks and it stands for Compact Disk – Read
Only Memory. This CD is prepared using a
molding process from a burned master disk.
This disk contains 16,000 tracks per inch.
The disk is written once only during manu-
facturing in the form of small pits and lands.
Once data is written, it cannot be erased. To
read data from disk, a low power laser beam
is focused on the surface of the disk. Con-
sequently, pitted area reflects less light and
smooth surface reflects more light. Then a de-
tector senses the reflected light. The limitation
of the disks is that they are read only memory Fig. 12.81 CD-ROM
device. Generally, the disk should be able to
hold 700 MB data. CDs are 1 mm thick disc of
polycarbonate plastic coated with a thin layer of
reflecting aluminum and protected by a lacquer
film as depicted in Fig.12.81. The polycarbonate
region is pressed with grooves and dents with
the digital data. The data is stored as regions of
high and low laser light reflection. The smooth
areas are highly reflective, while the pits or
grooves scatter light and drop the reflection. A
spiral-raised groove keeps the laser on track as
shown in Fig.12.82.

CD–R CD–R stands for Compact Disk

–Recorder. A CD-Recorder (CD-R) is a com-
mon peripheral which is similar in size to a Fig. 12.82 Spiral groove of CD-ROM
CD-ROM Drive. These devices are different
from magnetic disks as the user can write the disk once only. As the data is stored in the disk, it cannot
be erased. CD-Rs are very useful for backup purposes and specified applications where files/data never
be altered. Data from video scanners, keyboards, optical character recognition and other equipments are
recorded on CD-Rs.

CD-RW CD-RW stands for Compact Disk –Rewriteable. This CD uses both laser and magnetic head
to read and write the data. The stored data can be erased and rewritable. CD-RW is recorded using lasers
to heat magnetised areas and uses a different alloy for the recording layer. Therefore, CD-RW can not
be replaced CD-R and CD-RW blanks are much more expensive than the CR-R blanks. This CD is used
as backing up hard disks, stored data from video scanners, keyboards, and other equipments.
 536 Digital Electronics: Principles and Applications

12.10 CONTENT-ADDRESSABLE MEMORY (CAM)

The Content-Addressable Memory (CAM) compares input search data with a table of stored data, and
returns the address of the matching data. Usually, CAM is a memory that implements the lookup-table
function in a single clock cycle using dedicated comparison circuitry and making them faster than other
hardware and software-based search systems. CAMs can be used in a wide variety of applications
requiring high search speeds, such as parametric curve extraction, Hough transformation, Huffman
coding/decoding, Lempel–Ziv compression, and image coding, etc. The primary commercial application
of CAMs is to classify and forward Internet protocol (IP) packets in network routers. In networks like
the Internet, a message such as an e-mail or a Web page is transferred by initially breaking up the
message into small data packets of a few hundred bytes and then sending each data packet individually
through the network. These packets are routed from the source, through the intermediate nodes of the
network which are called routers and reassembled at the destination to reproduce the original message.
The function of a router is to compare the destination address of a packet to all possible routes, in order
to choose the appropriate one. A CAM is a good choice for implementing this lookup operation due to
its fast search capability. Hence, CAMs are very popular in network routers for packet forwarding and
packet classiûcation, but they are also beneûcial in a variety of other applications which require high-
speed table lookup.
Though the speed of a CAM comes at the cost of increased silicon area and power consumption,
designers should strive to reduce two design parameters namely silicon area and power consumption.
The optimum design of CAM is to reduce power consumption associated with the large amount of
parallel active circuitry, without sacrificing speed or memory density. As CAM applications grow,
demanding larger CAM sizes, the power problem is further exacerbated. Reducing power consumption,
without sacrificing speed or area, is the main thread of recent research in large-capacity CAMs. In this
section, the operation of CAM and also describe the CAM application of packet forwarding.

12.10.1 Structure of CAM

Figure 12.83 shows a simple block diagram of a CAM. The conceptual view of a content-addressable
memory containing words is depicted in Fig. 12.83. In this example, the search word matches location
(location of stored word 1) as indicated
by the shaded box. The matchlines
provide the row match results. The
encoder outputs are an encoded version
of the match location.
The input to the system is the search
word that is send to the searchlines to
the table of stored data. The number of
bits in a CAM word is usually large,
with existing implementations ranging
from 36 to 144 bits. Generally, a typical
CAM uses a table size ranging between
a few hundred entries to 32K entries,
corresponding to an address space Fig. 12.83 Basic structure of CAM
 Semiconductor Memories 537

ranging from 7 bits to 15 bits. Each stored word has a matchline that indicates whether the search word
and stored word are identical or are different. The matchlines are fed to an encoder that generates a
binary match location corresponding to the matchline that is in the match state. An encoder is used in
CAM systems, if only a single match is expected. In some CAM applications where more than one
word may match, then a priority encoder is used instead of a simple encoder. A priority encoder selects
the highest priority matching location to map to the match result, with words in lower address locations
receiving higher priority. In addition, there is a hit signal that flags the case in which there is no matching
location in the CAM. The overall function of a CAM is to find a search word and return the matching
memory location. The capacity of different CAM chips varies from 8K to 8M. Presently, the largest
commercially available single-chip CAMs are 18 Mbit implementations. It is a fact that a typical CAM
cell consists of two SRAM cells. As per thumb rule, usually the largest available CAM chip is about half
the size of the largest available SRAM chip.
12.10.2 CAM Architecture
A small model of CAM architecture is shown in Fig. 12.84. This schematic diagram of CAM shows
individual core cells, differential searchlines, and matchline sense amplifiers (MLSAs). It is depicted
in Fig. 12.84 that CAM consists of 4 words, with each word containing 3 bits arranged horizontally. In
this figure, CAM stands for CAM cells, SL stands for searchline, and ML stands for match line. Always,
there is a match line corresponding to each word (ML0, ML1, ML2, and ML3) feeding into matchline sense
amplifiers (MLSAs). There is a differential searchline pair corresponding to each bit of the search word
—– —–
(SL0, S L0…… SL2, SL2 ). The CAM search operation starts with loading the search-data word into the
search-data registers followed by precharging all matchlines high and putting them all temporarily in
the match state. After that, the searchline drivers send the search word onto the differential searchlines,
and each CAM core cell compares its stored bit against the bit on its corresponding searchlines. The

Fig. 12.84 Schematic block diagram of a model CAM with 4 words having 3 bits each
 538 Digital Electronics: Principles and Applications

matchlines on which all bits match remain in the precharged-high state. Then MLSA detects whether
its matchline has a matching condition. Afterwards, the encoder maps the matchline of the matching
location to its encoded address.

12.10.3 CAM Core Cells

A CAM cell serves two basic functions such as bit storage and bit comparison. Figure 12.85(a) shows
a 10-T NOR-type CAM cell and Fig. 12.85(b) shows the 9-T NAND-type CAM cell. The cells are
shown in Fig. 12.85 is an SRAM-based data-storage cells. In this SRAM cell bit storage device, cross-
–
coupled inverters implement the bit-storage nodes D and D. The nMOS access transistors and bit-lines
which are used to read and write. The SRAM storage bit are omitted to simplify the schematic diagram.
The bit comparison, which is logically equivalent to an XOR of the stored bit and the search bit can be
implemented using the NOR and the NAND cells.

NOR Cell The CAM implementation using NOR cell consists of the complementary stored bit, (D
– —–
and D), and the complementary search data on the complementary searchline, SL and S L , four transis-
tors M1 to M4 to maintain minimum-size and high cell density. The transistors implement the pulldown
path of a dynamic XNOR logic gate with D and SL inputs. Each pair of transistors either M1 and M3 or M2
and M4 forms a pulldown path from the matchline, ML. The mismatch of SL and D activates one of the
pulldown paths, connecting ML to ground. The correct match of SL and D disables both pulldown paths
after disconnecting ML from ground. The NOR nature of this cell can be justified when multiple cells are
connected in parallel to form a CAM word by shorting the ML of each cell to the ML of adjacent cells.
The pulldown paths are connected in parallel resembling the pulldown path of a CMOS NOR logic gate.
The match condition on a given ML is that each individual cell in the word has a match.

Fig. 12.85 (a) 10-T NOR-type CAM cells and (b) 9-T NAND-type CAM cells

NAND Cell The NAND cell based CAM implements the comparison between the complementary
–
stored bit, (D and D), and the complementary search data on the complementary search line,(SL and
—–
S L ) using transistors M1, MD and MD– to maintain minimum-size and high cell density. For example of
the bit-comparison operation of a NAND cell, assume SL=1 and D=1. When the transistor MD is ON,
 Semiconductor Memories 539

it passes the logic “1” on the SL to node B. The node B is the bit-match node which is logic “1” if there
is a match in cell. If the node B is logic “1”, transistor M1 becomes turn ON. The transistor M1 is also
turned ON in the other match condition when SL = 0 and D = 0. In this case, the transistor MD– passes
logic high to raise node B. When SL ≠ D, the result is a miss condition and the node B is logic “0” and
the transistor M1 is OFF. The node B is a pass-transistor implementation of SLD function. The NAND
nature of this cell can be justified when multiple cells are connected serially. The MLn and MLn+1 nodes
are connected to form a CAM word.

Ternary Cells Usually the NOR and NAND cells are binary CAM cells. These cells can store either
a logic “0” or a logic “1”. But ternary cells can store a logic “0”, a logic “1” and “X ” value. The “X ”
value is a don’t care, which represents both “0” and “1”, and allow a wildcard operation. The wildcard
operation means that an “X ” value stored in a cell causes a match regardless of the input bit. Table 12.12
shows the ternary encoding for NOR cell and ternary encoding for NAND cell is given in Table 12.13.
– –
The two bits are represented by D and D. It may be noted that the D and D are not necessarily comple-
mentary, but the complementary notations are maintained for consistency with the binary CAM cell. Two
bits can represent four possible states, but ternary storage requires only three states as the state where D
–
and D are both zero, is not used in this cell. To store a ternary value in a NOR cell, a second SRAM cell
–
is used as shown in Fig. 12.86. D is connected to the left pulldown path and D is connected to the right
pulldown path. Hence, the pulldown paths are independently controlled. A don’t care state, “X ” can be
–
stored when both D and D are equal to logic “1”, and both pulldown paths are disabled. A logic “1” is
– –
stored by setting D = 1 and D = 0 and logic “0” is stored by setting D = 0 and D = 1.

Fig. 12.86 (a) NOR-type Ternary core cells (b)NAND type Ternary core cells
 540 Digital Electronics: Principles and Applications

Table 12.12 Ternary Encoding For NOR Cell Table 12.13 Ternary Encoding For NAND Cell
Stored Stored– Search bit Value Stored Search Bit
—
Value D D D M SL SL
0 0 1 0 1 0 0 0 0 1
1 1 0 1 0 1 1 0 1 0
x 1 1 0 0 x 0 1 1 1
x 1 1 1 1
12.10.4 Matchline Structures
The matchline is one of the key structures in CAMs. Usually NOR Matchline and NAND Matchline struc-
ture are used. In this section, only NOR Matchline is discussed. Figure.12.87 shows the schematic diagram
of NOR Matchline structure, how NOR cells are connected in parallel to form a NOR matchline, ML.
Any NOR search cycle operates in three phases such as searchline precharge, matchline precharge, and
matchline evaluation. Firstly, the searchlines are precharged low to disconnect the matchlines from ground
by disabling the pulldown paths in each CAM cell. When the pulldown paths are disconnected, transistor
precharges the matchlines high. Then the searchlines are driven to the search word values, triggering the
matchline evaluation phase. When there is a match, the ML voltage stays high as there is no discharge path
to ground. While there is a miss match, there is at least one path to ground that discharges the matchline.
The matchline sense amplifier (MLSA) senses the voltage on ML and creates a corresponding full-rail
output match result. The main characteristic of the NOR matchline is its high speed of operation.

Fig. 12.87 Structure of a NOR matchline with match result

12.11 ADVANCE MEMORY

In digital computers, memory devices are organised according to their speeds. The fastest memory
devices, such as RAMs and ROMs are used in CPU of computers. These memories are known as primary
memory. Integrated circuit (IC) memories are usually employed ROMs and RAMs. The commonly
used ROMs are EPROM, EAPROM, and EEPROM. There are two types of RAM, namely static and
dynamic RAMs. Magnetic memory devices, such as floppy disks, CDROM and hard disks are used
for bulk data storage. The operation of ROM and RAM ICs and magnetic memory devices are already
explained in previous sections. The magnetic bubble and charge coupled device (CCD) memories now
a days are also used for bulk storage.
 Semiconductor Memories 541

Magnetic bubble devices memories were introduced in the late 1970s, but these are less popular than
RAM, and ROM ICs. Magnetic bubble technology lies in between magnetic disk and semiconductor
memory technology. These memories have no moving part and are non-volatile. Generally, magnetic
bubbles are developed on certain magnetic materials such as garnet crystal by applying magnetic field
which is perpendicular to the surface of the sheet of magnetic materials. The magnetic fields strengthen
some regions in the material and weaken others regions. Data are represented in bubble–storage by the
presence or absence of bubbles, which represents logic “1” or logic “0” .
The CCD memory devices stored data on capacitors as charge like DRAM. The data storage of CCD
memory is arranged in shift register configuration. The charge will be shifted from one CCD cell to the
other CCD cell. Just like DRAMs, data will be lost with switch off power supply. The detailed operation
of CCD memory devices is explained in Section 12.8.
The non-volatile RAM (NVRAM) is new version of RAM. NVRAM consists of a high speed static
RAM and each RAM cell has corresponding cell of an EEPROM with access-time of 200–300ns. Each
—–
NVRAM IC has a special pin, labelled as non-volatile enable, NE . The stored data in the RAM section,
—– —–
can be transferred to EEPROM section, when both NE and WE write are logic level “0”. The data in the
RAM section can be transferred to ROM section in about 10ms. To read data from EEPROM section,
—– —–
both NE and WE signal must be logic level “0”. Usually, this operation is performed, when power is
switched off.
The other memory devices are content addressable memories (CAMs), programmable logic arrays
(PLAs) and programmable array logic (PAL). The content addressable memory is a special purpose
random access memory device which can be accessed by searching for data content. The content-
addressable memory (CAM) compares input search data with a table of stored data, and returns the
address of the matching data. Usually, CAM is a memory that implements the lookup-table function.
The detailed operation of CAM is discussed in Section 12.10.
Canonical SOP and Canonical POS forms are used to implement any combinational logic functions.
To implement these circuits, logic gates are used. In programmable design of digital systems, an array
of logic cells is used. Actually, cells can be able to provide a universal logic function. In this design,
signal routing is done through switch box approach and RAM holds the routing patterns, which is
reprogrammable. The advantages of programmable design are less time required to design, easily
reworked on design system, design costs are low, and production time decreases. This technique has
limited flexibility, and this is suitable for only low volume production.
The other approach of combinatorial logic circuits and sequential logic circuits design is application
of Programmable Logic Devices (PLDs). A programmable Logic Device (PLD) is an IC that contains
a large number of logic functions, which are interconnected on the chip. The interconnection process is
user programmable and it is similar to PROM. Actually, the basic concepts of PLD have been developed
by combining combinatorial logic and ROM technologies. Generally, flexible architecture and fixed
architecture are used for programmable logic devices. Three basic forms of PLD’s are Programmable
ROM (PROM), Programmable Array Logic (PAL), and Programmable Logic Arrays (PLA).
Programmable read only memory (PROM) devices are developed using fixed architecture. PROM is
a fixed architecture programmable logic device and can be used as memory devices. The PROM is
not too much flexible with respect to PAL and PLA. In PAL, the OR array is fixed and AND array is
programmable. The PAL is more flexible than the PROM and is probably the most used of the fixed
architecture devices. The PLA is the most flexible of the programmable logic devices, as both AND
array and OR array are programmable. Therefore, in the logic circuits design using PLA, the additional
 542 Digital Electronics: Principles and Applications

flexibility is not needed. PLD ICs are most commonly used in application specific digital circuit design
due to flexibilities, low development cost, and low power consumption. The detail architecture and
operation of PLDs such as PROMs, PLAs, and PALs are explained in Chapter 13.
SUMMARY
In this chapter, the basic concept of semiconductor memories has been explained. The memory organisation and
operation of various semiconductor memories, namely ROM, PROM, EPROM, EEPROM, SRAMs, DRAMs are
discussed. Expansion of ROM and RAM are also incorporated in this section. Sequential memory, Dynamic shift
register and Charge-Coupled Device (CCD) have been introduced. Magnetic storage devices such as floppy disks, hard
disks and optical disks are explained briefly in this chapter. The basic concept of content addressable memory (CAM)
is incorporated.

MULTIPLE CHOICE QUESTIONS

1. The term ‘memory’ applies to
(a) Logic (b) Control (c) Data storage (d) Output device
2. In digital systems, the memories are used to store
(a) Data (b) Information (c) Instruction (d) None of the above
3. A semiconductor read only memory basically is
(a) A combinational logic circuit (c) A sequential circuit with flip-flops and gates
(b) A set of flip-flop memory elements (d) None of the above
4. A memory used for storing variable quantities is
(a) ROM (b) PROM (c) EPROM (d) RAM
5. The semiconductor memories are widely used in place of ASICs due to
(a) Small size (c) Interface able with digital systems
(b) Low cost (d) All of the above
6. A RAM is
(a) A random-access-memory (c) Static or dynamic memory
(b) A volatile memory (d) All of these
7. A ROM is
(a) A random-access-memory (c) Static or dynamic memory
(b) A volatile memory (d) All of these
8. A SRAM is fabricated using
(a) Bipolar technology (c) Both bipolar and MOS technology
(b) MOS technology (d) None of these
9. A M × N bits memory can be able to store
(a) M words of N bits each (c) M + N bits
(b) N words of M bits each (d) M – N bits
10. A memory has 10 -bit address bus. The number of memory locations are
(a) 1000 (b) 1024 (c) 100 (d) 10
11. The address bus width of a memory of size 1024 × 8 bits
(a) 10 bits (b) 11 bits (c) 12 bits (d) 13 bits
12. In a ROM, data can be stored
(a) By the user only once (c) At the time of fabrication
 Semiconductor Memories 543

(b) By the user a number of times (d) None of these

13. An example of volatile memory is
(a) ROM (b) RAM (c) LSI (d) None of these
14. The data bus width of a memory size 2048 × 8 bits is
(a) 8 bits (b) 10 bits (c) 12 bits (c) 16 bits
15. What is the number of bits required for addressing 4KB memory?
(a) 16 (b) 12 (c) 8 (d) None of these
16. The number of 16 × 4 size memory ICs are required to design a 64 × 8 memory
(a) 8 (b) 6 (c) 4 (d) 2
17. A shift register is a
(a) Sequential accessed memory (c) RAM
(b) ROM (d) None of these
18. A charge-coupled device is
(a) A bipolar device (b) A MOS device (c) A magnetic device (d) None of these
19. A ROM is
(a) A random-access-memory (c) Programmable memory
(b) A non volatile memory (d) All of these
20. A mask programmed ROM is
(a) Programmed at the time of fabrication (c) Erasable electrically
(b) Programmed by the user (d) None of these
21. A PROM is
(a) Mask programmed (c) Programmed once only
(b) Erasable by ultraviolet (d) None of these
22. A CCD is
(a) RAM (c) Sequential accessed memory
(b) ROM (d) None of these
23. MOS technology can be used for fabrication of
(a) SRAMs (b) EPROMs (c) ROM (d) All of these
24. A DRAM can be fabricated using
(a) MOS technology (b) TTL (c) I2L (d) None of these
25. An EPROM is
(a) Erasable and programmable (c) Non-erasable
(b) Volatile (d) None of these
26. The programming of EPROM can be done
(a) At the time of fabrication (c) By the user many times
(b) By the user once only (d) None of these
27. An EPROM is fabricated using
(a) MOS technology (b) TTL (c) ECL (d) None of these
28. Fusible link is associated with
(a) PROM (b) ROM (c) EPROM (d) All of these
29. A floppy disk is a
(a) Thin plastic disc coated with magnetic oxide
 544 Digital Electronics: Principles and Applications

(b) Thin magnetic oxide disc coated with plastic

(c) Aluminum disk coated with magnetic oxide
(d) None of these
30. Floating gate is fabricated for
(a) PROM (b) ROM (c) EPROM (d) All of these
31. The write cycle time of a memory is 200ns. The maximum rate at which data can be stored is
(a) 500 words/s (b) 5000 words/s (c) 50000words/s (d) 500000 words/s
32. The access time of a sequentially accessed memory is
(a) Same as that of a RAM (c) Higher than that of a RAM
(b) Less than that of a RAM (d) Same as that of a ROM
33. A memory, which is not random-access type, is
(a) CCD (b) RAM (c) ROM (d) None of these
34. Index hole is used in
(a) Floppy disk (b) Hard disk (c) Magnetic tape (d) None of these
35. A disk pack has 4 plates with 6 read/write heads and 400 tacks on each surface. Each track on a disk
surface is divided into 100 sectors of 512 bytes each. The total storage capacity of the disk pack is
(a) 122880000 bytes (b) 12288000 bytes (c) 1228800 bytes (d) 122880 bytes

REVIEW QUESTIONS
12.1 Explain the basic concept of one bit memory cell and mention applications of memory cell.
12.2 What the types of memory? Write the difference between ROM and RAM. What is nonvolatile
memory?
12.3 Discuss memory organisation with an example. What is the bit storage capacity of a ROM with a
512 × 4 organisation? How many address bits are required for a 2048 bit memory?
12.4 What is the difference between PROM and ROM? Draw the internal structure of typical ROM 32
× 32 memory array and explain its operation.
12.5 Explain memory expansion of ROM with examples. How many 16K × 1 ROMs are required to
achieve a memory with a word capacity of 16K and a word length of eight bits?
12.6 Draw the diode, bipolar and MOS ROM architecture for Table 11.12.
Table 11.12
Inputs Outputs
A B C F0 F1 F2
0 0 0 1 1 0
0 0 1 1 1 1
0 1 0 0 0 0
0 1 1 1 1 1
1 0 0 0 1 0
1 0 1 0 1 1
1 1 0 1 0 1
1 1 1 1 1 0
12.7 Implement the BCD to Excess-3 code conversion using ROM.
12.8 What are the types of ROMs? Write a block diagram of a ROM and explain it’s operation. What are
the advantages and limitations of PROM?
12.9 Implement the following logic functions F1, F2 and F3 as given below using PROM
 Semiconductor Memories 545

F1=m(0, 1,4,5,7,11)
F2=m(2, 7, 8, 9,11)
F3=m(4,5, 10,12,14,15)
12.10 IC 2716 is 2K × 8 EPROM IC. Find the number of 2716 and other ICs to implement
(a) 4K byte (b) 2K × 16 ROM (c) 4K × 16ROM
12.11 Write the difference between the following
(a) PROM and ROM
(b) EPROM and EEPROM
(c) ROM and RAM
12.12 Explain difference between static and dynamic RAM. What is the reason for the refresh operation
in dynamic RAMs.?
12.13 Draw the structure of a 4 × 4 Static RAM and explain it’s operation. How many 16K × 1 RAMs
are required to achieve a memory with a word capacity of 64K and a word length of eight bits?
12.14 Write short notes on the following
(a) Bipolar RAM cell (c) SRAM
(b) Six transistor MOS memory cell (d) DRAM
12.15 Draw the block diagram of 16K × 1-DRAM structure. Explain the operation of DRAM using timing
diagram. List the comparison between SRAM and DRAM.
12.16 Design the following RAM structure
(a) 1024 × 8 bit RAM using 1024 × 4 bit RAM
(b) 4096 × 4 bit RAM using 1024 × 4 bit RAM
12.17 Write short notes on the following
(a) Three transistor dynamic MOS RAM (b) Four transistor dynamic MOS RAM
12.18 What is sequential memory? What are the types of dynamic MOS shift register? Explain any one
dynamic MOS shift register.
12.19 Explain the operation of CCDs with diagrams.
12.20 Write short notes on the following
(a) Floppy disk (c) Optical disk
(b) Hard disk (d) Content addressable memory
12.21 A disk pack has 4 plates with 6 read/write heads and 400 tacks on each surface. Each track on a disk
surface is divided into 100 sectors of 512 bytes each. Determine
(a) number of cylinders in the disk pack
(b) number of tracks in the disk pack
(c) the total storage capacity of the disk pack
12.22 Design a PROM structure for the following functions
F1= m(0,1,8,11,12,15), F2= m(2,3,6,7,8,9,12,13)
F3= m(1,3,7,8,9,11,12,15) and F4= m(0,1,4,8,11,12,15)
12.23 Design a PROM structure for implementation of following logic functions
– – –
F1= ABC + ACD, F2= ACD + BC + A D, and F3 = ABC + A CD,
12.24 Explain briefly the applications of ROM.
12.25 A disk pack has 8 plates with 14 read/write heads and 400 tacks on each surface. Each track on a
disk surface is divided into 100 sectors of 512 bytes each. Determine the total storage capacity of
the disk pack.
 CHAPTER

13
PROGRAMMABLE
LOGIC DEVICES
13.1 INTRODUCTION
Integrated circuits (ICs) are built on a semiconductor substrate, usually one of single-crystal silicon. The
circuit, often called a chip, is packaged in a hermetically sealed plastic case, with leads extending from it
for input, output, and power-supply connections. Integrated circuit functions are virtually limitless and
used in various applications. Improvements in IC manufacturing technology have led to increasingly
dense integrated circuits. Therefore, smaller and denser chips will be able to provide speed benefits as
these chips have high-speed devices. Generally, the integrated circuits are manufactured by the following
fabricating steps: film formation, impurity doping, photolithography, etching, and packaging.
Digital integrated circuits contain one to millions of logic gates, flip-flops, multiplexers, demultiplexers,
adders, comparators etc. in a few square millimeters. The small size of these circuits allows high
speed, low power dissipation, and reduced manufacturing cost compared with board-level integration.
Sometimes the typical logic design task consists of interconnecting standard fixed function IC’s to
form more complex circuits and systems. This process requires many IC’s, which increases the cost
of the design due to large space and power requirements. Therefore, the need for application specific
integrated circuits (ASICs) is generated. ASICs can be used to meet the specific requirements and can
be manufactured by IC manufacturer as per user specifications. The advantages of ASICs are less space
requirements, less power requirements, and better security but initial development cost is very high.
Integrated circuits can be designed by using standard product ICs and application specific ICs (ASIC).
Figure 13.1(a) and (b) show the different options available to chip designer for final implementation of
combinatorial and sequential logic circuits.
Application specific ICs (ASICs) are semi-custom gate array, semi custom standard cell, and full
custom type.

Full Custom Design In full cus-

tom design, each individual transistor of
circuits can be accessed. This provides
total flexibility in the design of the chip.
In this design, the power consumption,
timing and chip area can be optimised. Fig.13.1(a) Classification of standard product ICs
But the times for fully optimised design-
 Programmable Logic Devices 547

ing a complete system will be long.

If there are any mistakes in design,
then it will be very expensive to
correct. The advantages of full
custom design are flexibility, and
design optimisation. The disadvan-
tages are long design time, expen-
sive to rework, and require high
volume product. In custom design,
the following options are available:
design with basic gates; design with Fig.13.1(b) Classification of application specific ICs
transmission gates; design with
complex gates and combination of basic gates, transmission gates and complex gates.
Standard Cell Design The standard cell design technique uses a set of predefined blocks such
as adders, multiplexers, demultiplexers, etc. This technique has less flexibility than full custom. When
parameterised standard cells are used in design, some flexibility in terms of shape and size of the cell
are available. In standard cell design, we can use predefined standard cells. Cells are connected with
power supply and ground. In this design, it is presently required to add signal routing. The advantages
of standard cell design are reduced design time, less errors, and moderately optimize design. This design
technique has following disadvantages: very limited flexibility, expensive to rework, and suitable for
high volume product.
Programmable Design In programmable design of digital systems, an array of logic cells is
used. Actually, cells are able to provide a universal logic function. In this design, signal routing is done
through switch box approach and RAM holds the routing patterns, which is reprogrammable. The ad-
vantages of programmable design are less time required to design, easily reworked on design system,
design costs are low, and production time decreases. This technique has limited flexibility, and this is
suitable for only low volume production.
The alternative approach of complex combinatorial and sequential logic circuits design is application
of Programmable Logic Devices (PLDs). A programmable Logic Device (PLD) is an IC that contains
a large number of logic functions, which are interconnected on the chip. The interconnection process is
user programmable and it is similar to PROM. Actually, the basic concepts of PLD have been developed
by combining combinatorial logic and ROM technologies. Generally, flexible architecture and fixed
architecture are used for programmable logic devices. Three basic forms of PLD’s are Programmable
ROM (PROM), Programmable Array Logic (PAL), and Programmable Logic Arrays (PLA).
Programmable Read Only Memory (PROM) devices are developed using fixed architecture. PROM
is a fixed architecture programmable logic device and can be used as memory devices. The PROM is not
too much flexible with respect to PAL and PLA. The PAL is more flexible than the PROM and is probably
the most used of the fixed architecture devices. The PLA is the most flexible of the programmable logic
devices, but in the logic circuit designs the additional flexibility is not needed.
PLDs are most commonly used in ASIC design due to flexibilities, low development cost, and low
power consumption. In this chapter architecture of PLDs such as PROMs, PLAs, PALs, PLDs, SPLDs,
CPLDs and FPGA are incorporated.
 548 Digital Electronics: Principles and Applications

13.2 PROGRAMMABLE READ ONLY MEMORY (PROM) DEVICES

A ROM or Read Only Memory is an array of interconnected semiconductor devices to store an array of
binary data. Data stored in the ROM can be read for reuse in digital devices, but the stored data cannot
be changed under normal operating conditions. A typical ROM consists of a decoder and a memory
array. The block diagram of ROM is shown in Fig.13.2. The ROM has n input lines and there are 2n
possible combinations of n binary digits. Therefore, ROM has 2n address lines from 0 to 2n-1, which is
represented, by a n lines to 2n line decoder. When a set of 1’s and 0’s is applied to the decoder inputs of
ROM, any one-address line of the 2n address lines of memory will be selected. Then data stored in this
memory address can be transferred to the
memory output lines. Here ROM has ‘m’
output lines. The ROM can effectively
store the truth table of an n-input, and
m-output combinational logic functions.
The size of memory is the number of
address lines × output lines. When
ROM has ‘n’ number of inputs and ‘m’
number outputs, the size of memory is 2n
× m bits. If number of address lines n=12
and output lines m = 8, the total storage
capacity is 212 × 8 = 4096 bytes = 4KB. Fig. 13.2 Block diagram of Read Only Memory
Usually, there are three types of ROM, namely mask-programmable ROM (ROM), programmable
ROM (PROM), and erasable programmable ROM (EPROM).
Mask-programmable ROM (ROM) ROMs are nonvolatile memories as initially data is stored
in memory through programming and stored data will not be changed when power supply is removed.
During the fabrication, the device (ROM) is programmed though selectively includes or omits switch-
ing elements at the row-column intersections according to design specification. Programming during
manufacturing is very expensive as very costly equipments are required. Therefore this is economic for
high volume production. Generally, mask programmable ROMs are manufactured by Bipolar as well as
CMOS technology.
Programmable ROM (PROM) The data can be stored into the ROM array by the user with the
help of PROM programmer. Initially, all switching elements at row-column intersections are built-in in
the ROM array during the fabrication of ROM using Bipolar fusible link. During programming, the user
selectively removed the fusible links of switching elements as per requirements. As the users are able to
program the device according to specific needs, PROM can be used for low-volume applications.
Erasable Programmable ROM (EPROM) In EPROM, a special charge storage mechanism
is used to enable or disable the switching elements of memory. So all switching elements can be pro-
grammed electrically and can be erased by exposure to Ultra-Violet light. Usually, CMOS technology
is used for manufacturing EPROM.
Electrically Erasable PROM (EEPROM) EEPROM is similar to EPROM but this type of
ROM can be completely erased electrically. There is a limit on the number of times of data erased and
programmed. Therefore, EEPROMs are not used in place of RAM.
 Programmable Logic Devices 549

13.2.1 Structure of PROM

The Bipolar and MOS technology are commonly used in fabrication of PROMs. Bipolar PROMs use the
fusible links and it has small access times. In MOS PROMs, floating MOSFETs are used as basic charge
storage elements and these ROMs have high packing density. Figure 13.3 shows the basic structure of
a MOS PROM matrix. It consists of two sets of bus bars, such as horizontal address lines and vertical
output lines. The vertical output lines are connected with address decoder though a floating MOSFETs.
When floating gate exists in the intersection of output lines and address line, the digital data ‘0’ can be
stored. If floating gate does not exist in the intersection of output lines and address line, the digital data
‘1’ will be stored in that location. When decoder inputs are A0 = 0 A1 = 0, data stored in address line 00
will be output at F0 to F7. Hence, the output data is 11111111.

Fig. 13.3 Structure of 4 × 8 PROM

The PROM is used as memory device and it can
be represented as an array of registers. This means
that the registers in the memory can be programmed.
After programming, usually they cannot be changed.
To program the PROM, each register must be loaded
with a desired binary number. Generally this is done
using a PROM programmer. Figure 13.4 shows the
array of registers of 4 × 8 PROM. To load in address
location 00, determine the output of logic expressions
Fig. 13.4 Array of registers for F0, F1, F2, F3 F4, F5, F6 and F7. From Table 13.1,
we can find that F0= F1= F2= F3= F4= F5 = F6= F7=1.
Table 13.1 Content of different registers So, at address 00, the register must be loaded with
Address of registers Contents of registers the value 11111111. Similarly, find the corresponding
00 1111 1111 values of F0 F1, F2, F3 F4, F5, F6 and F7 at each
01 0000 0000 address location from Table 13.1 and then the values
10 1010 1010
to be loaded into the memory register for all other
11 1111 1111
address. The number of registers in a memory device
is always a power of 2. If number of address line is 16, the number of registers will be 216 = 64K.
13.2.2 Implementation of Boolean Functions Using PROM
In implementation of combinational logic circuits using PROM, the circuit is expressed in minterms of
Boolean functions in the canonical sum of product form. For example, Fig.13.5 shows the implementation
of a typical Boolean functions as given below
 550 Digital Electronics: Principles and Applications

F = –xy– + –xy + xy– + xy, F1 = –xy– + xy

F2 = –xy– + –xy + xy– and F3 = –xy– + x–y + xy.
The PROM has two inputs x, and y and
four outputs F0, F1, F2, F3 which are used to
express the Boolean logic functions. The
2 to 4 line decoder decodes all minterms
–xy–, –xy, xy– and xy. These minterms are
also called as address lines. Actually,
PROM is a fixed AND plane (minterms) Fig. 13.5 Implementation of Boolean functions using
and a programmable OR
plane. Any combinations of
the minterms are connected
with OR gates for output. A
programmable switch is used
to establish the connection
between minterms and output
effectively. Connections with
in PROM have solid dots Fig. 13.6 Simplified representation of Fig.13.5
and unmarked intersections.
The solid dots represent logic 1 and
unmarked intersections stands for
logic 0. As shown in Fig. 13.5, all
minterms are connected with OR gate
for F0. Similarly, minterms –xy– and
xy are connected with OR gate for
F1. The simplified representation
of Fig. 13.5 is depicted in Fig. 13.6.
In one-dimensional addressing
mode, large numbers of input variables
are required for a large ROM. To
reduce the number of decoders, two-
dimensional addressing method of
ROM is used. The two dimensional
addressing scheme is shown in Fig.
13.7, which has eight input variables
A0 to A7 for 8 line to 256 line address
decoder and four other variables A8
to A11. Four input variables A8 to A11
are used as control signals of 16:1
multiplexers. In this scheme, 256 × 128 Fig. 13.7 Structure of a 32768 bit or 4Kbyte address in
= 32768 bit connections are needed to two dimensions
make the ROM matrix. It consists of
256 input lines and 8 × 16 =128 output lines.
 Programmable Logic Devices 551

13.2.3 Implementation of Sequential Circuits Using PROM

Sequential circuits are basically combinational circuits with feedback paths. PROMs can be used for
implementation of synchronous and asynchronous sequential circuits. The block diagram of sequential
circuit using ROM is illustrated in Fig.13.8. Here, present state is feedback to the next-state decoder.
The output of PROM A0+ A1+ … An-1+ are fed to D flip-flops which are driven by a common clock pulse
and flip-flops output are connected with PROM as feedback signals. The next state output of Y depends
on input X (X0 X1….Xn-1) and feed back inputs A0+ A1+ … An-1+ . Therefore, Y = f (X, A0+ A1+ … An-1+ ).

Fig. 13.8 Generalised sequential circuit using PROM

PROMs are fixed AND array, and programmable OR array. It can implement all minterms and any
OR combinations. Design of combinational and sequential circuits using PROM is very easy, as mini-
misation of logic function does not required. It is very chip compared to other PLDs but it’s all product
terms are not used. Therefore, complete memory will not be used in optimized way and power consump-
tion increases with number of input variables.

Example 13.1 Design a PROM structure to implement following Boolean functions

F1 =  m(0, 2, 5,7)
F2 =  m(1, 3, 4)
F3 =  m(0, 2, 3, 5,7)
 552 Digital Electronics: Principles and Applications

� Solution
The largest minterm of Boolean logic
functions is 7. Therefore, it is 3 variable
functions. To implement the Boolean logic
functions F1= Σ m(0, 2, 5,7) , F2= Σ m(1, 3,
4) and F3= Σ m(0, 2, 3, 5, 7) a 8 × 3 bit
PROM is required. Figure 13.9 shows the
PROM structure for implementing Boolean
functions F1, F2 and F3.

Fig. 13.9 PROM structure for F1, F2 and F3

Example 13.2 Implement the following logic functions F1, F2, F3 and F4 as given below using
PROM
F1 = Σm(0, 1,2,3,4,5,7); F2 = Σm(2,4,7,9,11)
F3 = Σm(10,12,14,15); F4 = Σm(1,2,3,5,7,9,13)

� Solution
The largest minterm of the four simultaneous logic functions is 15. So a 4 line to 16 line decoder is used to
decode minterms m0 to m15. To implement the Boolean logic functions F1= Σm(0, 1, 2, 3, 4, 5,7), F2= Σm(2, 4,
7, 9, 11), F3= Σm(10,12,14, 15) and F4= Σm(1,2,3,5,7,9,13) a 16 × 4 bit PROM is required. Figure 13.10 shows
the implementation of F1, F2 F3 and F4 using PROM.

Fig. 13.10 PROM structure for F1, F2, F3 and F4

 Programmable Logic Devices 553

Example 13.3 Design a 2 bit comparator using PROMs

� Solution
Table 13.2 shows the comparison of two 2-bit binary numbers. Here, the first data is A1 B1 and second data
is A0 B0. When A1B1 is greater than A0 B0, G = 1. If A1B1= A0 B0, E = 1. When A1B1 is less than A0 B0, L=1.
The implementation of 2-bit comparator using PROMs is depicted in Fig.13.11. Four inputs A1, B1, A0, B0
generates 16 minterms using 4 line to 16 line decoder. The Boolean logical expressions of L, E and G are
as follows
— —— —
L = A0 A1 + A0 B0 B1 + B 0 A1 B1
— —— — — — — —
E = A1 B1 A0 B0 + A1 B1 A0 B0 + A1 B1 A0 B0 + A1 B1 A0 B0 and
— — ——
G = A0 A 1 + A0 B0 B1 + B0 A1 B1.

The L, E and G can also be expressed in terms of minterms as given below:

L = Σm(1, 2, 3, 6,7,11); E=Σm(0, 5,10, 15) and G= Σm(4, 8, 9,13,14,15).

Table 13.2 2-bit Comparator

First Data Second Data minterms Less Than Equal Greater than
A1 B1 A0 B0 M L E G
0 0 0 0 m0 0 1 0
0 0 0 1 m1 1 0 0
0 0 1 0 m2 1 0 0
0 0 1 1 m3 1 0 0
0 1 0 0 m4 0 1 1
0 1 0 1 m5 0 0 0
0 1 1 0 m6 1 0 0
0 1 1 1 m7 1 0 0
1 0 0 0 m8 0 0 1
1 0 0 1 m9 0 1 1
1 0 1 0 m10 0 0 0
1 0 1 1 m11 1 0 0
1 1 0 0 m12 0 0 1
1 1 0 1 m13 0 0 1
1 1 1 0 m14 0 1 1
1 1 1 1 m15 0 0 0
 554 Digital Electronics: Principles and Applications

Fig. 13.11 PROM circuit of 2-bit comparator

Example 13.4 Design a 7-segment decoder using PROM structure

� Solution
The decimal number 0 to 9 can be displayed by the binary coded decimal inputs. Figure 13.12 shows the
display of decimal numbers 0
to 9 in seven segment displays.
For example, the segments
a, b, c, d, e, and f will be
bright for decimal number 0.
Similarly, other numbers will
be display. Table 13.3 shows
the different segments will be
bright for decimal number 0 Fig. 13.12 7 segment display of decimal numbers
to 9. The outputs a, b, c, d, e,
f and g are expressed in terms of mean terms as given below:
a = m(0,2,3,5,7,8,9),
b = m(0,1,2,3,4,7,8,9),
c = m(0,1,3,4,5,6,7,8,9)
d = m(0,2,3,5,6,8),
e = m(0,2,6,8),
f = m(0,4,5,6,8,9) and
g = m(2,3,4,5,6,8,9).
A BCD to 7-segment decoder can be implemented with a ROM as shown in Fig. 13.13 using 16 × 8=128 bit
ROM. As only seven columns are used, one column must be in don’t care state
 Programmable Logic Devices 555

Table 13.3 Truth table for seven segment display

Decimal Inputs Outputs
Number A B C D a b c d e f g
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 0 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 0 0 1 1
10 1 0 1 0 x x x x x x x
11 1 0 1 1 x x x x x x x
12 1 1 0 0 x x x x x x x
13 1 1 0 1 x x x x x x x
14 1 1 1 0 x x x x x x x
15 1 1 1 1 x x x x x x x

Fig. 13.13 PROM circuit of 7-segment decoder

Example 13.5 Design Binary to ASCII code conversion using PROM

� Solution
Truth table of binary to ASCII code conversion is shown in Table 13.4. The outputs A6 , A5 , A4 , A3 , A2 , A1
and A0 are expressed in terms of mean terms as given below. The implementation of Binary to ASCII code
conversion using 16 × 8 = 128 bit ROM is depicted in Fig. 13.14. As only seven columns are used, one
column must be in don’t care state.
A6 =  m(10,11,12,13,14,15)
A5 =  m(0,1,2,3,4,5,6,7,8,9)
556 Digital Electronics: Principles and Applications

A4 =  m(0,1,2,3,4,5,6,7,8,9)
A3 =  m(8,9)
A2 =  m(4,5,6,7)
A1 =  m(2,3,6,7,11,12,15)
A0 =  m(1,3,5,7,9,10,12,14)

Table 13.4 Truth table for Binary to ASCII code conversion

Binary minterms ASCII Code

A B C D m A6 A5 A4 A3 A2 A1 A0
0 0 0 0 m0 0 1 1 0 0 0 0
0 0 0 1 m1 0 1 1 0 0 0 1
0 0 1 0 m2 0 1 1 0 0 1 0
0 0 1 1 m3 0 1 1 0 0 1 1
0 1 0 0 m4 0 1 1 0 1 0 0
0 1 0 1 m5 0 1 1 0 1 0 1
0 1 1 0 m6 0 1 1 0 1 1 0
0 1 1 1 m7 0 1 1 0 1 1 1
1 0 0 0 m8 0 1 1 1 0 0 0
1 0 0 1 m9 0 1 1 1 0 0 1
1 0 1 0 m10 1 0 0 0 0 0 1
1 0 1 1 m11 1 0 0 0 0 1 0
1 1 0 0 m12 1 0 0 0 1 1 1
1 1 0 1 m13 1 0 0 0 1 0 0
1 1 1 0 m14 1 0 0 0 1 0 1
1 1 1 1 m15 1 0 0 0 1 1 0

Fig. 13.14 PROM circuit Binary to ASCII code conversion

 Programmable Logic Devices 557

Example 13.6 Design a PROM structure to implement the sequence table

Table 13.5
clock X m A1 A0 A1+ A0+ Y
0 m0 0 0 0 1 1
1 m4 0 0 1 0 0
0 m1 0 1 1 0 0
1 m5 0 1 0 1 1
0 m2 1 0 0 1 1
1 m6 1 0 0 0 0
0 m3 1 1 1 0 1
1 m7 1 1 0 1 1

� Solution
In the first row of Table 13.5, the current input to the ROM is A1= 0, A0= 0 X = 0 and the ROM output word is
A1+ = 0, A0+ = 1 and Y = 1. After the application of clock pulse, the ROM outputs A1+ = 0, A0+ = 1 are transferred
to the inputs of ROM A1 and A0 . When the ROM input is A1= 0, A0= 1, X = 0, the ROM output word is A1+ = 1,
A0+ = 0 and Y = 0. The outputs A1+, A0+ and Y are expressed in terms of mean terms as given below:
A1+ =  m(1,3,4)
A0+ =  m(0,2,5,7)
Y =  m(0,2,3,5,7).
The PROM can be used to implement the Table 13.5 with the help of additional logic element, D flip-flops.
Here, D flip-flops are used for transferring data from the outputs of ROM to the input of ROM on the positive
edge of the clock pulse. Figure 13.15 shows the implementation of Table 13.5 using PROM.

Fig. 13.15 Implementation of Table 13.5 using PROM

 558 Digital Electronics: Principles and Applications

13.3 PROGRAMMABLE
LOGIC
In programmable logic of PROM,
blowing the fusible link at all inter-
sections of the logic array the device
is programmed as per requirement. A
typical arrangement of AND, OR and
Ex-OR gates is shown in Fig.13.16.
–
Here, input X and it’s complement X
are connected to a AND gate through
bipolar or MOS transistor and fusible
link. Whe D gate. Therefore, output Fig. 13.16 (a) Programmable logic of AND gate
is in don’t care state. Figure 13.16 (b)
shows the connection of product terms
with OR gate. Output of OR gate is
in SOP form. If fuse link does not
blown, S=P. When fuse is not blown, Fig. 13.16 (b) Programmable logic of OR gate
S will be in don’t care state. Generally,
output of OR gates are connected
with XOR gates with fusible link
in programmable logic. The typical
connection of XOR gate is depicted
in Fig. 13.16 (c). When the fuse is in
Fig. 13.16 (c) Programmable logic of XOR gate
intact state, the input X of XOR gate is
grounded and it behaves as transmission gate which means output O=S. If the fuse is blown, the input X
–
is always in high state or logic 1. Then output O is complement of inputs. So O = S . These Programmable
logic of AND, OR and XOR gates are commonly used in all programmable logic devices.

13.4 PROGRAMMABLE LOGIC ARRAY

(PLA)
In Programmable Logic Array (PLA), the programmable AND
and OR arrays are used in order to realise any Boolean logic
functions. Fig. 13.17 shows the block diagram of Programmable
Logic Array (PLA). It has ‘n’ inputs, ‘k’ product terms and
‘m’ outputs. The number of product terms ‘k’ must be less
than 2n. As all possible 2n product terms are not available, the
logic functions must be represented in minimised form before Fig. 13.17 Block diagram of
implementation. The ‘m’ number of Boolean logic functions Programmable Logic
Array
 Programmable Logic Devices 559

are implemented using ‘k’ number of AND gates and ‘m’ number of OR gates. The typical structure of
PLA AND array and PLA OR array are explained in this section.
13.4.1 PLA AND Array
A typical structure of AND array is shown in
Fig.13.18. It has ‘k’ AND gates with product
outputs P0 through Pk–1. Each AND gate has ‘2n’
— — — —–
inputs D0,D0, D1, D1, D2, D2....... Dn–1, Dn–1. As each
AND gate has all input variables and the entire
fusible link are intact, the output of unprogrammed
— — — —–
AND gate will be D0 D0 D1D1D2D2.......Dn–1Dn–1.
After programming, each AND gate can be used
to generate a product term with proper selection of
input variables. Actually product terms are formed
by selectively blowing fuses at intersection of data
inputs and AND gate. When all intersection fuses
of AND gate are blown, AND gate output is in
Fig. 13.18 Structure of AND array don’t care state.

13.4.2 PLA OR Array

Figure 13.19 shows the structure of an OR
array to generate ‘m’ output functions F0,
F1, F2….Fm-1. There are ‘k’ product lines P0
to Pk–1 and all product lines are connected
with an OR gate. The output of OR gate is
the logical sum of the product terms. When
all the fuse links are intact, output F0=F1=
…Fn–1= P0 + P1 + P2…+ Pn-1. The OR array is
also programmable by blowing fuse links. If
the entire fuse links except P2, P3 and P4 of
first OR gate are intact, then output will be
F0=P2+ P3 + P4.
A typical PLA has 2 inputs A, B that can
produce 4 product terms and four outputs as
shown in Fig. 13.20. All input connections of
AND gate and OR gate are programmable.
Therefore, PLA has more flexibility than
PROM and PAL, but the circuit representation Fig. 13.19 Structure of an OR array
is very complex. After blowing the connecting
––
fuses, the output functions F1, F2, F3 and F4 are implemented as depicted in Fig.13.21. Here F1 = A B +
–– – – –– – –– –
AB, F2 = A B + A B + AB + AB, F3 = A B + A B + AB and F4 = A B + AB + AB.. In this figure, a dot
signifies that fuses are intact and without dot means that fuses are blown and there is no connection. The
simplified representation of Fig. 13.21 is illustrated in Fig. 13.22.
560 Digital Electronics: Principles and Applications

Fig. 13.20 Structure of a typical PLA with two input and four outputs

Fig. 13.21 Implementation of logic functions F1, F2, F3, and F4 using PLA
 Programmable Logic Devices 561

Fig. 13.22 Simplified representation of Fig.13.21

13.4.3 PLA ICs

Most commonly used PLA ICs are PLS 100, PLS 105, 82S100, 82S101, 82S105, 82S200, 82S201,
82S205, and PLUS 405 to implement combinational as well as sequential logic circuits. The PLS100
(3-State) and PLS101 (Open Collector) are bipolar fuse
Programmable Logic Arrays. These devices utilise the
standard AND/OR/Invert architecture for implementing sum
of product equations. Figure 13.23 shows the pin diagram
of PLS 100 and the logic diagram of PLS 100 is depicted
in Fig.13.24. This PLA IC has 16 inputs I0 to I15 and eight
outputs F0 to F7. Each input is fed to a driver circuit to generate
both inverted and non-inverted inputs for AND gates. Each
AND gate has 32 inputs and there are 48 product lines as 48
AND gates are available in this IC. OR gates have 48 inputs.
Therefore, each OR gate bus is a 48 line bus. All intersections
between the horizontal input lines and vertical input lines are
programmable. For inverting and non-inverting operation of
output, OR gate ouput is fed to XOR gate. When the fuse is
intact, the output will be non-inverting. If the fuse is blown,
the output will be inverting. To increase the driving capability
of the PLA, the output of XOR gates are connected with
—–
tristate drivers with a common external enable signal C E . If
—– —–
C E is low, the outputs are all turned on. When C E is high, the
outputs are in high impedance state. Application of PLS100 in
combinational logic circuit is given in Example 13.11.
Fig. 13.23 PIN diagram of PLS100
 562 Digital Electronics: Principles and Applications

Fig. 13.24 Logic diagram of PLS 100

13.4.4 Programming PLA ICs

A PLA programmer is used for programming an PLA devices. PLAs are generally available with fusible
links and erasable programmable devices for implementation of digital circuits. For programming, most
commonly used software’s are SNAP, PALASM, ABEL, CUPL and SLICE. All software packages
allow Boolean and state equation entry formats. Actually, the required input-output relationship is
developed inside a PLA ICs through programming. During manufacturing of mask programmable PLA
 Programmable Logic Devices 563

ICs, the data pattern according to design specification are generated by the manufacturer. In fusible link
programmable PLA, all fuses links are intact at the time of manufacturing. During programming some
fuse links are blown by applying voltages at the inputs and outputs of the device to develop specified
logic pattern in IC. This type of PLA is not reprogrammable.
The design procedure of a PLA based circuit is given below:
Step-1 Write the truth table of digital logic circuit, which will be implemented.
Step-2 Draw the K-map for each output with in variations of input variables and derive the simpli-
fied boolean logic expressions in SOP form.
Step-3 Simplify the Boolean logic expressions to get minimum SOP form.
Step-4 Determine the number of product terms and their logical expressions. Then find the input
connections of AND gate to generate all required product terms.
Step-5 Determine number of OR gates to implement output functions and find the input connection
of OR array to generate SOP form outputs.
Step-6 Find the requirement of programming of X-OR gates for invert or non-inverting the SOP
output.
Step-7 Lastly, the PLA will be programmed as per requirement of AND array and OR array to
implement the digital circuits. Some examples of PLA are incorporated in this section.

13.4.5 Applications of PLAs

Generally, PLA ICs are used to implement any combinational and sequential logic circuits. Some
examples are illustrated in this section. PLA ICs are also used in CRT display systems, function
generators, look-up and decision tables, code conversion, peripheral controllers, microprogramming,
address mapping, character generators, 16-bit to 8-bit bus interface, random logic replacement, data
security encoders, fault detectors, and frequency synthesisers.

Example 13.7 Derive the logic expression of PLD as shown in Fig. 13.25.

� Solution
Figure 13.25 shows the structure of a typical PLA. There are three inputs A, B, C and six product lines P0 to
–
P5. Dot sign in the AND array means that product line is connected with inputs. As P0 is connected with A ,
– – ––– – –– –
B and C , the product term P0 = A B C . Similarly, other product terms are P1 = A BC, P2 = AB C , P3 = ABC ,
–
P4 = AB C and P5 = ABC. Outputs are available from F1, F2, F3, and F4 through OR gate. It is depicted in
Fig.13.25 that the OR gate is connected with each product line. After programming some fuses are blown
and remaining fuses are intact. The output of OR gate is sum of product terms. As the first OR gate is
–––
connected with P0, P3, and P5, output F1 will be sum of these three product terms. So F1=P0+P3+P5 = A B C +
–
ABC + ABC. Similarly, other output functions can be expressed using product terms as given below

F2 = P0+P1+P2+P3+P4+P5, F3 = P0+P1+P3+P5, and F4= P0+P2+P3+P4+P5.

 564 Digital Electronics: Principles and Applications

Fig. 13.25 Structure of typical PLD

Example 13.8 Design a PLA structure using AND and OR logic for the following functions.
F1= m (0,1,2,3,4,7,8,11,12,15)
F2= m (2,3,6,7,8,9,12,13)
F3= m (1,3,7,8,11,12,15)
F4= m (0,1,4,8,11,12,15)

� Solution
Figures 13.26 (a), (b), (c) and (d) represents the K-map of Boolean logic functions F1, F2, F3 and F4
respectively. The Boolean logic expressions of F1 from K-map is
1 2 3
–– – –
F1 = A B + C D + CD
Similarly, other logic expressions are
4 5 3 6 7 2 8 9
– – –– –– –– –– –––
F2 = A C + AC , F3 = CD + AC D + A B D, and F3 = C D + AC D + A B D
Therefore, there are nine product terms in the above four logic functions. Each prime implicants are numbered.
––
Some of prime implicants like C D and CD are common in functions. To generate nine product terms, nine
AND gates are needed. The implementations of all these Boolean logic functions using PLA AND array and
OR array are shown in Fig. 13.27.
 Programmable Logic Devices 565

Fig. 13.27 PLA structure for implementation of F1, F2, F3 and F4

 566 Digital Electronics: Principles and Applications

Example 13.9 Design a PLA structure to implement NAND, NOR, EXOR and EXNOR functions.

� Solution
Firstly, the Boolean function of NAND, NOR, EXOR and EXNOR are expressed in terms of Products before
implementation using PLA. The logical expression of two inputs NAND, NOR, EXOR and EXNOR are
–— –—— – – – – –—— – –
F1 = A B , F2 = A + B = A B , F3 = A  B = AB + A B, and F4 = A  B = A B + AB respectively.
To implement NAND, NOR, EXOR and EXNOR functions, four product terms P0, P1, P2 and P3 are required.
–– – –
These product terms are P0 = A B , P1 = A B, P2 = AB , and P3 = AB. The implementation of NAND, NOR,
EXOR and EXNOR functions using PLA is depicted in Fig.13.28.

Fig. 13.28 Implementation of NAND, NOR, EXOR and EXNOR

Example 13.10 Design a 2-bit comparator using PLA.

� Solution
The implementation of two-bit comparator using PROM is already explained in Example 13.3. If PLA is
used to implement the two-bit comparator, fuse map will be different as all product terms are not available in
a typical PLA device. Consider the first data is A1 B1 and second data is A0, B0. When A1B1 is greater than A0,
B0 , G = 1. If A1B1= A0, B0, E = 1. When A1B1 is less than A0, B0 , L = 1. The logical expressions of L, E and
G are L = m(1, 2, 3, 6,7,11), E = m(0, 5,10, 15) and G = m(4, 8, 9,13,14,15) and can be expressed using
product terms as given below:
1 2 3 4
— — —— — — — —
E = A1B1A 0B0 + A 1B1A 0B0 + A1B1A0B0 + A1B1A0B0
5 6 7 8 9 10
— —— — — — ——
L = A0 A1 + A 0B0 B1 + B0A1B and G = A0 A 1 + A0 B0 B1 + B0 A 1 B 1
There are ten prime implicants as given above. Figure 13.29 shows the implementation of 2-bit comparator
using PLA.
 Programmable Logic Devices 567

Fig. 13.29 PLA structure of 2-bit comparator

Example 13.11 Design a PLA structure for implementation of following logic functions using
PLS100:

– – – –
F1 = AB + A CD, F2 = ACD + BC + A D, F3 = AB + C D, and F4 = ABC + A CD

� Solution
Figure 13.30 shows the PLS 100, which has 16 inputs, 8 outputs and 48 product terms. The output functions
F1,F2 , F3, and F4 are function of four input variables A, B, C and D. Therefore, four inputs are applied to
PLS 100 and eight product terms are required to implement above logic functions. The fuses of Ex-OR gates
are to be kept intact to maintain these inputs at ground level for active high outputs. The implementation of
– – – –
Boolean functions F1 = AB + A CD, F2 = ACD + BC + A D, F3 = AB + C D, and F4 = ABC + A CD is depicted
in Fig. 13.30.
 568 Digital Electronics: Principles and Applications

Fig. 13.30 Implementation of F1, F2, F3 and F4 using PLS100

13.5 PROGRAMMABLE ARRAY LOGIC (PAL)

The PAL is programmable array of logic gates like PLA. In PAL, AND array is programmable and OR
array is fixed. All inputs are connected with AND gate and all the AND gate outputs are not connected to
a OR gate. Therefore only a few fixed product terms can be implemented through OR gates. Figure 13.31
shows the simple pattern of AND and OR arrays of a PAL with 4 inputs, 6 programmable AND gates and
3 fixed OR gates. Each AND gate is connected with all inputs and generates a product term. So six AND
 Programmable Logic Devices 569

Fig. 13.31 Programmable array logic

gates can produce six product terms. There are two inputs of a OR gate and each OR gate has been used
to sum of two product terms. The total number of programmable fusible links of PAL is 2 × number of
inputs × number of product terms=2 × 4 × 6 = 48. Figure 13.32 shows that the PAL has been programmed
by selectively burning the fusible links to implement the following combinational logic functions.
– –
F1 = AC + BD, F2 = ABC + CD, and F3 = AD + BC
– –
There are six product terms such as P0=AC, P1=BD, P2=ABC , P3= CD, P4=AD, and P5= BC. Then OR
gates sum the product terms to generate output functions F , F and F as depicted in Fig. 13.32.

Fig. 13.32 Implementation of F1, F2 and F3 using PAL

 570 Digital Electronics: Principles and Applications

13.5.1 Internal Structure of PAL ICs

Generally, PAL ICs are available with different individual logic circuit. Most commonly used PAL circuit
configurations are depicted in Fig. 13.33. Figure 13.33 (a) shows a single logic circuit of a PAL. It has
two level logic circuit with seven AND gates of 32 inputs followed by a seven input OR gate. The top
AND gate is used to enable output buffer. All intersection of horizontal and vertical input lines of AND
gate are programmable. When a single line is used to represent a number of connections, it is called a
bus. The leveling of the circuit is depicted in Fig. 13.33 (a). The pin numbers are available externally to
connect with input signals and to get output from circuit. Here, I3 is one of the dedicated inputs and it
is connected with a driver to generate high and low assertion level of input signals. Therefore, the input
and it’s complement are available. B1 of the logic circuit is a bi-directional pin. The output of OR gate
is connected with a tristate driver and output of top AND gate is used as driver enable of tristate buffer.
When the enable is high, output signal is available at output. When enable is low, output of the driver is
in high impedance state. The enable input of driver is programmable. If driver output is enabled, B1 pin
behaves as output function. If the output driver is disabled, B1 pin will be used an input with it’s input
driver. Figure 13.33(b) is identical to the circuit Fig. 13.33(a) except it has low output assertion. The
top AND gate drives the inverted tristate driver. Figure 13.33(c) is similar with Fig. 13.33 (b) except it’s
output can not be used as feedback input but it will be used as output only.

Fig. 13.33 (a) Simple PAL circuit with dedicated high assertion level output

Fig. 13.33 (b) Simple PAL circuit with dedicated low assertion level output

Fig. 13.33 (c) Simple PAL with dedicated high assertion level output
 Programmable Logic Devices 571

Fig. 13.33 (d) Simple PAL with dedicated high assertion level output

Fig.13.33 (e) Simple PAL with dedicated low assertion level output

Figure 13.33(d) has eight AND gates of 32 inputs with respect of seven AND gates of Fig.13.33 (a)
and (b). This circuit has no tristate driver. The output of OR gate is connected with a buffer. So the output
of this circuit is dedicated high assertion level. Figure 13.33(e) is identical to the circuit Fig.13.33(d)
except it has low assertion level output as the inverted driver is connected with output of OR gate.
Figure 13.33(f ) shows the register output configuration, which is commonly used in sequential logic
– –
circuit. In this circuit the feedback is taken from output of D flip-flop, Q. Here, both Q and Q are
–
available as Q is connected with a driver circuit. Figure 13.33(g) is one PAL with programmable macro
cell output. This circuit can be configured in such a way that combinational and register circuits can be
implemented using this circuit.

Fig. 13.33 (f ) Simple register logic circuit of PAL

Fig.13.33 (g) A section of a PAL with programmable macro cell output

13.5.2 PAL ICs

The PAL16XX series utilises the sum of products implementation consisting of a programmable AND
array and a fixed OR array. The PAL16XX series consists of four PAL-type devices, namely PAL16L8,
 572 Digital Electronics: Principles and Applications

PAL16R8, PAL16R6, and PAL16R4. The pin diagram of PAL16L8, PAL16R8, PAL16R6, and
PAL16R4 are depicted in Fig. 13.34. Depending on the type of PAL device, there are a variable number
of combinational and registered outputs are available from the device. These devices are also capable
of replacing SSI/MSI integrated circuits to reduce package count and space, consequently improving
reliability of digital circuits.

(a) (b)

(c) (d)

Fig. 13.34 (a) Pin diagram of PAL16L8 (b) Pin diagram of PAL16R8
(c) Pin diagram of PAL16R6 (d) Pin diagram of PAL16R4
 Programmable Logic Devices 573

The logic circuit of PAL16L8 is depicted in Fig.13.35. It consists of eight separate logic circuits
and the sum of products AND-OR architecture, which is composed of 64 programmable AND gates
and eight fixed OR gates. This PAL circuit has ten dedicated inputs I0 to I9 and six bi-directional input
output lines B1 to B6, which can be individually configured as inputs or outputs. This circuit also has two
completely dedicated output lines and can be used to implement any combinational logic circuit.

Fig. 13.35 Logic diagram of PAL16L8

In some PAL ICs, both combinational logic circuit and flip-flops exist to implement sequential logic
circuits. Figure 13.36 shows the logic circuit of a small registered PAL16R4 IC. It has separate eight
programmable logic circuits. The top two and bottom two circuits are simple combinational logic
 574 Digital Electronics: Principles and Applications

circuits. It also consists of four D flip-flops. Each D flip-flop is loaded on the low to high transition of
the clock input. The outputs of flip-flops are capable to use as feedback inputs into the array to facilitate
design of synchronous state machines. A power–up reset function has been incorporated in PAL16RX
series ICs to reset all internal registers to active low after specified time duration. The PAL 16R8 has
eight output registers and the PAL 16R6 has six output registers. The logic diagram of PAL 16R8 and
PAL 16R6 are depicted in Fig. 13.37 and Fig. 13.38 respectively.

Fig. 13.36 Logic diagram of PAL16R4

The PAL16XX family of devices is field programmable, enabling the designer to quickly generate
custom patterns using standard programming equipments. The SNAP software package supports easy
 Programmable Logic Devices 575

design entry for the PAL16XX series as well as other PLD devices. Other industry standard CAD tools,
SLICE, PALASM, ABEL and CUPL also support the PAL16XX series. All software packages allow
Boolean and state equation entry format. ABEL, CUPL and SNAP are also accept data in schematic
capture format.

Fig. 13.37 Logic diagram of PAL16R8

 576 Digital Electronics: Principles and Applications

Fig. 13.38 Logic diagram of PAL16R6

PAL 22V10 is a CMOS flash erasable programmable array logic device. It is implemented with sum
of product (AND-OR) logic architecture and the programmable macro cell. The programmable macro
cell provides the capability of defining the architecture of each output individually. The logic circuit
diagram of PAL 22V10 is depicted in Fig. 13.39. It has ten logic sections and each logic section has 8 to
16 AND gates. The top AND gate of each section is independent programmable enable. This circuit has
12 inputs and ten programmable input/outputs. It can be used to design combinational logic circuits and
sequential (synchronous and asynchronous) logic circuits. There is some provision of asynchronous reset
(AR) and synchronous preset (SP) of all register outputs as depicted in Fig. 13.40. Each logic section
may be specified as registered or combinational. Therefore, polarity of each output S0 S1 may be selected
 Programmable Logic Devices 577

properly to allow complete flexibility of output configuration. Table 13.6 shows the configuration table
of each section. In combinatorial mode operation, S0= 0, S1= 1 for active low output and S0= 1, S1= 1 for
active high output. During registered mode operation, S0= 0, S1= 0 for active low output and S0= 0, S1= 1
for active high output. Figure 13.41 shows the register mode and combinational mode of macro cell.

Fig. 13.39 Logic diagram of PL 22V10

578 Digital Electronics: Principles and Applications

Fig. 13.40 Logic diagram of macro cell of PAL 22V10

Table 13.6 Configuration table

S1 S0 Configuration
0 0 Registered and active low output
0 1 Registered and active high output
1 0 Combinatorial and active low output
1 1 Combinatorial and active high output

Fig. 13.41 Combinatorial mode: (a) S0=0, S1=1 active low output and (b) S0=1, S1=1 active high
output; Registered mode: (c) S0=0, S1=0 active low output and
(d) S0=1, S1=0 active high output
 Programmable Logic Devices 579

13.6 COMPARISON BETWEEN PROM, PAL, AND PLA

Programmable Read Only Memory (PROM) is a fixed architecture programmable logic device and can
be used as memory devices. Data stored in the ROM can be read whenever required, however the stored
data cannot be changed under operating conditions. The PROM is not too much flexible with respect
to PAL and PLA. The PLA is the programmable AND and OR arrays and these logic devices are very
useful to implement any Boolean function. The PAL is more flexible than the PROM as AND array is
programmable but OR array is fixed. The detail operations of PROM, PAL, and PLA are explained in
previous sections. The comparison between PROM, PAL, and PLA are given Table 13.7.
Table 13.7 Comparison between PROM, PAL, and PLA
PROM PAL PLA
1. ROM - fixed AND array and 1. PAL - programmable AND array, fixed 1. PLA - programmable AND and
programmable OR array. OR array. OR arrays.
2. Can implement all minterms 2. Due to the fixed OR plane, the design 2. Most flexible, can implement any
and any OR combination. It is of logic circuits using PAL is very fast function—limited to the device
a medium speed device. in design and operation also fast. These functionality.
devices implement functions limited in
the number of terms.
3. Cheap 3. Cheaper and most popular. 3. Most expensive and very sophisti-
cated design tools are required to
design PLA devices.
4. These devices are very useful 4. These devices are used in sequential 4. These devices are used in combina-
when there is a limited number network design. tional logic circuit design.
of inputs combinational and
sequential logic circuit.

Example 13.12 Design a PAL circuit to implement the following combinational logic functions
F1= m(3,5,7,8,10,12,14); F2= m(7,11,13,14,15)

� Solution
The K-map of combinational logic functions F1, and F2 are illustrated in Fig. 13.42 (a) and (b) respectively.
– – –
The Boolean logic expression of F1 from K-map is F1 = AD + A CD + A BD. Similarly, the logic expression
of F2 is F2 = BCD + ACD + ABD + ABC. To implement the logic functions F1 and F2, three and four
product terms are required. The implementation of above logic functions using PAL 16L8 are depicted in
Fig. 13.43.

Fig. 13.42 (a) K map for F1 (b) K map for F2

 580 Digital Electronics: Principles and Applications

Fig. 13.43 Implementation of F1 and F2 using PAL16L8

Example 13.13 Design a 4 bit synchronous binary counter using PAL.

� Solution
A 4-bit binary counter has 16 different states. The counter has one clock input terminal and one overflow
terminal. The counter counts zero to fifteen sequentially. After count fifteen, the counter will reset to zero.
The block diagram of a 4-bit synchronous counter is given in Fig. 13.44. Clock (CLK) and present state d3 d2
d1 d0 are used as inputs of the counter. The next state output and overflow are the output of the counter. Table
13.8 shows the truth table of synchronous counter.
 Programmable Logic Devices 581

Fig. 13.44 Block diagram of 4-bit synchronous counter

Table 13.8 Truth table of 4 bit synchronous counter

Clock(CLK) Present state Next state Over flow
d3 d2 d1 d0 D3 D2 D1 D0
0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 1 0
0 0 0 0 1 0 0 0 1 0
1 0 0 0 1 0 0 1 0 0
0 0 0 1 0 0 0 1 0 0
1 0 0 1 0 0 0 1 1 0
0 0 0 1 1 0 0 1 1 0
1 0 0 1 1 0 1 0 0 0
0 0 1 0 0 0 1 0 0 0
1 0 1 0 0 0 1 0 1 0
0 0 1 0 1 0 1 0 1 0
1 0 1 0 1 0 1 1 0 0
0 0 1 1 0 0 1 1 0 0
1 0 1 1 0 0 1 1 1 0
0 0 1 1 1 0 1 1 1 0
1 0 1 1 1 1 0 0 0 0
0 1 0 0 0 1 0 0 0 0
1 1 0 0 0 1 0 0 1 0
0 1 0 0 1 1 0 0 1 0
1 1 0 0 1 1 0 1 0 0
0 1 0 1 0 1 0 1 0 0
1 1 0 1 0 1 0 1 1 0
0 1 0 1 1 1 0 1 1 0
1 1 0 1 1 1 1 0 0 0
0 1 1 0 0 1 1 0 0 0
1 1 1 0 0 1 1 0 1 0
0 1 1 0 1 1 1 0 1 0
1 1 1 0 1 1 1 1 0 0
0 1 1 1 0 1 1 1 0 0
1 1 1 1 0 1 1 1 1 0
0 1 1 1 1 1 1 1 1 0
1 1 1 1 1 0 0 0 0 1
The next state output of synchronous counter D3, D2, D1 and D0 can be expressed in terms of present state
inputs d3, d2, d1, d0 and CLK as given below:
 582 Digital Electronics: Principles and Applications

— ——–
D0 = d 0CLK + d0C L K
— ——– —
D1 = d 0C L K + d1d0CLK + d 1d0
— ——– — — — —
D2 = d2d1d0CLK + d 2C L K + d 2d 1 + d 2d 0
— ——– — —
D3 = d3d2d1d0CLK + d 3C L K + d 3d 0
— — — — ——–
and over flow can be expressed as OF = d3d2d1d0CLK = D3 = d 3 + d 2 + d 1 + d 0 + C L K . Figure 13.45 shows
the implementation of 4 bit synchronous counter using PAL16R6.

Fig. 13.45 Implementation of F1 and F2 using PAL16R6

13.7 SIMPLE PROGRAMMABLE LOGIC DEVICES (SPLDS)

Presently several types of programmable logic architecture are available. The major types are Simple
programmable logic devices (SPLDs), Complex programmable logic devices (CPLDs), and Field
programmable gate arrays (FPGAs). Simple programmable logic devices (SPLD) are the simplest,
smallest and cost effective type of programmable logic device(PLD). These devices consists of 4 to 12
macrocell configurations. Each macro cell is typically connected to the other parts in the device and it
use some form of combinational logic (AND and OR gates) and sequential logic (flip-flop). In other
 Programmable Logic Devices 583

words, Boolean logic equations can be fabricated within each macrocell. These boolean logic equations
can also be able to amalgamate the state of binary inputs into a binary output and may be able to store
that output in the flip-flop.
Generally, SPLDs use fuses or non-volatile memory cells such as EPROM, EEPROM and Flash
memory. SPLDs are also known as programmable Logic Arrays (PLA), Programmable Array Logic
(PAL), Field-Programmable Logic Arrays (FPLA), Generic Array Logic (GAL), and Programmable
Logic Devices (PLD). SPLD ICs are available in different integrated circuit (IC) packages, such as
single in-line package (SIP), dual in-line package (DIP), discrete package (DPAK), small outline
package (SOP), and quad flat package (QFP). Some SPLD manufacturers are Altera, Atmel, Cypress,
Latice, Philops, and Vantis. Now a days SPLDs can be used as a substitute of 74 series TTL ICs and
applied in communication, industrial and commercial applications.

13.8 COMPLEX PROGRAMMABLE LOGIC DEVICE (CPLDS)

Complex Programmable Logic Devices (CPLDs) are most commonly used programmable logic in
the electronics industry. It is the interconnection of Simple Programmable Logic Devices (SPLDs).
Actually, a number of SPLDs on a single chip with a programmable wiring network which can
develop interconnections between the individual programmable logic blocks. The main idea behind
CPLDs is that it can be used as substitute of discrete logic as CPLDs do not require external devices
for configuration and these devices can be able to provide a single chip logic solution.

CPLDs are also known as PEEL Array (Programmable Electrically Erasable Logic Array), EPLD
(Erasable Programmable Logic Device), EEPLD (Electrically-Erasable Programmable Logic Device)
and MAX (Multiple Array Matrix). These devices are manufactured based on CMOS EEPROM
technology and are available in 24, 28, and 44 pin packages in plastic Dual In-line Package (DIP),
plastic leaded chip carrier (PLCC), Quad Flat Pack (QFP), ceramic Pin Grid Array (PGA). A number
of CPLDs are available by different manufacters namely Altera, Atmel, Cypress, Latice, Philips,
Vantis and Xiliux etc. But Alteras CPLD products MAX 3000, MAX 7000, MAX 9000 and Xiliux
CPLD product XC9500 are most commonly used ICs in electronic industry.

Figure 13.46 shows the block diagram of CPLD. It consists of SPLDs, I/O blocks and programmable
wires. The connection between SPLDs and I/O block through programmable wires is depicted in
Fig. 13.47. A SPLD block is basically Programmable Array Logic (PAL) or Programmable Logic
Arrays (PLA) and Macrocells. Therefore, the base architecture of CPLD is versatile multiple-level
PLA or PAL architecture rich in input latches, buried registers, and sum-of-product logic functions.
A Macrocell consists of registers and a combinational path. It also provides feedback to the
Interconnect Array and I/O cells. The block diagram of a typical Macrocell is shown in Fig. 13.48.
This Macrocell consists of product terms, multiplexers and flip-flops. CPLDs have non-volatile
characteristics and low power consumption. When the power is removed, the program will still be
there. Generally, CPLDs are used in memory interface, low power applications, control operations
and bus control, etc.
584 Digital Electronics: Principles and Applications

Fig. 13.46 Block diagram of a CPLD

Fig. 13.47 Connection between SPLDs, I/O block and programmable wires of a CPLD
 Programmable Logic Devices 585

Fig. 13.48 Block diagram of a typical macrocell

13.9 FIELD PROGRAMMABLE GATE ARRAY (FPGA)

The most common field-programmable logic elements are Programmable Logic Devices (PLDs).
PLDs are primarily two-level logic device and they are used to implement logic functions in sum-of-
products form. PLDs have simple routing structures with conventional delays. As they are completely
prefabricated, these devices are readily available to use in seconds without delay of chip fabrication.
To enhance the flexibility, functionality and to increase effective size of PLDs, field programmable
gate array (FPGA) has been developed. In the late 1980s, the Field-Programmable Gate Array (FPGA)
was introduced to implement digital logic circuits. FPGAs are capable to implement significantly more
logic circuits than PLDs as they are based on multi-level logic. Most of the FPGAs are configured by
static RAM cells. These ICs can able to handle very complex circuits on a single chip but it scarifies the
predictable delays of PLDs. Most commonly used FPGA products are XC5200, XC4000, XC3000, and
XC2000 manufactured by Xiliux; Flex 6000, Flex 8000, Flex 10K, APEX 20K manufactured by Altera;
CY7C385P, CY7C386P, CY7C387P and CY7C388P manufactured by Cypress. These ICs contain
thousands of gates and can be used to implement very complex logic circuits.
Just like PLDs, FPGAs are also pre-fabricated and contain special features for customisation. The
FPGA configuration points are usually SRAM cells, EPROM, EEPROM or antifuses. Antifuse-based
FPGAs are one-time programmable devices as the configuration of an antifuse is permanent. The
SRAM cells based FPGAs are reprogrammable. As SRAMs are volatile, SRAM cells based FPGA be
required to reprogram every time when the system power supply is ON. Therefore, a ROM has been
incorporated in the circuit to hold the digital logic
circuit configuration. The features of EEPROM and
EPROM devices are lies in between SRAM cells
and antifuse. The programming of an EEPROM/
EPROM must be retained even after the power is
turned off, but the high voltages are required for
programming the device. SRAM cells are larger
than antifuses and EEPROM/EPROM. Therefore,
Fig. 13.49 Configuration SRAM cell of FPGAs SRAM cells based FPGAs have less configuration
 586 Digital Electronics: Principles and Applications

Fig. 13.50 Architecture of a FPGA

points than FPGAs using antifuses and EEPROM/EPROM technologies. On the other hand, SRAM-
based FPGAs have numerous advantages. SRAM are easily reprogrammable and their configurations
can also be changed. These devices have numerous different configurations, such as multi-mode systems
and reconfigurable computing machines. In SRAM-based FPGA, SRAM cells are scattered throughout
the FPGA. Figure 13.49 shows the configuration of memory cell. Here the n-transistor gate provides
–
either read or writes operation. The actual control of FPGA can be done by Q and Q.
Field Programmable Gate Array (FPGA) is the workhorse of the programmable logic industry. FPGA
are constructed by interconnected logic cells. FPGA can also replace discrete logic. Discrete logic is the
devices, which are interconnected SSI ICs with wires. It is also volatile. It requires reprogramming after
each power cycle. Xilinx logic cell array is well-known FPGAs. The third generation FPGA is the Xilinx
4000 as its structure is depicted in Fig.13.50. The Xilinx logic cells are embedded in a general routing
 Programmable Logic Devices 587

Fig. 13.51 Simplified logic diagram of a configurable logic block

structure, which permits arbitary point to point, communication. The

IOBs ring the outside of the device to interconnect to the outside world.
Configurable Logic Blocks (CLB) are used to implement combinational
and sequential logic. The look up table is the basic building block of the
FPGA. Fig.13.51 shows the simplified logic diagram of CLB. The CLB
consists of three lookup-tables (LUTs), two programmable flip-flops,
and multiple programmable multiplexers. The LUTs allow to generate
arbitrary combinational functions of its inputs. Any function of four /five
inputs and some functions of up to nine inputs can be implemented by
this structure. The propagation delay of LUT is independent of the functin
implemented. SRAM controlled multiplexers and two D flip-flops be able
to route the output signals X and Y. Figure 13.52 shows the logic diagram Fig. 13.52 D flip-flop
of D flip-flop. The input signals C1 to C4 generate enable and set or reset
signals to the flip-flops, a direct connection to the flip-flop inputs, and also input of LUT. In this way, this
structure provides a very powerful method of implementing arbitrary, complex digital logic.
Interconnecting wires are used to connect inputs and outputs of logic blocks. Input-output blocks are
special logic blocks at periphery of device for external connections. The series of programmable interconnects
connects the CLBs. The source and destinations of signals must be relatively close together for good routing
in this structure. The routing structure of FPGA is shown in Fig.13.53. At the intersection of each horizontal
and vertical routing channel is a programmable switch matrix as depicted in Fig.13.54. Each of the inputs of
CLB comes from one of a set of horizontal and vertical tracks adjacent to that CLB. Generally, the routing
structure is made up of three lengths of lines namely single-length lines, double-length lines and long lines.
 588 Digital Electronics: Principles and Applications

Single-length lines (SL) pass through the height

of a CLB and they then enter a programmable
switch matrix. The switch matrix allows this
signal to travel out horizontally/vertically from
the switch matrix. In this way multiple single-
length lines may be cascaded together for passing
signals to cover long distance. These lines are
used for connecting adjacent CLBs through PSM
and provide fast routing between adjacent CLBs.
Due to more propagation delay, these lines are not
suitable for routing long distances. Double-length
lines (DL) are similar with single-length lines,
but they travel the height of two CLBs before
entering a programmable switch matrix. It also be
noted that only half the double-length lines enter a
switch matrix and there is a twist in the middle of
the line. Therefore, double-length lines are useful
for longer-distance routing without incurring
propagation delays. Long lines (LL) do not enter
any programmable switch matrix and run the entire Fig. 13.53 Segmentation architecture
length and width of the array. These lines can cover
very long-distance routes efficiently and propagation delay time is minimum for long lines signals.
Generally, FPGAs are used in implementation of digital logic. FPGAs are also applied in digital
signal processing, modems, printers, video capture/ editing, mathematics applications such as long
multiplication, modular multiplication, and cryptography; physics applications such as real-time pattern
recognition in high-energy physics, statistical physics, Heat and Laplace equation solvers; general
algorithms such as the traveling salesman problem, genetic optimisation algorithms, region detection
and labeling, stereo matching for stereo vision, speech recognition, and genetic database searches, etc.

Fig. 13.54 (a) Programmable switch matrix (b) Six pass transistors per
switch matrix interconnect point
 Programmable Logic Devices 589

SUMMARY
In this chapter, the basic concept of digital system design using standard product ICs and application specific ICs
(ASICs) has been explained. PROM, PLA and PAL are most commonly used programmable logic devices to implement
sum of product expressions of digital logic circuits in ASIC design. PLA architecture is programmable AND and OR
array; PAL architecture is programmable AND and fixed OR array, but PROM is fixed AND array and programmable
OR array. These PLD devices are manufactured by mask, fusible link and floating gate programming technology. In
this chapter, applications of PLDs for implementing both combinational and sequential digital systems have been
incorporated. The concepts of Simple Programmable Logic Devices (SPLDs), Complex Programmable Logic Devices
(CPLDs) and Field Programmable Gate Array (FPGA) have also been discussed in this chapter.

MULTIPLE CHOICE QUESTIONS

1. The advantage of logic circuit design using fixed function ICs is
(a) Low development cost (c) Security
(b) Large board space (d) Low power consumption
2. The example of application specific integrated circuits (ASICs) is
(a) Programmable logic devices (c) Multiplexer
(b) Shift register (d) Logic gates
3. Which of the following devices is not a PLD?
(a) PLA (b) PAL (c) PLD (d) ROM
4. Which of the following devices are PLD?
(a) PROM (b) PAL (c) FPGA (d) ROM
5. A PROM is
(a) Fixed OR and programmable AND (c) Fixed OR and fixed AND
(b) Fixed AND and programmable OR (d) Programmable OR and programmable AND
6. A programmable logic device(PLD) consists of
(a) Fixed function ICs (c) Programmable array of logic gates
(b) ROM (d) None of these
7. A PLA device consists of
(a) AND matrix (b) OR matrix (c) Flip-Flops (d) Counters
8. A PLA is
(a) Fixed OR and programmable AND (c) Fixed OR and fixed AND
(b) Fixed AND and programmable OR (d) Programmable OR and programmable AND
9. PAL can accommodate a circuit which consists of
(a) 100 gates (b) 200 gates (c) 10 gates (d) 150 gates
10. A PAL is
(a) Fixed OR and programmable AND (c) Fixed OR and fixed AND
(b) Fixed AND and programmable OR (d) Programmable OR and programmable AND
11. CPLD can accommodate a circuit, which consists of
(a) 1000 gates (b) 10000 gates (c) 100 gates (d) 10 gates
 590 Digital Electronics: Principles and Applications

12. Number of macrocells of CPLD is

(a) 500 (b) 100 (c) 10 (d) None of these
13. A CPLD consists of
(a) PAL block, I/O block and interconnection wires
(b) PLA block, I/O block and interconnection wires
(c) PROM block, I/O block and interconnection wires
(d) None of thsese
14. PLDs are programmed using
(a) PROM technology (c) EEPROM technology
(b) EPROM technology (d) None of these
15. FPGA can accommodate a circuit, which consists of
(a) Above 10000 gates (c) 1000 gates
(b) Below10000 gates (d) 10 gates
16. Programmable low impedance circuit element (PLICE) used in
(a) CPLD (b) FPGA (c) PAL (d) PLA
17. CPLD can accommodate a circuit, which consists of
(a) 1000 gates (b) 10000 gates (c) 100 gates (d) 10 gates
18. Configurable logic block (CLB) consists of
(a) Flip-flops (b) PROM (c) Logic gates (d) None of these
19. Number of transistor of a programmable switch matrix interconnect point of FPGA is
(a) 6 (b) 4 (c) 2 (d) 1
20. An FPGA consists of
(a) CLB, PSM, and I/O block (c) CLB, and I/O block
(b) CLB,and PSM (d) None of these
21. The propagation delay FPGA routing channels is maximum in
(a) Single length lines (c) Longlines
(b) Double length lines (d) None of these
22. Which of the following PLD devices are used as register?
(a) PAL16L8 (b) PAL16R8 (c) PAL16R4 (d) PAL16R6
23. Which of the following PLD devices are used in combinational logic?
(a) PAL16L8 (b) PAL16R8 (c) PAL16R4 (d) PAL16R6

REVIEW QUESTIONS
13.1 Define standard product ICs and ASICs. What are the types of ASICs? Write the advantages of ASICs
with respect to standard product ICs.
13.2 What are the types of ROMs? Write a block diagram of a ROM and explain it’s operation. What are
the advantages and limitations of PROM?
13.3 Implement the following logic functions F1, F2 and F3 as given below using PROM
F1= m (0, 1,4,5,7,11)
F2= m (2, 7, 8, 9,11)
 Programmable Logic Devices 591

F3= m (4,5, 10,12,14,15)

F4= m (1,2,3,5,7,9,13)
13.4 Design a 4 bit comparator using PROMs.
13.5 Design a PROM structure to implement the Sequence Table 13.9.

Table 13.9

clock X A1 A0 A1+ A0+ Y

0 0 0 0 1 1
1 0 0 1 0 0
0 0 1 1 1 0
1 0 1 1 1 1
0 1 0 0 1 1
1 1 0 0 0 0
0 1 1 1 0 1
1 1 1 0 1 1

13.6 Draw a block diagram of a PLA and explain it’s architecture. Write differences between PLA and
PROM. What is the design procedure of a PLA based circuit?
13.7 Design a PLA structure using AND and OR logic for the following functions
F1= m(0,1,8,11,12,15), F2= m(2,3,6,7,8,9,12,13)
F3= m(1,3,7,8,9,11,12,15) and F4= m(0,1,4,8,11,12,15)
13.8 Design a PLA structure to implement NAND, and EXOR functions.
13.9 Design a PLA structure for implementation of following logic functions using PLS100
– – –
F1 = ABC + A CD, F2 = ACD + BC + A D, and F3 = ABC + A CD
13.10 Define PAL. Draw the architecture of PAL and explain it’s operation briefly. Write the difference
between PLA, PROM and a PAL.
13.11 Describe the steps for developing the fuse map for a PAL. Draw the logic diagram to implement
2 - bit comparator using PAL.
13.12 Explain the internal Structure of PAL ICs and explain briefly.
13.13 Design a PAL circuit to implement the following combinational logic functions:
F1=m (1,2,3,5,7,8,10,12,14) and F2=m (7,11,13,14,15)
13.14 Design a 4 bit synchronous binary counter using PAL.
13.15 What is SPLDs and CPLDs? Explain the operation of CPLD with a suitable diagram. Write the
names of CPLD ICs.
13.16 Explain the difference between the followings
(i) PROM and PAL (ii) PROM and PLA (iii) SPLD and CPLD (iv) PAL and PLA
13.17 Write short note on the following
(i) Application of CPLD (ii) Application of FPGA
(iii) Routing of FPGA (iv) Architecture of FPGA
13.18 Design a BCD counter using PLD device.
13.19 Implement the sequential Table 13.1 using suitable PLA device.
13.20 Implement the BCD to Excess-3 code converter using PROM, PLA and PAL.
 CHAPTER

14
COMPUTER AIDED DIGITAL
SYSTEM DESIGN
14.1 INTRODUCTION
Generally, SSI and MSI ICs are used to design small digital system, when circuits are simple. When size
is increased and system becomes very complex, the design feasibility is less using SSI and MSI ICs.
Then some computer added design tools could be used to design. Therefore, computer added design
(CAD) tools are developed to design complex logic circuits and the design work will be much simpler. A
lot of works of the digital system design process can be done automatically in CAD tools and the design
work will be very fast and efficient using these tools. Therefore, Hardware Description Languages
(HDLs) have been developed to explain the complex digital circuits at behavioral, register, and structural
levels modeling of digital circuits using VHDL and to verify logic designs of digital systems through
simulation. Most commonly used HDLs are Very High Speed Integrated Circuit Hardware Description
Languages (VHDL) and Verilog HDLs. In this chapter, the basic operation of VHDL and Verilog HDL
code are incorporated.
14.2 COMPUTER AIDED DIGITAL SYSTEM DESIGN
Generally, the specifications of digital systems in the form of system functions and input-output behaviors
of the system are available before design. The designer initially designs the digital systems with the
help of his design experiences and intuitions. This initial design is actually the general structure of the
intended hardware. Then this design idea passes through different stages before final implementation
using hardware. In all design stages, the designer evaluates and verifies the results. For this, the design
circuit will be tested giving one set of inputs data and the output results must be compared with specified
output. If any error exists in system, the design must be modified to remove errors. The modified design
circuit will be evaluated and also be verified with required results. This procedure will be repeatedly done
until error does not exist in the designed system. If this design process is implemented using hardware
in each stage of design, it is too much time consuming and practically impossible. Therefore, hardware
implementation process is very tedious and the design circuit will be very costly. So COMPUTER
AIDED DESIGN (CAD) tools are developed to make the design process easy and fast. In computer-
aided design of digital systems, the designers simulate the behaviors of a design of digital circuit without
its hardware implementation. After simulation, the simulation results are compared with required results
and check that the design satisfy the required specifications. If the results are not satisfied, the computer-
 Computer Aided Digital System Design 593

aided design of digital systems must be modified

through programming until the satisfied results
are obtained. After design, the developed
software is implemented a desired logic circuit
by using a programmable logic device, such as
complex programmable logic devices (CPLD)
and a field-programmable gate array (FPGA)
chip. Computer aided design process of digital
systems is depicted in Fig.14.1. Computer aided
design steps of any digital system are explained
below.
Design Entry
The desired logic circuit can be specified by
truth table, schematic diagram and hardware
description language. When the truth table of
a digital logic function is specified for design,
the CAD tools convert the truth table into a
network of logic gates. The CAD tools can
also be able to convert timing diagram into a
network of logic gates and the timing diagram
of digital system fed to CAD software through
its waveform editor. The truth table or timing
diagram design entry is used only for simple
digital circuits. The simple digital circuits can
be interconnected by using schematic capture
tool of CAD software to design complex digital
circuits. The schematic diagrams of complicated
digital circuits are drawn using available graphic
editor of CAD software. Hardware Description
Language (HDLs) is used to write programs
with its code for design entry of a digital logic
circuit. The most commonly used hardware
description languages (HDLs) in electronics
industry are Very High Speed integrated Circuit
Hardware description language (VHDL) and
Verilog HDL.
Synthesis Fig. 14.1 Computer aided design process of
The CAD Synthesis tool synthesises the design digital systems
entry of the circuit into a netlist. Actually netlist
is the representation of the digital circuit using all required logic elements namely gates, multiplexer,
demultiplexer, flip-flop, register, counter, read only memory and random access memory etc. and the
connections between the different logic elements so that, a set of logic expressions can be generated
using initial data.
 594 Digital Electronics: Principles and Applications

Functional Simulation
After synthesis, the synthesised circuit can be tested to verify its functional correctness. Therefore, the
functional simulator of CAD tools simulates the circuit function of the logic equations to verify the
functionality of the circuit. The output of the functional simulation can be obtained in the truth table
form or the timing diagram form. So, the truth table and the timing diagram are used to verify whether
the computer aided design circuit is correct or not. When the output does not satisfy the requirement, the
design must be modified through program code and the above process will be done repeatedly until the
desired functional operation is obtained.
Logic Synthesis and Optimisation
After developing the functionally correct design of a digital system, it is required to optimise the design of
the digital circuit. For this logic synthesis and optimisation, tools are used to optimised the digital system
Implementation of Digital system
The next step of ‘logic synthesis and optimisation’ is the implementation of the design of digital system.
The CAD tool determines the placement of all logic elements defined in the netlist into the target chip
CPLD or FPGA. It also determines routing wires in the chip so that all logic elements are connected
properly inside the chip.
Timing Simulation
To obtain the expected performance of the circuit, propagation delays along the different paths in
the circuit are analysed. Then fitted circuit in CPLD or FPGA chip is tested to verify the functional
correctness and timing diagram of digital system. From the timing diagram, the effect of propagation
delays must be studied and it must be verified that the digital system provides the required performance
in terms of propagation delays. Simulation tool is used for timing simulation.
Programming and Configuration
The designed digital circuit is implemented in a CPLD or FPGA chip by programming the configuration
switches which configure the logic elements and set up the required wiring connections in side the chip.

14.3 COMPUTER AIDED DESIGN (CAD) TOOLS

The basic concept computer aided designs of digital systems are explained in previous section. It is
very convenient, accurate, easy and fast to design digital systems through CAD softwares. Therefore,
various CAD tools, namely RHDL, AHDL, EDIF, JHDL, Hyda HDL, Meta HDLs, Verilog HDL,
VHDL, and ABEL Hardware Description Language have been developed to design electronics circuits
and are available in market to use in industry. Actually, CAD tools can help the designers to simulate
the behavior of a design without its hardware implementation. Usually these tools simulate the design,
then simulation results are compared with the design specifications. If the required specifications do
not fulfilled, the design must be modified properly so that the desired results can be obtained from
system. RHDL is stands for Ruby Hardware Description Language. It is an HDL based on the Ruby
programming language. It consists of a set of code libraries just like other HDLs. In RHDL code, blocks
are made to define a domain of this language. RHDL allow modeling at a higher level of abstraction.
AHDL is abreviated Altera Hardware Description Language as it was developed by Altera. It also
stands for Analog Hardware Description Language. It is a descriptive language and is very simple to use
for designing. It can be used as a powerful tool to design digital systems throgh programming any Altera
CPLD and FPGA devices. AHDL program is not a sequential series of instructions, but this is actually
 Computer Aided Digital System Design 595

code description of how output from a device relates to the input of that device. Generally, AHDL code
is generated using any text editor.
EDIF stands for Electronic Design Interchange Format. It has been predominantly used to store electronic
netlists and schematics in Electronic Design Automation (EDA) industry. This CAD tool operates in
neutral format. JHDL is stands for Java Hardware Description Language and it is based on JAVA program.
The digital components and their connections in a digital logic circuit can also be described using this
language. Hydra is an HDL based on the functional programming language Haskell.
VHDL is the VHSIC Hardware Description Language. VHSIC is an abbreviation for Very High
Speed Integrated Circuit. It can describe the behavior and structure of digital logic circuits like ASICs,
CPLDs, FPGAs and conventional digital circuits. The VHDL was developed in 1986 and was published
in IEEE Standard named as VHDL 1076 in 1987 after a lot of modifications. Therefore, VHDL is an
international standard language for designing electronics circuits in EDA industry. A revised standard
IEEE 1164 was published in 1993. This version is also called as VHDL ’93 and this is the most popular
language for electronics circuit designers. VHDL allows the designer to designs digital systems using
top down, bottom up or middle out methodology. VHDL can be used to describe hardware at the gate
level or in a more abstract way. Simulation and synthesis are the two main kinds of tools of VHDL.
Verilog is a Hardware Description Language. In Verilog, HDL text format is used to describe electronic
circuits and systems. Verilog can be used for verification of electronic circuits design through simulation,
and timing analysis.The Verilog HDL is an IEEE standard language and its-number is1364. The IEEE
standard 1364 provides the Programming Language Interface (PLI). This language is a collection of
software routines, which permit a bidirectional interface between Verilog and other languages. The first
IEEE standard Verilog HDL was published in 1995 as IEEE Std. 1364-1995 and its revised version
was also published in 2001 as IEEE Std. 1364–2001. This software tool is now used extensively in
the design of integrated circuits, and any digital systems, such as ASICs, CPLDs, and FPGAs. In this
chapter, most commonly used hardware description languages: VHDL and Verilog HDL are described
with examples.
14.4 HARDWARE DESCRIPTION LANGUAGE (HDL)
The Hardware Description Language (HDL) is a computer programming language used for formal
description of digital logic circuits. They can describe the circuit’s operation, its design and organisation,
and tests to verify its operation by simulation. HDLs are standard text-based expressions of the structure
and behaviour of digital electronic systems. In contrast to any high-level programming language, HDL
syntax and semantics include explicit notations for expressing time and concurrency, which are the
primary attributes of hardware.
The hardware programmed logic for designing digital systems has similarity with the statements
of BASIC or any other high-level computer language. As each step of programmed logic corresponds
to hardware, the programming logic is known as hardware description language. One of the popular
hardware description language is Register Transfer Language (RTL). In this section, RTL hardware
description language is discussed briefly.
HDL is a very convenient tool for describing hardware in which data is transferred from one register
to the other. The notation A←B states that the content of register B is transferred to A register, but the
content of source will not be altered. The length of register can be represented by modification in the
register transfer statement. For example, a 4-bit A register A=A[4], A[3], A[2], A[1] and a 4-bit B register
B=B[4], B[3], B[2], B[1]. Then register transfer statement A ← B means that A[4] ← B[4], A[3] ← B[3],
A[2] ← B[2], and A[1] ← B[1].
 596 Digital Electronics: Principles and Applications

The OR operation and AND operation on the content of B and C registers are represented by A ←
B C and A ← B C respectively. The OR operation between B and C transferred to A is represented
by A ← B C. The notation A ← B C also states that A[4] ← B[4] C[4], A[3] ← B[3] C[3], A[2]
← B[2] C[2], and A[1] ← B[1] C[1]. The notation ‘=’ is used for the connection between register
output signals and output lines. For example, the Z=B states that outputs of register B are connected to
the output vector Z.
In HDL, the branch statements are two types such as conditional and unconditional branch. The
unconditional branch is represented by → (Level), where ‘Level’ is the statement number. For example,
the statement → (5) notation means Go To 5. The conditional branch is represented by (F1, F2, F3….Fn)/
(S1, S2, S3….Sn) where F1, F2, F3….Fn are the logic functions and S1, S2, S3….Sn are statement numbers.
At a time any one of Fi will be true. When F1 is true, then S1 statement will be executed. If F1 is false,
the next statement is executed.
Conditional transfer notation also exists in HDL. The behaviour “ If A>B, then transfer content of A to
B” can be represented by B*GREATER(A:B) ← A. The control section uses the counter to keep track of
counting. The counting will be either up counting or down counting as per requirement. The statements
used for up counting or down counting are COUNT←INC (COUNT) and COUNT←DNC (COUNT). The
declaration statements are used in HDL. The commonly used declaration statements are as follows:
1. MODULE : Name of Digital System
2. INPUTS: A; B
3. MEMORY: A[8]; B[8]
4. OUTPUTS: C[8]; OUT
5. ENDSEQUENCE
6. END
7. BUSES: IBUS[8];
In HDL, there is some provision to develop connections between the bus and register for receiving
data from the bus and sending data on to the bus. The data connected to the bus will be appear on the
bus during the entire clock period. For example, IBUS ← B ^ C states that the result of ANDing of each
bit of registers B and C will be available on the bus during the entire clock period.

Example 14.1 Write a HDL program for the following operations:

Transfer the data existing on B to a register A. The stored data in A is complemented and stored in C register.
The content of C register is shifted into register D. Then register A and register B are to be ANDed and result
is stored in E register. Lastly, shift the content of register E on Z lines.

� Solution
MODULE : DATA TRANSFER
MEMORY: A[4]; B[4]; C[4]; D[4]; E[4]
INPUTS: B[4]
OUTPUTS: Z[4]
1. A←B
2. C ← A–
3. D←C
 Computer Aided Digital System Design 597

4. E ← A B
5. IBUS ← E
6. Z = IBUS
ENDSEQUENCE
END.
14.5 VERY HIGH SPEED INTEGRATED CIRCUIT HARDWARE
DESCRIPTION LANGUAGES (VHDL)
VHDL is a Hardware description Language used for modeling digital circuits from simple gates to
complex systems. This software can be used for simulation and designing digital systems using gates,
combinational logic circuits, flip-flops, counters, RAM and ROMs, and interconnection of components.
VHDL is an abbreviation for VHSIC Hardware description language and VHSIC is an acronym for Very
High Speed Integrated Circuits.
In early 80’s VHDL, software has been developed and it’s roots are in the ADA language. VHDL is
globally accepted by thousands of electronics engineers to design sophisticated electronics products. In
1987 VHDL becomes IEEE standard ‘IEEE-1076’ after number of revisions and modifications. It is a
very powerful language with different operators and numerous language constructs and can be used to
describe very complex behavior of digital systems.
Digital system design using VHDL consists of two design units, namely primary design unit and
secondary design unit. The entity declarations, the package declarations and configuration declarations
are the primary design unit. The secondary design unit is the architecture body and package body, which
are related with the primary design unit. Library is a collection of primary and secondary design units.
VHDL consists of IEEE library, work library, STD library and user library. Any designed digital system
usually contains one or more than one library. In this section a introduction to VHDL’93 software of
IEEE standard 1164 and its application in behavioral, data flow and structural model of digital logic
circuits have been discussed.
14.5.1 Data Objects
There are three types of data objects namely signal, variable, and constant. The data object SIGNAL
represents logic signals on a wire in the circuit. This signal does not have any memory. When source of
the signal is removed, the signal will not have any value. A variable object remembers its content and is
used for computations in a behavioural model. A constant object must be initialized with in a value and this
value cannot be changed with time. The example of signals, variables, and constants are given below:
SIGNAL a: BIT;
VARIABLE b: INTEGER;
CONSTANT one: STD_LOGIC_VECTOR(2 DOWNTO 0) : = “001”;
14.5.2 BIT and BIT VECTOR
The BIT and BIT_VECTOR types are always predefined in VHDL. The values ‘0’ and ‘1’ are used
to represent BIT. Actually, the BIT_VECTOR is a vector of type BIT. The examples of BIT and
BIT_VECTOR types are
SIGNAL a: BIT
SIGNAL b : BIT_VECTOR (7 DOWNTO 0);
a <= ‘0’
b <= ‘00001000”;
 598 Digital Electronics: Principles and Applications

14.5.3 STD_LOGIC and STD_LOGIC _VECTOR

To model a circuit more accurately, STD_LOGIC and STD_LOGIC _VECTOR types give more values
than the BIT type. Objects of these types have the following values given below:
‘0’ - normal 0 ‘Z’ - high impedance
‘1’ - normal 1 ‘-’- don’t care
As STD_LOGIC and STD_LOGIC _VECTOR types are not predefined, the following two library
statements must be included in order to use above types
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
When binary numbers are used for any arithmetic operation, the statement “USE ieee.std_logic_
signed.ALL” is used for signed number arithmetic and the statement “USE ieee.std_logic_unsigned.
ALL” is used for unsigned number arithmetic operation.

14.5.4 Comments and Data Operators

Two consecutive hyphens (--) is treated as comments. The example of comments is
-- Truth table of logic gates
The VHDL built-in operators are listed in Table 14.1.

Table 14.1(a) Logical Operation

Logical Operation Symbol Example
Logical AND AND / && a AND b
Logical NAND NAND a NAND b
Logical OR OR / | | a OR b
Logical NOR NOR a NOR b
Logical XOR XOR a XOR b
Logical XNOR XNOR a XNOR b
Logical NOT NOT / ! NOT b

Table 14.1(b) Bit-wise Logical Operation

Bit-wise Logical Operation Symbol Example
Logical AND & a&b
Logical OR | a|b
Logical XOR ^ a^b
Logical NOT ~ ~a

Table 14.1(c ) Relational Operation

Relational Operation Symbol Example
Equal = a=b
Not equal != a != b
Less than < a<b
Less than or equal <= a <= b
Greater than > a>b
Greater than or equal >= a >= b
 Computer Aided Digital System Design 599

Table 14.1(d ) Arithmetic Operation

Arithmetic Operation Symbol Example
Binary Addition + a+b
Binary Subtraction – a–b
Binary Multiplication * a*b
Binary Division / /b

14.5.5 ENTITY
All digital design must be expressed in terms of ENTITY. The ENTITY in VHDL specifies the name of the
ENTITY and it also refers to any digital device namely AND, NAND, OR, NOR, XOR, XNOR, and NOT
gates, flip-flops, ALU, etc. An ENTITY declaration specifies the name of the entity; the ports of ENTITY and
all ENTITY related operations. Sometimes, digital systems consist of more than one ENTITY.
The keyword ENTITY signifies the starting of an ENTITY statement. Each entity is uniquely assigned a
name and its input and output signals through PORT. Each PORT is associated with the two keywords IN
and OUT to represent input signals and output signals respectively. The following keywords ENTITY,
IS PORT IN, OUT, INOUT and END are used in VHDL code for any design ENTITY. The Syntax of
an ENTITY is as follows
ENTITY entity-name IS
PORT (list of input port names, list of output port names and their types);
END entity-name;
The example of an ENTITY and_gate is given below:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY and_gate IS
PORT (
a: IN std_logic;
b: IN std_logic;
c: IN std_logic;
d: OUT std_logic );
END and_gate;
Here, the name of ENTITY is and_gate. The entity has four ports in the PORT. Three ports are for IN
mode and one port is of OUT mode. The three data input ports (a,b,c) of and_ gate are std_logic type and
the data output port (d) is also std_logic type. Sometimes, bi-directional (INOUT) ports are also used in
an ENTITY. The keyword word END signifies the end of the ENTITY declaration. The symbol colon
(:) is used for separator and the symbol semicolon (;) is used as terminator.

14.5.6 ARCHITECTURE
The ARCHITECTURE describes the actual implementation of the functionality of the ENTITY. It
contains the statements, interconnected components to represent the behaviour of the ENTITY and
the structure of the ENTITY. An ARCHITECTURE is related with the ENTITY and it describes the
behavior of that ENTITY. The syntax for the architecture varies, depending on the model. Generally,
dataflow model, behavioral model and structural model ARCHITECTURE are used in VHDL to design
 600 Digital Electronics: Principles and Applications

digital system. An ARCHITECTURE body has declarative part and statement part. The keywords
ARCHITECTURE, OF, IS, BEGIN and END are used for any ARCHITECTURE body. The syntex of
ARCHITECTURE body is given below:
ARCHITECTURE architecture_name OF entity_name IS
declarations;
BEGIN;
statements;
END architecture_name;
Data Flow Model
In dataflow modeling of ARCHITECTURE, concurrent statements are used and also executed
concurrently. Therefore, the ordering of these statements does not affect on the output. The concurrent
statements are expressed using concurrent signal assignment, conditional signal assignment and selected
signal assignment. The syntax of dataflow model is
ARCHITECTURE architecture-name OF entity-name IS
signal-declarations;
BEGIN
concurrent-statements;
END architecture-name;
Concurrent Signal Assignment
The concurrent signal assignment statement assigns a numeric value. A signal assignment can be
identified by the symbol <=. The syntax of concurrent signal assignment is
signal <= expression;
The above statement means that after evaluating an expression the result will be a signal. This
statement will be executed when input signals of expression changes. The actual assignment of the
value to the signal will be assigned after a propagation delay. The expression may be any arithmetical
expressions and logical expressions.
a <= ‘0’;
c <= a XNOR (NOT b);
Conditional Signal Assignment
The conditional signal assignment statement selects one of the different values to assign to a signal
conditionally. The output signal value changes due to change in input signal values or conditions. The
syntax of conditional signal assignment is
signal <= value1 WHEN condition ELSE
value2 WHEN condition ELSE
………………………
…………………………
and the example of this statement is given below:
SELECT <= input0 WHEN s0= ‘0’AND s1=‘0’ ELSE
input1 WHEN s0= ‘1’AND s1=‘0’ ELSE
input2 WHEN s0= ‘0’AND s1=‘1’ ELSE
input3;
 Computer Aided Digital System Design 601

The signal ‘SELECT’ will get a numeric value assigned to it depending upon the values of s0 and s1.
This statement will be executed whenever the input signals s0 and s1 change. When s0=0 and s1=1, the
SELECT value will be the input2. Therefore, the signal assigned statement is sensitive with s0 and s1.
Selected Signal Assignment
In selected signal assignment statement, signal will get any one of several different values assigned to
it based on the value of a select expression. In this statement, all possible choices for the expression
are incorporated and the keyword OTHERS is used to denote all remaining choices. This statement can
be executed when input signals of the expression changes. The syntax of selected signal assignment
statement is
WITH expression SELECT
signal <= input_1 WHEN valuel,
input_2 WHEN value2
………………….
………………….
input_n WHEN OTHERS;
When the output of expression is equal to value1, input1 is assigned to signal. If the output of
expression is equal to value2, input2 can be assigned to signal. This will be repeated for value3 to
value(n-1). When OTHERS values are generated from expression, input_n will be assigned to signal.
Structural Model
In structural modeling, several components are interconnected with input signals. Therefore, all the
components must be defined in ENTITY and ARCHITECTURE body. The component statement is used
to declare each component, which are used in the netlist. Then the declared components are instantiated
with the actual components in the digital circuit using the PORT MAP statement. After that, signals are
used to connect the components together according to the netlist. The syntax of structure modeling is
ARCHITECTURE architecture-name OF entity-name IS
component-declarations;
signal-declarations;
BEGIN
PORT MAP-statements;
concurrent-statements;
END architecture-name;
Component Declaration
Each COMPONENT declaration statement must be within a ENTITY and an ARCHTECTURE. The
COMPONENT declaration statement declares the name of a component and component interfacing
within netlist of digital circuit. The keywords COMPONENT, IS, PORT, END COMPONENT are used
in COMPONENT declaration. The syntax of COMPONENT is
COMPONENT component-name IS
PORT(Iist of input ports, list of output ports and their types);
END COMPONENT;
and an example of component is
COMPONENT and IS
 602 Digital Electronics: Principles and Applications

PORT (a,b : IN bit;

c: OUT bit );
END COMPONENT;
Port Map
The PORT MAP statement is for a declared component to specify how the component is connected within
the digital circuit. These statements are concurrent statements. The syntax of PORT MAP is
label: component-name PORT MAP(association-list);
The positional method and named method are used in association list. The example of PORT MAP
is given below:
LEVEL: and PORT MAP (a, b, c);
Behavioral Model
In behavioral model, statements are executed sequentially just like high level computer programming
language. The PROCESS statement is the main body of this model. In this model, sequential statements
like sequential statements, variable declarations, if-then-else statements, case, loops, for loop, and
while loop statements are generally used to model the behaviors of digital circuits. The keywords
ARCHITECTURE, OF, IS, BEGIN, PROCESS, and END are incorporated in this model. The syntax of
behavioral model is as follows:
ARCHITECTURE architecture_name OF entity-name IS
signal-declarations;
function-definitions;
procedure definitions;
BEGIN
PROCESS-blocks;
concurrent-statements;
END architecture_name
Process
The PROCESS block contains concurrent statements. When multiple PROCESS blocks exist in an
architecture, all PROCESS blocks will be executed simultaneously. Any PROCESS block also contains
sequential statements, which are executed sequentially. The syntax of PROCESS block is
PROCESS (sensitivity-list)
Variable declarations;
BEGIN
sequential-statements;
END PROCESS
Here, keywords of any PROCESS are PROCESS, BEGIN and END PROCESS. PROCESS is
sensitive with its input signals. The sensitivity list is a comma-separated list of signals. Whenever any
signal in the list changes its value, all statements of PROCESS block will be executed sequentially.
After execution of the last statement, the program will be suspended until a signal in the sensitivity list
changes value for the next time. The example of a PROCESS is given below:
PROCESS (a,b,c)
BEGIN
e<= a OR b OR c;
 Computer Aided Digital System Design 603

END PROCESS;
Variable Declarations
Variables are always declared within a PROCESS. The variable assignment statement assigns a value to
a variable. The result of an expression may also be used to assign a value to a variable. Whenever any
value is assigned to the variables, this statement can be executed. The syntax of variable assignment is
signal:= expression;
and its example is
c := a+b;

Sequential-Statements
In the sequential assignment statement, a value to be assigned to a signal. This statement is expressed
just like concurrent statements but this statement will be executed sequentially. The syntax of sequential
statement is
signal <= expression;
and the example of this statement is
d <= a AND (b AND c);

If Then Else Statements

The example of IF statement is
IF (a = = b) THEN
c: = d;
END IF
The above statement starts with the keyword IF. Then the condition (a = = b) is followed by the
keyword THEN. When the condition is true, the assignment statement (c: = d ;) will be executed. If the
condition is false, no statements are executed as no ELSE clause exist within IF statement. The syntax
of IF THEN ELSE statements are
IF condition THEN
sequential_statements_1;
ELSE
sequential_statements_2;
END IF;
IF condition THEN
sequential_ statements_1;
ELSIF condition2 THEN
sequential _statements_2;
ELSE
sequential_statements_3;
END IF;
Case Statement
The case statement is used whenever a single expression value is used to select any value from multiple
values. The keywords CASE, IS WHEN, WHEN OTHERS, and END CASE are used in case statement.
The syntax of CASE statement is
CASE expression IS
WHEN choices => sequential-statements;
 604 Digital Electronics: Principles and Applications

WHEN choices => sequential-statements;

WHEN OTHERS => sequential-statements;
END CASE;
The case statements consists of the keyword CASE followed by an expression. The output of the
expression returns a value according to the choices in a WHEN statement or WHEN OTHERS statement.
After execution of WHEN statement and WHEN OTHERS statement, the control is transfered to the
statement following the END CASE clause. The example of case statement is
CASE bit_vector IS
WHEN “00” => a <= d0;
WHEN “01” => a <= d1;
WHEN “10” => a <= d2;
WHEN OTHERS => a <= d3;
END CASE;
Loop Statements
The LOOP statement is used when an operation is repeatedly done within a program. FOR, WHILE
and LOOP statements are commonly used for this purpose. The syntax of FOR, WHILE and LOOP
statements are given below:
FOR LOOP
FOR identifier IN start TO stop LOOP
sequential-statements;
END LOOP;
WHILE LOOP
WHILE condition LOOP
sequential-statements;
END LOOP;
LOOP
LOOP
sequential-statements;
EXIT WHEN condition;
END LOOP;

14.5.7 GENERIC
Generics are a general mechanism to pass information into an entity. For example, the values of rise
time and fall time delays may be passed into the entity with generics. Generics of an entity are declared
with the GENERIC keyword before the PORT list declaration for the entity. The syntax of GENERIC
is
ENTITY entity-name IS
GENERIC (identifier: type);
The identifier is used in GENERIC declaration wherever a constant is expected with in entity. It is a
 Computer Aided Digital System Design 605

constant, but this is only a readable data type. An example of GENERIC is illustrated below:
ENTITY and IS
GENERIC (rise, fall: TIME:=10ns);
PORT(a,b: IN bit;
c:OUT bit);
END and
Here, rise and fall time delays of signals are 10ns. This time delay information will be passed into the
entity through GENERIC.

14.5.8 PACKAGE
A PACKAGE provides a mechanism to hold data to be shared among several entites. A PACKAGE
consists of two parts: a package declaration section and a package body section. Generally, the package
declaration and body are stored together in a separate file. This file name must be same as package
name. The package declaration statements may be shared between different entites and also provide the
interface of the package which is visible in entites. The package body specifies the actual behavior of the
package like the architecture of a model. Actually, the package body consists of function declaration and
procedure declarations. The syntax of PACKAGE declaration and PACKAGE BODY are given below:
PACKAGE declaration
PACKAGE package_name IS
type _declarations;
signal _declarations;
variable _declarations;
component _declarations;
function _declarations;
procedure _declarations;
END package_name

PACKAGE BODY
PACKAGE BODY package_name IS
function _declarations;
procedure _declarations;
END package_name

Example 14.2 Write entity declaration and architecture body of AND gate and draw the timing
diagram.

� Solution
The and_2.vhd file shows the entity declaration and architecture body of two input AND gate. In this file
architecture body uses PROCESS and IF–THEN-ELSE statements to express AND logic. In the and_2a.vhd
file, the alternative architecture body of AND gate is expressed by the expression c<=a AND b. Figure 14.2
shows the simulation result of AND gate with input signals a, b and output signal, c. It is depicted in Fig.
14.2 that inputs are a=1 and b=1 at time 18.75ns and output c is equal to 1.
606 Digital Electronics: Principles and Applications

Fig. 14.2 Simulation results of two input AND gate

 Computer Aided Digital System Design 607

Example 14.3 Write entity declaration and architecture body of two input OR gate and draw the
timing diagram.

� Solution
The entity declaration and architecture body of two input OR gate are depicted in OR_2.vhd file and OR_
2a.vhd file. In OR_2.vhd file architecture body uses PROCESS and IF –THEN-ELSE statements to express
OR logic. The alternative architecture body of OR gate is represented in the OR_2a.vhd file. The simulation
results of OR gate with input signals a, b and output signal, c are illustrated in Fig.14.3.
608 Digital Electronics: Principles and Applications

Fig. 14.3 Simulation results of two input OR gate

Example 14.4 Write entity declaration and architecture body of NAND gate and draw the
simulation-timing diagram.

� Solution
The NAND_2 shows the entity declaration and architecture body of two input NAND gate. In this file,
architecture body uses PROCESS and IF –THEN-ELSE statements to express NAND logic. The simulation
results with input signals a, b and output signal, c are depicted in Fig.14.4.

Fig. 14.4 Simulation results of two input NAND gate

 Computer Aided Digital System Design 609

Example 14.5 Write entity declaration and architecture body of NOR, XOR, and XNOR gates and
draw their simulation timing diagrams.

� Solution
The NOR_2, XOR_2 and XNOR_2 file show the entity declaration and architecture body of two input NOR,
XOR, and XNOR gates respectively. Here, PROCESS and IF –THEN-ELSE statements are used to express
the architecture body of NOR, XOR, and XNOR gates. The simulation results of NOR, XOR, and XNOR
gates with input signals a, b and output signal c are shown in Fig.14.5, Fig.14.6 and Fig.14.7 respectively.

Fig. 14.5 Simulation results of two input NOR gate

610 Digital Electronics: Principles and Applications
 Computer Aided Digital System Design 611

Fig. 14.6 Simulation results of two input XOR gate

Fig. 14.7 Simulation results of two input XNOR gate

 612 Digital Electronics: Principles and Applications

Example 14.6 Write entity declaration and architecture body to implement the following
combination logic expressions
x = f1(a,b,c,d )= ab+cd
y = f2(a,b,c,d )=abc+da–
and z = f3(a,b,c,d )=ac– + bd using VHDL code.

� Solution
The entity declaration and architecture body to implement the combination logic expressions x = f1(a,b,c,d )
= ab + cd; y = f2(a,b,c,d )=abc + da–; and z = f3(a,b,c,d ) = ac– + bd are given in Comb_logic. Figure 14.8 shows
the logic circuit diagram and the simulation results with input signals a, b, c, d and output signals x, y, z are
shown in Fig. 14.9.

Fig. 14.8 Logic circuit of f1(a,b,c,d)= ab+cd , y = f2(a,b,c,d)=abc + da– , and z = f3(a,b,c,d)=ac–+bd
 Computer Aided Digital System Design 613

Fig. 14.9 Simulation results of combination logic expressions

Example 14.7 Write the structural modeling of Fig.14. 10 in VHDL.

� Solution
The entity declaration and architecture body using structural modeling of Fig.14.10 are given below.
COMPONENT and PORT MAP declarations are used to implement the structural modeling of Fig.14.10 .
ENTITY fig_14.10model IS
PORT ( a, b, c, d: IN std_logic;
o1: OUT std_logic);
END fig_14.10model;
ARCHITECTURE structural OF fig_14.10model IS
COMPONENT and2
PORT (x, y: IN std_logic;
z: OUT std_logic);
END COMPONENT;
COMPONENT or2
PORT ( p, q: IN std_logic;
r: OUT std_logic);
END COMPONENT;
SIGNAL s1, s2: std_logic; Fig. 14.10
BEGIN
A1: and2 PORT MAP (a, b, s1);
A2: and2 PORT MAP (c, d, s2);
A3: or2 PORT MAP (s1, s2, o1);
END structural;

Example 14.8 Write the VHDL code for a 4:1 multiplexer and draw its timing diagram.

� Solution
The mux_4_to_1.vhd shows the VHDL code of a 4:1 multiplexer. This multiplexer has four input signals:
input_0, input_1, input_2, and input_3 which are 4-bit data; one two bit select input, s and a 4 –bit data
output signal. In ENTITY std_logic_vector (3 DOWNTO 0) represents 4 –bit data bus and std_logic_vector
614 Digital Electronics: Principles and Applications

(1 DOWNTO 0) also represents 2 –bit select input bus. PROCESS and CASE statements are used to express
the architecture body of multiplexer to select a particular input from four inputs based on select signal. When
select input s =00, output will be equal to input_0. If select input s =11, output will be equal to input_3.
Figure 14.11 shows the timing diagram of 4:1 multiplexer. From 0 to 4 ns, select input is 11. Then input_3
will be selected for output and output is equal to 1111. During 4ns to 10ns, select input is 10 and output is
equal input_2 as depicted in simulation result. The logic diagram of 4:1 multiplexer in netlist form is shown
in Fig. 14.12.

Fig. 14.11 Simulation results of 4:1 multiplexer

 Computer Aided Digital System Design 615

Fig. 14.12 Logic diagram of 4:1 multiplexer

Example 14.9 Write the VHDL code for a 2:4 decoder.

� Solution
The entity declaration and architecture body of a 2:4 decode is given in decoder_2_4. At this
time, the decode architecture body uses PROCESS and CASE statements to express decoder
logic. When input signal, i = 00, output will be 0001. This is expressed by the expression.
WHEN “00” => O = “0001”; with in PROCESS statement.
 616 Digital Electronics: Principles and Applications

Example 14.10 Write the VHDL code for a D flip-flop with level triggered and edge triggered.
� Solution
The entity declaration and archi-
tecture body of a level triggered
D flip-flop is illustrated in D_
flip_flop.vhd. To check the level
change, enable signal is used in Fig. 14.13 Logic diagram of level triggered D flip flop
the sensitivity list of PROCESS statement. When enable =1, data output will be equal to data input. This is
expressed by the VHDL code
IF (enable=‘1’) THEN
data_output<=data_input; Figure.14.13 shows the level triggered D flip-flop.
 Computer Aided Digital System Design 617

The D_flip_flop_clock.vhd file shows the entity declaration and architecture body of a positive edge triggered
D flip-flop. Attribute ‘event is used to determine clock edges. By checking the clock signal has a particular
value, and if the clock signal has instantly changed, it can be expressed that an edge has occurred on the
clock signal. In edge triggered D flip-flop, the clock is used to transfer the input data to the output terminal,
on the rising edge of clock. To detect the rising or positive edge of clock input, ‘event is used in architecture
body of flip-flop. When the
value of clock is ‘1’ and the
value just changed, a positive
edge will be obtained. Then
output will be equal to input data
as shown in D_flip_flop_clock.
vhd. The logic symbol of edge
triggered D flip-flop is depicted Fig. 14.14 Logic diagram of edge triggered D flip flop
in Fig.14.14.

Example 14.11 Write the VHDL code for a ALU to perform logical operations: AND & OR and
arithmetic operations: addition and subtraction.

� Solution
The alu.vhd represents the entity declaration and architecture body of ALU to perform logical operations:
AND and OR and arithmetic operations: addition and subtraction. The input signals, a, b are 4 bit data
bus, selection input signal is two bit and output signal, result is 4 bit. PROCESS and CASE statements
are used for modeling of ALU. When selection input is equal to 00, result will be the output of a AND b.
If selection value is 10, result will be the addition of a and b. Depending upon the selection input result
will be any one output of the following operations: a AND b, a OR b, a + b and a − b. Figure.14.15
shows the logic diagram of ALU.
618 Digital Electronics: Principles and Applications

Fig. 14.15 Logic diagram of ALU

 Computer Aided Digital System Design 619

Example 14.12 Write the VHDL code for a comparator

� Solution
The VHDL code for a comparator is given in comparator.vhd. This comparator compares two 4-bit numbers
‘a’ and ‘b’ and generates three outputs less, equal and greater after comparison. If number a is greater than
number b, output will be greater =1, less = 0 , and equal = 0. Similarly, if a equal to b , output will be equal =
1, less = 0, and greater = 0. But, if the above two conditions are not satisfied, output will be less = 1 , equal =
0, and greater = 0. Figure.14.16 shows the logic diagram of the comparator and its timing diagram is depicted
in Fig. 14.17. It it clear from the timing diagram that the value of a is 1111, the value of b is1101 during 0 to
5ns and the output of comparator is less = 0 , equal = 0, greater = 1. Similarly, the other comparator results
can also be verified from Fig. 14.17.

Fig. 14.16 Logic diagram of ALU

 620 Digital Electronics: Principles and Applications

Fig. 14.17 Simulation results of 4:1 multiplexer

Example 14.13 Write the VHDL code for a JK flip-flop.

� Solution
The entity declaration and architecture body of JK flip-flop are illustrated in JK_flip_flop.vhd. The inputs of
–
JK flip-flop are J, K, CLOCK and RESET and output signals are Q and Q_BAR (Q ). The function of JK flip-
flop is logically represented by PROCESS and CASE statements in architecture body of JK_flip_flop.vhd.
Two intermediate signals,
output_state and ‘i’ are also
used in architecture body.
The ‘i’ is assigned for two
input signals J and K and it
is expressed by i <=J&K;.
When RESET=1, output_
state is 0. Attribute rising_
edge (CLOCK) is used to
detect the positive edge of
input CLOCK pulse. After
detection the positive edge
of CLOCK, the value of
output_state will be 1 or 0
or not output_state depend-
ing upon the J and K input
signals. This is modeled by
CASE statement as shown
in JK_flip_flop.vhd. Then
output of JK flip flop can be
obtained from the follow-
ing statements: Q<=output_
state and Q_BAR<= NOT
output_state. Figure 14.18
shows the timing diagram
of JK flip-flop and logic
diagram of JK flip-flop is
depicted in Fig. 14.19.
 Computer Aided Digital System Design 621

Fig. 14.18 Simulation results of JK flip-flop

Fig. 14.19 Logic diagram of JK flip-flop

Example 14.14 Write the VHDL code for a Tristate_buffer_register

� Solution
Tri-state (high impedance Z ) is often used in buses of microprocessors and microcomputers. The value ‘Z’ is
assigned to out signal of tri-state output. The entity declaration and architecture body of Tri-state buffer regis-
ter are given in Tristate_buffer_regis-
ter.vhd. The input signals of Tri-state
buffer register are 8-bit data input,
and enable and data output signal is
data_output. The architecture of Tri-
state buffer register is logically rep-
resented by PROCESS statements.
The data_output depend on the status
of enable input signal. When enable
input signal =1, data_output will be
data_input. If enable input signal is
at logic level 0, data output will be
high impedance state (Z ). The logic
diagram of Tri-state buffer register is
depicted in Fig. 14.20.
 622 Digital Electronics: Principles and Applications

Fig. 14.20(a)

Fig. 14.20 (b) Logic diagram of Tristate_buffer_register

Example 14.15 Write entity declaration and architecture of four bit register.

� Solution
The Four_bit_register.vhd file shows the entity declaration and architecture of a four bit register. In Four_
bit_register.vhd file, architecture body uses PROCESS and IF–THEN-ELSE statements to express the
function of register. The input signals of PROCESS are data_input, clock, load and clear. Q_temp is also
 Computer Aided Digital System Design 623

a four-bit vector signal which is assigned in architecture of register. The process variable is function of all
input signals. The output signal is Q which is four-bit vector output Q[0] to Q[3]. If clear input is 0, Q_temp
becomes 0. When clock=1 and detect the positive edge of clock input represented by clock’ event. If load=1
then data_input will be fed to Q_temp. After completion of process, the content of Q_temp will be output at
Q. Figure 14.21 shows the logic diagram of four bit register.

Fig. 14.21 Logic diagram of four bit shift register

 624 Digital Electronics: Principles and Applications

Example 14.16 Write the VHDL code for a four bit shift register.

� Solution
The entity declaration and architecture body of four bit shift register are given in Four_bit_shift_ register.
vhd. The inputs of shift register are data_input, clock, shift and data output signal is Q. The architecture
of shift register is logically represented by PROCESS statements. The data output signal Q depend on the
status of shift input signal. When shift input signal=1, clock=1 and positive edge of clock is detected, data
input signal is shifted through Q_temp[3] to Q_temp[0]. At end of process for each positive edge triggered
clock pulse, the content of Q_temp[0] is output at Q. The logic diagram of four bit shift register is depicted
in Fig. 14.22.
 Computer Aided Digital System Design 625

Fig. 14.22 (a) and (b) Logic diagram of four bit shift register
 626 Digital Electronics: Principles and Applications

Example 14.17 Write the VHDL code for a four bit counter

� Solution
The VHDL code for a four bit counter is given in Four_bit_binary_counter.vhd. There are three inputs
clock, clear, count and an output vector Q[3]…Q[0]. Q_temp is an logic vector signal which is assigned in
architecture of counter. If clear=1, Q_temp becomes 0 as Q_temp = Q_temp - Q_temp. Hence, the counter
is reset at 0000. When clock be applied and at positive edge triggered of each clock pulse, the counter is
incremented by 1 as Q_temp = Q_temp +1 and Q_temp becomes 0001 after first clock pulse. At end of
process, during first clock pulse, output Q will be Q_temp. The logic diagram of four bit counter is depicted
in Fig. 14.23.
 Computer Aided Digital System Design 627

Fig. 14.23 (a) and (b) Logic diagram of four bit counter

Example 14.18 Write the VHDL code for parity generator

� Solution
The Parity function can be built from XOR gates. Assume a, b, c and d are four input signals and parity
generator output is p. The VHDL code for parity generator is given in Parity.vhd. The intermediate signals
x and y are used in parity generator. The signal x is generated from the XOR operation of a and b, but y is
generated after XOR operation of x and c. Then parity p is generated from XOR operation of y and d. Figure
14.24 shows the schematic logic diagram of parity generator.
 628 Digital Electronics: Principles and Applications

Fig. 14.24 Logic diagram of parity generator with four bit inputs

Example 14.19 Write the VHDL code for 8 × 8 ROM array.

� Solution
The VHDL code for 8 × 8
ROM array is illustrated
in ROM.vhd. The inputs
of ROM array are clock,
read, reset, and enable.
Address is three bit vec-
tor input to locate ROM
address from 0 to 7 and
data_output is eight bit vec-
tor outputs. The ROM array
has eight different locations
and eight bit data is stored
in each memory location.
The content of memory lo-
cations 0 to 5 are 00000001,
00000010, 00000100,
00001000, 00010000 re-
spectively and the content
of other memory locations
are ‘11111111’. When en-
able = 1, read = 1 and pos-
itive edge triggered clock
pulse is applied, the data
output will be the content
of memory location speci-
fied by address inputs. For
any other conditions, data
output is ‘ZZZZZZZZ’.
The logic diagram of 8 ×
8 ROM array is depicted
in Fig. 14.25.
 Computer Aided Digital System Design 629

Fig. 14.25 Logic diagram of 8 × 8 ROM array

14.6 VERILOG HDL

Verilog is a hardware description language and it is simpler than very high-speed integrated circuit
hardware description language, VHDL. Similar to entity of VHDL, Verilog HDL models are represented
as module. The keywords module, input, output, inout, end module are used in module body. input,
output, and inout are used for scalar or vector input ports and the port size is a range from [msb : lsb]
(most significant bit to least significant bit). The syntax of module body is
module module_name (list of input variables, list of output variables);
input input_1 , input_2, ….input_n;
output output_1, output_2, …output_n;
endmodule
 630 Digital Electronics: Principles and Applications

The example of and_gate module is as follows

module and_gate(a,b,c,d);
input a,b,c;
output d;
and (d,a,b,c);
endmodule
In this module, a,b,c are input variables of AND gate and output is d. The three input AND gate is
expressed as and(d,a,b,c);. Here, semicolon is used to end of statement. It may be noted that endmodule
does not end with semicolon. Similar to AND gate, Verilog can also be able to support predefined gates
namely or, nor, xor, xnor and not with different input and output signals.
To describe the functionality of a digital circuit, the module body can be written in three different
ways namely structure model, dataflow model and behavior model in Verilog HDL. The structure model,
dataflow model and behavior model of digital circuits are explained briefly in this section.
14.6.1 Structure Model
It is a gate level modeling or component level modeling. The interconnected variable wire is used to
interconnect components in the circuit. The example of structure model of combination logic is given
below
module com_logic(a,b,c,d,e);
input (a, b, c, d );
output (e);
wire gate1, gate2;
and (gate1,a,b)
nand (gate2,c,d );
or gate3(e, gate1, gate2)
Fig. 14.26
endmodule
Figure.14.26 shows the logic diagram of com_logic. The
gate level modeling takes more space to describe digital logic circuit. Therefore, dataflow model and
behavior model are generally used to design complex digital logic circuits.

14.6.2 Data Flow Model

In data flow modeling, the keyword assign is used to explain the behavior of a digital circuit in Verilog
HDL code. All assign statement are concurrent. Therefore, these statements are executed concurrently
and their appearance in program sequentially or at random do not effect on the end result. Actually, data
flow model expressed as Boolean logic equations. In this modeling, a set of operators is used to express
Boolean expressions. Table 14.1 which is given in Section 14.5.4 can also be used for Verilog HDL
code. The syntax of assign is
assign data_ame=expression;.
 Computer Aided Digital System Design 631

The Boolean logic expression, x= ab+c can be represented by assign declaration as given below:
assign x= (a&b)|c);
In data flow model, assign keyword can also be represented in the form of
assign x=s?a:b;
The above statement means that x is equal to a, when S=0. If x is equal to b, s will be 1. Another
example is that the output (b) is invert of input (a). The invert operation can be expressed as assign
b=!a; and the complete module of invert circuit is
module invert_ckt(a,b);
input a;
output b;
assign b=!a;
endmodule.
The data flow model of Fig. 14.20 can be written as
module com_logic(a,b,c,d,e);
input(a, b, c, d );
output(e);
assign e= ((a&b)| (c&d ));
endmodule

14.6.3 Behavior Model

In behavioral model, statements are executed sequentially like behavior model of VHDL. The keywords
always, if-then elese, case, posedge, negedge and initial are generally used in this model of Verilog
HDL code. The syntax of always statement is
always @(sensitivity list)
and an example is always @(a or b or c or d ).
This statement will be executed whenever any variable within sensitivity list changes its values. The
procedure statements and output variables are existing within always.
The syntax of if –then- else and case statement are given below:
if –then- else statements case statements
if(a==1) x=d0; case (a)
else x=d1; 0: x = d0
1: x = d1
end case
if (a<b) x = 4’b0010; case ({a,b})
else if(a>b) x = 4’b1010; 0: x = d0
else x = 4’b0000; 1: x = d1
2: x = d2
3: x = d3
endcase
 632 Digital Electronics: Principles and Applications

The keyword psedge and needge are used for positive and negative edge triggering. The key word
reg is used to hold the value of a data object. The keyword initial ensures sequential execution of
Verilog HDL code. The syntax of initial is
initial
begin
statement_1;
statement_1;
…….
…….
statement_n;
end

Example 14.20 Write the structural mode of three inputs AND gate in Verilog HDL and draw its
timing diagram.

� Solution
The and_3.v shows the Verilog code of three inputs
AND gate. The input signals of AND gate are a,
b, c and output is x. In Verilog HDL, three input
and gate is expressed as and(x,a,b,c). Figure 14.27
shows the logic symbol of three input AND gate Fig. 14.27 Logic symbol three inputs AND gate
and it’s timing diagram is depicted in Fig. 14.28. At
time 9.81ns, a = 0, b = 1, c = 0 and output x = 0. The
result of AND gate at any instant between 0 to 20ns, can be verified from timing diagram.

Fig. 14.28 Simulation results of three inputs AND gate

 Computer Aided Digital System Design 633

Example 14.21 Write the Verilog structural code to perform the following operations as given
below:
— —— ——
o1 = ab, o2 = a + b, o3 = a  b, o4 = a  b, o5 = a–
� Solution
— —— ——
The Verilog code for performing o1 = ab, o2 = a + b, o3 = a  b, o4 = a b, o5 = a– operations is given in gates.v.
Here, a and b are inputs and outputs are o1 , o2 , o3, o4, and o5. The nand, nor , xor, and xnor operations of two
binary input signals a, b are expressed as nand(o1,a,b), nor(o2,a,b), xor(o3,a,b), xnor(o4,a,b) respectively.
To get invert of a, not(o5,a) is used. The logic circuit of gates.v is depicted in Fig. 14.29.

Fig. 14.29 Logic circuit of gates.v

Example 14.22 Write the Verilog structural code for Fig. 14.30.

� Solution
The Verilog code for Fig. 14.30 can be written as given in logic_ckt.v. The above logic circuit has four
inputs a, b, c. d and three outputs o1, o2, o3. In this code, two intermediate variables gate1 and gate2 are
used to represent output of and gate and or gate respectively through keyword wire. The output o1, o2,
and o3 are obtained from the following expressions: xnor(o1,gate1,d); nand(o2,a,gate2); and xor(o3,ab,c);
respectively.
634 Digital Electronics: Principles and Applications

Fig. 14.30

Example 14.23 Write the data flow model of Fig. 14.31 using Verilog HDL code.

Fig. 14.31
 Computer Aided Digital System Design 635

� Solution
The data flow model of Fig. 14.31 is illustrated in Fig_14_25.v. The simplified logic equations of Fig.14.30
are x = ab + cd and y = (a + b) (c + d ). Using assign statements, these boolean logic equations can be expressed
as assign x=(a|b)| (c&d ); and assign y=(a|b)&(c|d ); .

Example 14.24 Write the Verilog code to design a 4 to 1 multiplexer using behavioral model.

� Solution
The mux4_to_1.v represents the Verilog code of 4:1 multiplexer. In behavioral model of multiplexer, always
and case declarations are used. There are two select inputs a, b and four input data d 0, d 1, d 2, d 3 and one
output x. When a = 1,b = 1 output x = d 3. Similarly, the other three combinations of a and b can be evaluated
and output x must be assigned any value of d 0,d 1,and d 2 depending upon the values of a and b. Using
case({a,b}) statement, all four combinations are generated and accordingly output x is evaluated. Figure
14.32 shows the logic diagram of multiplexer and its timing diagram is given in Fig. 14.33.
 636 Digital Electronics: Principles and Applications

Fig.14.32 Logic symbol of 4 to 1 multiplexer

Fig.14.33 Simulation results of 4 to 1 multiplexer

Example 14.25 Design a 1:4 demultiplexer using Verilog HDL.

� Solution
The verilog code of 1:4 demultiplexer is given in demux_1_to_4.v. The select signal is a input vector[1:0]
and output x is also vector form [3:0]. Case({select}) statement generates four combinations 0, 1, 2, and 3.
When select=11 or 3, output will be 1000. Similarly, x will be evaluated for the other three combinations
of a and b. Figure 14.34 shows the logic diagram of 1 to 4 demultiplexer and simulation results of 1 to 4
demultiplexer is depicted in Fig. 14.35.
 Computer Aided Digital System Design 637

Fig. 14.34 Logic symbol of 1 to 4 demultiplexer

Fig. 14.35 Simulation results of 1 to 4 demultiplexer

Example 14.26 Write the Verilog HDL code for a full adder and the timing diagram of full adder.

� Solution
The Verilog HDL code of a full adder is given in full_adder.v. In a full adder, two binary input, data a and
b, can be added with the carry input signal, c. The sum and carry are the output of full adder and they can
be expressed as sum = a⊕b⊕c and carry = ab+bc+ac. Using assign statements, the Boolean logic equations
for sum and carry can be written as assign Carry=(a&b)|(b&c)|(c&a); and assign sum=a^b^c; respectively.
Figure.14.36 shows the logic diagram of full adder and simulation result is shown in Fig. 14.37.
 638 Digital Electronics: Principles and Applications

Fig. 14.36 Logic circuit of full adder

Fig. 14.37 Simulation results of full adder

Example 14.27 Write the VHDL code for a edge triggered D flip-flop.

� Solution
The d_flip_flop_clock.v verilog code describes a D flip-flop with positive edge triggered. The keyword
always is used in this flip-flop circuit. On positive edge of each clock pulse, the input data of D flip flop can
be transferred to the output terminal. If the value of clock, c is ‘1’ and the value just changed, a positive edge
 Computer Aided Digital System Design 639

will be obtained. At that time, output will be equal to input data. To detect the rising or positive edge of clock
input, always @ (posedge c) is used in module body of flip-flop The logic symbol of positive edge triggered
D flip-flop is depicted in Fig. 14.38 and the simulation result of D flip flop is given in Fig. 14.39.

Fig. 14.38 Logic symbol of edge triggered flip-flop

Fig. 14.39 Simulation results of edge triggered flip-flop

SUMMARY
In this chapter, the basic concept of computer aided design of digital systems are discussed. It is very convenient,
accurate, easy and fast to design digital systems using CAD tools. Therefore, various computer aided design (CAD)
tools are developed. Commonly used CAD tools are RHDL, AHDL, EDIF, JHDL, Hyda HDL, Meta HDLs, Verilog
HDL, VHDL, and ABEL Hardware Description Languages. Presently, VHDL and Verilog HDL computer aided
design software are widely used in industry to design complex digital logic circuits. The VHSIC Hardware Description
Language (VHDL) is an industry standard language used to describe hardware most appropriately. A basic introduction
to VHDL and how it can be used to model the behavior of devices and design of digital systems has been explained
in this chapter. Verilog is a hardware description language and it is simpler than VHDL. A very brief introduction to
Verilog HDL has been incorporated in this chapter. The examples of structure model, data flow model, and behavior
model of VHDL and Verilog HDL are also discussed in this chapter.
 640 Digital Electronics: Principles and Applications

MULTIPLE CHOICE QUESTIONS

1. CAD tools is used to
(a) Simulate logic system (c) Chip level design of logic circuit
(b) Implement logic circuit (d) None of these
2. VHDL is
(a) VHSIC hardware description language (c) HSIC hardware description language
(b) IC hardware description language (d) None of these
3. VHDL is used to design
(a) ASICs (b) PAL (c) CPLD (d) None of these
4. The syntax of an entity is
(a) ENTITY entity_name IS (c) ENTITY entity_name IS
PORT(); PORT();
END entity_name; END ;
(b) ENTITY entity_name IS (d) ENTITY entity_name
END entity_name; PORT();
END entity_name;
5. Architectute of digital circuit using VHDL and Verilog HDL are of
(a) Two types (b) Three types (c) Four types (d) None of these
6. Component declaration is used in
(a) Structure model (b) Data flow model (c) Behavior model (d) None of these
7. PROCESS statement is used in
(a) Structure model (b) Data flow model (c) Behavior model (d) None of these
8. Verilog is
(a) A hardware description language (c) Is more complex than VHDL
(b) The another name of VHDL (d) None of these
9. assign statement is used in
(a) Structure model (b) Data flow model (c) Behavior model (d) None of these
10. Concurrent statements are executed
(a) Sequentially (c) Concurrently
(b) Sequentially and concurrently (d) None of these

REVIEW QUESTIONS
14.1 Explain computer aided design process of digital systems. What are the advantages of CAD design?
What are the CAD tools are used in digital system design?.
14.2 Explain data flow modeling of VHDL ARCHITECTUTE with an example.
14.3 Write the entity declaration of three input AND, OR, and XNOR gates in VHDL.
14.4 Write a VHDL code to design a 8:1 multiplexer.
14.5 Write VHDL codes for
(a) 1:8 demultiplexer
(b) Full adder
(c) Flip flop with level triggered
(d) 4 bit register
 Computer Aided Digital System Design 641

14.6 Explain structure modeling of VHDL ARCHITECTUTE with an example.

14.7 What are the types of model of Verilog HDL? Explain any one modeling with an example.
14.8 Write a Verilog HDL code for a 4:1 multiplexer and draw the timing diagram.
14.9 Write a Verilog HDL codes for
(a) 2 : 4 decoder
(b) Full adder
(c) Flip flop with level triggered
(d) 2 bit register
14.10 A combinational circuit is defined by the equations
–
F1 = AB+ABC
F2 = A+B+C
– –
F3 = AB+AB
Write VHDL code for above equations.
14.11 Write VHDL codes to implement the following logic equations
–
F1 = ABC + ABC
F2 = A + B + C + D
F3 = A + B + CD + AD
– –
F4 = A C D + ACD + BCD + BCD
14.12 Write VHDL codes to implement the following 3-variable Boolean functions
F1 = Σ 0,2,3,5,7, control variables A and B
F2 = Σ 1,3,4,6,7, control variables B and C Table 14.2 Truth table

F3 = Σ 0,2,4,5,6,7, control variables A and C. Inputs Outputs

F0 F1 F2 F3 A B
14.13 Write a program to implement the truth Table 14.2.
14.14 Write VHDL code of Fig. 14.40. 0 0 0 0 0 0
1 0 0 0 0 0
0 1 0 0 0 1
0 0 1 0 1 0
0 0 0 1 1 1

Fig. 14.40
 642 Digital Electronics: Principles and Applications

14.15 Write Verilog HDL code of Fig. 14.41.

Fig. 14.41
 CHAPTER

15
LABORATORY EXPERIMENTS
15.1 INTRODUCTION
Laboratory experiments on digital electronics help the students to improve the concept of digital electronics
principles and their applications. It is also helpful to develop skill for connecting electronics components to
construct electronics circuits and checking their performance. In most cases it is found that the laboratories
utilise the commercial experiment kits for learning concept skill and process. Some digital kits are already
available in the market, but they are not being able to fulfill all requirements. Therefore, it is required to
design experiments in such a way that students can measure the desired performance of all electronics
components, which are used in electronic circuits. Figure 15.1 shows the flow chart for developing any
experiment. Generally, the following steps are followed for designing experiments:
• Choose a title of experiment from the course content of digital electronics.
• Analyse the experiment on the basis of concept, skill and process.
• Write the aim and objectives of the experiment.
• Design the circuits for experimentation unit.
• Select suitable values of the components, measuring devices, controlling devices and power sup-
ply for constructing the experimental circuits.
• Perform experiment for measuring correct result.
• Prepare the tables for data entry.
• Supply usable formula for the calculation of final result.
While designing the experimental unit, the following points are to be considered.
• Easy method of transferring concept.
• Easy method of implementation process learning.
• Easy method of practicing skills.
• Performing experiments within optimum time.
• Must not contain any distracting element.
• Proper selection of positions of the probing or observing points.
• Determine the prime parameter, which is to be measured.
• Easy to handle by both students and teachers.
• Proper labeling is required in the layout of the experimentation unit.
• Connections must be firm.
• Must contain the trouble-shooting manual.
• Must have ready stocks of spares.
• The cost of production of the experimentation unit must not exceed the same for commercial product.
• Must be better in performance in respect of the objective of the experiments.
 644 Digital Electronics: Principles and Applications

Fig. 15.1 Flow chart for developing the experimental unit

15.2 DEVELOPMENT OF INSTRUCTION MANUAL FOR

LABORATORY EXPERIMENTS
Laboratory instructions provide detailed informations of early experiments that will be used in later labs;
consequently, they are very valuable tool. Laboratory instruction contains information in draft form, written
while performing an experiment that will be used later to complete results and reports. This offers the
opportunity to draft procedures and draw wiring diagrams, which can be corrected prior to submitting final
diagrams. The following suggestions are made for the preparation of the Laboratory instruction although
it should be obvious that all of the sections below will not be required in a particular report. Specific
information relating to the requirements will be provided to students in the beginning of the laboratory
session. Figure 15.2 shows the flow chart for developing the instruction manual of any experiment.
Laboratory instruction should be complete in the sense that all required information to reproduce the
experiment is contained within it. The brief outlines of Laboratory instruction are as follows:
 Laboratory Experiments 645

• Title Page • Title Of The Experiment

• Aim Of The Experiment • Objectives Of The Experiment
• Theory • Instruments/Equipment Used
• Procedure • Precautions
• Observations • Sample Calculation
• Results and Discussions • Conclusion
• Objective-type/Short Answer-type Test Questions
• Reference
Title Page Every report must have a title page that identifies the experiment name and number, the
student’s name and student roll number, the date of performing experiment and the date of submission.
Title of the Experiment It must carry the theme of the experiment in the shortest possible
words.
Aim of the Experiment The aim of the experiment should be written in few words. It should
include the statements finally determined in a test or experiment.
Objectives of the Experiment The objectives of the experiment to be achieved by students
during testing/experimentation must be written briefly. The learning objectives to be accomplished by
the experiment.
Theory Theoretical background of the experiment includes fundamental principles, the basic for-
mula to be expressed along with the meaning of symbols and units, and definition of relevant terms. It
should be recorded here that there is absolutely no scope for the derivation of the formula in a laboratory
experiment.
Instruments/Equipment Used List of instruments/equipments used during the test / experi-
ment with specifications as far as applicable should be incorporated in Laboratory instruction.
Procedure The procedure will not be required in every instance but where it is required, we must
state it as concisely as possible, giving only the important features of the procedure that was followed
in conducting the experiment. In this section, we should present the method and steps taken to build the
circuit for demonstration purposes. All deviations from the written experimental procedure should be
carefully documented as this could affect results and will need to be discussed.
a) A standard procedure is to be followed, using codes of practice.
b) The procedure should be written down in the form of instruction using appropriate action verbs in
the beginning of a sentence, briefly, clearly and sequentially.
Precautions In all laboratory experiments, precautions are one of the very important matters to
be followed side by side with steps of procedure. In some of the experiments, measures of precautions
are so vital that without precautions some procedural steps are found to be prone to accidents. Students
are always advised to follow precautions. Students must be well informed about precautions to be taken
during the period of experiments and warned that “Not taking precautions while testing” should be
considered as a serious offence.
 646 Digital Electronics: Principles and Applications

Observations An appropriate observation table is to be prepared as per requirement of the experi-

ment. Columns in the observation table must have their proper symbols and carefully recorded observa-
tions are to be filled up in this table.
Sample Calculation A few sample calculations are to be presented in Laboratory instruction so
that students can be able to use observed data applied in mathematical and logical expressions to proof
the concept/principles.
Results and Discussions A presentation of test results usually in the form of table and graphs
should be given. Students must show their competence about the use of formula and graphs. The repeated
experience of plotting graphs by students will generate confidence with respect to interpretation of labo-
ratory learning experience of different experiments. It should be noted that figures and tables should be
numbered sequentially and be referred to by this number in the discussion section. Students are required
to mention the following during submission of a laboratory report in order to generate their independent
power of thinking regarding a laboratory experiment just performed.
• Discuss any difficulty or/inaccuracy introduced while performing the test.
• Suggest any improvement in the employed procedure. Sometimes some modified steps of proce-
dure may indicate qualitative changes in the procedure to be followed in future.
• Account for any unusual or unexpected results.
• Make a clear statement concerning probable accuracy of results due to errors in instruments used.
• Compare the results obtained with standard results.
• Analyse the results and graphs.
The preparation of report covering the suggested items mentioned above requires a sound understanding
of test/experimental results.

Conclusions A brief conclusion summarising the work done, theory applied, and the results of the
completed work should be included here. A short concluding section should accompany every report in
which the report is summarised for the benefit of the reader and recommendations are made. The conclusion
must have a logical argument based on strong evidence that answers the problem posed in the experiment.
Use measurement results (with the uncertainty) for evidence. Recommendations explain work that you
would do differently to get better performance in the experiment. Make additional recommendations
pertaining to the problem posed. Make additional recommendations about the laboratory equipment.

Multiple Choice/ Objective-type/Short Answer-type Test Questions The four

options multiple choice/true-false/short answer type test questions may be included in Laboratory instruc-
tion. Students shall be required to answer them and submit the same along with the report. The purpose
of these items is to check basic knowledge as relevant to this test/experiment.

15.3 EXPERIMENT ON BASIC LOGIC CIRCUITS USING DIODES

AND TRANSISTORS
Aim: Implement the logic gates using diodes and transistors
 Laboratory Experiments 647

Fig. 15.2 Flow chart for developing the instruction manual

Materials Required
Component Name Quantity
Transistor - BC548 4
Diode - IN4007 6
Resistor 15K 2
10K 6
4.7K 3
1K 6
680 1
470 2
Power supply (0 – 5V) 1
Bread board 1
Connecting wire 20
 648 Digital Electronics: Principles and Applications

Circuit Diagram

Fig. 15.3(a) Inverter Fig. 15.3(b) Diode AND logic

Fig. 15.3(c) Diode OR logic

Fig. 15.3(d) NAND logic Fig.15.3(e) NOR logic

Procedure
1. Construct the circuits as per circuit diagram given in Fig. 15.3(a) to Fig. 15.3(e).
2. Low level refers to 0V and high level refers to input voltage +5V.
3. Switch on the input according to truth table as given below.
4. Verify output and compare with the truth table as given in Table 15.1(a) to Table 15.1(e).
 Laboratory Experiments 649

Truth Table
Table 15.1(a) Inverter Table 15.1(b) Diode AND logic
Input Output Inputs Output
Vi V0 VA VB V0
0 1 0 0 0
1 0 0 1 0
1 0 0
1 1 1

Table 15.1(c) Diode OR logic Table 15.1(d) NAND logic

Inputs Output Inputs Output
VA VB V0 VA VB V0
0 0 0 0 0 1
0 1 1
0 1 1
1 0 1
1 0 1 1 1 0
1 1 1

Table 15.1(e) NOR logic

Inputs Output
VA VB V0
0 0 1
0 1 0
1 0 0
1 1 0

15.4 EXPERIMENT ON BASIC LOGIC CIRCUITS USING LOGIC GATES

Aim: Implement the logic gates using ICs

Materials Required
Component Name Quantity
NAND gate IC7400 1
NOR gate IC7402 1
NOT gate IC7404 1
AND gate IC7408 1
OR gate IC7432 1
EX-OR gate IC7486 1
Power supply (0-5V) 1
Bread board 1
Connecting wire 20
 650 Digital Electronics: Principles and Applications

Circuit Diagram

Fig. 15.4 (a) AND gate, (b) OR gate, (c) NAND gate, (d) NOR gate,
(e) Ex-OR and (f) Inverter

Procedure
1. Connect the circuits as per circuit diagram shown in Fig. 15.4(a) to Fig. 15.4(f).
2. Low level refers to 0V and high level refers to input voltage +5V.
3. Switch on the inputs according to truth tables as given below.
4. Note down the outputs for all the possible combinations of inputs.
5. Verify output and compare with the truth table as given in Table 15.2(a) to Table 15.2(f).

Truth Table
Table 15.2(a) Truth table of AND gate Table 15.2(b) Truth table of OR gate
A B A.B A B A+B
0 0 0 0 0 0
0 1 0 0 1 1
1 0 0 1 0 1
1 1 1 1 1 1

Table 15.2(c) Truth table of NAND gate Table 15.2(d) Truth table of NOR gate
–— ———
A B AB A B A +B
0 0 1 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 0

Table 15.2(e) Truth table of Ex-OR gate Table 15.2(f ) Truth

table of NOT gate
A B AB
A –
0 0 0
A
0 1
0 1 1
1 0
1 0 1
1 1 0
 Laboratory Experiments 651

15.5 EXPERIMENT ON COMBINATIONAL LOGIC CIRCUITS

USING LOGIC GATES
Aim: Implement the following combinational logic circuits using ICs
(a) Half adder (b) Full adder (c) Half subtractor
(d) Full subtractor (e) Multiplexer

Materials Required
Component Name Quantity
NOT gate IC7404 2
AND gate IC7408 2
OR gate IC7432 2
EX-OR gate IC7486 2
Power supply (0 –5V) 1
Bread board 1
Connecting wire 20

Circuit Diagram

Fig. 15.5 Half adder (a) using EX-OR and AND gates, (b) using AND and OR gates

Fig. 15.6 Full adder using EX-OR, AND and OR gates

 652 Digital Electronics: Principles and Applications

Fig. 15.7 Half subtractor using AND and OR gates

Fig. 15.8 Full subtractor using AND and OR gates

Fig. 15.9 4:1 Mutiplexer

Procedure
1. Rig up the circuits as per circuit diagram shown in Fig. 15.5, Fig. 15.6, Fig. 15.7, Fig. 15.8, and
Fig. 15.9.
2. Low level refers to 0V and high level refers to input voltage +5V.
3. Switch on the inputs according to truth tables as given below.
4. Observe the logic outputs for all the possible combinations of inputs.
5. Verify the output and compare with the truth table.
 Laboratory Experiments 653

Truth Table
Table 15.3 Truth table of half adder Table 15.4 Truth table of full adder

Inputs Outputs Inputs Outputs

Addend Augend Sum Carry Carry in Addend Augend Sum Carry out
(A) (B) (S) (C) (Cin) (A) (B) (S) (Cout)
0 0 0 0
0 1 1 0 0 0 0 0 0
1 0 1 0 0 0 1 1 0
1 1 0 0 1 0 1 0
1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Table 15.5 Truth table of half subtractor

Inputs Outputs
Minuend Subtracted Difference Borrow
(A) (B) (D) (Bout)
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

Table 15.6 Truth table of full subtractor

Inputs Outputs
Borrow (Bin) Minuend (A) Subtracted (B) Difference (D) Borrow (Bout)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Table 15.7 Table for 4:1 Muxtiplexer

Selects Data Inputs Output

S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3
 654 Digital Electronics: Principles and Applications

15.6 EXPERIMENT ON FLIP-FLOPS

Aim: Implement the following latches and flip-flops using logic gates
(a) S-R Latch using NOR gates (b) S-R Flip-Flops
(c) J-K Flip-Flop (d) J-K Master Slave Flip-Flops
(e) D Latch

Materials Required

Component Name Quantity

NAND gate IC7400 4
NOR gate IC7402 4
NOT gate IC7404 1
Clock generator 1
Power supply (0 – 5V) 1
Bread board 1
Connecting wires 20

Circuit Diagram
Procedure
1. Connect the ICs as per circuit configurations shown in Fig. 15.10, Fig. 15.11, Fig. 15.12,
and Fig. 15.13.
2. Low level refers to 0V and high level refers to input voltage +5V.
3. Give the inputs according to truth tables as given below.
4. Observe the logic outputs of flip-flops for all the possible combinations of inputs.
5. Verify the output and compare with the truth table result.

Fig. 15.10 S-R Latch using NOR gate

Fig. 15.11 S-R Flip-Flop using NAND and NOR gates

 Laboratory Experiments 655

Fig. 15.12 J-K Flip-Flop Fig. 15.13 D Latch

Truth Table
Table 15.8 Truth table of S-R latch using NOR gates

Inputs Present state Next state

S R Qn Qn+1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 x
1 1 1 x

Table 15.9 Truth table of positive edge triggered S-R flip-flop

Inputs Outputs Comments

–
Clock (CLK) S R Q Q
–
↑ 0 0 Q Q No change
↑ 0 1 0 1 Reset
↑ 1 0 1 0 Set
↑ 1 1 ? ? Invalid

Table 15.10 Truth table of J-K flip-flop

Inputs Outputs Comments

— –
Jn Kn Qn Qn Qn+1 Qn+1
0 0 0 1 0 1
0 0 1 0 1 0
0 1 0 1 0 1
0 1 1 0 0 1
1 0 0 1 1 0
1 0 1 0 1 0
1 1 0 1 1 0
1 1 1 0 0 1
 656 Digital Electronics: Principles and Applications

Table 15.11 Truth table of D latch

Input Output
–
D Q Q
0 0 1
1 1 0

15.7 EXPERIMENT ON REGISTER

Aim: Implement the following registers using ICs
(a) Serial In–Parallel Out register
(b) Serial In–Serial Out register
(c) Parallel In–Parallel Out register
Materials Required
Component Name Quantity
IC 74164 1
IC 7491 1
IC 74LS273 1
Clock generator 1
Power supply0 – 5V 1
Bread board 1
Connecting wire 20

Circuit Diagram

Fig. 15.14 The 8-bit Serial In– Parallel Out shift register IC 74164

Fig. 15.15 The 8-bit Serial In– Serial Output shift register IC 7491
 Laboratory Experiments 657

Fig. 15.16 8-bit Parallel In– Parallel Out shift register IC 74LS273
Procedure
1. Rig up the ICs as per circuit diagram and pin configuration of ICs given in Fig. 15.14, Fig. 15.15,
and Fig. 15.16.
2. Low level refers to 0V and high level refers to input voltage +5V.
3. Clear all flip-flops by applying 0V to the clear input.
4. Apply the data into the serial input one bit per clock pulse in Fig. 15.14, and Fig. 15.15. Feed the
input data in parallel form for Parallel In – Parallel Out shift register.
5. Observe the logic outputs of flip-flops at QA to QH for all the possible combinations of inputs.
6. Observe the output after each clock pulse and compare with the result shown in Table 15.12 and
Table 15.13.
Table
Table 15.12 Serial In-Parallel Out

Inputs Outputs
Clock Serial QA QB QC QD QE QF QG QH
0 0 0 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0 0 0
2 1 1 1 0 0 0 0 0 0
3 1 1 1 1 0 0 0 0 0
4 1 1 1 1 1 0 0 0 0
5 1 1 1 1 1 1 0 0 0
6 1 1 1 1 1 1 1 0 0
7 1 1 1 1 1 1 1 1 0
8 1 1 1 1 1 1 1 1 1
Table 15.13 Serial In Serial Out

Inputs Outputs
Clock Serial QA QB QC QD QE QF QG QH
0 0 0 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0 0 0
2 0 0 1 0 0 0 0 0 0
3 0 0 0 1 0 0 0 0 0
4 0 0 0 0 1 0 0 0 0
5 0 0 0 0 0 1 0 0 0
6 0 0 0 0 0 0 1 0 0
7 0 0 0 0 0 0 0 1 0
8 0 0 0 0 0 0 0 0 1
 658 Digital Electronics: Principles and Applications

15.8 EXPERIMENT ON SEVEN SEGMENT DISPLAY AND DECODER

DRIVER
Aim: Implement the seven segment display decoder
Materials Required
Component Name Quantity
7447 Decoder 1
Seven segment display SP5501 1
Power supply 0 –5V 1
Bread board 1
Connecting wire 20

Circuit Diagram

Fig. 15.17 (a) Logic diagram of IC 7447 and (b) seven segment display
 Laboratory Experiments 659

Truth Table
Table 15.14 Truth table for seven segment display

Decimal Inputs Outputs

Number A B C D a b c d e f g
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 0 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 0 0 1 1
10 1 0 1 0 x x x x x x x
11 1 0 1 1 x x x x x x x
12 1 1 0 0 x x x x x x x
13 1 1 0 1 x x x x x x x
14 1 1 1 0 x x x x x x x
15 1 1 1 1 x x x x x x x

Procedure
1. Construct the circuits as shown in Fig. 15.17(a) and Fig. 15.17(b).
2. Low level refers to 0V and high level refers to input voltage +5V.
3. Switch on the input according to truth table as given above.
4. Verify the display output and compare with the truth Table 15.14.

15.9 EXPERIMENT ON COUNTERS

Aim: Implement the following counters using ICs
(a) Asynchronous counter
Module 16
Module 10 or Decade counters
(b) Synchronous counter
Module 16

Materials Required

Component Name Quantity

IC 7493 1
IC 74163 1
CLOCK generator 1
Power supply 0 – 5V 1
Bread board, 1
Connecting wire 20
 660 Digital Electronics: Principles and Applications

Circuit Diagram

Fig. 15.18 Logic diagram of 7493 IC

Fig. 15.19 7493 can be used as module 16

Fig. 15.20 7493 can be used as module 10 counters

 Laboratory Experiments 661

Fig. 15.21 Synchronous counter using 74163

Procedure
1. Connect the circuits as per circuit diagram shown in Fig. 15.19, Fig. 15.20 and Fig. 15.21.
2. Low level refers to 0V and high level refers to input voltage +5V.
3. Connect the clock input.
4. Observe the output and compare with the sequence table

Count Sequence
Table 15.15 Sequence of mod 16 counter

State Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
 662 Digital Electronics: Principles and Applications

Table 15.15 (Contd.)

5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

Table 15.16 The sequence of mod 10 or decade counter

State Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1

15.10 EXPERIMENT ON CASCADE COUNTERS

(a) Cascade connection of mod-2 and mod-8 counters
(b) Cascade connection of mod-4 and mod-8 counters

Aim: Counters are connected in cascade to construct higher mod counters with smaller mod coun-
ters. In cascade counters, the last stage output of one counter is fed to another counter. The aim of this
experiment is to implement the mod-16 and mod-32 counters using the cascade connection of mod-2
and mod-8 and mod-4 and mod-8 counters respectively.

Materials Used
Component Name Quantity
J-K Flip-Flop 74LS73A 4
CLOCK generator 1
Power supply 0 – 5V 1
Bread board 1
Connecting wire 20
 Laboratory Experiments 663

Procedure
1. Connect the circuits as per circuit diagram shown in Fig. 15.22, and Fig. 15.23.
2. Low level refers to 0V and high level refers to input voltage +5V.
3. Connect the clock input properly.
4. Observe the output waveforms at output terminals as shown in Fig. 15.24 and Fig. 15.25.

Circuit Diagram

Fig. 15.22 Cascade connection of mod-2 and mod-8 counters

Fig. 15.23 Cascade connection of mod-4 and mod-8 counters

 664 Digital Electronics: Principles and Applications

Fig. 15.24 Timing diagram of mod-16 counter due to cascade

connection of mod-2 and mod-8 counters

Fig. 15.25 Timing diagram of mod-32 counter due to cascade connection

of mod-4 and mod-8 counters

15.11 EXPERIMENT ON SELF

STARTING AND SELF COR-
RECTING COUNTERS
Aim: The counter always starts counting sequence
from either 000 or 111. But, in real working environment,
the counter will not always start from this predefined
count value. Therefore, the counter should not be able
to start from any predefined state and the counting states
will not be correct. Then self starting and self correcting
counters are designed to eliminate this problem. The aim
of this experiment is to implement a typical self starting Fig. 15.26 State transition diagram of a
and self correcting counter as shown in Fig. 15.26. typical self start and self correcting counter
 Laboratory Experiments 665

Materials Used
Component Name Quantity
D Flip-flop 74LS175 3

CLOCK generator 1

AND gate IC7408 2

OR gate IC7432 2

Power supply 0 – 5V 1

Bread board 1

Connecting wire 20

Circuit Diagram

Fig. 15.27 Self-starting and self-correcting counter

Assume the counter counts in sequence 000 → 001 → 011 → 100 → 101 → 000. If initial count value
is either 111 or 110 or 010, then self-correcting capability has been added after incorporating the unused
states in counter design. While present state is 111 or 110, then next transition will be 000. When
present state is 010, then next state transition is 011. When this counter is designed with D flip-flops,
the excitation of D flip-fops will be the next state as given in Table 15.17. The excitation function of D
– – – – –– –– – – – ––
flip-flops are , D0 = A B + BC + AC , D1 = A BC + ABC, and D3 = ABC + ABC, where A=Q2, B=Q1, C=Q0.
Figure 15.27 shows the implementation of the self-start and self-correcting counter.
 666 Digital Electronics: Principles and Applications

Table 15.17 Flip-flops excitation for self-start and self-correcting counter

Clock pulse Preset state Next state Flip-flop inputs

FF2 FF1 FF0
CLK Q2 Q1 Q0 Q2 Q1 Q0 D2 D 1 D0
A B C A B C
0 0 0 0 0 0 1 0 0 1
1 0 0 1 0 1 1 0 1 1
2 0 1 0 0 1 1 0 1 1
3 0 1 1 1 0 0 1 0 0
4 1 0 0 1 0 1 1 0 1
Procedure
1. Connect the circuits as per circuit diagram shown in Fig. 15.27.
2. Connect ground and VCC of each flip-flop to power supply.
3. Connect the clock input properly
4. Observe the output voltage at output terminals and compare with state transition diagram of self-
start counter as shown in Fig. 15.26.

15.12 EXPERIMENT ON SEQUENCE GENERATOR

Aim: Implement a sequence generator as per State Table 15.18 using D flip-flops.
Table 15.18

Present state Next state Flip-flop inputs Output

X=0 X=1 X=0 X=1 X=0 X=1
A B A B A B D1 D0 D1 D0 O1 O0
0 0 0 0 0 1 0 0 0 1 1 0
0 1 1 1 0 1 1 1 0 1 0 0
1 0 1 1 0 1 1 1 0 1 0 0
1 1 0 0 1 0 0 0 1 0 0 1

Materials Used
Component Name Quantity
D Flip-flop74LS175 2
CLOCK generator 1
AND gate IC7408 2
OR gate IC7432 2
Inverter IC7404 1
Power supply 0 – 5V 1
Bread board 1
Connecting wire 20
 Laboratory Experiments 667

Circuit Diagram

Fig. 15.28 Implementation of sequence detector circuit using D flip-flops

The excitation function of D flip-flop inputs D1 and D0 are as follows

–– – – – – –
D1 = X A B + X AB + XAB and D0 = XA + A B + AB
––
The output equations are O1 = A B and O0 = AB. The implementation of the sequence detector circuit
using D flip-flops and combinational logic circuit elements is shown in Fig. 15.28.

Procedure
1. Connect the circuit as per circuit diagram shown in Fig. 15.28.
2. Connect ground and VCC of each flip-flop to power supply.
3. Connect the clock input properly and apply input on X.
4. Observe the output voltage at output terminals and compare with Table 15.18.

15.13 EXPERIMENT ON UP-DOWN COUNTER

AIM: Implement a up-down counter for the state diagram as shown in Fig. 15.29 using T flip-flops.
 668 Digital Electronics: Principles and Applications

Fig. 15.29 State diagram of up-down counter

Circuit Diagram

Fig. 15.30 Implementation of up-down counters using T flip-flops

Assume A=‘En’ stands for counter enable and B=‘dir’ represents direction of up-down counter. There
are four states S0=00, S1=01, S2=10 and S3=11 and two outputs O1 and O2. The sequential circuit consists
of two T flip-flops and the state transition table is given in Table 15.19. The excitation functions of T
flip-flops are as follows
 Laboratory Experiments 669

–— –— ———
T1 = ABQ0 + ABQ0 = A(BQ0 + BQ0) = AB Q0 and T0 = A
and the output functions are
O1 = AQ1 and O0 = AQ0
The implementation of the sequential circuit (up-down counter) using T flip-flops and combinational
logic circuit elements is shown in Fig.15.30.

Table 15.19(a) The state table Table 15.19 Table 15.19(b) The excitation table of T flip-flops

Inputs (AB) Inputs (AB)

Present state 00 01 10 11 Present state 00 01 10 11
(Q1Q0)
(Q1Q0)
00 00 00 11 01
00 00 00 11 01
01 00 00 01 11
01 01 01 00 10
10 00 00 11 01
10 10 10 01 11
11 00 00 01 11
11 11 11 10 00
Inputs of Flip-flops
Next State (Q *1 Q *)
0 T1 T0

Table 15.19(c) State transition table with outputs

Inputs (AB)
Present state 00 01 10 11
(Q1Q0)
00 00/00 00/00 11/11 01/01
01 01/00 01/00 00/00 10/10
10 10/00 10/00 01/01 11/11
11 11/00 11/00 10/10 00/00
Next State(Q1* Q0*)/Output(O1, O0)

Procedure
1. Construct the circuit as shown in Fig. 15.30.
2. Connect the clock input properly and apply inputs on A and B.
3. Observe the output voltage at output terminals and compare with table 15.19.

15.14 EXPERIMENT ON MULTIVIBRATORS

Aim: Implement the following multivibrators

(a) Astable multivibrator
(b) Monostable multivibrator
(c) Bistable multivibrator
 670 Digital Electronics: Principles and Applications

Materials Required
Component Name Quantity
Transistor BC548 2
Diode IN4007 1
555 timer IC 4
Resistor 100K 2
15K 4
10K 4
1K 4
Capacitance 10µF 2
0.01µF 2
Power supply 0 – 5V 1
CRO 1
Bread board 1
Connecting wire 20
Circuit Diagram

Fig. 15.31 Astable multivibrator/Clock Fig. 15.32 Astable multivibrator using

oscillator using NPN transistor 555 timer IC

Fig. 15.33 Duty cycle reduction of astable multivibrator using 555 timer IC
 Laboratory Experiments 671

Fig. 15.34 Monostable multivibrator using 555 timer IC

Fig. 15.35 Bistable multivibrator using 555 timer

Procedure
1. Connect the ICs as per circuit configuration shown in Fig. 15.31, Fig. 15.32, Fig. 15.33, 15.34
and Fig. 15.35.
2. Apply the power supply and see the output waveform using CRO.
3. Draw the output waveforms on a graph paper.
4. Calculate the theoretical time period using the following expressions
a. T1= 0.693 R1 C1 and T2= 0.693 R2 C2 for Fig. 15.31
b. T1= 0.693 (R1+R2) C1 and T2= 0.693 R2 C1 for Fig. 15.32
c. T1= 0.693 R1C1 and T2= 0.693 R2 C1 for Fig. 15.33
d. T1= 1.1R1 C1 for Fig. 15.34
5. Verify the theoretical and practical time period.
 672 Digital Electronics: Principles and Applications

Table
Table 15.20 Time period and frequency of multivibrator
T1 T2 T = T1 + T2 Frequency

15.15 EXPERIMENTS ON DAC

Aim: Implement the following DACs
(a) R-2R ladder circuit of 3-bit DAC
(b) DAC0800

Materials Required
Component Name Quantity
IC741 1
DAC0800 1
Resistor 10K 8
5K 4
Capacitance 0.1µF 2
0.01µF 1
Power supply 0 – 5V 1
–10V 0
10V 1
Bread board 1
Connecting wire 20

Circuit Diagram

Fig. 15.36 R-2R ladder circuit of 3-bit DAC

 Laboratory Experiments 673

Fig. 15.37 DAC0800

Procedure
1. Connect the circuits as per circuit diagram shown in Fig. 15.36 and Fig. 15.37.
2. Low level refers to 0V and high level refers to input voltage +5V.
3. Switch on the power supply and digital inputs are given according to truth tables as given below.
4. Note down the output voltages for all the possible combinations of inputs in tabular form.
5. Calculate the theoretical output voltage and compare with the actual output voltage.
Table
Table 15.21 Binary input and analog output Table 15.22 Binary input and analog output

Binary inputs Output voltage Binary inputs Output voltage

000 0000
001 0001
010 0010
011 0011
100 0100
101 0101
110 0110
111 0111
1000
1001
1010
1011
1100
1101
1110
1111

15.16 EXPERIMENT ON ADC

Aim: Implement the Flash ADC using comparators
 674 Digital Electronics: Principles and Applications

Materials Required
Component Name Quantity
IC741 7
IC 7445 1
Resistor 10K 6
5K 2
Power supply 0–5V 1
–12V0 + 12V 1
Bread board 1
Connecting wire 20
Circuit Diagram

Fig. 15.38 Flash ADC

Procedure
1. Connect the ICs as per circuit configuration given Fig. 15.38.
2. Low level refers to 0V and high level refers to input voltage +5V.
3. Set the reference voltage, V at +5V.
4. Slowly increase analog input voltage and observe the corresponding logic outputs of comparators.
5. Verify the output and compare with the truth table as shown in Table 15.23.
 Laboratory Experiments 675

Table 15.23 Analog input, comparator output and digital output of flash converter
Analog input voltage Comparator outputs Digital output

Vi C7 C6 C5 C4 C3 C2 C1 b2 b1 b0
0 ≤Vi<V/14 0 0 0 0 0 0 0 0 0 0
V/14<Vi<3V/14 0 0 0 0 0 0 1 0 0 1
3V/14<Vi<5V/14 0 0 0 0 0 1 1 0 1 0
5V/14<Vi<7V/14 0 0 0 0 1 1 1 0 1 1
7V/14<Vi<9V/14 0 0 0 1 1 1 1 1 0 0
9V/14<Vi<11V/14 0 0 1 1 1 1 1 1 0 1
11V/14<Vi<13V/14 0 1 1 1 1 1 1 1 1 0
13V/14<Vi ≤V 1 1 1 1 1 1 1 1 1 1

15.17 EXPERIMENT ON VHDL SIMULATION OF DIGITAL SYSTEM

Aim: VHDL simulation of the following digital system
(a) 4-bit Shift register
(b) 4-bit counter
(c) 4 × 4 RAM
Software Required: The ALTERA Quartus II software version 6.0 to 7.2, which can provide a
complete design environment for system-on-a-programmable-chip design, is required for VHDL simulation
of digital systems. The said software must be worked in a personal computer or a UNIX or Linux worksta-
tion. This software ensures easy design entry, fast processing, and straightforward device programming.
VHDL Code

Fig. 15.39 VHDL code for 4-bit shift register

676 Digital Electronics: Principles and Applications

Fig. 15.40 VHDL code for 4-bit counter

Fig. 15.41 VHDL code for 4 × 4 SRAM

 Laboratory Experiments 677

Netlist Viewer

Fig. 15.42 RTL Viewer 4-bit shift register

Fig. 15.43 Technology map viewer of 4-bit shift register

Fig. 15.44 RTL viewer 4-bit counter

Fig. 15.45 Technology map viewer of 4-bit counter

 678 Digital Electronics: Principles and Applications

Fig. 15.46 RTL viewer of 4 × 4 SRAM

Procedure
1. Create a new project file for register, counter and RAM separately.
2. Write VHDL code in the corresponding files and save as shift_reg.vhd, counter.vhd and SRAM.
vhd respectively.
3. Compile the files for analysis and synthesis, fitter, assembler, and timing analyser using compile tool.
4. Edit data input files as text file or vector waveform file or hexadecimal file
5. Use the Quartus II Simulator to simulate project files. Before running a simulation, specify input
vectors as the stimuli for the Simulator The Simulator uses these input vectors to simulate the
output signals.
6. View the RTL Viewer, Technology map viewer and simulation results.
7. Verify the output simulation results.

SUMMARY
In this chapter, the development of instruction manual for laboratory experiments have been discussed. To perform
the experiments on logic gates, combinational logic circuits, latches, flip-flops, register, seven segment display and
decoder driver, counters, sequential circuits, multivibrators, digital to analog converter, and analog to digital converter,
the required materials, circuit diagrams and procedure are incorporated. The VHDL code for simulation of 4-bit shift
register, 4-bit counter and 4×4 SRAM are also illustrated in this chapter.

REVIEW QUESTIONS
1. Justify that transistor is used as a switch in a inverter circuit as shown in Fig. 15.3.
2. Write the truth table when any one diode of Fig. 15.3 is opened.
3. Draw a transistor schematic of NOR gate, and write it’s truth table.
4. Draw a CMOS inverter. Why does CMOS technology dominate in VLSI manufacturing?
5. Design a circuit using combinational logic to double the output frequency.
 Laboratory Experiments 679

Fig. 15.47
6. What is a multiplexer?
7. Design a full-adder using a decoder.
8. What is the difference between latches and flip-flops?
9. What are the types of flip-flops? What is D-FF?
10. How can you convert an S-R flip-flop to a J-K flip-flop?
11. How can you convert a J-K flip-flop to a D flip-flop?
12. What is Race-around problem? How can you rectify it?
13. How to convert D-latch into J-K-latch and J-K-latch into D-latch?
14. Write an VHDL code for behavioral models of the following flip-flops:
(a) J-K flip-flop (b) D flip-flop (c) T flip-flop
15. Write some applications of shift register IC 74164.
16. Convert D-latch into divider by 2. What is the max clock frequency the circuit can handle if T_setup=
6ns, T_hold = 2ns, T_propagation = 10ns?
17. Consider two counters to count 16. First circuit is synchronous and second is “ripple”. Which circuit
has less propagation delay?
18. How to design a divide-by-3 counter with equal duty cycle ?
19. Design a 2-bit up/down counter with clear using gates.
20. What is MOD counter? Design a mod-9 and mod-12 counter using 7491 IC.
21. What is the difference between asynchronous and synchronous counters?
22. Draw the internal structure of a timer. Explain some applications of timer in monostable mode.
23. What are the modes of operation of a timer?
24. Classify DAC.
25. Why an inverted R-2R ladder network DAC is better than R-2R ladder DAC?
26. 8-bit ADC with parallel output converts input signal into digital numbers. Design a ADC circuit that
finds MAX of every 10 numbers at the output of the ADC.
27. Implement comparator that compares 2-bit numbers A and B. The comparator should have 3 outputs:
A > B, A < B, and A = B. Design the comparator in two ways:
- using combinational logic circuits;
- using multiplexers. Write VHDL code for your schematic at RTL and gate level.

Fig. 15.48
680 Digital Electronics: Principles and Applications

28. Describe the operation of DAC? What are the most important parameters of DAC? Do we really
need both INL and DNL to estimate linearity?
29. Compare briefly all types of ADC that you know.
30. For an 8-bit flash A/D converter with an input range from 0V to 2.55V, describe what happens when
the input voltage changes from 1.27V to 1.28V .
 APPENDIX

A
IEEE STANDARD SYMBOLS
The Institute of Electrical and Electronic Engineers (IEEE) has developed a standard set of logic symbols to
represent digital electronics circuits. The IEEE standard graphic symbols for logic functions are compatible with
standard 617 of International Electrotechnical Commission. Fundamental circuit diagram symbols corresponding
to SSI, and MSI ICs describe the logic function of ICs in a consistent and logical manner. But the detail logic
function representation of VLSI ICs is impractical, so that symbolic methodology can be used to indicate the
functions of major components. Professional digital electronics circuits designer should be familiar with IEEE
standard symbols as they are most commonly used in the manufacturer’s data sheets during design of digital
systems. In this section, IEEE standard symbols have been described to familiar with logic symbols which are
commonly used in digital system design.

A.1 INTERNAL LOGIC STATE AND EXTERNAL LOGIC STATE

The IEEE standard can support the notion of bubble to bubble logic design. The internal logic state means that the
logic state is existing inside the rectangular symbol outline at the input and output. The external logic state means
that the logic state is existing at external input or output. The inversion circle is used at the inputs and outputs of
conventional symbols. Figure A.1 shows the Internal and external logic states.

Fig. A.1 Internal and external logic states

A.2 LOGIC GATES AND GENERAL QUALIFYING SYMBOLS

The simplest Boolean logic gates have functional symbols that are simply rectangles labelled with appropriate
general symbols. Figure A.2 shows the symbols of logic gates. The general symbols for simple AND, OR and
EX-OR gates and buffers indicate the number of inputs that must be active in order to activate the output. The
functional system includes an alternative to the inversion circle or the polarity indicator. Some general qualifying
symbols for digital circuit representation are illustrated in Fig. A.3.
682 Appendix A

Fig. A.2 Functional logic symbols of AND, NAND, OR, NOR, Buffer, Inverter,
EX-OR and EX-NOR gates

Symbol Function
& AND gate
≥1 OR gate
=1 Exclusive OR
= Logic identity
2k An even number of inputs must be active
2k+1 An odd number of inputs must be active
1 The input must be active
or A buffer or element with more than usual output capability. Symbol is oriented in
the direction of signal flow
Schmitt trigger, element with hysteresis
X/Y Code converter
MUX Multiplexer
DMUX Demultiplexer
S Adder
P-Q Subtracter
CPG Look-ahead carry generator
p Multiplier
COMP Magnitude comparator
ALU arithmetic logic unit
Retriggerable monostable
 Appendix A 683

Nonretriggerable monostable
1
SRGm Shift register, m=number of bits
CTRm Counter, m=number of bits, cycle length 2m
CTR DIVm Counter with cycle length m
RCTRm Asynchronous ripple counter, cycle length 2m
Logic negation at input, External 0 produces internal 1
Logic negation at output, internal 1 produces External 0

Active low input equivalent to in positive logic

Active low output equivalent to in positive logic

Active low input in the case of right to left signal flow

Active low output in the case of right to left signal flow

Signal flow from right to left. If not otherwise indicated, signal flow is from left
to right
Bidirectional signal flow
Dynamic inputs active on indicated transition
Positive Logic Positive Logic Polarity Indication
1 0 H
0 1 L
1 0 H
0 1 L
Nonlogic connection A label inside the symbol usually defines the nature of this
pin
Input of analog signals

Input for digital signals

Fig. A.3 General qualifying symbols

A.3 DECODERS
The IEEE standard for logic symbols allows a decoder’s logic function to be displayed as part of the symbol. The
symbols are used as basic concept of internal qualifying symbols, general qualifying symbols, internal values,
input weights, output values, and enable input. Individual input and output signals may be labelled with symbols
inside the logic-symbol outline to describe the signal characteristics.
The top of a logic symbol may contain an alphanumeric label to denote the general function performed by the
device. The decoders and encoders use the standard symbol X/Y, where X is the input code and Y is the output code.
Each input combination of coder produces an internal value. The internal values of a 3 to 8 decoder are 0 to 7. Each
output may have a qualifying label listing the internal values that cause the output to be asserted. In a decoder , each
output is asserted for just one internal value. An enable input has the qualifying label EN which control the function
 684 Appendix A

of the device. While EN is asserted, output is active low available at output terminals. When EN is not asserted, an
enable input imposes the external high –impedance state on the three-state outputs. The IC 74×138, IC 74×139
and IC 74×328 have active –low outputs.

(a) (b) (c)

Fig. A.4 IEEE standard symbol for decoder (a) IC 74x328 (b) IC 74 ×138 (c) IC 74 ×139

A.4 TRI-STATE BUFFER REGISTER

The IEEE standard Tri-state buffer symbols are illustrated in Fig. A.5. The downward pointing triangle denotes
a three state output and an enable input is labelled by EN. When EN=1, the device is enabled for output and the
desired output corresponding to inputs are obtained at output terminals. If the device is disabled, output will be
high impedance state (Z). The IEEE standard symbols are used for MSI three state buffers. The common control
block concept is given in Fig A.6 in which a common block is used with an array of related elements. The inputs
to the common control block can control all the elements of the array.

Fig. A.5 IEEE standard Tri-state buffer symbols (a) non inverting active-high enable (b) inverting active-
high enable (c) non-inverting active-low enable (d) inverting active-low enable
 Appendix A 685

Fig. A.6 Common control block in IEEE standard symbols

The IEEE standard symbols for the IC 74 × 541 and IC 74 × 245 are shown in Fig. A.7. In this figure, the enable
and direction inputs can be applied to all elements of the device. The common control block controls all identical
elements. The other common features of IC 74 × 541 and IC 74 × 245 are hysteresis symbol, right – pointing or
left-pointing triangle, arrows and identical elements. Hysteresis symbol represents that inputs have hysteresis.
The right-pointing or left-pointing triangle is used to represent amplification signals. In case of three-state buffers,
output has more fan-out capacity. The arrows represent the direction of signal flow when it is not strictly left or
right. One or two identical elements in the array must be drawn in detail as shown in Fig. A.7. The other elements
must be identical to the first element.

(a) (b)
Fig. A.7 IEEE standard symbols for Tri-state buffer (a) IC 74 × 541 and (b) IC 74 × 245
 686 Appendix A

A.5 MULTIPLEXERS AND DEMULTIPLEXERS

The IEEE standard symbols for multiplexers and demultiplexers are shown in Fig. A.8 and Fig. A.9 respectively.
The general symbol MUX identifies multiplexer. The bit-grouping symbol is represented by a bracket which
indicates that a grouped inputs generate an internal value that is a weighted sum. The weight are given by the
qualifying labels on the individual inputs and the weights are power of two. In the standard symbol of IC 74×151
0
multiplexer, the notation G represents AND dependency with 0 to
7 7 signals. Any one input channel will be
selected depending on the weighted input signals and there are two outputs: one is equal to input and other is
complement of input.
0
In IC 74×153, the G represents the bit grouping for selected inputs and the common control block
3 for
two different block. Both half of the multiplexer is identical in function to the top as its qualifying labels are not
repeated. And each half has an independent EN input.
The IC 74×157 has no bit-grouping, but has a common enable input EN and control dependency signal G1. This
IC has four sections which are controlled by G1. When G1=1, pin 3 is selected. If G1=0, pin 2 is selected.

(a) (b) (c)

Fig. A.8 IEEE standard symbols for multiplexers (a) IC 74 ¥ 151, (b) IC 74 ¥157 and (c) IC 74 ¥153

The IEEE standard demultiplexer symbols for the MSI demultiplexer ICs are illustrated in Fig. A.9. The notation
0
G represents AND dependency with 0 to 7 signals. Any one output channel will be selected depending on the
7
weighted input signals and there are three inputs. The IC 74×139 consists of two independent demultiplexers. Each
0
demultiplexer has enabled input signal and bit grouping G . It is depicted in standard symbol of IC 74×155,
3
there is a common control block which is used to control two different demultiplexer sections. The input labelled 4
has an AND dependency with G4 so that the selected output is asserted when only both inputs are asserted.
 Appendix A 687

(a) (b) (c)

Fig. A.9 IEEE standard symbols for demultiplexers (a) IC 74 ¥ 138, (b) IC 74 ¥ 139 and
(c) IC 74¥155

A.6 ADDERS AND COMPARATORS

IEEE standard symbols for MSI adders and comparators are shown in Fig.A.10. The general qualifying symbol
is used to identify an adder or addition function. Figure A.10(a) is the symbol of 4 bit adder IC 74 × 283. The
numbers on the addend inputs and sum output indicate the weight of each pin as power of 2. Figure A.10(b) shows
the symbol of 4 bit comparator IC 74 × 85. Just like select inputs of multiplexers, the data inputs have qualifying
labels which indicate the weights in power of 2.

(a) (b)
Fig. A.10 IEEE standard symbols for (a) adders IC 74¥283 (b) comparators IC 74¥85
 688 Appendix A

A.7 LATCHES AND FLIP-FLOPS

Figure A.11 shows the IEEE standard symbols for latches and flip-flops. There are some differences between
latches and flip-flops. The major difference is that asynchronous preset and clear inputs are available on the left
of flip-flops IEEE standard symbols only. The names of these inputs are S (set) and R (reset). The clock input is
named as Ci , where i is an integer. The other inputs are labelled as iD for inputs. Figure A.11(a) represents the IC
74×375 which is a latch. IC 74×74 has two identical elements and it consists of two D flip-flops. The D flip-flop
has S (set) and R (reset) and Clock input C1. The D flip-flops input is represented by 1D and output is available in
normal and complement form. The IEEE standard symbol of JK flip-flop IC 74×112 is illustrated in Fig. A.11(c)
which operates on each negative edge triggered clock pulse.

(a) (b) (c)

Fig. A.11 IEEE Standard symbols for (a) D latch IC 74 ¥ 375
(b) D flip-flop IC 74 ¥ 74 (c) JK flip-flop IC 74 ¥ 112

A.8 SHIFT REGISTER

IEEE Standard symbols for 8 bit shift register with parallel outputs from each bit as shown in Fig.A.12. The upper
section of the diagram is control block and the lower section consists of eight flip-flops that make up eight stages
of shift register. The qualifying symbol
→ indicates that the data shifts one stage
further away from the control block every
time after the rising edge of clock input
pulse. The enabling control of the flip-
flops by the clock is indicated by control
dependency C1 and an enable signal
EN. The downward-pointing triangles
indicate tri-state outputs. In IC 74×377,
the input G1 is used as an enable for
inputs bearing the label 1 and the clock
input is IC2. The clock input controls
all of the inputs bearing the label 2 that
is data input lines 2D. The qualifying
symbol SRGn represents an n-bit shift
register. When the device is asserted , an input labelled with a → causes the device shift its data one position left
to right and an input labelled with a ← cause a shift in the opposite direction.
 Appendix A 689

Fig. A.12 IEEE standard symbols for registers (a) IC 74 ¥ 373 (b) IC 74 ¥ 377
(c) IC 74 ¥ 166 and (d) IC 74 ¥ 194

A.9 COUNTERS
IEEE standard symbols of counters are shown
in Fig. A.13. The general qualifying symbol
CTR represents counter and DIV16 indicates
that the counter is a divide-by-16 counter
and labels [1] to [8] indicate the arithmetic
weight of each counter bit. The common
control block is used to explain the counter
functions and it has the following control
signals content input, content output, mode
dependency. When the content input signal
bearing the label CT=m is asserted, the value
‘m’ is loaded into the device. In the counter
symbols, CT represents count but in general it
indicates content. In content output, an output
bearing the label CT=m is asserted when the
content of the device is m. In IC 74 × 161, the Fig. A.13 IEEE standard symbol for counters
output 3CT=15 is asserted when the counter (a) 74 ¥161 and
is in state 15. (b) 74 ¥169
The mode dependency of counter is indicated by Mi which is used as enable function. When Mi signal is
asserted, counter perform normal operations. But if Mi signal is not asserted¸ the affected signals have no effect on
the device’s function and ignored.
When the device is asserted, an input labelled with a + causes the device to count up once. While input labelled
with a – causes the device to count down once. The counter counts up on the rising edge of the signal if M2, G3
and G4 are asserted. In IC 74×169, if M2, M3, G5 and G6 are asserted, counter operates in up counting mode. If M2,
M4, G5 and G6 are asserted, counter operates in down counting mode.
 690 Appendix A

A.10 ADDRESS DEPENDENCY

In programmable logic devices, such as ROM and RAM, any one of the binary array elements (binary
words) can be selected by the use of a set of address inputs. This is indicated by a functional logic symbol
A, address dependency. The method of Address Dependency is that the address lines allow the element
that is selected by the address to function fully and to react the affected inputs. IEEE standard symbols of
TMS27128 16KB EPROM and TMS47256 32KB ROM are shown in Fig. A.14. All outputs are tri-stated
–
and EPROM has two control lines and an output enable which gates data to the output lines. When E = 1,
the tri-state output buffers are placed in their high-impedance state (Z). The address dependency indicates
that valid address range from 0 to 16383. IEEE standard symbol of TMS47256 32KB ROM is depicted in
–
Fig. A.14. Pin 20 has dual function: one chip enable (E ) and other is power down input (E). This IC has a
–
secondary chip select pin S 1 which can also be programmed during mask fabrication to be either active high
or active low. The address dependency represents the valid address range from 0 to 32767 and the eight
affected data outputs.

Fig. A.14
 Appendix A 691

Fig. A.14 IEEE standard symbol for memory

(a) TMS27128 16KB EPROM
(b) TMS47256 32KB ROM
(c) RAM 16¥4

A.11 ALU
The IEEE symbol for a 4-bit ALU IC 74×181 is shown in Fig. A.15. In common control block, the first five
inputs form a mode control word which is represented by M. The weights of the mode control bits are powers of
2 and they are designated by a number in the range 0 to 31. As per IEEE standard, a separate table accompanies
the logic symbol to define the functions performed in each mode. The output signals CP, CG and CO are enabled
in modes 0 to 15. This IC has four individual ALU blocks which are labelled with the weight of the bits.

Fig. A.15 IEEE symbol for ALU IC 74 × 181

 APPENDIX

B
PIN DIAGRAM
OF LOGIC GATES

Fig. B.1 Pin diagram of (a) IC 7408 (b) IC 7432 (c) IC 7404 (d) IC 7402 (e) IC 7400 ( f ) IC 7486
 APPENDIX

C
GLOSSARY
Active-High The input or output terminal is activated or enabled when the terminal is at HIGH logic level.
Active-Low The input or output terminal is activated or enabled when the terminal is at LOW logic level.
Analog System This is an electronic system which consists of analog devices to perform different operations.
AND A Boolean operation of two variables indicated by ‘.’. This is represented by A.B
AND Gate This is a logic circuit whose output is 1 if and only if all its inputs are 1.
Adder This is a logic circuit which can add two numbers.
ASCII Code American Standard Code for Information Interchange. It is seven bit alphanumeric code and used
for alphanumeric characters.
Absorption This theorem allows a term or factor to be absorbed into another term or factor.
Arithmetic-Logic Unit (ALU) A logic circuit that performs arithmetic and logical operations on two binary
numbers.
Asynchronous Counter In this counter, all the flip-flops are not triggered simultaneously but each flip-flop
output is used as the clock input of the next flip-flop.
Architecture Body Architecture body describes the actual implementation of the functionality of the ENTITY.
It contains the statements, interconnected components to represent the behaviour of the ENTITY and the structure
of the ENTITY.
Analog-to-Digital Converter (ADC) An electronic circuit that converts an analog signal to a corresponding
digital output signal.
Accuracy It is the limit within which the output of a D/A converter is obtained.
Acquisition Time The time required following a sample command for the output to reach its final value within
specified error±0.1%.
Aperture time The time required for the sample and hold switch opening from 10% open to 90%open.
Astable Multivibrator It is a digital circuit which oscillates between two unstable states which are quasi-stable
states. It is also known as free-running multivibrator.
Access Time The time required for reading or writing a memory location.
Address The binary code which identifies the location of a word in memory.
Address Bus A address code which comes out from microprocessor and fed to memory and I/O devices. The
address bus is unidirectional.
Address Decoder It is a n-line-to-2n lines decoder which is used to select a specified memory location.
Binary It has two states 1 or 0.
Binary Number System The number system with base 2 and it has two symbols 1 and 0.
Bit Digits of a binary system which is 0 or 1.
 694 Appendix C

Binary Coded Decimal (BCD) This code represents decimal numbers in which each decimal digit is repre-
sented by its 4-bit binary code.
Boolean Algebra The algebra of binary variables with operators NOT, AND, and OR.
Boolean Function A function of two valued binary variables. This function has only the value 1 or 0.
Boolean Variable A variable which has only two values either 1 or 0.
Bipolar Logic Logic circuits using bipolar junction semiconductor devices.
BCD Counter This a mod-10 counter that counts from 0000 to 1001, i.e., 0 to 9 decimal numbers.
Binary Counter A group of n flip-flops is connected in such a way that counts binary numbers equivalent to
the number of pulses. After counting 2N number pulses, recycle will be started.
Behavioural Model In behavioural model, statements are executed sequentially just like high level computer
programming language. The PROCESS statement is the main body of this model. In this model sequential state-
ments like sequential statements, variable declarations, if-then-else statements, case, loops, for loop, and while loop
statements are generally used to model the behaviours of digital circuits.
Bistable Multivibrator It is a digital circuit which has two stable states. Its state changes from one stable state
to another stable state when trigger pulse is applied. FLIP-FLOP is example of Bistable multivibrator.
Cut-off State of a transistor when collector current of transistor is zero.
Current Sink Logic In any logic family, the output of a logic circuit sinks current from the input of the logic
circuit.
Current Source Logic In any logic family, the output of a logic circuit sources or supplies current to the input
of the logic circuit.
CMOS (Complementary Metal-Oxide Semiconductor) This MOS device uses one p-channel and one n-
channel MOSFET to make an inverter circuit. This logic family belongs to the category of unipolar digital IC.
Carry Look Ahead Addition The Carry Look Ahead Addition involves two Boolean functions namely
Generate(G) and Propagate(P) for addition of two binary numbers.
Code Converter It is combinational a logic circuit which converts data from one binary code to another binary
code
Combinational Logic The combinational logic circuit generates outputs depending upon inputs. It can be
constructed using logic gates and there is no feedback from output to input.
Comparator A device that compares two binary numbers and produces an output i.e., greater than, or equal or
less than.
Clock A train of rectangular or square pulses. Usually clock frequency is constant and the operation of any syn-
chronous sequential circuit is synchronised with clock.
Counter It is a digital circuit which can count the number of pulses.
Cascade Counters Counters are connected in cascade to develop higher mod counters using small mod coun-
ters. In this counter, the last stage output of one counter is fed to another counter.
Computer Aided Design (CAD) Tools CAD tools are developed to make the design process easy and fast. In
computer-aided design of digital systems, the designers simulate the behaviours of a design digital circuit without
its hardware implementation.
Complex Programmable Logic Device (CPLD) A programmable logic device which contains a large number
of equivalent gates.
Custom Logic Device The logic circuit is fabricated on a single chip.
 Appendix C 695

CAM (Content Addressable Memory) The Content-Addressable Memory (CAM) is a special purpose RAM
device which compares input search data with a table of stored data, and returns the address of the matching data.
Usually CAM is used to implement the lookup-table function.
CCD (Charge Coupled Device) This is actually an array of MOS dynamic shift register sequential memory.
These devices are low cost, very simple construction and versatile. The fabrication procedure of CCD on a semi-
conductor substrate involves very few operations than MOSFET and bipolar technology.
Control Bus This is a bus which is used for handling control signals.
Decoder A device (combinational logic circuit) is used to decode a coded binary word. This logic circuit has n
inputs and one output out of 2n outputs.
De-multiplexer The logic circuit that performs inverse of multiplexing.
D-FLIP-FLOP A FLOP-FLOP whose output follows the input D, when clock pulse is applied.
Decimal Number The number system with base 10 and it has ten symbols 0, 1, 2, 3, 4, 5, 6, 7, 8, and 9.
Digital system This is an electronic circuit which processes digital signals represented by binary forms.
DeMorgan’s Theorems The complement of a sum (OR operation) is equal to the product (AND operation)
of the complements. The complement of a product (AND operation) is equal to the sum (OR operation) of the
complements.
Digital Logic Family This is a group of logic circuits which are built based on standardized integrated circuit
technology. The example of digital logic family are resistor transistor logic (RTL), Direct Coupled Transistor Logic
(DCTL), Transistor-Transistor Logic (TTL), and Complementary Metal-Oxide-Semiconductor Logic (CMOS), etc.
Don’t Care Condition This is an input-output condition which is never occurred during normal operating
condition. We represent the Don’t care condition by X . The value of X will be either 0 or 1.
Dynamic Memory In a dynamic memory, data can be stored on capacitors and to retain data every cell has
to be refreshed periodically. One transistor is used to build memory cell and required less space. These memories
consume less power compared to static RAMs.
Data bus A bus which is used for carrying data between CPU and memory or between CPU and I/O devices.
Digital-to-Analog Converter (D/A converter) An electronic circuit that converts digital input signal to a
corresponding proportional analog voltage or current.
Data Flow Model In dataflow modelling of ARCHITECTURE, concurrent statements are used and also ex-
ecuted concurrently.
Down Counter A counter counts in downward direction from maximum value to 0.
EBCDIC It stands for Extended Binary Coded Decimal Interchange. It is an 8 bit code and used by IBM computers.
Even Parity A binary number with an even number of 1s.
EX-OR Gate In a two input EX-OR gate, output is logic 1 when both the inputs are unequal and logic 0 when
they are unequal.
EX-NOR Gate In a two input EX-NOR gate, output is logic 1 when both the inputs are same.
Enable An input to a latch which be asserted for the flip-flop. When the enable input of latch is high, the output
of latch changes depending upon inputs.
Excitation Table A tabular form representation of the present state-next state of flip-flop with respect to clock.
Edge-triggered FLIP-FLOP A FLIP-FLOP changes its states on the positive or negative edge of a clock pulse.
Encoder This is a combinational logic circuit that generates outputs, i.e., opposite of decoder.
Erasable Programmable ROM (EPROM) In EPROM, a special charge storage mechanism is used to enable
or disable the switching elements of memory. So all switching elements can be programmed electrically and can be
erased by exposure to Ultra-Violet light. Usually CMOS technology is used for manufacturing EPROM.
Electrically Erasable PROM (EEPROM) EEPROM is similar to EPROM but this type of ROM can be
completely erased electrically. There is a limit on the number of times of data erased and programmed. Therefore,
EEPROMs are not used in place of RAM.
 696 Appendix C

Fan-in The maximum number of inputs of a logic gate in a particular family.

Fan-out The maximum number of similar logic gates can be driven by a single logic gate.
Full-Subtactor This is a logic circuit which accepts two one-bit signals and a borrow-in as inputs and generates
the difference bit and borrow bit as outputs.
Full-Adder It is a binary adder with carry-in and carry-out. This logic circuit accepts two one-bit signals and a
carry-in as inputs and generate the sum bit and carry bit as outputs.
FLIP-FLOP It is a one bit memory element in digital systems and it can store either 1 or 0.
Field-Programmable Gate Array (FPGA) This is a flexible architecture programmable logic device contain-
ing very large number of logic gates.
Fixed Architecture It is a Programmable Logic Device with fixed arrangement of logic elements.
Flexible Architecture It is a Programmable Logic Device in which the interconnection of logic elements is
flexible and not restricted.
Finite State Machine It is the most general type of digital circuit whose outputs depend upon both on the
present input signals and the previous input signals. It is a sequential machine which operate cyclically through a
finite set of states.
Free-running multivibrator Same as astable multivibrator.
Gate It is a logic circuit whose output depends upon the inputs and logic operations.
Generic It is a general mechanism to pass information into an entity.
Glitch This is a short sharp pulse.
Gray Code It is a 4-bit BCD code where only one bit changes between successive numbers.
Hexadecimal Number The number system with base 16 and it has sixteen symbols 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
A, B, C, D, E and F.
High-Impedance State This is the third state of a tristate logic (TSL) in which the device is not active and is
disconnected from the circuit.
Hazard This is unwanted glitches due to finite propagation delay of logic circuit.
Half-Adder It is a binary adder with no carry. This logic circuit accepts two single bit inputs and generate the
sum bit and carry bit as outputs.
Half-Subtractor This is a logic circuit which accepts two bits as inputs and generates the difference bit and
borrow bit as outputs.
Hold time The time after the active transition of the clock input to flip-flop, during which control input must be
stable in order to proper change at the output.
Inverter This is a logic gate whose output is the complement of its input.
Integrated Circuit (IC) It is a small semiconductor chip which consists of several electronic circuits, such as
logic gates, encoder, decoder, multiplexer and demultiplexer etc.
I2L(Integrated – Injection Logic) A form of bipolar logic circuit which uses only transistors. This is an alterna-
tive form of DCTL.
Integrated RAM A dynamic RAM in which refresh circuitry is integrated on the RAM chip.
IC Package An integrated circuit chip packaged as a single multi-terminals component.
JK-FLIP-FLOP A FLOP-FLOP whose state changes depending upon J and K inputs and the clock. When both J
and K inputs are logic 0, JK –flip-flop operates as Latch. While both J=K=1, JK –flip-flop operates as Toggle. The
FLIP-FLOP is set when J= 1 and K= 0 and reset when J = 0 and K= 1.
Johnson Counter This is a shift register in which the inverted output of the last flip-flop is connected to the
input of the first flip-flop.
Karnaugh map A graphical representation of any logic function. It is used in logic simplification.
 Appendix C 697

Least-Significant Bit (LSB) LSB is the right-most bit of a binary number. It has the least weight.
Least-Significant Digit (LSD) LSD is the right most digit of a number.
Logic Circuit An electronic circuit that operates on digital signals in accordance with a logic function.
Large Scale Integration (LSI) More than 1000 but Less than 10000 transistors in an IC.
Logic Adjacent Two terms (minterm or maxterm) can be simplified by using logic adjacency. This can also be
applied to 2n terms, where n=1,2,3…
Logic Adjacency This is a logic simplification theorem in two binary terms to be reduced to one such as (A +
– –
B) (A + B ) = A or (AB + AB ) = A.
Latch Latch is a bistable device and it has two states: Set and Reset for indefinite time period. When the Enable
input of Latch is high, the output of Latch changes depending upon inputs.
Level Triggered A device (Latch) which uses either a high or low level signal for transition to the next sate.
Left Shift Register In a shift register, data is shifted in the left direction with respect to clock pulses.
Linearity It is measured from the difference between the actual output voltage and the expected output voltage
of a D/A converter. It is generally specified as ± ½ LSB.
Maxterm It is a logical term which consist of all the literals in the ORed form in logic function.
Minterm It is a logical term which consist of all the literals in the ANDed form.
Most-Significant Bit (MSB) MSB is the left-most bit of a binary number. It has the maximum weight.
Most-Significant Digit (MSD) MSD is the left-most digit of a number.
Medium Scale Integration (MSI) More than 100 but less than 1000 transistors in an IC.
Multiplexer A logic circuit that selects one of ‘n’ input lines and connects it to one single output line.
Maximum Frequency ( fmax ) Maximum clock frequency is the highest clock frequency at which the flip-flop
can be triggered.
Memories Memories can be building up by flip-flops or capacitors in semiconductor memories and magnetism in
magnetic storage. The storage element is called a cell. Each storage element can store either logic ‘1’ or logic ‘0’.
Memory Read Operation To transfer data from the memory to the microprocessor through memory read
operation, 16-bit address bus is used to read from memory.
Memory Write Operation To transfer data from data bus to memory, a memory write operation is required.
Monostable multivibrator A digital circuit which has one stable states and one quasi-stable state. It generates
an output pulse for a fixed time duration when a trigger pulse is applied and then returns to stable state. This is also
known as one-shot circuit.
Mealy Machine In Maly machine, the outputs directly depend both on the present inputs and on the state infor-
mation. The behaviour of Moore machine is defined by equations
Next state=F(Present state, Inputs) and Output=G(Present state, Inputs).
Moore Machine In Moore machine, the outputs depends directly only on the state information. The behaviour
of Moore machine is defined by equations
Next state=F(Present state, Inputs) and Output=G(Present state).
Mask-Programmable ROM (ROM) ROMs are non-volatile memories as initially data is stored in memory
through programming and stored data will not be changed when power supply is removed.
NOT A Boolean operator which changes from 1 to 0 and 0 to 1. This is denoted by an overbar or 1.
Noise Unwanted electrical signals may be present in digital circuits and then digital circuit’s starts malfunction.
Noise Immunity This is circuit’s ability to tolerate noise voltages on its inputs.
Noise Margin It is quantitative measure of the noise immunity.
Negative Edge Triggered A device in which the transition occurs at the negative or falling edge of the clock signal
Next State decoder The part of a state machine that uses logic operations on the present state of a machine and
its input to produce a code, which in turn generates the next state of the machine in the memory.
 698 Appendix C

One’s Complement The number can be obtained by complementing each bit of a binary number.
Octal Number The number system with base 8 and it has eight symbols 0, 1, 2, 3, 4, 5, 6 and 7.
Odd parity A binary number with odd number of 1s.
OR A Boolean operation of two variables indicated by ’ +’. This is represented by A+B
OR Gate It is a logic circuit whose output is 1 if any one input is 1.
Open-Collector Output The output of a digital circuit which is the collector terminal of a Bipolar Junction
Transistor (BJT) not connected to any other point inside the IC.
One-shot Same as monostable multivibrator.
Positional Numbers Number composed of symbols called digits in which the digits have a value based on
position.
Products of Sum (POS) This is a form of logic function in which OR terms are ANDed together.
Priority Encoder This is an encoder which generates output corresponding to the highest priority number when
two or more numbers are applied simultaneously.
Positive Edge Triggered A device in which the transition occurs at the positive or rising edge of the clock signal.
Parallel in Parallel out register In this shift register, data will be loaded in parallel and data output in paral-
lel form.
Parallel in Serial out register In this shift register, data will be loaded in parallel but data output in serial form.
Pressetable Counter It is a programmable counter which has the capability to start counting from any
desired state.
Programmable Logic Device A logic device in which a large number of logic elements are fabricated on a
single chip with programmable interconnections.
Programmable Read Only Memory (PROM) PROMs are fixed architecture logic devices.
Programmable Array Logic (PAL) Fixed architecture logic devices with programmable AND array followed
by fixed OR array.
Programmable Logic Array (PLA) Fixed architecture logic devices with programmable AND array followed
by programmable OR array.
Programmable Logic Device (PLD) A programmable logic device which contains a large number of intercon-
nected logic gates.
PACKAGE A PACKAGE provides a mechanism to hold data to be shared among several entites. A PACKAGE
consists of two parts: a package declaration section and a package body section.
Programmable Design In this design, an array of logic cells is used and signal routing is done through switch
box approach and RAM holds the routing patterns, which is reprogrammable.
Pulse stretcher Same as monostable multivibrator.
Quine-McClusky Method It is a tabular method for logic simplification.
Quasi-stable State This state is not a stable state. Monostable multivibrator is temporarily triggered to move to a
quasi-stable state, and then it return back to its stable state after certain time depending upon the circuit elements.
Quantisation The quantisation of analog signal is to divide the complete amplitude range of analog signal into
number of equal intervals.
Quantisation error The error involved in the quantisation process.
Radix or Base The difference in positional value between two digits which are next to each other in a positional
number system.
Radix Point The point which separates digits with a positional value greater than 1 from those with a positional
value less than 1.
Reset It is represented by not asserted, inactive, false or OFF state
 Appendix C 699

Register It is an digital circuit which can store ‘n’ bits data and each bit is stored in a flip-flop.
Right Shift Register In a shift register, data is shifted in the right direction with respect to clock pulses.
Ring Counter It is a shift register in which the output of the last flip-flop is connected to the input of the first
flip-flop.
Random Access Memory (RAM) In this memory, the access time is same for all memory location.
Refresh The process of recharging the memory cells in a dynamic memory.
ROM Access Time The propagation delay between address inputs and data outputs of a ROM in each READ
operation.
Routing This is the process of interconnecting logic blocks.
Ripple Counter See Asynchronous counter.
Retriggerable Monostable Multivibrator A monostable multivibrator that will response to a triggered pulse
when it is in quasi-stable state.
Resolution The resolution of D/A converter refers to the smallest change in the analog output voltage. It is
equivalent to the value of the Least Significant Bit (LSB).
Schmitt trigger This is a comparator circuit with upper and lower triggering voltages. It exhibits hysteresis ef-
fect. It produces a rapid oscillation free transition at output from a slow changing input signal.
Small Scale Integration (SSI) Less than 100 transistors in an IC
Switching speed The operating Speed of an electronic switch which changes from OFF to ON or ON to OFF.
Generally this is measured in terms of the propagation delay time.
Saturation State of a transistor when collector current of transistor is maximum.
Sum Of Products (SOP) This is a form of logic function in which AND terms are ORed together.
Set It is represented by asserted, active, true or ON state
Set-Reset Memory Cell In a basic memory cell, Set places the cell in an asserted state and Reset places it in
a not-asserted state.
Set up Time The minimum time that input signal must be present on input terminal of flip-flop prior to the trig-
gering edge of the clock pulse.
Sequential Logic The logic circuit whose outputs are produced in the sequence in which input signals are applied.
Subtractor It is a logic circuit used for subtraction.
Stable State A state in which a digital circuit remains until a triggering signal is applied.
S-R FLIP-FLOP This FLIP-FLOP has two inputs S and R. The state of the FF does not change when S= R = 0.
This is set when S= 1 and R = 0 and reset when S= 0 and R= 1. S= R= 1 is not allowed.
Shift Register It is an digital circuit which can accepts binary data from input source and then shifts these data
through flip-flops but one bit data at a time.
Serial in Parallel out register In this shift register, data will be loaded serially and data output in parallel form.
Serial in Serial out register In this shift register, data will be loaded serially but data output is also in serial form.
Synchronous Counter In this counter, all the flip-flops are triggered (clocked) simultaneously.
Self Starting and Self Correcting Counter If the counter should not be able to start from any predefined
state or correct state, the self starting and self correcting counter corrects its counting state.
State Table The tabular form representation of sequential circuit.
Sequential Circuit Any sequential circuit consists of a combinational logic circuit and memory elements.
State Diagram This is a graphical approach of representing how the finite state machine changes from one
state to another state.
State Equation The state equation of a sequential circuit is a Boolean expression which represents the condi-
tions of flip-flop state transition.
 700 Appendix C

Sequential Machines Machines in which output depends on the immediate inputs to the machine but always
depends on the previous condition of the machine. Any sequential machine has a set of conditions for output.
State The condition of a sequential machine.
SPLD (Simple Programmable Logic Device) A programmable logic device which can be used for smaller
logic circuits, such as PLA, and PAL.
Standard Cell Design The standard cell design technique uses a set of predefined blocks, such as adders,
multiplexers, demultiplexers etc. This technique has less flexibility than full custom.
Structural Model In structural modelling, several components are interconnected with input signals. Therefore
all components must be defined in ENTITY and ARCHITECTURE body. The component statement is used to
declare each component, which are used in the netlist.
Sample and Hold Circuit A sample and hold circuit samples the input signal at the required instant and then
holds it when analog to digital conversion process is going on.
Settling Time The time required for the output of a D/A converter to come to and stay within ± ½ LSB of the
full scale analog output voltage when the input changes from all 0s to all 1s.
Successive Approximation ADC In this ADC, a comparator, a DAC, digital control logic and successive ap-
proximation register(SAR) are used for conversion process. The conversion time for this type of analog to digital
converter is always the same regardless of the value of the input analog signal.
Static RAM(SRAM) A static RAM memory cell consists of flip-flops. Flip-flops are set or reset and retain the
data until it’s charge or power is removed. Static RAMs are manufactured by using bipolar transistors, MOS and
integrated injected logic circuitry.
Sequential Memory In sequential memory, data can be written and read sequentially. Shift register is an ex-
ample of sequential memory.
Twos Complement A binary number can be obtained after adding one to the one’s complement of a binary
number.
Ten’s Complement It is 9’s complement of a decimal number plus one.
Truth table It is a table which represents outputs for all possible combinations of inputs to a logic circuit.
Tristate Output The output of a logic circuit has three states 1, 0, or high-impedance states.
Totem-pole Output A circuit with active devices used to pull up the output voltage of a logic circuit from LOW
to HIGH in response to the inputs.
T-FLIP-FLOP A FLOP-FLOP in which the state toggles on the clock if T is asserted.
Universal Gate A gate which can perform all the basic logic operations, such as NAND, and NOR.
Unipolar Logic Logic circuits using unipolar field-effect transistors (MOSFETs).
Up-Down Counter A counter counts in both upward and downward direction, depending upon the control
signal.
Up Counter A counter counts in upward direction from 0 to maximum value.
Very Large Scale Integration (VLSI) More than 10000 transistors in an IC
Variable Map It is extension of Karnaugh Map to develop a map for more variables.
VHDL It is the VHSIC Hardware Description Language. VHSIC is an abbreviation for Very High Speed Inte-
grated Circuit. It can describe the behaviour and structure of digital logic circuits like ASICs, CPLDs, FPGAs and
conventional digital circuits.
Verilog HDL It is a Hardware Description Language. In Verilog, HDL text format is used to describe electronic
circuits and systems. Verilog HDL can be used for verification of electronic design circuits through simulation, and
timing analysis.
Volatile Memory The memory that loses its contents when power is turned off.
 APPENDIX

D
ANSWERS OF MULTIPLE
CHOICE QUESTIONS
CHAPTER - 1
1. (a) 2. (d) 3. (a) 4. (a) 5. (a) 6. (a)
7. (a) 8. (c) 9. (d) 10. (d) 11. (d) 12. (b)
13. (a) 14. (b) 15. (b).

CHAPTER - 2
1. (a) 2. (a) 3. (d) 4. (a) 5. (b) 6. (a)
7. (a) 8.(c) 9. (c) 10. (b) 11. (d) 12. (b)
13. (d) 14. (a) 15. (a) 16. (a) 17. (b) 18.(a)
19. (a) 20. (d)

CHAPTER - 3
1. (b) 2. (a) 3. (a) 4. (d) 5. (a) 6. (a)
7. (a) 8.(a) 9. (a) 10. (d) 11. (b) 12. (b)
13. (b) 14. (a) 15. (a) 16. (c) 17. (a) 18.(a)
19. (a) 20. (a) 21.(a)

CHAPTER - 4
1. (a) 2. (a) 3. (b) 4. (c) 5. (d) 6. (a)
7. (a) 8.(b) 9. (b) 10. (c) 11. (d) 12. (a)

CHAPTER - 5
1. (c) 2. (c) 3. (b) 4. (a) 5. (a) 6. (c)
7. (a) 8. (d) 9. (a) 10. (d) 11. (c) 12. (a)
13. (a) 14. (d) 15. (d).

CHAPTER - 6
1. (b) 2. (a) 3. (b) 4. (b) 5. (a) 6. (b)
7. (d) 8. (d) 9. (b) 10. (c) 11. (c) 12. (a)
13. (a) 14. (a) 15. (b) 16. (b)
 702 Appendix D

CHAPTER - 7
1. (c) 2. (a) 3. (a) 4. (a) 5. (d) 6. (a)
7. (c) 8. (c) 9. (d) 10. (a) 11. (b) and (c) 12. (c)
13. (a) 14. (a) 15. (a) 16. (d) 17. (c) 18.(d)
19. (a) 20. (a)

CHAPTER - 8
1. (c) 2. (a) 3. (a) 4. (d) 5. (b) 6. (b)
7. (a) 8. (d) 9. (a) 10. (d) 11. (b) 12. (c)
13. (b) 14. (d) 15. (c) 16. (a) 17. (c) 18.(b)
19. (a) 20. (d) 21. (c) 22. (d) 23. (c) 24. (b)
25. (c) 26. (a) 27. (a) 28.(d) 29. (a) 30. (c)
31. (c) 32. (a) 33. (c) 34. (c) 35. (a) 36. (c)
37. (b) 38.(b) 39. (a) 40. (a)

CHAPTER - 9
1. (a) 2. (a) 3. (a) 4. (a) 5. (a) 6. (a)
7. (a) 8.(a) 9. (a) 10. (d) 11. (a) 12. (b)

CHAPTER - 10
1. (d) 2. (a) 3. (b) 4. (b) 5. (a) 6. (a)
7. (b) 8. (a) 9. (d) 10. (b) 11. (a) 12. (b)
13. (c) 14. (b) 15. (c) 16. (b) 17. (c) 18. (c)

CHAPTER - 11
1. (b) 2. (a) 3. (b) 4. (a) 5. (d) 6. (a)
7. (c) 8. (c) 9. (d) 10. (b) 11. (c) 12. (b)
13. (c) 14. (a) 15. (a) 16. (c) 17. (c) 18. (a)
19. (c) 20. (d)

CHAPTER - 12
1. (c) 2. (a) 3. (a) 4. (d) 5. (d) 6. (a)
7. (a) 8.(c) 9. (a) 10. (b) 11. (a) 12. (a)
13. (b) 14. (a) 15. (b) 16. (a) 17. (a) 18. (b)
19. (b) 20. (b) 21. (c) 22. (c) 23. (d) 24. (a)
25. (a) 26. (c) 27. (a) 28.(a) 29. (a) 30. (c)
31. (d) 32. (c) 33. (a) 34. (a) 35. (a)

CHAPTER - 13
1. (a) 2. (a) 3. (d) 4. (b) 5. (b) 6. (c)
7. (a) 8. (d) 9. (a) 10. (a) 11. (a) 12. (c)
13. (a) (b) 14. (c) 15. (b) 16. (b) 17. (a) 18.(a)
19. (a) 20. (a) 21. (a) 22. (b) 23. (a)

CHAPTER - 14
1. (a) 2. (a) 3. (a) 4. (a) 5. (b) 6. (a)
7. (c) 8. (a) 9. (b) 10. (c)
 INDEX
Asynchronous counters 326 Bipolar DAC and ADC 478 Classification of sequential
Absorption laws 49, 52
Asynchronous inputs (Preset Bipolar SRAM 506 circuit 357
Acquisition time 439
and clear) 273, 276 Bistable multivibrators 397, Clock oscillator using
ADC 439
Asynchronous sequential 398 BJTs 398
Addend 234
circuit 378 Bit and bit vector 597 Clocked J-K flip-flop 278
Adder 172
Augend 235 BJT characteristics 81 CMOS Characteristics Logic
Advance memory 540
Availability 77, 804 Boolean level, Noise margin, Fan
Advantages of TTL and
CMOS 116 algebra 46, 47 out, Fan in, Propagation
equation 131 delay 111–112
Algorithmic state
machines(ASM) 384
B CD adder 243 expression 55 CMOS gates 107
BCD DAC 438 laws 49, 64 CMOS inverter 108
Analog system 2
BCD to binary converter 216 notations 47 CMOS NAND, AND, NOR,
Analog to digital
BCD to decimal decoder 182 postulates 49 OR 109–110
converter 441
BCD to Excess-3 decoder 209 variables 48, 694 CMOS shift register stage 526
Analog voltage 1
BCD to nine’s Bridge faults 230 Code conversion using Logic
AND gate 48, 50
complement 215 Buffer gate 90 gates 209
AND operation 48
BCD to Seven segment Buffer register 310 Combinational logic circuits
Aperture time 440
display 180 Buffer 61 using gates 651
Applications of DAC and
Behavioral model 602, 631 Bus realisation 96 Combinational logic
ADC 481
Bidirectional Shift Bus 96 design 172
Applications of decoder 178
register 304 Combinational logic 122
Applications of
Binary coded decimal Commutation laws 49, 51
demultiplexer 208
BCD 29 Commutative laws 51
Applications of flip-flops 289
Binary adder using
Canonical POS 129, 130
Comparator 255
Applications of Canonical SOP 129
decoder 179 Comparison between PROM,
multiplexer 198, 233 Canonical forms 123
Binary addition 20, 234 PAL and PLA 579
Applications of shift Carry look ahead addition 244
Binary arithmetics 20 Comparison of flip-flops 289
register 315 Cascade counters 340, 662
Binary digit weight 442 Comparison of logic
Architecture 599 Cascade Demultiplexer 201
Binary division 22, 250 family 85
Arithmetic logic units Cascading decoders 177
(ALU) 251 Binary multiplication 21 Cascading multiplexer 197 Complements laws 49,51
ASCII code 35 Binary multiplier 247 Complex programmable logic
Cascading Priority
ASICs 546 Binary number system 6 devices 583
encoders 190
Binary number 6 Computer aided design
ASM block 386 Cascading SR flip-flops 272
Binary subtraction 21, 238 tools 599
ASM chart 385 CD-R, CD-RW 560
Association laws 49, 51 Binary to BCD converter 218 CD-ROM 560 Conditional output box 386
Astable multivibrators 397, Binary to decimal 7 Characteristics of digital logic Configurable logic block 587
398, 400 Binary to Gray code 31, 214 family 77 Consensus theorem 69–71
Asynchronous decade Binary to gray 31 Characteristics of TTL 96 Construction of Karnaugh
counters 323 Binary to hexadecimal 17 Charge coupled device Maps 144
Asynchronous up-down Binary to octal 13 CCD 527 Contact bounce
counters 324 Binary weighted DAC 450 Classification of counter 318 elimination 291
 704

Content addressable memory, Digital logic family 76 Encoders 183 Fraction decimal number to
CAM 536 Digital number systems 4 Entity 599 binary 9
Conversion Canonical POS to Digital system design 592 EPROM 548, 549 Frequency division 290
Canonical SOP 129–130 Digital to analog Error correcting code 40 Frequency measurement 344
Conversion Canonical SOP to converter 443 Essential Prime Full adder 235, 236
Canonical POS Canonical Digital voltage 1 implicants 143 Full custom design 546
SOP to Canonical Diode transistor logic Even parity 39–40 Full subtractor 239
POS 129 (DTL) 83 Excess-3 code 32 Function generator 505
Conversion one flip-flop to Direct –coupled transistor Exclusive NOR gate 60 Functional simulation 594
other 283 (DCTL) 82 Exclusive OR gate 59
Count down counter 318 Disadvantages of TTL and Extended capacity DAC 454
Counter ICs 326 CMOS 116 Gate sensitivity 230
Counter 326 Display 182 Fall time 100 Gates 46–50
Counters 290, 689 Distribution laws 49, 52 Fan in 79 General positional numbers 5
Counting ADC 466 Don’t cares 150 Fan out 79, 96 Generic 604
Current mode DAC 455 Double Complements laws 51 Fault detection 226 Glitch 220
Current parameters 77–78 DRAM 506–512 Fault of combinational Gray code 30
Drift current 441 logic 226 Gray to Binary code 212
D flip-flop with asynchronous Duality principle 69 Field programmable gate Gray to binary 31
inputs 276 Duel slope ADC 466 array 585 Group 139, 140
D latch with enable 269 Dynamic characteristics 446 Finite state machine 359
D latch 269 Dynamic hazards 220, 225 Five variables Karnaugh
D to T flip flop 285 Dynamic MOS register 521 Maps 142
Half adder / subtractor 241
Half adder 234
DAC 672 Flash converter 472
Half subtractor 238
Flash memory 503
Dark detector 423 E BCDIC Extended
Flip-flop ICs 292 Hamming distance 41
Data flow model 600 binary coded decimal
Decade counters 331, 345 Flip-flop 271, 280 Hamming code 40–42
interchange 37
Hard disk 532
Decimal number 5 ECL Emitter coupled logic 85 Flip-flops 654
Decimal point 5 Edge triggered D flip-flop 275 Floppy disks 533 Hardware description language
Decimal to binary 8 Edge triggered J-K flip- Four bit adder/subtractor 241 (HDL) 595
Decimal to hexadecimal 15 flop 279 Four bit by Four bit Hazard free 225
Decimal to octal 12 Edge triggered S-R flip- multiplication 249–250 Hazards 220
Decimal to Eccess-3(XS3) 32 flop 271 Four bit sign magnitude Hexadecimal number 14
Decision box 386 Edge triggered T flip-flop 281 number 234 Hexadecimal to binary 16
Decoder 174 EEPROM 487–504 Four bit sign magnitude Hexadecimal to octal 17
Effective aperture delay subtraction 238 High threshold logic
Delay time 100
time 441 (HTL) 86
DE-Morgans theorem 49, Four bit subtractor 238
Eight bit ALU 252 Hold time 288
53-55 Four bit binary adder 243
Eight line to one line
Demultiplexer 201 Four bit digital
multiplexer 194
Design entry 593 Eight to three encoder 187
comparator 257 Implementation of
Design of ASM 387 Eight to three Priority Four digit display 182 Boolean functions using
Design of asynchronous encoders 187 Four to 1 line multiplexer 193 PROM 549
sequential circuit 302 Electric eye alarm 422 Four to 2 line Priority Implementation of sequential
Design of counters 337 Elements of Combinational encoders 186 circuits using PROM 551
Design of synchronous logic 122 Four to two encoder 186 Implicant 159
sequential circuit 361 Elimination of Static-0 Four transistor Dynamic MOS Implication table 375
Digital systems 2-3 hazards 223 RAM 515 Instruction manual 644
Digital clock 345 Elimination of Static-1 Four variables Karnaugh Integrated injection logic
Digital comparators 255 hazards 222 Maps 141 (IIL) 86
 Index 705

Interfacing TTL and CMOS frequency 288 Odd parity 39 logic array 558
Intersection laws 49, 50 Maxterm 123 One bit digital logic 546
Inversion operation 47 McClusky method of comparator 255 switch matrix 588
Inverter circuit 81 minimisation 159 One to eight Programming PLA ICs 562
Inverter with feedback 263 Melay machine 358 Demultiplexer 204 PROM devices 548
Memory cell 263 One to four PROM 486, 498
J -K flip-flop with Memory operation 488 Demultiplexer 202 Propagation delay time 287
asynchronous inputs 279 Memory organisation 488 One to sixteen Propagation delay 100
J-K flip-flop 279 Memory 291 Demultiplexer 205 Pulse sequencer 423
J-K master slave flip-flop 279 Metal oxide One’s complement 25 Pulse train 198
J-K to D flip flop 286 semiconductor 102 OP AMPs as astable 411 Pulse width 287
J-K to S-R flip flop 284 Metronome 423 OP AMPs as bistable 408
J-K to T flip flop 285 Minimal SOP form 159 OP AMPs as monostable 413 Quantisation 441
Johnson counters 317 Minimisation of simultaneous OP AMPs 411, 406 Quine McClusky method of
functions 154 Open collector output minimisation 159
K arnaugh Maps 137 Minterms 123, 131 gates 90, 91, 94
R -2R ladder circuit 451
Minuend 238 Operating characteristics of
Race around condition 277,
L aboratory instruction 644 Missing pulse detector 422 flip-flops 287
299
Latch 264 Mod n counter 335 Operational amplifiers 433
Radix point 6
Monostable Optical-disks 534
Least Significant bit RAM expansions 518
multivibrators 431 OR gate 57
(LSB) 319 RAM 506
Moore machine 358 OR operation 48
Least Significant digit Ratioless Dynamic MOS
(LSD) 15 MOS characteristics 107 Output equation 364
register 524
Left Shift register 304 MOS ROM 497 Over flow 27
Reflected code 30
MOS SRAM 517
Literal 122
MOSFET 102
Package 605 Register transfer language 595
Logic circuits using diode and Packed BCD 29 Register 290, 295, 656
MSI ICs 208
transistors 646 Parallel addition 246 Repetitive division 8, 12, 15
Logic circuits using gates 651 MSI Medium scale Parallel converter 483
integration 77 Resistor Transistor logic
Logic circuits 64 Parity generator 39
Multi emitter transistor 83 (RTL) 82
Logic function 131 Parity 38
Multiplexers 190 Resolution 557
Logic gates 46 Partitioning 374
Multivibrator 693 Retriggerable monostable
Logic level 47, 97 Path sensitisation 229 multivibrator 397, 431,
Logic simplification using PIPO Shift register 304
Boolean algebra 132
N
bit adder 259
PISO Shift register 310
699
NAND gate 54 Right Shift register 304
Logic simplification using K PMOS (P channel
Negative logic AND/OR Ring counters 316
Maps 146 MOSFETs) 108
gates 70 Rise time 101
Low level input voltage, input Positive logic AND gate 70
Negative logic 70 ROM access time 493
current, output voltage and Positive logic OR gate 70
Nine’s complement 215 ROM expansions 491
output current 78
NMOS NAND NOR gate 106 Positive logic 70 ROM multiplier 505
Low noise margin 79 Power dissipation 78, 101
NMOS(N channel ROM 498
LSI Large scale integration 77 Presettable counters 342
MOSFETs) 105
Prime implicants 162
Noise immunity 77
M agnetic disks memory 530
Noise margin 99
Priority encoders 186 S-a-0 fault 228
Mask-programmable Product of Sums 123 s-a-1 fault 228
NOR gate 54
ROM 548 Programmable Sample and hold circuit 438
NOT gate 55
Master-slave S-R flip-flop 273 array logic 568 Saturation time 100
Matchline structure 540 O
ctal number 12 counters 344 Schmitt trigger 423
Maximum clock Octal to binary 13 design 546 Schottky TTL 84
 706

Self correcting counter 342 Sixteen to four encoder 185 T flip-flop with asynchronous Two state machine 262
Self starting and self correcting Source current 102 inputs 281 Two to one Multiplexers 191
counters 664 Specification of ADC 474 T flip-flop 286 Two variables Karnaugh
Self starting counter 343 Specification of DAC 437 T latch with enable 281 Maps 137
Sensitisation 229 Speed of operation 77 T to J-K flip flop 285 Two’s complement adder 241
Sequence generator 666 S-R flip-flop with preset and Tabular method of Two’s complement
Sequential circuit 302, 365 clear 272–274 minimisation 159 subtractor 241
Sequential logic 262 S-R flip-flop with asynchronous Two’s complement 25
Tautology 49–50
Sequential memory 520 inputs 273
Ten line to four line Priority
Serial adder 245 S-R latch with enable 268
Serial data to parallel data S-R latch NAND NOR 265
encoders 186 Unidirectional Shift
S-R to J-K flip flop 283 Ten’s complement 216 register 304
conversion 317
S-R to T flip flop 283 Ternary cells 539 Union laws 49
Settling time 440
SRAM 506, 676 Three transistor Dynamic MOS Universal gate 61
Set-up time 288
SSI Small scale integration 77 RAM 517 Universal shift register 311,
Seven bit hamming code 40
Standard cell design 547 Three variables Karnaugh 313
Seven segment
State diagram 362 Maps 124
display 180, 181, 658
reduction 363 Time delay 316
Shift register counters 316
equation 364 Time period 325
V ariable mapping 157
Shift register 303 Verilog HDL 629
table 362 Timer 555 419, 436
Sign magnitude number 24 VHSIC Hardware description
Static -1 hazards 222 Totem pole output gates 88
Sign magnitude binary Static characteristics 444, 446 Transistor in cut-off 47 language (VHDL) 597
subtracter 242 Static hazards 220 Voltage controlled
Sign magnitude 24 Transistor in saturation 46
Structure model 601, 700 oscillators 419
Simple programmable logic Transistor transistor logic
Stuck-at fault 228 Voltage to frequency
devices 582 (TTL) 83
Subtraction using 2’s converter 468
Simplification of logic complement 26 Tristate output 95
Voltage to time converter 469
circuits 64 Subtractor 238-239 Truth table 55
Simultaneous function 154 Subtrahend 239 TTL Logic gates 83
Simultaneous up-down Successive approximation TTL NAND gate 86, 93 Weighted BCD codes 32
counter 324 ADC 470 TTL to CMOS, TTL to TTL, Wired logic capability 80
Single slope ADC 466 Sum term 122 CMOS to CMOS, CMOS to Wired logic symbol 80
Sinking current 103, 113 Sum of Products 123 TTL 114
SIPO Shift register 306 Switched capacitor DAC 456 Two 4 bit binary number
SISO Shift register 308 Synchronous decade division 251
X NOR gate 60
counters 331 XOR gate 59
Six variables Karnaugh Two bit by two bit
Maps 168 Synchronous counters 328, multiplication 248
Sixteen line to 1 line 333 Two bit digital Z (High impedance) 95
multiplexer 195 Synthesis 593 comparator 255 Zero suppression 181