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Static Timing analysis is divided into several parts: Be the first of your f

Part1 -> Timing Paths

Part2 -> Time Borrowing
Part3a -> Basic Concept Of Setup and Hold
Part3b -> Basic Concept of Setup and Hold Violation
Part3c -> Practical Examples for Setup and Hold Time / Violation
Part4a -> Delay - Timing Path Delay
Part4b -> Delay - Interconnect Delay Models
Part4c -> Delay - Wire Load Model
Part5a -> Maximum Clock Frequency
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Part5b -> Examples to calculate the “Maximum Clock Frequency” for different circuits.
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Part 6a -> How to solve Setup and Hold Violation (basic example) Bridging Gap Betw
Acdamia and Indu
Part 6b -> Continue of How to solve Setup and Hold Violation (Advance examples)
Part 6c -> Continue of How to solve Setup and Hold Violation (more advance examples) Follow

Part 7a -> Methods for Increase/Decrease the Delay of Circuit (Effect of Wire Length On the Slew) 303 followers
Part 7b -> Methods for Increase/Decrease the Delay of Circuit (Effect of Size of the Transistor On the Slew)
Part 7c -> Methods for Increase/Decrease the Delay of Circuit (Effect of Threshold voltage On the Slew)
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Part 8 -> 10 ways to fix Setup and Hold Violation.

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This is a general question in most of the interview, what’s the maximum clock frequency for a particular circuit? Or Interviewer will provide some
data and they will repeat the same question. Many of us know the direct formula and after applying that we can come across the final “Ans” but if
someone twist the question. Some -time we become confuse. I motivation of this blog is the same. Several people asked me how to calculate the
max-clock frequency. So I thought that it’s best if I can write something over this.

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Here I will discuss the same but from basic point of view. It has 3 major sections.

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11/9/2017 Maximum Clock Frequency : Static Timing Analysis (STA) basic (Part 5a) |VLSI Concepts
1. In 1st section, we will discuss different definitions with respect to Sequential and combinational Circuits. Posts
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2. 2nd Section contains the basics of “Maximum Clock Frequency”. I will explain why and how you can calculate the max Clock frequency. Comments
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2-4 examples from easy one to difficult one.

As we know that now a days all the chips has combinational + sequential circuit. So before we move forward, we should know the definition of
“Propagation delay” in both types of circuits. Please read it once because it will help you to understand the “Maximum Clock Frequency”
concepts.

Propagation Delay in the Combinational circuits:

Let’s consider a “NOT” gate and Input/output waveform as shown in the figure
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"Timing Paths" : Sta

Timing Analysis (ST
From the above figure, you can define basic (Part 1)
Rise Time (tr): The time required for a signal to transition from 10% of its maximum value to 90% of its maximum value.
Basic of Timing
Fall Time (tf): The time required for a signal to transition from 90% of its maximum value to 10% of its maximum value. Analysis in Physical
Propagation Delay (tpLH, tpHL): The delay measured from the time the input is at 50% of its full swing value to the time the output Design
reaches its 50% value.
"Setup and Hold Tim
I want to rephrase above mention definition as : Static Timing Analy
(STA) basic (Part 3a
This value indicates the amount of time needed to reflect a permanent change at an output, if there is any change in logic of input.
Combinational logic is guaranteed not to show any further output changes in response to an input change after tpLH or tpHL time units Delay - "Wire Load
Model" : Static Timin
have passed.
Analysis (STA) basic
So, when an input X change, the output Y is not going to change instantaneous. Inverter output is going to maintain its initial value for some time (Part 4c)
and then it’s going to change from its initial value. After the propagation delay (tpLH or tpHL - depends on what type of change- low to high or
"Setup and Hold Tim
high to low), the inverter output is stable and is guaranteed not to change again until another input change ( here we are not considering any Violation" : Static
SI/noise effect). Timing Analysis (ST
basic (Part 3b)

Propagation Delay in the Sequential circuits:

"Examples Of Setup
and Hold time" : Sta
In the sequential circuits, timing characteristics are with respect to the clock input. You can correlate it in this way that in the combinational circuit Timing Analysis (ST
every timing characteristic/parameter are with respect to the data input change but in the sequential circuits the change In the “data input” is basic (Part 3c)
important but change in the clock value has higher precedence. E.g in a positive-edged-triggered Flip-flop, the output value will change only after
Delay - "Interconnec
a presence of positive-edge of clock whether the input data has changed long time ago. Delay Models" : Sta
Timing Analysis (ST
So flip-flops only change value in response to a change in the clock value, timing parameters can be specified in relation to the rising (for positive basic (Part 4b)
edge-triggered) or falling (for negative-edge triggered) clock edge.
"Time Borrowing" :
Static Timing Analys
Note: Setup and hold time we have discussed in detail in the following blogs. Setup and Hold part1; Setup and Hold part2; Setup and Hold part3 . (STA) basic (Part 2)
But just to refresh your memories :) , I have captured the definition here along with “propagation delay”.
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Let’s consider the positive-edge flip-flop as shown in figure.
10 Ways to fix SETU
and HOLD violation
Static Timing Analys
(STA) Basic (Part-8)

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Note: In case of flip-flop there is only one propagation delay i.e tclk-Q (clock→Q delay) but in case of Latches there can be two propagation arrived from googl
delays: tClk-Q (clock→Q delay) and tD-Q (data→Q delay). Lation delay we will discuss later. and viewed "10 Wa
So again let me rephrase the above mention definition fix SETUP and HO
violation: Static Tim
This value indicates the amount of time needed for a permanent change at the flip-flop output (Q) with respect to a change in the flip
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When the clock edge arrives, the D input value is transferred to output Q. After tClk−Q (here which is equivalent to tpLH), the output is
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Setup time (tsu) - This value indicates the amount of time before the clock edge that data input D must be stable. A
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Hold time (th) - This value indicates the amount of time after the clock edge that data input D must be held stable. arrived from vlsi-
The circuit must be designed so that the D flip flop input signal arrives at least “tsu” time units before the clock edge and does not change until at expert.com and vie
least “th” time units after the clock edge. If either of these restrictions are violated for any of the flip-flops in the circuit, the circuit will not "Delay - "Wire Loa
operate correctly. These restrictions limit the maximum clock frequency at which the circuit can operate (that’s what I am going to explain in the Model" : Static Tim
next section J ) Analysis
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I hope you may be asking that why there is a need of explaining the combinational circuit propagation delay here. Combinational circuit is always google.de and view
independent of clock, so why combination circuit here. J Ways to fix SETUP
Now the point is combinational circuit plays a very important role in deciding the clock frequency of the circuit. Let’s first discuss an example and HOLD violation: S
try to calculate the circuit frequency, and then we will discuss rest of the things in details. J Timing Analysis (S
Note: Following diagram and numbers, I have copied from one of the pdf downloaded by me long time back. Real-time view · Get Feedjit

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Now let’s understand the flow of data across these Flip-flops.

Let’s assume data is already present at input D of flip-flop A and it’s in the stable form.
Now Clock pin of FF (Flip-Flop) A i.e Clk has been triggered with a positive clock edge (Low to high) at time “0ns”.
As per the propagation delay of the sequential circuit (tclk-Q), it will take at least 10ns for a valid output data at the pin X.
Remember- If you will capture the output before 10ns, then no one can give you the guarantee for the accurate/valid value
at the pint X.
This data is going to transfer through the inverter F. Since the propagation delay of “F” is 5ns, it means, you can notice the valid output
at the pin Y only after 10ns+5ns=15ns (with reference to the positive clock edge- 10ns of FF A and 5 ns of inverter)

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Practically this is the place where a more complex combinational circuit are present between 2 FFs. So in a more complex
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Y, then the Power
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the sum of the propagation delay of all the combinational circuits/devices. (I will explain this in more detail in the next
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section with more example)
Now once valid data reaches at the pin Y, then this data supposed to capture by FF B at the next clock positive edge (in a single cycle
circuit).
We generally try to design all the circuit in such a way that it operates in a single clock cycle. Multiple clock cycle circuit are
special case and we are not going to discuss that right now (as someone says – it’s out of scope of this blog J )
For properly capturing the data at FF B, data should be present and stable 2ns (setup time) before the next clock edge as part of
setup definition).
So it means between 2 consecutive positive clock edge, there should be minimum time difference of 10ns +5ns +2ns = 17ns. And we can say
that for this circuit the minimum clock period should be 17ns (if we want to operate the circuit in single clock cycle and accurately).
Now we can generalize this
Minimum Clock Period = tclk-Q (A) + tpd (F) + ts (B)
And “Maximum Clock Frequency = 1/(Min Clock Period)”

Now at least we have some idea how to calculate the Max clock frequency or Min Clock Period. So even if we will forget the formula then we can
calculate our self and we can also prove the logic behind that. Let me use the same concept in few of the more complex design circuit or you can
say the practical circuit.

Wire Load Model (Previous) Index Examples: Calculating Maximum Clock Frequency (Next)

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Reactions: Excellent (4) Good (3) Interesting (1) Need More (2)

14 comments:
Anonymous June 18, 2013 at 2:45 AM

Isn't the output of not gate supposed to be inverted?

Reply

Replies

Anonymous February 14, 2015 at 9:57 PM

yes ..I also thinks so.

VlsiExpertGroup February 15, 2015 at 4:13 AM

you both are correct. I will correct soon.

Anonymous January 12, 2016 at 9:36 PM

how soon? :-/

Reply

Ishita Jain July 18, 2013 at 9:44 AM

This comment has been removed by the author.

Reply

Anonymous August 5, 2013 at 9:46 PM

Hi
while defining set-up/hold time in the previous blogs it is assumed that data/clock will arrive late due the delay form actual input to D(FF)/clk(FF).if the
delay is already specified (as in the above problem for calculation of max clock) do we need to consider the set-up of FF again.
is that the delay specified is varying?
please clarify..
Thanks

Reply

Anonymous October 19, 2014 at 12:16 PM

Hello..

Tclk-q + Tcomb - Tsu <= Tclk to avoid setup violation.

So, Max frequency calucation -> Tclk-q + Tcomb - Tsu (this will give the clock period of the max freq clock)
Hence, 10+5-2 = 13 is the period & 1/13 is the frequency.

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Anonymous October 19, 2014 at 12:23 PM

ignore prev comment...

It should be Tclk-q + Tcomb + Tsu <= Tclk, so your calculation of 10+5+2=17 is correct

Reply

Nishant Mittal September 17, 2015 at 11:22 PM

Hi,
In http://www.vlsi-expert.com/2011/05/example-of-setup-and-hold-time-static.html you have used Max Freq=1/Max(Time) here you have mentioned
1/Min(time) . I guess the 2nd one is write.

Reply

Replies

Anonymous July 4, 2017 at 12:33 PM

setup eqn
Tcomb(max) + Tc2q(max) + Tsu >= Tclk + Tskew(min)(assuming +ve skew)
ie
data path delay(max) = clock period(min)
here he is talking about clock period, in previous blog he talked about data path delay
conclusion
both are correct as both are same

Reply

Anonymous January 27, 2016 at 5:26 PM

Hello Sir,

Can you please post a detailed explaination on the Effect of Jitter on the Setup and Hold time requirements.

I read somewhere that Jitter effects only Setup but not Hold time. But I don't know Why it is...

Will you please help me to figure it out.

Reply

Anonymous December 16, 2016 at 4:46 PM

hello,can u please explain how to calculate overall frequency of the system,if it operates at different frequencies

Reply

Replies

VLSI EXPERT December 28, 2016 at 4:16 PM

If its operate at different frequency ...then you have to mention all of them. but just in case you need only 1 frequency ... then you have to
see what's the input clock frequency of the system. Inside the system... whatever you do with that frequency (double or half), no one care
about that.

Reply

slither io October 30, 2017 at 12:34 PM

Many thanks for sharing this very diverse opinion post where each expert has no doubt shared his best knowledge on the topic. Have more success in
your journey.

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