11/9/2017 Effect of Threshold voltage: Static Timing Analysis (STA) Basic (Part-7c) |VLSI Concepts

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Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6 Chapter7 Chapter8

STA & SI
Introduction Static Timing Analysis Clock Advance STA Signal Integrity EDA Tools Timing Models Other Topics

Chapter1 Chapter2 Chapter3 Chapter4 Chapter5 Chapter6

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DFM Introductio Parasitic Interconnect Corner (RC Manufacturing Effects and Their Dielectric Process Other
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Static Timing analysis is divided into several parts:

Part1 -> Timing Paths

Part2 -> Time Borrowing
Part3a -> Basic Concept Of Setup and Hold
Part3b -> Basic Concept of Setup and Hold Violation
Part3c -> Practical Examples for Setup and Hold Time / Violation
Part4a -> Delay - Timing Path Delay
Part4b -> Delay - Interconnect Delay Models
Part4c -> Delay - Wire Load Model
Part5a -> Maximum Clock Frequency VLSI EXPERT (v
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Part5b -> Examples to calculate the “Maximum Clock Frequency” for different circuits.
Bridging Gap Betw
Part 6a -> How to solve Setup and Hold Violation (basic example) Acdamia and Indu

Part 6b -> Continue of How to solve Setup and Hold Violation (Advance examples)
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Part 6c -> Continue of How to solve Setup and Hold Violation (more advance examples)
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Part 7a -> Methods for Increase/Decrease the Delay of Circuit (Effect of Wire Length On the Slew)
Part 7b -> Methods for Increase/Decrease the Delay of Circuit (Effect of Size of the Transistor On the Slew)
Part 7c -> Methods for Increase/Decrease the Delay of Circuit (Effect of Threshold voltage On the Slew)
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Part 8 -> 10 ways to fix Setup and Hold Violation.

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11/9/2017 Effect of Threshold voltage: Static Timing Analysis (STA) Basic (Part-7c) |VLSI Concepts
Effect of Threshold voltage on the propagation delay and transition delay:

If you will see the below equations – I am sure you can easily figure out how threshold voltage effect the cell delay. (Note: Below
Resistance formula is with respect to NMOS. You can derive similar formula for PMOS also (Just replace subscript “n” with “p” J
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Edusaksham
VLSI - Self...
INR 5,750.00

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From above equation we have following points
On Resistance of MOS is inversely proportional to the “VDD-VTn” (where VTn is Threshold Voltage).
Decreasing the threshold voltage (LOW VTn) increases “VDD-VTn” for constant VDD.
Increasing “VDD-VTn” means decreasing “On Resistance” Rn.
Decreasing Rn à RC decreases.
Means large Driving capability (Ability to source or sink current)
Decrease the time to charge the output load (capacitance) (Consists of source/drain capacitance of the driving
Edusaksham
gate, the routing capacitance of wire, and the gate capacitance of the driven gate) ** VLSI - Static...
Means “Output Transition time of Gate A” and “Input Transition time for Gate B” decreases. INR 2,300.00
Decreasing the transition time means decreases the propagation time.
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So we can say that…

"Delay can be reduced by using low Vt cells, but the cost paid is high leakage power"
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Direct effect is that low Vt cells are often more leaky i.e. leakage power increases.
If still you have any confusion below diagram should clarify your doubts. "Timing Paths" : Sta
Timing Analysis (ST
basic (Part 1)

Basic of Timing
Analysis in Physical
Design

"Setup and Hold Tim

: Static Timing Analy
(STA) basic (Part 3a

Delay - "Wire Load

Model" : Static Timin
Analysis (STA) basic
(Part 4c)

"Setup and Hold Tim

Violation" : Static
Timing Analysis (ST
basic (Part 3b)

"Examples Of Setup
and Hold time" : Sta
Timing Analysis (ST
basic (Part 3c)
I hope above diagram should clear your doubts about the effect of Threshold voltage on Delay.

Delay - "Interconnec
In the next post we will summarize/list down all the methods of fixing the setup and hold violations. Delay Models" : Sta
Timing Analysis (ST
basic (Part 4b)

"Time Borrowing" :
Static Timing Analys
(STA) basic (Part 2)

5 Steps to Crack VL
Effect of Size of the Transistor On the Slew (Previous) Index 10 ways to fix Setup and Hold Violation (Next) Interview

10 Ways to fix SETU

and HOLD violation
Static Timing Analys
You might also like:
(STA) Basic (Part-8)

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11/9/2017 Effect of Threshold voltage: Static Timing Analysis (STA) Basic (Part-7c) |VLSI Concepts

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