Conway’s Game Of Life On FPGA

Mojo V2 FPGA Development Board

Abstract initial conditions, the cells form

various patterns throughout the
The main aim of this project was to course of the game.
implement Conway’s game of life (a
cellular automata) on a grid of Conway’s game of life is a zero
16x16 led matrices. This was later player game and is governed by
upgraded to work on a VGA display. simple rules. The real challenge to
us was implementation using FPGA.
We have used Mojo V2 FPGA
Development board; our design uses FPGA (Field Programmable Gate
its parallelization and is hence fast. Arrays), unlike microcontrollers, do
nothing by themselves and the entire
We tried to make it interactive but it hardware has to be coded. This also
was not implemented due to the power of FPGA
technical difficulties. The game of
life is much more interesting if it’s
interactive. Motivation behind the Project
Introduction FPGAs are capable of ‘parallel
The Game of Life is not just a processing’ which means that they
typical computer game. It is a can simultaneously perform several
'cellular automaton'. Cellular operations which otherwise have to
automata are discrete, abstract be performed sequentially. We have
computational systems that have exploited this property of FPGA to
proved useful both as general manipulate the next stage every cell
models of complexity and as more in our game according to its
specific representations of non- neighbourhood cells simultaneously.
linear dynamics in a variety of As clear from the description, the
scientific fields. execution this way is considerably
faster than one-by-one method. This
The Game of Life is a simulation of factor will be noticeably significant
a collection of cells which, based on once the setup is scaled up. This
a few mathematical rules, can live, makes it ideal to study cellular
die or multiply. Depending on the

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automata as the processes  84 digital IO pins
necessarily don’t occur sequentially.
 8 analog inputs
 8 general purpose LEDs
Background Theory
 1 reset button
The game of life by John Conway
runs on simple rules as follows:  1 LED to show when the
FPGA is correctly configured 
1. A live cell with fewer than
two live neighbours dies, as if  On board voltage regulation
caused by under-population. that can handle 4.8V - 12V
2. A live cell with two or three  A microcontroller
live neighbours lives on to the (ATmega16U4) used for
next generation. configuring the FPGA, USB
3. A live cell with more than communications, and reading
three live neighbours dies, as the analog pins
if by overcrowding.
4. A dead cell with exactly three  On board flash memory to
live neighbours becomes a store the FPGA configuration
live cell, as if by reproduction. file

A prerequisite for working on FPGA

was to learn a HDL-Hardware
Descriptive Language. For FPGA
one can code in Verilog or VHDL.
We learnt the former. Each set of
commands in Verilog is executed
simultaneously as mentioned earlier
for parallel processing.

Mojo V2 FPGA Development Board

Implementation Details Source: embeddedmicro.com
Hardware:
The FPGA development board we For the first stage of implementation
used is Mojo V2. The Mojo features i.e. simulation of the game of life on
include a 16X16 LED matrix we used four
8X8 LED matrices shorted
 Spartan 6 XC6SLX9 FPGA
appropriately to effectively work as
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a 16X16. Each LED matrix we used  HS and VS (horizontal and
was a 26 pin matrix 10 pins of which vertical synchronization)
are not required for lighting it up.
All we needed to do is get a monitor
Following is the pin description of
for VGA display and a female VGA
the LED matrix used:
connector and connect the 15 pins in
the following manner:

Source: fpga4fun.com/PongGame

In order to light up an LED, the  Pins 13 and 14 of the VGA

column-pin(C) corresponding to it connector (HS and VS) are
has to be given high and the row-pin digital signals so can be
has to be grounded. For e.g.: for driven directly from two
LED(3, 4) we have to set R =0, FPGA pins.
C4=1and other row-pins have to be  Pins 1, 2 and 3 (R, G and B)
1 and column-pins 0. are 75Ω analog signals with
nominal values of 0.7V. With
These pins have to be connected to 3.3V FPGA outputs, use three
the I/O pins of the Mojo board. 270Ω series resistors. The
There are some pins which are by resistors form voltage dividers
default connected to the elements with the 75Ω resistors in the
like the Reset button and internal monitor inputs so that 3.3V
LEDs in the mojo board itself and become
this has to be taken care of. 3.3*75/(270+75)=0.72V,
For the second stage of the project which is close to 0.7V
i.e. simulation of game of life using  Pins 5, 6, 7, 8 and 10 are
VGA display: A VGA monitor ground pins.
requires 5 digital signals to display a
picture:
Software Platform:
 R, G and B (red, green and
blue signals).
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We have used ISE(Integrated switches and lighting a single
Software Environment) design LED in the LED matrix.
suite 14.7 by XilinxXilinx
Following is the entire code
ISE(Integrated Software
used for this version of the
Environment) is a software tool
game of life:
produced by Xilinx for synthesis
and analysis of HDL designs, In the main module, in which all
enabling the developer to modules are instantiated and
synthesize their designs, perform from where input/outputs from
timing analysis, examine RTL external hardware of the set-up
diagrams, simulate a design's are taken, we have three modules
reaction to different stimuli, and instantiated, namely ‘pin’, ‘copy’
configure the target device with and ‘light’ in the following
the programmer. One can manner:
simulate the hardware using pin p(
iSim. However the coding in
.clk(c1),
iSim does not work on FPGA.
Testbenches /Test-fixtures are .arr(arr),

meant for simulation part only. .next(next),

.rst(rst)
);
We descried small blocks of
hardware named modules. Inputs
and outputs of each module are copy c(
needed to be specified in the .rst(rst),
beginning and way it processes
.clk(clk),
the inputs and outputs are needed
to be specified after that. For .arr(arr),
more on syntax and rules see .next(next)
section on code. A module once );
created can be instantiated in any
other module keeping in mind the
hardware feasibility. light pov(
.clk(clk),
.test(next),
Code for Version 1:
.R(R),
Initially the team wrote small .C(C)
modules to light internal/ external
);
LEDs with internal/external

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Here R and C are the arrays of i.e. the next state of our cellular
I/O pins in mojo board to which grid. The module ‘copy’ assigns
row and column pins of the LED the values in next to
matrix (16X16) are connected. R corresponding cells in arr.
and C are defined as outputs from
The module ‘light’ is for POV.
the mojo-top. We had to
Any state of the game of life is
configure these pins in the
being displayed using Persistence
mojo.ucf file; mojo.ucf is where
of Vision. This is the module
we configure the I/O pins of the
which sends output to R and C
mojo board with some pins
pins. This module takes as input
configured by default to internal
a 256 bit array and depending on
elements of the board.
the state of each LED lights up
The default clock of the board each of them one by one at a
(clk) is a 50 MHz clock which is frequency of 50 MHz.
too fast to have a noticeable
The module ‘pin’ takes as input
updating of present state of the
the array arr, i.e. the present state
cell to the next. C1 is a 1 Hz
of the LED matrix and its
clock which has been slowed
function is to give the next state
down using the following
of the matrix in form of output
module:
next following the rules of the
module count (clk, b); game of life. In other words,
input clk; // synthesis according to the present state of
attribute PERIOD clk "50 MHz" the neighbouring cells of the cell
reg [25:0] count = 0; under consideration, it assigns
output reg b = 0; // one pulse per
the next state of the cell in the
second array next. For checking the
rules, we simply add the states
(1-live, 0-dead) of the neighbours
always @ (posedge clk) begin
and compare. For e.g. if arr[x] is
b <= (count == 50000000 - 2); live and the neighbours add upto
count <= b ? 0 : count + 1; 5, we assign next[x] to be a dead
end
cell.

endmodule The matrix is refreshed to its

initial seeding each time the reset
For reference to any LED in the
button on the mojo board is
LED matrix we used a 256 bit
pressed. As mentioned earlier,
array. The LED (i, j) is referred
the updating of the state occurs at
by arr[i*8+j]. The other 256 bit
a frequency of 1 Hz.
array, next is the updated state,

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All these modules run parallel to CounterX <= CounterX + 1;
give fast execution. If always @(posedge clk)
summarized, the ‘pin’ module if(CounterXmaxed)
initializes and updates the states.
CounterY <= CounterY + 1;
The ‘light’ module implements
POV for displaying the current endmodule
state. The module ‘copy’ copies Module vga:
the array next onto array arr.
module vga(input clk, input [9:0]
Code for Version 2: CounterX, input [9:0] CounterY, output
vga_HS, output vga_VS
This version of Conway’s game
);
of life gets displayed on a VGA
reg vga_HS, vga_VS;
screen. This is not as elegantly
simple as version-1. always @(posedge clk)

The modules for the slowed begin

down 1Hz clock (module: timer) vga_HS <= (CounterX[9:4]==0); //

and for copying (module: copy) active for 96 clocks
remain the same. For horizontal vga_VS <= (CounterY==0); // active for
and vertical synchronization 2 clocks
pulse generator we are using two end
modules, namely counter and endmodule
VGA. CounterX counts 768
values (from 0 to 767) and
CounterY counts 512 values (0 to To define cells for the game we
511). The two modules are: have hardcoded the blocks in this
Module counter: way:
block[0] =
module counter(input clk, output
((CounterX>=200&&CounterX<220)&&(Cou
CounterX, output CounterY nterY>=200&&CounterY<220))
);
The entire pin module has been
reg [9:0] CounterX; shifted to mojo-top, so the
reg [9:0] CounterY; updating of the grid occurs at the
wire CounterXmaxed = (CounterX==767); same block of hardware as the
display output.

always @(posedge clk)

In order to make a color be
displayed in the block we
if(CounterXmaxed)
defined, we assign the block
CounterX <= 0; signal to the color signal output
else in this way: R = block[x];
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Block Diagram:

16X16 LED Matrix

Mojo V2

Female VGA
Connector

Out to VGA Monitor

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Limitations and Compromises  Another idea is to simulate
spread of diseases and
There are some limitations to the
mutation at cellular level.
latest version of the project:
 There are several more
 The code for initial seeding applications of FPGAs.
needs to be changed whenever One of the ideas we were
a different initial seed is considering is making a
needed. genetic algorithm solver
 The code is not robust at using FPGAs.
present. For scaling up the  FPGAs can be used in bots
display, the code has to be making their execution
changed significantly, faster due to parallel
especially when it comes to processing.
VGA display which mainly  To emphasize on the scope
involves hard coding. of FPGA: it can be used to
 We haven’t been able to design any circuit be it a
implement user interfacing to simple AND gate or a
the game till now. Once the microprocessor.
game is set on, user can not
change the state of a desired
cell. References
 http://embeddedmicro.com/tut
Future Prospects and Scope orials/mojo/
 User interfacing can be  https://www.youtube.com/wat
added to the game. This ch?v=pkJAWpkaiHg
would mean the user can
set the initial seeding and  http://www.asic-world.com/
further user can access any
cell and change its state in  http://www.fpga4fun.com/Pon
run-time of the game. gGame.html
 There can be more than
two states associated with
each cell corresponding to
growth and aging using a
color gradient instead of
just one color.

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Team: E_Trix

Team Members:
Avani Samdariya,
Krati Agrawal,
Samyak Jain, and
Sanjari Srivastava

Acknowledgements:
Arjun Bhasin
Avi Singh (Mentor)
Kevin Jose
Piyush Awasthi