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Digital Design Lab: Snehangshu Bhattacharya 33 A 10900316057 4th

The document summarizes two digital logic designs: 1) A decade counter using JK flip-flops that counts from 0 to 9 and then resets. Its circuit, truth table, and state diagram are described. 2) A 4-bit ripple counter using T flip-flops that counts from 0 to 15 in a serial fashion. Its circuit, truth table, and state diagram are also outlined. The report was written by a student for a digital design lab course.

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87 views7 pages

Digital Design Lab: Snehangshu Bhattacharya 33 A 10900316057 4th

The document summarizes two digital logic designs: 1) A decade counter using JK flip-flops that counts from 0 to 9 and then resets. Its circuit, truth table, and state diagram are described. 2) A 4-bit ripple counter using T flip-flops that counts from 0 to 15 in a serial fashion. Its circuit, truth table, and state diagram are also outlined. The report was written by a student for a digital design lab course.

Uploaded by

John Doe
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Digital

Design Lab
Report

Name: Snehangshu Bhattacharya

Roll No.: 33 Section: A University Roll: 10900316057

Year: 4th

Netaji Subhash Engineering College


1. Design a Decade counter
using flipflop
A decade counter is a digital counter that can count ten digits. It can count from 0000,
0001, 0010, … up to 1010.
A 4-bit asynchronous/ripple up counter can easily be converted to a decade counter by
clearing each of the flipflops (T or JK) after the value 1010, i. e. when the output of Q_B
and Q_D becomes 1.

Circuit Diagram
The Circuit was simulated in Multisim with the following components:
1. 1x 7-segment LED display
2. 1x BCD to 7-segment decoder IC (74LS47N)
3. 4x JK flip flop IC (74LS112D)
4. 1x NAND IC (7400N)

2
Truth Table
Truth table of decade counter is given below:
Flip-flop outputs
Input Pulses Q_D (MSB) Q_C Q_B Q_A (LSB)
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
0 0 0 0 0 (reset)

Flow/State Diagram
Reset all of the flipflops in this state
0000
1001 0001

1000 0010

0111 0100

0110 0101

3
2. Design a 4-bit ripple counter
A n-bit ripple counter is an asynchronous counter that can count up to 2n states. A ripple
counter can be made by serially connecting ‘n’ JK or T flipflops. The clock pulse is only
given to the first flipflop which outputs LSB and the clock ripples through the stages of
flipflops, that is the reason behind naming them ripple counters. Some features of the
ripple counter are:
1. Ripple counters are asynchronous.
2. They are slower than their synchronous counterparts.
3. They are easy to implement as there is no need to solve complex Boolean Logic
using k-map.
4. The clock input is given to the LSB and the last flipflop in the series acts as MSB.
A 4-bit ripple counter is implemented using 4 T-flipflops in this experiment.

Circuit Diagram
The circuit was simulated in Multisim with the following components:
1. 4x T flip flop (Generic)
2. 2x oscilloscope to view the waveforms

4
Truth Table
Truth table of 4-bit ripple counter is given below:
Flip-flop outputs
Clock pulses Q_D (MSB) Q_C Q_B Q_A (LSB)
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
16 0 0 0 0

5
Flow/State Diagram
0000
1111 0001

1110 0010

1101 0011

1100 0100

1011 0101

1010 0110

1001 0111
1000

Plots
1. Plot of the 4-bit stages (Q_A, Q_B, Q_C, Q_D):

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2. Plot of the clock and the final stage:

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