Lecture 2:

Introduction to System
Design, VHDL Basics
TIE-50206 Logic Synthesis
Arto Perttula
Tampere University of Technology
Fall 2017
Contents
• 1. Introduction to System Design
– Abstraction
– Main phases
• 2. VHDL basics
– Entity – the interface
– Architecture – the behavior
– Continues next week

Arto Perttula 26.10.2017 2

Acknowledgements
• Prof. Pong P. Chu provided ”official” slides for
the book which is gratefully acknowledged
– See also: http://academic.csuohio.edu/chu_p/
• Most slides were originally made by Ari Kulmala
– and other previous lecturers (Teemu Pitkänen, Konsta
Punkka, Mikko Alho, Erno Salminen…)

Arto Perttula 26.10.2017 3

1a. Representation (View) and Abstraction

1. INTRODUCTION TO
SYSTEM DESIGN
Arto Perttula 26.10.2017 4
Examples of Different Views
• View: different perspectives of a system
1. Behavioral view:
– Describe functionalities and I/O behavior
– Treat system as a black box
2. Structural view:
– Describe the internal implementation
(components and interconnections)
– Essentially a block diagram (or schematic)
3. Physical view:
– Add more info to structural view: component size, component locations, routing wires
– E.g., layout of a print circuit board

Arto Perttula 26.10.2017 5

Examples of Different Views (2)
inputs:
button0_in, button1_in
...

outputs:
led0_out
audio_out
...

Function:
When user presses
button1, then...
When...

1. Behavioral 2. Structural 3. Physical

higher abstraction
Arto Perttula 26.10.2017 6
Complexity Management
• Q: How to manage complexity for a chip with 10 million transistors?
• A: Abstraction – a simplified model of a system
– Show the selected features
– Ignore many details
• E.g., timing of an inverter

Arto Perttula 26.10.2017 7

Levels of Abstraction in HDL
1. Transistor level, lowest abstraction
2. Gate level
3. Register transfer level (RTL)
– Typical level nowadays in addition to structural
4. Behavioral (Processor) level, highest abstraction
5. (Manager view: everything works just by snapping fingers…)
• Characteristics of each level
– Basic building blocks
– Signal representation
– Time representation
– Behavioral representation
– Physical representation
Arto Perttula 26.10.2017 8
 Summary of Abstractions
Example Course
Level block

ELT-
xxxx

DigiPer.
Dig Suunn
adder
divide Dig.Suunn.
FSM
this
SW CPU MEM
behavioral NOC System
I/O ACC design

This course focuses on RTL

Arto Perttula 26.10.2017 9
Behavioral Description
• An untimed algorithm description with no notation of time or registers (or
even interface)
• The tools automatically place the registers according to the constraints set
by the designer
• E.g., FFT described in Matlab/C
• The designer gives constraints to a behavioral synthesis tool
– Maximum latency, clock frequency, throughput, area
– Interface
• The tool explores the design space and creates the timing-aware circuit
• Not very well supported yet

Arto Perttula 26.10.2017 10

Register-Transfer Level (RTL)
• Typically, HW description languages use RT level
• The idea is to represent the combinational logic before registers
– The logic between registers, i.e., between register transfers
• The registers are ”implied” not explicitly defined in VHDL
– Synchronous processes imply registers and are covered later lectures
• Combinatorial logic is created by synthesis tool and depends on
1. Right-hand-side of the signal assignment (e.g. x_r <= a+b;)
2. Preceding control structures (if sel=’1’, for(i=0;i<9;i++)…)
Explicitly defined Implied by coding style Note that you can
create purely
x_r combinatorial logic
inputs

Comb.
D Q using RTL
logic
abstraction
11
Register-Transfer Level (RTL) (2)
• RT (Register Transfer) is a bit misleading term
• Two meanings:
1. Loosely: represent the module level
2. Formally: a design methodology in which the system operation is described by how the data is manipulated
and moved among registers

Time_instant Value of a_r Value of b_r Value of c_r

Clock
tick
T0 x0
T1 x1 foo(x0)

T2 x2 foo(x1) bar(foo(x0))
a_r b_r c_r
...,x1,x0 D Q foo() D Q bar() D Q
12
 Key for Success: Hierarchy

• All systems are designed and

implemented hierarchically
• The same component can be
replicated and used in many
products
• Usually only knowledge of
external behavior is required,
not the internals
Arto Perttula 26.10.2017 13
Structural VHDL Description
• Circuit is described in terms of its components
• High-level block diagram
• Black-box components, modularity
• For large circuits, low-level descriptions quicky become impractical
• Hierarchy is very essential to manage complex designs

Syntax:
Corresponds to the entity

Parameters

Ports

Arto Perttula 14
Example
• A hierarchical two-digit decimal counter
– pulse=1 when q is 9
– p100=1 when both q_ten and q_one are 9
– However, if en goes 0 when q=9, something strange happens…
• Let’s concentrare on the structure…
Top-level block diagram, ”hundred_counter”
Single
counter
component

15
Example Implemented in VHDL
Top-level entity

Instantiate the counters as in schematic and

connect the signals to ports.
Notation for mapping ports:
<port name in the component> =>
<signal name or port in higher
level>

”We will use an existing

component called
dec_counter”
Internal signals
Arto Perttula 26.10.2017 16
1b. Development Tasks

1. INTRODUCTION TO
SYSTEM DESIGN
Arto Perttula 26.10.2017 17
System Development
• Developing a digital system is a refining and validating process
• Main tasks:
I. requirements

I-III. verification
capture, specification

II. design, synthesis

III. physical design

time IV. fabrication, testing

Arto Perttula 26.10.2017 18
I. Specification
• Capture the
1. use cases, requirements
2. non-functional requirements (performance, cost, power consumption,
silicon area)
• Usually informal, natural language (English, Finnish) completed with
tables and illustrations
– Formal methods are being studied and their importance will increase

Arto Perttula 26.10.2017 19

II. Design, Synthesis
• A refinement process that realizes a description with components from the lower
abstraction level
– Manual/automated
• The resulting description is a structural view in the lower abstraction level
– A synthesis from VHDL code obtains netlist (gates and flip-flops)
– Estimates the size, maximum frequency and power consumption
• Type of synthesis:
– High-level synthesis
– RT level synthesis
– Gate level synthesis
– Technology mapping
• Emphasis of this course

Arto Perttula 26.10.2017 20

III. Physical Design
• Placement of cells and routing of wires
– Refinement from structural view to physical view
– Derive layout of a netlist
• Circuit extraction:
– Determine wire resistance and capacitance accurately to estimate
timing and power
• Others
– Derivation of power grid and clock distribution network, assurance of
signal integrity etc.

Arto Perttula 26.10.2017 21

I-III. Verification
• Check whether a design meets the specification and performance
goals
• Concern the correctness of the initial design and the refinement
processes
• Two aspects
1. Functionality (e.g., is the answer 42?)
2. Non-functional (e.g., performance)
• Takes ~40-80% of design time

Arto Perttula 26.10.2017 22

I-III. Methods of Verification
1. Simulation
– Spot check: cannot verify the absence of errors
– Can be computationally intensive
2. Hardware emulation with reconfigurable HW
– Almost real-time, connection to external devices
3. Timing analysis
– Just check the worst case delay, automated
4. Formal verification
– Apply formal mathematical techniques to determine certain properties, applicable only in small scale
– E.g., equivalence checking between two models
5. Specification/code review
– Explain the design/specification to others and they comment it
– Surprisingly powerfull!

Arto Perttula 26.10.2017 23

IV. Testing
• Testing is the process of detecting physical defects of a die or a package
occured at the time of manufacturing
– Testing and verification are different tasks in chip design
• Difficult for large circuit
– Must add auxiliary testing circuit into design
– E.g., built-in self test (BIST), scan chain etc.
– Some tests with specialized test-SW running on chip
• Locating the fault is not always needed
– Faulty chips simply discarded
• Basic tests are done at wafer-level
– Sub-set of tests also for packaged chips
Arto Perttula 26.10.2017 24
1c. Development Flow

1. INTRODUCTION TO
SYSTEM DESIGN
Arto Perttula 26.10.2017 25
EDA Software
• EDA (Electronic Design Automation) software can automate many tasks
• Mandatory for success together with re-use!
• Can software replace human hardware designer? (e.g., C-program to chip)
• Synthesis software
– Should be treated as a tool to perform transformation and local optimization
– Cannot alter the original architecture or convert a poor design into a good one
– See also the so called ”Mead & Conway revolution”
• EDA tools abstraction level in functional description has not increased
significantly since mid-90’s when RT-level gained popularity
– Increased abstraction always causes some penalty in performance, area etc.
when increasing abstraction, but significant improvement in time to design
Arto Perttula 26.10.2017 26
Design Flow
data file process

Synthesis Physical Design Verification

• Medium design targeting FPGA RTL 1 1

description testbench

• Circuit up to 50,000 gates synthesis 3 simulation 2

• Note the test bench development at netlist delay file

the same time as RTL (or before

that) placement & 54 simulation 4
routing

• Large design targeting FPGA needs

configuration delay file
also file

– Design partition
device simulation/

– More verification timing

7 6
programming analysis

– I/O-verification, external interfaces FPGA 8

chip
2a. Basics

2. VERY HIGH SPEED

INTEGRATED CIRCUIT
HARDWARE DESCRIPTION
LANGUAGE (VHSIC HDL =
VHDL)
Arto Perttula 26.10.2017 28
Why (V)HDL?
• Interoperability
• Technology independence
• Design reuse
• Several levels of abstraction
• Readability
• Standard language
• Widely supported
 Improved productivity

Arto Perttula 26.10.2017 29

What Is VHDL?
• VHDL = VHSIC Hardware Description Language
– (VHSIC = Very High Speed IC)

• Design specification language

• Design entry language
• Design simulation language
• Design documentation language
• An alternative to schematics
Arto Perttula 26.10.2017 30
A Brief VHDL History
• Developed in the early 1980’s
– For managing design problems that involved large circuits and multiple teams of
engineers
– Originally for documentation, synthesis developed soon after
– Funded by U.S. Department of Defence
• First publicly available version released in 1985
• IEEE standard in 1987 (IEEE 1076-1987)
– IEEE = Institute of Electrical and Electronics Engineers
• An improved version of the language was released in 1994
– IEEE standard 1076-1993
– No major differences to ’87, but some shortcuts added
Arto Perttula 26.10.2017 31
VHDL
• Parallel programming language(!) for hardware
– Allows sequential code portions also
• Modular
– Interface specification is separated from the functional specification
• Allows many solutions to a problem example.vhd
• The coding style matters!
– Different solutions will be slower and/or larger than others Interface
– Save money!
• Case-insensitive language Declarations
– Examples (usually) show reserved words in CAPITALS
• Widely used language Functionality
Arto Perttula 26.10.2017 32
 My First VHDL Example
ENTITY eg1 IS
PORT (
clk
rst_n
: IN
: IN
STD_LOGIC;
STD_LOGIC; eg1
a,b : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
both_1_out: OUT STD_LOGIC; both_1_out
siwa_out : OUT STD_LOGIC C
);
END eg1;
ARCHITECTURE rtl OF eg1 IS
SIGNAL c : STD_LOGIC;
BEGIN a 2
both_1_out <= c;
c <= a(0) AND b(0);
PROCESS ( clk, rst_n ) b 2
BEGIN
IF rst_n = ‘0’ THEN b(0) 00
siwa_out <= ‘0’;
ELSIF clk‘EVENT AND clk = '1' THEN ’0’ 01 siwa_out
IF a = ‘00' THEN
siwa_out <= b(0);
’0’ 10
ELSIF a = ‘11' then DFF
siwa_out <= b(1); 11
ELSE
siwa_out <= ‘0’; b(1) 26.10.2017
END IF; clk
END IF;
END PROCESS;
END rtl;
rst_n
Arto Perttula 33
VHDL Environment
(ModelSim)

(Quartus)
C <= A AND B

(Tools used in this course are shown in parentheses)

Physical design 34
 Interface

Entities – Interfaces Declarations

Functionality

• A black box with interface definition

– Functionality will be defined in architecture
• Defines the inputs/outputs of a component (pins)
• Defines the generic parameters (e.g., signal width)
• A way to represent modularity in VHDL
• Similar to symbol in schematic
8
• Reserved word ENTITY A_in eq_out
B_in comparator
8
ENTITY comparator IS
PORT (
a_in : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0);
b_in : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0);
eq_out : OUT STD_LOGIC
);
END comparator;

Arto Perttula 26.10.2017 35

 Interface

Architecture – Internals Declarations

Functionality

• Every entity has at least one architecture

• Architecture specifies the internals of a design unit and is coupled to a
certain entity entity X
– Defines functionality
A_in C_out
• One entity can have several architectures X
B_in
• Architectures can describe design on many levels
– Gate level
– RTL (Register Transfer Level) arch 1 arch 2
– Structural ”It is ”It is
logical logical
etc.
– Behavioral level
AND” XOR”

Arto Perttula 26.10.2017 36

Architecture (2)
• Example:
ARCHITECTURE rtl OF comparator IS
BEGIN
eq_out <= ’1’ WHEN (a_in = b_in) ELSE ’0’;
END rtl;

• Two main approaches

1. Define new functionality with control statements, e.g., if-for-case, (rtl), shown
above
2. Instantiate existing components and define interconnections between them
(structural)
Arto Perttula 26.10.2017 37
 Interface

Ports Declarations
Functionality

• Provide communication channels (=pins) between the component and its environment
• Each port must have a name, direction and a type
– An entity may omit port declaration, e.g., in test bench
• Port directions:
1. IN: A value of a port can be read inside the component, but cannot be assigned. Multiple reads
of port are allowed.
2. OUT: Assignment can be made to a port, but data from a port cannot be read. Multiple
assignments are allowed.
3. INOUT: Bi-directional, assignments can be made and data can be read. Multiple assignments
are allowed. (not recommended inside a chip)
4. BUFFER: An out port with read capability. May have at most one assignment (not recommended)

Arto Perttula 26.10.2017 38

 Interface

Signals Declarations
Functionality

• Used for communication inside the architecture, carry data

– Ports behave like signals
• Can be interpreted as
a) Wires (connecting logic gates)
b) ”wires with memory” (i.e., FF’s, latches etc.)
• VHDL allows many types of signals
– Bit vectors, integers, even multidimensional arrays and records
• Declared in the architecture body’s declaration section
• Signal declaration:
SIGNAL signal_name : data_type;
• Signal assignment:
signal_name <= new_value;
Arto Perttula 26.10.2017 39
 Interface

Other Declarations Declarations

Functionality

• Functions, procedures (subprograms)

– Much like in conventional programming languages
• Component declaration
– ”We will use an adder which looks like this”
• Configuration
– ”We will use exactly this adder component instead of that other
one”
– Binds certain architecture to the component instance

Arto Perttula 26.10.2017 40

 Interface

Libraries And Packages Declarations

Functionality

• Frequently used functions and types can be grouped in a package

• Libraries include several compiled packages and other design units
• Packages typically contain
– Constants
• Like header.h in conventional programming languages
– General-purpose functions
• E.g., Log2(x)
– Design-specific definitions
• E.g., own data types, records (structs)

Arto Perttula 26.10.2017 41

Design Units
• Segments of VHDL code that can be compiled separately and stored in a library
• Library = directory of compiled VHDL files
VHDL library

entity
VHDL declaration
source package
files declaration

architecture
architecture package configuration
architecture
body
body body declaration
body

Select an entity or configuration into simulation 42

Structure of VHDL Entity
entity declaration:
• Usually 1 entity plus 1 architecture per file in
ports, generics
out

– File named according to entity

architecture

arch declarations:
• Architectures contains usually either signals,
functions,
a) processes types

or arch body:
b) instantiations concurrent statements
component instantiations,
processes
(signal assignments,
if-for-case)

entity_name.vhd
Arto Perttula
Relation Between Circuit and VHDL
Realization Examples GENERIC VHDL STRUCTURE

A : IN
B : IN
Sel : IN
add C : OUT
A
Adder
B

0
Multiplier 1 C
mul signal add, mul
Components +, *
declaration

sel Mux realization

Component instantiation
Signal assignments
26.10.2017
Even Parity Detection Circuit
Truth table:
• Input: a(2), a(1), a(0)
• Output: even
Boolean function:

Logic with basic gates:

Arto Perttula 26.10.2017 45

 Even Parity Detection Circuit at Gate-Level VHDL
Defines packages
that are used in the
design p1

The interface of a
block ”even_detector”
Input a, 3 bits
Output even, 1 bit
p4

Signals used internally

Functionality of the
block (gate level
representation).
The order of
assigments does
NOT matter here
(concurrent
statements).
Arto Perttula 26.10.2017 46
VHDL Summary
Language Purpose Other notes C++ counterpart
constructs in VHDL
ENTITY Defines interface. Includes generics and ports ”Public interface”, the actual implementation is Class definition
(their names, widths, and directions). hidden into architecture.

GENERIC Instance-specific constant value Excellent idea in HDL! Constant parameters, templates

PORT I/O pin of an entity. Defines direction and type. See also signal. Method of a class, inter-process
message

ARCHITECTURE Contains functionality. One entity may have many architectures in the Class implementation
library

SIGNAL, Communication channel between They are not the same! Variables only inside Variable
(VARIABLE) components/processes. processes

COMPONENT For instantiating a sub-block Needed for hierarchy. Class instance, object

PROCESS These capture most of the functionality. Processes are executed in parallel. Both seq. Thread
and comb.

IF,FOR,CASE, Control statements Bounds must be known for loops at compile- The same
ASSIGNMENT time

PACKAGE Contains shared definitions. Constants, functions, procedures, types Header file (file.h)

LIBRARY Holds analyzed (’compiled’) codes Standard ieee library is practically always used Compiled object codes (file.o)

Arto Perttula 26.10.2017 47

EXTRA SLIDES ON VHDL

Arto Perttula 26.10.2017 48

Recap: Register Transfer Level (RTL)

• Circuit is described in terms of how data moves through the system

• In the register-transfer level you describe how information flows between
registers in the system
• The combinational logic is described at a relatively high level, the placement
and operation of registers is specified quite precisely

• The behavior of the system over the clock prediods is defined by registers

Arto Perttula 26.10.2017 49