Lecture 3:

VHDL Basics
TIE-50206 Logic Synthesis
Arto Perttula
Tampere University of Technology
Fall 2017
Contents
• VHDL basics
– Entity – the interface
• Ports, generics
– Architecture – the behavior
• Signals, types
• Process, component instantiation, control statements

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Acknowledgements
• Prof. Pong P. Chu provided ”official” slides for
the book which is gratefully acknowledged
– See also: http://academic.csuohio.edu/chu_p/
• Most slides were originally made by Ari Kulmala
– and other previous lecturers (Teemu Pitkänen, Konsta
Punkka, Mikko Alho, Erno Salminen…)

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VHDL Processes

VERY HIGH SPEED

INTEGRATED CIRCUIT
HARDWARE DESCRIPTION
LANGUAGE (VHSIC HDL =
VHDL)
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Process
• Basic modeling concept of VHDL
• The whole process is a concurrent statement
– i.e., processes are executed in parallel
• Contains a set of statements that are executed sequentially
• VHDL description can always be broken up to interconnected processes
• Keyword PROCESS entity
arch
process P2
P1
port P3 P4
a_v tmp_v

signal
variable
2.11.2017 5
Process (2)
• Processes are the basic building blocks of functional (in most cases
that means RTL) description
• Practically every design has at least one process
• In VHDL, the flip-flops are generated with (synchronous) processes
– No reserved word for registers in VHDL
– Synthesis/simulation tools recognize certain process structures that
imply registers (set of D-flip-flops)
– To be covered later

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Process (3)
• Resides in the architecture’s body
• A process is like a circuit part, which can be
a) active (known as activated)
b) inactive (known as suspended)
• It’s statements will be executed sequentially top-down until the end of the process
– Written order of statements matters, unlike in concurrent statements
• However, all signal assignments take place when process exits
– Forgetting this is a Top-3 mistake for beginners
b <= 1; -- b was 5
c <= b; -- c gets the old value of b, i.e. 5
– Last assignment to a signal will be kept

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Process’s Sensitivity List
• A process is activated when any of the signals in the sensitivity list changes its value
• Process must contain either sensitivity list or wait statement(s), but NOT both
– Similar behavior, but sensitivity list is much more common
• General format:
label: PROCESS[(sensitivity_list)]
process_declarative_part
BEGIN
process_statements
[wait_statement] Either but not both
END PROCESS;

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Example Sensitivity List
process triggered: all
staments executed
• Process with sensitivity list:
ex_p: PROCESS(a,b)
BEGIN
c <= a AND b;
END PROCESS ex_p;
• Process is executed when value of a or b changes
– Type of a and b can be arbitrary: scalar, array, enumeration, or record
– ex_p is a user defined label (recommended)

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Example (2)
• The same process with wait statement:
PROCESS Wait for change on a or b,
BEGIN as in prev slide
WAIT ON a,b;
c <= a AND b;
END PROCESS;
• Bad process with incomplete sensitivity
list: Trigger only when
PROCESS(a) a changes
BEGIN
c <= a AND b; Not evaluated when b changes
(simulation does not match synthesis
END PROCESS; !!!). superbad. 2.11.2017 10
 Example: Last Assignment Is Kept
ENTITY Pitfall1 IS
END Pitfall1;
ARCHITECTURE behav OF
Pitfall1 IS
SIGNAL A, B, C :
std_logic;
BEGIN
A <= ’1’ AFTER 5
ns,
Input wave ’0’ AFTER 15 ns,
generation, ’1’ AFTER 25 ns;
(sim only) B <= ’1’ AFTER 0
ns,
’0’ AFTER 10 ns,
’1’ AFTER 20 ns;
PROCESS (A, B)
OK BEGIN -- process
C <= A;
...
C <= B;
END PROCESS;
END behav;

Only the last assignment, C <= B; ,is kept.

However, this is also useful. In a complex process, designer can assign a default 2.11.2017 11
value at first and then overrride it later in some branch.
 Concurrent vs. Sequential VHDL
-- architecture -- process

Modeling style
Location Inside architecture Inside process or function
Example statements process, component instance, concurrent if, for, switch-case, signal assignment,
signal assignment variable assignment

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Concurrent vs. Sequential VHDL: Example
ARCHITECTURE rtl OF rotate_left IS
SIGNAL rot_r : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
shift : PROCESS(rst, clk)
BEGIN
IF (rst = ’1’) THEN
rot_r <= (others =>’0’); -- reset the register
Concurrent

Sequential ELSIF (clk = ’1’ AND clk’EVENT) THEN

IF (load_en_in = ’1’) THEN
rot_r <= data_in; -- store new value
ELSE
rot_r (7 DOWNTO 1)<= rot_r(6 DOWNTO 0);
rot_r (0) <= rot_r(7);
END IF;
END IF;
END PROCESS;
q_out <= rot_r; -- connect DFF’s output to output port
END concurrent_and_sequential;

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Signals, Variables, Constants

VERY HIGH SPEED

INTEGRATED CIRCUIT
HARDWARE DESCRIPTION
LANGUAGE (VHSIC HDL =
VHDL)
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Signals
• Signals carry the data
• Two possible assignment styles:
1. Sequential signal assignments
– Inside a process
– Evaluated only whenever a process is triggered, e.g., every clock cycle
2. Concurrent signal assignments
– Outside any process
– Used in the concurrent portion of the architecture
• Typically these are simple signal-to-output or signal-to-signal assignments
– ”Always-on” assignments, continuously evaluated
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Signals (2)
• Signal assignment operator is <=
– NOTE: Sequential and concurrent signal assignments look similar
– They are distinguished by their location on code (inside or outside a process)
– General form:
target <= [transport] expr
[after t_expr{, expr after t_expr}];
– Assigns a future and/or current value(s)
• Entity’s ports are also signals
– Note that an out-port cannot be read
• Signal is declared outside the processes
– In the architecture declaration
• Location and right-hand side of the assignment infer some combinatorial logic (e.g.,
addition) or just a simple wire
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1. Sequential Signal Assignments
• Signal assignment inside a process (or a subprogram)
• Assignments are executed every time an event occurs on any of the signals in the sensitivity list of the process
• A process can have only one driver for a signal
– Assignments are scheduled and do not occur until the process has been suspended
– The last assignment takes effect when the process suspends
• Example: data_in has changed from 5 to 1 (note that order of assignments does not actually matter here)

PROCESS (clk, rst_n) rst_n

BEGIN
IF (rst_n = ‘0’) THEN
. . . data_in b_r c_r
ELSIF (clk’EVENT AND clk=‘1’) THEN
b_r <= data_in; -- b is set to 1
c_r <= b_r; -- c gets the old value of b, i.e. 5
END IF;
END; clk

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2a) Concurrent Signal Assignments
• Happens outside a process
• Assignment is executed any time an event occurs in the right-hand side
• Examples
a <= ‘1’; -- These two are
data_out <= data_r; -- the most common

• (test bench code can use delays, after ignored in synthesis):

color <= red after 5 ns, yellow after 1 ns;
line <= transport b after 1 ps;

-- After/transport delays are used only in

-- simulation. Synthesis does create an
-- assignment but without any delay (just
-- a wire)

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1,2) Conditional Signal Assignment
• Concurrently:
target <= value1 WHEN cond1 ELSE
value2 WHEN cond2 ELSE
value3;
• Equivalent process:
PROCESS(cond1,cond2,value1,value2,value3)
BEGIN
IF cond1 THEN
target <= value1;
ELSIF cond2
target <= value2;
ELSE
target <= value3;
END IF;
END PROCESS;

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1,2) Selected Signal Assignments
• Concurrently:
WITH expression SELECT
target <= value1 WHEN choice1,
value2 WHEN choice2, Note that only a single case branch is
value3 WHEN OTHERS;
• Equivalent process: executed. (No need for break commands
PROCESS(expression,value1,value2,value3) like in C)
BEGIN
CASE expression IS
WHEN choice1 => Unfortunately, case has some limitations
target <= value1; compared to if-elsif. Expression must be
WHEN choice2 =>
target <= value2; ’locally static’ , i.e. value can be
WHEN OTHERS => determined inside the design where it
target <= value3;
END CASE; appears. E.g. actual value of a generic
END PROCESS; can be set from upper level, so it’s not
locally static
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VHDL Semantics
• If a process is executed and a certain signal is not assigned, it will keep its previous value
– Good and bad sides…
– Example:

implies

--’0’ to create XNOR

= results in latch!
(in comb. processes, always include the else-branch)

Note that this feature simplifies sequential processes.

Note also that eq is never nullified in example. Once it’s high, it stays high until the
end of the world.
Variables
• A storage facility with a single current value
• Variable value changes instantly as opposed to signal
– Somewhat alike to variables in C/C++
– But differs in many ways from regular programming languages
• Can be used in:
1. Processes
2. Functions
3. Procedures
• No global variables in VHDL’87. They are local to a process or a function.

PROCESS (...)
VARIABLE Q1_v : STD_LOGIC;
BEGIN -- PROCESS
Q1_v := ‘0’;
Q2_v := not Q1_v; -- Q2 sees the “new” value of Q1

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Variables (2)
• Note: variable assignment operator is :=
• Variables should only be used as an intermediate storage
– Short-hand notation to beautify the code
tmp_v := arr_a(i) and arr_b(i) and
arr_c(enable_index_c)…;
if (tmp_v = ’1’) then
d_out <= tmp_v or…
• Variables in processes retain their values during simulation, but in functions and procedures they
do not
• However, never re-use variable value between iterations!
– Re-using the variable value may result in combinatorial feedback loop, which can be a catastrophe
– Re-using the variable obfuscates the code
• Variables are slightly faster to simulate than signals
• Not recommended for processes. More info later why not.

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Constants
• An object that has a constant value and cannot be changed
• The value of contant is assigned when constant is declared
• May be declared globally (within packages) or locally
– Constant declarations can be located in any declaration are
• Clarify the code because magic numbers get a symbolical,
decriptive name

CONSTANT send_data_c : BOOLEAN := TRUE;

CONSTANT base_addr_c : STD_LOGIC_VECTOR(8-1 DOWNTO 0)
:= “10010001”;
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Types in VHDL

VERY HIGH SPEED

INTEGRATED CIRCUIT
HARDWARE DESCRIPTION
LANGUAGE (VHSIC HDL =
VHDL)
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Types
• VHDL is strongly typed language
1. Scalar types
– integer types
– enumeration types
– physical types
– real (floating point) types
2. Composite types
– array types
– record types
3. File types
4. Access types
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http://www.cs.umbc.edu/help/VHDL/types.html

• types-+-scalar----+-discrete-------+-integer-------+-integer
• | | | +-natural
• | | | +-positive
• | | |
• | | -enumeration---+-boolean
• | | +-bit
• | | +-character
• | | +-file_open_kind
• | | +-file_open_status
• | | +-severity_level
• | |
• | +-floating point-+-----------------real
• | |
• | +-physical-------+-----------------delay_length
• | +-----------------time
• |
• +-composite-+-array----------+-constrained-
• | | |
• | | +-unconstrained-+-bit_vector
• | | +-string
• | |
• | +-record-
• |
• +-file-
• |
• +-access

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1a. Scalar Types: Integer
• Minimum range (in VHDL ’87):
– Symmetric 32-bit range
– From -2147483647 to +2147483647
– i.e., –(231-1) to 231–1
– Simulator dependent, can be larger
• Predefined integer types (built-in standard package):
TYPE INTEGER IS RANGE -xxxx TO yyyy;
SUBTYPE NATURAL IS INTEGER RANGE 0 TO INTEGER’HIGH
SUBTYPE POSITIVE IS INTEGER RANGE 1 TO INTEGER’HIGH

• Examples of user defined integer types:

TYPE bit_int IS INTEGER RANGE 0 TO 1;
TYPE byte IS INTEGER RANGE 0 TO 255;
TYPE word IS INTEGER RANGE 0 TO 65535;
-- You should define integer range explicitly to avoid
-- area and delay overheads.

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Peculiarities of Integer
• Omitting negative values does not increase maximum value
– Although in C/C++ it does
– Note thename; unsigned is separate type (vector)
– There is no (confusing) specifier long either
• VHDL standard defines that integer must support 32-bit ”one’s complement range”
– This way inverse number is always valid
• However, RTL Synthesis standard specifies that signed integer should be
represented in two’s complement, supporting range of -(231) to 231-1
– The range of the used tool can be checked with attribute, integer’low and
integer’high
– ModelSim and Quartus support this range
– http://ieeexplore.ieee.org/xpls/abs_all.jsp?tp=&isnumber=18052&arnumber=836335&punumber=6748

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1b. Scalar Types: Enumeration
• Has a set of user defined values
• Ordered
• Pre-defined: BIT, BOOLEAN, SEVERITY_LEVEL, CHARACTER
• Examples of enumeration type declarations:
TYPE SEVERITY_LEVEL IS (NOTE,WARNING,ERROR,FAILURE);
TYPE BIT IS (‘0’, ‘1’); -- package STD
TYPE mybit IS (‘0’, ‘1’, ‘X’, ‘Z’);
TYPE opcode IS (add, sub, lda);
TYPE state IS (idle, start, read, stop);
• NOTE:
– Enumeration literals can be overloaded. Look definitions of BIT and mybit.
– Type of the enumeration literal must be determinable from the context
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1c. Scalar Types: Real
• REAL is the only predefined floating point type
• Minimum range from -1E38 to +1E38
– Simulator (implementation) dependent
• Examples:
TYPE int_real IS REAL RANGE -2147483647.0 TO +2147483647.0; Not
-- Conversion from integer to real as follows
r := REAL(i);
necessarily
synthesizable
!
• NOTE:
– Some synthesis tools may support floating point types. To be safe, use only in simulation.
– Fixed-point representation is often accurate enough
– http://www.eda.org/fphdl/

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1d. Scalar Types: Physical
• Represent physical quantities
• TIME: minimum range from -2147483647 to +2147483647, 32 bit range
– only for simulation
– not synthesizable, there isn’t logic to produce accurate arbitrary delay
– very much simulator dependent
TYPE TIME IS RANGE -1E18 to 1E18
UNITS
fs; Not
ps = 1000 fs;
ns = 1000 ps; synthesizable
us = 1000 ns;
ms = 1000 us; !
sec = 1000 ms;
min = 60 sec;
END UNITS;

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2a. Composite Type: Array
• A collection of one or more values or objects of the same type
• Strong typing forces you to define a new array type before using it
• Unconstrained and constrained declarations possible
– Unconstrained declarations are good for re-using and generic
descriptions
• Support slicing: one-dimendional array is created constraining a
larger array
• Arrays can be returned from functions
• Multidimensional arrays possible
– >3D may not be supported in synthesis
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2a. Composite Type: Array (2)
• Indexed with regular parentheses ’()’
• Examples:
TYPE bit_vector IS ARRAY ( NATURAL RANGE <> ) OF BIT
TYPE defvec IS ARRAY (1 to 10) OF BIT;

TYPE string IS ARRAY ( POSITIVE RANGE <> )

OF BIT;

TYPE matrix IS ARRAY ( INTEGER RANGE <>,

INTEGER RANGE <>)
OF BIT;

-- using unconstrained array needs bounds

SIGNAL addr_r : bit_vector (7 downto 0);
SIGNAL ctrl_c : defvec;
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2b. Composite Type: Record
• Collection of objects with same class
– constant, variable or signal
• Elements can be of any type
• Fields can be referenced with selected name notation (recname.fieldname)
TYPE location IS RECORD
x : INTEGER;
y: INTEGER;
END RECORD;
TYPE ififo IS RECORD
rd_ptr: INTEGER;
wr_ptr: INTEGER;
data : real_array;
END RECORD;
SIGNAL coord_r : location;
...
coord_r.x <= 42;
y_out <= coord_r.y;

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3. File Handling: VHDL ’87
• Sequential stream of objects
– Last file element is end of file (EOF) mark
– File elements can be read (file is IN mode)
– Elements can be written to file (file is OUT mode)
• Built-in file type declaration:
TYPE <type_name> IS FILE OF <object_type>;
• User’s file object declaration
FILE file_identifier : <type_name> IS MODE <file_name>;
• Procedure READ(file,data) reads data from file
• Procedure WRITE(file,data) writes data to file
• Function ENDFILE(file) checks EOF
Not
synthesizable
• Package STD.TEXTIO contains functions for text file manipulation
• File path is relative to simulation directory
!
– Not the VHDL source code directory
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3. File Example in VHDL ’87
access_files : process (clk, rst_n)
-- vhd'87 syntax
file my_in_file : text is in "input.txt";
file my_out_file : text is out "output.txt";
variable in_line_v, out_line_v : line;
variable tmp_v : integer := 0;
begin
if rst_n = '0' then
-- …
elsif (clk'event and clk = '1') then
while (not ENDFILE(my_in_file)) loop

READLINE(my_in_file, in_line_v);
READ(in_line_v, tmp_v);
-- many flavors of read() available

WRITE(out_line_v, tmp_v);
WRITELINE(my_out_file, out_line_v);
end loop;
end if;
end process access_files;

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3. Whole ’87 Example (2)
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;

entity test_file87 is
end test_file87;
architecture behav of test_file87 is
signal clk : std_logic := '0';
signal rst_n : std_logic;
begin -- behav
rst_n <= '0', '1' after 50 ns;
clk <= not clk after 10 ns;
access_files : process (clk, rst_n)
-- vhd'87 syntax
file my_in_file : text is in "input.txt";
file my_out_file : text is out "output.txt";
variable in_line_v, out_line_v : line; -- type "LINE" is a pointer to a string
variable tmp_v : integer := 0;
begin
if rst_n = '0' then -- asynchronous reset (active low)

elsif (clk'event and clk = '1') then -- rising clock edge

while (not ENDFILE(my_in_file)) loop

-- This loop reads the whole file in single clk cycle.
-- Only the first string from each line is converted to
-- integer and the rest are ignored.
-- Runtime error occurs if a line does not start with integer.
READLINE(my_in_file, in_line_v);
READ(in_line_v, tmp_v); -- many flavors of read() available
WRITE(out_line_v, tmp_v);
WRITELINE(my_out_file, out_line_v);
end loop;

end if;
end process access_files;
end behav;

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3. File Types: VHDL ’93
• Quite silmilar to ’87 but files can be opened and closed as needed
• File operations in VHDL ’93:
FILE_OPEN(<file_identifier>, <file_name>, <file_mode>);
FILE_OPEN(<status>, <file_identifier>, <file_name>, <file_mode>); Not
FILE_CLOSE(<file_identifier>); synthesizable
!
• File modes are:
– READ_MODE (file is read-only)
– WRITE_MODE (file is write-only, initially empty)
– APPEND_MODE (file is write-only, output will be added to the end of the file)
Common usage
for files: testbench
check ok?
design under output vectors,
input vectors verification trace, statistics
clk (DUV)

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More Complex Example in VHDL’93
access_files : process (clk, rst_n)
-- vhd'93 syntax, only these 2 lines differ from previous in minimal case
file my_in_file : text open read_mode is "input.txt";
file my_out_file : text open write_mode is "output.txt";
variable in_line_v, out_line_v : line;
variable tmp_v : integer;
variable valid_number : boolean := false;
variable curr_line : integer := 0;
begin
if rst_n = '0' then -- asynchronous reset (active low)
…
elsif (clk'event and clk = '1') then -- rising clock edge
valid_number := false;
-- Loop until finding a line that is not a comment.
while valid_number = false and not(endfile(my_in_file)) loop

READLINE(my_in_file, in_line_v); -- a) read from file, b) from terminal: READLINE(input, in_line_v);

READ (in_line_v, tmp_v, valid_number); -- 3rd param tells if ok
curr_line := curr_line+1; -- just for reporting

if valid_number = false then

report "Skipped the line “ & integer'image(curr_line) & " ( it’s comment or malformed)” severity note;
next; -- start new loop interation
end if;

-- Another way for debug printing, LF = line feed = new line

write (output,string'(“Got value " & integer'image(tmp_v)& " at t:" & time'image(now) & LF));

WRITE(out_line_v, tmp_v);
WRITELINE(my_out_file, out_line_v); -- a) write to file, b) to terminal: WRITELINE(output, out_line_v);
end loop;
end if;
end process access_files;

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4. Access Types
• Very similar to C pointers (suitable for LIFO/FIFO modelling)
• Two predefined functions NEW and DEALLOCATE
• Only variables can be declared as access type
• Very rare. Not synthesizable.
• Example declaration and usage of new and deallocate:
TYPE point_loc IS ACCESS LOCATION;
VARIABLE pl1_v, pl2_v, pl3_v: point_loc;

pl1_v := NEW location; -- new object is created

pl2_v := pl1; -- pl1 points to same obj as pl2
Not
pl3_v := NEW location; synthesizable
pl1_v := pl3_v; !
DEALLOCATE(pl2_v);

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 Summary of VHDL Types
Type name Sim. only Note

std_logic, std_logic_vector Actually enumeration, you’ll need pkg ieee_1164,

use these instead of bit/bit_vector, use downto indexing

integer Limit range for synthesis

unsigned, signed Similar to std_logic_vector, but safer for artihmetic
most common

array E.g. std_logic_vector is array. Define the array type first and then
signal/constnat/variable of that type

enumeration bit and std_logic are actually enumerations,

use this at least for states of an FSM
record Synthesizable, but not very common
file x For reading input data and storing trace/log during simulation-based verification

physical x For detailed gate-level simulation with timing

real x Quite rare because cannot be (always) synthesized
access x Very rare

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EXTRA SLIDES ON VHDL

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 Variables: Example
• THIS IS WRONG! • THIS IS RIGHT (but variable is not very useful)
testi: process (clk, rst_n) testi: process (clk, rst_n)
<= temp_v or a_in(1); variable temp_v : std_logic;
variable temp_v : std_logic; begin -- process testi
begin -- process testi if rst_n = '0' then
if rst_n = '0' then c_out <= '0';
c_out <= '0'; temp_r <= '0';
temp_v := '0'; -- naughty habit
elsif clk'event and clk = '1' then
elsif clk'event and clk = '1' then temp_v := temp_r and a_in(0);
temp_v := temp_v and a_in(0); c_out <= temp_v or a_in(1);
c_out temp_r <= temp_v;
end if; end if;

end process testi; end process testi;

Variable is read before it is written inside the
elsif brach, and hence it must retain the old temp_v temp_r
value. It is not a good custom to infer registers a_in(0)
with variables (although possible)

Fig. The circuit we are trying to create: a_in(1) c_out

44
Signal Drivers
• Every signal has at least one driver, if it is not disconnected
• Signal assignment changes driver
• A conceptual circuit that is created for every signal driver
• Example of driver:
signal ex: positive;
...
ex <= 3 AFTER 5 ns, 2 AFTER 10 ns,
4 AFTER 15 ns, 0 AFTER 20 ns;

ex

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Signal Drivers
• Signal ”ex” as a function of time
ex

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