EE8691: EMBEDDED SYSTEMS

UNIT – II

EMBEDDED Networking

 Embedded Networking: Introduction

 I/O Device Ports & Buses

 Serial Bus communication protocols RS232 standard

 RS422

 RS 485

 CAN Bus

 Serial Peripheral Interface (SPI)

 Inter Integrated Circuits (I2C)

 Need for device drivers.

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UNIT-II

IO DEVICES:
A serial port is a port for serial communication. Serial communication means
that over a given line or channel one bit can communicate and the bits
transmit at periodic intervals generated by a clock. A serial port
communication is over short or long distances.
A parallel port is a port for parallel communication. Parallel
communication means that multiple bits can communicate over a set of
parallel lines at any given instance. A parallel port communicates within the
same board, between ICs or wires over very short distances of at most less
than a meter.
Ports can interconnect by wireless. Wireless or Mobile communication
is a serial communication but without wires, can be over a short range
personal area network as well as long range wireless network, and
transmission takes place by using carrier frequencies. The carrier modulates
the serial bits before transmission in an air. A receiver demodulates and
retrieves the serial bits back.

Serial and Parallel ports of IO devices can be classified into following IO types:
i) Synchronous serial input ii) Synchronous serial output
iii) Asynchronous serial UART input iv) Asynchronous serial UART output
v) Parallel port one bit input vi) Parallel port one bit output vii) Parallel port
input viii) Parallel port output. Some devices function both as input and
output: for example, a MODEM.

i) Synchronous Serial input:

Figure shows a synchronous input serial port. Each bit in each byte
and each received byte are in synchronization. Synchronization means

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separation by a constant interval or phase difference. If clock period equals T,

then each byte at the port is received at input in period 8 T. The bytes are
received at constant rates. Each byte at the input port separates by 8 T and
data transfer rate for the serial line bits is 1/T bps [1 bps=1 bits per second].
The sender along with the serial bits, also sends the clock pulses SCLK (serial
clock) to the receiver port pin. The port synchronizes the serial data input bits
with clock bits.

The serial data input and clock pulse input are on same input line
when the clock pulses either encode or modulate serial data input bits
suitably. The receiver detects clock pulses and receives data bits after
decoding or demodulating.
When a separate SCLK input is sent, the receiver detects at the middle,
positive or negative edge of the clock pulses that indicate whether data input
is 1 or 0 saves the bits in 8-bit shift register. The processing element at the
port(peripheral) saves the byte at a port register from where the
microprocessor reads the byte.
Synchronous serial input is also called master output slave input
(MOSI) when the SCLK is sent from the sender to the receiver and slave is
forced to synchronize sent inputs from the master as per the master clock
inputs. Synchronous serial input is also called master input slave output
(MISO) when the SCLK is sent to the sender (slave) from the receiver (master)
and the slave is forced to synchronize sending the inputs to master as per the
master clock’s outputs.
Synchronous serial input is used for interprocessor transfers, audio
inputs and streaming data inputs.

ii) Synchronous Serial Output:

Part 3 in Figure shows synchronous output serial port. Each bit in each
byte is in synchronization with a clock. The bytes are sent at constant
rates. If the clock period equals T, then the data transfer rate is 1/T bps.
The sender sends either the clock pulses at SCLK pin or the serial data

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output and clock pulse input through same output line when the clock
pulses either suitably modulate or encode the serial output bits.
The processing element at the port (peripheral) sends the byte through
a shift register at the port to which the microprocessor writes the bytes.
Synchronous serial output is used for inter processor transfers, audio
outputs and streaming data outputs.

iii) Synchronous serial input-output:

Part 5 in figure shows a synchronous serial input- output port. Each bit in
each byte synchronizes with the clock input and output. The bytes are sent or
received at constant rates as shown in part 2 and 4 in figure. The IOs are on
same IO line when the clock pulses suitably modulate or encode the serial
input and output respectively. If the clock period equals T, then the data
transfer rate is 1/T bps. The processing element at the port sends and
receives the byte at a port register to or from which the microprocessor writes
or reads byte.
Synchronous serial input/outputs are also called master input slave
output (MISO) and master output slave input (MOSI).
They are used for interprocessor transfers and streaming data. The bits
read from or written on magnetic media such as a hard disk or on optical
media such as a CD by using devices with serial synchronous IO ports.
The part 6 in figure shows the IO synchronous port when input and output
lines are separate.

iv) Asynchronous Serial input:

 Asynchronous input serial port line, denoted by RxD (receive data).

Each RxD bit is received in each byte at fixed intervals but each
received byte is not in synchronization.
 The bit transfer rate ( for the serial line bits) is (1/T)baud per second
but different bytes may be received at varying intervals. The sender
does not send the clock pulses along with the bits.

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 The receiver detects n bits at the intervals of T from the first indicating
bit, n=0, 1,…..10 or 11, finds out whether the data-input is 1 or 0 and
saves the bits in an 8-bit shift register. The processing element at the
port (peripheral) saves the byte at a port register, from where the
microprocessor reads the byte.
 Asynchronous serial input is also called UART input if the serial input
is according to the UART protocol. Asynchronous serial input is used
for keypad and modem inputs.

v) Asynchronous serial Output:

It is denoted by TxD (transmit data). Each bit in each byte is sent at fixed
intervals but each output byte is not in synchronization. Figure c shows the
starting point of sending bits for each byte, which is indicated by a line
transition from 1 to 0 for a period T. The sender port of TxD does not send
clock pulses along with the bits.
The sender transmits bytes at the minimum intervals of n T.Bits start
from the middle of the start indicating bit where n=0,1,…..10 or 11 and sends
bits through a 10 or 11 bits register. The processing element at the port
sends the byte at a port register to where the microprocessor writes the byte.
Asynchronous serial output is also called UART output if the serial output is
according to a UART protocol. Asynchronous serial output is used for modem
and printer inputs.

vi) Parallel port:

A parallel port can have one or multi bit input or output and can be
bidirectional IO
 One bit input, output and IO
 Eight or more bit input, output and IO
vii) Half duplex and full duplex:
Half duplex means that at any point communication can only be one way on
a bidirectional line. ex: Telephone communication.
full duplex means that the communication can be both ways simultaneously.
ex: communication between the modem and computer.

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Serial Communication Using I2C Bus:

General Features:
 When there are number of device circuits, some for measuring
temperatures and some for measuring pressure in a number of
processes in a plant, there is a need for a common bus to mutually
interconnect these ICs.
 I2C (Inter- Integrated Circuits) bus is a standard bus for interconnecting
these circuits.
 I2C is of three standards
i. Industrial 100 Kbps I2C
ii. 100 Kbps SM I2C
iii. 400 Kbps I2C
Configuration & Working:
 I2C has two lines that carry its signals.
 One line is for clock
 one is bidirectional data

Integrated
Clock
Circuit 2

Data
Data
Integrated
Circuit 1 Clock

Data
Integrated
Circuit 3
Clock

 I2C protocol and data format is as follows,

Start Bit R/W ACK NACK Stop Bit

Slave Address(7bits) Data Bits(8 bits)
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 From master

Fields Description:

S Field Widt Explanation

No. h
1 Start field 1 bit It is Start bit
2 Address field 7 It defines the slave address, which is being
bits sent the data frame by the master
3 R/W control 1 bit It defines whether a read or write cycle is in
field progress.
4 ACK control 1 bit Bit defines whether the present data is an
field acknowledgment
5 Data field 8bits Data to be send
6 NACK 1 bit Negative Acknowledgment. If active then
acknowledgment after a transfer is not
needed from the slave, else acknowledgment
is expected from the slave.
7 Stop field 1 bit It is Stop bit

Disadvantage :

 Time taken by the algorithm in the master hardware that analyzes the
bits through I2C in case the slave hardware does not provide for
hardware that supports it.
 The open collector drives at the master, therefore a pull up resistance of
2.2K on each line is essential.

CAN Bus
General Features:
 CAN is a standard bus in a distributed network.
 Mainly used in Automotive electronics.
 It has a bi-directional serial line.
 Sends or receives bits at the maximum rate of 1 Mbps.
 It employs a twisted pair connection to each nodes, which can run up
to a maximum length of 40m.

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Configuration & Working:

 In idle state CANs serial line is at logic level ‘1’, it’s called recessive
state.
 A node sends the output at an instance by pulling the serial line to
logic '0' or a node receives the input at any instance from the serial line
after sensing logic '0' in the line, This state is called dominant state.
 A node sends data bits as data frame. Data frame always starts with '1'
and always ends with seven ‘0’s. Other field of each frame is as
explained below.

Start Arbitratio Control Data Field CRC ACK End

Field n Field Field (0 to 64 (16 bits) Field Field
(1 bit) (12 bits) (6 bits) bits) (2 bits) (7 bits)

 CAN bus usually interconnect to a CAN controller between line

and the host at the node.
 It basically sends and receive data between physical and data link
layer at the host node.
 The CAN controller has
 a BIU (Bus Interfacing Unit consisting of buffer and driver.
 A protocol controller
 status cum control register
 receiver buffer
 message object
There is an arbitration method called CSMA/AMP(Carrier Sense Multiple
Access with Arbitration on Message Priority), Node stops transmitting on
sensing a dominant bit which indicates that another node is transmitting

Field Name Description

Start Field this bit is always 1
Arbitration First 11bits - > Destination Address.
Field Last bit (12th bit) -> RTR (Remote Transmission Request)
RTR is 1 means, the packet is for the destination

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address.
RTR is 0 means, the packet is a request for the data
from a device, the device is
defined by identifier field.
Control Field First bit is identifier extension.
Second bit is always 1.
Last 4 bits are code for data length.
Data Field information(Data) to be send, its length depends on the
data length code in the control field.
CRC Cyclic Redundancy Check word, The receiver node uses it
to detect errors if any during transmission.
ACK Field First bit is ACK Slot, Sender send it as 1 during
transmission and receiver sends back 0 in this slot when
the receiver detects an error in the reception, Sender
Second bit is ACK delimiter, It signals the end of ACK field.
End Field End of frame specification, has seven 0s.

USB Bus

 Universal Serial Bus is a Bus between a host system and a number of

interconnected peripherals.
 It provides a fast (up to 12Mbps) as well as low speed (up to 1.5Mbps)
serial transmission and reception between host and serial devices like
scanner, keyboard, printer, ISDN, etc.
 Its of two standards:
 USB1.1 – a low speed 1.5Mbps 3 meter channel along with a high
speed 12Mbps 25 meter channel.
 USB2.0 – high speed 480Mbps 25 meter channel.
 USB protocol has the feature of – a device can be attached, configured
and used, reset, reconfigured and used, share the bandwidth with
other devices among the devices attached at an instance.
 A device can be either bus powered (eg. Mouse, pen drive) or self
powered (eg. Printer). Also there is a power management by the
software at the host for the USB ports.

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 Connection : The host connects to the devices using USB port driving
software and host controller. The host system has a host controller,
which connects to a root hub. A hub is one that connects to other
nodes or hubs. The root hub connects to the hub and the node at level
1. A hub at level 1 connects to the hub at the level 2 an soon and hence
forms a tree like topology.
 Pins Specifications : USB bus cable has four wires

 one for +5V

 two for twisted pair

 one for ground

 Serial signals are Non Return to Zero (NRZI) coded and the clock is

encoded by inserting synchronous code (SYNC) field before each packet.

The receiver synchronizes its bit recovery clock continuously.

 The data transfer is of four types :

 Controlled data transfer

 Bulk data transfer

 Interrupt driven data transfer

 Is synchronous transfer

 USB is polled bus. i.e. The host controller regularly polls the presence

of a device as scheduled by the software.

 Polling is done by sending a token packet, the token packet consist of

following fields

■ Field for type

■ direction

■ USB device address

■ device end point number

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 The device does the handshaking through a handshake packet,

indicating successful or unsuccessful transmission, a CRC field in the

data packet permits error detection.

 USB supports three types of pipes as follows, the host configures each

pipes with the data bandwidth to be used, transfer service type and

buffer size.

o 'Stream' with no USB defined protocol, it’s used when the

connection is already established.

o 'Default Control' for providing access.

o 'Message' for the control function of the devices.

Need for Advanced Serial High Speed Buses

An embedded system may need to connect multi gigabits per second

(Gbps) transceiver serial interfaces like wireless LAN, Gigabit Ethernet,

SONET, etc., hence there comes a need for high speed serial buses, the

following are examples of new advanced bus protocols

1. IEEE 802.3-2000 [1Gbps bandwidth Ethernet MAC (media Access

Control)] for 125MHz performance.
2. IEE P802.3oe draft 4.1 [10Gbps Ethernet MAC] for 156.25MHz dual
direction performance.
3. IEE P802.3oe draft 4.1 [12.5Gbps Ethernet MAC] for four channel
3.125 Gbps per channel transceiver performance.
4. XAUI (10 Gigabit Attached Unit)
5. XSBI ( 10 Gigabit Serial Bus Interchange)
6. SONET OC -48

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7. SONET OC -192
8. SONET OC -768
9. ATM OC-12/46/192

PARALLEL COMMUNICATION BUS

 There is a need for interconnection bus within a embedded system to a

number of PC based I/O cards, other systems and devices like display
monitor, printer network, video card, modem card, hard disk controller,
etc. Each of these devices which perform a specific function may
contain a processor and software. Each device has the specific memory
address range, specific interrupt vectors and the device I/O port
addresses.
 A bus of appropriate specifications and protocols interfaces theses to
the host system.
 Two old interconnection buses for such communication between host
and a device are ISA and EISA (Extended ISA)
 New interconnection bus is PCI or PCI/X or its variant Compact PCI
(CPCI)

ISA Bus

 ISA bus (IBM Standard Architecture) connects only to a card or an

embedded device that has an 8086 or 80186 or 80286 processor in it.
 Memory access limitation by a system using ISA bus: ISA memory
access can be in two ranges, 640KB to 1MB and 15MB to 16MB. The
former range also overlays with the range used by video boards and
BIOS.

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S Address Components/Devices
No.
1 000 – 00F DMA Chip 8237
2 020 – 021 Programmable Interrupt controller
8255
3 040 – 043 Timer 8253
4 060 – 063 Parallel port programmable parallel
interface.
5 080 – 083, 0A0 – 0AF, 0C0 Components on mother board
– 0CF, 0E0 – 0EF
6 220 – 24F, 278 – 27F, 2F0 Reserved address for peripherals
– 2F7, 3C0 – 3CF, 3E0 -
3F0
7 2F8 – 2FF, 3F8 – 3FF IBM COM ports
8 320 – 32F Hard Disk
9 3F0 – 3F7 Floppy Disk
10 300 – 31F Prototype cards like ADC card
11 380 – 389, 3A0 – 3A9 Synchronous Communication
12 380 – 38C Synchronous Data Link Control
(SDLC)
13 380 – 38F Monochrome display monitors
14 3D0 – 3DF Color and graphics display monitor

Fig

 I/O port address limitations for the devices that use ISA bus :
8086 to 80286 processor has I/O mapped I/Os, not memory mapped
I/Os. Though the instruction set provides for I/O instructions for 64KB

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I/O address, IBM PC configuration ignores the address lines A 10 to A15

and these lines are not decoded. Therefore only 1023 I/O port
addresses are available. A hexadecimal addressing scheme with three
nibble addressing between 000 to 3FF only can be used for a device.

 Following are the address allotted in IBM Standard Architecture (ISA)

 In IBM 80x 86 families only limited interrupt vectors are available.

Interrupt service routines are now shared at software level, Original ISA
specification did not allow that.

EISA Extended ISA

 It’s a 32 bit address and data lines version of ISA.

 ISA devices are also supported by EISA.
 An EISA device first checks the EISA bus availability on the hosting
system
 It supports the sharing of the interrupt functions, SCI (Serial
Communication Interface) controller and Ethernet devices.
 Unix and Linux support EISA bus driven cards and devices.

PCI and PCI/X Buses

Specification
 PCI stands for Peripheral Component Interconnect.
 PCI provides superior throughput than EISA
 It’s Almost platform independent, where ISA depends on IBM platform.
 Its Clock rate is nearest to the sub – multiple of the system clock.
 PCI provides three types of synchronous parallel interfaces
 Its two versions are 32/33MHz and 64/66MHz, also recently
introduced PCI-X 64/100MHz.
 Lately two super speed versions of PCI have been introduced. These are
PCI Super V2.3 264/538MBps 3.3V (on a 64bit bus), 132/264 (on a 32

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bit bus) and PCI Super V1.01 for 800MBps 64bit 3.3Volts.
 PCI had 32 bit data bus extensible to 64bits also a 32 bit address bus
extensible to 64bits.
 Its synchronous/asynchronous throughput is up to 132/526MBps
 It operates on 3.3V to 5V signal
 An exemplary PCI card has an 16MB Flash ROM with a router gateway
for a LAN

Working
 A PCI driver can access the hardware automatically as well as by the
programmer assigned addresses. The PCI feature of automatically
detecting the interfacing systems for assigning new addresses is
important for coding a device driver. The PCI bus therefore simplifies
the addition and deletion (Attachment and detachment) of the system
peripherals.
 A manufacturer registers a global number, for eg. 68HC11 and 80386
are globally registered numbers. A 16bit register in a PCI device
identifies this number to let that device auto detect it.
 Another 16bit register identifies a device ID number. These two
numbers allow the device to carry out its auto – detection by its host
system.
 Each device may use FIFO controller with a FIFO buffer for maximum
throughput.
 There are three identification numbers by which a device identifies its
address space.
i. I/O port
ii. Memory locations
iii. Configuration registers of total 256B with a 4byte unique ID. This
configuration address space is the unique feature of PCI.
 Interrupts are handled by the uniquely assigned interrupt type
(number). A configuration register number 60 stores the one byte for
the interrupt type that defines this unique number.

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 The 64byte standard configuration register in a PCI device is as follows

IRQ Min Max

EXP ROM IRQ
0x30 Reserved Lin - -
BA6 Pin
e GNT GNT
0x20
BA4 BA5 CBCISP SSVID SSDID

0x10
BA0 BA1 BA2 BA3

0x00
VID DID CR SR RID CC CL LT HT BIST

 VID – Vendor ID
 DID – Device ID
 RID – Revision ID
 CR – Common Register
 CC – Class Code
 SR – Status Register
 CL – Cache Line
 LT – Latency Timer
 BIST - Base Input Tick
 HT – Hear Type
 BA – Base Address
 CBCISP – Card Based CIS Pointer
 SSVID - Subsystem VID
 SSDID – Subsystem DID
 EXPROM – Expansion ROM
 MIN-GNT – Minimum Guaranteed time
 MAX-GNT – Maximum Guaranteed time

VID, DID, RID,CR,SR and HT are compulsorily configured, rests are optional.

 A PCI controller must access one driver at a time, thus all the devices
within the host computer can share I/O port addresses and memory
locations but cannot share the configuration registers.

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 A device cannot modify other configuration registers but can access

other device resources or share the work or assist the other devices.
 A device can initialize at booting time, this helps in avoiding any
address collision.
 A PCI device on boot up disables its interrupt and closes its door to its
address space except to the configuration register space.
 The PCI BIOS with the device performs the configuration transaction
and the, memory and address spaces automatically map to the address
space in the host system.

Need for advanced high speed buses

Many embedded processor based products need parallel buses for

systems I/Os. The three versions of PCI parallel synchronous/asynchronous
buses may not have sufficient high speed and ultra high speed and large
bandwidth that need systems I/Os, routers, LANs, switches and gateways,
SANs (Storage Area Network), WANs and other products. Bandwidth needs
increases exponentially in the order audio, graphics, video and interactive
video and broadband IPv6 Internet. An Embedded system may need to
connect to the I/O using gigabit parallel synchronous interfaces. The
following are the number of new advanced bus standard protocols and a
number of propriety protocols developed recently.
1. GMII ( Gigabit Ethernet MAC Interchange Interface)
2. XGMI (10 Gigabit Ethernet MAC Interchange Interface)
3. CSIX -1 6.6Gbps 32bit HSTL with 200MHz performance.
4. RapidIO Interconnect Specification v1.1 at 8Gbps with 500MBps
performance or 250MHz dual direction registering performance using
8bit LVDS (Low Voltage Data Bus)

RS 232 C STANDARD:

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RS 232 C was defined by Electronic Industries Association (EIA) for data

interchange. RS232 is an interfacing signal standard. It is a point to point
interface.

It provides communication between DTE and DCE. It follows the

asynchronous UART protocol.
Receiver end voltage level from -3V to -25V denotes logic 1 and voltage level
from +3V to +25V denotes 0.
Transmitter end voltage level from -5V to -15V denotes logic 1 and from
+5 to +15V denotes logic 0.
Commonly used Band rate for asynchronous serial communication with
UART mode is 9600.
The RS232 C standard allows data to be sent and received at the same time.
(full duplex)
RS232 C standard defines two types of lines such as DB9 and DB 25 for real
world applications.
The RS232 C standard defines,
o The Mechanical aspects of interface.
o The characteristics of electrical signals.
o The functional aspects of the interchange.
RS485:
RS-485 allows multiple devices (up to 32) to communicate at half-duplex and
full duplex at distances up to 1200 meters .
Both the length of the network and the number of nodes can easily be
extended using a variety of repeater.
Data is transmitted differentially on two wires twisted together, referred to as
a twisted pair.
A 485 network can be configured two ways, two-wire or four-wire

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In a two-wire network the transmitter and receiver of each device are

connected to a twisted pair.
Four-wire networks have one master port with the transmitter connected to
each of the slave receivers on one twisted pair. The slave transmitters are all
connected to the master receiver on a second twisted pair.
In either configuration, devices are addressable, allowing each node to be
communicated to independently.
Only one device can drive the line at a time, so drivers must be put into a
high- impedance mode (tri-state) when they are not in use.
Two-wire 485 networks have the advantage of lower wiring costs and the
ability for nodes to talk amongst themselves. But is limited to half-duplex.
Four-wire networks allow full-duplex operation, but are limited to master-
slave situations. Slave nodes cannot communicate with each other.
RS485 communication is half duplex. Each communicating element on an
RS485 interface is called a node. One of the nodes is called the master while
all other nodes are called slaves. Each node has a unique ID number. Node
#0 is generally assigned to the master.
RS485 features are
o Very noise immune
o Maximum cable length of 4000 feet
o Data rate up to 10 Mbps
o Capable of supporting a multi-master configuration.

DEVICE DRIVER

A system has number of physical device. A device may have multiple

function. Each device function requires a driver. Example of multiple function
in a device are as follows.
1. A timer device performs timing functions as well as counting functions.
It also performs the delay function and periodic system calls.

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2. A transceiver device transmits as well as receives It may not be just a

repeater. It may also do the jabber control and collision control.(jabber
control means prevention of continuous streams of unnecessary bytes in
case of system fault. Collision control means that it must first sense the
network bus availability then only transmit)
3. Voice-data-fax modem device has transmitting as well as receiving
functions for voice, fax as well as data
A common driver or separate drivers for each device function are required.
The driver has the following features:
1. The driver provides a software layer (interface) between the application
and actual device: When running an application, the devices are used.
A driver provides a routine that facilitates the use of a device function
in the application.
2. The driver facilitates the use of a device by executing an ISR: The driver
function is usually written in such a manner that it can be used like a
black box by an application developer. Simple commands from a task
or function can then drive the device. Once a driver function is
available for writing the codes, the application developer does not need
to know anything about the mechanism, addresses, registers, bits, and
flags used by the device.

Common method of using the driver is as follows: a device is opened before

using the driver. If means device is first initialized and configured by setting
and resetting the control bits of device control register and use of the
interrupt service is enable. Using a user function or OS function, a device can
also be closed or de-registered or detached by another process. After
executing that process, the device driver is not accessible till the device is
reopened (reregistered/reattached).

I Writing physical device – driving ISR’s in a system:

For writing the software for driver in assembly, the following points must be
clear

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1. Information about how the device communicates

2. Information about the three sets of registers – data registers, buffers,
control registers and status registers. A device initializes (configures,
registers, attaches) by setting the control register bits. A device closes
(resets, deregisters, detaches) by resetting the control register bits.
3. Information of other registers and common addresses to a device
register.
4. Control register bits control all actions of the device. A control bit can
even control which address corresponds to which data register at an
instance.
5. A status register bit reflects the flags for status of the device at an
instance and change after performing actions as per the device driver. A
status flag at a status register reflects the present status of a device.
6. Either setting of an enable bit is used by the system to initiate a call for
executing an ISR related to the device driver function.
The following information must therefore be available when writing a device
control and configuring and driver ports.
1. Addresses for each register: physical device hardware and its
interfacing circuit fix the addresses for a physical device and they
usually cannot be relocated. The device becomes the owner of these
addresses.
2. There may be input buffer register as well as output buffer register at a
common address.
3. There may be multiple registers at the same address
4. Purpose of each bit of the control register
5. Purpose of each status flag in the status register
6. Whether control bits and status flags are at the same address. The
processor reads the status from this address during the read
instructions. The processor writes the control bits at that address
during the write instructions.
7. Whether bits, control bit and flags coexist in the same register.
8. Whether the status flag, which sets on a device, interrupt, auto resets
on executing the ISR or if an ISR instruction should reset.

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9. Whether control bits need to be changed, reset/set again before return

to the interrupted process
10. List of actions required by the driver at the data buffers, control
registers and status registers.

II Virtual Device Drivers:

Virtual Device Drivers emulate the device hardware, for ex hard disk
generates software interrupts similar physical device drivers. The file and pipe
are two ex. of virtual devices.
Both Virtual devices and physical device drivers have functions for
device open, read, write and close.
The concept of virtual device drivers is very important in programming,
for eg.,
1. A memory block can have data buffers in analogy to buffers at an
i/o device. It can be accessed from a character driver or from a block
driver. The device is called the character device or block device when
it can access a character or a block of characters respectively.
2. A physical device transceiver or repeater is equivalent to a virtual
device called loop back device. It stores allocated memory block
using that block device driver and returns the data back from the
memory.
3. A bounded buffer device in memory can be like a printer buffer. A
data stream is sent by one routine (driver) and read by another
routine (driver). Bounded buffer device is a virtual device, usually
called pipe device.
4. A program can store in a set of memory blocks called RAM disc in
the analogous way a file system does at the hard disk. RAM disk is a
device that consists of multiple internal file devices.

III Parallel port drivers in a system:

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Device driver read () function can be implemented by calling an ISR is

port_isr_input, which handle the port input. Figure a shows control and
status bits used in the ISR’s in the device drivers and port pins interface with
the data bus. Figure b shows step A for port initialization step B for calling
the driver and step 0-5 for driver port_isr_input. The driver reads by from port
and puts it into a queue that builds the memory on successive inputs to the
port.
Port_isr_input does the following.
1. Step A sets the device control bit for read. Step B is no action till input
event.
2. Step 0-2 are for reading the input buffers by emptying the buffer and
storing the bytes in memory or using the bytes received as per the
system requirements.
3. Step 3 resets the device received buffer ready flag and does prepares
the device for the next read after step 4. In step 4 interrupt flag resets
to enable next byte read on next interrupt.
An example for device driver write() function is a driver ISR for handling the
port outputs. The ISR does the following,
1. Sets the device control bit for write.
2. Sends into the device output buffer bytes from the memory.
3. Resets the device transmits buffer empty flag on completion of
transmission of the bytes and prepare the device for the next write.

IV Serial Port Drivers in a System:

There is IEEE standard called POSIX (Portable Operating System

Interface) standard. Portability of the UART drivers in different systems is
essential. In a PC with 8086 processor an UART 8250 or a new generation
UART device UART16550, which includes the 16 byte FIFO input and output
buffer is used.

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