VHDL slides for CStruct

Mux & Decoder

A VHDL process example: 2→1 mux
A A 0
Y ≡ Y
B 1
B

sel sel

mux_2to1: process (A, B, sel)

begin
if sel = ‘0' then
Y <= A; This IF statement stands for that
else
Y <= B;
end if;
end process;
 2→1 mux vs. Nx(2→1)
(2→1) mux 8x(2→1) mux
A 0 A[7:0] 8 0
Y 8
Y[7:0]
B 1 B[7:0] 1
8

sel sel

In both cases we have the same process code

process (A, B, sel)

begin In the single wire case we define:
if sel = ‘0' then signal A : STD_LOGIC;
Y <= A;
else
Y <= B; In the multi-wire case we define:
end if; signal A : STD_LOGIC_VECTOR (7 downto 0);
end process;
 4→1 mux
4→1 mux
A 00

B 01
process (A, B, C, D sel) 10
Y
C
begin
if sel = b”00” then D 11

Y <= A;
elsif sel = b”01” then 2

Y <= B; Sel[1:0]
elsif sel = b”10” then
Y <= C;
8x(4→1) mux
else
Y <= D; A[7:0] 00
8
end if; B[7:0] 01
end process; 8
Y[7:0]
C[7:0] 8
10 8

D[7:0] 8
11

2
Sel[1:0]
 2→4 decoder
signal sel : STD_LOGIV_VECTOR (1 downto 0);
signal Y : STD_LOGIV_VECTOR (3 downto 0);

process (sel)
begin 2→4 decoder
if sel = b”00” then
Y <= b“0001”; Y(0)
elsif sel = b”01” then sel(0) Y(1)
Y <= b”0010”;
elsif sel = b”10” then sel(1) Y(2)
Y <= b”0100”;
else Y(3)
Y <= b”1000”;
end if;
end process;
 What do we do with VHDL?
• We describe our design in VHDL
This is similar to writing a program

• While programs are compiled to machine language

and then loaded into a computer and run, we here
must implement our design on some kind of HW

• We “compile” our design and “load” it into a

special HW device called FPGA
• FPGA device can implement any function we want
• How??
 FPGA concept
The Field Programmable Gate Array has an array of Logic Blocks

0
0 Y
D Q 1
A0 1
A1 LUT
sel2
A2 CK
sel1
A3

Configure (load) the LUT

Let’s demonstrate implementation of a simple mux.

During “configuration phase”, we fill up the LUT and choose values for sel1 & sel2
 FPGA concept
The Field Programmable Gate Array has an array of Logic Blocks

0
in0 0 Y
D Q 1
x000 => 0
A0 x001 => 1 1
x010 => 0
in1 A1 x011 => 1
x100 => 0 sel2
sel A2 x101 => 0 CK
x110 => 1 sel1
A3 x111 => 1

Configure (load) the LUT

Let’s demonstrate implementation of a simple mux.

During “configuration phase”, we fill up the LUT and choose values for sel1 & sel2
We fill up the LUT with the truth-table representing the required function!
Here it is the mux truth table. When sel=0, we have Y=in0, when sel=1 we have Y=in1
 FPGA concept
There is also a matrix of internal lines allowing connections to/from the Logic Blocks

Logic Logic Logic

Block Block Block

Logic Logic Logic

Block Block Block

We can “connect” between Logic Blocks by connecting specific intersections

Clock signals have special lines with minimal skew
The connections are determined during configuration - 1 bit determines a connection
 End of
VHDL slides for
mux & decoder lecture
VHDL slides for Cstruct
ALU lecture
 ALU example

-- Book 32bit ALU (chapter 3 pages 11-12, July 2014 version)

process(ALU_A_in, ALU_B_in, ALU_cmd)
begin
case ALU_cmd is
when b"000" => ALU_output <= ALU_A_in + ALU_B_in;-- ADD
when b"001" => ALU_output <= ALU_A_in - ALU_B_in; -- SUB
when b"010" => ALU_output <= ALU_A_in and ALU_B_in; -- AND
when b"011" => ALU_output <= ALU_A_in or ALU_B_in; -- OR
when b"100" => ALU_output <= ALU_A_in xor ALU_B_in); -- XOR
when b"101" => ALU_output <= not(ALU_A_in) ; --not A
when b"110" => ALU_output <= ALU_A_in; -- A
when others => ALU_output <= ALU_B_in;-- B
end case;
end process;
 End of
VHDL slides for Cstruct
ALU lecture
VHDL slides for CStruct
Registers lecture
 A combinational process example
A A 0
Y ≡ Y
B 1
B

sel sel

process (A, B, sel)

begin
if sel = ‘0' then
Y <= A; This IF statement stands for that
else
Y <= B;
end if;
end process;
 2→1 mux vs. Nx(2→1)
(2→1) mux 8x(2→1) mux
A 0 A[7:0] 8 0
Y 8
Y[7:0]
B 1 B[7:0] 1
8

sel sel

In both cases we have the same process code

process (A, B, sel)

begin In the single wire case we define:
if sel = ‘0' then signal A : STD_LOGIC;
Y <= A;
else
Y <= B; In the multi-wire case we define:
end if; signal A : STD_LOGIC_VECTOR (7 downto 0);
end process;
 A sequential process example
A[7:0] 8
D Q
8
Y[7:0]
D Q
8
Y[7:0]
A[7:0] 8 ≡ CE

CE CK CK
Here:
signal A : std_logic_vector (7 downto 0);
signal Y : std_logic_vector (7 downto 0);
signal CE : std_logic;
signal CK : std_logic;
process (CK)
begin
if CK’event and CK=‘1’ then If we have a rise in the CK then:
if CE = ‘1' then
Y <= A; If CE=‘1’ we sample data,
end if; else we keep the data unchanged.
end if;
end process;
 A simple Data Path in VHDL- I

R0
n n

WE0

n x (2 → 1) mux
CK

R1 n
A ALU
n n

WE1 Y n
2
A1A0

2→4 CK
n B
decoder

2
R2 3
C1 C0
n n
S 2S 1S 0
2
WE2
B 1B 0

CK

R3
n n

WE3
S 2S 1S 0 A1A0 B 1B 0 C1 C0 n bits imm
CK
The CPU instruction format
 A simple Data Path in VHDL- II
-- Definition of all signals used
29,28 25,24 21,20 17,16 15 0
0 S 2S 1S 0 0 0 A1A0 0 0 B 1B 0 0 0 C1 C0 16 bits imm
-- CPU “instruction”
signal instruction : STD_LOGIC_VECTOR (31 downto 0);
-- fields of the instruction
signal ALU_op : STD_LOGIC_VECTOR (2 downto 0);
signal ALU_src_A : STD_LOGIC_VECTOR (1 downto 0);
signal ALU_src_B: STD_LOGIC_VECTOR (1 downto 0);
signal ALU_destinaton: STD_LOGIC_VECTOR (1 downto 0);
signal imm : STD_LOGIC_VECTOR (15 downto 0);

-- ALU signals
signal ALU_A_in : STD_LOGIC_VECTOR (15 downto 0);
signal ALU_B_in : STD_LOGIC_VECTOR (15 downto 0);
signal ALU_Y_out : STD_LOGIC_VECTOR (15 downto 0);

-- Data Path registers

signal R0 : STD_LOGIC_VECTOR (15 downto 0) := x"FFFF";
signal R1 : STD_LOGIC_VECTOR (15 downto 0) := x"8888";
signal R2 : STD_LOGIC_VECTOR (15 downto 0) := x"7777";
signal R3 : STD_LOGIC_VECTOR (15 downto 0) := x"5A00";
signal R4 : STD_LOGIC_VECTOR (15 downto 0) := x"A5A5";

-- general signals
signal CK : STD_LOGIC;
 A simple Data Path in VHDL- III
-- renaming fields of the instruction
ALU_op <= instruction (30 downto 28);
29,28 25,24 21,20 17,16 15 0
ALU_src_A <= instruction (25 downto 24);
0 S 2S 1S 0 0 0 A1A0 0 0 B 1B 0 0 0 C1 C0 16 bits imm
ALU_src_B <= instruction (21 downto 20);
ALU_destinaton <= instruction (17 downto 16);
imm <= instruction (15 downto 0);

-- ALU src A mux

process (R0,R1,R2,R3,ALU_src_A)
begin
case ALU_src_A is
when b"00" => ALU_A_in <= R0;
when b"01" => ALU_A_in <= R1;
when b"10" => ALU_A_in <= R2;
when others => ALU_A_in <= R3; R0

end case;
end process;
R1
-- ALU src B mux A
process(R0,R1,R2,imm,ALU_src_B) Y
begin
B
case ALU_src_B is R2

when b"00" => ALU_B_in <= R0;

when b"01" => ALU_B_in <= R1;
when b"10" => ALU_B_in <= R2;
when others => ALU_B_in <= imm; R3

end case;
end process;
-- ALU
A simple Data Path in VHDL- IV
process (ALU_A_in, ALU_B_in, ALU_op)
begin
case ALU_op is
when b"000" => ALU_Y_out <= ALU_A_in + ALU_B_in;-- ADD
when b"001" => ALU_Y_out <= ALU_A_in - ALU_B_in;-- SUB
when b"010" => ALU_Y_out <= ALU_A_in and ALU_B_in;-- AND
when b"011" => ALU_Y_out <= ALU_A_in or ALU_B_in;-- OR
when b"100" => ALU_Y_out <= ALU_A_in xor ALU_B_in;-- XOR
when b"101" => ALU_Y_out <= not(ALU_A_in);--not A
when b"110" => ALU_Y_out <= ALU_A_in; -- A
when others => ALU_Y_out <= ALU_B_in;-- B
end case;
end process;
-- Data Path registers
process (CK) R0

begin
if CK'event and CK='1' then
if ALU_destinaton=b"00" then R1
R0 <= ALU_Y_out; A

elsif ALU_destinaton=b"01" then Y

R1 <= ALU_Y_out; B
elsif ALU_destinaton=b"10" then R2

R2 <= ALU_Y_out;
else
R3 <= ALU_Y_out;
R3
end if;
end if;
end process;
A simple Data Path in VHDL- V

instruction <= x"1000" & x"0000";-- R0 = R0-R0 (result should be 0000h)

instruction <= x"1001" & x"0000";-- R1 = R0-R0; (result should be 0000h)
instruction <= x"0102" & x"0000";-- R2 = R1+R0; (result should be 0000h)
instruction <= x"0031" & x"1234";-- R1 = R0 + imm (1234h) (result should be 1234h)
instruction <= x"0032" & x"0001";-- R2 = R0 + imm (1h) (result should be 0001h)
instruction <= x"1121" & x"0000";-- R1 = R1 - R2 (result should be 1233h)
instruction <= x"1013" & x"0000";-- R3 = R0 - R1 (result should be EDCDh)
 End of
VHDL slides for CStruct
Registers lecture
VHDL slides for CStruct
FSM lecture
Traffic Light FSM - I
 Traffic Light FSM - II

NextState CrntState

Red
Yellow
X Green
 Traffic Light FSM - III
-- Definitions related to the FSM
-- FSM states
type FSM_state is (
Red_State,
YellowRed_State,
Green_State,
Green2_State,
Green3_State,
Off1_State,
Off2_State,
Off3_State,
Yellow_State );

-- FSM signals (their type is FSM_state)

signal CrntState : FSM_state := Red_State;-- in FPGA power up in Red_State
signal NextState : FSM_state;

Begin -- start of implementation processes

-- Moore FSM state register

process (FSM_CK)
begin
if FSM_CK'event and FSM_CK='1' then
CrntState <= NextState;
end if;
end process;
 Traffic Light FSM - IV
-- Moore FSM implementation
process (CrntState, X)
begin
case CrntState is
when Red_State => if X='1' then NextState <= YellowRed_State;
else NextState <= Red_State;
end if;
when YellowRed_State => NextState <= Green_State;
when Green_State => if X='1' then NextState <= Off1_State;
else NextState <= Green_State;
end if;
when Off1_State => NextState <= Green2_State;
when Green2_State => NextState <= Off2_State;
when Off2_State => NextState <= Green3_State;
when Green3_State => NextState <= Off3_State;
when Off3_State => NextState <= Yellow_State;
when Yellow_State => NextState <= Red_State;
when OTHERS => NextState <= Red_State; -- We MUST have the OTHERS case. Always!
end case;
end process;

-- FSM output decoder

Red <= '1' when CrntState=Red_State or CrntState=YellowRed_State else '0';
Yellow <= '1' when CrntState=YellowRed_State or CrntState=Yellow_State else '0';
Green <= '1' when CrntState=Green_State or CrntState=Green2_State or CrntState=Green3_State else '0';
Traffic Light FSM - V
 End of
VHDL slides for CStruct
FSM lecture