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Jtag CPLD PDF

This document provides a circuit diagram for a USB to Ethernet converter. It shows the connections between an Ethernet PHY chip and USB to Ethernet controller chip powered by a 5V USB input. Capacitors and resistors are used to regulate voltage and provide decoupling. The USB to Ethernet controller outputs connect to the Ethernet PHY for communication over the Ethernet interface.

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Deilyn Rivas
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0% found this document useful (0 votes)
173 views1 page

Jtag CPLD PDF

This document provides a circuit diagram for a USB to Ethernet converter. It shows the connections between an Ethernet PHY chip and USB to Ethernet controller chip powered by a 5V USB input. Capacitors and resistors are used to regulate voltage and provide decoupling. The USB to Ethernet controller outputs connect to the Ethernet PHY for communication over the Ethernet interface.

Uploaded by

Deilyn Rivas
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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+5V +VCCIO

+5V_USB

BLM21PG331SH1
U7
L1
TXB0104
C1 C2
+ 1 14
VCCA VCCB

R3
470E
100n 2 13
10uF 16V T C3 A1 B1
3 12
A2 B2
4 11
A3 B3
100n 5 10
A4 B4
D3
6 9
NC NC

30
3
26
13
BAV99 D2 7
GND
J2 C4 U3-B
AVCC VCC VCCIO 8
USB-B BAV99 6 EPM570T100-NORMAL OE
3V3OUT
1 25 2 51
VBUS 27E D0 B1_0 B1_33
2 470n 8 24 3 50
D- R1 UDBDM D1 B1_1 B1_32
3 R2
7 23 4 49
D+ USBDP D2 B1_2 B1_31
4 27E 22 5 48
GND D3 B1_3 B1_30
R4
5 21 6 47
RSTOUT D4 B1_4 B1_29
Shield +5V 1K5 4 20 7 42
RESET D5 B1_5 B1_28
6 5 C5 19 8 41
D6 B1_6 B1_27
27 18 15 40
XTIN D7 B1_7 B1_26
9
7
5
3
1

16
C7 22p Y1 B1_8
17 38
U1 B1_9 B1_24 U6
16 18
100n 6MHZ RD B1_10 TXB0104
FT245BM 15 19 36
WR B1_11 B1_22
C6 14 20 35 IO_7 1 14
TXE
TDI/ASDI

B1_12 B1_21 VCCA VCCB


DATAOUT
TCK/DCLK

28 12 21 34 IO_6
U2 XTOUT RXF B1_13 B1_20
TMS/CONFIG

IO_0 26 33 IO_5 2 13
J5

B1_14 B1_19 A1 B1

R5
R6

10K
10K
93C46B 22p 11 27 30 3 12
SI/WU IO_1 B1_15 B1_18 IO_4 A2 B2
TDO/CONF_DONE

8 1 32 10 IO_2 28 29 IO_3 4 11
VCC CS EECS PWREN B1_16 B1_17 A3 B3
6 1 5 10
2K2 ORG EESK A4 B4
4 3 2
R7
CONN-JTAG-ALTERA

Q D EEDATA
2 6 9
SCL NC NC

R20
R21

220E
220E
GND
CS/RTCK
CE/SRST
VCC
GND

7 7
DU GND
5 TEST AGND GND
8
6
4
2

GND J1
10

9
OE

31
29
17
1
2
3 PANIC SWITCH

+VCCIO +VCCINT +VCCIO

D5
D4
1K
R16
10K
+VCCINT
R17

10K
+VCCIO

10K
10K
10K
POWER SUPPLY R22

C20

R12
R13
R14

9
31
45
59
80
94
13
63
39
88
U5 100n
+VCCINT +VCCIO SPXO018043 RS: 478-8704 VCCIO1 VCCIO2 VCCINT
1 4 47E 12 23 9 10
+5V EN VDD R8 IO/GCLK0 TDI TDI/ASDI GND
dnp 14 22 7 8
R9 IO/GCLK1 TMS DATAOUT CS/RTCK
U4 2 3 dnp 62 24 5 6
GND OUT R10 IO/GCLK2 TCK TMS/CONFIG CE/SRST
LK112M33TR dnp 64 25 3 4
R11 IO/GCLK3 U3-A TDO TDO/CONF_DONE VCC
5 4 D1 1 2
IN OUT 48 MHZ EPM570T100-NORMAL TCK/DCLK GND
C11 10K 43
BAT54C R18 IO/DEV_OE
1 10K 44 CONN-JTAG-ALTERA
SHDWN 100n R19 IO/DEV_CLR
3 2 J3
BYPASS GND

10K
R15
C9 C10 GNDIO GNDIO GNDINT

100n 100n

10
32
46
60
79
93
11
65
37
90
C8

100n

SPARE CPLD BANK


U3-C
EPM570T100-NORMAL
52 1
GENERIC INPUT / OUTPUT CPLD DECOUPLER CAPS. B2_0 B2_39 MECHANICAL
53 100
B2_1 B2_38
54 99
B2_2 B2_37
+5V_USB +VCCIO 55 98 CORNER HOLES
B2_3 B2_36
56 97
+VCCIO +VCCINT B2_4 B2_35 1
FO1 1
FO2 1
FO5
57 96
B2_5 B2_34
58 95
B2_6 B2_33
J4 61 92
B2_7 B2_32
66 91
IO_0 1 2
B2_8 B2_31
67
IO_1 3 4 B2_9 CENTRAL HOLE
68 89
IO_2 5 6 IO_7 B2_10 B2_29
69 1
FO3
IO_3 7 8 IO_6 B2_11
C12 C13 C14 C15 C16 C17 C18 C19 70 87
IO_4 9 10 IO_5 B2_12 B2_27
71 86
11 12 100n 100n 100n 100n 100n 100n 100n 100n
B2_13 B2_26
72 85
B2_14 B2_25
73 84
External I/O B2_15 B2_24
74 83
B2_16 B2_23
75 82
B2_17 B2_22 FIDUTIAL MARK
76 81
B2_18 B2_21 PIAZZ. PIAZZ.
77 78
B2_19 B2_20

FID1 FID2

ORGANIZATION: TITLE: CODE: SIZE: DRAWING NO: REV: SCALE: SHEET: 1 OF 1


OPENJTAG.ORG JTAG CPLD QUAD 1.1
DRAWN: DATE: CHECKED: DATE: QUALITY CONTROL: DATE: RELEASED: DATE:
RHM May-22-2010 RHM May-24-2010

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