A.V.

PAREKH TECHNICAL INSTITUTE, RAJKOT

ELECTRONICS & COMMUNICATION DEPT.
VLSI MCQ

1. nMOS devices are formed in

a) p-type substrate of high doping level
b) n-type substrate of low doping level
c) p-type substrate of moderate doping level
d) n-type substrate of high doping level

Answer: c
Explanation: nMOS devices are formed in a p-type substrate of moderate doping level.
nMOS devices have higher mobility and is cheaper.

2. Source and drain in nMOS device are isolated by

a) a single diode
b) two diodes
c) three diodes
d) four diodes

Answer: b
Explanation: The source and drain regions are formed by diffusing n-type impurity, it gives
rise to depletion region which extend in more lightly doped p-region. Thus Source and drain
in a nMOS device are isolated by two diodes.

3. In depletion mode, source and drain are connected by

a) insulating channel
b) conducing channel
c) VDD
d) VSS

Answer: b
Explanation: In depletion mode, source and drain are connected by conducting channel but
the channel can be closed by applying suitable negative voltage to the gate.

4. The condition for non saturated region is

a) VDS = VGS – VTO
b) VGS < VTO
c) VDS < VGS – VTO
d) VDS > VGS – VTO

Answer: c
Explanation: The condition for non-saturated region is Vds lesser Vgs – Vt. In non-
saturation region MOSFET acts as voltage source. Varying Vds will provide significant
change in drain current.

5. In enhancement mode, device is in _________ condition

a) conducting
b) non conducting
c) partially conducting
d) insulating
Answer: b
Explanation: In enhancement mode, the device is in non-conducting condition. For n-type
FET, threshold voltage is positive and p-type threshold voltage is negative.

6. The condition for non-conducting mode is

a) VDS < VGS
b) VGS < VDS
c) VGS = VDS = 0
d) VGS = VDS = VS = 0

Answer: d
Explanation: In enhancement mode the device is in non-conducting mode, and its condition
is VDS = VGS = VS = 0.

7. nMOS is
a) donor doped
b) acceptor doped
c) all of the mentioned
d) none of the mentioned

Answer: b
Explanation: nMOS transistors are acceptor doped. Acceptor is a dopant which when added
forms p-type region. Some of the acceptors are silicon, boron, aluminum etc.

8. MOS transistor structure is

a) symmetrical
b) non symmetrical
c) semi symmetrical
d) pseudo symmetrical

Answer: a
Explanation: MOS transistor structure is completely symmetrical with respect to source and
drain.

9. pMOS is
a) donor doped
b) acceptor doped
c) all of the mentioned
d) none of the mentioned

Answer: a
Explanation: nMOS is acceptor doped and pMOS is donor doped devices. Acceptor doped
forms p-type region and donor doped forms n-type region.

10. Inversion layer in enhancement mode consists of excess of

a) positive carriers
b) negative carriers
c) both in equal quantity
d) neutral carriers

Answer: b
Explanation: Inversion layer in enhancement mode consists of excess of negative carriers
that is electron.
 11. The condition for linear region is
a) VGS lesser than VTO
b) VGS greater than VTO
c) VDS lesser than VGS
d) VDS greater than VGS

Answer: b
Explanation: The condition for linear region is VGS > VTO. The power of MOS in linear region
is less. It is a power dissipating region.

12. As source drain voltage increases, channel depth

a) increases
b) decreases
c) logarithmically increases
d) exponentially increses

Answer: b
Explanation: As source drain voltage Vds increases, the channel depth at the drain end
decreases.

13. MOS transistors consists of

a) semiconductor layer
b) metal layer
c) layer of silicon-di-oxide
d) all of the mentioned

Answer: d
Explanation: MOS transistors are formed as a sandwich consisting of a semiconductor
layer, a silicon-di-oxide layer and a metal layer.

14. In MOS transistors, _____ is used for their gate

a) metal
b) silicon-di-oxide
c) polysilicon
d) gallium

Answer: c
Explanation: In MOS transistors, polycrystalline silicon is used for their gate region instead
of metal. Polysilicon gates have replaced all other older devices.

15. The gate region consists of

a) insulating layer
b) conducting layer
c) lower metal layer
d) p type layer

Answer: b
Explanation: The gate region is a sandwich consisting of semiconductor layer, an insulating
layer and an upper metal layer.

16. Electrical charge flows from

a) source to drain
b) drain to source
c) source to ground
 d) source to gate

Answer: a
Explanation: Electrical charge or current flows from source to drain depending on the
charge applied to the gate region.

17. Source in MOS transistors is doped with ______ material

a) n-type
b) p-type
c) n & p type
d) none of the mentioned

Answer: a
Explanation: Source and drain in the MOS transistors are doped with N-type material and
substrate is doped with p-type material.

18. In N channel MOSFET which is the more negative of the elements?

a) source
b) gate
c) drain
d) source and drain

Answer: a
Explanation: In N channel MOSFET, source is the more negative of the elements and in the
case of P channel MOSFET, it is the more positive of the elements.
19. If the gate is given sufficiently large charge, electrons will be attracted to
a) drain region
b) channel region
c) switch region
d) bulk region

Answer: b
Explanation: If the gate is given sufficiently large charge, the negative charge carreirs,
electrons will be attracted from the bulk of the substrate material into the channel region
below the oxide.

20. Enhancement mode device acts as ____ switch, depletion mode acts as _____
switch
a) open, closed
b) closed, open
c) open, open
d) close, close

Answer: a
Explanation: Enhancement mode transistor acts as open switch whereas depletion mode
transistor acts as normally closed switch.

21. Depletion mode MOSFETs are more commonly used as

a) switches
b) resistors
c) buffers
d) capacitors
Answer: b
Explanation: Depletion mode MOSFETs are more commonly used as resistors than as
switches. As permanently on switch it has high resistance.

22. Enhancement mode MOSFETs are more commonly used as

a) switches
b) resistors
c) buffers
d) capacitors

Answer: a
Explanation: Enhancement mode MOSFETs are more commonly used as switches and
depletion mode devices are more used as resistors.

23. Depletion mode transistor should be large.

a) true
b) false

Answer: a
Explanation: Depletion mode transistors should be made large that is long and thin to create
the large ‘on’ resistance.
24. Which expression is true?
a) charging time < discharging time
b) charging time > discharging time
c) charging time = discharging time
d) charging time and discharging time are not related

Answer: b
Explanation: When driving a capacitive output load, charging time will be long compared to
the discharging time.
25. Overheating in device occurs due to more number of resistors per unit area.
a) true
b) false

Answer: a
Explanation: When the number of resistors per unit area increases, the device may
dissipate heat very well. This results in device overheating which leads to its failure.
26. In n channel MOSFET, _____ is constant
a) channel length
b) channel width
c) channel depth
d) channel concentration

Answer: a
Explanation: In all n channel MOSFET transistors, channel length is constant where as
channel width can be varied.
27. VLSI technology uses ________ to form integrated circuit
a) transistors
b) switches
c) diodes
d) buffers
Answer: a
Explanation: Very-large scale integration is the process of creating integrated circuit with
thousands of transistors into one single chip.

28. Medium scale integration has

a) ten logic gates
b) fifty logic gates
c) hundred logic gates
d) thousands logic gates

Answer: c
Explanation: Small scale integration has one or more logic gate. Further improved
technology is medium scale integration which consists of hundred logic gates. Large scale
integration has thousand logic gates.

29. ______ architecture is used to design VLSI

a) system on a device
b) single open circuit
c) system on a chip
d) system on a circuit

Answer: c
Explanation: SoC that is system on a chip architecture is used to design the very high level
integrated circuit.

30. The design flow of VLSI system is

1. Architecture design 2. Market requirement 3. Logic design 4. HDL coding
a) 2-1-3-4
b) 4-1-3-2
c) 3-2-1-4
d) 1-2-3-4

Answer: a
Explanation: The order of the design flow of VLSI circuit is market requirement, architecture
design, logic design, HDL coding and then verification.

31. ______ is used in logic design of VLSI

a) LIFO
b) FIFO
c) FILO
d) LILO

Answer: b
Explanation: First in first out (FIFO) technique and finite state machine technique is used in
the logic design of the VLSI circuits.
32. Which provides higher integration density?
a) switch transistor logic
b) transistor buffer logic
c) transistor transistor logic
d) circuit level logic

Answer: c
Explanation: Transistor-transistor logic offers higher integration density and it became the
first integrated circuit revolution.
 33. Physical and electrical specification is given in
a) architectural design
b) logic design
c) system design
d) functional design

Answer: d
Explanation: Functional design defines the major functional units of the system,
interconnections, physical and electrical specifications.

34. Which is the high level representation of VLSI design

a) problem statement
b) logic design
c) HDL program
d) functional design

Answer: a
Explanation: Problem statement is a high level representation of the system. Performance,
functionality and physical dimensions are considered here.

35. nMOS fabrication process is carried out in

a) thin wafer of a single crystal
b) thin wafer of multiple crystals
c) thick wafer of a single crystal
d) thick wafer of multiple crystals

Answer: a
Explanation: nMOS fabrication process is carried out in thin wafer of a single crystal with
high purity.

36. _____ impurities are added to the wafer of the crystal

a) n impurities
b) p impurities
c) silicon
d) crystal

Answer: b
Explanation: p impurities are introduced as the crystal is grown. This increases the hole
concentration in the device.

37. In nMOS device, gate material could be

a) silicon
b) polysilicon
c) boron
d) phosphorus

Answer: b
Explanation: In nMOS device, the gate material could be metal or polysilicon. This
polysilicon layer has heavily doped polysilicon deposited by CVD.
38. The commonly used bulk substrate in nMOS fabrication is
a) silicon crystal
b) silicon-on-sapphire
c) phosphorus
d) silicon-di-oxide
Answer: b
Explanation: In nMOS fabrication, the bulk substrate used can be either bulk silicon or
silicon-on-sapphire.

39. Heavily doped polysilicon is deposited using

a) chemical vapor decomposition
b) chemical vapor deposition
c) chemical deposition
d) dry deposition

Answer: b
Explanation: The polysilicon layer consists of heavily doped polysilicon deposited by
chemical vapour deposition.

40. SIlicon-di-oxide is a good insulator.

a) true
b) false

Answer: a
Explanation: Silicon-di-oxide is a very good insulator so a very thin layer is required in the
fabrication of MOS transistor.
41. _______ is used to suppress unwanted conduction
a) phosphorus
b) boron
c) silicon
d) oxygen

Answer: b
Explanation: Boron is used to suppress the unwanted conduction between transistor sites. It
is implanted in the exposed regions.
42. Which is used for the interconnection?
a) boron
b) oxygen
c) aluminum
d) silicon

Answer: c
Explanation: Aluminum is the suitable material used for the circuit interconnection or
connecting two layers.

43. CMOS technology is used in developing

a) microprocessors
b) microcontrollers
c) digital logic circuits
d) all of the mentioned

Answer: d
Explanation: CMOS technology is used in developing microcontrollers, microprocessors,
digital logic circuits and other integrated circuits.

44. CMOS has

a) high noise margin
b) high packing density
c) high power dissipation
 d) high complexity

Answer: b
Explanation: Some of the properties of CMOS are that it has low power dissipation, high
packing density and low noise margin.

45. In CMOS fabrication, nMOS and pMOS are integrated in same substrate.
a) true
b) false

Answer: a
Explanation: In CMOS fabrication, nMOS and pMOS are integrated in the same chip
substrate. n-type and p-type devices are formed in the same structure.

46. P-well is created on

a) p substrate
b) n substrate
c) p & n substrate
d) none of the mentioned

Answer: b
Explanation: P-well is created on n substrate to accommodate n-type devices whereas p-
type devices are formed in the ntype substrate.

47. Which type of CMOS circuits are good and better?

a) p well
b) n well
c) all of the mentioned
d) none of the mentioned

Answer: b
Explanation: N-well CMOS circuits are better than p-well CMOS circuits because of lower
substrate bias effect.

48. MOS technology has more load driving capability.

a) true
b) false

Answer: b
Explanation: One of the disadvantage of MOS technology is it has limited load driving
capabilities.

49. What is the disadvantage of MOS device?

a) limited current sourcing
b) limited voltage sinking
c) limited voltage sourcing
d) unlimited current sinking

Answer: a
Explanation: MOS devices have limited current sourcing and current sinking abilities.
50. CMOS is
a) unidirectional
b) bidirectional
c) directional
 d) none of the mentioned

Answer: a
Explanation: CMOS is unidirectional.

51. Which has high input resistance?

a) nMOS
b) CMOS
c) pMOS
d) BiCMOS

Answer: b
Explanation: CMOS technology has high input resistance and is best for constructing simple
low-power logic gates.

52. IDS(drain current) depends on

a) VG
b) VDS
c) VDD
d) VSS

Answer: b
Explanation: Ids depends on both Vgs and Vds. The charge induced is dependent on gate
to source voltage Vgs also charge can be moved from source to drain under influence of
electric field created by Vds.
53. IDS can be given by
a) Qc x Ʈ
b) Qc / Ʈ
c) Ʈ / Qc
d) Qc / 2Ʈ

Answer: b
Explanation: Ids can be given as charge induced in the channel(Qc) divided by transit time
(Ʈ). Ids is equivalent to (-Isd).

54. Transit time can be given by

a) L / v
b) v / L
c) v x L
d) v x d

Answer: a
Explanation: Transit time (Ʈ) can be given by lenght of channel(L) by velocity(v). Transit
time is the time required for an electron to travel between two electrodes.
55. EDS is given by
a) VDS / L
b) L / VDS
c) VDS x L
d) VDD / L

Answer: a
Explanation: Electric field(EDS) can be given as the ratio of VDS and L. EDS is the electric field
created from drain to source due to volta VDS.
 56. In resistive (Linear) region
a) VDS greater than (VGS – VTO)
b) VDS lesser than (VGS – VTO)
c) VGS greater than (VDS – VTO)
d) VGS lesser than (VDS – VTO)

Answer: b
Explanation: In non-saturated or resistive region, VDS lesser than VGS – VTO where VDS is the
voltage between drain and source, VGS is the gate-source voltage and VTOis the threshold
voltage.
57. The condition for saturation is
a) VGS = VDS
b) VDS = VGS – VTO
c) VGS= VDS – VTO
d) Vds greater than VGS – VTO

Answer: b
Explanation: The condition for saturation is VDS = VGS – VTO, since at this point IR drop in
the channel equals the effective gate to channel voltage at the drain.

58. Threshold voltage is negative for

a) nMOS depletion
b) nMOS enhancement
c) pMOS depletion
d) pMOS enhancement

Answer: a
Explanation: The threshold voltage for nMOS depletion denoted as Vtd is negative.
59. The current Ids _______ as Vds increases
a) increases
b) decreases
c) remains fairly constant
d) exponentially increases

Answer: c
Explanation: The current Ids remains fairly constant as Vds increases in the saturation
region.

60. In linear region, ______ channel exists

a) uniform
b) non-uniform
c) wide
d) uniform and wide

Answer: a
Explanation: In linear region of MOSFET, the channel is uniform and narrow. This is the
concentration distribution.

61. When the channel pinches off?

a) VGS>VDS
b) VDS>VGS
c) VDS>(GS-VTO)
 d) VGS>(VDS-VTO)

Answer: c
Explanation: In MOSFET, in saturation region, when VDS > (VGS – VTO), the channel pinches
off that is the channel current at the drain spreads out.

62. MOSFET is used as

a) current source
b) voltage source
c) buffer
d) divider

Answer: a
Explanation: MOSFET is used as current source. Bipolar junction transistor also acts as
good current source.

63. The work function difference is negative for

a) silicon substrate
b) polysilicon gate
c) both of the mentioned
d) none of the mentioned

Answer: c
Explanation: The work function difference between gate and Si (Φms) is negative for silicon
substrate and polysilicon gate.
64. Substrate bias voltage is positive for nMOS.
a) true
b) false

Answer: b
Explanation: Substrate bias voltage Vsb is positive for pMOS and negative for nMOS.

65. According to body effect, substrate is biased with respect to

a) source
b) drain
c) gate
d) Vss

Answer: a
Explanation: According to body effect, substrate is biased with respect to the source. Body
effect can be seen as a change in the threshold voltage.

66. Increasing VSB, _______ the threshold voltage

a) does not effect
b) decreases
c) increases
d) exponentially increases

Answer: c
Explanation: Increasing the substrate bias voltage VSB, increases the threshold voltage
because it depletes the channel of charge carriers.

67. IDS is _______ to length L of the channel

a) directly proportional
b) inversely proportional
 c) not related
d) logarithmically related

Answer: b
Explanation: Ids is inversely proportional to the length L of the channel and using this
relationship strong dependence of output conductance on channel length can be
demonstrated.
68. Switching speed of a MOS device depends on
a) gate voltage above threshold
b) carrier mobility
c) length channel
d) all of the mentioned

Answer: d
Explanation: Switching speed of a MOS device depends on gate voltage above threshold
and on carrier mobility and inversely as the square of channel length.

69. Surface mobility depends on

a) effective drain voltage
b) effective gate voltage
c) channel length
d) effective source voltage

Answer: b
Explanation: Surface mobility is dependent on the effective gate voltage (Vgs-Vt). Electron
mobility on oriented n-type inversion layer surface is larger than that on a oriented surface.
70. MOS transistor is a
a) minority carrier device
b) majority carrier device
c) majority & minority carrier device
d) none of the mentioned

Answer: b
Explanation: MOS transistor is a majority carrier device,in which current in a conducting
channel between the source and drain is modulated by a voltage.

71. The MOS transistor is non-conducting when

a) zero source bias
b) zero threshold voltage
c) zero gate bias
d) zero drain bias

Answer: c
Explanation: The MOS transistor normally is at cut-off or becomes non-conducting with zero
gate bias (gate voltage-source voltage).

72. Inverters are essential for

a) NAND gates
b) NOR gates
c) sequential circuits
d) all of the mentioned
Answer: d
Explanation: Inverters are needed for restoring logic levels for NAND and NOR gates,
sequential and memory circuits.

73. In basic inverter circuit, ______ is connected to ground

a) source
b) gates
c) drain
d) resistance

Answer: a
Explanation: A basic inverter circuit consists of transistor with source connected to ground
and a load resistor connected from drain to positive supply rail Vdd.

74. In inverter circuit, ________ transistors preferred as load

a) enhancement
b) depletion
c) all of the mentioned
d) none of the mentioned

Answer: b
Explanation: Depletion mode transistors are preferred to be used as load in inverter circuits
as it occupies lesser area and are produced on silicon substrate unlike resistors.

75. For depletion mode transistor, gate should be connected to

a) source
b) drain
c) ground
d) positive voltage rail

Answer: a
Explanation: For the depletion mode transistor, gate is connected to source so it is always
on and only the characteristic curve Vgs=0 is relevant.

76. In nMOS inverter configuration depletion mode device is called as

a) pull up
b) pull down
c) all of the mentioned
d) none of the mentioned

Answer: a
Explanation: In nMOS inverter configuration, depletion mode devices are called as pull up
and enhancement mode devices are called as pull down transistor.

77. How is depletion load nMOS inverter represented?

a) b)
 c) d)

Answer: b
Explanation: nMOS inverter can be represented using two transistors, depletion mode
pMOS transistor followed by nMOS transistor. Input is given to the nMOS.

78. Pass transistors are transistors used as

a) switches connected in series
b) switches connected in parallel
c) inverters used in series
d) inverter used in parallel

Answer: a
Explanation: Pass transistors are transistor used as switches in series with lines carrying
logic levels due to its isolated nature of the gate.
79. In depletion mode pull-up, dissipation is high since current flows when
a) Vin = 1
b) Vin = 0
c) Vout = 1
d) Vout = 0

Answer: a
Explanation: In nMOS depletion mode pull-up, dissipation is high since current flows Vin =
logical 1.

80. In complementary transistor pull-up, current flows when

a) Vin = 1
b) Vin = 0
c) current doesn’t flow
d) Vout = Vin

Answer: c
Explanation: In complementary transistor pull-up no current flows either for logical 1 or 0,
full logical 1 and 0 levels are presented at the output.
81. CMOS inverter has ______ regions of operation
a) three
b) four
c) two
d) five

Answer: d
Explanation: CMOS inverter has five distint regions of operation which can be determined
by plotting CMOS inverter current versus Vin.
 82. If n-transistor conducts and has large voltage between source and drain, then
it is said to be in _____ region
a) linear
b) saturation
c) non saturation
d) cut-off

Answer: b
Explanation: If n-transistor conducts and has large voltage between source and drain, then
it is in saturation.

83. If p-transistor is conducting and has small voltage between source and drain,
then the it is said to work in
a) linear region
b) saturation region
c) non saturation resistive region
d) cut-off region

Answer: c
Explanation: If p-transistor is conducting and has small voltage between source and drain,
then it is said to be in unsaturated resistive region.

84. In the region where inverter exhibits gain, the two transistors are in _______
region
a) linear
b) cut-off
c) non saturation
d) saturation

Answer: d
Explanation: In the region where the inverter exhibits gain, the two transistors n and p
operates in saturation region.

85. If both the transistors are in saturation, then they act as

a) current source
b) voltage source
c) divider
d) buffer

Answer: a
Explanation: When both the transistors are in saturation, then act as current sources so that
the equivalent circuit is two current sources between Vdd and Vss.

86. Mobility of electron depends on

a) transverse electric field
b) VG
c) VDD
d) Channel length

Answer: a
Explanation: Mobility is affected by transverse electric field and thus also depends on
VGSand the mobility of p-device and n-device are inherently unequal.

87. In CMOS inverter, transistor is a switch having

a) infinite on resistance
b) finite off resistance
 c) buffer
d) infinite off resistance

Answer: b
Explanation: In CMOS inverter, transistor is a awitch having finite on resistance and infinite
off resistance.

88. CMOS inverter has ______ output impedance

a) low
b) high

Answer: a
Explanation: CMOS inverter has low output impedance and this makes it less prone to
noise and disturbance.

89. Input resistance of CMOS inverter is

a) high
b) low

Answer: a
Explanation: Input resistance of CMOS inverter is extremely high as it is a perfect insulator
and draws no dc input source.

90. Increasing fan-out, ______ the propogation delay

a) increases
b) decreases
c) does not affect
d) exponentially decreases

Answer: a
Explanation: In CMOS inverter, increasing the fan-out also increases the propogation delay.
Fan-out is a term that defines the maximum number of digital inputs that the output of a
single logic gate can feed.

91. Fast gate can be built by keeping

a) low output capacitance
b) high on resistance
c) high output capacitance
d) input capacitance does not affect speed of the gate

Answer: a
Explanation: Fast gate can be built by keeping the output capacitance small and by
decreasing the on resistance of the transistor.

92. The conductivity of the pure silicon is raised by :

a) Introducing Dopants (impurities)
b) Increasing Pressure
c) Decreasing Temperature
d) Deformation of Lattice

Answer: a
Explanation: By introducing Dopants free charge carriers increases further increasing the
conductivity of silicon.
93. The n-type semiconductor have _______ as majority carriers :
a) Holes
 b) Negative ions
c) Electrons
d) Positive ions

Answer: c
Explanation: In n-type semiconductor the majority charge carriers present are electrons.

94. The majority carriers of p-type semiconductor are :

a) Holes
b) Negative ions
c) Electrons
d) Positive ions

Answer: a
Explanation: The majority charge carriers of n-type semiconductor are holes.

95. The n-MOS transistor is made up of:

a) N-type source, n-type drain and p-type bulk
b) N-type source, p-type drain and p-type bulk
c) P-type source, n-type drain and n-type bulk
d) P- type source, p-type drain and n-type bulk

Answer: a
Explanation: n-MOS Transistor consists of n-type source, n-type drain and p-type bulk.

96. The correct representation of p-MOSFET is:

a) b) c) d)

Answer: b
Explanation: This is the correct representation of p-MOSFET:

97. The oxide layer formed in the MOSFET is :

a) Metal oxide
b) Silicon dioxide
c) Poly Silicon oxide
d) Oxides of Non metals

Answer: b
Explanation: Silicon Dioxide (Commonly called as glass) is the insulating oxide layer formed
in MOSFET.

98. The drain current is varied by:

a) Gate to source voltage
b) Gate current
c) Source Voltage
d) None of the mentioned

Answer: a
Explanation: The Gate to Source voltage acts as input which varies the drain current.
 99. The low voltage on the gate of p-MOSFET forms :
a) Channel of negative carriers
b) Channel is not formed
c) Channel is clipped
d) Channel of positive carriers

Answer: d
Explanation: For a p-MOS low gate voltage forms a conducting channel of positive carriers.
100. The n-MOSFET is working as accumulation mode when:
a) Gate is applied with positive voltage
b) Gate is grounded
c) Gate is applied with negative voltage
d) Gate is connected to source

Answer: c
Explanation: When the negative voltage is applied to the gate, there develops a presence of
negative charge on the gate. The mobile positively charged holes are attracted to the region
beneath the gate. This explains the formation of accumulation mode.

101. The current through the n-MOS transistor will flow when:
a) VGS > VTO, VDS =0
b) VGD < VTO, VDS =0
c) VGS > VTO, VDS >0
d) VGD > VTO, VDS <0

Answer: c
Explanation: The current flows through the n-MOS transistor when Vgs>Vtreshold, Vds>0.

102. The p-MOS Transistor is said to be in Saturation mode when:

a) VDS,p > VGS,p – VTO,p
b) VGS,p < VDS,p – VTO,p
c) VGS,p > VTO,p
d) VDS,p < VGS,p – VTO,p

Answer: d
Explanation: The pMOS transistor is in Saturation mode when VDS,p < VGS,p – VTO,p and VGS,p <
VTO,p.

103. The Fermi potential of the p-type MOSFET is :

a) φfp = (kT/q)ln(ND/NA)
b) φfp = (kT/q)ln(NA/ND)
c) φfp = (kT/q)ln(NA/ ni)
d) φfp = (kT/q)ln(ni/NA)

Answer: d
Explanation: The Fermi potential of the p-type semiconductor is φfp = (kT/q)ln(ni/NA) where
ni denotes the intrinsic carrier concentration of silicon, NA is acceptor concentration, ND is
Donor Concentration.

104. The Fermi potential(φfp) for the n-type MOSFET is :

a) φfp = (kT/q)ln(ND/NA)
b) φfp = (kT/q)ln(NA/ND)
c) φfp = (kT/q)ln(ND/ ni)
d) φfp = (kT/q)ln(ni/ND)
Answer: c
Explanation: The Fermi potential of the p-type semiconductor is φfp = (kT/q)ln(ND/ ni) where
ni denotes the intrinsic carrier concentration of silicon, NA is acceptor concentration, ND is
Donor Concentration.

105. The principle of the MOSFET operation is:

a) Control the conduction of current between the source and the drain, using the
potential difference applied at the gate voltage as a control variable
b) Control the current conduction between the source and the gate, using the electric
field applied at the drain voltage as a control variable
c) Control the current conduction between the PN junction, using the electric field
generated by the bias voltage as a control variable
d) Control the current conduction between the PN junctions, using the electric
potential generated by the gate voltage as a control variable

Answer:a
Explanation: By varying the gate voltage the current between the source and drain are
varied.

106. The conduction of current IDS depends on:

1) Gate to source voltage 2) Drain to source voltage 3) Bulk to source voltage
4) Threshold voltage 5) Dimensions of MOSFET

a) Only 1st option

b) Only 1st, 2nd and 3rd option
c) Only 5th option
d) All of the mentioned

Answer: d
Explanation: The current depends on VGS, VDS, VBS, VTO and dimensions of MOSFET.

107. The impedance at the input of n-MOS transistor circuit is :

a) Lesser than p-MOS transistor
b) Greater than BJT transistor
c) Lesser than JFET transistor
d) Zero

Answer: b
Explanation: The impedance at the input of n-MOS transistor is more than BJT transistor.

108. The depletion mode n-MOS differs from enhancement mode n-MOS in:
a) Threshold voltage
b) Channel Length
c) Switching time
d) None of the mentioned

Answer: a
Explanation: If n-MOS operates with negative threshold voltage then it is in depletion mode.
If n-MOS operates with positive threshold voltage then it is in enhancement mode.
109. The n-MOS invertor is better than BJT in terms of:
a) Fast switching time
b) Low power loss
c) Smaller overall layout area
d) All the mentioned
Answer: d
Explanation: The n-MOS invertor is better than BJT invertor due to fast switching time, low
power loss, smaller overall layout area.

110. The n-MOS invertor consists of n-MOS transistor as driven and

a ) Resistor as a load
b ) Depletion mode n-MOS as a load
c) Enhancement mode n-MOS as a load
d) Any of the mentioned

Answer: d
Explanation: the n-MOS inverter consists of n-MOS and resistor or depletion mode n-MOS
or enhancement mode n-MOS at the pull up load.

111. If the n-MOS and p-MOS of the CMOS inverters are interchanged the
output is measured at:
a) Source of the both transistor
b) Drains of the both transistor
c) Drain of n-MOS and source of p-MOS
d) Source of n-MOS and drain of p-MOS

Answer: a
Explanation: When the transistors are interchanged, The drain of n-MOS is connected to
supply voltage, drain of p-MOS is connected to ground . The output is measured at source
of both the transistors.
112. What will be the effect on output voltage if the positions of n-MOS and
p-MOS in CMOS inverter circuit are exchanged?
a) Output is same
b) Output is reversed
c) Output is always high
d) Output is always low

Answer: b
Explanation: When the input is low, p-MOS is ON and the output is pulled down to the
ground. When the input is high, n-MOS is ON and the output is pulled up to the supply
voltage.

113. The average power dissipated in resistive load n-MOS inverter is:
a) 0
b) VDD (VDD-VOL)/R
c) VDD (VDD-VOL)/2R
d) VDD (VDD-VIH)/2R

Answer: c
Explanation: When the input voltage is equal to VOH on the other hand, both the driver
MOSFET and the load resistor conduct a nonzero current. Since the output voltage in this
case is equal to VOL, DC power consumption of the inverter can be estimated as V DD.(VDD-
VOL)/2R
114. The depletion mode n-MOS as an active load is better than
enhancement load n-MOS in:
a) Sharp VTC transition and better noise margins
b) Single power supply
c) Smaller overall layout area
 d) All of the mentioned

Answer: d
Explanation: The depletion mode n-MOS transistor as load requires single power supply,
smaller overall layout area, and sharp VTC transition.

115. The enhancement mode n-MOS load inverter requires 2 different supply
voltages to:
a) Keep load transistor in cutoff region
b) Keep load transistor in linear region
c) Keep load transistor in saturation region
d) None of the mentioned

Answer: b
Explanation: The enhancement mode n-MOS load inverter requires 2 different supply
voltages to keep load transistor in linear region.

116. The CMOS inverter consist of:

a) Enhancement mode n-MOS transistor and depletion mode p-MOS transistor
b) Enhancement mode p-MOS transistor and depletion mode n-MOS transistor
c) Enhancement mode p-MOS transistor and enhancement mode p-MOS transistor
d) Enhancement mode p-MOS transistor and enhancement mode n-MOS transistor

Answer: d
Explanation: The CMOS inverter consist of enhancement mode p-MOS and enhancement
mode n-MOS.
117. In the CMOS inverter the output voltage is measured across:
a) Drain of n-MOS transistor and ground
b) Source of p-MOS transistor and ground
c) Source of n-MOS transistor and source of p-MOS transistor
d) Gate of p-MOS transistor and Gate of n-MOS transistor

Answer: a
Explanation: In the CMOS inverter the output voltage is measured across Drain of n-MOS
transistor and ground.

118. When the input of the CMOS inverter is equal to Inverter Threshold
Voltage Vth, the transistors are operating in:
a) N-MOS is cutoff, p-MOS is in Saturation
b) P-MOS is cutoff, n-MOS is in Saturation
c) Both the transistors are in linear region
d) Both the transistors are in saturation region
Answer: d

119. The switching threshold voltage VTH for an ideal inverter is equal to:
a) (VDD-VOL)/2
b) VDD
c) (VDD)/2
d) 0

Answer: c
Explanation: The switching threshold voltage VTH for an ideal inverter is equal to (VDD)/2
 120. Which of these invertors is more efficient?

a) Depletion mode n-MOS inverter b) pMOS inverter

c) CMOS inverter d) Resistive load nMOS inverter

Answer: c
Explanation: The power loss in CMOS inverter is very small and the I-V characteristics is
approximately equal to ideal inverter. Therefore the CMOS inverter is most efficient.

121. The electrical equivalent component for MOS structure is:

a) Resistor
b) Capacitor
c) Inductor
d) Switch

Answer: b
Explanation: The MOS structure acts as a capacitor with metal gate and semiconductor
acting as parallel plate conductors and oxide as dielectric between them.

122. The Fermi potential is the function of:

a) Temperature
b) Doping concentration
c) Difference between Fermi level and intrinsic Fermi level
d) All of the mentioned

Answer: d
Explanation: The Fermi potential, which is a function of temperature and doping, denotes
the difference between the intrinsic Fermi level and the Fermi level.

123. The direction of electric field when the gate voltage is zero:
a) Metal to semiconductor
b) Semiconductor to metal
c) No electric field exists
d) None of the mentioned

Answer: a
Explanation: Metal being more positive compared to semiconductor.. Electric field exists
from metal to semiconductor.
 124. When gate voltage is negative for enhancement mode n-MOS, the
direction of electric field will be:
a) Metal to semiconductor
b) Semiconductor to metal
c) No field exists
d) None of the mentioned

Answer: b
Explanation: When gate voltage is negative, holes in substrate are attracted towards
surface creating electric field from semiconductor to metal.

125. At threshold Voltage, the surface potential is:

a) – Fermi potential
b) Fermi potential
c) 2 Fermi potential
d) -2 Fermi potential

Answer:a
Explanation: When surface potential reaches –fermi potential, the surface inversion occurs.
The gate voltage which brings these changes is known as threshold voltage.

126. Surface inversion occurs when gate voltage is:

a) Less than zero
b) Less than threshold voltage
c) Equal to threshold voltage
d) Greater than threshold voltage

Answer: c
Explanation: Surface inversion occurs when gate voltage is equal to threshold voltage.

127. The energy band diagram of the MOS system when gate voltage is zero is:

a) b)

c) d)

Answer: a
Explanation: Read MOS under external bias operation
 128. For enhancement mode n-MOSFET, the threshold voltage is:
a) Equal to 0
b) Greater than zero or Positive quantity
c) Negative voltage or lesser than zero
d) All of the mentioned

Answer: b
Explanation: For enhancement mode n-MOSFET, the threshold voltage is positive quantity.
129. The threshold voltage depends on:
a) The work function difference between gate and channel
b) The gate voltage component to change surface potential
c) The gate voltage component to offset the depletion charge and fixed charges in
gate oxide
d) All of the mentioned

Answer: d
Explanation: The threshold voltage depends on: The workfunction difference between gate
and channel, The gate voltage component to change surface potential, The gate voltage
component to offset the depletion charge and fixed charges in gate oxide

130. The Energy band diagram of MOS system when gate voltage is equal to
threshold voltage is:

a) b)

c) d)

Answer: c
Explanation: Read MOS under external bias operation.

131. Input Voltage between VIH and VOH is considered as:

a) Logic Input 1
b) Logic Input 0
c) Uncertain
d) None of the mentioned

Answer: a
Explanation: None.

132. Noise Margin is :

a) Amount of noise the logic circuit can withstand
b) Difference between VOH and VIH
c) Difference between VIL and VOL
 d) All of the Mentioned

Answer: d
Explanation: Noise Margin is defined as the amount of noise the logic circuit can withstand,
it is given by difference between VOH and VIH or VIL and VOL.

133. The VIL is found from transfer characteristic of inverter by:

a) The point where straight line at VOH ends
b) The slope of the transition at a point at which the slope is equal to -1
c) The midpoint of the transition line
d) All of the mentioned

Answer: b
Explanation: The VIL is the input voltage at which the slope of the transition will be equal to -
1.

134. The VIH is found from transfer characteristic of inverter by:

a) The point where straight line at VOH ends
b) The slope of the transition at a point at which the slope is equal to -1
c) The midpoint of the transition line
d) All of the mentioned

Answer: b
Explanation: The VIH is the input voltage at which the slope of the transition will be equal to -
1. In Transfer characteristics at 2 points we will find the slope to be -1.
135. The relation between threshold voltage and Noise Margin is:
a) Vth = sqrt(Noise Margin)
b) Vth = NMH – NML
c) Vth = (NMH+NML)/2
d) None of the mentioned

Answer: d
Explanation: None.

136. The Lower Noise Margin is given by:

a) VOL – VIL
b) VIL – VOL
c) VIL ~ VOL(Difference between VIL and VOL, depends on which one is greater)
d) All of the Mentioned

Answer: b
Explanation: Noise margin = VIL-VOL.

137. The Higher Noise Margin is given by:

a) VOH – VIH
b) VIH – VOH
c) VIH ~ VOH(Difference between VIH and VOH, depends on which one is greater)
d) All of the mentioned

Answer: a
Explanation: Noise margin =VOH – VIH.

138. The Uncertain or transition region is between:

a) VIH and VOH
b) VIL and VOL
 c) VIH and VIL
d) VOH and VOL

Answer: c
Explanation: In Input the uncertain region is VIH and VIL.

139. The noise immunity ____________ with noise margin

a) Decreases
b) Increases
c) Constant
d) None of the Mentioned

Answer: b
Explanation: The noise immunity is directly proportional to noise margin.

140. If VIL of the 2nd gate is higher than VOL of the 1st gate, then logic output
0 from the 1st gate is considered as :
a) Logic input 1
b) Uncertain
c) Logic input 0
d) None of the mentioned

Answer: c
Explanation: Logic output 0 from first gate is considered as logic input 0 at second gate as it
lies within the range.

141. If VIL of the 2nd gate is lower than VOL of the 1st gate, then logic output 0
from the 1st gate is considered as :
a) Logic input 1
b) Uncertain
c) Logic input 0
d) None of the mentioned

Answer: b
Explanation: The level of output signal from 1st gate is higher than the range for low input at
2nd gate. So it is uncertain.

142. Input Voltage between VIL and VOL is considered as:

a) Logic Input 1
b) Logic Input 0
c) Uncertain
d) None of the mentioned

Answer: b
Explanation: Read VTC of inverter

143. If VIH of the 2nd gate is higher than VOH of the 1st gate, then logic output
0 from the 1st gate is considered as :
a) Logic input 1
b) Uncertain
c) Logic input 0
d) None of the mentioned
Answer: b
Explanation: The level of output signal from 1st gate is higher than the range for low input at
2nd gate. So it is uncertain.

144. Determine the Noise Margin for 5V CMOS inverter gate:

a) NMH = 1V and NML = 1V

b) NMH = 3.7V and NML = 0.2V
c) NMH = 0.94V and NML = 1V
d) NMH = 0.2V and NML =0.5V

Answer: c
Explanation: NMH = VOH – VIH, NML = VIL - VOL

145. Noise margin of CMOS is :

a) Better than TTL and ECL
b) Less than TTL and ECL
c) Equal to TTL and ECL
d) None of the Mentioned

Answer: a
Explanation: None.

Reference:

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