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Event in Ystem Verilog

uvm_event provides additional functionality over SystemVerilog events such as passing data when triggered and setting callbacks. It allows data to be passed when triggering an event using trigger() and get_trigger_data(). Callbacks can be registered and used to disable event triggering. The number of waiters and trigger time can also be obtained using functions like get_num_waiters() and get_trigger_time().

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Dan Kumar Yadav
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54 views1 page

Event in Ystem Verilog

uvm_event provides additional functionality over SystemVerilog events such as passing data when triggered and setting callbacks. It allows data to be passed when triggering an event using trigger() and get_trigger_data(). Callbacks can be registered and used to disable event triggering. The number of waiters and trigger time can also be obtained using functions like get_num_waiters() and get_trigger_time().

Uploaded by

Dan Kumar Yadav
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Advantage of uvm_event over SV event and how to

disable uvm_event using callback


The uvm_event#(type T = uvm_object) class is an extension of the abstract uvm_event_base class.
The optional parameter T allows the user to define a data type which can be passed during an event
trigger. uvm_event class is an abstract wrapper class around SystemVerilog event construct.

It provides additional services such as over traditional SystemVerilog event like,


1) pass data when event is triggered,
A traditional Systemverilog event does not have functionality to pass data when event is triggered.
While uvm_event adds this functionality. So, you can pass the transaction class handle when some
event is triggered.
By calling trigger task we can trigger the event and optionally give the data which we want to pass
using uvm_event.
By calling wait_trigger()/wait_ptrigger() task of uvm_event we can wait for event to be trigger and then
by calling get_trigger_data() function we can get data.
or we can directly use only one task wait_trigger_data()/wait_ptrigger_data() of uvm_event to wait for
event to be triggered and to get the data.

2) setting callbacks,
We can also add callbacks whenever an event is triggered. This is done by registering a callback
class with particular event.

3) maintaining the number of waiters,


We can get the number of processes waiting on the event (using get_num_waiters() function).

4) maintaining the time when event was triggered,


We can get the time that this event was last triggered (using get_trigger_time() function)

Like SystemVerilog event has trigger (@event) and persistent trigger (wait(event.triggered)) mode,
uvm_event also has trigger (wait_trigger task) and persistent trigger (wait_ptrigger task).

Let's go through below example and see how we can transfer data using uvm_event and how we can
disable uvm_event from triggering using callbacks of uvm_event

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