Fundamentals of

Device and Systems

Packaging
Technologies and Applications

Rao R. Tummala, Ph.D.  Editor

Georgia Institute of Technology, USA

Second Edition

New York Chicago San Francisco

Athens London Madrid
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00_Tummala_FM_i-xx.indd 1 26/06/19 12:08 pm

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Fundamentals of Device and Systems Packaging: Technologies and Applications,

Second Edition

Copyright © 2019, 2001 by McGraw-Hill Education. All rights reserved. Printed in the United
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The first edition of this book was titled Fundamentals of Microsystems Packaging.

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 I would like to dedicate this book:

To my parents: For your lifelong dedication to me as your only child, for your love
and support, and for teaching me the meaning of family and the value of education.

To my family (Anne, Dinesh, Vijay, and Suneel and grandchildren Gracen, Mason,
and Cooper): For being my love, pride, and joy to go to work for every day.

To my teachers: For teaching me how to learn well and quickly and for insisting on
my getting the best education at any cost.

To my students: For allowing me to learn with you and to teach you those principles
I believe in, in preparing you and challenging you to be the best you can be.

To IBM: For giving me endless opportunities to learn, contribute, grow, and

become an IBM Fellow, my ultimate goal.

To Georgia Tech: For allowing me to pursue my dream of being part of the

new generation of industry-centric academicians.

To PRC team: For realizing my dream of educating interdisciplinary

individual students, for exploring the SOP vision, and for educating the world
about it through books and classes.

To NSF: For allowing me to pursue my dream of impacting the industry with the needed
strategic technologies and educated workforce.

To my academic colleagues: For accepting me into your world, for using this book,
and for working to make packaging an academic subject.

Finally, thank you to the book’s coordinator, Karen May, Georgia Institute of Technology;
the chapters editor, Prof. Raj Pulugurtha, Florida International University (FIU);
and, for graphics, Reed Crouch, Karen May, and Leonard Mendoza.

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 About the Editor
Prof. Rao R. Tummala is a Distinguished and
Endowed Chair Professor at the Georgia Institute
of Technology, USA. He is well known as an
industrial technologist, technology pioneer, and
educator.
Prior to joining Georgia Tech, he was an IBM
Fellow and the Director of IBM’s Advanced S
­ ystems
Packaging Technology Lab. He pioneered major
technologies such as plasma display in the 1970s;
and the first three generations of 100-chip MCM package integration,
based on the first LTCC, HTCC, and thin-film RDL, introducing the
original MCM concept behind today’s 2.5D packages for servers, main-
frames, and supercomputers.
As an educator, Prof. Tummala was instrumental in setting up at
Georgia Tech the largest academic center funded by NSF, the
­Microsystems Packaging Research Center, of which he is Director. He
pioneered a vision for an integrated approach to research, education,
and industry collaborations with companies in the USA, Europe,
Japan, Korea, Taiwan, India, and China. The Center has produced
more than 1200 Ph.D. and M.S. packaging engineers, supplying the
entire electronics industry.
Prof. Tummala has published 850 technical papers and invented
technologies that resulted in over 110 patents. He is the author of the
first and best-selling microelectronics packaging reference book,
Microelectronics Packaging Handbook, the definitive work in the field;
the first undergraduate textbook, Fundamentals of Microsystems Pack-
aging; and the book that introduced the SOP concept, Introduction to
System-on-Package. Prof. Tummala has received more than 50 ­industry,
academic, and professional society awards. He is a Member of NAE,
an IEEE Fellow, and past president of IEEE EPS and IMAPS.

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 Contents
Contributors  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii
Preface  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix
1 Introduction to Device and Systems Packaging Technologies 
Prof. Rao R. Tummala. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1  What Is Packaging and Why?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1.1  What Is Packaging?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.2  Why Is Packaging Important?. . . . . . . . . . . . . . . . . . . . . . . 6
1.1.3  Every IC and Device Has to Be Packaged. . . . . . . . . . . . . 7
1.1.4  Controls Performance of Computers. . . . . . . . . . . . . . . . . 7
1.1.5  Controls Size of Consumer Electronics . . . . . . . . . . . . . . . 7
1.1.6  Controls Reliability of Electronics. . . . . . . . . . . . . . . . . . . . 7
1.1.7  Controls Cost of Electronic Products. . . . . . . . . . . . . . . . . 7
1.1.8  Required in Nearly Everything. . . . . . . . . . . . . . . . . . . . . . 7
1.2 Anatomy of an Electronic Packaged System
from a Packaging Point of View. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2.1  Fundamentals of Packaging. . . . . . . . . . . . . . . . . . . . . . . . 8
1.2.2 Systems Packaging Involves Electrical, Mechanical,
and Materials Technologies. . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2.3 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3  Devices and Moore’s Law . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.1  On-Chip Interconnections. . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3.2  Interconnect Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3.3 The Resistance and Capacitance Delays (RC Delays)
of On-Chip Interconnects. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.3.4  Future of Device Scaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.4 Electronic Technology Waves: Microelectronics, RF/Wireless,
Photonics, MEMS, and Quantum Devices . . . . . . . . . . . . . . . . . . . 16
1.4.1  Microelectronics: The First Technology Wave. . . . . . . . . . 16
1.4.2  RF and Wireless: The Second Technology Wave. . . . . . . . 18
1.4.3  Photonics: The Third Technology Wave. . . . . . . . . . . . . . . 19
1.4.4 Micro-Electro-Mechanical Systems (MEMS):
The Fourth Technology Wave. . . . . . . . . . . . . . . . . . . . . . . 21
1.4.5  Quantum Devices and Computing: Fifth Wave. . . . . . . . 22
1.5  Packaging and Moore’s Law for Packaging . . . . . . . . . . . . . . . . . . 23
1.5.1  Three Eras in Packaging. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.5.2  Moore’s Law or SOC Era (1960–2010) . . . . . . . . . . . . . . . . 25
1.5.3  Moore’s Law for Packaging Era from 2010 to 2025 . . . . . 26
1.5.4  Moore’s Law for Systems Era from 2025. . . . . . . . . . . . . . 27

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 vi Contents

1.6  Electronic Systems Technologies Trends . . . . . . . . . . . . . . . . . . . . . 29

1.6.1  Core Packaging Technologies . . . . . . . . . . . . . . . . . . . . . . . 29
1.6.2  Packaging Technologies and Their Trends . . . . . . . . . . . . 30
1.7  Future Outlook. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.7.1  Emerging Computing Systems. . . . . . . . . . . . . . . . . . . . . . 33
1.7.2  Emerging 3D Systems Packaging. . . . . . . . . . . . . . . . . . . . 34
1.8  How the Book Is Organized. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
1.9  Homework Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1.10  Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Part 1 Fundamentals of Packaging

2 Fundamentals of Electrical Design for Signals, Power, and
Electromagnetic Interference  Prof. Eakhwan Song,
Prof. Dong Gun Kam, Prof. Joungho Kim, Prof. Madhavan Swaminathan,
and Prof. Andrew F. Peterson. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.1  What Is Electrical Package Design and Why?. . . . . . . . . . . . . . . . . 45
2.2  Electrical Anatomy of a Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.2.1  Fundamentals of Electrical Package Design. . . . . . . . . . . 47
2.2.2 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2.3  Signal Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.3.1  Devices and Interconnections. . . . . . . . . . . . . . . . . . . . . . . 54
2.3.2  Kirchhoff’s Laws and Transit Time Delay. . . . . . . . . . . . . 58
2.3.3  Transmission Line Behavior of Interconnections. . . . . . . 59
2.3.4  Characteristic Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.3.5 Typical Transmission Line Structures Used as
Package Interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.6  Transmission Line Losses. . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.3.7 Crosstalk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.4  Power Distribution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.4.1  Power Supply Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.4.2  Inductive Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.4.3  Effective Inductance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
2.4.4  Effect of Package Design on Inductance . . . . . . . . . . . . . . 76
2.4.5  Decoupling Capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2.5  Electromagnetic Interference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
2.6  Summary and Future Trends. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.7  Homework Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
2.8  Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3 Fundamentals of Thermal Technologies  Dr. Kamal Sikka,
Prof. Yogendra Joshi, and Mr. Justin Broughton . . . . . . . . . . . . . . . . . . . . . . . . 91
3.1  What Is Thermal Management and Why?. . . . . . . . . . . . . . . . . . . . 93
3.2  Anatomy of a Thermal Package System. . . . . . . . . . . . . . . . . . . . . . 94
3.2.1  Fundamentals of Heat Transfer. . . . . . . . . . . . . . . . . . . . . . 94
3.2.2 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

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 Contents vii

3.3  Chip Level Thermal Technologies. . . . . . . . . . . . . . . . . . . . . . . . . . . 104

3.3.1  Thermal Interface Materials (TIMs). . . . . . . . . . . . . . . . . . 104
3.3.2  Heat Spreaders. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
3.3.3  Thermal Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
3.4  Module Level Thermal Technologies. . . . . . . . . . . . . . . . . . . . . . . . 114
3.4.1  Heat Sinks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
3.4.2  Heat Pipes and Vapor Chambers . . . . . . . . . . . . . . . . . . . . 117
3.4.3  Closed-Loop Liquid Cooling. . . . . . . . . . . . . . . . . . . . . . . . 121
3.4.4  Cold Plates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
3.4.5  Immersion Cooling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
3.4.6  Jet Impingement Cooling. . . . . . . . . . . . . . . . . . . . . . . . . . . 125
3.4.7  Spray Cooling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
3.5  System Level Thermal Technologies. . . . . . . . . . . . . . . . . . . . . . . . 127
3.5.1  Air Cooling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
3.5.2  Hybrid Cooling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
3.5.3  Immersion Cooling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
3.6  Power and Cooling Technologies for Electric Vehicles . . . . . . . . . 132
3.7  Summary and Future Trends. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
3.8  Homework Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
3.9  Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
4 Fundamentals of Thermo-Mechanical Reliability 
Prof. Suresh K. Sitaraman, Dr. Krishna Tunga, and Prof. John H. L. Pang . . . 137
4.1  What Is Thermo-Mechanical Reliability?. . . . . . . . . . . . . . . . . . . . . 139
4.2  Anatomy of a Package with Failures and Failure Mechanisms. . . . . 139
4.2.1  Fundamentals of Thermo-Mechanical Reliability . . . . . . 141
4.2.2  Thermo-Mechanical Modeling . . . . . . . . . . . . . . . . . . . . . . 143
4.2.3 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
4.3 Types of Thermo-Mechanical-Induced Failures
and Design Guidelines for Reliability. . . . . . . . . . . . . . . . . . . . . . . 148
4.3.1  Fatigue Failures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
4.3.2  Brittle Fractures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
4.3.3  Creep-Induced Failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
4.3.4  Delamination-Induced Failures . . . . . . . . . . . . . . . . . . . . . 158
4.3.5  Plastic Deformation Failures. . . . . . . . . . . . . . . . . . . . . . . . 161
4.3.6  Warpage-Induced Failures. . . . . . . . . . . . . . . . . . . . . . . . . . 162
4.4  Summary and Future Trends. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
4.5  Homework Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
4.6  Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
5 Fundamentals of Package Materials at Microscale and Nanoscale 
Dr. Himani Sharma, Prof. Markondeya Raj Pulugurtha, Prof. C. P. Wong,
and Dr. Rabindra Das. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
5.1  What Is the Role of Materials in Packaging?. . . . . . . . . . . . . . . . . . 173
5.2  Anatomy of a Package with a Variety of Materials . . . . . . . . . . . . 173
5.2.1  Fundamentals of Package Materials. . . . . . . . . . . . . . . . . . 173
5.2.2 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

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 viii Contents

5.3  Package Materials, Processes, and Properties. . . . . . . . . . . . . . . . . 177

5.3.1  Substrate Materials, Processes, and Properties. . . . . . . . . 177
5.3.2 Interconnection and Assembly Materials, Processes,
and Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
5.3.3 Passive Component Materials, Processes,
and Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
5.3.4 Thermal and Thermal Interface Materials (TIMs),
Processes, and Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . 207
5.4  Summary and Future Trends. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
5.5  Homework Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
5.6  Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

6 Fundamentals of Ceramic, Organic, Glass, and Silicon

Package Substrates   Mr. Chandra Nair, Dr. Venky Sundaram,
Prof. Markondeya Raj Pulugurtha, Mr. Fuhan Liu, Dr. Vijay Sukumaran,
and Mr. Bartlet H. DeProspo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
6.1  What Is a Package Substrate and Why?. . . . . . . . . . . . . . . . . . . . . . 219
6.2 Anatomy of Three Package Substrates: Ceramics,
Organic Laminates, and Silicon. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
6.2.1  Fundamentals of Package Substrates. . . . . . . . . . . . . . . . . 223
6.2.2 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
6.3  Package Substrate Technologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
6.3.1  Historical Trends. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
6.4  Thick-Film Substrates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
6.4.1  Ceramic Substrates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
6.5  Thin-Film Substrates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
6.5.1  Organic Substrates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
6.5.2  Glass Substrates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
6.6 Ultra-Thin-Film Substrates with Semiconductor
Packaging Processes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
6.6.1  Silicon Substrates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
6.7  Summary and Future Trends. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
6.8  Homework Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
6.9  Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

7 Fundamentals of Passive Components and Integration

with Active Devices  Prof. Markondeya Raj Pulugurtha,
Dr. Parthasarathi Chakraborti, Dr. John Prymak,
Dr. Swapan Bhattacharaya, Dr. Saumya Gandhi, and Dr. Dibyajat Mishra. . . 281
7.1  What Are Passive Components and Why? . . . . . . . . . . . . . . . . . . . 283
7.2  Anatomy of Passive Components. . . . . . . . . . . . . . . . . . . . . . . . . . . 283
7.2.1  Fundamentals of Passive Components . . . . . . . . . . . . . . . 286
7.2.2 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
7.3  Passive Component Technologies. . . . . . . . . . . . . . . . . . . . . . . . . . . 311
7.3.1  Discrete Passives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
7.3.2  Integrated Passive Devices (IPDs) . . . . . . . . . . . . . . . . . . . 312

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 Contents ix

7.3.3  Embedded Discrete Passives. . . . . . . . . . . . . . . . . . . . . . . . 314

7.3.4  Embedded Thin-Film Passives. . . . . . . . . . . . . . . . . . . . . . 314
7.4  Functional Modules with Passives and Actives. . . . . . . . . . . . . . . 316
7.4.1  RF Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
7.4.2  Power Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
7.4.3  Voltage Regulator Power Modules. . . . . . . . . . . . . . . . . . . 325
7.5  Summary and Future Trends. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
7.6  Homework Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
7.7  Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
8 Fundamentals of Chip-to-Package Interconnections and Assembly 
Dr. Vanessa Smet, Dr. Ninad Shahane, and Dr. Eric Perfecto. . . . . . . . . . . . . . 331
8.1 What Are Chip-to-Package Interconnections
and Assembly and Why?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
8.2  Anatomy of an Interconnection and Assembly. . . . . . . . . . . . . . . . 333
8.2.1 Types of Chip-Level Interconnections
and Assembly Technologies . . . . . . . . . . . . . . . . . . . . . . . . 334
8.2.2  Fundamentals of Interconnections and Assembly. . . . . . 336
8.2.3  Fundamentals of Assembly and Bonding. . . . . . . . . . . . . 339
8.2.4 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
8.3  Interconnection and Assembly Technologies . . . . . . . . . . . . . . . . . 342
8.3.1 Evolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
8.4  Interconnections and Assembly Technologies . . . . . . . . . . . . . . . . 345
8.4.1 Wire-Bonding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
8.4.2  Tape Automated Bonding (TAB). . . . . . . . . . . . . . . . . . . . . 348
8.4.3 Flip-Chip Interconnection and Assembly
Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
8.4.4  Copper Pillar with Solder Cap Technology. . . . . . . . . . . . 353
8.4.5  SLID Interconnection and Assembly Technology . . . . . . 354
8.5 Future Trends in Interconnection and Assembly Technologies. . . . 357
8.5.1  Extension of SLID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
8.6  Homework Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
8.7  Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
9 Fundamentals of Embedded and Fan-Out Packaging 
Dr. Beth Keser, Mr. Tailong Shi, and Prof. Rao R. Tummala. . . . . . . . . . . . . . . 367
9.1  What Is Embedding and Fan-Out Packaging and Why?. . . . . . . . 369
9.1.1  Why Embedding and Fan-Out Packaging?. . . . . . . . . . . . 370
9.2  Anatomy of a Fan-Out Wafer-Level Package (FO-WLP). . . . . . . . 371
9.2.1  A Typical Fan-Out Wafer-Level Package Process. . . . . . . 371
9.2.2 Fundamentals of Fan-Out Wafer-Level
Package Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
9.2.3 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
9.3  Fan-Out Wafer-Level Package Technologies. . . . . . . . . . . . . . . . . . 376
9.3.1 Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
9.3.2  Materials and Processes. . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
9.3.3  Fan-Out Wafer-Level Packaging Tools. . . . . . . . . . . . . . . . 387

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9.3.4 Challenges in Fan-Out Wafer-Level Packaging

Technology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
9.3.5  Applications of Fan-Out Wafer-Level Packaging. . . . . . . 391
9.4  Panel-Level Package (PLP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
9.4.1  What Is Panel-Level Packaging and Why?. . . . . . . . . . . . 393
9.4.2 Types of Manufacturing Infrastructure
for Panel-Level Packaging. . . . . . . . . . . . . . . . . . . . . . . . . . 394
9.4.3  Applications of Panel-Level Packaging. . . . . . . . . . . . . . . 395
9.5  Summary and Future Trends. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
9.6  Homework Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
9.7  Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403

10 Fundamentals of 3D Packaging with and without TSV 

Prof. Subramanian S. Iyer, Dr. Mukta Farooq, Prof. Rao R. Tummala,
Mr. Omkar Gupte, Mr. Siddharth Ravichandran, Mr. Bartlet H. DeProspo,
and Mr. Nithin Nedumthakady . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
10.1  What Are 3D ICs with TSV and Why?. . . . . . . . . . . . . . . . . . . . . . . . 409
10.1.1  Why 3D ICs with TSVs?. . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
10.2  Anatomy of a 3D Package with TSV. . . . . . . . . . . . . . . . . . . . . . . . . . 411
10.2.1  Fundamentals of 3D ICs with TSV. . . . . . . . . . . . . . . . . . . 412
10.2.2 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
10.3  3D ICs with TSV Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
10.3.1  Through-Silicon-Vias (TSVs). . . . . . . . . . . . . . . . . . . . . . . . 416
10.3.2  Ultra-Thin ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
10.3.3  Back-End-of-Line (BEOL) RDL Wiring . . . . . . . . . . . . . . . 425
10.3.4  Chip-to-Chip Interconnections within the 3D Stack . . . . 426
10.3.5  Packages for 3D IC Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . 430
10.3.6 Underfill. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
10.4  Summary and Future Trends. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
10.5  Homework Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
10.6  Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
10.7 Acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440

11 Fundamentals of RF and Millimeter-Wave Packaging 

Dr. Srikrishna Sitaraman, Prof. Emmanouil M. Tentzeris,
Prof. Markondeya Raj Pulugurtha, Dr. Junki Min, Prof. Rao R. Tummala,
and Prof. John Papapolymerou. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
11.1  What Is RF and Why?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
11.1.1  History and Evolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
11.1.2  When Was the First Mobile Phone Introduced?. . . . . . . . 444
11.2  Anatomy of an RF System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
11.2.1  Fundamentals of RF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
11.2.2  RF Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
11.3  RF Technologies and Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . 467
11.3.1 Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
11.3.2 Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467

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11.3.3 Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
11.3.4  Modulation Schemes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
11.3.5 Antenna. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
11.3.6  Components in RF Front-End Module. . . . . . . . . . . . . . . . 471
11.3.7 Filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
11.3.8  RF Materials and Components. . . . . . . . . . . . . . . . . . . . . . 475
11.3.9  RF Modeling and Characterization Techniques. . . . . . . . 481
11.3.10  Applications of RF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
11.4  What Is a Millimeter-Wave System?. . . . . . . . . . . . . . . . . . . . . . . . . . 486
11.5  Anatomy of a Millimeter-Wave Package. . . . . . . . . . . . . . . . . . . . . . 486
11.5.1  Fundamentals of Millimeter-Wave Packaging. . . . . . . . . 486
11.6  Millimeter-Wave Technologies and Applications. . . . . . . . . . . . . . . 492
11.6.1  5G and Beyond . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
11.6.2  Automotive Radars. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
11.6.3  Millimeter-Wave Imaging . . . . . . . . . . . . . . . . . . . . . . . . . . 493
11.7  Summary and Future Trends. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
11.8  Homework Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
11.9  Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
12 Fundamentals of Optoelectronics Packaging  Dr. Bruce C. Chou,
Prof. Gee Kung Chang, Dr. Daniel Guidotti, and Mr. Rui Zhang. . . . . . . . . . . 497
12.1  What Is Optoelectronics?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
12.2  Anatomy of an Optoelectronics System. . . . . . . . . . . . . . . . . . . . . . . 499
12.2.1  Fundamentals of Optoelectronics. . . . . . . . . . . . . . . . . . . . 500
12.2.2 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
12.3  Optoelectronic Technologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
12.3.1  Active Optoelectronic Devices . . . . . . . . . . . . . . . . . . . . . . 506
12.3.2  Passive Optical Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
12.3.3  Optical Interconnections . . . . . . . . . . . . . . . . . . . . . . . . . . . 519
12.4  Optoelectronic Systems, Applications, and Markets. . . . . . . . . . . . 527
12.4.1  Optoelectronic Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
12.4.2  Applications of Optoelectronics. . . . . . . . . . . . . . . . . . . . . 534
12.4.3  Optoelectronics Markets . . . . . . . . . . . . . . . . . . . . . . . . . . . 538
12.5  Summary and Future Trends. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
12.6  Homework Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
12.7  Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
13 Fundamentals of MEMS and Sensor Packaging  Prof. Peter Hesketh,
Prof. Oliver Brand, and Prof. Klaus-Juergen Wolter. . . . . . . . . . . . . . . . . . . . . 547
13.1  What Are MEMS? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
13.1.1  Historical Evolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
13.2  Anatomy of a MEMS Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
13.2.1  Fundamentals of MEMS Packaging. . . . . . . . . . . . . . . . . . 552
13.2.2 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
13.3  MEMS and Sensor Device Fabrication Technologies. . . . . . . . . . . . 558
13.3.1  Photolithographic Pattern Transfer . . . . . . . . . . . . . . . . . . 558
13.3.2  Thin-Film Deposition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559

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13.3.3  Wet and Dry Etching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

13.3.4  Bulk and Surface Micromachining of Silicon . . . . . . . . . . 562
13.3.5  Wafer Bonding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
13.3.6  Laser Micromachining. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
13.3.7  Process Integration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
13.4  MEMS Packaging Technologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
13.4.1  MEMS Package Materials . . . . . . . . . . . . . . . . . . . . . . . . . . 568
13.4.2  MEMS Package Assembly Processes. . . . . . . . . . . . . . . . . 571
13.5  Application of MEMS and Sensors. . . . . . . . . . . . . . . . . . . . . . . . . . . 576
13.5.1  Pressure Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578
13.5.2  Accelerometers and Gyroscopes. . . . . . . . . . . . . . . . . . . . . 579
13.5.3  Projection Displays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582
13.6  Summary and Future Trends. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
13.7  Homework Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
13.8  Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
14 Fundamentals of Package Encapsulation, Molding, and Sealing 
Prof. C. P. Wong, Dr. Treliant Fang, and Dr. Pengli Zhu. . . . . . . . . . . . . . . . . 587
14.1  What Is Sealing and Encapsulation and Why?. . . . . . . . . . . . . . . . . 589
14.2  Anatomy of an Encapsulated and a Sealed Package. . . . . . . . . . . . 589
14.2.1  Fundamentals of Encapsulation and Sealing . . . . . . . . . . 589
14.2.2 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
14.3  Properties of Encapsulants. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
14.3.1  Mechanical Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
14.3.2  Thermal Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599
14.3.3  Physical Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
14.4  Encapsulation Materials. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
14.4.1  Epoxy and Related Materials. . . . . . . . . . . . . . . . . . . . . . . . 602
14.4.2  Cyanate Ester. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604
14.4.3 Urethanes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
14.4.4 Silicones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
14.5  Encapsulation Processes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
14.5.1 Molding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
14.5.2  Liquid Encapsulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
14.6  Hermetic Sealing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
14.6.1  Sealing Processes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
14.7  Summary and Future Trends. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
14.8  Homework Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
14.9  Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
15 Fundamentals of Printed Wiring Boards   Mr. Shinichi Iketani,
Dr. Sundar Kamath, Dr. Koushik Ramachandran,
and Prof. Rao R. Tummala . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
15.1  What Is a Printed Wiring Board?. . . . . . . . . . . . . . . . . . . . . . . . . . . . 623
15.2  Anatomy of a Printed Wiring Board. . . . . . . . . . . . . . . . . . . . . . . . . . 624
15.2.1  Fundamentals of Printed Wiring Boards. . . . . . . . . . . . . . 625
15.2.2  Types of PWBs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625

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15.2.3  PWB Material Grades. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627

15.2.4 Single- to Multi-Layer Boards and Their Applications . . . 627
15.2.5  PWB Design Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
15.2.6 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
15.3  Printed Wiring Board Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . 631
15.3.1  PWB Materials. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
15.3.2  PWB Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
15.3.3  PWB Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
15.4  Summary and Future Trends. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646
15.5  Homework Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648
15.6  Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649

16 Fundamentals of Board Assembly   Dr. Mulugeta Abtew,

Dr. Sundar Kamath, and Prof. Rao R. Tummala . . . . . . . . . . . . . . . . . . . . . . . . 651
16.1  What Is a Printed Circuit Board Assembly (PCBA) and Why?. . . . 653
16.2  Anatomy of Printed Circuit Board Assembly. . . . . . . . . . . . . . . . . . 654
16.2.1  Fundamentals of PCBA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
16.2.2 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
16.3  PCBA Technologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
16.3.1  PCB Substrate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
16.3.2  Package Substrates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
16.4  Types of Printed Circuit Board Assembly. . . . . . . . . . . . . . . . . . . . . 666
16.4.1  Plated Through Hole (PTH) Assembly . . . . . . . . . . . . . . . 666
16.4.2  Surface Mount Assembly (SMA). . . . . . . . . . . . . . . . . . . . . 667
16.5  Types of Assembly Soldering Processes. . . . . . . . . . . . . . . . . . . . . . . 668
16.5.1  Reflow Soldering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
16.5.2  Wave Soldering with PTH. . . . . . . . . . . . . . . . . . . . . . . . . . 682
16.6  Summary and Future Trends. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684
16.7  Homework Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
16.8  Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
16.9 Acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687

Part 2 Applications of Packaging Technologies

17 Applications of Packaging Technologies in Future Car Electronics 
Mr. Haksun Lee, Prof. Rao R. Tummala, and Prof. Klaus-Juergen Wolter . . . . 691
17.1  What Are Future Car Electronics and Why?. . . . . . . . . . . . . . . . . . . 693
17.2  Anatomy of a Future Car. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
17.2.1  Fundamentals of a Future Car. . . . . . . . . . . . . . . . . . . . . . . 695
17.2.2 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696
17.3  Future Car Electronic Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . 697
17.3.1  Computing and Communications . . . . . . . . . . . . . . . . . . . 697
17.3.2  Sensing Electronics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
17.3.3  High-Power Electronics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
17.4  Summary and Future Trends. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708

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 xiv Contents

17.5  Homework Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708

17.6  Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709

18 Applications of Packaging Technologies in Bioelectronics 

Prof. Markondeya Raj Pulugurtha, Dr. Melinda Varga, and
Prof. Rao R. Tummala. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
18.1  What Are Bioelectronics?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
18.1.1  Bioelectronics Applications. . . . . . . . . . . . . . . . . . . . . . . . . 713
18.1.2  Anatomy of a Bioelectronic System . . . . . . . . . . . . . . . . . . 715
18.2  Packaging Technologies for Bioelectronic Systems . . . . . . . . . . . . . 716
18.2.1  Biocompatible and Biostable Packaging . . . . . . . . . . . . . . 717
18.2.2  Heterogeneous Integration . . . . . . . . . . . . . . . . . . . . . . . . . 719
18.3  Examples of Bioelectronic Implants. . . . . . . . . . . . . . . . . . . . . . . . . . 720
18.3.1  Pacemakers and Electronic Stents. . . . . . . . . . . . . . . . . . . . 720
18.3.2  Cochlear Implants. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
18.3.3  Retinal Prosthetics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
18.3.4  Neuromuscular Stimulators . . . . . . . . . . . . . . . . . . . . . . . . 724
18.3.5  Brain Neural Recording and Stimulations . . . . . . . . . . . . 726
18.4  Summary and Future Trends. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
18.5  Homework Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
18.6  Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728

19 Applications of Packaging Technologies in Communication

Systems   Mr. Muhammad Ali, Prof. Markondeya Raj Pulugurtha,
and Prof. Rao R. Tummala . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
19.1  What Are Communication Systems and Why?. . . . . . . . . . . . . . . . . 731
19.2 Anatomy of Two Communication Systems:
Wired and Wireless. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
19.2.1  Anatomy of a Wired Communication System . . . . . . . . . 732
19.2.2  Anatomy of a Wireless Communication System . . . . . . . 732
19.3  Communication System Technologies. . . . . . . . . . . . . . . . . . . . . . . . 733
19.3.1  Historical Evolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
19.3.2  Communication System Technologies. . . . . . . . . . . . . . . . 735
19.3.3  Wireless Communication System Technologies. . . . . . . . 738
19.4  Summary and Future Trends. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
19.5  Homework Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
19.6  Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751

20 Applications of Packaging Technologies in Computing Systems 

Dr. Ravi Mahajan, Dr. Sandeep Sane, Dr. Kashyap Mohan, and
Prof. Rao R. Tummala. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
20.1  What Is Computer Packaging? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755
20.2  The Anatomy of a Computer Package. . . . . . . . . . . . . . . . . . . . . . . . 756
20.2.1  Fundamentals of Computer Packaging. . . . . . . . . . . . . . . 756
20.2.2  Types of Computing Systems . . . . . . . . . . . . . . . . . . . . . . . 757
20.2.3 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758

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 Contents xv

20.3  Computer Packaging Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . 759

20.3.1 Evolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
20.3.2  Interconnection Technologies . . . . . . . . . . . . . . . . . . . . . . . 759
20.3.3  Interconnection Designs for Signal and Power. . . . . . . . . 760
20.4  Thermal Technologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
20.4.1  Thermal Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762
20.4.2  Thermo-Mechanical Reliability. . . . . . . . . . . . . . . . . . . . . . 763
20.4.3  Material Technologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
20.5  Summary and Future Trends. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
20.5.1  Beginning of Moore’s Law for Packaging. . . . . . . . . . . . . 766
20.5.2  Moore’s Law for Packaging: Cost. . . . . . . . . . . . . . . . . . . . 767
20.6  Homework Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768
20.7  Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768
20.8 Acknowledgments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768

21 Applications of Packaging Technologies in Flexible Electronics 

Mr. Siddharth Ravichandran, Prof. Markondeya Raj Pulugurtha,
Dr. Vanessa Smet, and Prof. Rao R. Tummala. . . . . . . . . . . . . . . . . . . . . . . . . . 769
21.1  What Are Flexible Electronics and Why?. . . . . . . . . . . . . . . . . . . . . . 771
21.1.1 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771
21.2  Anatomy of a Flexible Electronic System. . . . . . . . . . . . . . . . . . . . . . 773
21.2.1  Fundamentals of Flexible Electronics Technologies. . . . . 774
21.2.2 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774
21.3  Flexible Electronics Technologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . 776
21.3.1  Component Technologies. . . . . . . . . . . . . . . . . . . . . . . . . . . 776
21.3.2  Process Integration of Flexible Electronics
   Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
21.3.3  Component Assembly on Flexible Substrates. . . . . . . . . . 787
21.4  Summary and Future Trends. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791
21.5  Homework Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792
21.6  Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792

22 Applications of Packaging Technologies in Smartphones 

Mr. Siddharth Ravichandran and Prof. Rao R. Tummala . . . . . . . . . . . . . . . . . 793
22.1  What Are Smartphones?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795
22.1.1  Why Smartphones?. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795
22.1.2  Historical Evolution of Smartphones . . . . . . . . . . . . . . . . 796
22.2  Anatomy of a Smartphone. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796
22.2.1  Fundamentals of Smartphones. . . . . . . . . . . . . . . . . . . . . . 797
22.2.2 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
22.3  Smartphone Packaging Technologies. . . . . . . . . . . . . . . . . . . . . . . . . 799
22.3.1  Application Processor Packaging. . . . . . . . . . . . . . . . . . . . 799
22.3.2  Memory Packaging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800
22.3.3  RF Packaging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801
22.3.4  Power Packaging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
22.3.5  MEMS and Sensors Packaging . . . . . . . . . . . . . . . . . . . . . . 804

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 xvi Contents

22.4  Systems Packaging in Smartphones. . . . . . . . . . . . . . . . . . . . . . . . . . 804

22.5  Summary and Future Trends. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806
22.6  Homework Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806
22.7  Suggested Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
Index  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809

00_Tummala_FM_i-xx.indd 16 26/06/19 12:08 pm

 Contributors
Mulugeta Abtew  Sanmina Corporation, USA (Chap. 16)
Muhammad Ali  Georgia Institute of Technology, USA (Chap. 19)
Swapan Bhattacharaya  Engent Inc., USA (Chap. 7)
Oliver Brand  Georgia Institute of Technology, USA (Chap. 13)
Justin Broughton  Georgia Institute of Technology, USA (Chap. 3)
Parthasarathi Chakraborti  Intel Corporation, USA (Chap. 7)
Gee Kung Chang  Georgia Institute of Technology, USA (Chap. 12)
Bruce C. Chou  Rockley Photonics, USA (Chap. 12)
Rabindra Das  Massachusetts Institute of Technology, USA (Chap. 5)
Bartlet H. DeProspo  Georgia Institute of Technology, USA (Chaps. 6, 10)
Treliant Fang  Motorola, USA (Chap. 14)
Mukta Farooq  GlobalFoundries, USA (Chap. 10)
Saumya Gandhi  Texas Instruments, USA (Chap. 7)
Daniel Guidotti  Georgia Institute of Technology, USA (Chap. 12)
Omkar Gupte  Georgia Institute of Technology, USA (Chap. 10)
Peter Hesketh  Georgia Institute of Technology, USA (Chap. 13)
Shinichi Iketani  Sanmina Corporation, USA (Chap. 15)
Subramanian S. Iyer  University of California, Los Angeles, USA (Chap. 10)
Yogendra Joshi  Georgia Institute of Technology, USA (Chap. 3)
Dong Gun Kam  Ajou University, Korea (Chap. 2)
Sundar Kamath  Sanmina Corporation, USA (Chaps. 15, 16)
Beth Keser  Intel Corporation, USA (Chap. 9)
Joungho Kim  Korea Advanced Institute of Science and Technology (KAIST) (Chap. 2)
Haksun Lee  Georgia Institute of Technology, USA (Chap. 17)
Fuhan Liu  Georgia Institute of Technology, USA (Chap. 6)
Ravi Mahajan  Intel Corporation, USA (Chap. 20)
Junki Min  Georgia Institute of Technology, USA (Chap. 11)

xvii

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 xviii Contributors

Dibyajat Mishra  Texas Instruments, USA (Chap. 7)

Kashyap Mohan  Georgia Institute of Technology, USA (Chap. 20)
Chandra Nair  Georgia Institute of Technology, USA (Chap. 6)
Nithin Nedumthakady  Georgia Institute of Technology, USA (Chap. 10)
John H. L. Pang  Nanyang Technological University, Singapore (Chap. 4)
John Papapolymerou  Michigan State University, USA (Chap. 11)
Eric Perfecto  GlobalFoundries, USA (Chap. 8)
Andrew F. Peterson  Georgia Institute of Technology, USA (Chap. 2)
John Prymak  KEMET, USA (Chap. 7)
Markondeya Raj Pulugurtha  Florida International University, USA (Chaps. 5, 6, 7, 11,
18, 19, 21)
Koushik Ramachandran  GlobalFoundries, USA (Chap. 15)
Siddharth Ravichandran  Georgia Institute of Technology, USA (Chaps. 10, 21, 22)
Sandeep Sane  Intel Corporation, USA (Chap. 20)
Ninad Shahane  Texas Instruments, USA (Chap. 8)
Himani Sharma  Georgia Institute of Technology, USA (Chap. 5)
Tailong Shi  Georgia Institute of Technology, USA (Chap. 9)
Kamal Sikka  IBM Corporation, USA (Chap. 3)
Srikrishna Sitaraman  TE Connectivity, USA (Chap. 11)
Suresh K. Sitaraman  Georgia Institute of Technology, USA (Chap. 4)
Vanessa Smet  Georgia Institute of Technology, USA (Chaps. 8, 21)
Eakhwan Song  Kwangwoon University, Korea (Chap. 2)
Vijay Sukumaran  FormFactor Inc., USA (Chap. 6)
Venky Sundaram  Georgia Institute of Technology, USA (Chap. 6)
Madhavan Swaminathan  Georgia Institute of Technology, USA (Chap. 2)
Emmanouil M. Tentzeris  Georgia Institute of Technology, USA (Chap. 11)
Rao R. Tummala  Georgia Institute of Technology, USA (Chaps. 1, 9, 10, 11, 15, 16, 17, 18,
19, 20, 21, 22)
Krishna Tunga  IBM Corporation, USA (Chap. 4)
Melinda Varga  Georgia Institute of Technology, USA (Chap. 18)
Klaus-Juergen Wolter  Technische Universität Dresden, Germany (Chaps. 13, 17)
C. P. Wong  Georgia Institute of Technology, USA (Chaps. 5, 14)
Rui Zhang  Georgia Institute of Technology, USA (Chap. 12)
Pengli Zhu  Shenzhen Institutes of Advanced Technology, Chinese Academy of Sciences
(Chap. 14)

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 Preface

E
lectronic packaging means primarily interconnecting active and passive
components to form modules initially and systems finally. While powering,
cooling, and protecting are important functions of any package, they are
secondary. Design, materials, and processes as well as test are assumed to be part of
interconnections. The end goal of packaging is to form systems by interconnecting all
the miniaturized components with and without transistors. These systems can be
consumer products like smartphones, self-driving electric cars, cloud computers, PCs,
laptops, notebooks, and watches. All these systems currently have two parts: devices
with transistors and components without transistors. Combined, these two span 15
different technologies, as described in this book.
This book is about both device and systems packaging. The market for these
technologies is in excess of $500 billion worldwide, employing millions of people. Yet,
device and systems packaging is not considered an academic subject, except at Georgia
Tech. A typical academic subject such as microelectronics or VLSI has extensive courses,
curricula, educational tracks, fundamental books, software tools, and hands-on
facilities. Most of these don’t exist in packaging. The number of universities offering
research programs with one or more courses, however, has increased rapidly in recent
years. In the United States, there were only two universities offering any packaging
research or education in the 1980s: Cornell and Stanford. It is estimated that this number
in the United States, Europe, and the Far East is about 200 now, having grown from less
than 10 universities in 1990 and 50 or so in 2000.
Fundamentals of Device and Systems Packaging is written to meet the academic need to
educate undergraduate and graduate students in the fundamentals as well as all 15
technologies necessary to form systems. While there have been many books since my
first modern book in 1988, Microelectronics Packaging Handbook, most, if not all, are
considered reference books. They typically deal with one or more topics in a review
fashion. However, electronic systems, as described in this book, require 15 different
device and systems packaging technologies. The topics span IC packaging and assembly,
system board packaging and assembly, and all the variations in between. It also deals
with electrical design, thermo-mechanical design, thermal design and technologies,
materials, processes, properties, reliability, and so on. This was the case 10–20 years ago
when I wrote the first book. Today’s systems are more than microelectronics. They are
RF, optical, MEMS and sensors, power, etc.
This book is more than interconnecting. It includes microelectronics, photonics, RF
and millimeter wave, and MEMS and sensors. All these devices along with other

xix

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 xx Preface

components need to be packaged to form systems. This is exactly what this book is all
about. It deals with all these technologies at the fundamental level—defining each,
illustrating the key concepts behind each, and introducing the critical nomenclature in
a systematic fashion. Each topical chapter includes fundamental equations, homework
problems, and future trends.
The book introduces Moore’s Law for packaging as Moore’s Law for cramming
transistors to form large ICs begins to come to an end. It proposes the cramming of
small ICs to form large homogeneous and heterogeneous packages. In contrast to
Moore’s Law for large ICs, with the highest number of transistors compromising
performance and cost, from node to node, Moore’s Law for packaging can be thought
of as interconnecting the smallest transistors in smaller ICs with the highest performance
and lowest cost in 2D, 2.5D, and 3D package architectures with an equal or higher
aggregate number of transistors.
I am grateful to all of the 55 global authors from industry and academia. This book,
just like the first edition, is written by so many authors and yet reads as if written by
one. I am thankful to Karen May, who headed the book project from start to finish, and
to Prof. Raj Pulugurtha, who moved from Georgia Tech to Florida International
University during the course of preparing this book. They have put in endless hours,
coordinating with all of the 55 authors from around the world.
I am also grateful to Senior Editors Michael McCabe and Lara Zoble and the other
editors at McGraw-Hill, who facilitated printing the book in two colors and at a very
affordable low cost for such a book that goes from wafers to systems with all the
electronic technologies and applications. I thank my wife, Anne, for her patience,
understanding, and full support during the course of the book, as I worked every day
and every weekend over 3 years, on top of my normal responsibilities of being a Professor
and the Director of the Microsystems Packaging Research Center at Georgia Tech.
My final thanks are, again, to all the authors who contributed to the book, working
nights and weekends, adding to their normal job responsibilities.

Prof. Rao R. Tummala

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 CHAPTER 1
Introduction to
Device and Systems
Packaging Technologies
Prof. Rao R. Tummala
Georgia Institute of Technology, USA

RF Power MEMS &

3D ICs Modules Modules Sensor Photonic
Modules Modules
Moore’s Law
High for Systems Ultra-thin
Substrate
Thru
Vias

3D IPD Thermal Power

HMC Passives Structures
System Integration

3D System Package
MEMS
DNA
Med Moore’s Law Image
BGA Package RF
for Packaging Processor
Memory
2.5D 3D
Optical MEMS Direct
Signal Programmable
Logic
I/O Processing
Moore’s Law for ICs SOC
Low Analog Memory
DRAM
Micro-
processor
CMOS-
RF

1960 1970 1980 1990 2000 2010 2020 2030

Year

01_Tummala_CH01_p001-040.indd 1 26/06/19 1:30 pm



Chapter Outline
1.1.
What Is Packaging and Why?
1.1.1  What Is Packaging?
1.1.2  Why Is Packaging Important?
1.1.3  Every IC and Device Has to Be Packaged
1.1.4  Controls Performance of Computers
1.1.5  Controls Size of Consumer Electronics
1.1.6  Controls Reliability of Electronics
1.1.7  Controls Cost of Electronic Products
1.1.8  Required in Nearly Everything
1.2 Anatomy of an Electronic Packaged System from a Packaging Point of View
1.2.1  Fundamentals of Packaging
1.2.2 Systems Packaging Involves Electrical, Mechanical,
and Materials Technologies
1.2.3 Nomenclature
1.3 Devices and Moore’s Law
1.3.1  On-Chip Interconnections
1.3.2  Interconnect Materials
1.3.3 The Resistance and Capacitance Delays (RC Delays)
of On-Chip Interconnects
1.3.4  Future of Device Scaling
1.4 Electronic Technology Waves: Microelectronics, RF/Wireless,
Photonics, MEMS, and Quantum Devices
1.4.1  Microelectronics: The First Technology Wave
1.4.2  RF and Wireless: The Second Technology Wave
1.4.3  Photonics: The Third Technology Wave
1.4.4 Micro-Electro-Mechanical Systems (MEMS):
The Fourth Technology Wave
1.4.5  Quantum Devices and Computing: Fifth Wave
1.5 Packaging and Moore’s Law for Packaging
1.5.1  Three Eras in Packaging
1.5.2  Moore’s Law or SOC Era (1960–2010)
1.5.3  Moore’s Law for Packaging Era from 2010 to 2025
1.5.4  Moore’s Law for Systems Era from 2025
1.6 Electronic Systems Technologies Trends
1.6.1  Core Packaging Technologies
1.6.2  Packaging Technologies and Their Trends
1.7 Future Outlook
1.7.1  Emerging Computing Systems
1.7.2  Emerging 3D Systems Packaging
1.8 How the Book Is Organized
1.9 Homework Problems
1.10 Suggested Reading

Chapter Objectives
• Define packaging and describe its functions
• Introduce a three-level packaging to form systems
• Define and describe devices and their evolution
• Describe the evolution of packaging technologies during and post–Moore’s Law
• Introduce the concept of Moore’s Law for packaging
2

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 Chapter 1: Introduction to Device and Systems Packaging Technologies 3

1.1  What Is Packaging and Why?

Imagine a world without smartphones. They are able to integrate computing, commu-
nications, cameras, and a variety of sensing technologies and many others into one
small product that fits in ones’ pocket, and almost every person can afford one. Today
we use them hourly to communicate, to watch movies, to talk, to bank, to get instant
answers to almost any question instantly, to monitor health, and many, many, more
functions. The other three discoveries that changed the world forever are the first dis-
covery of electricity that can be traced to Ben Franklin in 1752, the invention of the tran-
sistor in 1949 at Bell Labs, and the first digital computer by IBM in 1963. Each of these
sets the stage for the next discovery, such as a smartphone by Apple in 2007.
Now imagine what is coming.
Electronic machines that think and act like humans are way behind humans, but
humans are prone to emotions, judgements, and errors. For example, there are 30,000
deaths a year in the U.S. alone, 220,000 in China, and 1.3 M worldwide—all attributable
to human error. The key is to develop electronic machines that think, communicate,
and act better than humans. This is the basis of artificial intelligence, deep learning, and
virtual and augmented reality. The other important emerging strategic technologies are:
6G and beyond, self-driving electric cars, the Internet of Things (IOT) and many others,
such as bioelectronics and drones. The technologies behind all the electronic products
in computer, consumer, automotive, communications, aerospace, and medical indus-
tries are based on micro- and nanoscale devices, components, and interconnections,
and the assembly of all these to form a three-level hierarchy to form systems, as shown
in Figure 1.1. This figure conveys how ICs with as much as 5 billion transistors in 2015
and 50 billion around 2025 at I/O (input/output) pitch of 2–5 microns get intercon-
nected to package substrates at 80 microns I/O pitch, which are then interconnected at
400 microns I/O pitch to the system board. This figure also conveys two other impor-
tant points about integration and interconnections.

Transistor On-Chip
Level Integration
IC 1 IC 2
2 µm SOC
Package 80µm On-Package
Level 80 µm Integration
400µm SOP

Board RF
Level Digital Optical On-Board
400 µm PWB Integration
MEMS SOB
Sensors
Power

Total Interconnection Length at Systems

Level between All Components
Figure 1.1  A three-level packaging hierarchy currently in use at IC, package, and board levels
to form electronic systems, interconnecting all components at board level with extremely long
interconnect length.

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 4 Chapter 1: Introduction to Device and Systems Packaging Technologies

System integration can take place at one or more of the three levels, as shown in
Figure 1.1.

1. At IC level to system-on-chip (SOC)

2. At package level to system-on-package (SOP)
3. At board level to system-on-board (SOB)

The current approach to end-product systems starts with on-chip transistor inte-
gration but ends up interconnecting mostly through system board level to SOB, as
described below:

1. The devices such as IC1 and IC2, which are individually-packaged on package
substrate 1 and substrate 2, are interconnected through the board, making chip-
to-chip interconnections very, very long.
2.
System integration, which includes active ICs with transistors and passive
components without transistors, can be integrated at IC level to SOC, package
level to SOP, or system level to SOB. Figure 1.1 illustrates the process of forming
these three-level systems. It starts with system design, and then wafer
fabrication processes using 750 mm thick, 300 mm diameter wafers. It contains
hundreds of ICs, which are diced from this wafer. These individual diced ICs
are then packaged either by wirebond, flip-chip, or tape-automated bonding
assembly technologies onto either ceramic, leadframe, organic laminate, silicon
or glass package substrates. These and other components such as capacitors (C)
or inductors (L) are assembled onto boards to form systems like smartphones.

Figures 1.2 and 1.3 show the technologies involved and their manufacturing flow
to form systems. As can be seen from Figure 1.2, there are two major parts to packaging
a system:

1. Device packaging either as individual packages or as multi-chip packages in

2D, 2.5D, or 3D
2.
Systems packaging of all the components required to form the entire system

1.1.1  What Is Packaging?

This book is about packaging. As shown in Figure 1.4, packaging is defined as inter-
connecting, powering, cooling, and protecting devices during the Moore’s Law era
from the 1960s. The role of packaging has been changing, however, with the changes in

Design IC Packaging Systems Packaging

Wafer Substrate IC Assy PWB PWB Assy System

Assembly

Figure 1.2  Packaging starts with design, then device and packaging, and ends up with a system
like a smartphone.

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 Chapter 1: Introduction to Device and Systems Packaging Technologies 5

Applications

Software

Algorithms

Boards

Architectures

Circuits

Package Components

Package Substrates

Devices

Structures

Materials

Figure 1.3  System includes many technologies, starting with materials and structures to form
devices at device level; package substrates and passive components to form functional circuits
and architectures; system components on boards; and software at the system level.

Interconnect Power

IC Interconnections IC

Package or Board

Power Planes
Power Power Signal

Protect Cool

Figure 1.4  Definition of packaging: interconnecting, powering, cooling, and protecting all system
components.

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 6 Chapter 1: Introduction to Device and Systems Packaging Technologies

Interdisciplinarity of Electronics Systems

Electrical Sciences Mechanical Sciences
• Signal Integrity • Thermomechanical
• Power Integrity IC Signals IC Reliability
• EMI • Fatigue and Creep
• Warpage
• Heat Transfer

Package or Board
Material Sciences Chemical Sciences
• Dielectrics • Lithographic Processes
• Conductors Power Planes • Microstructure vs.
• Magnetics Power Power Signal Properties
• Encapsulants
• C, L, R, Materials
Bioelectronics
• Biocompatible
• Components
• Interconnections

Figure 1.5  Interdisciplinarity of packaging: electrical, mechanical, thermal, materials, bioelectronic,

and chemical processes.

device and device integration technologies as well as with the changes in end-product
systems, such as a smartphone. The end goal of packaging is a final heterogeneous sys-
tem such as a smartphone with all the system components interconnected. A better defi-
nition of packaging, therefore, is interconnecting, powering, cooling, and protecting all
the system components that make up that entire system. Figure 1.4 defines packaging
this way, and Figure 1.5 shows the interdisciplinarity of packaging, requiring electrical,
mechanical, thermal, materials, chemical, and bioengineering disciplines.

• Electrical: For signal and power.

• Mechanical: For heat transfer and for thermo-mechanical reliability.
• Materials: For many functions with many types of materials such as dielectrics,
conductors, capacitors, inductors, solder joints, encapsulants, thermal materials,
and others.
• Chemical: For processing of materials to form functional materials such as
dielectrics, capacitors, inductors, and encapsulants, as well as for photolitho­
graphy to form wiring layers.
• Bioelectronics: For medical devices, such as hearing implants, electronic retinas
for vision, and many others.

1.1.2  Why Is Packaging Important?

IC is not an electronic system, and no system is complete without interconnecting, pow-
ering, cooling, and protecting all system components. The importance of packaging,
however, differs from one type of system to another. The following is a summary of the
importance of packaging.

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 Chapter 1: Introduction to Device and Systems Packaging Technologies 7

1.1.3  Every IC and Device Has to Be Packaged

There are currently >100 billion ICs and devices that are manufactured worldwide, and
all of these have to be packaged at the IC-level to form IC packages, and at system-level
to form system boards. Packaging at both levels is often considered the biggest bottle-
neck, because it controls the system’s electrical performance, cost, size, and reliability.

1.1.4  Controls Performance of Computers

The number of ICs and their interconnections required to form a processor or cen-
tral processing unit (CPU) determines the cycle-determining path from IC through the
package interconnections, and thus controls the speed or clock frequency of the CPU.

1.1.5  Controls Size of Consumer Electronics

The number and size of ICs in a given system, such as a smartphone, tend to be small.
However, the total number of components in the smartphone is more than 100. The bat-
tery and other components occupy most of the space. Space is thus controlled not by
devices but by packaging.

1.1.6  Controls Reliability of Electronics

Solid-state devices such as ICs are extremely reliable, with failure rates in parts-per-
million (ppm). Since the majority of interconnections in a system are within packag-
ing at IC package and system board levels, the failure rate tends to be more highly
attributed to the interconnections or packaging of the devices rather than to the devices
themselves.

1.1.7  Controls Cost of Electronic Products

The cost of producing today’s ICs and micro-electro-mechanical systems (MEMS)
devices is low due to a variety of factors such as large-scale and high- throughput
wafer starts-per-day and automation. The approximate IC fabrication cost, excluding
design cost, is about $4/cm2 at mature production levels. On the other hand, system-
level packaging cost, with all the components to form system-level boards including
assembly and test, is much higher.

1.1.8  Required in Nearly Everything

Electronics are now a part of nearly all industries such as automotive, telecommuni-
cation, computer, consumer, medical, aerospace, and military. All electronics require
packaging.

1.2 Anatomy of an Electronic Packaged System

from a Packaging Point of View
Figure 1.6 shows a three-level hierarchy in forming any electronic system. As shown in
this figure, devices are fabricated with transistors on large and round 300-mm silicon
wafers to form front-end of line (FEOL) with transistors and back-end of line (BEOL)
interconnections by so-called redistribution layers (RDL). A typical leading-edge logic
IC ends up with I/O bumps at about 80 microns pitch in 2018. Such a chip from wafer

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 8 Chapter 1: Introduction to Device and Systems Packaging Technologies

Packaging @ Device
Device 1 Device 2 Level - 2µm BEOL

RDL Packaging
Package Package @ Substrate Level
Substrate 1 Substrate 2
RDL Packaging
@ Board Level

System Board

Figure 1.6  Anatomy of a packaged electronic system with three levels.

fabs is then assembled by so-called flip-chip assembly on to the surfaces of package

substrates with its own I/O bumps at 80 microns pitch. These package substrates are
made up of polymer-based laminates, ceramic, silicon, or glass. The final assembly
to form a system involves assembling these and many, many other packaged active
devices and passive components on a system board to form the entire system. Such a
system assembly is performed by so called surface-mount technology (SMT) at about
400 microns pitch in 2018.

1.2.1  Fundamentals of Packaging

Electronic systems packaging involves two major functions: one at the IC or device
level, and the other at the system board level, as shown in Figure 1.7(a) and (b). At
the IC level, it involves interconnecting, powering, cooling, and protecting ICs. At this
level, typically referred to as Level 1, the packaging acts as an IC “carrier.” The IC

IC Packaging System Packaging

Removal of Heat

Encapsulation

IC1 IC2
Signals IC
L C B QFP L C B

PWB, Flex
IC Package

Power Power Signal

(a) (b)
Figure 1.7  (a) Device packaging, and (b) Systems packaging.

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 Chapter 1: Introduction to Device and Systems Packaging Technologies 9

carrier is also called Packaged-IC. It allows ICs to be shipped “certified or qualified” by

IC manufacturers after “burn-in” and an electrical test to be “ready” for assembly onto
a system board by end-product or contract manufacturers.
Packaging a single IC does not generally lead to a complete system, since a
typical system requires a vast number of different active devices and passive compo-
nents. System-level packaging involves interconnection of all these components to
be assembled onto the system board, regardless of the type of component being
assembled. The system-board, also called “motherboard,” not only carries all these
components on top and below, but also interconnects every one of these components
with conductor wiring so as to form one interconnected system. This system-level is
typically referred to as Level 2 in the packaging hierarchy.
In forming an electrically wired system boards with assembled components, there
are two additional interconnections that need to be made. First, interconnection
must occur at the IC level where the input/output (I/O) pads on the IC are con-
nected to the first level of the packaging. This is typically done by wire-bonding the
components to a substrate such as a leadframe or a ceramic that has been fabricated
to a specific shape in order to make it ready for interconnection to the next level of
packaging. This is referred to as IC assembly. The second interconnection is typically
achieved by means of solder bonding between the substrate of the first-level package
and electrically conductive pads on the second-level package, which is typically a “card”
or “board.” This is referred to as board assembly. The system board, with components
assembled on either or both sides, typically completes the system.
There are products, such as mainframes and supercomputers, that require a very
large number of ICs. By today’s standards, a single system board may not carry all
the components necessary to form that total system, since some of these require
several processors to provide the extremely high transactional throughput. These types
of systems might be used to manage large amounts of data such as an airline reserva-
tion system or a corporate mainframe network, or to process high-resolution imagery,
such as with certain types of medical equipment. In this case, connectors and cables
typically connect the system boards.

1.2.2 Systems Packaging Involves Electrical, Mechanical,

and Materials Technologies
It should be recognized that in this three-level hierarchy, a transistor on an IC might
communicate by means of an electrical or optical signal to another IC. This signal com-
munication poses a whole set of electrical, mechanical, thermal, chemical, and environ-
mental challenges which, if not properly engineered and manufactured, may result in
either poor communication or no communication at all.

Electrical Packaging Technology

Electrical problems relate to both signal propagation between the transistors and to the
power distribution required to operate these transistors. The electrical parameters such
as resistance, capacitance, and inductance are always present and cause signal delays
and signal distortions. Signal degradation is another problem that is due primarily to
line resistance. Line resistance causes voltage drops, thus increasing transition time.
The power distribution problems stem from simultaneous switching of all the driving
transistors in a given circuit, resulting in drawing a huge amount of current. This is
referred to as “switching noise.”

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 10 Chapter 1: Introduction to Device and Systems Packaging Technologies

Since an electronic system involves more than one IC, effective communication
between one transistor on one IC and another transistor on another IC, all the way
through the system-level board with the required signal quality, is required. Signal
communication, however, does not start until an appropriate power is supplied to each
and every transistor. Such power distribution, however, poses a whole set of challenges
that include voltage drop as a result of long and high-resistive wiring from the power
supply to the transistor through all the levels of packaging. Simultaneous switching off
millions of transistors poses yet another challenge, in that the current drawn from the
power supply results in what is referred to as delta-I noise. Signal distribution poses a
different set of problems such as “cross-talk” between lines, as well as distortion, reflec-
tion, and alternation of signals. Electromagnetic radiation, as a result of all this radiated
energy, is yet another electrical challenge.

Materials Packaging Technology

The signal and power distribution requires appropriate use of materials to form the
system packaging hierarchy. Power distribution, for example, requires metals of high-
est electrical conductivity for least voltage drop. Heat transfer requires materials of
highest thermal conductivity. The need for minimized delta-I noise requires low-
inductance and high-capacitance power distribution. High-performance computers
require high-speed signal propagation, which requires the use of lowest dielectric con-
stant dielectrics in which to embed the best electrical conductors. Materials are also
required to join ICs to packages to form IC packages, as well as to join materials to
form precise electrical structures with the required impedance, capacitance, resistance,
and inductance.

Mechanical Packaging Technology

The combination of power distribution through all levels of system packaging, and
the use and fabrication of materials with the above diversity of properties, invariably
leads to the development of thermomechanical stresses at every interface. These
stresses, which develop not only during fabrication of IC and system packages, but
also during the shipment of product in hot and cold climates and during actual product
usage, could lead to electrical failure of interconnections. Effective heat transfer, so as
to keep the IC and the system packaging “cool,” is one way to address this challenge.
The mechanical problems typically relate to reliability of the packaging structure
that provides the electrical function. This occurs particularly at solder-to-chip interface
and package-to-board interface during processing and fabrication of the IC packages
and system boards. It also occurs during electrical operation of final electronic products.
In both cases, stresses are developed due to the combined effect of mismatch in thermal
expansion coefficients between various interfaces and temperature cycles.

1.2.3  Nomenclature
3D  Bare ICs that are stacked one on top of the other and interconnected on one substrate,
in contrast to packaged dies that are stacked in POP.
Embedding  Embedding typically means embedded active die inside a substrate in contrast
to assembled die on top of the substrate.
Interconnect  Interconnect is the length of wiring or joints between two active or passive
components.

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 Chapter 1: Introduction to Device and Systems Packaging Technologies 11
Moore’s Law  Moore’s Law is an empirical law observed by Gordon Moore in 1968 with two
components: doubling of transistors and halving of cost every two or so years.
Multi-chip module (MCM)  Two or more chips interconnected on a single carrier. Together
with the board, it forms a system.
Package-on-package (POP)  POP that is interconnected on one substrate.
Printed wiring board (PWB)  A PWB interconnects all the components to form a final system.
Quantum computing  A quantum computer is a device that performs quantum computing.
Quantum computing is expected to transform almost every aspect of human life with science,
technology, and economy behind it. Quantum computers are very different from binary
digital electronic computers based on transistors. Whereas common digital computing
requires that the data be encoded into binary digits (bits), each of which is always in one
of two definite states (0 or 1), quantum computation uses quantum bits, which can be in
superpositions of states.
System-in-a-package (SIP)  Two or more ICs stacked and wire-bonded with or without
passives. Requires systems board. SIP can also be a functional package.
System-on-board (SOB) 2.5D  Second Generation MCM fabricated with thin film film
technology in contrast to first generation with thick film technology.
System-on-chip (SOC)  Highly integrated and mixed signal IC. Partial system functions in
one device.
System-on-package (SOP)  A micro or nano-miniaturized single-package system with two or
more RF, power, digital, optical, and bio functions. Best of on-chip and package integration
for cost, performance, size, and reliability.

1.3  Devices and Moore’s Law

Devices are the brains behind all electronics. Moore’s Law has been the driving force
behind these devices.
Moore’s Law has two parts: 1) Increased number of transistors by scaling, and 2)
simultaneous cost reduction as the transistor scales to the next node.
Moore’s Law is an empirical law that predicted that the number of transistors will
double every 18–24 months. As shown in Figure 1.8, this has proven to be an excellent
predictor of the number of transistors on a single chip from one node to the next. It is
about the continuous size decrease of a transistor. There is a so-called Dennard scaling
theory that predicted electrical performance would increase as the size of the transistor
is decreased. The first paper was published predicting the end of Moore’s Law around
1980. But Moore’s Law continued for decades.
Since Moore’s Law has two parts, transistors and cost, many companies claim
Moore’s Law is no longer valid because cost has stopped to come down, starting around
14-nm node. This concept is shown in Figure 1.9.
The other part of Moore’s Law continues, however, toward a 50B transistor IC
around 2022, with nodes from 7 to 5 to 3 nm. There are two reasons for the eventual in
validity of Moore’s Law—leakage due to tunneling current at higher electric fields and
lower perfoormance. New generations of other devices such as FinFETs and FD SOIs
are being counted upon in the short term.

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 12 Chapter 1: Introduction to Device and Systems Packaging Technologies

?
1.E+10

1.E+09

1.E+08
Number of Transistors

1.E+07

1.E+06
~
2x/2 yrs.

1.E+05

1.E+04

1.E+03
1970 1980 1990 2000 2010 2020
Year of Introduction
Figure 1.8  Moore’s Law for doubling of transistors about every two years.

Node N-1
Node N
Node N+1
Cost

1
2
3

Past Future
Figure 1.9  Moore’s Law for cost reduction from node to node.

1.3.1  On-Chip Interconnections

It’s well known that the most advanced chips contain more than 5 billion transistors in
2017 and are expected to grow to 50 billion by 2025. This is an incredible, mind-blowing
fact to be sure—but do we know that large-scale integrated chips (about the size of a

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 Chapter 1: Introduction to Device and Systems Packaging Technologies 13

fingernail) can contain ~30 miles of interconnect “wires” in stacked levels? These wires
function like highways or pipelines to transport electrons, connect transistors and other
components to each other, and make them functional. And just as the speed we can
drive our sport cars depends (at least in part) on how clogged the freeway is, chip per-
formance depends on the ability to move signals and power through these ultra-tiny
wires. In fact, as the shrinking of feature dimensions, called scaling, has continued,
interconnects are now becoming the speed bottleneck in today’s most advanced chips.
During the first portion of chip-making in the front-end-of-line, the individual
components such as transistors or capacitors are fabricated on the wafer. In the back-
end-of-line, these components are connected to each other to distribute signals, as well
as power and ground. There is simply no room on the chip surface to create all those
connections in a single layer, so chip manufacturers build vertical levels of intercon-
nects. While simpler ICs may have just a few metal layers, complex ICs can have 10 or
more layers of wiring, as shown in Figure 1.10.
Interconnects close to the transistors need to be small, as they attach to the com-
ponents that are themselves very small and often closely packed together, as shown
in Figure 1.10. These lower-level wiring lines—called local interconnects—are usually
thin and short in length. Global interconnects are higher up in the structure; they travel
between different blocks of the circuit and are thus typically thick, long, and widely
separated with lower resistance. Vertical connections between interconnect levels,
called vias, allow signals and power to be transmitted from one layer to the next.

1.3.2  Interconnect Materials

For decades, aluminum interconnects were the industry standard. To create these inter-
connects, a layer of aluminum is deposited. Then, the metal is patterned and etched,
and insulating material is deposited to separate the conducting lines. In the late 1990s,
chipmakers switched to copper, which conducts electricity better than aluminum.
Higher-conductivity wiring lines improve overall IC performance. In addition,
copper lines could be made smaller, keeping pace with transistor-size scaling. Copper
wiring is also more durable and reliable. However, creating copper interconnects is

Metal Line

Via Global
Interconnects

Local
Interconnects

Transistors

Figure 1.10  On-chip interconnections: local and global. (Courtesy of Larry Zhao.)

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 14 Chapter 1: Introduction to Device and Systems Packaging Technologies

Aluminum Interconnect

Aluminum

Aluminum Etch Dielectric Gapfill

Copper Interconnect

Dielectric

Dielectric Etch Copper Fill Excess Copper

Removal
Figure 1.11  On-chip interconnection wiring fabrication.

much more complex, and a whole new manufacturing scheme has to be developed
for this new technology inflection, as shown in Figure 1.11. The copper interconnect
process starts with deposition of an insulating dielectric material, for example silicon
dioxide, followed by the creation of trenches. The trenches are then filled with copper
using chemical/electroplating technologies, and the excess is removed to form flat
surfaces for subsequent processing.

1.3.3 The Resistance and Capacitance Delays (RC Delays)

of On-Chip Interconnects
Over the years, transistor sizes have decreased dramatically. As transistors have gotten
smaller and smaller, interconnects also have had to scale in size. Today, conventional
copper interconnects are facing a significant roadblock to further scaling, and that
roadblock is known as the RC challenge, as described and illustrated in Figures 1.11
and 1.12.

Higher Resistance with Smaller Line Width

Core (Copper)
Line Width
Resistance (arb)
Copper Line

Core (Copper)
Line Width
Copper

0 10 20 30 40 50 60 Dielectric
Line Width (nm)
Figure 1.12  Resistance of on-chip copper wiring as a function of line width.

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 Chapter 1: Introduction to Device and Systems Packaging Technologies 15

The electrical resistance (R) of a material describes how difficult it is to move elec-
trical current through a particular cross-section of that material, which is a function
of the orientation and proximity of the material’s atoms. Capacitance (C) refers to a
material’s ability to store electrical charge. The product of resistance and capacitance (RC)
needs to be low to create fast chips, since device speed is inversely proportional to RC
(lower RC = faster devices).
Looking at the “R” side of this challenge, higher-resistance lines carry less current,
which slows device speed. This is because higher resistance reduces electron flow, so it
takes longer to build up the minimum charge (number of electrons) or “threshold voltage”
at a transistor’s “gate” to turn it on. While transistor speed continues to improve with
scaling and by reducing the distance electrons must travel, the challenge for inter-
connect scaling is to not become a bottleneck and lose that performance improvement
by slowing the flow of electrons between transistors.
On the “C” side, capacitance is a function of the insulating dielectric material
around the metal lines and the distance between them. Higher capacitance slows elec-
trons and can create unwanted “cross-talk,” where the signal in one metal line influ-
ences the signal in a neighboring line and causes the device to malfunction. In addition
to maintaining a suitable distance between lines, the development of “low-k” dielectric
materials (capacitance is a function of a material’s “k value”) has significantly lowered
capacitance. Today’s dielectric materials average around k = 2.5, compared with k = 3.8
for pure silicon dioxide. Various methods exist to achieve lower values; however, the
resulting ultra-low-k films become increasingly fragile as the k value decreases, posing
additional challenges in manufacturing.

1.3.4  Future of Device Scaling

To address these issues for further scaling, the industry continues to identify ways to
manage RC, particularly focusing on the metals involved. Copper has been success-
fully used for multiple device generations, so the industry is investing significant effort
in developing new approaches to extend its use. Creating copper vias, as shown in
Figure 1.13, involves a series of layers—typically a tantalum nitride barrier to prevent
metal diffusion into the dielectric, a tantalum liner to improve barrier adherence to the
metal, a copper seed layer to seed the metal plating, and finally, the core conducting

Core Metal
Width Simple Shrink Leads to Lower Line Resistance
Line Resistance Issues Options
Not Enough Room Alternate No
for Core Metal Barrier Barrier
Copper

Liner
Barrier

Total Line Total Line Alternate

Width Width Metal
Figure 1.13  Copper metallization in Si requires liner, barrier, and seed layers.

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 16 Chapter 1: Introduction to Device and Systems Packaging Technologies

bulk copper metal. A key area of research focus is identifying strategies for improving
the barrier/liner/seed layers to lower the overall resistance and to enable smaller lines
by creating “space” for the bulk copper fill.
One strategy is to make the high-resistance barrier and liner thinner. However,
opportunity for further thinning of these layers is limited. Both need to be continuous
with no gaps or voids in the film in order to achieve good reliability performance. This
requires a minimum thickness of about 1.5 to 2 nm for each layer, which leads to a com-
bined thickness of 3–4 nm on both sides of the trench structures.
A potential alternative being studied is a new type of “self-forming” barrier that
reacts with and forms on the dielectric surface adjacent to the copper line, which allows
more room for copper. Also, new liners made of cobalt and ruthenium are being devel-
oped to replace tantalum. They adhere better to the copper seed, enabling it to be more
conformal, eliminating voids, and thinner. Already, new technologies are in place to
achieve void-free copper fill of small trenches. Around the 5-nm technology node, how-
ever, copper as the primary conducting metal will ultimately have to be replaced with a
conducting material that does not require a barrier for these ultra-thin lines.
While much attention is placed on the metals, there are also many challenges requir-
ing investigations into improvements on the dielectric side. Here, the Holy Grail is to
reduce the dielectric constant as much as possible, the ultimate being k = 1, which is
air. Indeed, novel developments using “air gaps” have been developed, but both fab-
rication and production cost challenges are significant. Thus, many of the ideas being
explored for interconnect scaling involve the development of new metals, designs, and
processes.

1.4 Electronic Technology Waves: Microelectronics, RF/Wireless,

Photonics, MEMS, and Quantum Devices
The fundamental building block technologies behind all the electronic products,
whether that product is a PC, a DVD player, a smartphone, or an airbag in a car,
are four technology waves: microelectronics, RF/wireless, photonics, and MEMS.
A fifth wave, Quantum computing, is emerging in a big way, as described below.

1.4.1  Microelectronics: The First Technology Wave

Microelectronics is the first and most important technology wave. It started with
the invention of the transistor. The three discoveries that made this possible were:

1. The invention of the transistor in 1949 by Brattain, Bardeen, and Shockley at

Bell Labs.
2. The development of planar transistor technology by Bob Noyce in 1959.
3. The first integrated circuit (IC), which incorporated two transistors and a
resistor as shown in Figure 1.14, was developed by Jack Kilby in 1959. Their
combined discoveries earned them Nobel Prizes in 1972 and in 2000. The
transistor is the single most important fundamental building block of all
modern electronics. Microelectronics acts as the fundamental base of more than
90 percent of all microsystems products.

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 Chapter 1: Introduction to Device and Systems Packaging Technologies 17

Transistor Rudimentary IC Packaged IC

Transistors

Resistors Integration IC
of Transistors

Circuit
Board
Figure 1.14  The invention of the first integrated circuit.

Figure 1.15 illustrates the famous Moore’s Law. In 1965, three years before he
co-founded Intel with Bob Noyce, Gordon Moore published an article in Electronics
magazine that turned out to be uncannily prophetic. Moore wrote that the number of
circuits on a silicon chip would keep doubling every year. He later revised this to every
18–24 months, a forecast that has held up remarkably well over several decades and
countless product cycles. He also described cost reduction as the second important
parameter in Moore’s Law.

Moore’s Law Prediction

108
1 billion
transistors
Number of Transistors

107 Pentium III

Xeon

106
80386 80486 Pentium III
80286
105
Pentium II
4004
8086 Pentium Pro
104
Pentium
8080 Projected
103

‘70 ‘75 ‘80 ‘85 ‘90 ‘95 ‘00 ‘05 ‘10 ‘15
Year
Figure 1.15  Moore’s Law predicts the IC integration to double every 18–24 months.

01_Tummala_CH01_p001-040.indd 17 26/06/19 1:30 pm

 18 Chapter 1: Introduction to Device and Systems Packaging Technologies

The secret behind Moore’s Law is that every 18–24 months or so, chipmakers double
the number of transistors that can be crammed onto a silicon wafer the size of a finger-
nail, as shown in Figure 1.15. They do this by etching microscopic grooves onto crystal-
line silicon with beams of ultraviolet radiation. A typical wire in a Pentium chip by Intel
was 1/500 the width of a human hair; the insulating layer is only 25 atoms thick. They
are now scaled by another factor of 5X in 2018.
But the laws of physics suggest that this doubling cannot be sustained forever.
Eventually, transistors will become so tiny that their silicon components will
approach the size of molecules. At these incredibly tiny distances, the bizarre rules of
quantum mechanics take over, permitting electrons to jump from one place to another
without passing through the space in-between. Like water from a leaky fire hose,
electrons will spurt across atom-size wires and insulators, causing fatal short circuits.
Transistor components are fast approaching the dreaded point-one limit—when
the width of transistor components reaches 0.1 micron and their insulating layers
are only a few atoms thick. Recently, Intel engineer Paul Pakan publicly sounded
the alarm in Science magazine, warning that Moore’s Law could collapse. He wrote,
“There are currently no known solutions to these problems.”
The key word is “known.” The search for a successor to silicon has become a kind
of crusade; it is the Holy Grail of computation. Among physicists, the race to create
another Silicon Valley for the next century has already begun.
The economic destiny and prosperity of entire nations may rest on one question:
can silicon-based computer technology sustain Moore’s Law beyond 2020? Moore’s
Law is the engine pulling a trillion-dollar industry. It’s the reason kids assume that
it’s their birthright to get a video-game system each Christmas that’s almost twice as
powerful as the one they got last Christmas. It’s the reason you can receive (and later
throw away) a musical birthday card that contains more processing power than the
combined computers of the Allied Forces in World War II.
But microsystems are more than microelectronics. The microelectronics based on
the transistor building block technology is one aspect of today’s electronic systems,
such as personal computers. But other systems, such as modern fiberoptic telecom-
munications, are based on photons, the fundamental properties of which are more
superior in some respects, providing the needed higher bandwidth for today’s Internet
traffic. We call this the photonic wave. There are other systems that are not transistors
based that are beginning to play a major role in modern electronics. These are RF and
MEMS waves.

1.4.2  RF and Wireless: The Second Technology Wave

The world is going portable and wireless. The radio and wireless revolution started with
Marconi in 1901. In December 1901, Guglielmo Marconi, in St. John’s, Newfoundland,
received the first wireless message to cross the Atlantic. Sent from Poldhu, Cornwall,
in England, his message was the letter S—three dots in Morse code. The demonstration
of the transatlantic reception over 2900 km helped Marconi establish the business of
wireless telegraphy. The originator of numerous innovations, including a method of
continuous-wave transmission, as well as grounded antennas, improved receivers, and
receiver relays, Marconi was also remarkable for his skills at marketing and promoting.
In 1897, he had established a company that soon offered radio communications services,
notably to shipping lines, though the transmission range was initially limited to some
240 km. By World War I, Marconi Companies in Britain and elsewhere were providing

01_Tummala_CH01_p001-040.indd 18 26/06/19 1:30 pm

 Chapter 1: Introduction to Device and Systems Packaging Technologies 19

Frequency (Hz)
104 105 106 107 108 109 1010 1011 1012

FM radio and TV
AM radio
Wireless cable

Cellular and PCS

Satellite and terrestrial microwave

LF MF HF VHF UHF SHF FHF
10
4
10 3
10 2
10 1
1 10 -1
10-2 10-3
Wavelength (meters)
Figure 1.16  RF and wireless: wavelength and applications.

radio communications worldwide. This earned Marconi the Nobel Prize for physics.
The fundamental technology behind today’s mobile phone is the same. A whole new
industry has emerged with applications that span from AM and FM radio to cellular
phone to satellite to microwave communications, as illustrated in Figure 1.16, across the
entire electromagnetic spectrum.
The main advantage of wireless is the fact that it cuts the cables, thus liberating
the user from the tether to the network. It allows communications anywhere anytime.
Of course, that is only realistic if the wireless equipment is small enough that it can
actually be carried around everywhere. This is where systems packaging applies.
Wireless technology is also increasingly used for non-communications functions.
Top-of-the-line Mercedes cars, for example, are now equipped with a collision avoidance
system that is based on radar. Navigational global positioning systems (GPS) are being
integrated into even more consumer items, where size and cost are paramount. For all of
these products, a small, low-cost RF module is required. Another RF/wireless applica-
tion is electronic toll taking on bridges and roads.
5G: The next big wireless communication is 5G, which started in 2018.

1.4.3  Photonics: The Third Technology Wave

In 1970, Corning Glass Works demonstrated highly transparent fibers, and Bell
Laboratories demonstrated semiconductor lasers that could operate at room temperature.
These demonstrations helped establish the feasibility of fiberoptic communications.
These discoveries are the fundamental building block technologies of today’s Internet
networks.
As we enter the new millennium with exploding Internet volume and limitless busi-
ness opportunities, it is natural to pause and think about how we are going to meet this
challenge. Needless to say, there is no better known physical medium than fiber, and
no signal source better than light to meet these new requirements. Therefore, as opti-
cal networking technology evolves from megabits per second to gigabits per second,

01_Tummala_CH01_p001-040.indd 19 26/06/19 1:30 pm

 20 Chapter 1: Introduction to Device and Systems Packaging Technologies

we should become quite comfortable with the power of the exponents and what it
means at the service levels. Fortunately, we have long ways to go to reach the data
transport limit of fiber. For example, with the current state of device technology,
a good laser source can emit 1016 photons/s, and a good detector—which can detect
a bit with 10 photons—can detect 1 Pb (1015 b/s) on a single fiber. Nevertheless, the
device technology is going to get better with time, further pushing the limit of optical
fiber capacity. Thus, fiber optics is a future-proof technology. With wavelength-division
multiplexing (WDM), it is now possible to transmit different colors of light over the
same fiber, which has provided another dimension to increasing bandwidth capacity
and channeling raw data capacity into smaller chunks of bandwidth. This advance is
akin to a self-expanding highway, where you open another channel when the traffic load
increases without laying a new fiber. Thus, WDM optical networks offer, among other
capabilities, flexibility, scalability, and capacity. Current systems are capable of deliv-
ering more than one Gb/s channel on a 100-channel system. By 2030, a 100-channel
capability, each at 10 Gb/s as illustrated in Figure 1.17, optical interconnections can be
expected to provide lot more than terabit capacities. In addition to bandwidth increase,
new technologies also enable more functionality in optics. If history is any indicator,
these capabilities will only get better and richer in features. Optical networks are already
being deployed, not only in the backbone of networks, but also in regional, metropolitan,
and access networks. Thus, optics will play a key role in next-generation network modes
and eventually at customers’ premises.

1000 1000

Total
Throughput
Number of Channels
Data Rate (Gbit/s)

100 100
Number of
Channels

10 10
Data Rate
Per Channel

1 1

1995 2000 2005 2010 2015

Year
Figure 1.17  Potential of optoelectronics technology to terabits per second.

01_Tummala_CH01_p001-040.indd 20 26/06/19 1:30 pm

A. Dedication
I would like to dedicate this book:

To my parents: For your lifelong dedication to me as your only child, for your love and support, and for teaching me the
meaning of family and the value of education.

To my family (Anne, Dinesh, Vijay, and Suneel and grandchildren Gracen, Mason, and Cooper): For being my love, pride, and
joy to go to work for every day.

To my teachers: For teaching me how to learn well and quickly and for insisting on my getting the best education at any cost.

To my students: For allowing me to learn with you and to teach you those principles I believe in, in preparing you and
challenging you to be the best you can be.

To IBM: For giving me endless opportunities to learn, contribute, grow, and become an IBM Fellow, my ultimate goal.

To Georgia Tech: For allowing me to pursue my dream of being part of the new generation of industry-centric academicians.

To PRC team: For realizing my dream of educating interdisciplinary individual students, for exploring the SOP vision, and for
educating the world about it through books and classes.

To NSF: For allowing me to pursue my dream of impacting the industry with the needed strategic technologies and educated
workforce.

To my academic colleagues: For accepting me into your world, for using this book, and for working to make packaging an
academic subject.

Finally, thank you to the book's coordinator, Karen May, Georgia Institute of Technology; the chapters editor, Prof. Raj
Pulugurtha, Florida International University (FIU); and, for graphics, Reed Crouch, Karen May, and Leonard Mendoza.

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B. About the Editor

Prof. Rao R. Tummala is a Distinguished and Endowed Chair Professor at the Georgia Institute of Technology, USA. He is well
known as an industrial technologist, technology pioneer, and educator.

Prior to joining Georgia Tech, he was an IBM Fellow and the Director of IBM's Advanced Systems Packaging Technology Lab.
He pioneered major technologies such as plasma display in the 1970s; and the first three generations of 100-chip MCM
package integration, based on the first LTCC, HTCC, and thin-film RDL, introducing the original MCM concept behind today's
2.5D packages for servers, mainframes, and supercomputers.

As an educator, Prof. Tummala was instrumental in setting up at Georgia Tech the largest academic center funded by NSF,
the Microsystems Packaging Research Center, of which he is Director. He pioneered a vision for an integrated approach to
research, education, and industry collaborations with companies in the USA, Europe, Japan, Korea, Taiwan, India, and China.
The Center has produced more than 1200 Ph.D. and M.S. packaging engineers, supplying the entire electronics industry.

Prof. Tummala has published 850 technical papers and invented technologies that resulted in over 110 patents. He is the
author of the first and best-selling microelectronics packaging reference book, Microelectronics Packaging Handbook, the
definitive work in the field; the first undergraduate textbook, Fundamentals of Microsystems Packaging; and the book that
introduced the SOP concept, Introduction to System-on-Package. Prof. Tummala has received more than 50 industry,
academic, and professional society awards. He is a Member of NAE, an IEEE Fellow, and past president of IEEE EPS and
IMAPS.

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C. Contributors
Mulugeta Abtew Sanmina Corporation, USA (Chap. 16)

Muhammad Ali Georgia Institute of Technology, USA (Chap. 19)

Swapan Bhattacharaya Engent Inc., USA (Chap. 7)

Oliver Brand Georgia Institute of Technology, USA (Chap. 13)

Justin Broughton Georgia Institute of Technology, USA (Chap. 3)

Parthasarathi Chakraborti Intel Corporation, USA (Chap. 7)

Gee Kung Chang Georgia Institute of Technology, USA (Chap. 12)

Bruce C. Chou Rockley Photonics, USA (Chap. 12)

Rabindra Das Massachusetts Institute of Technology, USA (Chap. 5)

Bartlet H. DeProspo Georgia Institute of Technology, USA (Chaps. 6, 10)

Treliant Fang Motorola, USA (Chap. 14)

Mukta Farooq GlobalFoundries, USA (Chap. 10)

Saumya Gandhi Texas Instruments, USA (Chap. 7)

Daniel Guidotti Georgia Institute of Technology, USA (Chap. 12)

Omkar Gupte Georgia Institute of Technology, USA (Chap. 10)

Peter Hesketh Georgia Institute of Technology, USA (Chap. 13)

Shinichi Iketani Sanmina Corporation, USA (Chap. 15)

Subramanian S. Iyer University of California, Los Angeles, USA (Chap. 10)

Yogendra Joshi Georgia Institute of Technology, USA (Chap. 3)

Dong Gun Kam Ajou University, Korea (Chap. 2)

Sundar Kamath Sanmina Corporation, USA (Chaps. 15, 16)

Beth Keser Intel Corporation, USA (Chap. 9)

Joungho Kim Korea Advanced Institute of Science and Technology (KAIST) (Chap. 2)

Haksun Lee Georgia Institute of Technology, USA (Chap. 17)

Fuhan Liu Georgia Institute of Technology, USA (Chap. 6)

Ravi Mahajan Intel Corporation, USA (Chap. 20)

Junki Min Georgia Institute of Technology, USA (Chap. 11)

Dibyajat Mishra Texas Instruments, USA (Chap. 7)

Kashyap Mohan Georgia Institute of Technology, USA (Chap. 20)

Chandra Nair Georgia Institute of Technology, USA (Chap. 6)

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 Nithin Nedumthakady Georgia Institute of Technology, USA (Chap. 10)

John H. L. Pang Nanyang Technological University, Singapore (Chap. 4)

John Papapolymerou Michigan State University, USA (Chap. 11)

Eric Perfecto GlobalFoundries, USA (Chap. 8)

Andrew F. Peterson Georgia Institute of Technology, USA (Chap. 2)

John Prymak KEMET, USA (Chap. 7)

Markondeya Raj Pulugurtha Florida International University, USA (Chaps. 5, 6, 7, 11, 18, 19, 21)

Koushik Ramachandran GlobalFoundries, USA (Chap. 15)

Siddharth Ravichandran Georgia Institute of Technology, USA (Chaps. 10, 21, 22)

Sandeep Sane Intel Corporation, USA (Chap. 20)

Ninad Shahane Texas Instruments, USA (Chap. 8)

Himani Sharma Georgia Institute of Technology, USA (Chap. 5)

Tailong Shi Georgia Institute of Technology, USA (Chap. 9)

Kamal Sikka IBM Corporation, USA (Chap. 3)

Srikrishna Sitaraman TE Connectivity, USA (Chap. 11)

Suresh K. Sitaraman Georgia Institute of Technology, USA (Chap. 4)

Vanessa Smet Georgia Institute of Technology, USA (Chaps. 8, 21)

Eakhwan Song Kwangwoon University, Korea (Chap. 2)

Vijay Sukumaran FormFactor Inc., USA (Chap. 6)

Venky Sundaram Georgia Institute of Technology, USA (Chap. 6)

Madhavan Swaminathan Georgia Institute of Technology, USA (Chap. 2)

Emmanouil M. Tentzeris Georgia Institute of Technology, USA (Chap. 11)

Rao R. Tummala Georgia Institute of Technology, USA (Chaps. 1, 9, 10, 11, 15, 16, 17, 18, 19, 20, 21, 22)

Krishna Tunga IBM Corporation, USA (Chap. 4)

Melinda Varga Georgia Institute of Technology, USA (Chap. 18)

Klaus-Juergen Wolter Technische Universität Dresden, Germany (Chaps. 13, 17)

C. P. Wong Georgia Institute of Technology, USA (Chaps. 5, 14)

Rui Zhang Georgia Institute of Technology, USA (Chap. 12)

Pengli Zhu Shenzhen Institutes of Advanced Technology, Chinese Academy of Sciences (Chap. 14)

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D. Preface
Electronic packaging means primarily interconnecting active and passive components to form modules initially and systems
finally. While powering, cooling, and protecting are important functions of any package, they are secondary. Design, materials,
and processes as well as test are assumed to be part of interconnections. The end goal of packaging is to form systems by
interconnecting all the miniaturized components with and without transistors. These systems can be consumer products like
smartphones, self-driving electric cars, cloud computers, PCs, laptops, notebooks, and watches. All these systems currently
have two parts: devices with transistors and components without transistors. Combined, these two span 15 different
technologies, as described in this book.

This book is about both device and systems packaging. The market for these technologies is in excess of $500 billion
worldwide, employing millions of people. Yet, device and systems packaging is not considered an academic subject, except at
Georgia Tech. A typical academic subject such as microelectronics or VLSI has extensive courses, curricula, educational
tracks, fundamental books, software tools, and hands-on facilities. Most of these don't exist in packaging. The number of
universities offering research programs with one or more courses, however, has increased rapidly in recent years. In the United
States, there were only two universities offering any packaging research or education in the 1980s: Cornell and Stanford. It is
estimated that this number in the United States, Europe, and the Far East is about 200 now, having grown from less than 10
universities in 1990 and 50 or so in 2000.

Fundamentals of Device and Systems Packaging is written to meet the academic need to educate undergraduate and graduate
students in the fundamentals as well as all 15 technologies necessary to form systems. While there have been many books
since my first modern book in 1988, Microelectronics Packaging Handbook, most, if not all, are considered reference books.
They typically deal with one or more topics in a review fashion. However, electronic systems, as described in this book, require
15 different device and systems packaging technologies. The topics span IC packaging and assembly, system board
packaging and assembly, and all the variations in between. It also deals with electrical design, thermo-mechanical design,
thermal design and technologies, materials, processes, properties, reliability, and so on. This was the case 10–20 years ago
when I wrote the first book. Today's systems are more than microelectronics. They are RF, optical, MEMS and sensors, power,
etc.

This book is more than interconnecting. It includes microelectronics, photonics, RF and millimeter wave, and MEMS and
sensors. All these devices along with other components need to be packaged to form systems. This is exactly what this book
is all about. It deals with all these technologies at the fundamental level—defining each, illustrating the key concepts behind
each, and introducing the critical nomenclature in a systematic fashion. Each topical chapter includes fundamental equations,
homework problems, and future trends.

The book introduces Moore's Law for packaging as Moore's Law for cramming transistors to form large ICs begins to come to
an end. It proposes the cramming of small ICs to form large homogeneous and heterogeneous packages. In contrast to
Moore's Law for large ICs, with the highest number of transistors compromising performance and cost, from node to node,
Moore's Law for packaging can be thought of as interconnecting the smallest transistors in smaller ICs with the highest
performance and lowest cost in 2D, 2.5D, and 3D package architectures with an equal or higher aggregate number of
transistors.

I am grateful to all of the 55 global authors from industry and academia. This book, just like the first edition, is written by so
many authors and yet reads as if written by one. I am thankful to Karen May, who headed the book project from start to finish,
and to Prof. Raj Pulugurtha, who moved from Georgia Tech to Florida International University during the course of preparing
this book. They have put in endless hours, coordinating with all of the 55 authors from around the world.

I am also grateful to Senior Editors Michael McCabe and Lara Zoble and the other editors at McGraw-Hill, who facilitated
printing the book in two colors and at a very affordable low cost for such a book that goes from wafers to systems with all the

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electronic technologies and applications. I thank my wife, Anne, for her patience, understanding, and full support during the
course of the book, as I worked every day and every weekend over 3 years, on top of my normal responsibilities of being a
Professor and the Director of the Microsystems Packaging Research Center at Georgia Tech.

My final thanks are, again, to all the authors who contributed to the book, working nights and weekends, adding to their
normal job responsibilities.

Prof. Rao R. Tummala

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1. PART 1: Fundamentals of Packaging
CHAPTER 2 Fundamentals of Electrical Design for Signals, Power, and Electromagnetic Interference

CHAPTER 3 Fundamentals of Thermal Technologies

CHAPTER 4 Fundamentals of Thermo-Mechanical Reliability

CHAPTER 5 Fundamentals of Package Materials at Microscale and Nanoscale

CHAPTER 6 Fundamentals of Ceramic, Organic, Glass, and Silicon Package Substrates

CHAPTER 7 Fundamentals of Passive Components and Integration with Active Devices

CHAPTER 8 Fundamentals of Chip-to-Package Interconnections and Assembly

CHAPTER 9 Fundamentals of Embedded and Fan-Out Packaging

CHAPTER 10 Fundamentals of 3D Packaging with and without TSV

CHAPTER 11 Fundamentals of RF and Millimeter-Wave Packaging

CHAPTER 12 Fundamentals of Optoelectronics Packaging

CHAPTER 13 Fundamentals of MEMS and Sensor Packaging

CHAPTER 14 Fundamentals of Package Encapsulation, Molding, and Sealing

CHAPTER 15 Fundamentals of Printed Wiring Boards

CHAPTER 16 Fundamentals of Board Assembly

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