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Digital System Design-LAB #4: Sir Naveed Baloch Hamza Farooq 17-CP-18

This document contains the solutions to 3 questions from a digital systems design lab assignment. Question 1 involves designing a 1024x8 RAM circuit in Verilog including block diagram, code, test bench, and waveform. Question 2 involves designing a 2048x16 ROM circuit using a text file for initialization in Verilog. Question 3 involves designing a 256x8 ROM connected to an 8-bit program counter that can operate in 4 modes and provides the block diagram, Verilog code, test bench, and waveform for the circuit.

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malik Arsh
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53 views7 pages

Digital System Design-LAB #4: Sir Naveed Baloch Hamza Farooq 17-CP-18

This document contains the solutions to 3 questions from a digital systems design lab assignment. Question 1 involves designing a 1024x8 RAM circuit in Verilog including block diagram, code, test bench, and waveform. Question 2 involves designing a 2048x16 ROM circuit using a text file for initialization in Verilog. Question 3 involves designing a 256x8 ROM connected to an 8-bit program counter that can operate in 4 modes and provides the block diagram, Verilog code, test bench, and waveform for the circuit.

Uploaded by

malik Arsh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Digital System Design-LAB #4

Submitted To:
Sir Naveed Baloch
Submitted By:
Hamza Farooq
17-CP-18
-------------------------------------------------------------------
LAB TASKS

Question no 1: Practice a Verilog code for designing the RAM circuit of 1024 locations and
each location consists of 8-bits.
Answer:
 Block Diagram
 Verilog Code

 Test Bench
 Waveform

---------------------
Question no 2: Design a ROM of 2048 locations, in which each location consists of 16-bits.
using
$readmemb(“romdata.txt”,R,0,7);
Answer:
 Block Diagram
 Verilog Code

 Text File: rom_2048.txt

 Test Bench
 Waveform

---------------------
Question no 3: A 256x8 read only memory (ROM) is connected with a special
type of 8-bit register called program counter (PC). PC can operate in four possible
modes:
Mode of operation PC_ModeSel Description
Value in PC is
Increment 00
incremented by 1
Value in PC is
Decrement 01
decremented by 1
Load data (Branching A new 8-bit data can be
10
mode) loaded inside PC.
The current value of PC
Retain data 11
remains unchanged
In increment mode, the PC will update value by one at each positive edge of the clock. In
Branching mode, a value of 8-bit will be loaded from outside. After this the PC will
increment/decrement from this newly loaded value. The circuit diagram of problem is shown
below: Write a Verilog code and test bench for the above design.
Answer:
 Block Diagram

 Verilog Code
1. Program Counter:

2. ROM 256*8:
3. Final PC plus ROM:

 Test Bench

 Waveform

---------------------

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