CS 251, Winter 2019, Assignment 3.0.

1
3% of course mark

Due Friday, March 1st, 5:30 PM

Lates accepted until 1:00 PM, March 2nd with a 15% penalty

1. (5 points) Consider the single-cycle computer shown on page 5 of this assignment.

Suppose the circuit elements take the following times: Instr mem: 150ps, Register
read: 50ps, Register write: 50ps, ALU and all adders: 75ps, Data memory: 150ps,
Control Unit: 15ps, Sign Extend & Shift Left Units: 5ps.
Assume that PC and MUXes don’t take any time.
Compute the minimum execution time for each instruction type below:
R-format: ps.

LW: ps.

SW: ps.

Branch: ps.

Jump: ps.

2. (8 points)
Consider the assembly language instruction at memory address 2516:

2516: addi $9,$4,251

In the figure on the next page, there are eight darks lines. On each line, write in
the value that travels along the corresponding wire(s) when executing this assembly
language instruction. Note: you should write a decimal number on each dark line, and
not an expression involving things like ‘PC’, etc. (Some numbers are more natural to
write in binary; for any binary numbers you use, you should subscript them with a ’2’
like 1012 .)
Assume that each register $i (with i > 0) contains the decimal value 60010 + i. For
example, $2 contains the value 602.

1
 0
M
u
x
(Question 2, continued)

Add ALU 1
result
Add Shift PCSrc
RegDst left 2
4 Branch
MemRead
Instruction [31 26] MemtoReg
Control
ALUOp
MemWrite

2
ALUSrc
RegWrite

Instruction [25 21] Read

PC Read register 1
address Read
Instruction [20 16] data 1
Read
register 2 Zero
Instruction
[31–0] 0 Registers Read ALU ALU
M Write data 2 0 Address Read
result 1
Instruction u register M data
u M
memory x u
Instruction [15 11] Write x
1 Data x
data 1 memory 0
Write
data
16 32
Instruction [15 0] Sign
extend ALU
control

Instruction [5 0]
3. (6 pts)
Consider the following MIPS assembly language instructions:

addi $1, $2, 100: addi $rt, $rs, immediate # add immediate
swr $1, 100($2): swr $rt, immediate($rs) # store word write register
ber $2, $3, -5: ber $rs, $rt, immediate # branch on equal, update register

These instructions are I-format instructions similar to the load word and store word
instructions. The addi, swr and ber instructions write a computed value to the des-
tination register $rt. The instructions do not require any physical hardware changes
to the datapath. The effect of each instruction is given below. Fill in the table below
indicating the value of all existing control lines necessary to execute the addi, swr and
ber instructions on the datapath. You must use don’t cares where appropriate.

The swr instruction stores to memory and writes to the register file. It stores to mem-
ory at address [$rs+$rt] the value contained in $rt. Also, it takes the sum of the $rs
and $rt registers and writes the result to register $rt. The new value of $rt is updated
at the end of the clock cycle.

The ber (branch on equal and update register) instruction takes the branch if $rs ==
$rt. It will also modify register $rt to the difference between $rs and $rt.

addi: $rt <= se immediate + $rs

swr: MEM[$rs+$rt] <= $rt, $rt <= $rs + $rt
ber: PC <= PC+4 + (offsetx4), $rt <= $rs-$rt

Type Reg ALU Mem Reg Mem Mem Branch ALU ALU
Dst Src ToReg Write Read Write op1 op0
R-format 1 0 0 1 0 0 0 1 0
lw 0 1 1 1 1 0 0 0 0
sw X 1 X 0 0 1 0 0 0
beq X 0 X 0 0 0 1 0 1
addi
swr
ber

3
4. (10 pts)
We want to modify the single-cycle computer to implement a new instruction in the
datapath. The lui or load upper immediate instruction is an I-format instruction.
The form of this MIPS instruction is

lui rt, imm

This instruction loads the 16-bit imm into the upper halfword of the register rt; the
lower bits of the register are set to 0. For example, using hexidecimal for the immediate
field,

liu $6, 0xA7CF

will set

$6 <- 0xA7CF0000

(a) (6 pts) Modify the Single Cycle datapath on the next page to implement the lui
instruction. You may add multiplexors, control bits and additional components as
needed. Marks will also be awarded for the efficiency of the solution. Be sure that
all other MIPS instructions executing on the datapath will still work. Summarize
your changes to the datapath below, and make the modifications to the datapath
provided on the next page.

(b) (4 pts) In the table below, give the settings of the control bits to implement the
new lui MIPS instruction. Use Don’t Cares where appropriate. If you need an
extra control line to implement this instruction or if you need to increase the
number of bits in a control line, add additional columns to the table for the new
control line, split a column to increase the number of bits in a control line, and in
either case include a note below explaining the effect of the new/increased con-
trol line(s) on the datapath and what its setting should be for other instructions.
Make sure you do not break any other instructions. You should be able to deter-
mine the purpose and effects of each of the control signals from the Single Cycle
datapath on the next page.
Type Reg ALU Mem Reg Mem Mem Branch ALU ALU lui
Dst Src ToReg Write Read Write op1 op0
lui

State the value(s) of any new control signal(s) for other MIPS instructions:

4
 Instruction [25–0] Shift Jump address [31–0]
left 2
26 28 0 1

PC+4 [31–28] M M
u u
x x
Add ALU 1 0
result
Add Shift
RegDst
Jump left 2
4 Branch
MemRead
Instruction [31–26]
Control MemtoReg
ALUOp
MemWrite
ALUSrc

5
RegWrite

Instruction [25–21] Read

PC Read register 1
address Read
Instruction [20–16] Read data 1
register 2 Zero
Instruction
[31–0] 0 Registers Read ALU ALU
M Write data 2 0 Address Read
result 1
Instruction u register M data
u M
memory x u
Instruction [15–11] Write x
1 Data x
data 1 memory 0
Write
data
16 32
Instruction [15–0] Sign
extend ALU
control

Instruction [5–0]
 Additional exercises on single-cycle architecture: The rest of the course will focus
on improvements to the single-cycle architecture. Before proceeding, you may wish to do
some additional exercises from the textbook (unmarked, solutions not provided):

• Exercise 3.21

• Exercise 4.1

• Exercise 4.2

• Exercise 4.3