A B C D E

CLK GEN
3
Leopard 3 Block Diagram Project code: 91.4C901.001 36
SYSTEM DC/DC
MAX1999
PCB P/N : 48.4C901.001 INPUTS OUTPUTS
ICS954206AG 4,5
REVISION : 05205-1 5V_S3
Mobile CPU DCBATOUT
3V_S5
4 Dothan 4

26 DDR2*2 11,12 SYSTEM DC/DC

1394
533MHz 37 TPS5130
Conn
INPUTS OUTPUTS
Host BUS
22,23 400/533MHz 1D05V_S0

24 22 DCBATOUT 1D2V_S0
PCMCIA Power PCI7411 1D8V_S3
6,7,8,9,10 14
1 SLOT Switch LVDS LCD
TPS2220A CARDBUS
SD/MS 24
1394 Alviso 13 MAXIM CHARGER
SD/MS/MMC/SM
6 in 1 GM SVIDEO/COMP TVOUT 34 MAX1909
Card Slost
INPUTS OUTPUTS
RGB CRT CRT BT+
3
DMI I/F 18V 4.0A 3

29 100MHz DAUGHTER BOARD DCBATOUT

Mini-PCI 5V 100mA
BLUE THUMB
802.11a/b/g
16,17,18,19

26 25,26 USB 2.0 USB x 2 CPU DC/DC

RJ45 USB x 2 30 35
10/100 RTL8100C PCI BUS
MAX1907
CONN
21 INPUTS OUTPUTS
P IDE MASTER HDD
ICH6-M VCC_CORE
30
25 DCBATOUT
RJ11 MODEM AC97-LINK DVD/ 21 0.844~1.3V
MDC Card SLAVE 27A
CONN CD-RW

21
MIC IN13 PCI EXPRESS/ USB2.0 EXPRESSCARD
2

AC'97 CODEC
27 PCB LAYER 2

AD1981B LPC Bus

L1: Signal 1
L2: GND
LINE OUT
L3: Signal 2
31 LPC 33 21
13 X-BUS Power
OP AMP
28 Docking KBC Debug
Switch
L4: Signal 3
NS97551 Conn TPS2231
G1420BF3U L5: VCC
L6: Signal 4

2CH
29 31\ 31 19 32
SPEAKER Comsumer Touch Int. Thermal FlashRom
1 IR Pad KB & Fan 4Mb 1
G768D (512kB)
Wistron Corporation

om
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

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Taipei Hsien 221, Taiwan, R.O.C.

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tm
Title

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Block Diagram

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Size Document Number Rev

in
A3 -1
Leopard 3

xa
he
Date: Tuesday, July 19, 2005 Sheet 1 of 41
A B C D E
 A B C D E

ICH6-M Integrated Pull-up

and Pull-down Resistors ICH6-M EDS 14308 0.8V1
Power name description
5V_S0= 5 Voltage power up on system work(S0 state)
ACZ_BIT_CLK, DPRSLP#, EE_DIN,
5V_S3= 5 Voltage suspend to RAM(S3 state)
EE_DOUT, EE_CS, GNT[5]#/GPO[17],
ICH6 internal 20K pull-ups 5V_S5= 5 Voltage soft off(S5 state)
4 GNT[6]#/GPO[16], LDRQ[1]/GPI[41], 4
3D3V_S0= 3.3 Voltage power up on system work(S0 state)
LAD[3:0]#/FB[3:0]#, LDRQ[0],
3D3V_S3= 3.3 Voltage suspend to RAM(S3 state)
PME#, PWRBTN#, TP[3]
3D3V_S5= 3.3 Voltage soft off(S5 state)
LAN_RXD[2:0] ICH6 internal 10K pull-ups LVDDR_1D8V= 1.8 Voltage power up on system work(S0 state)
1D8V_S3= 1.8Voltage suspend to RAM(S3 state)
ACZ_RST#, ACZ_SDIN[2:0], ACZ_SYNC, ICH6 internal 20K pull-downs
2D5V_S0= 2.5 Voltage power up on system work(S0 state)
ACZ_SDOUT,ACZ_BITCLK, DPRSLPVR,
SPKR
VCC_CORE_S0= CPU VID Voltage power up on system work(S0 state)
USB[7:0][P,N] ICH6 internal 15K pull-downs 1D5V_VCCA_S0= 1.5 Voltage power up on system work(S0 state)
1D5V_S0= 1.5 Voltage power up on system work(S0 state)
DD[7], SDDREQ ICH6 internal 11.5K pull-downs
1D5V_S5= 1.5 Voltage soft off(S5 state)
LAN_CLK ICH6 internal 100K pull-downs DDR_VREF_S3= 0.9 Voltage suspend to RAM(S3 state)
0D9V_S0= 1.25 Voltage power up on system work(S0 state)
1D2_VGA_S0= 1.2 Voltage power up on system work(S0 state) for VGA
3 3
1D05V_S0= 1.05 Voltage power up on system work(S0 state)
ICH6-M IDE Integrated Series CORE_GMCH_S0= 1.05 Voltage power up on system work(S0 state) for ALVISO core power
Termination Resistors VCCP_GMCH_S0= 1.05 Voltage power up on system work(S0 state)for ALVISO BUSIO power
DD[15:0], DIOW#, DIOR#, DREQ,
approximately 33 ohm
DDACK#, IORDY, DA[2:0], DCS1#,
DCS3#, IDEIRQ

PCI RESOURCE TABLE

2 2
DEVICE IDSEL PCI IRQ REQ# / GNT#

Mini-PCI AD21 P_INTE# REQ0#/GNT0#

(CARBUS)P_INTG#
Cardbus Controller (1394)P_INTF#
AD22 (CARD READER)P_INTG# REQ1#/GNT1#
TI7411

LAN AD23 P_INTE# REQ2#/GNT2#

Blue Thumb AD24

1 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
ITP
Size Document Number Rev
A3
Leopard 3 -1
Date: Tuesday, July 12, 2005 Sheet 2 of 41
A B C D E
 A B C D E

3D3V_S0 3D3V_S0 3D3V_S0

R114
1 2 3D3V_APWR_S0 1 2 3D3V_48MPWR_S0
5,7,9,11,13,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41 3D3V_S0
L17 MLB-201209-11 4D7R3

1
3D3V_S0
C156 C373 C154 C155
SC4D7U10V5ZY SCD1U16V SC4D7U10V5ZY SCD1U16V

1
DY DY R118
10KR2
DummyR118(up side),Mounting R125(down side)

2
4
3D3V_S0 ITP_EN --SRC7 on 4

1 L34 2 3D3V_CLKGEN_S0

1
MLB-201209-11

1
R125 Mounting R118(up side),DummyR125(down side)
C362 C374 C371 C378 C379 C372 C361 C382 10KR2
SC10U10V6ZY-U SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V
DY --CPU2_ITP on
2

2
DY DY DY

2
3D3V_S0
20,36 CLK_PWRGD#
3D3V_APWR_S0

1
3D3V_48MPWR_S0 R453
1 2 C380 CLK_XOUT 10KR2
SC22P 3D3V_CLKGEN_S0
2 CLK_XIN

2
X6 H/L: 100/96MHz
X-14D31818M-17 U57
SS_SEL

49
50

10

34
28
21

42
37
11
48
1

7
1
1 2 C381

1
SC22P RN61

VDDPCI
VDDPCI

VDDA

VDDREF
X2
X1

VDD48
VTT_PWRGD#/PD

VDDSRC
VDDSRC
VDDSRC

VDDCPU
CLK_CPUC1 1 4 R455
CLK_MCH_BCLK 6 10KR2
CLK_CPUT1 2 3 CLK_MCH_BCLK# 6
RN58 DY
4 1 CLK_SRCC1 SRN33-2-U2
21 CLK_PCIE_NEW# PM_STPCPU# 17,36

2
3 3 2 CLK_SRCT1 3
21 CLK_PCIE_NEW
20 54 RN60
SRCCLKC1 CPU_STOP# CLK_CPUC2
SRN33-2-U2 23 43 2 3 CLK_XDP_CPU# 4
RN40 25
SRCCLKC2 CPUCLKC0
40 CLK_CPUT2 1 DY 4
SRCCLKC3 CPUCLKC1 CLK_XDP_CPU 4
4 1 CLK_SRCC3 27 35
7 CLK_MCH_3GPLL# SRCCLKC4_SATA CPUCLKC2_ITP/SRCCLKC7
3 2 CLK_SRCT3 30 SRN33-2-U2
7 CLK_MCH_3GPLL SRCCLKC5
32 44 RN59
SRCCLKC6 CPUCLKT0 CLK_CPUT0 DREFCLK
SRN33-2-U2
CPUCLKT1 41 1 4 CLK_CPU_BCLK 4 1 2 R520
RN41 19 36 CLK_CPUC0 2 3 49D9R2F
SRCCLKT1 CPUCLKT2_ITP/SRCCLKT7 CLK_CPU_BCLK# 4
4 1 CLK_SRCC5 22 DREFCLK# 1 2 R521
17 CLK_PCIE_ICH# SRCCLKT2 49D9R2F
3 2 CLK_SRCT5 24 12 FS_A SRN33-2-U2 1 R459 2 10R2
17 CLK_PCIE_ICH SRCCLKT3 FSLA/USB_48MHZ CLK48_USB 17
26 16 1 2 CLK_PCIE_NEW 1 2 R451
SRCCLKT4_SATA FSLB/TEST_MODE CLK48_CARDBUS 22

SEL100_96MHZ#/PCICLK_F1
SRN33-2-U2 31 R460 33R2 49D9R2F
SRCCLKT5 CPU_SEL1 4,7
TPAD30 TP57 TP_SRCC6 R523 2 DY 0R2-0
1 CLK_SRCT6 33 18 CLK_SRCC0 RN56 CLK_PCIE_NEW# 1 2 R452
TPAD30 TP56 TP_SRCT6 R524 2 0R2-0 CLK_SRCC6 SRCCLKT6 96MHZ_SSC/SRCCLKC0 CLK_SRCT0 49D9R2F
1 96MHZ_SST/SRCCLKT0 17 1 4 SB DREFSSCLK# 7
DY CLK_REF14 52 2 3 CLK_XDP_CPU 1 2 R470
DY 49D9R2F
21 PREQ2# REF0 DREFSSCLK 7
R468 1 2 22R2
ITP_EN/PCICLK_F0
53 15 DOT96C
17 CLK_ICH14 REF1/FSLC/TEST_SEL DOTC_96MHZ
R467 1 2 22R2 46
PCI/SRC_STOP#
14 DOT96T SRN33-2-U2 CLK_XDP_CPU# 1 2 R465
DY 49D9R2F
27 CLK_CODEC SCLK DOTT_96MHZ
47 2 R117
1 33R2
SDATA DREFCLK# 7
R522 2 1 2K2R2 2 R116
1 33R2 CLK_CPU_BCLK 1 2 R461
4,7 CPU_SEL0 DREFCLK 7 49D9R2F
PCICLK5
PCICLK4
PCICLK3
PCICLK2
CLK_CPU_BCLK# 1 2 R464
11,19 SMBC_ICH
GNDA

49D9R2F
IREF
GND
GND
GND
GND
GND
GND

11,19 SMBD_ICH
CLK_MCH_BCLK 1 2 R463
49D9R2F
CLK_MCH_BCLK# 1 2 R462
51
45
29
13
6
2
38

9
55
8
5
4
3
56
39

ICS954206AG 49D9R2F

2 CLK_IREF 2 R115 2
1
475R2F

1
R458
2 SS_SEL
REQSEL ICS954206AG Spread DREFSSCLK 1 2 R450
49D9R2F
31 PCLK_KBC 22R2 CLK_PCI3 R466 33R2 DREFSSCLK# 2 R457
17 PM_STPPCI#
R126
CLK_PCI4
CLK_PCI5
2
2
1
R123
1
R124
33R2
33R2
PCLK_PCM 22
PCLK_LAN 25
Spectrum Select CLK_MCH_3GPLL
1
49D9R2F
2 1 PCLK_MINI 29 1 2 R441
1 2 ITP_EN 49D9R2F
17 CLK_ICHPCI 33R2 SS3 SS2 SS1 SS0 Spread Amount% CLK_MCH_3GPLL# 1 2 R442
49D9R2F
0 0 0 0 -0.8
0 0 0 1 -1.0
0 0 1 0 -1.25 CLK_PCIE_ICH 1 2 R444
49D9R2F
0 0 1 1 -1.5 CLK_PCIE_ICH# 1 2 R443
3D3V_S0
NEAR CLKGEN 49D9R2F
0 1 0 0 -1.75
0 1 0 1 -2.0
SD 0817 CLK_CPU_BCLK TP87 TPAD30
0 1 1 0 -2.5
CLK_CPU_BCLK# TP88 TPAD30
1

3D3V_CLKGEN_S0 0 1 1 1 -3.0
R525 R113 close to CPU
10KR2 1 2 FS_A 1 0 0 0 +-0.3
10KR2
1 1 0 0 1 +-0.4 1
2

REQSEL 1 0 1 0 +-0.5
FS_C FS_B FS_A CPU Wistron Corporation
1

1 0 1 1 +-0.6 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

om
R526 0 0 0 266M Taipei Hsien 221, Taiwan, R.O.C.

l.c
DUMMY-R2 0 0 1 133M 1 1 0 0 +-0.8

ai
0 1 0 200M Title

tm
0 1 1 166M
DY 1 0 0 333M
1 1 0 1 +-1.0 Clock Generator (ICS954206AG )

ho
2

1 0 1 100M 1 1 1 0 +-1.25 Size Document Number Rev

f@
1 1 0 400M A3
Leopard 3 -1

in
1 1 1 Reserved 1 1 1 1 +-1.5

xa
Date: Monday, August 15, 2005 Sheet 3 of 41

he
A B C D E
 A B C D E

VCCP_GMCH_S0

5,6,7,9,10,16,18,36,40,41 VCCP_GMCH_S0
3D3V_S0

ADDR GROUP 0
3,5,7,9,11,13,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41 3D3V_S0

6 H_A#[31..3]

U45A 62.10055.011
VCCP_GMCH_S0
4 H_A#3 P4 N2 4
A3# ADS# H_ADS# 6
H_A#4 U4 L1
A4# BNR# H_BNR# 6
H_A#5 V3 J3
A5# BPRI# H_BPRI# 6

1
H_A#6 R3
H_A#7 A6# R289
V2 A7# DEFER# L4 H_DEFER# 6
H_A#8 W1 H2 56R2J
A8# DRDY# H_DRDY# 6
H_A#9 T4 M2
A9# DBSY# H_DBSY# 6
H_A#10 W2

2
H_A#11 A10# Place testpoint on
Y4 A11# BR0# N4 H_BREQ#0 6
H_A#12 Y1 H_IERR# with a GND

CONTROL
H_A#13 A12# H_IERR# 0.1" away
U1 A13# IERR# A4
H_A#14 AA3 B5
A14# INIT# H_INIT# 16
H_A#15 Y3
H_A#16 A15#
AA2 A16# LOCK# J2 H_LOCK# 6
6 H_ADSTB#0 U3 ADSTB#0 H_CPURST# 6
6 H_REQ#[4..0] RESET# B11 H_RS#[2..0] 6
H_REQ#0 R2 H1 H_RS#0
H_REQ#1 P3 REQ0# RS0# H_RS#1 U45B
REQ1# RS1# K1 H_D#[63..0] 6
H_REQ#2 T2 L2 H_RS#2
H_REQ#3 P1 REQ2# RS2# H_D#0 62.10055.011 H_D#32
REQ3# TRDY# M3 H_TRDY# 6 A19 D0# D32# Y26
H_REQ#4 T1 H_D#1 A25 AA24 H_D#33
REQ4# VCCP_GMCH_S0 H_D#2 D1# D33# H_D#34
K3 H_HIT# 6 A22 T25

XTP/ITP SIGNALS
H_A#17 HIT# H_D#3 D2# D34# H_D#35
AF4 K4 B21 U23

DATA GRP 0
DATA GRP 2
A17# HITM# H_HITM# 6 D3# D35#
H_A#18 AC4 H_D#4 A24 V23 H_D#36
A18# D4# D36#

1
H_A#19 AC7 C8 H_D#5 B26 R24 H_D#37
ADDR GROUP 1
H_A#20 A19# BPM#0 R285 H_D#6 D5# D37# H_D#38
AC3 A20# BPM#1 B8 A21 D6# D38# R26
H_A#21 AD3 A9 56R2J H_D#7 B20 R23 H_D#39
H_A#22 A21# BPM#2 VCC_CORE_S0 H_D#8 D7# D39# H_D#40
AE4 A22# BPM#3 C9 C20 D8# D40# AA23
H_A#23 AD2 A10 H_D#9 B24 U26 H_D#41

2
3 H_A#24 A23# PRDY# XDP_BPM#5 H_D#10 D9# D41# H_D#42 3
AB4 A24# PREQ# B10 D24 D10# D42# V24

1
H_A#25 AC6 A13 XDP_TCK H_D#11 E24 U25 H_D#43
H_A#26 A25# TCK XDP_TDI R16 H_D#12 D11# D43# H_D#44
AD5 A26# TDI C12 C26 D12# D44# V26
H_A#27 AE2 A12 XDP_TDO 150R2 H_D#13 B23 Y23 H_D#45
H_A#28 A27# TDO XDP_TMS H_D#14 D13# D45# H_D#46
AD6 A28# TMS C11 E23 D14# D46# AA26
H_A#29 AF3 B13 XDP_TRST# H_D#15 C25 Y25 H_D#47

2
H_A#30 A29# TRST# DBR# D15# D47#
AE1 A30# DBR# A7 6 H_DSTBN#0 C23 DSTBN0# DSTBN2# W25 H_DSTBN#2 6
H_A#31 AF1 C22 W24
A31# 6 H_DSTBP#0 DSTBP0# DSTBP2# H_DSTBP#2 6
AE5 B17 CPU_PROCHOT# D25 T24
6 H_ADSTB#1 ADSTB#1 PROCHOT# 6 H_DINV#0 DINV0# DINV2# H_DINV#2 6
B18
HCLK THERM

THERMDA THERMDP1 20
16 H_A20M# C2 A20M# THERMDC A18 THERMDN 20
D3 H_D#16 H23 AB25 H_D#48
16 H_FERR# FERR# PM_THRMTRIP-A# 7,16 D16# D48#
A3 C17 H_D#17 G25 AC23 H_D#49
16 H_IGNNE# IGNNE# THERMTRIP# D17# D49#
H_D#18 L23 AB24 H_D#50
PM_THRMTRIP-I# 7,16 D18# D50#
C6 A15 H_D#19 M26 AC20 H_D#51

DATA GRP 1
DATA GRP 3
16 H_STPCLK# STPCLK# ITP_CLK1 CLK_XDP_CPU# 3 D19# D51#
D1 A16 H_D#20 H24 AC22 H_D#52
16 H_INTR LINT0 ITP_CLK0 CLK_XDP_CPU 3 D20# D52#
D4 B14 H_D#21 F25 AC25 H_D#53
16 H_NMI LINT1 BCLK1 CLK_CPU_BCLK# 3 D21# D53#
B4 B15 H_D#22 G24 AD23 H_D#54
16 H_SMI# SMI# BCLK0 CLK_CPU_BCLK 3 PM_THRMTRIP# D22# D54#
H_D#23 J23 AE22 H_D#55
should connect to H_D#24 D23# D55# H_D#56
M23 D24# D56# AF23
ICH6 and Alviso H_D#25 J25 AD24 H_D#57 Layout Note:
PZ47903 D25# D57#
without T-ing H_D#26 L26 AF20 H_D#58 Comp0, 2 connect with Zo=27.4 ohm, make
( No stub) H_D#27 D26# D58# H_D#59 trace length shorter than 0.5" .
N24 AE21
ITP Conn. H_D#28 M25
D27# D59#
AD21 H_D#60 Comp1, 3 connect with Zo=55 ohm, make
CPU H_D#29 H26
D28#
D29#
D60#
D61# AF25 H_D#61 trace length shorter than 0.5" .
H_D#30 N25 AF22 H_D#62
H_D#31 D30# D62# H_D#63
K25 D31# D63# AF26
6 H_DSTBN#1 K24 DSTBN1# DSTBN3# AE24 H_DSTBN#3 6
2
Dothan A: R43,R44=DUMMY 6 H_DSTBP#1 L24 DSTBP1# DSTBP3# AE25 H_DSTBP#3 6 2
6 H_DINV#1 J26 AD20 H_DINV#3 6
Dothan B: R43,R44=0R DINV1# DINV3#
TCK(PIN 5) TPAD30 TP3 PSI# E1 P25 COMP0 R302 1 2 27D4R2F VCCP_GMCH_S0
0R0402-PAD PSI# COMP0 COMP1 R301 54D9R2F
COMP1 P26 1 2
3,7 CPU_SEL0 1 R273 2 CPU_SEL0_CPU C16 BSEL0 COMP2 AB2 COMP2 R25 1 2 27D4R2F

1
3,7 CPU_SEL1 1 R276 2 CPU_SEL1_CPU C14 BSEL1 COMP3 AB1 COMP3 R24 1 2 54D9R2F
R288
0R0402-PAD 200R2J
TCK(PIN A13)
MISC G1
DPRSTP# H_DPRSLP# 16
TPAD30 TP1 CPU_TP3 C3 B7 H_DPSLP# 16

2
TPAD30 TP5 CPU_TP4 RSVD2 DPSLP#
AF7 RSVD3 DPWR# C19 H_DPWR# 6
FBO(PIN 11) TPAD30 TP6 CPU_TP5 AC1 E4
RSVD4 PWRGOOD H_PWRGD 16
VCCP_GMCH_S0 TPAD30 TP38 CPU_TP6 E26 A6
RSVD5 SLP# H_CPUSLP# 6,16
1 2R23 GTLREF AD26 GTLREF0 TEST1 C5 TEST1
1KR2F F23 TEST2
TEST2
VCCP_GMCH_S0 1
R22
2KR2F Layout Note:
PZ47903

1
0.5" max length.
R18 R284
2

H_CPURST# 2 1R283 1KR2 1KR2

54D9R2F
XDP_TDO
DY DY
2 1R275 BSEL[1:0] Freq.(MHz)

2
54D9R2F LH 100 NO STUFF
CPU_PROCHOT# 2 1R274 LL 133
56R2J
XDP_TDI 1 2R277
150R2
1 1
XDP_TMS 1 2R279
39D2R2F
XDP_TRST# 1 2R278
680R2 Wistron Corporation
XDP_TCK 1 2R280 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
27D4R2F Taipei Hsien 221, Taiwan, R.O.C.

Title
CPU (1 of 2)
Size Document Number Rev
A3
All place within 2" to CPU Leopard 3 -1
Date: Monday, August 15, 2005 Sheet 4 of 41
A B C D E
 A B C D E

U45D
62.10055.011 VCC_CORE_S0
A2 VSS0 VSS97 D13
VCC_CORE_S0 VCC_CORE_S0 1.8V is for Dothan A5 D15
U45C VSS1 VSS98 4,36 VCC_CORE_S0
A2 before. A8 VSS2 VSS99 D17
A11 VSS3 VSS100 D19
AA11 62.10055.011 G5 A14 D21 VCCP_GMCH_S0
VCC0 VCC59 VSS4 VSS101
AA13 VCC1 VCC60 H22 1D5V OR 1D8V A17 VSS5 VSS102 D23
AA15 VCC2 VCC61 H6 Intel suggest Dothan A20 VSS6 VSS103 D26 4,6,7,9,10,16,18,36,40,41 VCCP_GMCH_S0
AA17 VCC3 VCC62 J21 A2 or later only use A23 VSS7 VSS104 E3
AA19 J5 A26 E6 3D3V_S0
VCC4 VCC63 1.5V VSS8 VSS105
AA21 VCC5 VCC64 K22 AA1 VSS9 VSS106 E8
AA5 VCC6 VCC65 U5 AA4 VSS10 VSS107 E10 3,7,9,11,13,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41 3D3V_S0
4 AA7 V22 1D5V_VCCA_S0 AA6 E12 4
VCC7 VCC66 VSS11 VSS108
AA9 VCC8 VCC67 V6 AA8 VSS12 VSS109 E14
AB10 VCC9 VCC68 W21 AA10 VSS13 VSS110 E16
AB12 VCC10 VCC69 W5 AA12 VSS14 VSS111 E18

1
AB14 VCC11 VCC70 Y22 AA14 VSS15 VSS112 E20
AB16 Y6 C15 C10 AA16 E22
VCC12 VCC71 SCD01U16V3KX SC10U10V6ZY-U VSS16 VSS113
AB18 AA18 E25

2
VCC13 VSS17 VSS114 1D5V_VCCA_S0
AB20 VCC14 VCCA0 F26 AA20 VSS18 VSS115 F1
AB22 B1 TP_VCCA1 AA22 F4
VCC15 VCCA1 TP_VCCA2 TP2 TPAD30 VSS19 VSS116
AB6 VCC16 VCCA2 N1 AA25 VSS20 VSS117 F5
AB8 AC26 TP_VCCA3 TP4 TPAD30 VCCP_GMCH_S0 AB3 F7 1D5V_VCCA_S0 1D5V_S0
VCC17 VCCA3 VSS21 VSS118

1
AC11 TP39 TPAD30 AB5 F9
VCC18 VSS22 VSS119

1
AC13 VCC19 VCCP0 D10 CPU_D10 1 R286
2 AB7 VSS23 VSS120 F11 I max = 120 mA R295
AC15 D12 0R2-0 AB9 F13 3D3V_S0 BC54 12K7R3F
VCC20 VCCP1 VSS24 VSS121 SC22P R17
AC17 D14 AB11 F15 U44 DY

2
VCC21 VCCP2 VSS25 VSS122
AC19 D16 AB13 F17 DY 1 2

2
VCC22 VCCP3 VSS26 VSS123 1D5V_VCCA_SET
AC9 VCC23 VCCP4 E11 AB15 VSS27 VSS124 F19 1 SHDN# SET 5
AD10 E13 AB17 F21 2 0R2-0
VCC24 VCCP5 VSS28 VSS125 GND
AD12 VCC25 VCCP6 E15 AB19 VSS29 VSS126 F24 3 IN OUT 4
AD14 VCC26 VCCP7 F10 AB21 VSS30 VSS127 G2

1
AD16 VCC27 VCCP8 F12 AB23 VSS31 VSS128 G6

1
AD18 F14 AB26 G22 G913C-U DY R296
VCC28 VCCP9 VSS32 VSS129 BC53 BC2 49K9R2F
AD8 VCC29 VCCP10 F16 AC2 VSS33 VSS130 G23
SC1U10V3ZY SC1U10V3ZY
AE11 K6 AC5 G26 DY

2
VCC30 VCCP11 VSS34 VSS131
AE13 L21 AC8 H3 DY DY

2
VCC31 VCCP12 VSS35 VSS132
AE15 VCC32 VCCP13 L5 AC10 VSS36 VSS133 H5
AE17 VCC33 VCCP14 M22 AC12 VSS37 VSS134 H21
AE19 VCC34 VCCP15 M6 AC14 VSS38 VSS135 H25
AE9 VCC35 VCCP16 N21 AC16 VSS39 VSS136 J1 0.1u *10 150u *1
3 AF10 N5 AC18 J4 VCCP_GMCH_S0 3
VCC36 VCCP17 VSS40 VSS137
AF12 VCC37 VCCP18 P22 AC21 VSS41 VSS138 J6
AF14 VCC38 VCCP19 P6 AC24 VSS42 VSS139 J22
AF16 R21 AD1 J24 NO STUFF
VCC39 VCCP20 VSS43 VSS140
AF18 VCC40 VCCP21 R5 AD4 VSS44 VSS141 K2
AF8 VCC41 VCCP22 T22 AD7 VSS45 VSS142 K5

1
D18 T6 AD9 K21 C18 C19 C27 C33 C22 C11 C28 C34 C20 C26
VCC42 VCCP23 VSS46 VSS143 TC1
D20 VCC43 VCCP24 U21 AD11 VSS47 VSS144 K23

SCD1U10V2MX-1

SCD1U10V2MX-1

SCD1U10V2MX-1

SCD1U10V2MX-1

SCD1U10V2MX-1

SCD1U10V2MX-1

SCD1U10V2MX-1

SCD1U10V2MX-1

SCD1U10V2MX-1

SCD1U10V2MX-1
D22 AD13 K26 ST100U6D3VM-U

2
VCC44 VSS48 VSS145
D6 VCC45 VCCQ0 P23 AD15 VSS49 VSS146 L3
D8 VCC46 VCCQ1 W4 AD17 VSS50 VSS147 L6
E17 VCC47 AD19 VSS51 VSS148 L22
E19 VCC48 VID0 E2 H_VID0 36 AD22 VSS52 VSS149 L25
E21 VCC49 VID1 F2 H_VID1 36 AD25 VSS53 VSS150 M1
E5 VCC50 VID2 F3 H_VID2 36 AE3 VSS54 VSS151 M4
E7 VCC51 VID3 G3 H_VID3 36 AE6 VSS55 VSS152 M5
E9 VCC52 VID4 G4 H_VID4 36 AE8 VSS56 VSS153 M21
F18 VCC53 VID5 H4 H_VID5 36 AE10 VSS57 VSS154 M24
F20 VCC54 AE12 VSS58 VSS155 N3
F22 VCC55 AE14 VSS59 VSS156 N6
F6 AE7 TP_VCCSENSE AE16 N22
VCC56 VCCSENSE VSS60 VSS157
F8 VCC57 AE18 VSS61 VSS158 N23
G21 AF6 TP_VSSSENSE AE20 N26
VCC58 VSSSENSE VSS62 VSS159
AE23 VSS63 VSS160 P2
1

AE26 VSS64 VSS161 P5

PZ47903 R34 R33 AF2 P21
54D9R2F 54D9R2F VSS65 VSS162
AF5 VSS66 VSS163 P24
DY DY AF9 VSS67 VSS164 R1
VCC_CORE_S0
AF11 R4
2

2 VSS68 VSS165 2
AF13 VSS69 VSS166 R6
AF15 VSS70 VSS167 R22
AF17 VSS71 VSS168 R25
AF19 VSS72 VSS169 T3
AF21 VSS73 VSS170 T5
Layout Note: AF24 T21
VCCSENSE and VSSSENSE lines VSS74 VSS171
B3 VSS75 VSS172 T23

1
should be of equal length. B6 T26 C16 C17 C21 C23 C29 C31 C32 C36 C37 C38 C39 C44 C276 C277 C279 C280 C281 C282 C283 C284
VSS76 VSS173
B9 VSS77 VSS174 U2

SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX

SC10U6D3V5MX
SC10U10V5ZY-L

SC10U10V5ZY-L

SC10U10V5ZY-L

SC10U10V5ZY-L

SC10U10V5ZY-L

SC10U10V5ZY-L

SC10U10V5ZY-L

SC10U10V5ZY-L

SC10U10V5ZY-L

SC10U10V5ZY-L
B12 U6

2
Layout Note: VSS78 VSS175
B16 VSS79 VSS176 U22
Provide a test point (with B19 U24
no stub) to connect a VSS80 VSS177
B22 VSS81 VSS178 V1
differential probe B25 V4
between VCCSENSE and VSS82 VSS179
VSSSENSE at the location
C1 VSS83 VSS180 V5 DY DY DY DY DY DY DY DY DY DY
C4 VSS84 VSS181 V21
where the two 54.9ohm C7 V25
resistors terminate the VSS85 VSS182
C10 VSS86 VSS183 W3
55 ohm transmission line. C13 W6
VSS87 VSS184
C15 VSS88 VSS185 W22
C18 VSS89 VSS186 W23
C21 VSS90 VSS187 W26
C24 VSS91 VSS188 Y2
D2 VSS92 VSS189 Y5
D5 VSS93 VSS190 Y21
D7 VSS94 VSS191 Y24
D9 VSS95
D11 VSS96
1 1

PZ47903
Wistron Corporation

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21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

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Taipei Hsien 221, Taiwan, R.O.C.

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Title

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CPU (2 of 2)

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Size Document Number Rev

in
A3
Leopard 3 -1

xa
he
Date: Monday, August 15, 2005 Sheet 5 of 41
A B C D E
 A B C D E

CORE_GMCH_S0
12/12 Trace 10 mil wide with 20 mil spacing
9,10,40,41 CORE_GMCH_S0
H_XRCOMP H_YRCOMP

VCCP_GMCH_S0
1

1
R69 R87
24D9R2F 24D9R2F 4,5,7,9,10,16,18,36,40,41 VCCP_GMCH_S0
2

2
4 4

VCCP_GMCH_S0 VCCP_GMCH_S0 Power On Sequencing

U17A
4 H_D#[63..0] H_A#[31..3] 4 VID
2

2
H_D#0 E4 G9 H_A#3 >3mS
R70 R89 H_D#1 HD0# HA3# H_A#4
E1 HD1# HA4# C9
54D9R2F 54D9R2F H_D#2 F4 E9 H_A#5
H_D#3 HD2# HA5# H_A#6
H7 HD3# HA6# B7 VR_ON
H_D#4 E2 A10 H_A#7
1

H_D#5 HD4# HA7# H_A#8

F1 HD5# HA8# F9
H_XSCOMP H_YSCOMP H_D#6 E3 D8 H_A#9 Vboot Vvid
H_D#7 HD6# HA9# H_A#10 Vboot
D3 HD7# HA10# B10
H_D#8 K7 E10 H_A#11 Vcc_core >100uS
H_D#9 HD8# HA11# H_A#12 <10uS
F2 HD9# HA12# G10
VCCP_GMCH_S0 VCCP_GMCH_S0 H_D#10 J7 D9 H_A#13
H_D#11 HD10# HA13# H_A#14
J8 HD11# HA14# E11
H_D#12 H6 F10 H_A#15 Vccp
HD12# HA15#
1

H_D#13 F3 G11 H_A#16

R67 R86 H_D#14 HD13# HA16# H_A#17
K8 HD14# HA17# G13
221R3F 221R3F H_D#15 H5 C10 H_A#18
H_D#16 HD15# HA18# H_A#19
H1 HD16# HA19# C11 Vcc_mch
H_D#17 H2 D11 H_A#20
2

H_XSWING H_YSWING H_D#18 HD17# HA20# H_A#21 10~30uS

K5 HD18# HA21# C12
H_D#19 K6 B13 H_A#22 MCH_PWERGD
HD19# HA22#
1

H_D#20 J4 A12 H_A#23

HD20# HA23#
2

R68 R88 H_D#21 G3 F12 H_A#24

3 100R2F C73 100R2F C91 H_D#22 HD21# HA24# H_A#25 3
H3 HD22# HA25# G12
SCD1U16V SCD1U16V H_D#23 J1 E12 H_A#26 CLK_ENABLE#
1

H_D#24 HD23# HA26# H_A#27 VCCP_GMCH_S0

L5 C13
2

H_D#25 HD24# HA27# H_A#28

K4 HD25# HA28# B11
H_D#26 J5 D13 H_A#29 3~10mS
HD26# HA29#

1
H_D#27 P7 A13 H_A#30 VGATE TO ICH6
H_D#28 HD27# HA30# H_A#31 R336
L7 HD28# HA31# F13
12/12 Trace 10 mil wide with 20 mil spacing H_D#29 J3 100R2F
H_D#30 HD29#
P5 HD30# HADS# F8 H_ADS# 4
H_D#31 L3 B9 H_ADSTB#0 4

2
H_D#32 HD31# HADSTB#0
U7 HD32# HADSTB#1 E13 H_ADSTB#1 4
H_D#33 V6 J11 H_VREF
Alviso Strapping Signals H_D#34
H_D#35
R6
R5
HD33#
HD34#
HVREF
HBNR# A5
D5
H_BNR# 4
HD35# HBPRI# H_BPRI# 4

1
H_D#36
and Configuration REV.NO. 1.0
REF. NO. 15577
page 183 H_D#37
H_D#38
P3
T8
HD36#
HD37#
HBREQ0#
HCPURST#
E7
H10
H_BREQ#0 4
H_CPURST# 4
C308
R337
200R2F
R7

2
H_D#39 HD38# SCD1U10V2KX
Pin Name Strap Description Configuration R8 HD39#
H_D#40 U8

HOST

2
H_D#41 HD40#
CFG[2:0] FSB Frequency Select 001 = FSB533 R4 HD41# HCLKINN AB1 CLK_MCH_BCLK# 3
101 = FSB400 H_D#42 T4 AB2
HD42# HCLKINP CLK_MCH_BCLK 3 CORE_GMCH_S0
others = Reversed H_D#43 T5
H_D#44 HD43#
R1 HD44# HDBSY# C6 H_DBSY# 4
H_D#45 T3 E6
HD45# HDEFER# H_DEFER# 4 H_DINV#[3..0] 4

1
H_D#46 V8 H8 H_DINV#0
H_D#47 HD46# HDINV#0 H_DINV#1 R391
CFG[4:3] Reserved U6 HD47# HDINV#1 K3
H_D#48 W6 T7 H_DINV#2 0R2-0
H_D#49 HD48# HDINV#2 H_DINV#3
CFG5 DMI x2 Select 0 = DMI x2 U3 HD49# HDINV#3 U5 DY
1 = DMI x4 (Default) H_D#50 V5 G6 H_DPWR# 4

2
2 H_D#51 HD50# HDPWR# H_DPWR# 2
W8 HD51# HDRDY# F7 H_DRDY# 4 H_DSTBN#[3..0] 4
CFG6 Reserved 0 = DDR2 H_D#52 W7 G4 H_DSTBN#0
H_D#53 HD52# HDSTBN#0 H_DSTBN#1
1 = DDR1 (Default) U2 HD53# HDSTBN#1 K1
H_D#54 U1 R3 H_DSTBN#2
H_D#55 HD54# HDSTBN#2 H_DSTBN#3
CFG7 CPU Strap 0 = Reserved Y5 HD55# HDSTBN#3 V3 H_DSTBP#[3..0] 4
1 = Dothan (Default) H_D#56 Y2 G5 H_DSTBP#0
H_D#57 HD56# HDSTBP#0 H_DSTBP#1
V4 HD57# HDSTBP#1 K2
CFG8 Reserved H_D#58 Y7 R2 H_DSTBP#2
H_D#59 HD58# HDSTBP#2 H_DSTBP#3
W1 HD59# HDSTBP#3 W4
CFG9 PCI Express Graphics 0 = Reserve Lanes H_D#60 W3 F6 TP_H_EDRDY# TP42 TPAD30
H_D#61 HD60# HEDRDY#
Lane Reversal 1 = Normal (Default) Y3 HD61# HHIT# D4 H_HIT# 4
H_D#62 Y6 D6
HD62# HHITM# H_HITM# 4
CFG[11:10] Reserved H_D#63 W2 B3
HD63# HLOCK# H_LOCK# 4
A11 TP_H_PCREQ#
HPCREQ# H_REQ#[4..0] 4
CFG[13:12] XOR/ALL Z test 00 = Reserved H_XRCOMP C1 A7 H_REQ#0 TP9 TPAD30
H_XSCOMP HXRCOMP HREQ#0 H_REQ#1
straps 01 = XOR mode enabled C2 HXSCOMP HREQ#1 D7
10 = All Z mode enabled H_XSWING D1 B8 H_REQ#2
H_YRCOMP HXSWING HREQ#2 H_REQ#3
11 = Normal Operation (Default) T1 HYRCOMP HREQ#3 C7
H_YSCOMP L1 A8 H_REQ#4
HYSCOMP HREQ#4 H_RS#[2..0] 4
CFG[15:14] Reversed H_YSWING P1 A4 H_RS#0
HYSWING HRS0# H_RS#1
HRS1# C5
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled B4 H_RS#2 0R0402-PAD
HRS2# H_CPUSLP#_GMCH
1 = Dynamic ODT Enabled (Default) HCPUSLP# G8 1 R311 2 H_CPUSLP# 4,16
HTRDY# B5 H_TRDY# 4
CFG17 Reversed For Banias/Celeron-M:R93=DUMMY
ALVISO-GM For Dothan A:R93=DUMMY
CFG18 GMCH core VCC 0 = 1.05V (Default)
Select 1 = 1.5V For Dothan B:R93=0R
1 1

CFG19 CPU VTT Select 0 = 1.05V (Default)

1 = 1.2V
Wistron Corporation
CFG20 Reversed 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
SDVOCRTL SDVO Present 0 = No SDVO device present (Default)
ALVISO-GM:71.0GMCH.08U
_DATA
1= SDVO device present
ALVISO-PM:71.0GMCH.0BU Title

ALVISO-GML:71.0GMCH.0JU GMCH (1 of 5)
NOTE: All strap signals are sampled with respect to the leading Size Document Number Rev
edge of the Alviso GMCH PWORK In signal. A3
Leopard 3 -1
Date: Monday, August 15, 2005 Sheet 6 of 41
A B C D E
 A B C D E

9,15,18,40 2D5V_S0 2D5V_S0

9,10,11,12,38,39,40,41 1D8V_S3 1D8V_S3

Alviso will provide SDVO_CTRLCLK
and CTRLDATA pulldowns on-die 5,9,17,18,21,38,39,41 1D5V_S0 1D5V_S0

6,9,10,40,41 CORE_GMCH_S0 CORE_GMCH_S0

11,40 DDR_VREF_S3 DDR_VREF_S3

U17B

17 DMI_TXN[3..0] 1D5V_S0
4 DMI_TXN0 AA31 G16 CFG0 4
DMI_TXN1 DMIRXN0 CFG0 CFG1 R534 U17G
AB35 DMIRXN1 CFG1 H13 Intel suggest NC Due to votusly DVO
DMI_TXN2 AC31 G14 1 2 CFG2 R71
DMI_TXN3 DMIRXN2 CFG2 CFG3 1KR2 TPAD30 TP46 SDVO_DAT PEG_COMP 2
AD35 DMIRXN3 CFG3 F16 H24 SDVOCTRL_DATA EXP_COMPI D36 1
CFG4 TPAD30 TP49 SDVO_CLK 24D9R2F

MISC
17 DMI_TXP[3..0] CFG4 F15 H25 SDVOCTRL_CLK EXP_ICOMPO D34
DMI_TXP0 Y31 G15 CFG5 AB29
DMIRXP0 CFG5 3 CLK_MCH_3GPLL# GCLKN
DMI_TXP1 AA35 E16 CFG6 AC29 E30
DMIRXP1 CFG6 3 CLK_MCH_3GPLL GCLKP EXP_RXN0
DMI_TXP2 AB31 D17 CFG7 F34
DMI_TXP3 DMIRXP2 CFG7 CFG8 EXP_RXN1
AC35 DMIRXP3 CFG8 J16 13 COMP_VGA A15 TVDAC_A EXP_RXN2 G30
D15 CFG9 C16 H34

DMI
17 DMI_RXN[3..0] CFG9 13 LUMA_VGA TVDAC_B EXP_RXN3

CFG/RSVD
DMI_RXN0 AA33 E15 CFG10 A17 J30
DMITXN0 CFG10 13 CRMA_VGA TVDAC_C EXP_RXN4
DMI_RXN1 AB37 D14 CFG11 1 2 TV_REFSET J18 K34
DMITXN1 CFG11 TV_REFSET EXP_RXN5

TV
DMI_RXN2 AC33 E14 CFG12 R373 4K99R2F B15 L30
DMI_RXN3 DMITXN2 CFG12 CFG13 R53 R54 R55 TV_IRTNA EXP_RXN6
AD37 DMITXN3 CFG13 H12 B16 TV_IRTNB EXP_RXN7 M34
C14 CFG14 150R2F 150R2F 150R2F B17 N30
17 DMI_RXP[3..0] CFG14 TV_IRTNC EXP_RXN8
DMI_RXP0 Y33 H15 CFG15 SD 0817 P34
DMI_RXP1 DMITXP0 CFG15 CFG16 EXP_RXN9
AA37 J15 R30

2
DMI_RXP2 DMITXP1 CFG16 CFG17 EXP_RXN10
AB33 DMITXP2 CFG17 H14 EXP_RXN11 T34
DMI_RXP3 AC37 G22 CFG18 U30
DMITXP3 CFG18 CFG19 EXP_RXN12
CFG19 G23 15 GMCH_DDCCLK EXP_RXN13 V34
D23 CFG20 W30
CFG20 15 GMCH_DDCDATA EXP_RXN14
AM33 G25 RSVD21 TP48 E24 Y34
11 CLK_DDR0 SM_CK0 RSVD21 Trace impendance 50ohm Less than 0.5", trace impendance 37.5ohm DDCCLK EXP_RXN15
AL1 G24 RSVD22 TP44 E23
11 CLK_DDR1 SM_CK1 RSVD22 DDCDATA
AE11 J17 RSVD23 TP43 E21 D30
SM_CK2 RSVD23 15 VGA_BLUE BLUE EXP_RXP0
AJ34 A31 RSVD24 TP11 D21 E34
11 CLK_DDR3 SM_CK3 RSVD24 15 VGA_GREEN BLUE# EXP_RXP1
AF6 A30 RSVD25 TP10 C20 F30

VGA
11 CLK_DDR4 SM_CK4 RSVD25 15 VGA_RED GREEN EXP_RXP2
AC10 D26 RSVD26 TP47 B20 G34
SM_CK5 RSVD26 RSVD27 TP45 GREEN# EXP_RXP3
RSVD27 D25 DY A19 RED EXP_RXP4 H30
11 CLK_DDR0# AN33 SM_CK0# DY1 2R59 150R2F B19 RED# EXP_RXP5 J34
3
11 CLK_DDR1# AK1 SM_CK1# DY1 2R57 150R2F VSYNC H21 VSYNC EXP_RXP6 K30 3
AE10 SM_CK2# 1 2R56 150R2F HSYNC G21 HSYNC EXP_RXP7 L34
AJ33 1 2R60 39R2J CRTIREF J20 M30

PCI-EXPRESS GRAPHICS
11 CLK_DDR3# SM_CK3# 13 VGA_VSYNC REFSET EXP_RXP8
11 CLK_DDR4# AF5 SM_CK4# 13 VGA_HSYNC 1 2R58 39R2J
EXP_RXP9 N34
AD10 SM_CK5# 1 2R374 255R2F EXP_RXP10 P30
EXP_RXP11 R34
11,12 M_CKE0_R# AP21 SM_CKE0 EXP_RXP12 T30
MUXING

11,12 M_CKE1_R# AM21 SM_CKE1 EXP_RXP13 U34

AH21 J23 LBKLT_CRTL E25 V30
11,12 M_CKE2_R# SM_CKE2 BM_BUSY# PM_BMBUSY# 17 LBKLT_CRTL EXP_RXP14
11,12 M_CKE3_R# AK21 SM_CKE3 EXT_TS0# J21 PM_EXTTS#0 31 BL_ON F25 LBKLT_EN EXP_RXP15 W34
EXT_TS1# H22 PM_EXTTS#1 LCTLA_CLK C23 LCTLA_CLK
AN16 F5 LCTLB_DATA C22 E32
PM

11,12 M_CS0_R# SM_CS0# THRMTRIP# PM_THRMTRIP-A# 4,16 LCTLB_DATA EXP_TXN0

AM14 AD30 LDDC_CLK F23 F36
11,12 M_CS1_R# SM_CS1# PWROK PWROK 20 LDDC_CLK EXP_TXN1
DDR

Layout Note: AH15 AE29 RST1# 1 2 LDDC_DATA F22 G32

11,12 M_CS2_R# SM_CS2# RSTIN# PLT_RST1# 19,21 LDDC_DATA EXP_TXN2
Route as short AG16 R406 100R2 F26 H36
as possible 11,12 M_CS3_R# SM_CS3# 14 LCDVDD_ON LVDD_EN EXP_TXN3
A24 LIBG C33 J32
DREF_CLKN DREFCLK# 3 LIBG EXP_TXN4
M_OCDCOMP0 AF22 A23 TPAD30 TP41 L_LVBG C31 K36
CLK

SM_OCDCOMP0 DREF_CLKP DREFCLK 3 LVBG EXP_TXN5

M_OCDCOMP1 AF16 C37 TPAD30 TP51 L_VREFH F28 L32
SM_OCDCOMP1 DREF_SSCLKN DREFSSCLK# 3 LVREFH EXP_TXN6
1

D37 TPAD30 TP50 L_VREFL F27 M36

DREF_SSCLKP DREFSSCLK 3 NO STUFF LVREFL EXP_TXN7
R405 R404

LVDS
11,12 M_ODT0 AP14 SM_ODT0 EXP_TXN8 N32
40D2R2F 40D2R2F AL15 AP37 GMCH_TP3 TP20 TPAD30 B30 P36
11,12 M_ODT1 SM_ODT1 NC1 2D5V_S0 14 TXACLK- LACLKN EXP_TXN9
AM11 AN37 GMCH_TP4 TP18 TPAD30 B29 R32
11,12 M_ODT2 SM_ODT2 NC2 14 TXACLK+ LACLKP EXP_TXN10
AN10 AP36 GMCH_TP5 TP19 TPAD30 RN39 C25 T36
11,12 M_ODT3 14 TXBCLK-
2

SM_ODT3 NC3 GMCH_TP6 TP15 TPAD30LCTLA_CLK 1 LBCLKN EXP_TXN11

NC4 AP2 8 14 TXBCLK+ C24 LBCLKP EXP_TXN12 U32
DDR_VREF_S3 M_RCOMPN AK10 AP1 GMCH_TP7 TP16 TPAD30LCTLB_DATA2 7 V36
M_RCOMPP SMRCOMPN NC5 GMCH_TP8 TP17 TPAD30LDDC_CLK 3 EXP_TXN13
AK11 SMRCOMPP NC6 AN1 6 14 TXAOUT0- B34 LADATAN0 EXP_TXN14 W32
AF37 B1 GMCH_TP9 TP7 TPAD30LDDC_DATA 4 5 B33 Y36
NC

SMVREF0 NC7 14 TXAOUT1- LADATAN1 EXP_TXN15

AD1 A2 GMCH_TP10 TP8 TPAD30 B32
SMVREF1 NC8 14 TXAOUT2- LADATAN2
SMXSLEW AE27 B37 GMCH_TP11 TP14 TPAD30 SRN2K2 D32
SMXSLEWIN NC9 EXP_TXP0
1

2 GMCH_TP12 TP13 TPAD30 2

AE28 SMXSLEWOUT NC10 A36 EXP_TXP1 E36
C109 SMYSLEW AF9 A37 GMCH_TP13 TP12 TPAD30 A34 F32
SMYSLEWIN NC11 14 TXAOUT0+ LADATAP0 EXP_TXP2
SCD1U10V2MX-1 AF10 BL_ON 1 2 R382 A33 G36
14 TXAOUT1+
2

SMYSLEWOUT 100KR2 LADATAP1 EXP_TXP3

14 TXAOUT2+ B31 LADATAP2 EXP_TXP4 H32
LBKLT_CRTL 1 2 R381 J36
100KR2 EXP_TXP5 2D5V_S0
ALVISO-GM 14 TXBOUT0- C29 LBDATAN0 EXP_TXP6 K32 When High 1K Ohm
2D5V_S0 LIBG 1 2 R379 D28 L36
1K5R2F 14 TXBOUT1- LBDATAN1 EXP_TXP7
When Low 2.2K Ohm 14 TXBOUT2- C27 LBDATAN2 EXP_TXP8 M32
R375 10KR2 N36 1 DY 2 R380 CFG18
PM_EXTTS#0 EXP_TXP9 DUMMY-R2
1 2 1 DY 2 R350 CFG3
14 TXBOUT0+ C28 LBDATAP0 EXP_TXP10 P32
DUMMY-R2 2 R376 CFG19
14 TXBOUT1+ D27 LBDATAP1 EXP_TXP11 R36 1 DY DUMMY-R2
1 DY 2 R348 CFG4
14 TXBOUT2+ C26 LBDATAP2 EXP_TXP12 T32
R378 10KR2 VCCP_GMCH_S0 Ref ALVISO EDS-1 Page 115 DUMMY-R2 2 R377 CFG20
PM_EXTTS#1 EXP_TXP13 U36 1 DY DUMMY-R2
1 2 1 DY 2 R343 CFG5
EXP_TXP14 V32
DUMMY-R2 3D3V_S0 W36
R571 CFG6 EXP_TXP15
1 2
2K2R2

1D8V_S3
FOR DDR2 1 DY 2 R352
DUMMY-R2
CFG7 ALVISO-GM
For Dothan-B
1

2 R340 CFG8 2D5V_S0

1 DY
1
2
R344 R49 R50 DUMMY-R2
10KR2 10KR2 1KR2 1 DY 2 R347 CFG9 RN38
1

DUMMY-R2 SRN4D7KJ
R403 1 DY 2 R349 CFG10
U14
2

80D6R2F DUMMY-R2
CFG2 1 DY 2 R52 CFG11
CPU_SEL0 3,4
4
3

CFG1 DUMMY-R2 LDDC_CLK 4 3

CPU_SEL1 3,4
2

M_RCOMPN CFG0 1 DY 2 R345 CFG12

M_RCOMPP DUMMY-R2 5 2
1 14 EDID_CLK 1
1 DY 2 R338 CFG13
1

DUMMY-R2 6 1 LDDC_DATA
CFG(2..1) FREQ.(MHz) 14 EDID_DAT
R429 R48 R51 1 DY 2 R346 CFG14
80D6R2F 4K7R2 4K7R2 10 400 DUMMY-R2 Wistron Corporation

om
00 533 2 R342 CFG15 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
DY DY 1 DY
11 Reserved
Strapping 2N7002S

l.c
DUMMY-R2 Taipei Hsien 221, Taiwan, R.O.C.
2

ai
1 DY 2 R339 CFG16

tm
DUMMY-R2 Title
2 R341 CFG17

ho
CFG2=0(R51):133MHZ 1 DY DUMMY-R2 CFG[17:3] have internal pullup resistors. GMCH (2 of 5)

f@
CFG2=1(R50):100MHZ Size Document Number Rev
CFG[19:18] have internal pulldown resistors

in
A3
Leopard 3 -1

xa
he
Date: Monday, August 15, 2005 Sheet 7 of 41
A B C D E
 A B C D E

4 4

U17C U17D

11 M_A_DATA[63..0] 11 M_B_DATA[63..0]
M_A_DATA0 AG35 AK15 M_B_DATA0 AE31 AJ15
SADQ0 SA_BS0# M_A_BS0# 11,12 SBDQ0 SB_BS0# M_B_BS0# 11,12
M_A_DATA1 AH35 AK16 M_B_DATA1 AE32 AG17
SADQ1 SA_BS1# M_A_BS1# 11,12 SBDQ1 SB_BS1# M_B_BS1# 11,12
M_A_DATA2 AL35 AL21 M_B_DATA2 AG32 AG21
SADQ2 SA_BS2# M_A_BS2# 11,12 SBDQ2 SB_BS2# M_B_BS2# 11,12
M_A_DATA3 AL37 M_B_DATA3 AG36
SADQ3 M_A_SDM[7..0] 11 SBDQ3 M_B_SDM[7..0] 11
M_A_DATA4 AH36 AJ37 M_A_SDM0 M_B_DATA4 AE34 AF32 M_B_SDM0
M_A_DATA5 SADQ4 SA_DM0 M_A_SDM1 M_B_DATA5 SBDQ4 SB_DM0 M_B_SDM1
AJ35 SADQ5 SA_DM1 AP35 AE33 SBDQ5 SB_DM1 AK34
M_A_DATA6 AK37 AL29 M_A_SDM2 M_B_DATA6 AF31 AK27 M_B_SDM2
M_A_DATA7 SADQ6 SA_DM2 M_A_SDM3 M_B_DATA7 SBDQ6 SB_DM2 M_B_SDM3
AL34 SADQ7 SA_DM3 AP24 AF30 SBDQ7 SB_DM3 AK24
M_A_DATA8 AM36 AP9 M_A_SDM4 M_B_DATA8 AH33 AJ10 M_B_SDM4
M_A_DATA9 SADQ8 SA_DM4 M_A_SDM5 M_B_DATA9 SBDQ8 SB_DM4 M_B_SDM5
AN35 SADQ9 SA_DM5 AP4 AH32 SBDQ9 SB_DM5 AK5
M_A_DATA10 AP32 AJ2 M_A_SDM6 M_B_DATA10 AK31 AE7 M_B_SDM6
M_A_DATA11 SADQ10 SA_DM6 M_A_SDM7 M_B_DATA11 SBDQ10 SB_DM6 M_B_SDM7
AM31 SADQ11 SA_DM7 AD3 AG30 SBDQ11 SB_DM7 AB7
M_A_DATA12 AM34 M_B_DATA12 AG34
SADQ12 M_A_DQS[7..0] 11 SBDQ12 M_B_DQS[7..0] 11
M_A_DATA13 AM35 AK36 M_A_DQS0 M_B_DATA13 AG33 AF34 M_B_DQS0
M_A_DATA14 SADQ13 SA_DQS0 M_A_DQS1 M_B_DATA14 SBDQ13 SB_DQS0 M_B_DQS1
AL32 SADQ14 SA_DQS1 AP33 AH31 SBDQ14 SB_DQS1 AK32
M_A_DATA15 AM32 AN29 M_A_DQS2 M_B_DATA15 AJ31 AJ28 M_B_DQS2
M_A_DATA16 SADQ15 SA_DQS2 M_A_DQS3 M_B_DATA16 SBDQ15 SB_DQS2 M_B_DQS3
AN31 SADQ16 SA_DQS3 AP23 AK30 SBDQ16 SB_DQS3 AK23
M_A_DATA17 AP31 AM8 M_A_DQS4 M_B_DATA17 AJ30 AM10 M_B_DQS4
M_A_DATA18 SADQ17 SA_DQS4 M_A_DQS5 M_B_DATA18 SBDQ17 SB_DQS4 M_B_DQS5
AN28 SADQ18 SA_DQS5 AM4 AH29 SBDQ18 SB_DQS5 AH6
M_A_DATA19 AP28 AJ1 M_A_DQS6 M_B_DATA19 AH28 AF8 M_B_DQS6
M_A_DATA20 SADQ19 SA_DQS6 M_A_DQS7 M_B_DATA20 SBDQ19 SB_DQS6 M_B_DQS7
AL30 SADQ20 SA_DQS7 AE5 AK29 SBDQ20 SB_DQS7 AB4
M_A_DATA21 AM30 M_B_DATA21 AH30
SADQ21 M_A_DQS#[7..0] 11 SBDQ21 M_B_DQS#[7..0] 11
M_A_DATA22 AM28 AK35 M_A_DQS#0 M_B_DATA22 AH27 AF35 M_B_DQS#0
3 M_A_DATA23 SADQ22 SA_DQS0# M_A_DQS#1 M_B_DATA23 SBDQ22 SB_DQS0# M_B_DQS#1 3
AL28 SADQ23 SA_DQS1# AP34 AG28 SBDQ23 SB_DQS1# AK33
DDR SYSTEM MEMORY A

M_A_DATA24 AP27 AN30 M_A_DQS#2 M_B_DATA24 AF24 AK28 M_B_DQS#2

M_A_DATA25 SADQ24 SA_DQS2# M_A_DQS#3 M_B_DATA25 SBDQ24 SB_DQS2# M_B_DQS#3
AM27 AN23 AG23 AJ23

DDR SYSTEM MEMORY B

M_A_DATA26 SADQ25 SA_DQS3# M_A_DQS#4 M_B_DATA26 SBDQ25 SB_DQS3# M_B_DQS#4
AM23 SADQ26 SA_DQS4# AN8 AJ22 SBDQ26 SB_DQS4# AL10
M_A_DATA27 AM22 AM5 M_A_DQS#5 M_B_DATA27 AK22 AH7 M_B_DQS#5
M_A_DATA28 SADQ27 SA_DQS5# M_A_DQS#6 M_B_DATA28 SBDQ27 SB_DQS5# M_B_DQS#6
AL23 SADQ28 SA_DQS6# AH1 AH24 SBDQ28 SB_DQS6# AF7
M_A_DATA29 AM24 AE4 M_A_DQS#7 M_B_DATA29 AH23 AB5 M_B_DQS#7
M_A_DATA30 SADQ29 SA_DQS7# M_B_DATA30 SBDQ29 SB_DQS7#
AN22 SADQ30 M_A_A[13..0] 11,12 AG22 SBDQ30 M_B_A[13..0] 11,12
M_A_DATA31 AP22 AL17 M_A_A0 M_B_DATA31 AJ21 AH17 M_B_A0
M_A_DATA32 SADQ31 SA_MA0 M_A_A1 M_B_DATA32 SBDQ31 SB_MA0 M_B_A1
AM9 SADQ32 SA_MA1 AP17 AG10 SBDQ32 SB_MA1 AK17
M_A_DATA33 AL9 AP18 M_A_A2 M_B_DATA33 AG9 AH18 M_B_A2
M_A_DATA34 SADQ33 SA_MA2 M_A_A3 M_B_DATA34 SBDQ33 SB_MA2 M_B_A3
AL6 SADQ34 SA_MA3 AM17 AG8 SBDQ34 SB_MA3 AJ18
M_A_DATA35 AP7 AN18 M_A_A4 M_B_DATA35 AH8 AK18 M_B_A4
M_A_DATA36 SADQ35 SA_MA4 M_A_A5 M_B_DATA36 SBDQ35 SB_MA4 M_B_A5
AP11 SADQ36 SA_MA5 AM18 AH11 SBDQ36 SB_MA5 AJ19
M_A_DATA37 AP10 AL19 M_A_A6 M_B_DATA37 AH10 AK19 M_B_A6
M_A_DATA38 SADQ37 SA_MA6 M_A_A7 M_B_DATA38 SBDQ37 SB_MA6 M_B_A7
AL7 SADQ38 SA_MA7 AP20 AJ9 SBDQ38 SB_MA7 AH19
M_A_DATA39 AM7 AM19 M_A_A8 M_B_DATA39 AK9 AJ20 M_B_A8
M_A_DATA40 SADQ39 SA_MA8 M_A_A9 M_B_DATA40 SBDQ39 SB_MA8 M_B_A9
AN5 SADQ40 SA_MA9 AL20 AJ7 SBDQ40 SB_MA9 AH20
M_A_DATA41 AN6 AM16 M_A_A10 M_B_DATA41 AK6 AJ16 M_B_A10
M_A_DATA42 SADQ41 SA_MA10 M_A_A11 M_B_DATA42 SBDQ41 SB_MA10 M_B_A11
AN3 SADQ42 SA_MA11 AN20 AJ4 SBDQ42 SB_MA11 AG18
M_A_DATA43 AP3 AM20 M_A_A12 M_B_DATA43 AH5 AG20 M_B_A12
M_A_DATA44 SADQ43 SA_MA12 M_A_A13 M_B_DATA44 SBDQ43 SB_MA12 M_B_A13
AP6 SADQ44 SA_MA13 AM15 AK8 SBDQ44 SB_MA13 AG15
M_A_DATA45 AM6 M_B_DATA45 AJ8
M_A_DATA46 SADQ45 M_B_DATA46 SBDQ45
AL4 SADQ46 SA_CAS# AN15 M_A_CAS# 11,12 AJ5 SBDQ46
M_A_DATA47 AM3 AP16 M_B_DATA47 AK4 AH14
SADQ47 SA_RAS# M_A_RAS# 11,12 SBDQ47 SB_CAS# M_B_CAS# 11,12
M_A_DATA48 AK2 AF29 GMCH_TP48 TP55 M_B_DATA48 AG5 AK14
SADQ48 SA_RCVENIN# SBDQ48 SB_RAS# M_B_RAS# 11,12
M_A_DATA49 AK3 AF28 GMCH_TP49 TP54 M_B_DATA49 AG4 AF15 GMCH_TP50 TP53
M_A_DATA50 SADQ49 SA_RCVENOUT# M_B_DATA50 SBDQ49 SB_RCVENIN# GMCH_TP51 TP52
AG2 SADQ50 SA_WE# AP15 M_A_WE# 11,12 AD8 SBDQ50 SB_RCVENOUT# AF14
M_A_DATA51 AG1 M_B_DATA51 AD9 AH16
2 SADQ51 SBDQ51 SB_WE# M_B_WE# 11,12 2
M_A_DATA52 AL3 M_B_DATA52 AH4
M_A_DATA53 SADQ52 M_B_DATA53 SBDQ52
AM2 SADQ53 AG6 SBDQ53
M_A_DATA54 AH3 M_B_DATA54 AE8
M_A_DATA55 SADQ54 M_B_DATA55 SBDQ54
AG3 SADQ55 AD7 SBDQ55
M_A_DATA56 AF3 M_B_DATA56 AC5
M_A_DATA57 SADQ56 M_B_DATA57 SBDQ56
AE3 SADQ57 AB8 SBDQ57
M_A_DATA58 AD6 M_B_DATA58 AB6
M_A_DATA59 SADQ58 M_B_DATA59 SBDQ58
AC4 SADQ59 AA8 SBDQ59
M_A_DATA60 AF2 M_B_DATA60 AC8
M_A_DATA61 SADQ60 M_B_DATA61 SBDQ60
AF1 SADQ61 AC7 SBDQ61
M_A_DATA62 AD4 M_B_DATA62 AA4
M_A_DATA63 SADQ62 M_B_DATA63 SBDQ62
AD5 SADQ63 AA5 SBDQ63

ALVISO-GM ALVISO-GM

1 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
GMCH (3 of 5)
Size Document Number Rev
A3
Leopard 3 -1
Date: Tuesday, July 12, 2005 Sheet 8 of 41
A B C D E
 A B C D E

1D5V_S0 1D5V_DLVDS_S0
1D5V_S0 G10
R354 1 2
1D5V_TVDAC_S0 1 2

1
0R3-U GAP-CLOSE-PWR 1D5V_DDRDLL_S0 1D5V_S0
C299 C59 C58 G29
SCD1U10V2MX-1 SCD1U10V2MX-1 SC10U10V5ZY-L 1 2

2
3D3V_S0 3D3V_VGA_S0

1
R36 D2 1D5V_S0 GAP-CLOSE-PWR
1 2TVDAC_PWR1 2 C340 C131
2D5V_S0 2D5V_ALVDS_S0 SCD1U10V2MX-1 ST100U6D3VM-U

2
10R2 SSM5818SL R353 G12
1D5V_QTVDAC_S0 1 2 1 2

1
4 0R3-U 4

1
C300 GAP-CLOSE-PWR
R35 R313 SCD1U10V2MX-1 C63 C62

2
1 2 1 2 3D3V_ATVBG_S0 SCD1U10V2MX-1 SCD01U16V3KX

2
1
0R3-U 1D5V_PCIE_S0 1D5V_S0
0R3-U C310 G51
SCD1U10V2MX-1 2D5V_TVDAC_S0 2D5V_S0 1 2
2

G9 2D5V_S0 2D5V_TXLVDS_S0

1
1 2 G11 GAP-CLOSE-PWR
1 2 C343 C92 TC16

1
R312 GAP-CLOSE-PWR SC10U10V5ZY-L SC10U10V5ZY-L ST100U6D3VM-U

2
1

1
3D3V_VGA_S0 1 2 3D3V_TVDACC_S0 C54 C55 GAP-CLOSE-PWR DY
1

SCD1U10V2MX-1SC10U10V5ZY-L C61 C60

2
0R3-U C309 SCD1U10V2MX-1 SC4D7U10V5ZY

2
SCD1U10V2MX-1
2

1D5V_3GPLL_S0 1D5V_S0
1

1
R355 G50
C461 1 2 3D3V_TVDACB_S0 C127 FOR DDR2 C123 1 2
1

SCD1U10V2MX-1 SCD1U10V2MX-1
2

V1.8_DDR_CAP1 2

1
SC10U6D3V5MX 0R3-U C311 1D8V_S3 GAP-CLOSE-PWR
SCD1U10V2MX-1 Note: All VCCSM C342 C330
2

pins shorted Note: All VCCSM SCD1U10V2MX-1 SC10U10V5ZY-L

2
1

1
internally TC7 pins shorted

1
1D5V_DLVDS_S0 C126 ST150U4VBM-L1 internally C122
SCD1U10V2MX-1 C351 C339 SCD1U10V2MX-1

V1.8_DDR_CAP2 2

2
R356 SC10U10V5ZY-L SC10U10V5ZY-L

2
1 2 3D3V_TVDACA_S0 1 2 C125 1 2 C124

AP29 V1.8_DDR_CAP5

V1.8_DDR_CAP4
V1.8_DDR_CAP3
1

2D5V_ALVDS_S0 2D5V_TXLVDS_S0 2D5V_3GBG_S0 2D5V_S0

AP8 V1.8_DDR_CAP6
3 0R3-U C314 SCD1U10V2MX-1 SCD1U10V2MX-1 G13 3
SCD1U10V2MX-1 1 2
2

1
C74 GAP-CLOSE-PWR
SCD1U10V2MX-1

2
AM37

AM26

AM25

AM13

AM12
AG26

AG25

AG13

AG12
AH37

AD28
AD27
AC27

AN26

AH26

AN25

AH25

AN13

AH13

AN12

AH12

AD11
AC11
AP26

AK26

AE26
AP25

AK25

AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AE17
AE16
AE15
AE14
AP13

AK13

AE13
AP12

AK12

AE12

AB11
AB10

AP19

AE37
AF26

AF25

AF13

AF12

AF20

AF19
AF18
AL26

AL25

AL13

AL12
AJ26

AJ25

AJ13

AJ12

W37
AM1
G18

G37
AB9

AE1
D18
C18

H18

D19
H17

U37
R37
N37
E17

E18

B26
B25
A25

A35

B22
B21
A21

B28
A28
A27

Y29
Y28
Y27
F17

F18

F37
L37
J37
U17E
3D3V_S0 2D5V_CRTDAC_S0
VCCA_LVDS

VCCA_3GBG
VSSA_3GBG
VCCA_TVDACA0
VCCA_TVDACA1
VCCA_TVDACB0
VCCA_TVDACB1
VCCA_TVDACC0
VCCA_TVDACC1

VCCA_TVBG
VSSA_TVBG

VCCHV0
VCCHV1
VCCHV2

VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64

VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2
VCCD_TVDAC

VCCD_LVDS0
VCCD_LVDS1
VCCD_LVDS2

VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3

VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6

VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2
VCCDQ_TVDAC

U66

VOUT 2
3 VIN
1

1 C466
GND
1

POWER

VCCA_CRTDAC0
VCCA_CRTDAC1
C465 SC10U6D3V5MX
2

VSSA_CRTDAC
SCD1U10V2MX-1 APL5308-25AC-TR

VCCH_MPLL1
VCCH_MPLL0
VCCA_DPLLA
VCCA_DPLLB
2

VCCA_MPLL
VCCA_HPLL

VCC_SYNC
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48

M11 VTT10
L11 VTT11
K11 VTT12
W10 VTT13
V10 VTT14
U10 VTT15
T10 VTT16
R10 VTT17
P10 VTT18
N10 VTT19
M10 VTT20
K10 VTT21
J10 VTT22
Y9 VTT23
W9 VTT24
U9 VTT25
R9 VTT26
P9 VTT27
N9 VTT28
M9 VTT29
L9 VTT30
J9 VTT31
N8 VTT32
M8 VTT33
N7 VTT34
M7 VTT35
N6 VTT36
M6 VTT37
A6 VTT38
N5 VTT39
M5 VTT40
N4 VTT41
M4 VTT42
N3 VTT43
M3 VTT44
N2 VTT45
M2 VTT46
B2 VTT47
V1 VTT48
N1 VTT49
M1 VTT50
G1 VTT51
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9

K13 VTT0
J13 VTT1
K12 VTT2
W11 VTT3
V11 VTT4
U11 VTT5
T11 VTT6
R11 VTT7
P11 VTT8
N11 VTT9

VCCP_GMCH_CAP2
1VCCP_GMCH_CAP1
T29
R29
N29
M29
K29
J29
V28
U28
T28
R28
P28
N28
M28
L28
K28
J28
H28
G28
V27
U27
T27
R27
P27
N27
M27
L27
K27
J27
H27
K26
H26
K25
J25
K24
K23
K22
K21
W20
U20
T20
K20
V19
U19
K19
W18
V18
T18
K18
K17

AC2
AC1
B23
C35
AA1
AA2

F19
E19
G19

H20

VCCP_GMCH_CAP3

VCCP_GMCH_CAP4
2 2
CORE_GMCH_S0

1
C53 C52
GMCH_CORE_VCC SCD47U16V3ZY SCD47U16V3ZY

1
2D5V_CRTDAC_S0
1

1
R357 R560 C90
C341 C325 C326 C329 C328 C327 1D5V_HMPLL_S0 1 2 1 DY 0R3-U
2 C71
2D5V_S0

2
SC10U10V5ZY-L SC10U10V5ZY-L
SC10U10V5ZY-L SCD1U10V2MX-1SCD1U10V2MX-1SCD1U10V2MX-1 0R5J SCD22U16V3ZY SCD22U16V3ZY
2

2
1

1
C312
1 2 1D5V_DPLLA_S0 C459 C301 VCCP_GMCH_S0
L4 IND-D1UH SCD022U16V SC22U10V6MX SCD1U10V2MX-1

2
1

1D5V_S0 VCCP_GMCH_S0
C56 C57 DY
SC10U6D3V5MX SCD1U10V2MX-1 R358 D22
DY
2

1
1 2 1 2
1

1
1D5V_S0 10R2 C324 C323
G43 1 2 1D5V_DPLLB_S0 C313 SSM5818SL SC4D7U10V5ZY SC4D7U10V5ZY

2
GAP-CLOSE-PWR L22 IND-D1UH SCD1U10V2MX-1
1D5V_S0 5,7,17,18,21,38,39,41

2
1

1
2

2D5V_S0 C302 C315 Route VSSA_CRTDAC gnd from GMCH to

SC10U6D3V5MX SCD1U10V2MX-1 decoupling cap ground lead and then
DY
2

connect to the gnd plane.

2D5V_S0 7,15,18,40
1D8V_S3 1 2 1D5V_HPLL_S0
L14 IND-D1UH
1 1
1

1D8V_S3 7,10,11,12,38,39,40,41 Layout Notes: VSSA_CRTDAC

C108 C110
VCCP_GMCH_S0 SC10U6D3V5MX SCD1U10V2MX-1 VCCP_GMCH_S0 Route caps within 250mil
DY Wistron Corporation
2

of Alviso. Route FB

om
within 3" of Alviso. 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
VCCP_GMCH_S0 4,5,6,7,10,16,18,36,40,41

l.c
1 2 1D5V_MPLL_S0 Taipei Hsien 221, Taiwan, R.O.C.
1

IND-D1UH

ai
L13
1

tm
CORE_GMCH_S0 C72 C88 C89 Title
C107 C111 SCD1U10V2MX-1 ST100U6D3VM-U SC10U10V6ZY-U

ho
GMCH (4 of 5)
2

SC10U6D3V5MX SCD1U10V2MX-1
DY

f@
CORE_GMCH_S0 6,10,40,41
2

Size Document Number Rev

in
A3
Leopard 3 -1

xa
he
Date: Tuesday, August 16, 2005 Sheet 9 of 41
A B C D E
 1
2
3
4

U17F

ALVISO-GM
B36 VSSALVDS
VSS267 AL24
VSS266 AN24

A
A

Y1 VSS271 VSS265 A26

D2 VSS270 VSS264 E26
G2 VSS269 VSS263 G26
J2 J26

U17H
VSS268 VSS262
L2 VSS260 VSS261 B27

ALVISO-GM
P2 VSS259 VSS129 E27
T2 VSS258 VSS128 G27
VCCSM_NCTF31 AB12 V2 VSS257 VSS127 W27
VCCSM_NCTF30 AC12 AD2 VSS256 VSS126 AA27
VCCSM_NCTF29 AD12 AE2 VSS255 VSS125 AB27

1D8V_S3
VCCSM_NCTF28 AB13 AH2 VSS254 VSS124 AF27
VCCSM_NCTF27 AC13 AL2 VSS253 VSS123 AG27
VCCSM_NCTF26 AD13 AN2 VSS252 VSS122 AJ27
VCCSM_NCTF25 AC14 A3 VSS251 VSS121 AL27
VCCSM_NCTF24 AD14 C3 VSS250 VSS120 AN27
VCCSM_NCTF23 AC15 AA3 VSS249 VSS119 E28
VCCSM_NCTF22 AD15 AB3 VSS248 VSS118 W28
VCCSM_NCTF21 AC16 AC3 VSS247 VSS117 AA28
VCCSM_NCTF20 AD16 AJ3 VSS246 VSS116 AB28
VCCSM_NCTF19 AC17 C4 VSS245 VSS115 AC28
VCCSM_NCTF18 AD17 H4 VSS244 VSS114 A29
AC18 L4 D29

VCCP_GMCH_S0
VCCSM_NCTF17 VSS243 VSS113
VCCSM_NCTF16 AD18 P4 VSS242 VSS112 E29
VCCSM_NCTF15 AC19 U4 VSS241 VSS111 F29
VCCSM_NCTF14 AD19 Y4 VSS240 VSS110 G29
VCCSM_NCTF13 AC20 AF4 VSS239 VSS109 H29
VCCSM_NCTF12 AD20 AN4 VSS238 VSS108 L29
L12 AC21 E5 P29

FOR DDR2
VTT_NCTF17 VCCSM_NCTF11 VSS237 VSS107
M12 VTT_NCTF16 VCCSM_NCTF10 AD21 W5 VSS236 VSS106 U29
N12 VTT_NCTF15 VCCSM_NCTF9 AC22 AL5 VSS235 VSS105 V29
P12 VTT_NCTF14 VCCSM_NCTF8 AD22 AP5 VSS234 VSS104 W29
R12 VTT_NCTF13 VCCSM_NCTF7 AC23 B6 VSS233 VSS103 AA29
T12 AD23 J6 AD29

B
B

VTT_NCTF12 VCCSM_NCTF6 VSS232 VSS102

U12 VTT_NCTF11 VCCSM_NCTF5 AC24 L6 VSS231 VSS101 AG29
V12 VTT_NCTF10 VCCSM_NCTF4 AD24 P6 VSS230 VSS100 AJ29
W12 VTT_NCTF9 VCCSM_NCTF3 AC25 T6 VSS229 VSS99 AM29
L13 VTT_NCTF8 VCCSM_NCTF2 AD25 AA6 VSS228 VSS98 C30
M13 VTT_NCTF7 VCCSM_NCTF1 AC26 AC6 VSS227 VSS97 Y30
N13 VTT_NCTF6 VCCSM_NCTF0 AD26 AE6 VSS226 VSS96 AA30
P13 VTT_NCTF5 AJ6 VSS225 VSS95 AB30
R13 VTT_NCTF4 VCC_NCTF78 L17 G7 VSS224 VSS94 AC30
T13 VTT_NCTF3 VCC_NCTF77 M17 V7 VSS223 VSS93 AE30
U13 VTT_NCTF2 VCC_NCTF76 N17 AA7 VSS222 VSS92 AP30
V13 VTT_NCTF1 VCC_NCTF75 P17 AG7 VSS221 VSS91 D31
W13 VTT_NCTF0 VCC_NCTF74 T17 AK7 VSS220 VSS90 E31
VCC_NCTF73 U17 AN7 VSS219 VSS89 F31
VCC_NCTF72 V17 C8 VSS218 VSS88 G31
VCC_NCTF71 W17 E8 VSS217 VSS87 H31
VCC_NCTF70 L18 L8 VSS216 VSS86 J31
VCC_NTTF69 M18 P8 VSS215 VSS85 K31
Y12 VSS_NCTF68 VCC_NCTF68 N18 Y8 VSS214 VSS84 L31
AA12 VSS_NCTF67 VCC_NCTF67 P18 AL8 VSS213 VSS83 M31
Y13 VSS_NCTF66 VCC_NCTF66 R18 A9 VSS212 VSS82 N31
AA13 VSS_NCTF65 VCC_NCTF65 Y18 H9 VSS211 VSS81 P31
L14 VSS_NCTF64 VCC_NCTF64 L19 K9 VSS210 VSS80 R31
M14 VSS_NCTF63 VCC_NCTF63 M19 T9 VSS209 VSS79 T31
N14 VSS_NCTF62 VCC_NCTF62 N19 V9 VSS208 VSS78 U31
P14 VSS_NCTF61 VCC_NCTF61 P19 AA9 VSS207 VSS77 V31
R14 VSS_NCTF60 VCC_NCTF60 R19 AC9 VSS206 VSS76 W31
T14 VSS_NCTF59 VCC_NCTF59 Y19 AE9 VSS205 VSS75 AD31
U14 VSS_NCTF58 VCC_NCTF58 L20 AH9 VSS204 VSS74 AG31
V14 VSS_NCTF57 VCC_NCTF57 M20 AN9 VSS203 VSS73 AL31
W14 N20 D10 A32
VSS

VSS_NCTF56 VCC_NCTF56 VSS202 VSS72

Y14 VSS_NCTF55 VCC_NCTF55 P20 L10 VSS201 VSS71 C32
AA14 VSS_NCTF54 VCC_NCTF54 R20 Y10 VSS200 VSS70 Y32

C
C

AB14 Y20 AA10 AA32

NCTF

VSS_NCTF53 VCC_NCTF53 VSS199 VSS69

L15 VSS_NCTF52 VCC_NCTF52 L21 F11 VSS198 VSS68 AB32
M15 VSS_NCTF51 VCC_NCTF51 M21 H11 VSS197 VSS67 AC32
N15 VSS_NCTF50 VCC_NCTF50 N21 Y11 VSS196 VSS66 AD32
P15 VSS_NCTF49 VCC_NCTF49 P21 AA11 VSS195 VSS65 AJ32
R15 VSS_NCTF48 VCC_NCTF48 T21 AF11 VSS194 VSS64 AN32
T15 VSS_NCTF47 VCC_NCTF47 U21 AG11 VSS193 VSS63 D33
U15 VSS_NCTF46 VCC_NCTF46 V21 AJ11 VSS192 VSS62 E33
V15 VSS_NCTF45 VCC_NCTF45 W21 AL11 VSS191 VSS61 F33
W15 VSS_NCTF44 VCC_NCTF44 L22 AN11 VSS190 VSS60 G33
Y15 VSS_NCTF43 VCC_NCTF43 M22 B12 VSS189 VSS59 H33
AA15 VSS_NCTF42 VCC_NCTF42 N22 D12 VSS188 VSS58 J33
AB15 VSS_NCTF41 VCC_NCTF41 P22 J12 VSS187 VSS57 K33
L16 VSS_NCTF40 VCC_NCTF40 R22 A14 VSS186 VSS56 L33
M16 VSS_NCTF39 VCC_NCTF39 T22 B14 VSS185 VSS55 M33
N16 VSS_NCTF38 VCC_NCTF38 U22 F14 VSS184 VSS54 N33
P16 VSS_NCTF37 VCC_NCTF37 V22 J14 VSS183 VSS53 P33
R16 VSS_NCTF36 VCC_NCTF36 W22 K14 VSS182 VSS52 R33
T16 VSS_NCTF35 VCC_NCTF35 L23 AG14 VSS181 VSS51 T33
U16 VSS_NCTF34 VCC_NCTF34 M23 AJ14 VSS180 VSS50 U33
V16 VSS_NCTF33 VCC_NCTF33 N23 AL14 VSS179 VSS49 V33
W16 VSS_NCTF32 VCC_NCTF32 P23 AN14 VSS178 VSS48 W33
Y16 VSS_NCTF31 VCC_NCTF31 R23 C15 VSS177 VSS47 AD33
AA16 VSS_NCTF30 VCC_NCTF30 T23 K15 VSS176 VSS46 AF33
AB16 VSS_NCTF29 VCC_NCTF29 U23 A16 VSS175 VSS45 AL33
R17 VSS_NCTF28 VCC_NCTF28 V23 D16 VSS174 VSS44 C34
Y17 VSS_NCTF27 VCC_NCTF27 W23 H16 VSS173 VSS43 AA34
AA17 VSS_NCTF26 VCC_NCTF26 L24 K16 VSS172 VSS42 AB34
AB17 VSS_NCTF25 VCC_NCTF25 M24 AL16 VSS171 VSS41 AC34
AA18 VSS_NCTF24 VCC_NCTF24 N24 C17 VSS170 VSS40 AD34
AB18 VSS_NCTF23 VCC_NCTF23 P24 G17 VSS169 VSS39 AH34
AA19 VSS_NCTF22 VCC_NCTF22 R24 AF17 VSS168 VSS38 AN34
AB19 VSS_NCTF21 VCC_NCTF21 T24 AJ17 VSS167 VSS37 B35
D
D

AA20 VSS_NCTF20 VCC_NCTF20 U24 AN17 VSS166 VSS36 D35

AB20 VSS_NCTF19 VCC_NCTF19 V24 A18 VSS165 VSS35 E35
R21 VSS_NCTF18 VCC_NCTF18 W24 B18 VSS164 VSS34 F35
Y21 VSS_NCTF17 VCC_NCTF17 L25 U18 VSS163 VSS33 G35
AA21 VSS_NCTF16 VCC_NCTF16 M25 AL18 VSS162 VSS32 H35
AB21 VSS_NCTF15 VCC_NCTF15 N25 C19 VSS161 VSS31 J35
Y22 VSS_NCTF14 VCC_NCTF14 P25 H19 VSS160 VSS30 K35
AA22 VSS_NCTF13 VCC_NCTF13 R25 J19 VSS159 VSS29 L35
AB22 VSS_NCTF12 VCC_NCTF12 T25 T19 VSS158 VSS28 M35
Y23 VSS_NCTF11 VCC_NCTF11 U25 W19 VSS157 VSS27 N35
AA23 VSS_NCTF10 VCC_NCTF10 V25 AG19 VSS156 VSS26 P35
AB23 VSS_NCTF9 VCC_NCTF9 W25 AN19 VSS155 VSS25 R35
A3

Y24 VSS_NCTF8 VCC_NCTF8 L26 A20 VSS154 VSS24 T35

Title

Size

AA24 VSS_NCTF7 VCC_NCTF7 M26 D20 VSS153 VSS23 U35

AB24 VSS_NCTF6 VCC_NCTF6 N26 E20 VSS152 VSS22 V35
Y25 VSS_NCTF5 VCC_NCTF5 P26 F20 VSS151 VSS21 W35
AA25 VSS_NCTF4 VCC_NCTF4 R26 G20 VSS150 VSS20 Y35
AB25 VSS_NCTF3 VCC_NCTF3 T26 V20 VSS149 VSS19 AE35
Y26 VSS_NCTF2 VCC_NCTF2 U26 AK20 VSS148 VSS18 C36
AA26 VSS_NCTF1 VCC_NCTF1 V26 C21 VSS147 VSS17 AA36
AB26 VSS_NCTF0 VCC_NCTF0 W26 F21 VSS146 VSS16 AB36
AF21 VSS145 VSS15 AC36
AN21 AD36
Document Number

VSS144 VSS14
A22 AE36
Date: Tuesday, July 12, 2005

VSS143 VSS13
D22 VSS142 VSS12 AF36
E22 VSS141 VSS11 AJ36
J22 VSS140 VSS10 AL36
AH22 AN36
CORE_GMCH_S0

VSS139 VSS9
AL22 VSS138 VSS8 E37
4,5,6,7,9,16,18,36,40,41

H23 VSS137 VSS7 H37

AF23 VSS136 VSS6 K37
B24 VSS135 VSS5 M37
Leopard 3

D24 P37
E
E

VSS134 VSS4
7,9,11,12,38,39,40,41

F24 T37
Sheet

VSS133 VSS3
GMCH (5 of 5)

J24 VSS132 VSS2 V37

AG24 VSS131 VSS1 Y37
10

AJ24 VSS130 VSS0 AG37

VCCP_GMCH_S0
6,9,40,41 CORE_GMCH_S0

1D8V_S3

of
Taipei Hsien 221, Taiwan, R.O.C.
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

41
Rev
-1
Wistron Corporation
1D8V_S3
VCCP_GMCH_S0
CORE_GMCH_S0

1
2
3
4
 8,12 M_B_A[13..0] DM2 8,12 M_A_A[13..0] DM1
M_B_A0 102 108 M_A_A0 102 108
A0 /RAS M_B_RAS# 8,12 A0 /RAS M_A_RAS# 8,12
M_B_A1 101 109 M_A_A1 101 109
A1 /WE M_B_WE# 8,12 A1 /WE M_A_WE# 8,12
M_B_A2 100 113 M_A_A2 100 113
A2 /CAS M_B_CAS# 8,12 A2 /CAS M_A_CAS# 8,12
M_B_A3 99 M_A_A3 99
M_B_A4 A3 M_A_A4 A3
98 A4 /CS0 110 M_CS2_R# 7,12 98 A4 /CS0 110 M_CS0_R# 7,12
M_B_A5 97 115 M_A_A5 97 115
A5 /CS1 M_CS3_R# 7,12 A5 /CS1 M_CS1_R# 7,12
M_B_A6 94 M_A_A6 94
M_B_A7 A6 M_A_A7 A6
92 A7 CKE0 79 M_CKE2_R# 7,12 92 A7 CKE0 79 M_CKE0_R# 7,12
M_B_A8 93 80 M_A_A8 93 80
A8 CKE1 M_CKE3_R# 7,12 A8 CKE1 M_CKE1_R# 7,12
M_B_A9 91 M_A_A9 91
M_B_A10 A9 M_A_A10 A9
105 A10/AP CK0 30 CLK_DDR3 7 105 A10/AP CK0 30 CLK_DDR0 7
M_B_A11 90 32 M_A_A11 90 32
A11 /CK0 CLK_DDR3# 7 A11 /CK0 CLK_DDR0# 7
M_B_A12 89 M_A_A12 89
M_B_A13 A12 M_A_A13 A12
116 A13 CK1 164 CLK_DDR4 7 116 A13 CK1 164 CLK_DDR1 7
86 A14 /CK1 166 CLK_DDR4# 7 86 A14 /CK1 166 CLK_DDR1# 7
84 A15 M_B_SDM[7..0] 8 84 A15 M_A_SDM[7..0] 8
85 10 M_B_SDM0 85 10 M_A_SDM0 1D8V_S3
8,12 M_B_BS2# A16/BA2 DM0 8,12 M_A_BS2# A16/BA2 DM0
26 M_B_SDM1 26 M_A_SDM1
DM1 M_B_SDM2 DM1 M_A_SDM2
8,12 M_B_BS0# 107 BA0 DM2 52 8,12 M_A_BS0# 107 BA0 DM2 52 7,9,10,12,38,39,40,41 1D8V_S3
106 67 M_B_SDM3 106 67 M_A_SDM3
8,12 M_B_BS1# BA1 DM3 8,12 M_A_BS1# BA1 DM3
130 M_B_SDM4 130 M_A_SDM4 DDR_VREF_S3
M_B_DATA0 DM4 M_B_SDM5 M_A_DATA0 DM4 M_A_SDM5
5 DQ0 DM5 147 5 DQ0 DM5 147
M_B_DATA1 7 170 M_B_SDM6 M_A_DATA1 7 170 M_A_SDM6
8 M_B_DATA[63..0] DQ1 DM6 8 M_A_DATA[63..0] DQ1 DM6 7,40 DDR_VREF_S3
M_B_DATA2 17 185 M_B_SDM7 M_A_DATA2 17 185 M_A_SDM7
M_B_DATA3 DQ2 DM7 M_A_DATA3 DQ2 DM7
19 DQ3 19 DQ3
M_B_DATA4 4 195 M_A_DATA4 4 195 SMBD_ICH 3D3V_S0
DQ4 SDA SMBD_ICH 3,19 DQ4 SDA
M_B_DATA5 6 197 M_A_DATA5 6 197 SMBC_ICH
DQ5 SCL SMBC_ICH 3,19 DQ5 SCL
M_B_DATA6 14 M_A_DATA6 14
DQ6 DQ6 3,5,7,9,13,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41 3D3V_S0
M_B_DATA7 16 199 M_A_DATA7 16 199
DQ7 VDDSPD 3D3V_S0 DQ7 VDDSPD 3D3V_S0
M_B_DATA8 23 R575 10KR2 0329 SB M_A_DATA8 23 R573 10KR2
M_B_DATA9 DQ8 M_A_DATA9 DQ8
25 DQ9 SA0 198 1 2 25 DQ9 SA0 198 1 2

1
M_B_DATA10 35 200 1 2 M_A_DATA10 35 200 1 2 0329 SB
DQ10 SA1 3D3V_S0 DQ10 SA1
M_B_DATA11 37 C471 M_A_DATA11 37 C470 C472
M_B_DATA12 DQ11 R574 10KR2 C469 SC2D2U6D3V3MX-1 M_A_DATA12 DQ11 R572 10KR2 SCD1U16V SC2D2U6D3V3MX-1
20 50 20 50

2
M_B_DATA13 DQ12 NC#50 M_A_DATA13 DQ12 NC#50
M_B_DATA14
22 DQ13 NC#69 69
SCD1U16V
DY M_A_DATA14
22 DQ13 NC#69 69 DY
36 DQ14 NC#83 83 36 DQ14 NC#83 83
M_B_DATA15 38 120 M_A_DATA15 38 120
M_B_DATA16 DQ15 NC#120 M_A_DATA16 DQ15 NC#120
43 DQ16 NC#163/TEST 163 43 DQ16 NC#163/TEST 163
M_B_DATA17 45 M_A_DATA17 45
M_B_DATA18 DQ17 M_A_DATA18 DQ17
55 DQ18 55 DQ18
M_B_DATA19 57 81 M_A_DATA19 57 81
M_B_DATA20 DQ19 VDD M_A_DATA20 DQ19 VDD
44 DQ20 VDD 82 44 DQ20 VDD 82
M_B_DATA21 46 87 M_A_DATA21 46 87
M_B_DATA22 DQ21 VDD M_A_DATA22 DQ21 VDD
56 DQ22 VDD 88 56 DQ22 VDD 88
M_B_DATA23 58 95 M_A_DATA23 58 95

NORMAL TYPE
M_B_DATA24 DQ23 VDD M_A_DATA24 DQ23 VDD
61 DQ24 VDD 96 61 DQ24 VDD 96
M_B_DATA25 63 103 M_A_DATA25 63 103
M_B_DATA26 DQ25 VDD M_A_DATA26 DQ25 VDD
73 DQ26 VDD 104 73 DQ26 VDD 104
M_B_DATA27 75 111 M_A_DATA27 75 111
M_B_DATA28 DQ27 VDD M_A_DATA28 DQ27 VDD
62 112 62 112
NORMAL TYPE

M_B_DATA29 DQ28 VDD M_A_DATA29 DQ28 VDD

64 DQ29 VDD 117 64 DQ29 VDD 117
M_B_DATA30 74 118 M_A_DATA30 74 118
DQ30 VDD 1D8V_S3 DQ30 VDD 1D8V_S3
M_B_DATA31 76 M_A_DATA31 76
M_B_DATA32 DQ31 M_A_DATA32 DQ31
123 DQ32 VSS 3 123 DQ32 VSS 3
M_B_DATA33 125 8 M_A_DATA33 125 8
M_B_DATA34 DQ33 VSS M_A_DATA34 DQ33 VSS
135 DQ34 VSS 9 135 DQ34 VSS 9
M_B_DATA35 137 12 M_A_DATA35 137 12
M_B_DATA36 DQ35 VSS M_A_DATA36 DQ35 VSS
124 DQ36 VSS 15 124 DQ36 VSS 15
M_B_DATA37 126 18 M_A_DATA37 126 18
M_B_DATA38 DQ37 VSS M_A_DATA38 DQ37 VSS
134 DQ38 VSS 21 134 DQ38 VSS 21
M_B_DATA39 136 24 M_A_DATA39 136 24
M_B_DATA40 DQ39 VSS M_A_DATA40 DQ39 VSS
141 DQ40 VSS 27 141 DQ40 VSS 27
M_B_DATA41 143 28 M_A_DATA41 143 28
M_B_DATA42 DQ41 VSS M_A_DATA42 DQ41 VSS
151 DQ42 VSS 33 151 DQ42 VSS 33
M_B_DATA43 153 34 M_A_DATA43 153 34
M_B_DATA44 DQ43 VSS M_A_DATA44 DQ43 VSS
140 DQ44 VSS 39 140 DQ44 VSS 39
M_B_DATA45 142 40 M_A_DATA45 142 40
M_B_DATA46 DQ45 VSS M_A_DATA46 DQ45 VSS
152 DQ46 VSS 41 152 DQ46 VSS 41
M_B_DATA47 154 42 M_A_DATA47 154 42
M_B_DATA48 DQ47 VSS M_A_DATA48 DQ47 VSS
157 DQ48 VSS 47 157 DQ48 VSS 47
M_B_DATA49 159 48 M_A_DATA49 159 48
M_B_DATA50 DQ49 VSS M_A_DATA50 DQ49 VSS
173 DQ50 VSS 53 173 DQ50 VSS 53
M_B_DATA51 175 54 M_A_DATA51 175 54
M_B_DATA52 DQ51 VSS M_A_DATA52 DQ51 VSS
158 DQ52 VSS 59 158 DQ52 VSS 59
M_B_DATA53 160 60 M_A_DATA53 160 60
M_B_DATA54 DQ53 VSS M_A_DATA54 DQ53 VSS
174 DQ54 VSS 65 174 DQ54 VSS 65
M_B_DATA55 176 66 M_A_DATA55 176 66
M_B_DATA56 DQ55 VSS M_A_DATA56 DQ55 VSS
179 DQ56 VSS 71 179 DQ56 VSS 71
M_B_DATA57 181 72 M_A_DATA57 181 72
M_B_DATA58 DQ57 VSS M_A_DATA58 DQ57 VSS
189 DQ58 VSS 77 189 DQ58 VSS 77
M_B_DATA59 191 78 M_A_DATA59 191 78
M_B_DATA60 DQ59 VSS M_A_DATA60 DQ59 VSS
180 DQ60 VSS 121 180 DQ60 VSS 121
M_B_DATA61 182 122 M_A_DATA61 182 122
DQ61 VSS DQ61 VSS

Low5.2 mm
M_B_DATA62 192 127 M_A_DATA62 192 127
M_B_DATA63 DQ62 VSS M_A_DATA63 DQ62 VSS
194 128 194 128
High 9.2mm

DQ63 VSS DQ63 VSS

VSS 132 VSS 132
M_B_DQS#0 11 133 M_A_DQS#0 11 133
M_B_DQS#1 /DQS0 VSS M_A_DQS#1 /DQS0 VSS
8 M_B_DQS#[7..0] 29 /DQS1 VSS 138 8 M_A_DQS#[7..0] 29 /DQS1 VSS 138
M_B_DQS#2 49 139 M_A_DQS#2 49 139
M_B_DQS#3 /DQS2 VSS M_A_DQS#3 /DQS2 VSS
68 /DQS3 VSS 144 68 /DQS3 VSS 144
M_B_DQS#4 129 145 M_A_DQS#4 129 145
M_B_DQS#5 /DQS4 VSS M_A_DQS#5 /DQS4 VSS
146 /DQS5 VSS 149 146 /DQS5 VSS 149
M_B_DQS#6 167 150 M_A_DQS#6 167 150
M_B_DQS#7 /DQS6 VSS M_A_DQS#7 /DQS6 VSS
186 /DQS7 VSS 155 186 /DQS7 VSS 155
VSS 156 VSS 156
M_B_DQS0 13 161 M_A_DQS0 13 161
M_B_DQS1 DQS0 VSS M_A_DQS1 DQS0 VSS
8 M_B_DQS[7..0] 31 DQS1 VSS 162 8 M_A_DQS[7..0] 31 DQS1 VSS 162
M_B_DQS2 51 165 M_A_DQS2 51 165
M_B_DQS3 DQS2 VSS M_A_DQS3 DQS2 VSS
70 DQS3 VSS 168 70 DQS3 VSS 168
M_B_DQS4 131 171 M_A_DQS4 131 171
M_B_DQS5 DQS4 VSS M_A_DQS5 DQS4 VSS
148 DQS5 VSS 172 148 DQS5 VSS 172
M_B_DQS6 169 177 M_A_DQS6 169 177
M_B_DQS7 DQS6 VSS M_A_DQS7 DQS6 VSS
188 DQS7 VSS 178 188 DQS7 VSS 178
VSS 183 VSS 183
7,12 M_ODT2 114 ODT0 VSS 184 7,12 M_ODT0 114 ODT0 VSS 184
7,12 M_ODT3 119 ODT1 VSS 187 7,12 M_ODT1 119 ODT1 VSS 187
190 190
Wistron Corporation

om
VSS VSS
DDR_VREF_S3 1 VREF VSS 193 DDR_VREF_S3 1 VREF VSS 193

l.c
2 196 2 196 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
VSS VSS VSS VSS
1

Taipei Hsien 221, Taiwan, R.O.C.

ai
C386 C473 C182 C474

tm
202 GND GND 201 202 GND GND 201
SCD1U16V SC2D2U6D3V3MX-1 SCD1U16V SC2D2U6D3V3MX-1 Title

ho
2

DDR2-200P-4 DDR2-200P-5
DDR Socket

f@
Hi 9.2 mm Size Document Number Rev

in
Custom

xa
Leopard 3 -1

he
Date: Tuesday, August 16, 2005 Sheet 11 of 41
 0D9V_S0
RN68
8,11 M_A_A1 1 8 1 2 C180
8,11 M_A_A0 2 7 DY SCD01U16V2KX
8,11 M_A_A3 3 6
4 5 1 2 C404 0D9V_S0
8,11 M_A_A10 SCD1U16V
PLACE CAPS BETWEEN AND NEAR DDR SKTS RN69 SRN56-1 39 0D9V_S0
PLACE EACH 0.1UF CAP CLOSE TO POWER 7,11 M_CKE2_R# 1 8 1 2 C358
1D8V_S3
PIN 8,11 M_B_BS1# 2 7 DY SCD01U16V2KX 1D8V_S3
8,11 M_B_A0 3 6
8,11 M_B_A2 4 5 1 2 C196
SCD1U16V
7,9,10,11,38,39,40,41 1D8V_S3
SRN56-1 RN22
1

1
C200 C175 C164 C157 C165 C166 C364 1 8 1 2 C356
8,11 M_A_A7
SC1U6D3V2KX SC1U6D3V2KX SC1U6D3V2KX SC1U6D3V2KX SC1U6D3V2KX SC1U6D3V2KX SC1U6D3V2KX
C363
SCD1U16V 8,11 M_A_A6 2 7 DY SCD01U16V2KX
8,11 M_A_A4 3 6
2

2
8,11 M_A_A2 4 5 1 2 C399
SCD1U16V
SRN56-1
RN7 1 2 C197
7,11 M_CS3_R# 1 8 DY SCD01U16V2KX
8,11 M_B_CAS# 2 7
1

1
C146 C365 3 6 1 2 C202
8,11 M_B_WE# SCD1U16V
C147 C170 C174 C198 C192 C186 4 5
SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V 8,11 M_B_BS0#
SC1U6D3V2KX SC1U6D3V2KX
2

2
SRN56-1
RN49
8,11 M_B_A7 1 8 1 2 C396
2 7 SCD1U16V
8,11 M_B_A4
8,11 M_B_A6 3 6
7,11 M_CKE3_R# 4 5 1 2 C403
1

1
DY SCD01U16V2KX
C203 C375 C383 EC39 EC36 EC42 EC44 SRN56-1 0D9V_S0
SCD1U16V SC10U10V5ZY-L SC10U10V5ZY-L SCD1U16V SCD1U16V SCD1U16V SCD1U16V Address / Command RN21
2

2
8,11 M_A_BS1# 1 8 1 2 C194
2 7 SCD1U16V
8,11 M_A_RAS#
7,11 M_CS0_R# 3 6
8,11 M_A_A13 4 5 1 2 C357
DY SCD01U16V2KX
SRN56-1

1
1

1
TC23 RN50 1 2 C161
C355 C366 C384 C392 C390 C389 ST100U4VBM-U 1 8 SCD1U16V
8,11 M_B_A8

2
8,11 M_B_A9 2 7
2

2
8,11 M_B_A12 3 6 1 2 C388
8,11 M_B_BS2# 4
SRN56-1
5 DY SCD01U16V2KX
SC2D2U6D3V3MX-1 SC2D2U6D3V3MX-1 SC2D2U6D3V3MX-1 SC2D2U6D3V3MX-1 SC2D2U6D3V3MX-1 SC2D2U6D3V3MX-1 RN48
8,11 M_B_A13 1 8 1 2 C181
2 7 SCD1U16V
7,11 M_CS2_R#
8,11 M_B_RAS# 3 6
8,11 M_B_A11 4 5 1 2 C385
DY SCD01U16V2KX
SRN56-1
For 1GB Memory RN67
8,11 M_A_WE# 1 8 1 2 C405
2 7 SCD1U16V
8,11 M_A_BS0#
8,11 M_A_CAS# 3 6
7,11 M_CS1_R# 4 5 1 2 C177
DY SCD01U16V2KX
SRN56-1
RN8
8,11 M_B_A10 1 8 1 2 C401
2 7 SCD1U16V
8,11 M_B_A1
8,11 M_B_A3 3 6
8,11 M_B_A5 4 5 1 2 C187
DY SCD01U16V2KX
SRN56-1
Control
RN70
7,11 M_CKE0_R# 1 8 1 2 C193
2 7 SCD1U16V
8,11 M_A_BS2#
8,11 M_A_A12 3 6
8,11 M_A_A9 4 5 1 2 C387
SCD1U16V
SRN56-1
RN71 DY
7,11 M_CKE1_R# 1 8 1 2 C395
2 7 SCD1U16V
8,11 M_A_A11
8,11 M_A_A8 3 6
8,11 M_A_A5 4 5
1 2 C171
SRN56-1 DY SCD01U16V2KX

0D9V_S0

R585 1 2 56R2J
7,11 M_ODT0
R586 1 2 56R2J
7,11 M_ODT1
R587 1 2 56R2J
7,11 M_ODT2
Wistron Corporation
R588 1 2 56R2J 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
7,11 M_ODT3
Taipei Hsien 221, Taiwan, R.O.C.

Title
DDR Serial/Terminator Resistor
Size Document Number Rev
A3
Leopard 3 -1
Date: Thursday, August 18, 2005 Sheet 12 of 41
 A B C D E

3D3V_S0
Digital Signal CONN 5V_S0 5V_S0
CN5
3,5,7,9,11,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41 3D3V_S0
21
1

2
USB_PP1

USB_PN1
USB_PP1

USB_PN1
17

17 VOL_UP_DK# 3
D29
2
VOL_DWN_DK# 3
D30
2 Docking Connector 14,18,19,20,21,23,24,27,28,29,32,36,39,40,41 5V_S0
5V_S0

3 5V_S3 LUMA_CN5 1 2 LUMA 5V_S3

USB_PP3 L12 BLM11B750S CN12
4 USB_PP3 17 1 1
5 USB_PN3 60
USB_PN3 17 14,26,28,30,32,37,38,40,41 5V_S3
6 CRMA_CN5 1 2 CRMA BAV99LT1 BAV99LT1 MH1
CRMA_CN5 5V_S3 L15 BLM11B750S
7 DY DY

1
4 8 LUMA_CN5 56 55 4

1
9 R94 R91
10 DDC_DATA 15 BC12 BC13 C99 C102 150R2F 150R2F
11 DDC_CLK 15 SC3P50V2CN SC3P50V2CN SC3P50V2CN PR_PRESENT# 2 1 DCBATOUT
RJ45-7 26

2
12 SC3P50V2CN DY
JVGA_HS 7

2
13 JVGA_VS 7 DY 26 RJ45-4 4 3 RJ45-8 26 14,35,37,38,39,40,41 DCBATOUT
14 26 RJ45-5 6 5 RJ45-3 26
15 5V_S0 8 7 5V_AUX
26 RJ45-1 RJ45-6 26
16 CRT_R 15 26 RJ45-2 10 9 JACK_DETECT# 28
17 12 11 SPDIF
14,15,35,37,38,39 5V_AUX
18 MIC_PR 14 13 5V_Dock_S0
1 2 R43
CRT_G 15 5V_S0
19 16 15 0R2-0
AUD_AGND MUTE_LED 14,31
20 CRT_B 15 28 DK_SPKR_R+ 18 17
22 20 19 1394_TPA1P_PR 26
28 DK_SPKR_L+
22 21 1394_TPA1N_PR 26
31 VOL_UP_DK#
USB_PN7 24 23 1394_TPB1P_PR 26
17 USB_PN7
JST-CON20 LINE-OUT USB_PP7 26 25 1394_TPB1N_PR 26
17 USB_PP7
28 27
IR_OUT 30 29 JACK_DETECT# 1 2 EC8
Analog Signal CONN TPAD30 TP40 32 31 SCD1U16V
34 33 MUTE_LED 1 2 EC11
CN6 R333 36 35 SCD1U16V
11 1 2 38 37 AUD_AGND 1 2 EC93
1 MIC_PR COMP_PR 40 39 SCD1U16V
2 0R2-0 LUMA_PR 42 41 MIC_PR 1 2 EC95
EXT_MIC_1 27 SC1000P16V2KX
3 CRMA_PR 44 43
EXT_MIC_2 27
4 46 45 DK_SPKR_R+ 1 2 EC94
31 VOL_DWN_DK# SC1000P16V2KX
5 CIR_PR 48 47
HP_OUT_R 27
6 50 49 DK_SPKR_L+ 1 2 EC102
3
HP_OUT_L 27 5V_DOCK 5V_DOCK SC1000P16V2KX 3
7 52 51
8 MIC-IN 54 53 DOCK_PRESENT COMP_PR 1 2 EC100

1
9 DCBATOUT_BEAD SC1000P16V2KX
EARPHONE 28
10 58 57 VOL_UP_DK# 1 2 EC101
LID_SW 14 AD+ AD+ SC1000P16V2KX
12 R65
1KR2 MH2 VOL_DWN_DK# 1 2 EC103
MOLEX-CON10-1 3D3V_S0 59 SC1000P16V2KX

2
DOCK_PRESENT 1 2 EC20
AUD_AGND SC1000P16V2KX
FOX-CONN58D-U3
PR_PRESENT# 1 2 EC92
1

SC1000P16V2KX
R432 BT_LED 1 2 EC19
47KR2 3D3V_S3 SC1000P16V2KX
63.47334.1D1 BT_LED 14,26
D31
2

2
EARPHONE
LID_SW 3
INPUT FUNCTION Place near the GMCH
1

BAV99LT1 LOW B0
5V_S0
26 BC0EX1 1 DY 2 R495 HIGH B1
DUMMY-R2 ICH_PME# 17,25,29
U7

26 BC0EX2 1 DY 2 R225 LUMA 1 6 PR_INSERT#

DUMMY-R2 PCI_AD24 17,22,25,29 5V_S3 AD+ 5V_S0 B1 S
5V_S0 DCBATOUT_BEAD 2 5
LUMA_PR 1 LUMA_PR_1 GND VCC
2 3 B0 A 4 LUMA_VGA 7
2 L26 IND-1D2UH 2
Please close to ICH6

1
1

1
5V_S0 C296 C297 R334 NC7SB3157P6X-U
C337 C70 C458 C69 C338 SC47P50V2JN SC47P50V2JN 150R2F

2
SCD1U16V SCD1U25V3KX SCD1U16V SCD1U25V3KX SCD1U16V
2

2
1

2
R309
10KR2 U8

CRMA 1 6 PR_INSERT#
2

B1 S
2 GND VCC 5
PR_INSERT# CRMA_PR
1 2 CRMA_PR_1 3 4
PR_INSERT# 31 IND-1D2UH B0 A CRMA_VGA 7
L24

1
3

R63 C294 C307 NC7SB3157P6X-U

DOCK_PRESENT 1 2 1 Q17 SPDIF_OUT 1 2 SPDIF SC47P50V2JN SC47P50V2JN
27 SPDIF_OUT

2
47R2 S2N3904-U3 L19 BLM18PG600SN1
1

1
2

R64 C51 R536

2K2R2 PR_PRESENT# C464 COMP_PR 1 2 1 2 COMP_VGA 7

2
SC470P25V2KN L25 IND-1D2UH
2

1
SC470P25V2KN 0R2-0
2

1
C298
1 2 EC124 C295 SC47P50V2JN R335 R372

2
SCD1U16V SC47P50V2JN 150R2F 150R2F

2
DY

2
1
AUD_AGND Place near the DOCK 1

5V_S3 5V_DOCK 1 R259

2 Wistron Corporation

om
15 CIR 0R2-0
F3 100 mil 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

l.c
1 2 CIR_PR 1 R371
2 Taipei Hsien 221, Taiwan, R.O.C.
0R2-0

ai
CIR_KBC 31
1

tm
FUSE-2A6V Title
C306 C305 TC15

ho
SC4D7U10V5ZY
SCD1U16V ST47U6D3V-U1 Board to board conn/ Docking

f@
2

DY CIR,CIR_PR,CIR_KBC are connect togather. default setting 12/12 Size Document Number Rev

in
A3 -1
Leopard 3

xa
he
Date: Monday, August 15, 2005 Sheet 13 of 41
A B C D E
 A B C D E

3D3V_S0

3,5,7,9,11,13,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41 3D3V_S0

INVERTER/LCD 3D3V_S0 3D3V_LCD_S0

3D3V_S3

13,30,40 3D3V_S3
3D3V_LCD_S0 SI3865_R1C1 1 2 BC61 5V_S0
SC6800P50V3KX
U49 13,18,19,20,21,23,24,27,28,29,32,36,39,40,41 5V_S0
CN3

1
R315 1 R317
2 6 1 SI3865_R2 5V_S5
BC11 BC10 270KR2F R1/C1 R2
4 41 43 7 LCDVDD_ON 1 2 LCDVDD_ON_1 5 ON/OFF D2 2 4
SCD1U16V SC10U10V6ZY-U 1KR2 4 3 18,20,36,38 5V_S5

2
S2 D2
1 MH1

1
DCBATOUT
2 BC60 BC57 SI3865DV-U R318 3D3V_S3
3 45 SC1U10V3ZY SCD1U16V 84.03865.03D 47KR2
7 TXAOUT0- 35,37,38,39,40,41 DCBATOUT

2
7 TXAOUT0+ 4

1
5

2
6 R430
7 TXAOUT1- 3D3V_LCD_S0 4K7R2
7 TXAOUT1+ 7
8
9 5V_S5 R431
7 TXAOUT2-

2
1
10 1 2 LID_SW
7 TXAOUT2+ 31 KBC_LID# 100KR2 LID_SW 13
11 R316

1
12 150R2
7 TXACLK-

1
13 C352
7 TXACLK+ SC1000P50V
14 R314

2
15 10KR2
7 TXBOUT0-
7 TXBOUT0+ 16
17 D19

D
2
18 Q18 Q19 Q21 2
7 TXBOUT1- 802_ACT_LED 29
7 TXBOUT1+ 19 3 OUT 32 802_BT_LED# OUT 3
20 LCDVDD_ON 2 R1 R1 2 802_BT_LED 3
7 TXBOUT2- 21 IN 1 GND G GND 1 IN
22 R2 R2 1
7 TXBOUT2+ BT_LED 13,26
23 DTC114EUA-U1 DTC114EUA-U1

S
24 2N7002-F-GP
7 TXBCLK-
7 TXBCLK+ 25
26 CH715F
3 27 Q9 3
7 EDID_CLK
7 EDID_DAT 28 3 OUT 7421_LED#
29 2 R1
3D3V_S0 22 7421_LED
30 IN 1 GND 5V_S3 5V_S0
31 R2
31 BRIGHTNESS 32 DTC114EUA-U1
31 FPBACK 33
DCBATOUT 34 Q6
35 3 OUT CAPS_LED# 5V_S3_PA 5V_S0_PA
5V_S0 36 2 R1
31 CAPS_LED

2
37 IN 1 GND R538 R539
38 46 R2 ID_DET 1 2 1 Q33 ID_DET 1 2 1 Q34
39 DTC114EUA-U1 47KR2 2N3906-2-U 47KR2 2N3906-2-U
40 MH2

3
Q22
1

C291 BC56 BC59 42 44 3 OUT NUM_LED# 32

C292 BC55 2 R1
31 NUM_LED
SC1000P16V2KX SC1000P16V2KX SCD1U16V SCD1U IN 1 GND
2

SCD1U16V R2
IPEX-CON40-1-U1
5V_AUX DTC114EUA-U1
5V_S3_PR 5V_S0_PR
5V_AUX

2
R540 R541
ID_DET# 1 2 1 Q35 ID_DET# 1 2 1 Q36
5V_AUX_PA 47KR2 2N3906-2-U 47KR2 2N3906-2-U
1

3
2
R542
1

PWR CHR HDD IR CAPS 7421 10KR2 1 Q37

R543 2N3906-2-U
2 100KR2
DY 1 2
2

3
R544
PR Amber Amber Amber U42 Amber Amber 47KR2
2

Botton
LED4 LED5 LED6 LED1 LED2
HDD_LED# 21
2

ID_DET
Blue Blue 31,32 ID_DET
PA Blue U64 Blue Blue IDE_LED#
D

CDROM_LED# 21
Top 5V_AUX_PR
LED8 LED7 LED9 LED1 LED2 Q38

2
R545 Q20
G ID_DET#1 2 1 Q39 3 OUT MUTE_LED# 32
47KR2 2N3906-2-U 2 R1
change R from 100 to 200 ohm 13,31 MUTE_LED
IN 1 GND
S

5V_S0_PR 2N7002-F-GP 3 R2 Q14

R546 LED10 DTC114EUA-U1 3 OUT CHG_LED#
1 2 1 2 CAPS_LED# 5V_S0_PA 2 R1
31 CHG_LED
1K2R2J-1 IN 1 GND
LED-O-10 R93 LED1 R2
5V_S0_PR 1 2 1 2 CAPS_LED# DTC114EUA-U1
R547 LED11 5V_S0_PA 100R2
1 2 1 2 7421_LED# LED-B-53 Q13
1K2R2J-1 R112 LED2 3 OUT PWR_LED# 32
LED-O-10 1 2 1 2 7421_LED# 2 R1
31 PWR_LED
NC

5V_S0_PR 200R2J IN 1 GND

R258 LED6 LED-B-53 R2
1 2 2 1 IDE_LED# DTC114EUA-U1
NC

1K2R2J-1 5V_S0_PA
R549 LED9
LED-O-11-U
1 1 2 2 1 IDE_LED# 1
200R2J
5V_AUX_PR LED-B-54-U
NC

NC

5V_AUX_PA
R257 LED5 R550 LED8 Wistron Corporation
1 2 2 1 CHG_LED# 1 2 2 1 CHG_LED# 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1K2R2J-1 200R2J Taipei Hsien 221, Taiwan, R.O.C.
LED-O-11-U LED-B-54-U
5V_S3_PR Title
NC

NC

5V_S3_PA
R256 LED4 R548 LED7 Inverter/LCD
1 2 2 1 PWR_LED# 1 2 2 1 PWR_LED# Size Document Number Rev
1K2R2J-1 200R2J A3
Leopard 3 -1
LED-O-11-U LED-B-54-U
Date: Monday, August 15, 2005 Sheet 14 of 41
A B C D E
 A B C D E

PA & PR diffent parts

2D5V_S0
PA PR
LED1 83.00190.Y70 83.00190.W70
LED2 83.00190.Y70 83.00190.W70
LED4 Dummy 83.00110.D70
LED5 Dummy 83.00110.D70

4
3
LED6 Dummy 83.00110.D70 RN37
4 2D5V_S0 SRN2K2J 4
LED7 83.00110.E70 Dummy
LED8 83.00110.E70 Dummy
LED9 83.00110.E70 Dummy CRT

1
2
U64 56.15006.001 Dummy
U42 Dummy 56.15006.001
R256 63.20134.1D1 63.12234.1D1
R257 63.20134.1D1 63.12234.1D1
R258 63.20134.1D1 63.12234.1D1 13 DDC_CLK 1 2 DDC_CLK_CON
L8 BLM11B750S
R93 63.20134.1D1 63.12234.1D1 13 DDC_DATA 1 2 DDC_DATA_CON
U12
R112 63.20134.1D1 63.12234.1D1 L7 BLM11B750S
4 3 DDC_DATA_CON
7,13 JVGA_HS JVGA_HS 7 GMCH_DDCDATA
VGA_HSYNC 7,13
5 2
7,13 JVGA_VS JVGA_VS
VGA_VSYNC 7,13
DDC_CLK_CON 6 1 GMCH_DDCCLK 7
CBUS1 21.H0088.001 21.H0088.001
R176 63.10334.1D1 Dummy 2N7002DW
R177 Dummy 63.10334.1D1
1 2 CRT_B
7 VGA_BLUE BLM11B750S
L6 CRT_B 13
1 2 CRT_G
7 VGA_GREEN BLM11B750S CRT_G 13
L5
3 3
1 2 CRT_R
7 VGA_RED BLM11B750S CRT_R 13
L9
C103 C87 C86

SC10P50V2JN-1

SC10P50V2JN-1

SC10P50V2JN-1
1

1
C101 C100 C84
SB SB

SC10P50V2JN-1

SC10P50V2JN-1

SC10P50V2JN-1

2
1

1
R92 R85 R84
75R2F 75R2F 75R2F

2
2

2
Close to CN5

Close to U17 (N/B)

CIR FOR FF 5V_AUX

2 2
1
1

R260 R261
10KR2 100R2

IR-TSOP6236-U
2
2

GND 1
GND 2
VS 3 1 2 C273
4 CIR SC4D7U10V5ZY
OUT CIR 13

U64

IR-TSOP6236-U

GND 1
GND 2
DY VS 3
OUT 4

1 1
U42

Wistron Corporation

om
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

l.c
Taipei Hsien 221, Taiwan, R.O.C.

ai
tm
Title
CRT/ CIR

ho
f@
Size Document Number Rev

in
A3
Leopard 3 -1

xa
he
Date: Monday, August 15, 2005 Sheet 15 of 41
A B C D E
 A B C D E

3D3V_S0

3D3V_AUX RTC_AUX_S5
3,5,7,9,11,13,14,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41 3D3V_S0
D13 C256
1 2 1 2 SC4D7P50V3CN 3D3V_AUX

1
CH751H-40-U
RTC_VCC 20,31,32,34,35,36,37 3D3V_AUX
C257

4
SC1U10V3ZY VCCP_GMCH_S0

1
X4
XTAL-32D768K-4P R228
4,5,6,7,9,10,18,36,40,41 VCCP_GMCH_S0
10MR2J
D14 R507
RTC circuitry
4 1 2 1 2 4

2
U35A
1

2
CH751H-40-U 20KR2
LPC_LAD[3..0] 31
1

1
R250 G66 1 2
1KR2 R508 C455 C255 RCT_X1 Y1 P2 LPC_LAD0
1MR2 SC1U10V3ZY GAP-OPEN SC3D9P50V3CN RCT_X2 RTCX1 LAD[0]/FWH[0] LPC_LAD1
Y2 N3

2
RTCX2 LAD[1]/FWH[1] LPC_LAD2
N5
BAT2

1
RCT_RST# LAD[2]/FWH[2] LPC_LAD3 3D3V_S0

LPC
AA2 N4

RTC
2

RTCRST# LAD[3]/FWH[3] Open J5G1 for Dothan A step

INTRUDER# AA3 N6 Shunt for Dothan B step R488
INTRUDER# LDRQ[0]# LPC_LDRQ0# 31 & all Yonah
AA5 P4 LPC_LDRQ1# RCIN# 1 2
INTVRMEN LDRQ[1]#/GPI[41]
4
1

2
3
5

10KR2
P3 LPC_LDRQ1# 1 2
LFRAME#/FWH[4] LPC_LFRAME# 31 10KR2
D12 R501
EE_CS VCCP_GMCH_S0
3D3V_S0
B12 EE_SHCLK 12/12 INTEL check list
RTC1 D11 AF22
EE_DOUT A20GATE ICH_A20GATE 31
ETY-CON3-S1 F13 AF23
EE_DIN A20M# H_A20M# 4

1
DY
1

The symbol use 2nd source TPAD30 TP67 ICH_TP5 F12 AE27 H_CPUSLP#_ICH R310 1 2 0R2-0 R162

LAN
LAN_CLK CPUSLP# H_CPUSLP# 4,6 56R2J
The P/N is the main source R249 R194
D

10KR2 1 2 LAN_RSTSYNC B11 AE24 H_DPRSLP#_R R160 1 2 0R2-0

Main source:20.D0152.103 10KR2 LAN_RSTSYNC DPRSLP# H_DPRSLP# 4
Q11 DY AD27 H_DPSLP#_R R148 1 2 0R2-0 H_DPSLP# 4

2
2nd source:20.D0012.103 2N7002-F-GP DPSLP#
E12
2

LANRXD[0] H_FERR_R R159 1

G E11 AF24 2 56R2J

CPU
LANRXD[1] FERR# H_FERR# 4
DY C13 LANRXD[2]
AG25 H_PWRGD 4
S

CPUPWRGD/GPO[49]
C12 LANTXD[0]
C11 LANTXD[1] IGNNE# AG26 H_IGNNE# 4
E13 AE22 R717 R388 R370
3 LANTXD[2] INIT3_3V# 3
INIT# AF27 H_INIT# 4
C10 AG24 Dothan A DUMMY 56R 0R
20,31,39 RSMRST# 27,30 AC97_BITCLK ACZ_BIT_CLK INTR H_INTR 4
1 R192 2 AC97_SYNC_ICH B9 VCCP_GMCH_S0

AC-97/AZALIA
27,30 AC97_SYNC ACZ_SYNC Dothan B 0R 0R DUMMY
33R2 AD23
RCIN# RCIN# 31
1 R191 2 AC97_RST#_ICH A10
27,30 AC97_RST# ACZ_RST#

1
33R2 AF25
NMI H_NMI 4
F11 AG27 R157
27 AC97_DIN0 ACZ_SDIN[0] SMI# H_SMI# 4 R6V9 75R2
30 AC97_DIN1 F10 ACZ_SDIN[1]
B10 ACZ_SDIN[2] STPCLK# AE26 H_STPCLK# 4
R493 R158

2
1 2 AC97_DOUT_ICH C9 AE23 H_THERMTRIP_R 1 2
27,30 AC97_DOUT 33R2 ACZ_SDO THRMTRIP# 56R2J PM_THRMTRIP-I# 4,7
R6V7
AC19 AC16 Layout Note: R6V7 needs to placed
SATALED# DA[0] IDE_A0 21 within 2" of ICH6, R6V9 must be placed
DA[1] AB17 IDE_A1 21
AE3 AC17 within 2" of R6V7 w/o stub.
SATA[0]RXN DA[2] IDE_A2 21
AD3 SATA[0]RXP
AG2 SATA[0]TXN DCS1# AD16 IDE_CS#0 21
1 2R496 AF2 SATA[0]TXP DCS3# AE17 IDE_CS#1 21
0R2-0
AD7 SATA[2]RXN DD[0] AD14 IDE_D0 21
AC7 AF15

SATA
SATA[2]RXP DD[1] IDE_D1 21
AF6 SATA[2]TXN DD[2] AF14 IDE_D2 21
AG6 SATA[2]TXP DD[3] AD12 IDE_D3 21

IDE
DD[4] AE14 IDE_D4 21
AC2 SATA_CLKN DD[5] AC11 IDE_D5 21
AC1 SATA_CLKP DD[6] AD11 IDE_D6 21
DD[7] AB11 IDE_D7 21
SATA_RBIAS_PN AG11 AE13
2 SATARBIAS# DD[8] IDE_D8 21 2
AF11 SATARBIAS DD[9] AF13 IDE_D9 21
AB12 VCCP_GMCH_S0
DD[10] IDE_D10 21
2

DD[11] AB13 IDE_D11 21

R195 AC13
DD[12] IDE_D12 21

1
0R2-0 AF16 AE15
21 IDE_IORDY IORDY DD[13] IDE_D13 21
AB16 AG15 R149 VCCP_GMCH_S0
Place within 500 mils 21 IDE_IRQ14 IDEIRQ DD[14] IDE_D14 21 56R2J
21 IDE_DACK# AB15 AD13 IDE_D15 21
1

of ICH6 ball DDACK# DD[15]

21 IDE_IOW# AC14 DIOW# DY

1
21 IDE_IOR# AE16 AB14 IDE_DREQ 21

2
DIOR# DDREQ H_DPSLP# R161
56R2J
ICH6M DY

2
H_DPRSLP#

1 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
ICH6-M (1 of 4)
Size Document Number Rev
A3
Leopard 3 -1
Date: Tuesday, July 12, 2005 Sheet 16 of 41
A B C D E
 A B C D E

U35C
U35B PCIE AC coupling caps
3D3V_S0 need to be within 250 mils of the driver.
13,22,25,29 PCI_AD[31..0]
PM_RI# T2 H25
RI# PERn[1] PCIE_RXN0 21
PCI_AD0 E2 L5 PCI_REQ#0 RN33 H24
AD[0] REQ[0]# PCI_REQ#0 29 PERp[1] PCIE_RXP0 21
PCI_AD1 E5 PCI C1 1 8 SATA0_R0 AF17 G27 PCIE_TXN0_R 1 2
AD[1] GNT[0]# PCI_GNT#0 29 SATA[0]GP/GPI[26] PETn[1] PCIE_TXN0 21
PCI_AD2 C2 B5 PCI_REQ#1 2 7 SATA0_R1 AE18 G26 PCIE_TXP0_R C207 1 2 SCD1U16V
AD[2] REQ[1]# PCI_REQ#1 22 SATA[1]GP/GPI[29] PETp[1] SCD1U16V PCIE_TXP0 21
PCI_AD3 F5 B6 3 6 SATA0_R2 AF18 C208
AD[3] GNT[1]# PCI_GNT#1 22 SATA[2]GP/GPI[30]
PCI_AD4 F3 M5 PCI_REQ#2 4 5 SATA0_R3 AG18 K25
AD[4] REQ[2]# PCI_REQ#2 25 3D3V_S0 SATA[3]GP/GPI[31] PERn[2]
PCI_AD5 E9 F1 K24

PCI-EXPRESS
AD[5] GNT[2]# PCI_GNT#2 25 PERp[2]
PCI_AD6 F2 B8 PCI_REQ#3 SRN100K Y4 J27
AD[6] REQ[3]# 19,21 SMB_CLK SMBCLK PETn[2]
PCI_AD7 D6 C8 ICH_GNT3 TP72 TPAD30 W5 J26
AD[7] GNT[3]# 19,21 SMB_DATA SMBDATA PETp[2]
PCI_AD8 E6 F7 PCB_VER2 SMB_LINK_ALERT# Y5
PCI_AD9 AD[8] REQ[4]#/GPI[40] ICH_GPO48 3D3V_S5 SMLINK0 LINKALERT#
D3 E7 W4 M25

GPIO
4 4
PCI_AD10 AD[9] GNT[4]#/GPO[48] PCI_REQ#5 TP75 TPAD30 SMLINK1 SMLINK[0] PERn[3]
A2 AD[10] REQ[5]#/GPI[1] E8 U6 SMLINK[1] PERp[3] M24

1
PCI_AD11 D2 F6 ICH_GPO17 TP74 TPAD30 MCH_SYNC# AG21 L27
PCI_AD12 AD[11] GNT[5]#/GPO[17] ICH_GPI0_R R227 MCH_SYNC# PETn[3]
D5 AD[12] REQ[6]#/GPI[0] B7 1 2 27 ICH_SPKR F8 SPKR PETp[3] L26
PCI_AD13 H3 D8 ICH_GPO16 R193 10KR2 10KR2
PCI_AD14 AD[13] GNT[6]#/GPO[16] TP73 TPAD30 PM_SUS_STAT#
B4 AD[14] W3 SUS_STAT#/LPCPD# PERn[4] P24
PCI_AD15 J5 J6 P23
PCI_C/BE#0 22,25,29

2
PCI_AD16 AD[15] C/BE[0]# SYS_RESET# PERp[4]
K2 AD[16] C/BE[1]# H6 PCI_C/BE#1 22,25,29 U2 SYS_RESET# PETn[4] N27
PCI_AD17 K5 G4 N26
AD[17] C/BE[2]# PCI_C/BE#2 22,25,29 PETp[4]
PCI_AD18 D4 G2 AD19
AD[18] C/BE[3]# PCI_C/BE#3 22,25,29 PM_BMBUSY#
7 D34 BMBUSY#
PCI_AD19 L6 T25
AD[19] DMI[0]RXN DMI_RXN0 7
PCI_AD20 G3 A3 3 1 ICH_GPI7 AE19 T24
AD[20] IRDY# PCI_IRDY# 22,25,29 21 CPPE# GPI[7] DMI[0]RXP DMI_RXP0 7 Layout Note:
PCI_AD21 H4 E1 ECSMI# R1 R27

Direct Media Interface

AD[21] PAR PCI_PAR 22,25,29 GPI[8] DMI[0]TXN DMI_TXN0 7 PCIE AC coupling caps
PCI_AD22 H2 R2 R26
AD[22] PCIRST# ICH_PCIRST# 19 S1N4148-U2 DMI[0]TXP DMI_TXP0 7 need to be within 250 mils of the driver.
PCI_AD23 H5 C3 ECSCI# W6
PCI_AD24 AD[23] DEVSEL# PCI_DEVSEL# 22,25,29 SB SMBALERT#/GPI[11]
PCI_AD25
B3 AD[24] PERR# E3
PCI_LOCK#
PCI_PERR# 22,25,29 DY GPI12 DMI[1]RXN V25 DMI_RXN1 7
M6 AD[25] PLOCK# C5 M2 GPI[12] DMI[1]RXP V24 DMI_RXP1 7
PCI_AD26 B2 G5 ECSWI# R6 U27
AD[26] SERR# PCI_SERR# 22,25,29 GPI[13] DMI[1]TXN DMI_TXN1 7
PCI_AD27 K6 J1 U26
AD[27] STOP# PCI_STOP# 22,25,29 DMI[1]TXP DMI_TXP1 7
PCI_AD28 K3 J2 AC21
AD[28] TRDY# PCI_TRDY# 22,25,29 3 PM_STPPCI# STP_PCI#
PCI_AD29 A5 Y25
AD[29] DMI[2]RXN DMI_RXN2 7
PCI_AD30 L1 TPAD30 TP68 ICH6_GPO19 AB21 Y24
AD[30] GPO[19] DMI[2]RXP DMI_RXP2 7
PCI_AD31 K4 R5 W27
AD[31] PLTRST# PLT_RST# 19 DMI[2]TXN DMI_TXN2 7
PCICLK G6 CLK_ICHPCI 3 3,36 PM_STPCPU# AD22 STP_CPU# DMI[2]TXP W26 DMI_TXP2 7
22,25,29 PCI_FRAME# J3 FRAME# PME# P6 ICH_PME# 13,25,29
TPAD30 TP69 ICH6_GPO21 AD20 AB24
GPO[21] DMI[3]RXN DMI_RXN3 7 1D5V_S0
Interrupt I/F TPAD30 TP89 ICH_GPO27 AD21 AB23
GPO[23] DMI[3]RXP DMI_RXP3 7
INT_PIRQA# N2 D9 INT_PIRQE# AA27
PIRQ[A]# PIRQ[E]#/GPI[2] INT_PIRQE# 25,29 DMI[3]TXN DMI_TXN3 7 Place within 500 mils of ICH
INT_PIRQB# L2 C7 INT_PIRQF# V3 AA26
PIRQ[B]# PIRQ[F]#/GPI[3] INT_PIRQF# 22 GPIO[24] DMI[3]TXP DMI_TXP3 7

1
3 INT_PIRQC# M1 C6 INT_PIRQG# 3
PIRQ[C]# PIRQ[G]#/GPI[4] INT_PIRQG# 22
INT_PIRQD# L3 M3 INT_PIRQH# P5 AD25 R479
PIRQ[D]# PIRQ[H]#/GPI[5] 21 NEWCARD_RST# GPIO[25] DMI_CLKN CLK_PCIE_ICH# 3 24D9R2F
26 BT_EN R3 GPIO[27] DMI_CLKP AC25 CLK_PCIE_ICH 3
TPAD30 TP79 ICH_TP8
RESERVED ICH_TP13 TP81 TPAD30
29 WIRELESS_EN# T3 GPIO[28]
AC5 AD9 22,25,29,31 PM_CLKRUN# AF19 F24

2
TPAD30 TP80 ICH_TP9 RSVD[1] RSVD[6] ICH_TP14 TP31 TPAD30 PCB_VER0 CLKRUN# DMI_ZCOMP
AD5 RSVD[2] RSVD[7] AF8 AF20 GPIO[33]
TPAD30 TP34 ICH_TP10 AF4 AG8 ICH_TP15 TP32 TPAD30 PCB_VER1 AC18 F23 DMI_IRCOMP_R
TPAD30 TP33 ICH_TP11 RSVD[3] RSVD[8] ICH_TP16 TP83 TPAD30 GPIO[34] DMI_IRCOMP
AG4 RSVD[4] TP[3] U3
TPAD30 TP78 ICH_TP12 AC9 U5 C23 USB_OC#4
RSVD[5] 21 PCIE_WAKE# WAKE# OC[4]#/GPI[9]
D23 USB_OC#5
OC[5]#/GPI[10] USB_OC#6
22,29,31 PCI_SERIRQ AB20 C25 RP3 3D3V_S5
SERIRQ OC[6]#/GPI[14] USB_OC#7 USB_OC#0
OC[7]#/GPI[15] C24 1 10
ICH6M AC20 USB_OC#1 2 9 USB_OC#5
20 PM_THRM# THRM#
C27 USB_OC#0 USB_OC#3 3 8 USB_OC#4
ICH6 Pullups 3D3V_S5
20 VRM_PWRGD AF21 VRMPWRGD
OC[0]#
OC[1]# B27 USB_OC#1
USB_OC#2
USB_OC#2 4 7 USB_OC#7
USB_OC#6
RP4 3D3V_S0 B26 3D3V_S5 5 6
PCI_FRAME# OC[2]# USB_OC#3
1 10 E10 C26

CLOCKS
3 CLK_ICH14 CLK14 OC[3]#
PCI_IRDY# 2 9 INT_PIRQD# SRP10K
PCI_TRDY# 3 8 INT_PIRQG# RN35 A27 C21 TP27 TPAD30
3 CLK48_USB CLK48 USBP[0]N
PCI_STOP# 4 7 INT_PIRQF# PM_RI# 1 8 D21 TP28 TPAD30
INT_PIRQE# SMB_LINK_ALERT# TPAD30 TP77 PM_SUS_CLK USBP[0]P
3D3V_S0 5 6 2 7 V6 SUSCLK USBP[1]N A20 USB_PN1 13
SMLINK0 3 6 B20
USBP[1]P USB_PP1 13
SRP10K SMLINK1 4 5 T4 D19
21,28,31,37,38,40 PM_SLP_S3# SLP_S3# USBP[2]N USB_PN2 26
RP1 3D3V_S0 21,31,37,38 PM_SLP_S4# T5 C19 USB_PP2 26
PCI_SERR# ICH_SLP_S5# SLP_S4# USBP[2]P
1 10 SRN10K T6 A18 USB_PN3 30
PCI_DEVSEL# INT_PIRQH# PCIE_WAKE# R504 1 SLP_S5# USBP[3]N
2 9 2 5K6R2 TPAD30 TP76
USBP[3]P B18 USB_PP3 30
PCI_PERR# 3 8 PCI_REQ#2 AA1 E17
20 ICH6_PWROK PWROK USBP[4]N USB_PN4 30

POWER MGT
PCI_LOCK# 4 7 PCI_REQ#3 PM_BATLOW#_R R505 1 2 8K2R2 D17
USBP[4]P USB_PP4 30
5 6 PM_CLKRUN# 1 2 PM_DPRSLPVR_R AE20 B16
2 3D3V_S0 36 PM_DPRSLPVR 100R2 DPRSLPVR USBP[5]N USB_PN5 21 2
PM_SUS_STAT#R506 1 DY 2 10KR2 R489 A16

USB
USBP[5]P USB_PP5 21
SRP10K 31 PM_SUS_STAT# PM_BATLOW#_R V2 C15
BATLOW# USBP[6]N USB_PN6 13
RP2 3D3V_S0 D15 USB_PP6 13
PCI_REQ#5 3D3V_S0 USBP[6]P
1 10 31 PM_PWRBTN# U1 PWRBTN# USBP[7]N A14 USB_PN7 13
INT_PIRQA# 2 9 PCI_SERIRQ B14
USBP[7]P USB_PP7 13
1

INT_PIRQC# 3 8 MCH_SYNC# PCI_REQ#1 R190 1 2 10KR2 PLT_RST# V5

INT_PIRQB# PCI_REQ#0 R481 LAN_RST# R156
4 7 USBRBIAS# A22
5 6 PM_THRM# ICH_GPI7 R172 1 2 10KR2 100KR2 Y3 B22 USB_RBIAS_PN 1 2 Intel 22.6 ohm 1%
3D3V_S0 31 RSMRST#_KBC RSMRST# USBRBIAS
SRP10K GPI12 R500 1 2 10KR2 22D6R2F
2

ICH6M Place within 500 mils of ICH

3D3V_S0

RN36
R590 1 8 ICH_TP16
1

R245 R247 ICH_TP9 3D3V_S5

2 7 ICH6-M Strapping Options
1

ICH_TP8
DUMMY-R2

SB 3 6
10KR2 4 5 ICH_TP13
DY 10KR2 REF FUNCTION DEFAULT OPTIONAL OVERRIDE

1
SRN0
2

R226 R502 R503

2

PCB_VER2 100KR2 100KR2 100KR2 R7F9 No Reboot NO_STUFF STUFF

PCB_VER0
PCB_VER1
PUMA Board Version Setting

2
R246 R7F8 A16 Swap NO_STUFF STUFF
1

R591 Override
1

R248
DUMMY-R2

PCB_VER0 PCB_VER1 PCB_VER2

10KR2 Ver. R7F7 Boot BIOS NO_STUFF STUFF
DUMMY-R2

1 DY SA 0 0 0 1
D12
2

DY ECSMI# 6 1
SB 0 1 0 ECSMI#_KBC 31
2

Wistron Corporation
2

SC 1 0 0

om
ECSCI# 5 2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
ECSCI#_KBC 31

l.c
Taipei Hsien 221, Taiwan, R.O.C.
-1 1 1 0

ai
tm
ECSWI# 4 3 Title
1D5V_S0 1D5V_S0 5,7,9,18,21,38,39,41 -2 0 0 1 ECSWI#_KBC 31

ho
CH731U-U
ICH6-M (2 of 4)

f@
3D3V_S5 3D3V_S5 18,19,21,25,29,31,35,37,39,40
Size Document Number Rev

in
A3
3D3V_S0 3D3V_S0 3,5,7,9,11,13,14,16,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41 Leopard 3 -1

xa
he
Date: Monday, August 15, 2005 Sheet 17 of 41
A B C D E
 A B C D E

1D5V_S0
3,5,7,9,11,13,14,16,17,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41 3D3V_S0 3D3V_S0
Layout Note:
Place above caps within 17,19,21,25,29,31,35,37,39,40 3D3V_S5 3D3V_S5

1
100 mils of ICH near F27, P27, AB27
13,14,19,20,21,23,24,27,28,29,32,36,39,40,41 5V_S0 5V_S0
U35E C417 C420 C423 C428 C425
SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1
5,7,9,17,21,38,39,41 1D5V_S0 1D5V_S0

2
Layout Note:
1D5V_S0
Place near pin AA19 39 1D5V_S5 1D5V_S5
AA22 VCC1_5_B VCC1_5_A F9 7,9,15,40 2D5V_S0 2D5V_S0
AA23 VCC1_5_B VCC1_5_A U17

1
C209 AA24 U16
VCC1_5_B VCC1_5_A 4,5,6,7,9,10,16,36,40,41 VCCP_GMCH_S0 VCCP_GMCH_S0

1
4 TC9 C409 C424 AA25 U14 4
ST220U10V-U SCD1U10V2MX-1SCD1U10V2MX-1 VCC1_5_B VCC1_5_A C438 C439 C422 C421 C436 C239
DY AB25 U12

2
VCC1_5_B VCC1_5_A SCD1U10V2MX-1SCD1U10V2MX-1SCD1U10V2MX-1SCD1U10V2MX-1 SCD1U10V2MX-1SCD1U10V2MX-1
AB26 U11

2
SCD1U10V2MX-1 VCC1_5_B VCC1_5_A
AB27 VCC1_5_B VCC1_5_A T17 DY DY DY DY DY DY
F25 VCC1_5_B VCC1_5_A T11
F26 P17

CORE
VCC1_5_B VCC1_5_A
F27 VCC1_5_B VCC1_5_A P11
G22 VCC1_5_B VCC1_5_A M17
G23 VCC1_5_B VCC1_5_A M11
G24 VCC1_5_B VCC1_5_A L17
Layout Note: G25 L16
IDE decoupling VCC1_5_B VCC1_5_A
H21 VCC1_5_B VCC1_5_A L14
3D3V_S0 H22 L12
VCC1_5_B VCC1_5_A
J21 VCC1_5_B VCC1_5_A L11 ALL NO_STUFF Caps do
1

J22 VCC1_5_B VCC1_5_A AA21 not have layout

C252 K21 AA20 Place within 100 requirements but if
SC10U10V5ZY-L VCC1_5_B VCC1_5_A mils of ICH pin 3D3V_S0
K22 AA19 layout allows then place *Within a given well, 5VREF needs to be up before the
2

VCC1_5_B VCC1_5_A AG13, AG16

L21 VCC1_5_B
next to ICH6 corresponding 3.3V rail
L22 AA10

PCIE
VCC1_5_B VCC3_3
M21 VCC1_5_B VCC3_3 AG19

1
M22 AG16 5V_S0
VCC1_5_B VCC3_3 C224 C226
N21 VCC1_5_B VCC3_3 AG13
N22 AD17 SCD1U10V2MX-1 SCD1U10V2MX-1

2
VCC1_5_B VCC3_3

1
Layout Note: N23 AC15
VCC1_5_B VCC3_3

IDE
PCI decoupling N24 AA17 D11
3D3V_S0 VCC1_5_B VCC3_3 CH751H-40-U
N25 VCC1_5_B VCC3_3 AA15
P21 AA14 Layout Note: 3D3V_S0
VCC1_5_B VCC3_3
1

P25 AA12 Distribute in PCI section 3D3V_S0 1D5V_ICH_S5 1D5V_S5

12
C225 VCC1_5_B VCC3_3 near pin A2-A6 near D1-H1
P26 VCC1_5_B

1
3 SC10U10V5ZY-L P27 P1 R189 3
2

VCC1_5_B VCC3_3

1
R21 M7 D8 100R2
VCC1_5_B VCC3_3 C435 C253 C254 CH751H-40-U
R22 VCC1_5_B VCC3_3 L7
T21 L4 SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1 Intel 10 ohm

2
VCC1_5_B VCC3_3
T22 J7

2
VCC1_5_B VCC3_3 1D5V_ICH_S5 V5REF_S0

PCI
U21 VCC1_5_B VCC3_3 H7
U22 VCC1_5_B VCC3_3 H1

1
V21 VCC1_5_B VCC3_3 E4
V22 B1 C235 C234
VCC1_5_B VCC3_3

1
W21 A6 SCD1U16V SC1U10V3ZY

2
VCC1_5_B VCC3_3 C437 C440
W22 VCC1_5_B
Y21 U7 SCD1U10V2MX-1 SCD1U10V2MX-1Layout Note:

2
1D5V_S0 VCC1_5_B VCCSUS1_5 Place near U7
Y22 VCC1_5_B VCCSUS1_5 R7
1D5V_ICH_S5 3D3V_S5 5V_S5
AA6 VCC1_5_A 1D5V_S0

USB
AB4 VCC1_5_A VCCSUS1_5 G19
1

1
Place within 100 C442 NO_STUFF NO_STUFF AB5 VCC1_5_A

1
mils of ICH SCD1U10V2MX-1 C445 C237 AB6 G20 ICH_VCC1_5 R480
VCC1_5_A VCC1_5_A

1
near pin AG5 SCD1U10V2MX-1 SCD1U10V2MX-1 AC4 F20 C418 10R2
2

VCC1_5_A VCC1_5_A

1
SCD1U10V2MX-1 D28 Intel 10 ohm
DY DY DY AD4 E24

2
VCC1_5_A VCC1_5_A C407 C406 CH751H-40-U
AE4 E23

USB CORE

2
VCC1_5_A VCC1_5_A SCD1U10V2MX-1 SCD1U10V2MX-1
AE5 E22

2
VCC1_5_A VCC1_5_A Place both V5REF_S5
AF5 E21

12
VCC1_5_A VCC1_5_A

1
1D5V_S0 AG5 E20 within 100 mils
SATA

Place within 100 VCC1_5_A VCC1_5_A of ICH near D27 C391 C408
VCC1_5_A D27
mils of ICH AA7 D26 SCD1U16V SC1U10V3ZY

2
near pin AG9 VCC1_5_A VCC1_5_A
AA8 VCC1_5_A VCC1_5_A D25
1

C444 NO_STUFF NO_STUFF AA9 D24

SCD1U10V2MX-1 C238 C443 VCC1_5_A VCC1_5_A
AB8 VCC1_5_A
2 1D5V_S0 1D5V_GPLL_ICH_S0 SCD1U10V2MX-1 SCD1U10V2MX-1 V2D5S_PCI_IDE 2D5V_S0 2
AC8 G8
2

VCC1_5_A VCC1_5_A
G32 DY DY DY AD8 G65
VCC1_5_A
1 2 AE8 AB18 1 2
PCI/IDE

VCC1_5_A VCC2_5

1
AE9 P7 1D5V_ICH_S0
VCC1_5_A VCC2_5
1

Place within 100 GAP-CLOSE-PWR AF9 C427 GAP-CLOSE-PWR

VCC1_5_A SCD1U10V2MX-1
REF

mils of ICH C210 C211 AG9

2
SC10U10V5ZY-L SCD01U16V3KX VCC1_5_A Layout Note: Place within 100
AA18
2

V5REF

1
3D3V_S0 AC27 A8 Place near AB18 mils of ICH
VCCDMIPLL V5REF V5REF_S0 C217
E26 VCC3_3
F21 V5REF_S5 SCD01U16V3KX

2
1D5V_S0 1D5V_ICH_S0 V5REF_SUS 3D3V_S5
AE1 VCCSATAPLL
1

G37 AG10 A25 ICH6_VCCLAN1D5V

Place within 100 VCC3_3 VCCUSBPLL 1D5V_S0
C426 1 2 A24
mils of ICH SCD1U10V2MX-1 VCCSUS3_3 Place within 100
A13
2

VCCLAN3_3/VCCSUS3_3
1

1
near E26, E27 GAP-CLOSE-PWR F14 AB3 mils of ICH
C456 VCCLAN3_3/VCCSUS3_3 VCCRTC C218
G13 VCCLAN3_3/VCCSUS3_3
Place within 100 SCD1U10V2MX-1 G14 SCD1U10V2MX-1
ICH6_VCCLAN3D3V
2

2
mils of ICH VCCLAN3_3/VCCSUS3_3 ICH6_VCCLAN1D5V
3D3V_S0 pin AE1
DY VCCLAN1_5/VCCSUS1_5 G11
A11 VCCSUS3_3 VCCLAN1_5/VCCSUS1_5 G10
U4 Place within 100 RTC_AUX_S5
VCCSUS3_3 mils of ICH
V1 VCCSUS3_3 V_CPU_IO AG23
Place within 100 V7 AD26 pin G10 Layout Note:
VCCSUS3_3 V_CPU_IO
1

mils of ICH W2 AB22 Place near AB3

VCCSUS3_3 V_CPU_IO VCCP_GMCH_S0

1
pin AG10 C236 Y7 VCCSUS3_3
1

SCD1U10V2MX-1 G16 C453 C454

3D3V_S0
2

VCCSUS3_3 C410 SCD1U10V2MX-1 SCD1U10V2MX-1

A17 G15 DY

2
VCCSUS3_3 VCCSUS3_3 SCD1U10V2MX-1
B17 F16
2

VCCSUS3_3 VCCSUS3_3
C17 VCCSUS3_3 VCCSUS3_3 F15
Intel dummy F18 E16 Layout Note:
1 VCCSUS3_3 VCCSUS3_3 1
G17 D16 Place near AG23
Place within 100 VCCSUS3_3 VCCSUS3_3
G18 VCCSUS3_3 VCCSUS3_3 C16
mils of ICH
pin A13 Place within 100 3D3V_S5 Wistron Corporation
3D3V_S5 mils of ICH ICH6M 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
pin V7 Taipei Hsien 221, Taiwan, R.O.C.
1

1
Title
1

C416 C419 C415 C223

C441 SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1 SCD1U10V2MX-1 ICH6-M (3 of 4)
2

SCD1U10V2MX-1 NO_STUFF NO_STUFF Place within 100 Size Document Number Rev
2

pin
mils
A17of ICH A3
Leopard 3 -1
Date: Monday, August 15, 2005 Sheet 18 of 41
A B C D E
 A B C D E

3D3V_S0
U35D
3,5,7,9,11,13,14,16,17,18,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41 3D3V_S0
3D3V_S5 E27 F4
VSS VSS
Y6 VSS VSS F22
17,18,21,25,29,31,35,37,39,40 3D3V_S5 Y27 VSS VSS F19
Y26 VSS VSS F17
5V_S0 Y23 E25
VSS VSS
W7 VSS VSS E19
13,14,18,20,21,23,24,27,28,29,32,36,39,40,41 5V_S0 W25 VSS VSS E18
W24 VSS VSS E15
W23 VSS VSS E14
4 W1 VSS VSS D7 4
V4 VSS VSS D22
V27 VSS VSS D20
V26 VSS VSS D18
V23 VSS VSS D14
U25 VSS VSS D13
U24 VSS VSS D10
U23 VSS VSS D1
U15 VSS VSS C4
U13 VSS VSS C22
T7 VSS VSS C20
T27 VSS VSS C18
T26 VSS VSS C14
T23 VSS VSS B25
T16 VSS VSS B24
T15 VSS VSS B23
T14 VSS VSS B21
T13 VSS VSS B19
T12 VSS VSS B15
T1 VSS VSS B13
R4 AG7

VSS
VSS VSS
R25 VSS VSS AG3
R24 VSS VSS AG22
R23 VSS VSS AG20
R17 VSS VSS AG17
R16 VSS VSS AG14
R15 VSS VSS AG12
R14 VSS VSS AG1
R13 VSS VSS AF7
3 R12 AF3 3
VSS VSS
R11 VSS VSS AF26
P22 VSS VSS AF12
P16 VSS VSS AF10
P15 VSS VSS AF1
P14 VSS VSS AE7
P13 VSS VSS AE6
P12 VSS VSS AE25
N7 VSS VSS AE21
N17 VSS VSS AE2
N16 VSS VSS AE12
N15 VSS VSS AE11
5V_S0 N14 AE10
VSS VSS
N13 VSS VSS AD6
N12 VSS VSS AD24
U61A

14
N11 VSS VSS AD2
N1 VSS VSS AD18
PLT_RST# 1 M4 AD15
RSTDRV#_R VSS VSS
3 1 2 RSTDRV#_5 21 M27 VSS VSS AD10
2 R511 33R2 M26 AD1
VSS VSS
M23 VSS VSS AC6
TSAHCT32 M16 AC3

7
VSS VSS
M15 VSS VSS AC26
M14 VSS VSS AC24
M13 VSS VSS AC23
M12 VSS VSS AC22
L25 VSS VSS AC12
L24 VSS VSS AC10
2 PCIRST# 3V to 5V level shift for HDD & CDROM L23 VSS VSS AB9
2
L15 VSS VSS AB7
L13 VSS VSS AB2
K7 VSS VSS AB19
K27 VSS VSS AB10
K26 VSS VSS AB1
K23 VSS VSS AA4
K1 AA16
SMBUS(ICH6 ---> SODIMM,CLKGEN) 3D3V_S0
J4
VSS
VSS
VSS
VSS AA13
J25 VSS VSS AA11
J24 VSS VSS A9
J23 VSS VSS A7
3D3V_S0 U37B

14
H27 VSS VSS A4
H26 VSS VSS A26
4 H23 VSS VSS A23
6 PLT_RST#_R 1 2 G9 A21
33R2 PLT_RST1# 7,21 VSS VSS
5 R187 G7 A19
3D3V_S0 17 PLT_RST# VSS VSS
G21 VSS VSS A15
TSLCX08-U ICH6 asserts PLTRST# to reset G12 A12
7

VSS VSS
1
2

G1 A1
RN31 devices on the platform. VSS VSS
3D3V_S5 SRN4D7KJ
ICH6M
3D3V_S0
4
3

U37C
14
1
2

SMB_ICH_CTL 9
RN32 8 ICH_PCIRST#_R 1 2
1 U32 SMBD_ICH 3,11 33R2 PCIRST1# 22,23,25,29,31 1
SRN10KJ 10 R188
17 ICH_PCIRST#
4 3 TSLCX08-U Secondary PCI Bus reset signal.
Wistron Corporation
7

om
4
3

5 2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

l.c
Taipei Hsien 221, Taiwan, R.O.C.

ai
17,21 SMB_CLK 6 1 SMBC_ICH 3,11

tm
Title

ho
PCIRST# Buffer to enhance the driving strength ICH6-M (4 of 4)

f@
2N7002DW Size Document Number Rev
17,21 SMB_DATA

in
A3
Leopard 3 -1

xa
he
Date: Monday, August 15, 2005 Sheet 19 of 41
A B C D E
 A B C D E

3D3V_S0

3,5,7,9,11,13,14,16,17,18,19,21,22,23,24,25,27,29,30,31,32,36,38,40,41 3D3V_S0
3D3V_S5

17,18,19,21,25,29,31,35,37,39,40 3D3V_S5
Reserve for G768B 3D3V_AUX
works at High
Speed 16,31,32,34,35,36,37 3D3V_AUX
5V_S0 5V_G768_S0 Close to G768D 5V_S0
4 G8 5V_G768_S0 4
1 2 13,14,18,19,21,23,24,27,28,29,32,36,39,40,41 5V_S0
GAP-CLOSE-PWR 1 5V_S5

1
U6
EC12 BC7 BC5
SC10U10V6ZY-U 14,18,36,38 5V_S5
SC1000P50V SCD1U16V VCC_FAN 1 16
2

2
FANVCC TH_SHUT
DY 2 VCC VCC 15
SMBC_G768D
4 THERMDP1 3 DXP1 SMBCLK 14
4 THERMDN 4 DXN NC 13
THERMDP2 5 12 SMBD_G768D
RUNPWROK DXP2 SMBDATA
1 2 G768_RST# 6 RESET# ALERT# 11 PM_THRM# 17
R31 4K7R2 7 10 FAN_FB
GND FG

1
8 AGND CLK 9
R32 CLK32_G768 31
10KR2
G768D

2
R47:5K SET TO 120°C
Must close to MAX6509
SD 0817 3D3V_S0
U4

M6509_SET 1 5
SET VCC 5V_S5
2 GND

1
U65 3 4
R19 OUT# HYST C30
Put these two Caps near the thermal diode. 1 NC VCC 5
2 22KR3F SCD1U25V3KX
3,36 CLK_PWRGD#

2
3 A VRM_PWRGD 3D3V_AUX 3
3 4 MAX6509HAUK-T-U
GND Y

2
SD 0817 NC7S14-U
THERMDP2 THERMDP1
DY Put under CPU Socket

3
1

1
Q5 D3
BC9 1 BC1 R47 BAT54-1
SC470P50V3JN RSMRST# 16,31,39
SC470P50V3JN 10KR2 DY 3D3V_AUX
2

DY S2N3904-U3 DY
2

THERMDN 0R0402-PAD U13

2
36 VGATE 1 R532 2 PWROK 7 1 A VCC 5
SYSTEM SENSOR

1
0R0402-PAD 2
31 S5_ENABLE B
1 R533 2 VRM_PWRGD 17
BC6
SCD1U16V 3 4 1999_S5ENABLE 37,38

2
GND Y
THERMDP1 THERMDP2
DY
NC7S08-U
1

BC8 BC4
SC2K2P SC2K2P
2

THERMDN THERMDN 3D3V_S0

THERMDP1/DP2/THERMDN ON THE SAME LAYER U37D

14

2 W/S = 10/5 MIL, 12 MIL AWAY FROM OTHERS RUNPWROK 2

12
CAPS CLOSE TO G768B 11 ICH6_PWROK 17
38 VCCP_PWGD 13
TSLCX08-U
7

180 ms after VCC_G768 > 4.38v, p2, 7

5V_S0

5V_S0
1

1
2
R435 RN1
10KR2 SRN10KJ
FAN1
5
2

3 FAN_FB
4
3

1 VCC_FAN
4
3

SMBD_G768D
1

ETY-CON3-S1 D26 BC67 31 SMBD_KBC

S1N4148-U2 BC65 BC66 SCD1U16V
2

SC10U10V6ZY-U SCD1U16V
2

1 1
1

SMBC_G768D Wistron Corporation

The symbol use 2nd source 31 SMBC_KBC 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
The P/N is the main source Taipei Hsien 221, Taiwan, R.O.C.
Main source:20.D0152.103
Title
2nd source:20.D0012.103
G768D
Size Document Number Rev
A3
Leopard 3 -1
Date: Monday, August 15, 2005 Sheet 20 of 41

A B C D E
 A B C D E

3,5,7,9,11,13,14,16,17,18,19,20,22,23,24,25,27,29,30,31,32,36,38,40,41 3D3V_S0 3D3V_S0

HDD Connector
25,41 3D3V_LAN_S5 3D3V_LAN_S5

13,14,18,19,20,23,24,27,28,29,32,36,39,40,41 5V_S0 5V_S0

HDD1
47

CDROM
5,7,9,17,18,38,39,41 1D5V_S0 1D5V_S0
16 IDE_D[15..0] 45
2 1 PBRSTDRV1#_5
RSTDRV#_5 19
IDE_D8 4 3 IDE_D7 CN16
IDE_D9 6 5 IDE_D6 5V_S0 51
IDE_D10 8 7 IDE_D5 3D3V_S0 MH1
4 IDE_D11 10 9 IDE_D4 3D3V_S0 2 1 4
27 CD_AUDR CD_AUDL 27
IDE_D12 12 11 IDE_D3

1
IDE_D13 14 13 IDE_D2 4 3 CD_AGND 27

1
IDE_D14 16 15 IDE_D1 R421 R401 IDE_D8 6 5 RSTDRV#_5
IDE_D15 18 17 IDE_D0 R425 4K7R2 4K7R2 IDE_D9 8 7 IDE_D7
20 19 4K7R2 IDE_D10 10 9 IDE_D6
22 21 DY IDE_D11 12 11 IDE_D5

2
IDE_DREQ 16 IDE_D12 IDE_D4
24 23 IDE_IOW# 16 14 13

2
26 25 5V_S0 IDE_D13 16 15 IDE_D3
IDE_IOR# 16
HDDCSEL1 28 27 IDE_D14 18 17 IDE_D2
IDE_IORDY 16
30 29 PBIDDACK# 1 R424 2 0R0402-PAD IDE_D15 20 19 IDE_D1
IDE_DACK# 16
1

2
32 31 IDE_DREQ 22 21 IDE_D0
R400 DIAG IDE_IRQ14 16 R423 IDE_IOR#
34 33 IDE_A1 16 24 23
470R2 36 35 10KR2 26 25 IDE_IOW#
16 IDE_A2 IDE_A0 16
38 37 IDE_DACK# 28 27 IDE_IORDY
16 IDE_CS#1 IDE_CS#0 16
40 39 HDD_LED# TPAD30 TP35 BAY_ID0 30 29 IDE_IRQ14
HDD_LED# 14
2

1
42 41 DIAG 32 31 IDE_A1 5V_S0
44 43 IDE_A2 34 33 IDE_A0

1
46 IDE_CS#1 36 35 IDE_CS#0

2
48 R422 38 37
2K7R2J 5V_S0 CDROM_LED# 14
5V_S0 40 39 R230
SPD-CONN44D-3-U1 10KR2
20.F0362.044
DY 42 41 5V_S0
44 43

2
46 45

1
48 47 CSEL CDROM_CSEL

1
50 49

1
5V_S0 C258 MH2
1

2
SCD1U16V 52 R196

2
C354 D25 DUMMY-R2
3 SCD1U16V C353 SSM24L-U SYN-CONN50-4R3GP DY 3
2

1
SC10U10V5ZY-L DY BC38 PIN 49,50 DON'T USE
1

2
SC10U10V6ZY-U

2
The symbol use 2nd source
1013 -1 The P/N is the main source
Main source:20.10150.050
2nd source:20.B0040.050

3D3V_S0

NEWCARD Connector SKT3

IDE_IRQ14 1
R229
2
8K2R2

1 2
Place them Near to Chip Place them Near to Connector

3D3V_S5 1D5V_S0 3D3V_NEW_S0 1D5V_NEW_S0 3D3V_NEW_LAN_S5 3 4

CARD-SKT21-U2
1

For Newcard socket

C215 C216 C232 C231 C221 C220 C219
SCD1U16V SCD1U16V SC10U10V5ZY-L SCD1U16V SC10U10V5ZY-L SCD1U16V SCD1U16V
2

2 DY DY 2

CN14
26
3D3V_S5 25
17 PCIE_TXP0
RN30 17 PCIE_TXN0 24
2 3 CPPE# MH2
1 4 CPUSB# 23
U34 PCIE_RXP0_R 22
17 PCIE_RXP0
SRN100KJ PCIE_RXN0_R 21
17 PCIE_RXN0
19 14 CPUSB# 20
1D5V_S0 1.5VIN CPUTSB#
18 15 CPPE# 19
1.5VIN CPPE# 3 CLK_PCIE_NEW
STBY# 4 PM_SLP_S3# 17,28,31,37,38,40 3 CLK_PCIE_NEW# 18
17 3 3D3V_S0 17
1D5V_NEW_S0 1.5VOUT SHDN# PM_SLP_S4# 17,31,37,38 17 CPPE#
16 2 TPS2231_RST# CONN_CLKREQ# 16
1.5VOUT SYSRST# TPAD30 TP65
RCLKEN 22 3D3V_NEW_S0 15
1

3D3V_S0 5 3.3VIN 1 2 PLT_RST1# 2N7002-F-GP 14

6 R183 0R2-0 R569 PERST# 13
3.3VIN 10KR2
NC#1 1 Q30 3D3V_NEW_LAN_S5 12
7 10 CONN_WAKE# 11
3D3V_NEW_S0 17 PCIE_WAKE#
SMBUS(ICH6--NEWCARD,LAN)
S

3.3VOUT NC#10
8 12 1D5V_NEW_S0 10
2

3.3VOUT NC#12 CONN_CLKREQ#

NC#13 13 G 9
TP-2 TP26 NEWCARD_OC# 23 24 SMB_DATA_C 8
OC# NC#24 17,19 SMB_DATA
3D3V_S5 21 SMB_CLK_C 7
1 3.3VAUX_IN 17,19 SMB_CLK 1
PERST# 9 11 CONN_TP2 6
PERST# GND TPAD30 TP66 CONN_TP3
3D3V_NEW_LAN_S5 20 25 PREQ2# 3 SD 0817 5
D

AUX_OUT GND TPAD30 TP61 CPUSB# 4

3D3V_S5 MH1 Wistron Corporation

om
TPS2231 U68 3 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
17 USB_PP6

l.c
1 5 2 Taipei Hsien 221, Taiwan, R.O.C.
7,19 PLT_RST1# A VCC 17 USB_PN6

ai
tm
2 1 Title
17 NEWCARD_RST# B

ho
3 4 TPS2231_RST# JAE-CON26-U HDD / CDROM/NEWCARD

f@
GND Y Size Document Number Rev

in
NC7SZ08-U A3
Leopard 3 -1

xa
DY

he
Date: Tuesday, July 12, 2005 Sheet 21 of 41
A B C D E
 A B C D E

INTA# CARBUS 1 3D3V_S0

INTB# NONE
3D3V_S0 INTC# 1394 3,5,7,9,11,13,14,16,17,18,19,20,21,23,24,25,27,29,30,31,32,36,38,40,41 3D3V_S0
U39A 1 of 4
INTD# CARD READER
W3 N3 3D3V_S0
VCCP U1-1 MFUNC0 INT_PIRQG# 17
W10 M5 PCM_INTB# 1 2
VCCP MFUNC1 R237 0R2-0
13,17,25,29 PCI_AD[31..0] MFUNC2 P1 INT_PIRQF# 17
MFUNC3 P2 PCI_SERIRQ 17,29,31
PCI_AD31 U2 P3 INT_PIRQG#
PCI_AD30 AD31 MFUNC4 CB_MFUNC5
V1 AD30 MFUNC5 N5 7421_LED 14 Bypass/Decupoling Capacitors
PCI_AD29 V2 R1
AD29 MFUNC6 PM_CLKRUN# 17,25,29,31
4 PCI_AD28 U3 Should be places as close to 4
PCI_AD27 AD28
W2 AD27
PCI_AD26 V3 M1 PCI7421 as possible
AD26 CLK_48 CLK48_CARDBUS 3
PCI_AD25 U4
PCI_AD24 AD25 3D3V_PLL_S0
V4 AD24
PCI_AD23 V5
PCI_AD22 AD23 3D3V_S0
U5 AD22 AVDD R13
PCI_AD21 R6 U1-7 R14
PCI_AD20 AD21 AVDD
P6 AD20 AVDD V17
PCI_AD19 W6 AD19

1
PCI_AD18 V6 V19 VDPLL_33
PCI_AD17 AD18 VDPLL_33 C270 C247 C248 C249
U6 AD17 VSSPLL P14
PCI_AD16 R7 C242 SCD1U16V SC1000P50V SCD1U16V SCD1U16V SCD1U16V

2
PCI_AD15 AD16 VDPLL_15
PCI_AD14
V9 AD15 VDPLL_15 T18 1 2 DY DY
U9 AD14 VSSPLL T17
PCI_AD13 R9
PCI_AD12 AD13 * All 1394 signals must be routed on top side only
N9 AD12
PCI_AD11 V10 U18 1394_R0 1 2 * Differential pairs of each ports should have equal trace length 3D3V_S0

CARD BUS
PCI_AD10 AD11 R0 6K34R3F * Stubs must be keep as short as possible
U10 AD10 R1 U19 1394_R1 R198
PCI_AD9 R10
PCI_AD8 AD9
N10 AD8 TPBIAS0 U15 1394_TPBIAS0 26

1
PCI_AD7 V11
PCI_AD6 AD7 C269 C271 C260 C261
U11 AD6 TPA0P V15 1394_TPA0P 26
PCI_AD5 R11 W15 SC1000P50V SCD1U16V SCD1U16V SCD1U16V
1394_TPA0N 26

2
PCI_AD4 AD5 TPA0N
PCI_AD3
W12 AD4 DY DY
V12 V14

1394
AD3 TPB0P 1394_TPB0P 26
PCI_AD2 U12 W14
AD2 TPB0N 1394_TPB0N 26
PCI_AD1 N11
PCI_AD0 AD1
W13 AD0 PHY_TEST_MA R17 1394_PHYTEST
1 2 R232
3
CPS M11 1394_CPS 4K7R2
3D3V_S0
3
W11 P15 1394_CNA
1 2 R231 3D3V_S0 3D3V_PLL_S0
17,25,29 PCI_C/BE#0 C/BE0# CNA
W9 4K7R2 G34
17,25,29 PCI_C/BE#1 C/BE1#
W7 R19 1394_XO 1 2 1 2
17,25,29 PCI_C/BE#2 C/BE2# XO
W4 R18 1394_XI C243 SC12P
17,25,29 PCI_C/BE#3 C/BE3# XI

1
GAP-CLOSE-PWR
R12 PC[2:0]=000 X2 C228 C229 C227
PC0(TEST1) X-24D576M-2 SC10U10V5ZY-L SC1000P50V SC1U10V3KX
17,25,29 PCI_PAR P9 U13

2
PAR PC1(TEST2)
17,25,29 PCI_FRAME# V7 V13

1
FRAME# PC2(TEST3)
17,25,29 PCI_TRDY# R8 TRDY# 1 2
U7 C259 SC15P
17,25,29 PCI_IRDY# IRDY#
17,25,29 PCI_STOP# W8 STOP# AGND N12
17,25,29 PCI_DEVSEL# N8 DEVSEL# AGND U14
PCI_AD22 1 2CS_IDSEL W5 U16
R210 100R2 IDSEL AGND
17,25,29 PCI_PERR# V8 PERR#
U8 U17 1394_TPBIAS1 3D3V_S0
17,25,29 PCI_SERR# SERR# TPBIAS1 1394_TPBIAS1 26
17 PCI_REQ#1 U1 REQ#

1
17 PCI_GNT#1 T2 GNT# TPA1P V18 1394_TPA1P 26

1
P5 W18 C240
3 PCLK_PCM PCLK TPA1N 1394_TPA1N 26 SCD1U16V
R3 R184
19,23,25,29,31 PCIRST1#

2
PRST# 1394_TPB1P 10KR2
T1 GRST# TPB1P V16
TPAD30 TP82 7421_PME# T3 W16 1394_TPB1N 1394_TPB1P
RI_OUT#/PME# TPB1N 1394_TPB1P 26
1394_TPB1N
1394_TPB1N 26

2
3D3V_S0
1 2 CS_SUSPEND# R2 SUSPEND#
R211 10KR2 F1 MC_PWR_CTRL# MC_PWR_CTRL#
U1-8 MC_PWR_CTRL_0 MC_PWR_CTRL-1
23 CB_DATA N1 DATA MC_PWR_CTRL_1 F2
L6 TP36 TPAD30
23 CB_CLOCK CLOCK
23 CB_LATCH N2 LATCH
2 2
27 PCI_SPKR L7 SPKROUT SD_CD# E3 SD_CD# 24 SD

1
SD/SDIO

F5 MS/MS_pro 3D3V_S0
MS_CD# MS_CD# 24
F6 U36 3D3V_S0
SM_CD# SM_CD# 24
R233 G5 1 2 2N7002DW
MS_CLK/SD_CLK/SM_EL_WP# 0R2-0 MS_CLK 24
1 10KR2
2 B_USB_EN E1 F3 R570
3D3V_S0 B_USB_EN# MS_BS/SD_CMD/SM_WE# MS_BS 24

1
1 2 A_USB_EN E2 U1-10
R234 10KR2 A_USB_EN# R182
1

2
H5 10KR2
MS_D3 24 D9

6
R236 MS_DATA3/SD_DAT3/SM_D3 R180
M2 SDA MS_DATA2/SD_DAT2/SM_D2 G3 MS_D2 24 MS/MS_pro
150R2 M3 U1-5 G2 XD SD_CD# 1 100KR2
MS_D1 24

2
SCL MS_DATA1/SD_DAT1/SM_D1
UNUSED TERMINALS

MC_PWR_CTRL 24
G1 MS_SDIO 24 3
2

1
MS_SDIO(DATA0)/SD_DAT0/SM_D0 SM_CD# 7421_LED
W17 NC#W17 SD_CLK/SM_RE# J5 SM_RE# 24 2
T19 U1-6 J3
RSVD SD_CMD/SM_ALE SM_ALE 3,4,5,6,7,9,10,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41
P12 TEST0 BAW56-1
3D3V_S0 H3
SD_DAT0/SM_D4 SM_D4 24
SD_DAT1/SM_D5 J6 SM_D5 24 SM
TPAD30 TP85 PCI7421_TP1 L5 J1
RSVD SD_DAT2/SM_D6 SM_D6 24
L2 RSVD SD_DAT3/SM_D7 J2 SM_D7 24
TPAD30 TP84 PCI7421_TP2 K5 U1-9
TPAD30 TP86 PCI7421_TP3 RSVD
K3 RSVD SD_WP/SM_CE H7 SD_WP 24
K7 RSVD SM_CLE J7 SM_CLE 24
TPAD30 TP37 PCI7421_TP5 L1 K1
RSVD SM_R/B# SM_R/B# 3,4,5,6,7,9,10,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41
L3 RSVD SM_PHYS_WP# K2

PCI7411

1 1

7411:71.07411.00U Wistron Corporation

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
7421:71.07421.00U Taipei Hsien 221, Taiwan, R.O.C.

Title
TI SNC1Q21 (1 of 2)
Size Document Number Rev
A3
Leopard 3 -1
Date: Monday, August 15, 2005 Sheet 22 of 41
A B C D E
 A B C D E

3D3V_S0

3,5,7,9,11,13,14,16,17,18,19,20,21,22,24,25,27,29,30,31,32,36,38,40,41 3D3V_S0
5V_S0

13,14,18,19,20,21,24,27,28,29,32,36,39,40,41 5V_S0

VCC_ASKT_S0 U39C 3 of 4
2 of 4 C448
U39B 1 2 SCD01U16V3KX
4
VCCA
VCCA
A5
A11
RSVD
RSVD
D19
K19

B15
Power switch 4

RSVD VPP_ASKT_S0 VCC_ASKT_S0

RSVD A16
A_CAD31/A_D10 D1 CBB_D10 24 RSVD B16
A_CAD30/A_D9 C1 CBB_D9 24 RSVD A17
A_CAD29/A_D1 D3 CBB_D1 24 RSVD C16

1
A_CAD28/A_D8 C2 CBB_D8 24 RSVD D17

1
B1 C19 R497 C449 C433
A_CAD27/A_D0 CBB_D0 24 RSVD 100KR2 SCD1U16V SC4D7U10V5ZY
B4 D18 C450
CBB_A0 24

2
A_CAD26/A_A0 RSVD SCD1U16V
A4 CBB_A1 24 E17

2
A_CAD25/A_A1 RSVD
E6 CBB_A2 24 E19

2
A_CAD24/A_A2 RSVD
A_CAD23/A_A3 B5 CBB_A3 24 RSVD G15
A_CAD22/A_A4 C6 CBB_A4 24 RSVD F18
B6 H14 PCIRST1#
A_CAD21/A_A5 CBB_A5 24 RSVD
A_CAD20/A_A6 G9 CBB_A6 24 RSVD H15

1
C7 U1-3 G17
A_CAD19/A_A25 CBB_A25 24 RSVD
B7 K17 C451
A_CAD18/A_A7 CBB_A7 24 RSVD SC100P50V2JN-U
A7 CBB_A24 24 L13

2
A_CAD17/A_A24 RSVD VCC_ASKT_S0
A10 CBB_A17 24 K18 DY U60
A_CAD16/A_A17 RSVD
A_CAD15/A_IOWR# E11 CBB_IOWR# 24 RSVD L15
G11 CBB_A9 24 L17 3 9
A_CAD14/A_A9
C11
RSVD
L18 5V_S0 22 CB_DATA
4
DATA AVCC
10

CARDBUS B
A_CAD13/A_IORD# CBB_IORD# 24 RSVD 22 CB_CLOCK CLOCK AVCC
A_CAD12/A_A11 B11 CBB_A11 24 RSVD L19 22 CB_LATCH 5 LATCH
U1-2 C12 M17 12
A_CAD11/A_OE# CBB_OE# 24 RSVD 19,22,25,29,31 PCIRST1# RESET#
B12 M14 1 2 PS_SHDN# 21 8
A_CAD10/A_CE2# CBB_CE2# 24 RSVD 3D3V_S0 10KR2 SHDN# AVPP VPP_ASKT_S0
A12 M15 R498
A_CAD9/A_A10 CBB_A10 24 RSVD
A_CAD8/A_D15 E12 CBB_D15 24 RSVD N19
3 C13 N18 13 15 3
A_CAD7/A_D7 CBB_D7 24 RSVD 3.3V OC#
A_CAD6/A_D13 F12 CBB_D13 24 RSVD N15
A13 M13 5V_S0
A_CAD5/A_D6 CBB_D6 24 RSVD

1
A_CAD4/A_D12 C14 CBB_D12 24 RSVD P18 1 5V
C452 C434
CARDBUS A

A_CAD3/A_D5 E13 CBB_D5 24 RSVD P17 2 5V NC 24

A14 P19 SCD1U16V SC4D7U10V5ZY 23
CBB_D11 24

2
A_CAD2/A_D11 RSVD NC
A_CAD1/A_D4 B14 CBB_D4 24 DY NC 22

1
A_CAD0/A_D3 E14 CBB_D3 24 7 12V NC 19
F15 C447 C446 20 18
RSVD SCD1U16V SC1U10V3ZY 12V NC
G18 17

2
RSVD NC
A_CC/BE3#/A_REG# C5 CBB_REG# 24 RSVD K14 NC 16
A_CC/BE2#/A_A12 F9 CBB_A12 24 RSVD M18 11 GND NC 14
A_CC/BE1#/A_A8 B10 CBB_A8 24 25 GND NC 6
A_CC/BE0#/A_CE1# G12 CBB_CE1# 24 RSVD K13

G10 G19 TSP2220A

A_CPAR/A_A13 CBB_A13 24 RSVD
RSVD H17
A_CFRAME#/A_A23 C8 CBB_A23 24 RSVD J13
A_CTRDY#/A_A22 A8 CBB_A22 24 RSVD J17
A_CIRDY#/A_A15 B8 CBB_A15 24 RSVD H19
A9 J19 3D3V_S0
A_CSTOP#/A_A20 CBB_A20 24 RSVD
A_CDEVSEL#/A_A21 C9 CBB_A21 24
E10 J18 U39D 4 of 4
A_CBLOCK#/A_A19 CBB_A19 24 RSVD
RSVD B18
A_CPERR#/A_A14 F10 CBB_A14 24 H8 VCC
A_CSERR#/A_WAIT# B3 CBB_WAIT# 24 RSVD E18 H9 VCC
RSVD J15 H10 VCC
A_CREQ#/A_INPACK# E7 CBB_INPACK# 24 H11 VCC VR_PORT M19 PT_PORT
A_CGNT#/A_WE# B9 CBB_WE# 24 RSVD F14 H12 VCC VR_PORT H1 VR_PORT
2 2
RSVD A18 J8 VCC
A_CSTSCHG/A_BVD1(STSCHG#/RI#) B2 CBB_BVD1# 24 RSVD H18 M7 VCC
A_CCLKRUN#/A_WP(IOIS16#) C3 CBB_WP 24 J12 VCC VR_EN# H2
A_CCLK/A_A16 E9 CBB_A16 24 RSVD B19 M9 VCC
RSVD F17 M10 VCC
C4 C17 M12

POWER TERMINALS
A_CINT#/A_READY(IREQ#) CBB_RDY 24 RSVD VCC

1
A6 K8 C262
A_CRST#/A_RESET CBB_RESET 24 VCC
N13 K12 C263 SCD1U16V
RSVD VCC SCD1U16V
A2 CBB_BVD2# 24 B17 N7

2
A_CAUDIO/A_BVD2(SPKR#) RSVD VCC
RSVD C18
A_CCD1#/A_CD1# C15 CBB_CD1# 24 RSVD F19
A_CCD2#/A_CD2# E5 CBB_CD2# 24 G7 GND
A_CVS1/A_VS1# A3 CBB_VS1# 24 RSVD N17 G8 GND
A_CVS2/A_VS2# E8 CBB_VS2# 24 RSVD A15 G13 GND
RSVD K15 H13 GND
A_RSVD/A_D14 B13 CBB_D14 24 J9 GND
A_RSVD/A_D2 D2 CBB_D2 24 J10 GND
C10 PCI7411 J11
A_RSVD/A_A18 CBB_A18 24 GND
K9 GND
K10 U1-4
PCI7411 GND
K11 GND
L8 GND
L9 GND
L10 GND
L11 GND
L12 GND
M8 GND
1 1

PCI7411

Wistron Corporation

om
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

l.c
Taipei Hsien 221, Taiwan, R.O.C.

ai
tm
Title

ho
TI PCI7411 GHK (2 of 2)

f@
Size Document Number Rev

in
A3
Leopard 3 -1

xa
he
Date: Tuesday, July 12, 2005 Sheet 23 of 41
A B C D E
 A B C D E

3D3V_S0

Cardbus I/F 3,5,7,9,11,13,14,16,17,18,19,20,21,22,23,25,27,29,30,31,32,36,38,40,41 3D3V_S0

DCBATOUT

PCMCIA Socket CBB_D[0..15] 23

CBB_A[0..25] 23 14,35,37,38,39,40,41 DCBATOUT
CBUS1 CBB_IORD# 23
CBB_IOWR# 23
CBB_OE# 23
69 CBB_WE# 23
CBB_REG# 23
4 1 CBB_RDY 23 4
CBB_WP 23
35 CBB_RESET 23
CBB_D3 2 CBB_WAIT# 23
CBB_CD1# 36 CBB_INPACK# 23
CBB_D4 3
CBB_D11
CBB_D5
CBB_D12
37
4
38
CBB_CE1# 23
CBB_CE2# 23
6 in 1 Connector
CBB_D6 5 3D3V_CR_S0
CBB_BVD1# 23
CBB_D13 39 CBB_BVD2# 23
CBB_D7 6 CBB_CD1# 23
CBB_D14 40 CBB_CD2# 23

1
CBB_CE1# 7 C370
CBB_VS1# 23
CBB_D15 41 C359 C377 C360 SCD01U16V3KX
CBB_VS2# 23
CBB_A10 8 SCD01U16V3KX SCD01U16V3KX SCD01U16V3KX

2
CBB_CE2# 42
VCC_ASKT_S0 CBB_OE# 9 SKT2
CBB_VS1# 43
CBB_A11 10 40 2
CBB_IORD# XD-VCC SM-CD-COM SM_CD#
44 29 S.M-VCC SM-CD-SW 3
CBB_A9 11 VCC_ASKT_S0 20 43 MS_CLK_R0
CBB_IOWR# MS-VCC SM-WP-SW
45 9 SD-VCC
CBB_A8 12 13 MS_BS_1
MS-BS
1

1
CBB_A17 46 17 MS_CD# MS_CD# 22
C432 C429 CBB_A13 R212 MS_SDIO R576 33R2 MS-INS MS_CLK_R 1
13 1 2 7 SD-DAT0 MS-SCLK 19 2 MS_CLK MS_CLK 22
SC22U10V6ZY-U C431 SCD1U16V CBB_A18 47 DUMMY-R2 MS_D1 R577 1 2 33R2 6 R449 33R2
2

SC1000P50V CBB_A14 MS_D2 R578 33R2 SD-DAT1

CBB_A19
14 DY MS_D3 R579
1 2
33R2
12 SD-DAT2 RSV#4 4
SM_CD#
3 CBB_WE#
48 47K 1 2 11 SD-DAT3 XD-CD 39
3
15

2
CBB_A20 49 CBB_RESET 41
CBB_RDY 22 MS_SDIO MS_SDIO15 SD-CD-COM SD_CD#
16 MS-DATA0 SD-CD-SW 42 SD_CD# 22

1
CBB_A21 50 22 MS_D1 MS_D1 14 5 SD_WP
MS-DATA1 SD-WP-SW SD_WP 22
17 C250 22 MS_D2 MS_D2 16 8 MS_CLK
VPP_ASKT_S0 SCD01U16V3KX 22 MS_D3 MS_D3 18 MS-DATA2 SD-CLK MS_BS
51 10 1 2

2
MS-DATA3 SD-CMD R584 33R2
18
52 38 SM_CLE
S.M#/XD-CLE SM_CLE 22
CBB_A16 19 MS_D1 33 37 SM_ALE
S.M/XD-D1 S.M#/XD-ALE SM_ALE 22
1

CBB_A22 53 MS_D2 32 36 MS_BS_1 1 2

3D3V_CR_S0 3D3V_CR_S0 S.M/XD-D2 S.M#/XD-WE 22R2 MS_BS 22
C430 CBB_A15 20 MS_D3 31 28 SD_WP R564
SCD1U16V CBB_A23 22 SM_D4 SM_D4 S.M/XD-D3 S.M#/XD-CE SM_RE#
54 21 27 SM_RE# 22
2

CBB_A12 22 SM_D5 SM_D5 S.M/XD-D4 S.M#/XD-RE SM_R/B#

21 22 S.M/XD-D5 S.M#/XD-R/B 26 SM_R/B# 22
CBB_A24 55 22 SM_D6 SM_D6 23 35 MS_CLK_R0
S.M/XD-D6 S.M/XD-WP-IN

1
CBB_A7 22 22 SM_D7 SM_D7 24
CBB_A25 R562 R563 S.M/XD-D7
56
CBB_A6 23 22KR2J 22KR2J 46 1 2 MS_CLK_R
CBB_VS2# GND
CBB_A16 CBB_A5
57
22 SM_CD# SM_CD#
DY 25 S.M-LVD GND 45
R440 330R2
24 1 2 30 44

2
CBB_RESET MS_SDIO R555 0R2-0 S.M-CD# GND
58 34 S.M-D0 GND 1
1

CBB_A4 25 SM_RE# MS_BS

R186 CBB_WAIT# 59
DUMMY-R2 CBB_A3
DY CBB_INPACK#
26
SKT-MEMO-12-GP
60
CBB_A2 27 3D3V_CR_S0 3D3V_CR_S0 3D3V_S0
CBB_REG# 61
1 2

Place close to pin 19. CBB_A1 28 U30

CBB_BVD2# 62 3D3V_CR_S0
1

1
C233 CBB_A0 29
2 DUMMY-C2 CBB_BVD1# R565 R566 2
63 1 OUT IN 5
CBB_D0 22KR2J 22KR2J
DY CBB_D8
30 DY DY 2 GND
64 3 SET ON# 4
CBB_D1 31
2

1
CBB_D9 65 22

1
CBB_D2 32 SM_ALE SM_CLE AAT46101GV-1 MC_PWR_CTRL
CBB_D10 66 R589 C169

1
CBB_WP 33 4K7R2 SCD1U16V
Clock AC termination

1
CBB_CD2# 67 R583

2
34 3D3V_CR_S0 15KR2 C185
33MHz clock for 32-bit 68 3D3V_CR_S0 SC1U10V3ZY

2
Cardbus card I/F

2
70
1
1

R568
R567 47KR2
CARDBUS68P-9 22KR2J
62.10024.491 5V_S0
2
2

SD_WP
SKT1 SM_R/B#
1 2
U67
3 4 MS_CLK 1 5
A VCC
CARDBUS-SKT45-U1 MS_CLK_R 2 DY
B
3 4 SD_CD#
GND SE
1 1
NC7SZ66P5X

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
PCMCIA SLOT/ CARDBUS SKT
Size Document Number Rev
A3
Leopard 3 -1
Date: Tuesday, July 12, 2005 Sheet 24 of 41
A B C D E
 A B C D E

3D3V_LAN_S5
Close to RTL8100C AVDD25
PCI_C/BE#[0..3] 17,22,29
1 2 VDD25
Pin121,Pin122 R111 3K6R3
PCI_AD[0..31] 13,17,22,29

1
U29
LAN_X1 EECS_3 1 8 C168 1 2
EESK CS VCC SCD1U16V R100 0R3-U
2 7

2
EEDI SK DC
3 DI ORG 6
R110 EEDO 4 5
DO GND

1
LAN_X2 1 2
M93C46-W-3 C135
DUMMY-R2 SCD1U16V

2
X5
4 1 2 4

XTAL-25MHZ-43
1

1
R108
C145 C144 5K6R3F
SC12P50V2JN SC12P50V2JN 2 1 3D3V_LAN_S5
2

TP23 3D3V_LAN_S5
TPAD30
TP21 TP22
TPAD30 TPAD30

1
TX+ TX- RX- RX+ C143 C148 C150 C141 C151 C153 C133
SCD1U16V SCD1U16V SCD1U16V SCD1U16V

LAN_X2

LAN_X1

2
1

SCD1U16V SCD1U16V SCD1U16V

1

R106

LAN_LED0

LAN_LED1
LAN_LED2

EESK

EEDI
EEDO

EECS_3

PCI_AD0
PCI_AD1
Close
1

49D9R2F R104 R105

to LAN R107 49D9R2F 49D9R2F
chip 49D9R2F
2

3D3V_LAN_S5
2

128
127

126

125

124

123

122

121

120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
1

U28
C140 C137 3D3V_LAN_S5

3
SCD1U16V SCD1U16V
VSS

VSS

VSS

EESK

EEDI

EECS
LANWAKE
RSET

VSSPST
AVDD18

CTRL18

XTAL2

XTAL1

LED0
VDD18
LED1
LED2
LED3

VDD18

EEDO
VDD33

PCIAD0
PCIAD1
AVDDH

GND

GND
2

CTRL25 1 2LAN_PWR_CTRL
1 CHP69
3 R103 0R2-0 Q8 3
G30 VDD25

2
1 2
GND

NC

NC

GND

GND

NC
GND
NC
NC

NC
NC
NC
1 TX+ 102 PCI_AD2 GAP-CLOSE-PWR
26 TX+ MDI0+ PCIAD2

1
26 TX- 2 MDI0- TX- GND
VSSPST 101

1
AVDD33 3 AVDD33 100 C132 C142 C149 C152
AVDDL GND VDD25 C130 SCD1U16V SCD1U16V SCD1U16V
4 GND VDD25 VDD18 99

2
VSS PCI_AD3 SC22U10V6ZY-U SCD1U16V
26 RX+ 5 RX+ 98

2
MDI1+ PCIAD3 PCI_AD4
26 RX- 6 MDI1- RX- PCIAD4 97
AVDD33 7 AVDD33 96 PCI_AD5
CTRL25 AVDDL PCIAD5 PCI_AD6
8 CTRL25 PCIAD6 95
9 VSS NC VDD33 94
PCI_AD7
10 AVDDH NC PCIAD7 93
PCI_C/BE#0
AVDD25
11 HSDAC+ NC CBEB0 92
3D3V_LAN_S5
12 HSDAC- AVDD25 GND VSSPST 91
PCI_AD8
13 VSS NC PCIAD8 90
14 NC 89 PCI_AD9
MDI2+ PCIAD9

1
15 MDI2- NC NC M66EN 88
16 NC 87 PCI_AD10 L16
AVDDL PCIAD10 PCI_AD11 BLM11A601S
17 VSS GND PCIAD11 86
18 NC 85 PCI_AD12
MDI3+ PCIAD12 AVDD33
19 MDI3- NC VDD33 84
AVDD33 20 AVDD33 83 PCI_AD13

2
AVDDL PCIAD13 PCI_AD14
21 VSSPST GND PCIAD14 82
22 GND NC GND VSSPST 81
ISOLATE 23 ISOLATE# ISOLATEB GND 80

1
24 NC 79 PCI_AD15
VDD18 PCIAD15 VDD25 C139 C138 C136 C134
2 17,29 INT_PIRQE# 25 INTA# INTAB VDD25 VDD18 78
2
26 77 PCI_C/BE#1 SCD1U16V SCD1U16V SCD1U16V SCD1U16V
3D3V_LAN_S5

2
VDD33 CBEB1 PCI_PAR
19,22,23,29,31 PCIRST1# 27 PCIRST# PCIRSTB PAR 76
PCI_SERR#
PCI_PAR 17,22,29
3 PCLK_LAN 28 PCICLK SERRB SERR# 75 PCI_SERR# 17,22,29
17 PCI_GNT#2 29 GNT# GNTB NC 74 DY
17 PCI_REQ#2 30 REQ# REQB NC GND 73
13,17,29 ICH_PME# 31 PME# PMEB NC 72
VDD25 32 VDD25 71
PCI_AD31 VDD18 VDD33 PCI_PERR#
33 PCIAD31 PERRB PERR# 70 PCI_PERR# 17,22,29
PCI_AD30 34 STOPB STOP# 69 PCI_STOP#
PCIAD30 PCI_STOP# 17,22,29
35 DEVSELBDEVSEL# 68 PCI_DEVSEL#
FRAME#FRAMEB

GND PCI_DEVSEL# 17,22,29

PCI_AD29 36 TRDYB TRDY# 67 PCI_TRDY#
VDD18 VDD25

IRDY# IRDYB

PCIAD29 PCI_TRDY# 17,22,29 3D3V_S5 3D3V_LAN_S5

PCI_AD28 37 GND VSSPST 66
PCIAD28
38 VSSPST GND CLKRUNBCLKRUN# 65
VDD18 NC

NC

GND

NC
VDD18 NC

PM_CLKRUN# 17,22,29,31
G31
PCIAD27
PCIAD26

PCIAD25
PCIAD24

PCIAD23

PCIAD22
PCIAD21

PCIAD20

PCIAD19

PCIAD18
PCIAD17
PCIAD16
VSSPST

1 2
CBEB3

CBEB2
VDD33

VDD33
IDSEL

GND

GND

GND

GAP-CLOSE-PWR
3D3V_S0
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

3D3V_S0 RTL8100CL-U
3,5,7,9,11,13,14,16,17,18,19,20,21,22,23,24,27,29,30,31,32,36,38,40,41 3D3V_S0
3D3V_S5
1

17,18,19,21,29,31,35,37,39,40 3D3V_S5
R102
PCI_AD27
PCI_AD26

PCI_AD25
PCI_AD24
PCI_C/BE#3

LAN_IDSEL
PCI_AD23

PCI_AD22
PCI_AD21

PCI_AD20
VDD25
PCI_AD19

PCI_AD18
PCI_AD17
PCI_AD16
PCI_C/BE#2

1KR2 3D3V_LAN_S5

41 3D3V_LAN_S5
2

1 1
ISOLATE

3D3V_LAN_S5
Wistron Corporation
1

om
2

R101 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

l.c
15KR2 R109 Taipei Hsien 221, Taiwan, R.O.C.

ai
DY 100R2

tm
Title
2

PCI_IRDY# 17,22,29

ho
LAN RTL8100C
1

f@
PCI_FRAME# 17,22,29
PCI_AD23 Size Document Number Rev

in
A3
Leopard 3 -1

xa
he
Date: Wednesday, July 13, 2005 Sheet 25 of 41
A B C D E
 A B C D E

3D3V_LAN_S5
Place on bottom side
Blue thumb 1394 Connector 25,41 3D3V_LAN_S5

R556 100R2 CN4

29 BT_PRIOR 1 2 10
29 WLAN_ACT 1 2 8
13 BC0EX2 7
R557 6 0R0402-PAD
13 BC0EX1
100R2 5 1 R98 2 TPA0+
13,14 BT_LED 22 1394_TPA0P
17 USB_PN2 4 1394_1
3 0R0402-PAD 6
17 USB_PP2
4 2 22 1394_TPA0N 1 R96 2 TPA0- 3 4 4

1 0R0402-PAD TPB0- 1 2
3D3V_BT_S0
9 22 1394_TPB0P 1 R97 2 TPB0+ 5

JST-CON8-7 0R0402-PAD SKT-1394-4P-6-U1

22 1394_TPB0N 1 R99 2

1
BC0EX2 connect to PCI_AD22 on main board.
BC0EX1 connect to ICH_PME# on main board. R205 R206 R207 R208
56R2F 56R2F 56R2F 56R2F

2
1394_TPB0_T
22 1394_TPBIAS0

1
1

1
R209
C245 C246 5K1R2
BC0EX2 SC1U10V3KX SC220P

2
MAX 150mA BC0EX1 3D3V_BT_S0

2
BT_LED
POWER SWITCH 5V_S3 3D3V_BT_S0

1
EC18 EC17 EC16 EC110
SCD1U SCD1U SCD1U SCD1U 0R0402-PAD

2
1

1
C322 C304 DY DY DY DY 1 R66 2
22 1394_TPA1P
SC1U10V3ZY I max = 150 mA SC20P R370
78.10593.4B1 18KR3F 0R0402-PAD
1394_TPA1P_PR 13
2

2
U55 78.20034.1B1 1 R45 2
3 Close to CN20 22 1394_TPA1N 1394_TPA1N_PR 13
1394_TPB1P_PR 13
3

2
BT_EN# 1 5 3D3V_BT_SET 0R0402-PAD
SHDN# SET
2 GND 22 1394_TPB1P 1 R62 2 1394_TPB1N_PR 13

1
3 IN OUT 4 3D3V_BT_S0
R369 0R0402-PAD
1

11KR3F 1 R42 2
22 1394_TPB1N
G913C-U C321 C85

1
SC4D7U10V5ZY SCD1U16V
2

5V_S3 78.47593.411 2 R200 R203 R202

R201 56R2F 56R2F 56R2F
1

56R2F
R390

2
10KR2 1394_TPB1_T
22 1394_TPBIAS1

1
2

1
BT_EN#
C241 C244 R204
D

10/100 LAN Transformer RJ45 PIN SC1U10V3KX SC220P 5K1R2

2
QB4

2
2N7002-F-GP
17 BT_EN G TD+ --> TX+ RJ45-1
TD- --> TX- RJ45-2
These components near to chip side.
S

RD+ --> RX+ RJ45-3

RD- --> RX- RJ45-6
2 2
10/100M Lan Transformer
U3

XFR_RDC 3 15 RX- RJ45-8

CT RX- RJ45-8 13
XFR_CMT 11 16 RX+ RJ45-7
CT RX+ RJ45-7 13
XFR_RXC 14 RJ45-6
CT RJ45-6 13
XFR_TDC 6 2 RJ45-5
CT RD- RX- 25 RJ45-5 13
1 RJ45-4
RD+ RX+ 25 RJ45-4 13
RJ45-3
RJ45-3 13
8 9 TX- RJ45-2
TX- TD- TX- RJ45-2 13
7 10 TX+ RJ45-1
TX+ TD+ TX+ RJ45-1 13
JK1
9
1

XFORM-187-U RJ45_END1
C24 C25 RJ45_END2
SCD1U16V SCD1U16V
2

DY RJ45-1 RJ45_1
R300 R299
75R2F 75R2F RJ45-2 RJ45_2
XFR_RXC 1 2 RJ45-3 RJ45_3
R298 75R2F RJ45-4 RJ45_4
2

XFR_CMT 1 2 RJ45_END RJ45-5 RJ45_5

R297 75R2F RJ45-6 RJ45_6
LAN_TERMINAL 1 2 C278 RJ45-7 RJ45_7
SC1500P2KV8KX RJ45-8 RJ45_8
1.route on bottom as differential pairs.
1 1
2.Tx+/Tx- are pairs. Rx+/Rx- are pairs.
4

3.No vias, No 90 degree bends. CN1 TIP RJ11_1

L20 MLB160808 RING RJ11_2
4.pairs must be equal lengths. 1 TIP_MDC 1 2 TIP 10 Wistron Corporation
5.6mil trace width,12mil separation. 2 RING_MDC 1 2 RING 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
L21 MLB160808 RJ45-74-U1 Taipei Hsien 221, Taiwan, R.O.C.
6.36mil between pairs and any other trace.
7.Must not cross ground moat,except ETY-CON2-R1 Title
3

RJ-45 moat. 20.D0151.102 LAN / 1394 Connector

Size Document Number Rev
A3
Leopard 3 -1
Date: Monday, August 15, 2005 Sheet 26 of 41
A B C D E
 A B C D E

3D3V_S0

3,5,7,9,11,13,14,16,17,18,19,20,21,22,23,24,25,29,30,31,32,36,38,40,41 3D3V_S0
5V_S0
3D3V_S0
13,14,18,19,20,21,23,24,28,29,32,36,39,40,41 5V_S0

1
BC82 BC81 BC80 BC79
SCD1U16V SCD1U16V SC1U10V3ZY SCD1U16V

2
4 4

AUD_AGND
5V_AUDIO_S0

1 2 C267 3D3V_S0
SC270P50V3JN
1 2 C265

1
SC270P50V3JN

CODECVREF

2
BC73 BC41 BC44 BC43 1 2 C266

VREFOUT
SCD1U16V SCD1U16V SCD1U16V SCD1U16V SC270P50V3JN R213

ADAF1
ADAF2
ADAF3
ADAF4
1 2 C268 10KR2
SC270P50V3JN
D10

1
AUD_AGND AUD_AGND
U41

25
38
43
34

27
28

29
30
31
32
1 3 HPSENSE_1 28

1
9

VREF
VREFOUT
AVDD1
AVDD2
AVDD3
AVDD4

DVDD1
DVDD2

AFILT1
AFILT2
AFILT3
AFILT4
AD1981_JS0 S1N4148-U2
1 2
BC31 SC1U10V3ZY R499 2K2R2
EXT_MIC_1 AUD_MICIN1
DY
2 1 21 MIC1 JS0 17
EXT_MIC_2 2 1 AUD_MICIN2 22 16
MIC2 JS1 HPSENSE 28
EAPD 47 EAPD 28,31
BC32 SC1U10V3ZY 23 1 2 BC46
LINE_IN_L R243 0R2-0 SC22P
28 AUD_LOL 35 LINE_OUT_L DY

1
24 LINE_IN_R 1 2 CLK_CODEC 3
36 2 X3
28 AUD_LOR LINE_OUT_R XTL_IN
BC42 3 XTALOUT_CODEC X-24D576MHZ-3-U1
XTL_OUT
30 AUD_MDC_OUT 1 2 SCD1U16V AUD_MDC_CODEC 37 2 DY 1 BC37 DY

2
MONO_OUT DUMMY-C2
3
30 AUD_PHONE 1 2 BC36 AUD_PHONE_CODEC13
PHONE_IN SDATA_IN 8 AC97_DIN0_CODEC
1 2 AC97_DIN0 16 1 2 BC45 3
SCD1U16V R223 22R2 SC22P
CDAUDL CDAUD_L 18 SDATA_OUT 5 AC97_DOUT 16,30
R242
DY BC47
21 CD_AUDL 1 2 1 2 CD_L
R221 22R2 BC35 CDAUD_R 20 6 AC97_CBITCLK 1 2 1 2XTALOUT_CODEC_R1 2 5V_AUDIO_S0
CD_R BIT_CLK 33R2 AC97_BITCLK 16,30
SC1U25V5ZY CDAUD_GND
19 10 R224
CD_GND_REF SYNC AC97_SYNC 16,30
1 2 CDAUDR 1 2 11 DUMMY-R2 DUMMY-C2
21 CD_AUDR RESET# AC97_RST# 16,30

1
R218 22R2 BC33 SPDIF_OUT
39 HP_OUT_L SPDIF 48 SPDIF_OUT 13 DY DY

1
SC1U25V5ZY 41 R515
HP_OUT_R

1
1 2 CDAGND 1 2 5V_S0 BC84 28K7R3F EC156
21 CD_AGND 22R2
R219 BC34 AUD_PC_BEEP 14 R241 SC22P SCD1U16V

2
AUX_L
1

SC1U25V5ZY 15 4K7R2 U63

2
R220 R217 R222 AUX_R 5VA_SET
1 5

DVSS1
DVSS2
AVSS1
AVSS2
AVSS3
AVSS4
150KR2J 150KR2J 150KR2J SHDN# SET

ID1#
ID0#

1
5V_AUDIO_S0

NC
NC
DY DY DY BC85
2 GND R516
2

AD1981B-AS SC1U10V3ZY 3 4 10KR3F

26
40
44
33

4
7

46
45

12
42

2
IN OUT

1
MAX8863-S

2
AUD_AGND BC83
SC10U10V6ZY-U

2
For High limit --> H45
AUD_AGND AUD_AGND
13 HP_OUT_L
AUD_AGND
13 HP_OUT_R

G38
1 2
VREFOUT
GAP-CLOSE
2 2

1
BC29 G36 AUD_AGND
SC1U10V3ZY R215 1 2

2
3KR2F
DY
GAP-CLOSE
AUD_AGND
MIC2 PREAMP

2
AUD_AGND
13 EXT_MIC_2
CLOSE TO CODEC
5V_AUDIO_S0 UNDER CODEC
CUT MOAT

1
U40A BC27 G68 G35
14

SC1000P50V3KX 1 2 1 2

2
22 PCI_SPKR 1
3 AUD_BEEP1 GAP-CLOSE GAP-CLOSE
17 ICH_SPKR 2 AUD_AGND

TSAHCT86 AUD_AGND AUD_AGND

7

5V_AUDIO_S0 G40 G39

1 2 1 2
AUD_AGND U40B VREFOUT
14

GAP-CLOSE GAP-CLOSE
5V_AUDIO_S0 4 C264 SCD1U16V

1
6 AUD_SYS_BEEP 1 2 AUD_BEEP 1 2 AUD_PC_BEEP
1

U40C R238 10KR2 R216 AUD_AGND AUD_AGND

14

5
BC30 3KR2F SB-27-02
9 TSAHCT86 SC1U10V3ZY
31 KBC_BEEP
7

2
1

1 8 AUD_BEEP2 DY 2 1
U39_PL 10 C272 R251
AUD_AGND SCD1U16V 1KR2 AUD_AGND
MIC1 PREAMP
2
2

TSAHCT86
13 EXT_MIC_1
Wistron Corporation
7

R252

om
2

10KR2 CLOSE TO CODEC 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1

l.c
Taipei Hsien 221, Taiwan, R.O.C.

ai
AUD_AGND BC28
1

tm
AUD_AGND SC1000P50V3KX Title
2

ho
AUD_AGND AUDIO CODEC AD1981B

f@
AUD_AGND Size Document Number Rev

in
A3
Leopard 3 -1

xa
he
Date: Tuesday, July 12, 2005 Sheet 27 of 41
A B C D E
 A B C D E

5V_S0

13,14,18,19,20,21,23,24,27,29,32,36,39,40,41 5V_S0

1 2 BC88
SC10P50V2JN-1
4 BC78 R519 4
AUD_LOL 1 2 CSOUTL2 1 2 1 2 SPKR_L+
R518 20KR2
SC4D7U10V5ZY 15KR2 5V_S0

SB 1 2 BC49
SC220P
BC50 R254

1
1 2 CSOUTL1 1 2 L_LINE_IN 1 2 SPKR_L+ 1 2
27 AUD_LOL DK_SPKR_L+ 13
R253 18KR2J R561
SCD1U16V3KX 15KR2 TC21 SE100U16VGM-2 100KR2

U62

2
G1420_SHUTDOWN#
4 3 SPKR_L+

D
5VA_OP_S0 HP_L LLINEIN LOUT+ SPKR_L-
5 LHPIN LOUT- 10
L_BYPASS 6 Q40
LBYPASS HPSENSE_1 2N7002-F-GP
7 LVDD SE/BTL# 14
HP/LINE# 16 PM_SLP_S3# G
G1420_SHUTDOWN# 8 11 AUD_MUTE
SHUTDOWN MUTEIN 17,21,31,37,38,40

1
2 9

S
BC87 BC74 BC86 TJ MUTEOUT
17 HP-IN GND/HS 1
SC10U10V6ZY-U SCD1U16V3KX SCD1U16V3KX 23 12

2
AUD_AGND VOL GND/HS R517 10KR2 AUD_AGND
GND/HS 13
18 24 AUD_AGND G1420_SHUTDOWN# 1 DY 2
R_BYPASS RVDD GND/HS
19 RBYPASS
AUD_AGND HP_R 20 15 SPKR_R-
RHPIN ROUT- SPKR_R+
21 22

GND
RLINEIN ROUT+
3 AUD_AGND G1421BF3U AUD_AGND 3
SB

25
AUD_AGND
BC40 SCD1U16V3KX
1 2 CSOUTR1 1 2 R_LINE_IN 1 2 SPKR_R+ 1 2 DK_SPKR_R+ 13
27 AUD_LOR 15KR2
R240 R239 18KR2J
TC22 SE100U16VGM-2
1 2 BC39
SC220P

5VA_OP_S0
5V_S0
BC77 SC4D7U10V5ZY G67
AUD_LOR 1 2 CSOUTR2 1 2 1 2 SPKR_R+ 1 2
R513 15KR2 R514 20KR2
GAP-CLOSE-PWR
1 2 BC76
SC10P50V2JN-1

5V_S0 R_BYPASS

L_BYPASS
1

R510

1
100KR2

1
2 5V_S0 BC75 2
BC48 SC4D7U10V5ZY
2

2
HPSENSE_1 SC4D7U10V5ZY
HPSENSE_1 27

2
1

R509
100KR2
D

AUD_AGND AUD_AGND
Q29
2

2N7002-F-GP 1 2 EARPHONE_R
13 EARPHONE 22KR2J HPSENSE 27
G R214
13 JACK_DETECT#
1

1
S

C457 C251
SC1U10V3ZY SC1U10V3ZY
2

5V_S0

5V_S0 SPK1

U61B SPKR_R+
Speaker 6
14

4
U61C
14

3
4 SPKR_R- 2
31 KBC_MUTE
1 6 AUD_MUTE_1 9 SPKR_L+ 1
5 8 AUD_MUTE SPKR_L- 1
27,31 EAPD
HPSENSE 10
1

TSAHCT32 5
Wistron Corporation
7

TSAHCT32
7

R512 ETY-CON4-11-U 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

10KR2 EC152 EC154 EC159 EC153 Taipei Hsien 221, Taiwan, R.O.C.
SC220P SC220P SC220P SC220P 20.D0151.104
2

Title
AUDIO
Size Document Number Rev
A3
Leopard 3 -1
Date: Monday, August 15, 2005 Sheet 28 of 41
A B C D E
 A B C D E

3D3V_S0

3,5,7,9,11,13,14,16,17,18,19,20,21,22,23,24,25,27,30,31,32,36,38,40,41 3D3V_S0
5V_S0

MINI-PCI 13,14,18,19,20,21,23,24,27,28,32,36,39,40,41 5V_S0

4 4

3D3V_S0

1
BC71 BC69 BC72 BC70
PCI_AD[31..0] 13,17,22,25 SC4D7U10V5ZY SCD1U16V SCD1U16V SCD1U16V

2
PCI_C/BE#[3..0] 17,22,25

3D3V_S0 3D3V_S5

CN13
TIP 125 RING
1

1 2
R244 R476
10KR2 DUMMY-R2 3 4
DY 5 6
7 8
2

9 10
1

14 802_ACT_LED 11 12
WIRELESS_EN 13 14
WIRELESS_EN 15 16
INT_PIRQE# 17 18 5V_S0
19 20
D

3D3V_S0 INT_PIRQE# 17,25

MINI_PIN21 21 22
3 Q12 TPAD30 TP25 23 24 3
2N7002-F-GP 3D3V_S5
3 PCLK_MINI 25 26 PCIRST1# 19,22,23,25,31
17 WIRELESS_EN# G 27 28 3D3V_S0
17 PCI_REQ#0 29 30 PCI_GNT#0 17
31 32
S

PCI_AD31 33 34 MINI_PME# 1 DY 0R2-0

2 ICH_PME# 13,17,25
PCI_AD29 35 36 R484
BT_PRIOR 26
37 38 PCI_AD30
PCI_AD27 39 40
PCI_AD25 41 42 PCI_AD28 1201 -2
43 44 PCI_AD26
26 WLAN_ACT
PCI_C/BE#3 45 46 PCI_AD24
PCI_AD23 47 48 MOD_IDSEL 1 R485
2 PCI_AD21
49 50 10R2
3D3V_S0 PCI_AD21 51 52 PCI_AD22
PCI_AD19 53 54 PCI_AD20
55 56 PCI_PAR 17,22,25
PCI_AD17 57 58 PCI_AD18
1

PCI_C/BE#2 59 60 PCI_AD16
R477 61 62
17,22,25 PCI_IRDY#
10KR2 63 64 PCI_FRAME# 17,22,25
17,22,25,31 PM_CLKRUN# 65 66 PCI_TRDY# 17,22,25
17,22,25 PCI_SERR# 67 68 PCI_STOP# 17,22,25
2

69 70
17,22,25 PCI_PERR# 71 72 PCI_DEVSEL# 17,22,25
PCI_C/BE#1 73 74
PCI_AD14 75 76 PCI_AD15
77 78 PCI_AD13
PCI_AD12 79 80 PCI_AD11
2 PCI_AD10 2
81 82
83 84 PCI_AD9
PCI_AD8 85 86 PCI_C/BE#0
PCI_AD7 87 88
89 90 PCI_AD6
PCI_AD5 91 92 PCI_AD4
93 94 PCI_AD2
PCI_AD3 95 96 PCI_AD0
5V_S0 97 98
PCI_AD1 99 100 PCI_SERIRQ 17,22,31
101 102
103 104
105 106
107 108
109 110
111 112
113 114
115 116
117 118
119 120
121 122

123 124 3D3V_S5

126

PCIMODEM124A1U1
62.10032.001

1 1

The symbol use 2nd source

The P/N is the main source Wistron Corporation

om
Main source:62.10032.001 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

l.c
Taipei Hsien 221, Taiwan, R.O.C.
2nd source:62.10032.031

ai
tm
Title

ho
MINI-PCI

f@
Size Document Number Rev

in
A3
Leopard 3 -1

xa
he
Date: Tuesday, July 12, 2005 Sheet 29 of 41
A B C D E
 A B C D E

5V_AUX

USB POWER 14,15,35,37,38,39 5V_AUX

5V_S3

13,14,26,28,32,37,38,40,41 5V_S3
5V_S3 5V_USB1_S3
F1 100 mil
1 2 3D3V_S3

1
MINISMDC110-U
13,14,40 3D3V_S3
4 C106 C105 C104 TC6 4
SC4D7U10V5ZY SCD1U16V SC1000P50V ST100U6D3VBM-6GP

2
5V_USB1_S3

USB1
11
9
0329 SB 1 5

17 USB_PN4 2 6
3 3 7 USB_PN5 17 3
17 USB_PP4 USB_PP5 17
4 8
10
12

SKT-USB-76-U

2 2

MDC Connector
R155
1 2 AUD_MDCIN
27 AUD_MDC_OUT

DY DUMMY-R2
CN9
35

3D3V_S3
3D3V_S0 31 32

1 2
3 4 AUD_PHONE 27
1

5 6
1

R486 G64 7 8
DUMMY-R2 9 10
DY GAP-CLOSE-PWR
11 12
13 14
2

15 16
2

MDC_S3_1 17 18 Check with Ambit

19 20
21 22 AC97_SYNC 16,27
23 24 ACSDATAIN1_A 1 DY 22R2
2
16,27 AC97_DOUT AC97_DIN1 16
25 26 ACSDATAIN1_B 1 2 R169
1 16,27 AC97_RST# 22R2
1
27 28 R168
29 30 AC97_BITCLK 16,27
33 34 Wistron Corporation
1

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

1

C413 AMP-CONN30A-1 C222 Taipei Hsien 221, Taiwan, R.O.C.

36

SCD1U16V C412 C411 20.F0099.030 SC22P

2

DY SC4D7U10V5ZY SCD1U16V DY Title

2

USB / MDC CONN.

Size Document Number Rev
A3
Leopard 3 -1
Date: Tuesday, July 12, 2005 Sheet 30 of 41
A B C D E
 A B C D E

3D3V_S0
KBC_3D3V_AUX RTC_AUX_S5
KBC_3D3V_AUX
3,5,7,9,11,13,14,16,17,18,19,20,21,22,23,24,25,27,29,30,32,36,38,40,41 3D3V_S0
3D3V_AUX KBC_3D3V_AUX 1 2 KBC_RTC_VCC1 2

1
L18 BLM11P600S R139 1KR2 3D3V_AUX

1
D7 BC15

KBC_AVCC
G33 3D3V_S0 SCD1U16V BC25 BC17
16,20,32,34,35,36,37 3D3V_AUX

1
SSM5818SL SCD1U16V SCD1U16V
1 2 DY

2
BC21 BC16 BC20 BC23 BC24 BC26 5V_AUX

2
GAP-CLOSE-PWR SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V

2
14,15,35,37,38,39 5V_AUX

123
136
157
166

161
U33 3D3V_S5

16

34
45

95
16 LPC_LAD[0..3]
BC22
4 SCD1U16V 4

VDD

VCC
VCC
VCC
VCC
VCC
VCC

AVCC

VBAT
17,18,19,21,25,29,35,37,39,40 3D3V_S5

2
BT+

7 81 BT_SENSE 3D3V_S0
17,22,29 PCI_SERIRQ SERIRQ AD0

1
16 LPC_LDRQ0# 8 IOPQ0/LDRQ# AD1 82 BT_TH 34,35
9 83 R174 RN34
16 LPC_LFRAME# LFRAME# AD2 AIRLINE_VOLT 35 560KR3F
LPC_LAD0 15 84 VOL_UP_BTN# 1 8
LAD0 AD3 AD_IA 35
LPC_LAD1 14 87 VOL_DWN_BTN# 2 7
LAD1 AD input IOPE0 PM_SUS_STAT# 17
LPC_LAD2 13 88 VOL_UP_DK# 3 6
KBC_MATRIX1 32

2
LPC_LAD3 LAD2 IOPE1 VOL_DWN_DK#
10 LAD3 IOPE2 89 KBC_MATRIX2 32 4 5
3 PCLK_KBC 18 LCLK IOPE3 90 EAPD 27,28
19 Host Interface 93 THERMAL_DP BT_SENSE 1 2 SRN10K
16,20,39 RSMRST# RESET1# NC#93 100KR3F
R173 22 94 THERMAL_DN TP30 TPAD30 R175
17 ECSMI#_KBC IOPQ1/SMI# NC#94
ECSWI#_KBC 1 2 KBC_PWUREQ# 23 R558 0R2-0 TP29 TPAD30
IOPQ2/PWUREQ# DA_BRI
KBC_3D3V_AUX DUMMY-R2 DA0 99 1
CHG_ICTL
DY 2 BRIGHTNESS 14 AD_IA
100 1 2 C230
CN15 DY 31 DA Output DA1
101 CHG_VCTL SCD1U16V3KX
17 ECSCI#_KBC IOPD3/ECSCI DA2
9 DA3 102
TP63
1 5 32 TPAD30
TP62
16 ICH_A20GATE IOPB5/(GA20) IOPA0/PWM0 KBC_BEEP 27
TPAD30
2 KBC_D0 6 33
16 RCIN# IOPB6/KBRST# IOPA1/PWM1 PWR_LED 14
3 TINT# 36 KBC_3D3V_AUX
IOPA2/PWM2 CHG_LED 14
4 TCK 37 RN15 SRN10KJ
32 KROW[1..8] PWM or PortA IOPA3/PWM3 VOL_UP_BTN# 32
5 TDO KROW1 71 38 SMBC_KBC 2 DY 3
KBSIN0 IOPA4/PWM4 VOL_DWN_BTN# 32
6 TDI KROW2 72 39 SMBD_KBC 1 4
TMS KROW3 KBSIN1 IOPA5/PWM5 MUTE_BTN# 32
7 73 KBSIN2 IOPA6/PWM6 40
8 KROW4 74 Key Matrix Scan 43 PWM_BRI
1 2 802_BT_BTN# 32 BT_SCL 1 2
KROW5 KBSIN3 IOPA7/PWM7 R559 0R2-0 BRIGHTNESS R136 6K8R2F
77 KBSIN4
10 KROW6 78 153 BT_SDA 1 2
KBSIN5 IOPB0/URXD1 CAPS_LED 14 6K8R2F
KROW7 79 154 R135
3 KBSIN6 IOPB1/UTXD1 NUM_LED 14 3
MOLEX-CON8-2 KROW8 80 162 KBC_PME# 1 2
KBSIN7 PortB IOPB2/USCLK1 MUTE_LED 13,14 10KR2
163 BT_SCL R165
32 KCOL[1..16] IOPB3/SCL1 BT_SCL 34
DY KCOL1 49 164 BT_SDA
KBSOUT0 IOPB4/SDA1 BT_SDA 34
KCOL2 50 165 PM_PWRBTN# 2 1
KBSOUT1 IOPB7/RING#/PFAIL#/RESET2# PCIRST1# 19,22,23,25,29
KCOL3 51 R138 DUMMY-R2
3D3V_S0 KCOL4 KBSOUT2
52 168
KCOL5 53
KBSOUT3 IOPC0
169
PM_PWRBTN# 17 DY
KBSOUT4 IOPC1/SCL2 SMBC_KBC 20
KCOL6 56 170 RSMRST#_KBC 1 2
KBSOUT5 IOPC2/SDA2 SMBD_KBC 20 KBC_3D3V_AUX 100KR2
KCOL7 57 171 R150
KBSOUT6 PortC IOPC3/TA1 MAINTAIN_CHG 35
KCOL8 58 172
KBSOUT7 IOPC4/TB1/EXWINT22 DVD_BT# 32
KCOL9 59 175 S5_ENABLE 1 2
KBSOUT8 IOPC5/TA2 PM_SLP_S4# 17,21,37,38
4
3
2
1

KCOL10 60 176 R142 10KR2

KBSOUT9 IOPC6/TB2/EXWINT23 PM_SLP_S3# 17,21,28,37,38,40
RN28 KCOL11 61 1
KBSOUT10 IOPC7/CLKOUT CLK32_G768 20
SRN10K-2 KCOL12 64 DVD_BT# 1 2
KCOL13 KBSOUT11 R137 10KR2
65 KBSOUT12 IOPD0/RI1#/EXWINT20 26 CDROM_BT# 32
KCOL14 66 PortD-1 29 CDROM_BT# 1 2
KBSOUT13 IOPD1/RI2/EXWINT21 CIR_KBC 13 10KR2
KCOL15 67 30 R166
AC_IN# 35
5
6
7
8

KCOL16 KBSOUT14 IOPD2/EXWINT24/RESET2#

68 KBSOUT15/XOR_OUT
IOPE4/SWIN 2 KBC_PWRBTN# 32
TINT# 105 PortE 44
TINT# IOPE5/A20//EXWINT40 KBC_LID# 14
TCK 106 24 KBC_PME#
TDO TCK JTAG Debug Port IOPE6/LPCPD#/EXWINT45
107 TDO IOPE7/CLKRUN#/EXWINT46 25 1 2 PM_CLKRUN# 17,22,25,29
TDI 108 R164 0R2-0
TMS 109
TDI
TMS A0/ENV0 124 A0/ENV0 33
KBC HARDWARE SETTING
A1/ENV1 125 A1/ENV1 33
PSCLK1 110 126 KBC_3D3V_AUX
X1 IOPF0/PSCLK1 A2/BADDR0 A2/BADDR0 33
PSDAT1 111 127
IOPF1/PSDAT1 PortH A3/BADDR1 A3/BADDR1 33
SC3P50V2CN 2 1 PSCLK2 114 128 DY R152
IOPF2/PSCLK2 A4/TRIS A4/TRIS 33
1

PSDAT2 115 131

IOPF3/PSDAT2 PS2 Interface A5/SHBM A5/SHBM 33
BC19
3 4 R141 3D3V_S0 116 132 A0/ENV0 1 2
2 32 TCLK_5 IOPF4/PSCLK3 A6 A6 33 2
20MR3 117 133
32 TDATA_5 A7 33
2

IOPF5/PSDAT3 A7 DUMMY-R2
118 KBC_D[0..7] 33 RN29
X4P-32D768KHZ-3 PSDAT4 IOPF6/PSCLK4 KBC_D0 A1/ENV1
1 2 119 138 2 3
2

R151 10KR2 IOPF7/PSDAT4 D0 KBC_D1 A2/BADDR0

D1 139 1 4
140 KBC_D2
KBC_32KX1 D2 KBC_D3
158 141 SRN10KJ
KBC_32KX2_1 KBC_32KX2 32KX1/32KCLKIN PortP D3 KBC_D4
1 2 160 32KX2 D4 144
R140 0R2-0 145 KBC_D5 R153
D5
1

146 KBC_D6 A3/BADDR1 1 DY 2

BC18 D6 KBC_D7 DUMMY-R2
13 VOL_UP_DK# 62 IOPJ2/BST0 D7 147
SC3P50V2CN 63 PortJ-2 R144
13 VOL_DWN_DK#
2

CHG_I_SEL IOPJ3/BST1 A4/TRIS

35 CHG_I_SEL
CHG_I_PRE_SEL
69 IOPJ4/BST2 PortJ-1 RD# 150 KBCBIOS_RD# 33 1 DY 2
DUMMY-R2
35 CHG_I_PRE_SEL 70 IOPJ5/PFS WR0# 151 KBCBIOS_WE# 33
35 LI/NI# 75 IOPJ6/PLI
CHG_ON# 76 152 KBC_SEIO# TP60 TPAD30 ENV0 ENV1 TRIS
35 CHG_ON# IOPJ7/BRKL_RSTO# SELIO# IRE 0 0 0
41 OBD 0 1 0
IOPD4 PR_INSERT# 13 DEV 1 0 0
7 BL_ON 148 IOPM0/D8 IOPD5 42 KBC_MUTE 28
149 PortD-2 54 PROG 1 1 0
14,32 ID_DET IOPM1/D9 PortM IOPD6 ECSWI#_KBC 17
3D3V_S5 155 55
14 FPBACK IOPM2/D10 IOPD7
20 S5_ENABLE 156 IOPM3/D11
1 2 VCC_+3VSB 3 143 SHBM=1: Enable shared memory with host BIOS
100KR2 IOPM4/D12 A8 A8 33 TRIS=1: While in IRE and OBD, float all the
R134 4 142
17 RSMRST#_KBC IOPM5/D13 A9 A9 33 signals for clip-on ISE use
35 NI_BAT 27 IOPM6/D14 A10 135 A10 33
1

34 AD_OFF 28 IOPM7/D15 A11 134 A11 33

BC14 PortK 130 I/O Address
A12 A12 33 BADDR1-0 Index Data
SC1U10V3ZY 129 A13 33
2

A13_BE0 0 0 2E 2F
33 KBCBIOS_CS# 173 SEL0# A14_BE1 121 A14 33
KBC_SEL1 174 120 0 1 4E 4F
SEL12_SEL2# A15_CBRD A15 33 1 0 (HCFGBAH, HCFGBAL) (HCFGBAH, HCFGBAL)+1
TPAD30 TP59 KBC_CLK 47
1 TPAD30 TP70 IOPQ3/CLK 1 1 Reserved 1
A16 113 A16 33
A17 112 A17 33
A18 104 A18 33
PortL 103
IOPL3/A19 WR1# Wistron Corporation

om
KBC_3D3V_AUX 48 TP64 TPAD30
IOPL4/WR1# TP71 TPAD30 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

l.c
Taipei Hsien 221, Taiwan, R.O.C.
VCORF
NC#11
NC#12
NC#20

NC#85
NC#86
NC#91
NC#92
NC#97
NC#98
AGND

ai
1 2
GND
GND
GND
GND
GND
GND
GND

tm
R143 10KR2 Title
1

ho
C214 KBC NS97551

f@
17
35
46
122
137
159
167

96

11
12
20
21
85
86
91
92
97
98

PC97551-VPC-U SCD1U16V Size Document Number Rev

2

in
For NS97551 use only Custom
Leopard 3 -1

xa
A5/SHBM KBC_PIN21

he
Date: Wednesday, July 13, 2005 Sheet 31 of 41
A B C D E
 A B C D E

3D3V_S0

3,5,7,9,11,13,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,36,38,40,41 3D3V_S0
3D3V_S0 3D3V_AUX

3D3V_S0
INTERNAL KEYBOARD CONNECTOR 16,20,31,34,35,36,37 3D3V_AUX
5V_S0

1
R319 R321
10KR2 10KR2 13,14,18,19,20,21,23,24,27,28,29,36,39,40,41 5V_S0

KROW[1..8] 31 KCOL[1..16] 31
4 5V_S3 CN2 4

LAUNCH Board

2
802_BT_BTN# MUTE_BTN# C289 21
CN7 1 2 1

25 SCD1U10V2MX-1 2
14 PWR_LED#
1 KROW2 3D3V_AUX 3
14 MUTE_LED#
14 802_BT_LED# 4
2 KROW8 5
31 VOL_UP_BTN#
3 KROW7 6
31 VOL_DWN_BTN#

1
4 KCOL10 7
31 802_BT_BTN#
5 KROW5 R303 8
6 KROW6 POWER 10KR2 5V_S0
14,31 ID_DET 9
7 KCOL1 C290 10
8 KROW3 BUTTON SCD1U10V2MX-1
14 NUM_LED#
31 MUTE_BTN# 11

2
9 KROW4 2 1 12
10 KCOL6 1 2 PWRBTN# 13
31 KBC_PWRBTN# 470R2
11 KCOL2 R322 14
12 KROW1 15

1
13 KCOL3 16
14 KCOL5 BC58 17
15 KCOL8 SCD1U16V DVD_BT# 18
31 DVD_BT#

2
16 KCOL9 CDROM_BT# 19
KBC_3D3V_AUX 31 CDROM_BT#
17 KCOL7 20
18 KCOL4 22

1
19 KCOL13
20 KCOL14 the matrix table for PCB EC89 EC88
21 KCOL15 SC1000P16V2KX SC1000P16V2KX JST-CON20

2
22 KCOL12 KBC_MATRIX2,KBC_MATRIX1

2
2
3 23 KCOL11 PA PR 3
24 KCOL16 R178 R177
26 10KR2 10KR2 3D3V_S0
DY DY FF 00 01
1
ETY-CON24-1 1 D32
20.K0170.001 DF 10 11 2
DY R179 10KR2
VOL_UP_BTN# 3
VOL_DWN_BTN#
VOL_UP_BTN#
2 1 KBC_MATRIX2 31
2 1 802_BT_LED#
KBC_MATRIX1 31
1 MUTE_LED#
DY R176 10KR2 PWR_LED# EC86

1
BAV99LT1 NUM_LED# EC85 SC1000P16V2KX

1
DY EC82 EC83 EC84

1
EC87 SC1000P16V2KX

2
SC1000P16V2KX SC1000P16V2KX

2
SC1000P16V2KX SC1000P16V2KX

2
3D3V_S0

D33
NONE Quick Play Quick Play 2

VOL_DWN_BTN#
3
MATRIXID1# 0 1
1

BAV99LT1
DY TouchPad Connector 5V_S3
2 2

1
R433 R434
KCOL9 KROW1 KCOL14 KCOL16 10KR2 10KR2 CN8
KCOL8 KCOL2 KCOL13 KCOL11 9
KCOL5 KCOL6 KCOL4 KCOL12 8

2
KCOL3 KROW4 KCOL7 KCOL15 7
31 TDATA_5 6
31 TCLK_5 5
4
8
7
6
5

8
7
6
5

8
7
6
5

8
7
6
5

3
RC4 RC3 RC2 RC1 2
SRC100P50V-U SRC100P50V-U SRC100P50V-U SRC100P50V-U

1
1
BC63 BC64 BC68 BC62 10
1
2
3
4

1
2
3
4

1
2
3
4

1
2
3
4

SC47P50V2JN SC47P50V2JN SC1U10V3ZY

2
SCD1U16V
DY DY DY DY ETY-CON8-5
20.K0121.008

for EMI for EMI

KROW3 KCOL10
KCOL1 KROW7
KROW6 KROW8
KROW5 KROW2
1 1
8
7
6
5

8
7
6
5

RC6 RC5 Wistron Corporation

SRC100P50V-U SRC100P50V-U 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
1
2
3
4

1
2
3
4

Title
KEYBOARD/TOUCH PAD/Launch key
Size Document Number Rev
A3
for EMI Leopard 3 -1
Date: Tuesday, July 12, 2005 Sheet 32 of 41
A B C D E
 A B C D E

3D3V_S0

3,5,7,9,11,13,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41 3D3V_S0
5V_S0

13,14,18,19,20,21,23,24,27,28,29,32,36,39,40,41 5V_S0

4 4

KBC_D[0..7] 31

3 3
512KB Flash
U38

A0/ENV0 20 21 KBC_D0
31 A0/ENV0 A0 DQ0
A1/ENV1 19 22 KBC_D1
31 A1/ENV1 A1 DQ1
A2/BADDR0 18 23 KBC_D2
31 A2/BADDR0 A2 DQ2
A3/BADDR1 17 25 KBC_D3
31 A3/BADDR1 A3 DQ3
A4/TRIS 16 26 KBC_D4
31 A4/TRIS A4 DQ4
A5/SHBM 15 27 KBC_D5
31 A5/SHBM A5 DQ5
A6 14 28 KBC_D6
31 A6 A6 DQ6
A7 13 29 KBC_D7
31 A7 A7 DQ7
A8 3
31 A8 A8
A9 2
31 A9 A9
A10 31 30
31 A10 A10 CE# KBCBIOS_CS# 31
A11 1
31 A11 A11
A12 12
31 A12 A12
A13 4 7
31 A13 A13 WE# KBCBIOS_WE# 31
A14 5
31 A14 A14
A15 11
31 A15 A15
A16 10 32
31 A16 A16 OE# KBCBIOS_RD# 31
KBC_3D3V_AUX A17 6
31 A17 A17
A18 9
31 A18 A18
8 VDD VSS 24

PM39LV040-70VC
2 2

1 1

Wistron Corporation

om
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

l.c
Taipei Hsien 221, Taiwan, R.O.C.

ai
tm
Title

ho
BIOS/GF

f@
Size Document Number Rev

in
A3
Leopard 3 -1

xa
he
Date: Tuesday, July 12, 2005 Sheet 33 of 41
A B C D E
 A B C D E

3D3V_AUX
Adaptor in to generate DCBATOUT
16,20,31,32,35,36,37 3D3V_AUX
AD+
D15
3 1 13,35,41 AD+
AD+
Layout 200mil BT+
MMBZ5252B
DCIN1 31,35,41 BT+
4 U1 4
1 AD_JK 1 S D 8 5V_AUX
2 S D 7
3 3 S D 6
G D 14,15,35,37,38,39 5V_AUX
AD+_2 4 5
2

1
AO4407

1
4 BC52

1
SC1000P50V R15

2
5 EC1 200KR2J BC51 EC165
SCD1U50V3ZY SCD1U50V3ZY SCD1U50V3ZY
2

2
DC-JACK92

2
1 2 C274
SCD1U50V5KX

2
E

1
B Q1 R14
AD_OFF# 1 100KR2
PDTA124EU

2
C
Q2
3 OUT

3
2 R1
31 AD_OFF
IN 1 GND
R2
DTC114EUA-U1
3 3

3D3V_AUX 3D3V_AUX
3D3V_AUX
D17
2 D18 D16
2 2
BT_SCL 3
BT_SDA 3 BT_TH 3
1
1 1
BAV99LT1
BAV99LT1 BAV99LT1

BATTERY CONNECTOR
BT+
2 2

CN11
2

7
F2 1
FUSE-10A125V
2
3
1

31 BT_SCL 4
31 BT_SDA 5
G5 31,35 BT_TH 6
35 BT+SENSE 1 2 BAT+ 8

GAP-CLOSE SYN-CON6-2-U2
1

BCC1 BC3
SCD1U SC1000P50V
2

1 1

Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title
Adaptor/ Bettery conn.
Size Document Number Rev
A3
Leopard 3 -1
Date: Tuesday, July 12, 2005 Sheet 34 of 41
A B C D E
 A B C D E

DB1 3D3V_S5 3D3V_AUX

1 2 CB1 2
SCD1U
16,20,31,32,34,36,37 3D3V_AUX
3
1 2 5V_AUX
15K4R2F-GP AIRLINE_VOLT 31
R368 1

1
HM1-SB 14,15,37,38,39 5V_AUX
R366
100KR2F AD<=17V, disable BAV99LT1 DCBATOUT
-1 charger function DCBATOUT_BEAD DCBATOUT
AD+
L35 14,37,38,39,40,41 DCBATOUT

2
U43 R272 U46
8 D S 1 AD+_TO_SYS 1 2 1 2 1 S D 8 AD+
D S S D BT+
7 2 2 7
6 D S 3 D01R3720F HI1806T600R-00 3 S D 6 13,34,41 AD+

1
5 D G 4 4 G D 5
C275 R367 BT+

1
4 SC1000P50V 100KR2F 4
AO4407 AO4407

2
DY C288
SCD1U 31,34,41 BT+

2
2

2
MAX1909_ACIN G42 G41
AC_IN Threshold 2.089V Max.

1
MAX1909_PDL
AC_IN > 2.089V --> AC R365 GAP-CLOSE-PWR GAP-CLOSE-PWR

1
DETECT 19K1R3F

SET Vout MAX VCELL= 4.1998V/CELL HM1-SB

2
VBAT=CELL*VCELL==>VCELL=VBAT/CELL ACOK DCBATOUT
=VREF+(VVCTL-1.8) /9.52 =4.1998V D4
is 13V
1 2 AD+_TO_SYS
AD+
CH521S-30 MAX1909_REF

1
C68 MAX1909_LDO

1
EC166 SCD1U

1
C66 SCD1U25V3KX C67

2
1

1
C50 SCD1U25V3KX SCD1U Near MAX1909

2
SCD1U R39 C65
2 Pin 2

1
39KR3F SCD1U25V3KX C46

2
1 2 C49 C47 C45 SC10U25V0KX

4
3
2
1
CSSN1
MAX1909_LDO SC1U10V3ZY SCD1U SC10U25V0KX

MAX1909_DHIV
2/24

2
U9

G
S
S
S
Close to U11 SI4431BDY

26

25

2
MAX1909
pin 24 R37

CSSP

CSSN
33R2
1

D
D
D
D
1

R41 R40 MAX1909_PDS27 22

5
6
7
8
R304 R329 28K7R3F AD+_TO_SYS PDS DHIV
24 SRC PDL 28 Near MAX1909
54K9R3F 100KR3 20KR3F MAX1909_DC_IN 1 2
DCIN LDO Pin 21 BT+
2

1
2

21 MAX1909_DLOV C64 R324 D015R3720F-1

MAX1909_VCTL DLOV SC1U10V3ZY CHG_PWR-2
3 11 1 2 CHG_PWR-31 2 3

2
MAX1909_ICTL VCTL L23 IND-15UH-35
10 ICTL
MAX1909_MODE 7 MODE
1

23 MAX1909_DHI
D

DHI
1

R305 Q24
22K6R3F R330 2N7002-F-GP 3 ACIN

5
6
7
8

1
49K9R3F
MAX1909_IINP U10 TC12 TC13

D
D
D
D
31 CHG_I_SEL G 8
2

IINP MAX1909_DLO SI4800BDY SC10U25V0KX SC10U25V0KX

20
2

2
MAX1909_CLS DLO
9
S

MAX1909_LDO CLS
D

Q23
QB1 1 2 6 19

G
S
S
S
2N7002-F-GP R328 31K6R2F ACOK PGND

4
3
2
1
G G AC_OK 1 2 29
31 LI/NI# 31 CHG_ON# 49K9R2F PGND
R327
2N7002-F-GP 18
S

PKPRES# CSIP
1 2 5 PKPRES
R38 1KR2

G6
1 2 MAX1909_CCV 13 17
31 AD_IA CCV CSIN
MAX1909_CCI 12 16
CCI BATT BT+SENSE 34
1

3/19 HM1-SD GAP-CLOSE-PWR MAX1909_CCS 14 15

CCS GND
Detect
REF

R26
adaptor 10KR2
1

input 3D3V_AUX
2

4
1

C43 R27 C40 MAX1909ETI

current SCD1U16V3KX 16K5R3F C42 SCD01U16V3KX V_REF :4.2235V (<500uA)
2

2
1

SCD01U16V3KX
2

C41
2

SCD01U16V3KX
MAX1909_REF

-1 ISOURCE_MAX =
2

1
R325 (0.075/R615)*(VCLS/VREF) = 3.16A R307
When V(ICTL)<0.8V or DCIN<7V 27KR3F 100KR2

1
MAX1909_LDO
-->Charge Disable So,Constant Power=18.5*3.16=58.46W R308
2

2
2 2
MAX1909_CLS(90%) 100KR2

1
SET CHG OFF U48
1

R331
BAT_CHG_I = (0.075/R624)*(VICTL/3.6)

2
1

C48 100KR2
LI BAT : SC1U10V3ZY
R326 4 3
2

19K6R3F
CHG_I_SET = H(6cell),

2
31,34 BT_TH 5 2
Charge current = 3A
2

PKPRES# 6 1
CHG_I_SET = L(12cell), G7
Charge current = 3.3A 1 2
NI-MH BAT : GAP-CLOSE-PWR 2N7002S
NI_BAT = H, QB2
TP0610K-U
Charge current = 2.5A
Pre-Charge (or Maintain Charge) : MAX8725
MAX1909 : Pre-Charge current = 300mA, 2 3 1 2
499R5F BT+
D

RB2
S

MAX8725 : CHG_I_PRE_SEL = H,
DY DY
Pre-Charge current = 200mA DCBATOUT
Maintain charge current = 12.5mA
2

G
1

==> H 4sec, L 60sec RB3

100KR2

DY
1

5V_AUX
1

UB1
2N7002S RB4
1

49K9R2F
DY DY R306
1 6 1 2
R332 1K5R3F 100KR2
2

2 5 NI_BAT 31 U47
1 1
D

31 CHG_I_PRE_SEL 3 4
QB3 4 3 MAX1909_ICTL
2

2N7002-F-GP
RB1 DY G 5 2 AC_OK
31 MAINTAIN_CHG

om
100KR3F DY
DY Maintain Charge Current = 12.2mA 31 AC_IN# 6 1
S

l.c
Wistron Corporation
1

MAX1909_ICTL MAINTAIN_CHG is H 4sec, L 1sec

ai
So, Avg. Current = 9.76mA 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

tm
2N7002S Taipei Hsien 221, Taiwan, R.O.C.

ho
Title
If Charger is MAX8725,dummy them.

f@
If Charger is MAX1909,dummy them. CHARGER MAX1999

in
Size Document Number Rev

xa
C -1
Leopard 3

he
Date: Thursday, August 18, 2005 Sheet 35 of 41
A B C D E
 A B C D E

5V_S5 5V_S0 5V_S5

CPU_CORE-MAX1907

1
MAX1907_VCC R535 DCBATOUT_BEAD
10R3 R537 R554
0R3-0-U 0R3-0-U DCBATOUT_BEAD
3D3V_S0 1 2 C7 DY

2
SCD1U25V3KX

2
78.10422.2B1 DCBATOUT_BEAD
1 2 C2
2 SC4D7U10V5ZY

2
4 4

1
R13 R11 R12 D D

2
2K2R2F 100KR2 100KR2 U2 C12 C14 C286 C285 C13 C9 C287 TC10

10

34

4
SC4D7U10V5ZY D1 SCD1U SC4D7U25V6KX-L SC4D7U25V6KX-L SCD1U SE100U25V-U1

2
SSM5818SL Q15 Q4 SC4D7U25V6KX-L SC4D7U25V6KX-L

V+
VCC
1

1
30 IRFR3707Z IRFR3707Z
VDD
1 1

1
3,20 CLK_PWRGD# 38 CLKEN# G G
SYSPOK 36 31 1 2 1 2 C8

3
SYSPOK BST R10 0R3-0-U SCD1U25V3KX
20 VGATE 37 IMVPOK S S
MAX1907_S0 MAX1907_DH
MAX1907_S1
4
5
S0 DH 33 HS/IRFR3707Z/12.5mOhm/@4.5V VCC_CORE_S0
MAX1907_S2 S1 MAX1907_LX
6 S2 LX 32

29 MAX1907_DL
H_VID0 DL
5 H_VID0 26 D0 1 2
H_VID1 25 L1 IND-D68UH-10
5 H_VID1 D1
H_VID2 24 28 1 2
5 H_VID2 D2 PGND 200R2F
H_VID3 23 R5
5 H_VID3 D3

1
H_VID4 22
5 H_VID4 D4
H_VID5 21 R21 TC11 TC3 TC4 TC2
5 H_VID5 D5

1
18 1907_CSP1 1 2 C5 698R2F G2 ST220U2VDM-1 ST220U2VDM-1

2
CSP
1

MAX1907_B0 1 19 1907_CSN1 SC1000P50V 1 2 D D ST220U2VDM-1 ST220U2VDM-1

R553 MAX1907_B1 B0 CSN R8 200R2F
2

2
B1

4
100KR2 MAX1907_B2 3 GAP-CLOSE-PWR

2
B2 MAX1907_OAIN+ Q16 Q3 R20

1907_CSP_G
OAIN+ 17 1 2
MAX1907_OAIN- 1 2 C6 R7 110R2F IRFR3709Z IRFR3709Z
16 1 DY 2
2

38 CPU_SHDN# OAIN- SC470P50V2KX DUMMY-R3

1 2 7 SHDN# 1 1
1KR2

VCC_CORE_S0_G92
3 R2 G G 3
R62
Ton=NC, Freq.=300KHz 1

3
40 15 698R2F S S
TON FB
1

1 2 C4 1 2 C35
R269 DY C1 SC270P50V2JN SC100P50V2JN-U SCD47U10VKX
DUMMY-R2 1 2 MAX1907_CC 12 CC

1
14 G4
NEG

1
1 2 G3
R9 130R3F
2

MAX1907_NEG GAP-CLOSE-PWR
MAX1907_REF 8 13 LS/IRFR3709Z/8.2mOhm/@4.5V

2
REF POS
GAP-CLOSE-PWR

2
MAX1907_ILIM 9 MAX1907_POS 1907_CSP 1 2
ILIM
1

1
DPSLP#

C3 R270 GND 11 R4 DY 130R3F

TIME

27 41
SUS

SC1U10V3KX 150KR2F DDO# NC R294

2

1K18R3F 1 2
MAX1907AETL-U R293 698R2F
2

20

35

39

2
1 2 G1
PM_STPCPU# R268 100KR2F 1 2
3,17 PM_STPCPU#
1

offset 1.2%
2

1 2 R3 GAP-CLOSE
17 PM_DPRSLPVR 0R2-0 47KR3
R581
1

R271
100KR2 DY
2

R582 3D3V_S0
1

DUMMY-R2
3D3V_AUX
2

2 2

1
VCCP_GMCH_S0
R527

1
100KR2
R528 DY
OCP=30A, Vally current = 27.5A, 10KR2

2
1
Vilim=550mV(55mVp-p*10) R529 SYSPOK

D
2
4K7R2
Q31
2N7002-F-GP

2
G
Boot-up Voltage : 1.2V VID Vcore
Deeper Sleep Voltage : 0.940V

S
, B0=L, B1=L, B2=Open VID5 VID4 VID3 VID2 VID1 VID0 V

3
, S0=L, S1=L, S2=Open, Q32
0 1 0 1 1 1 1.340 1
S2N3904-U3
5V_S0 5V_S0 5V_S0 5V_S0 5V_S0 5V_S0 0 1 1 0 0 0 1.324

2
1

1
0 1 1 0 1 0 1.292
1

C462 R530
DY R264 DY R263 DY R262 DY R267 DY R266 DY R265 0 1 1 1 0 0 1.260 SCD1U10V2MX-1 22KR2J

2
DUMMY-R2 DUMMY-R2 DUMMY-R2 DUMMY-R2 DUMMY-R2 DUMMY-R2
0 1 1 1 0 1 1.244

2
0 1 1 1 1 1 1.212
2

MAX1907_S0 MAX1907_S1 MAX1907_S2 MAX1907_B0 MAX1907_B1 MAX1907_B2

1 1 0 0 0 0 1 1.180 1
1

1
1

DY R281 DY R290 1 0 0 0 1 1 1.148

R287 R282 DUMMY-R2 R292 R291 DUMMY-R2
20KR2 20KR2 20KR2 20KR2 1 0 0 1 1 0 1.100 Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
1 0 1 0 0 1 1.052 Taipei Hsien 221, Taiwan, R.O.C.
2

1 0 1 0 1 1 1.020 Title

1 0 1 1 1 0 0.972 IMVP IV-CPU POWER-MAX1907

Size Document Number Rev
1 1 0 0 0 0 0.940 A3 -1
Leopard 3
Date: Thursday, August 18, 2005 Sheet 36 of 41
A B C D E
 A B C D E

3,5,7,9,11,13,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,40,41 3D3V_S0 3D3V_S0

SYSTEM DC/DC 3D3V_S5 / 5V_S5 17,18,19,21,25,29,31,35,39,40

16,20,31,32,34,35,36
3D3V_S5

3D3V_AUX
3D3V_S5

3D3V_AUX

14,18,20,36,38 5V_S5 5V_S5

14,15,35,38,39 5V_AUX 5V_AUX

14,35,38,39,40,41 DCBATOUT DCBATOUT

DCBATOUT
5V_AUX MAX1999_VCC
4 4

1 2 MAX1999_V+ 1 2
R83 4D7R5 R387 47R2
Sanyo / 6*7.7 / CV-AX
5V = 5Arms,

1
C80 C81 C319

3
SC1U25V5ZY SCD1U SC1U10V3ZY
OCP>6.8A

2
D21
BAW56-1
DCBATOUT

2
C121 C120
SCD1U SC4D7U25V-U

1
MAX1999_BST3

8
7
6
5
C82 C83 C98
3V = 4Arms,

5
6
7
8
SC4D7U25V-USC4D7U25V-U SCD1U

D
D
D
D
U24 U16

2
1

1
AO4422

D
D
D
D
OCP>6A C336
SCD1U50V5KX
R399
0R3-U U54
R362
0R3-U
C303
SCD1U50V5KX

20

17
2

2
3D3V_DC_S5 CLOSE TO 5V_DC_S3

S
S
S
G

V+

VCC
1

1
CMOS AO4422

1
2
3
4

G
S
S
S
MAX1977_BST3R
28 BST3 14 MAX1999_BST5R

4
3
2
1
BST5

MAX1999_DH3 26 16 MAX1999_DH5
DH3 DH5
1 2 MAX1999_LX3 27 15 MAX1999_LX5 1 2
3 L30 IND-8UH-2 LX3 LX5 L28 IND-8UH-2 3
MAX1999_DL3 24 19 MAX1999_DL5
DL3 DL5
8
7
6
5

5
6
7
8

1
22 21 U19
OUT3 OUT5

1
D
D
D
D
U25 TC14

D
D
D
D
1

AO4422 MAX1999_FB3 7 9 MAX1999_FB5 C79 ST150U6D3VDM-9

2
C96 FB3 FB5 SC47P50V2JN

2
SC47P50V2JN
1 2
1

1
TC19 MAX1999_ON3 3 AO4422
S
S
S
G

G
S
S
S
ST220U4VDM-L3 R90 Rds(on) = 24 mohm MAX1999_ON5 ON3 MAX1999_PRO# R81 R79
4 10 1 2
2

1
2
3
4

4
3
2
1
ON5 PRO#
1

1
2MR3 1 R385 100KR2 Rds(on) = 24 mohm 2MR3 15K4R3
C78 R80 MAX1999_SHDN# NC C77
6 SHDN#
SC100P50V2JN-U 6K98R3F SC100P50V2JN-U
2

2
2

11 MAX1999_ILIM
ILIM5
1

1
13 MAX1999_VCC
R82 TON R78
ILIM3 5
10KR3F 2 1 10KR3F
These components should be R77 300KR3
located near by MAX1977 20,38 1999_S5ENABLE 1 2 8 2
2

2
REF PGOOD

2
R393 1KR2
17,21,31,38 PM_SLP_S4# 1 2 R75 These components should be
D6 1SS400 R386 1KR2 12 23 200KR3
SKIP# GND located near by MAX1977

LDO3

LDO5
2 1
MAX1999_REF
DY

1
2 MAX1999EEI 2
39 BL3# 2 1 Vref = 2V

25

18
DY
2

D5 1SS400 3V_LDO=100mA 5V_LDO=100mA

5V_AUX C316
SCD22U10V3KX MAX1999_LDO3 MAX1999_LDO5 5V_AUX
1

5V_DC_S3 5V_S3 MAX1999_V+

1

G44
R384 1 2
1

300KR2J
R76 GAP-CLOSE-PWR
1

1
300KR3 ILIM5: 5V * 200K / (200K+300K) = 2.0V
2

MAX1999_SKIP# C320 C318 200mV / 24 = 8.3A

SC1U10V3KX SC2D2U6D3V3MX-1
2

2
OCP point = 8.3A +1/2Iripple
3D3V_AUX G45
1

1 2 ILIM3: 5V * 200K / (200K+300K) = 2.0V

R74 3D3V_S5
150KR3
200mV / 24 = 8.3A
Q26 GAP-CLOSE-PWR
OCP point = 8.3A +1/2Iripple
3 OUT
1

2 R1 OCP point = 20A +1/2Iripple

2

IN 1 GND EC167
R2 SCD1U25V3KX
ILIM*=Vcc 100mV
2

DTC115EE-U 5V_S5 spec. = 10mA

17,21,28,31,38,40 PM_SLP_S3#
ILIM*=Vref 200mV
3D3V_DC_S5 3D3V_S5 OCP= 0.1Vth/Rds(on) + 0.5Iripple
PM_SLP_S3# high = PWM
PM_SLP_S3# low = Ultrasonic MAX1999_ON3
1 1
G21
SKIP# > 2.4V : PWM mode MAX1999_ON5 1 2
SKIP# = GND( ,0.8V) : SKIP MODE Wistron Corporation
1

GAP-CLOSE

om
SKIP# = REF (1.7V~2.3V)/FloatING C317 C331 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
DY

l.c
Ultrasonic MODE(25KHz min) DUMMY-C2 DUMMY-C2 Taipei Hsien 221, Taiwan, R.O.C.

ai
tm
DY Title

ho
DC/DC 3V_S5/5V_S5
2

f@
Size Document Number Rev

in
A3 -1
Leopard 3

xa
he
Date: Monday, August 15, 2005 Sheet 37 of 41
A B C D E
 A B C D E

For 1.5V
SETTING=1.517V
PWM_1D5V TI TPS5130 for 1D8V, 1.5V, 1.05V.
1
R413
2
680R2
1 2 C348
SC4700P50V3KX
(1D5V=>CH1 , 1D8V=>CH2 , 1D05V =>CH3)
1
R416
2
10KR3F OCP_1.05V
1 2 DCBATOUT
1 R410 7K87R2F 1 2
R409 R408 15KR3
3K9R2F 5130_TRIP1
C346
4 1 2 4
1 2

For 1.05V PWM_1D05V SCD1U16V3KX

C349 5130_INV1 SETTING=1.061V
SC4700P50V3KX 1 2 1 2 C333 5V_DC_S5 close to IC
2

5130_FB1 R396 680R2 SC5600P25V2KX

1 2 OCP_1.8V -1

3
R398 80K6R3F
R407
For 1.8V 1 2 D24 15KR3 DCBATOUT
PWM_1D8V R395 20KR2F BAW56-1 1 2

1
SETTING=1.8V
1 2 1 2 C347 R397 5130_LH1 5130_TRIP2 G28

2
R411 680R2 SC5600P25V2KX 2K7R2J C345 1 2
1 2 C115 SCD1U50V5KX 1 2
R415 10K2R3F 1 2 5130_LL1 GAP-CLOSE
5130_LL1 39

1 2
1 2 SCD1U16V3KX
1

R412 11K5R2F
R414 C334 5130_INV3 5130_OUT1U close to IC
5130_OUT1U 39
2KR2F SC3300P50V2KX 5130_OUT1D
5130_OUT1D 39

2
5130_FB3
SB OCP_1D5V
1 2

5130_TRIP1 DCBATOUT
DCBATOUT 1 2
C350 5130_INV2 5130_TRIP2 R394 20KR3
SC3300P50V2KX 5130_TRIP3
2

5130_FB2 5130_FLT C332

1 2

1
5130_FLT 5130_OUT2D
5130_OUT2D 39
1 2 C116 5130_INV1 SCD1U16V3KX
5V_AUX 100KR2 SCD01U16V3KX
3 R360 3
close to IC

2
U23

48
47
46
45
44
43
42
41
40
39
38
37
C114 SCD1U50V5KX

FLT
INV1

LH1

OUTGND1
TRIP1

TRIP2
OUT1_U
LL1
OUT1_D

VIN_SENSE12

OUTGND2
OUT2_D
5130_LH2 1 2 5130_LL2
5130_LL2 39
6

U51
2N7002S
close to IC DCBATOUT
5130_FB1 1 36
5130_SS_STBY1 FB1 LL2 5130_OUT2U
2 SS_STBY1 OUT2_U 35 5130_OUT2U 39 1 2 C344 5V_DC_S5 5V_S5
5130_INV2 3 34 SCD1U
1

5130_FB2 INV2 LH2

4 FB2 VIN 33
5130_SS_STBY2 5 32 G52
5130_SS_STBY1 5130_PWM_SEL SS_STBY2 VREF3.3
6 PWM_SEL VREF5 31 1 2
5130_CT 7 30 1 2
CT
TPS5130 REG5V_IN 5V_S3
1

8 29 R552 0R2-0 GAP-CLOSE-PWR

GND LDO_IN

1
PM_SLP_S3# C119 5130_REF 9 28
SC1500P50V3KX REF LDO_CUR C93
10 27
2

STBY_VREF5 LDO_GATE

2
1 2 STBY_REF 11 26 SC4D7U10V5ZY

2
20,37 1999_S5ENABLE R392 1KR3 STBY_VREF3.3 LDO_OUT C463
12 STBY_LDO INV_LDO 25
1 2 SCD1U
5V_AUX

1
R359 100KR2

VIN_SENSE3
PG_DELAY
SS_STBY3

OUTGND3
6

OUT3_U

OUT3_D
PGOUT

TRIP3
U50

INV3

LH3
FB3
2 2

LL3
2N7002S 5130_CT
For 1.5V
1

TPS5130PT-U

13
14
15
16
17
18
19
20
21
22
23
24
C117 SETTING=1.505V
SC47P50V2JN
1

5130_SS_STBY3
5130_FB3
5130_SS_STBY2 5130_INV3
5130_OUT3D 5V_AUX
5130_OUT3D 39
1

5130_LL3
17,21,31,37 PM_SLP_S4# C118 5130_REF 5130_OUT3U
5130_OUT3U 39
1

1
SC4700P50V3KX
2

C95 5130_LH3 1 2 R383

5130_LL3 39 300KR2J
C97 SC1000P25V C94 SCD1U50V5KX
2

SCD1U16V3KX
2

D23 2 5V_DC_S5

2
3 5130_PWM_SEL
1 Q25
3 OUT
DCBATOUT 2 R1
17,21,28,31,37,40 PM_SLP_S3#
5V_AUX 1 2 BAT54-1 IN 1 GND
R361 100KR2 R2
DTC115EE-U
3D3V_S0
5130_TRIP3
6

U53 3D3V_S0
1 2N7002S R170 1
10KR2
U37A
14

Wistron Corporation
2

20 VCCP_PWGD 1
1

3 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

CPU_SHDN# 36
PM_SLP_S3# 2 Taipei Hsien 221, Taiwan, R.O.C.
5130_SS_STBY3
TSLCX08-U Title
7
1

PM_SLP_S3# C335 DC/DC 2D5V/1D5V/1D05V

SC1500P50V3KX Size Document Number Rev
2

HW Thermal Throttling A3 -1
Leopard 3
Date: Monday, August 15, 2005 Sheet 38 of 41
A B C D E
 A B C D E

TI TPS5130 for 2.5V, 1.5V, 1.05V 14,35,37,38,40,41 DCBATOUT DCBATOUT

17,18,19,21,25,29,31,35,37,40 3D3V_S5 3D3V_S5

(1D5V=>CH1 , 2D5V=>CH2 , 1D05V =>CH3) 14,15,35,37,38 5V_AUX 5V_AUX

18 1D5V_S5 1D5V_S5
DCBATOUT
1D5V/5A 7,9,10,11,12,38,40,41 1D8V_S3 1D8V_S3

OCP=10A 13,14,18,19,20,21,23,24,27,28,29,32,36,40,41 5V_S0 5V_S0

1
12 0D9V_S0 0D9V_S0
4 C128 C129 4

5
6
7
8
SCD1U SC4D7U25V6KX-L

2
U27

D
D
D
D
SI4800BDY
1.5V_S5 (For ICH6)
PWM_1D5V 1D5V_S0

G
S
S
S
PWM_1D5V PWM_1D05V 1D05V_S0

4
3
2
1
1D5V_S5
5130_OUT1U
38 5130_OUT1U
5130_LL1 1 2 U59
38 5130_LL1 L31 IND-4D7UH-56 3D3V_S5

VOUT 2
3 VIN
GND 1
5
6
7
8

1
U26

1
D
D
D
D

IRF7807Z C414
TC18 G9131-15T73UF-GP SC10U10V6ZY-U

2
Rds(on)=16mOhm ST220U2VDM-1

2
G
S
S
S
4
3
2
1

Imax=300mA
5130_OUT1D
38 5130_OUT1D
PWM_1D8V 1D8V_S3

3 3
DCBATOUT

Power budget:0D9V/2.2Apeak (For DDR2_VTT) 1D8V_S3

1

C112 C113
5
6
7
8

SCD1U SC4D7U25V6KX-L
2

1
U22
D
D
D
D

SI4800BDY C367 5V_S0 1D8V_S3

SC10U10V5ZY-L

2
0D9V / 1A

1
G
S
S
S

1
0D9V_S0 R446
4
3
2
1

PWM_1D8V C376 1KR2F

5130_OUT2U U58 SCD1U10V2MX-1
38 5130_OUT2U

2
5130_LL2 1 2

2
38 5130_LL2 L29 IND-4D7UH-56 4 VOUT VIN 1
3 APL533_VREF1 1 2
VREF 0R2-0 DDR_VREF_1 40
TC20 8 6 R133
NC VCNTL
5
6
7
8

1
U21 TC8 C460 ST150U4VBM-L17
NC

1
D
D
D
D

IRF7807Z 5 2
NC GND

1
Rds(on)=16mOhm SE220U16VM-U SC10U10V5ZY-L 9 R447

2
GND C368 1KR2F
1

SCD1U10V2MX-1

2
TC17 DY
G
S
S
S

APL5331KAC-TR

2
R446,R447 for 1G Memory
4
3
2
1

ST330U3VDM-1-GP
2 2

38 5130_OUT2D
5130_OUT2D
L3# circuit
5V_AUX
DCBATOUT
1

1
C75 C76 DCBATOUT C293
5
6
7
8

SCD1U SC4D7U25V6KX-L SCD1U10V2MX-1

2

2
U18
D
D
D
D

SI4800BDY

U52
1
G
S
S
S

R363 HTH 1 5 D20

4
3
2
1

1MR2F HTH VCC

2 GND 2
PWM_1D05V 3 4 3
5130_OUT3U LTH RESET#/RESET
38 5130_OUT3U 1 RSMRST# 16,20,31
2

38 5130_LL3 5130_LL3 1 2
L27 IND-4D7UH-56 L3# at 8.13V G680LT1
1D05V/5A BAT54-1
1

OCP=10A R364
37 BL3#
5
6
7
8

U15 6K04R2F
1
D
D
D
D

1
IRF7807Z 1
1

Rds(on)=16mOhm R73
2

1KR2 TC5 HTH

ST220U4VDM-10
DY Wistron Corporation
2
G
S
S
S

om
2

21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

4
3
2
1

l.c
R323 Taipei Hsien 221, Taiwan, R.O.C.
174KR2F

ai
tm
5130_OUT3D Title
38 5130_OUT3D

ho
39.DC/DC 1D8V/1D5V/1D05V-2
2

f@
Size Document Number Rev

in
A3 -1
Leopard 3

xa
he
Date: Thursday, August 18, 2005 Sheet 39 of 41
A B C D E
 A B C D E

3,5,7,9,11,13,14,16,17,18,19,20,21,22,23,24,25,27,29,30,31,32,36,38,41 3D3V_S0 3D3V_S0

13,14,30 3D3V_S3 3D3V_S3

17,18,19,21,25,29,31,35,37,39 3D3V_S5 3D3V_S5

FOR GMCH Power 13,14,18,19,20,21,23,24,27,28,29,32,36,39,41 5V_S0 5V_S0

13,14,26,28,30,32,37,38,41 5V_S3 5V_S3

G27 14,18,20,36,38 5V_S5 5V_S5
1 2
7,9,15,18 2D5V_S0 2D5V_S0
4 GAP-CLOSE-PWR 4
7,9,10,11,12,38,39,41 1D8V_S3 1D8V_S3
G26
CORE_GMCH_S0 1 2 1D05V_S0 7,11 DDR_VREF_S3 DDR_VREF_S3
GAP-CLOSE-PWR 14,35,37,38,39,41 DCBATOUT DCBATOUT
G25 38,39,41 1D05V_S0 1D05V_S0
1 2
4,5,6,7,9,10,16,18,36,41 VCCP_GMCH_S0 VCCP_GMCH_S0
GAP-CLOSE-PWR
6,9,10,41 CORE_GMCH_S0 CORE_GMCH_S0

G14
1 2

GAP-CLOSE-PWR
1D8V_S3
G15
1 2 5V_S3
VCCP_GMCH_S0 1D05V_S0

1
GAP-CLOSE-PWR
C183 R130 1 2 C206
DDR_VREF_S3 need 10 mil and
SCD1U16V3KX 220R3F SCD1U16V
G16 must neat NB and DIMM

2
1 2
U31

2
GAP-CLOSE-PWR 1 5 DDR_VREF_S3
39 DDR_VREF_1 IN+ VDD
2 VSS

1
3 3 4 3
C184 R132 IN- OUT

1
SCD1U16V3KX 220R3F G1214 VREFOUT = 0.9V
DY

2
C167
SCD1U16V

2
1 2
R131 0R3-U

FOR DDR 2 Power

Q27

Run Power TP0610K-U

DCBATOUT
2 3 5V_S0 5V_S3 Suspend Power
D
S

U20
1 S D 8
1 2 2 S D 7
R437 10KR2
G

3 6
1

2 PWR_S0_CTL
S D
3D3V_S3 3D3V_S5 2
4 G D 5
1

AO4422 2 1
C369 D27 R95 0R3-U
1 2 SCD22U50V5KX MMGZ5242B 3D3V_S0 3D3V_S5
2

R438 330KR2 U56

1 8
1

S D
2 S D 7
3 6
1

S D
4 5
1

G D
R436
1KR2 RB5 AO4422
100R2
2

Q28
D

2N7002-F-GP
QB5
2N7002-F-GP
17,21,28,31,37,38 PM_SLP_S3# G G
S

3D3V_S0 2D5V_S0
2

1
R448 U69 1
100KR2
VOUT 2
3
Wistron Corporation
1

VIN
1

GND 1
1

C468 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

C467 SC10U6D3V5MX Taipei Hsien 221, Taiwan, R.O.C.
2

SCD1U10V2MX-1 APL5308-25AC-TR
2

Title
PWRPLANE&RESETLOGIC
Size Document Number Rev
A3
Leopard 3 -1
Date: Tuesday, July 12, 2005 Sheet 40 of 41
A B C D E
 A B C D E
AD+
DCBATOUT_BEAD DCBATOUT DCBATOUT

1
EC79 EC98 EC129 EC105 EC108 EC99 EC106 EC76 EC109 EC90 EC81 EC3 EC77 EC5 EC4

1
EC35 EC125 EC136 EC145 EC158 SCD1U25V3KX SCD1U25V3KX SCD1U25V3KX SCD1U25V3KX SCD1U25V3KX SC1000P50V SCD1U25V3KX SCD1U25V3KX

2
EC132 EC157 EC151 EC74 SCD1U25V3KX SCD1U25V3KX SCD1U25V3KX SCD1U25V3KX SCD1U25V3KX SCD1U25V3KX
SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U25V3KX

2
SCD1U16V SCD1U16V SCD1U25V3KX

DY DY DY DY DY DY DY DY VCCP_GMCH_S0
4 4
AUD_AGND AUD_AGND BT+
AUD_AGND AUD_AGND AUD_AGND

1
EC168 EC104 EC9 EC96 EC7 EC118 EC111 EC134

1
EC169 EC160 EC161 EC162 EC163 EC164 EC52 EC91 EC14
SCD1U25V3KX SCD1U16V SCD1U16V SCD1U16V SCD1U16V

2
SCD1U25V3KXSCD1U25V3KXSCD1U25V3KXSCD1U25V3KX SCD1U16V SCD1U16V SCD1U16V SCD1U16V

2
5V_S0 SCD1U25V3KXSCD1U25V3KXSCD1U25V3KXSCD1U25V3KX

1
5V_S0 5V_AUDIO_S0 EC171 EC75 EC128 EC73 EC107 EC2 EC6 EC13 EC15 EC97
EC78
SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V 1D05V_S0 1D8V_S3 3D3V_LAN_S5

2
U61D U40D SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V
14

14

12 12

1
11 11 EC32 EC119 EC26 EC28 EC27 EC25 EC24 EC117 EC122
13 13 EC21 EC116 EC30
SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V

2
TSAHCT32 TSAHCT86 SCD1U16V SCD1U16V SCD1U16V SCD1U16V
7

AUD_AGND AUD_AGND
3D3V_S0

3D3V_S0 3D3V_S0 3D3V_S0

1
3 3
EC140 EC155 EC50
SCD1U16V SCD1U16V SCD1U16V

1
EC41 EC57 EC137 EC150 EC71 EC143 EC127 EC123
EC141 EC130 EC70 EC138 EC144
SPR8 SPR2 SPR3 SPR7 SPR4 SPR1 SPR9 AUD_AGND AUD_AGND SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V

2
DY SCD1U16V SCD1U16V SCD1U16V SCD1U16V

SPRING-18-U SPRING-18-U SPRING-18-U SPRING-18-U SPRING-18-U SPRING-18-U SPRING-18-U

1

1
DY DY DY DY DY DY DY DY DY DY DY DY DY

5V_S3 3D3V_S0

1
K72 EC55 EC139 EC48 EC65 EC58 EC47 EC43
GNDPAD EC131 EC62 EC46
SPR12 SPR13 SPR14 SPR17 SPR11 SPR15 SPR16 SPR10 SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V

2
SCD1U16V SCD1U16V

SPRING-4 SPRING-4 SPRING-4 SPRING-4 SPRING-4 SPRING-4SPRING-4 SPRING-4

1

DY DY DY DY DY DY DY DY
1

K70 K71 1 K69 5V_S3 5V_S3 5V_S3

GNDPAD GNDPAD GNDPAD

1
EC147 EC53
2 EC67 EC59 EC66 EC72 EC64 EC29 EC51 EC38 EC45 EC23 2
SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V

2
SCD1U16V SCD1U16V SCD1U16V SCD1U16V
H19 H17 H14 H8 H11 H10 H12 H15
HOLE HOLE HOLE HOLE HOLE HOLE
DY DY DY DY DY DY DY DY DY DY

CORE_GMCH_S0
1

5V_S0 5V_S0 5V_S0

1

1
EC170 EC113 EC112 EC120 EC40 EC68 EC69
EC61 EC60 EC49 EC54 EC142 EC37 EC63
H5 H13 H6 H7 H4 H16 H21 H23 H25 SCD1U25V3KXSCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V
2

2
HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE HOLE SCD1U16V SCD1U16V SCD1U16V

DY DY DY DY DY DY DY DY DY DY
1

1D5V_S0
1

1
EC133 EC115 EC10 EC33 EC148 EC126 EC34 EC146 EC149 EC121 EC135 EC114
1 1
H1 H9 H2 H3 H22 H20 H18 H24 SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V
2

2
HOLE HOLE HOLE HOLE HOLE HOLE SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V SCD1U16V

Wistron Corporation

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21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,

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Taipei Hsien 221, Taiwan, R.O.C.

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Title

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MISC & EMI

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Size Document Number Rev

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A3 -1
Leopard 3

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Date: Tuesday, July 12, 2005 Sheet 41 of 41
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