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Phony Targets:: Clean: RM .O Temp RM Make Clean

The document discusses various aspects of makefiles including: 1. Phony targets which are targets that are not files and allow rules to always run when the target is specified. 2. Using variables in recipes by prefixing with '$' or '$$' to reference make or shell variables respectively. 3. Automatic variables like '$@' for the target name and '$<' for the first prerequisite. 4. Multiple targets can be specified for a single rule to avoid duplicating recipes. The target name '$@' is substituted for each target.

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Dan Kumar Yadav
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91 views4 pages

Phony Targets:: Clean: RM .O Temp RM Make Clean

The document discusses various aspects of makefiles including: 1. Phony targets which are targets that are not files and allow rules to always run when the target is specified. 2. Using variables in recipes by prefixing with '$' or '$$' to reference make or shell variables respectively. 3. Automatic variables like '$@' for the target name and '$<' for the first prerequisite. 4. Multiple targets can be specified for a single rule to avoid duplicating recipes. The target name '$@' is substituted for each target.

Uploaded by

Dan Kumar Yadav
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Note that assigning more than one target name to .

DEFAULT_GOAL is invalid and


will result in an error.

Phony Targets:
A phony target is one that is not really the name of a file; rather it is just a name for a
recipe to be executed when you make an explicit request. There are two reasons to
use a phony target:
1) To avoid a conflict with a file of the same name, and 
2) To improve performance.

If you write a rule whose recipe will not create the target file, the recipe will be
executed every time the target comes up for remaking. Here is an example:
clean:
    rm *.o temp
Because the rm command does not create a file named clean, probably no such file
will ever exist. Therefore, the rm command will be executed every time you say
‘make clean’.
In this example, the clean target will not work properly if a file named clean is ever
created in this directory. Since it has no prerequisites, clean would always be
considered up to date and its recipe would not be executed. To avoid this problem
you can explicitly declare the target to be phony by making it a prerequisite of the
special target .PHONY
For example:
.PHONY: clean
clean:
    rm *.o temp 
Once this is done, ‘make clean’ will run the recipe regardless of whether there is a
file named clean.
Phony targets are also useful in conjunction with recursive invocations of make.

Rules without Recipes or Prerequisites:


If a rule has no prerequisites or recipe, and the target of the rule is a nonexistent file,
then make imagines this target to have been updated whenever its rule is run. This
implies that all targets depending on this one will always have their recipe run.
An example will illustrate this:
clean: FORCE
    rm $(objects)
FORCE:
Here the target ‘FORCE’ satisfies the special conditions, so the target clean that
depends on it is forced to run its recipe. There is nothing special about the name
‘FORCE’, but that is one name commonly used this way.
As you can see, using ‘FORCE’ this way has the same results as using ‘.PHONY:
clean’. Using ‘.PHONY’ is more explicit and more efficient. However, other versions
of make do not support ‘.PHONY’; thus ‘FORCE’ appears in many makefiles.

Using Variables in Recipes:


To substitute a variable’s value, write a dollar sign followed by the name of the
variable in parentheses or braces: either ‘$(foo)’ or ‘${foo}’ is a valid reference to the
variable foo.

if you want a dollar sign to appear in your recipe, you must double it (‘$$’). For shells
like the default shell, that use dollar signs to introduce variables, it’s important to
keep clear in your mind whether the variable you want to reference is a make
variable (use a single dollar sign) or a shell variable (use two dollar signs).
For example:
LIST = one two three
print:
    for i in $(LIST); do \
      echo $$i; \
    done  
#Command:
#    make print
#Output:
#    one
#    two
#    three
Variable references work by strict textual substitution.

Environment variables can be accessed by using both $ (a single dollar sign) and $


$ (two dollar signs).
For example:
.PHONY: display
display:
    echo $(HOME)
    echo $$HOME 
#Command:
#    make display
#Output:
#     /home/sagar.shah
#     /home/sagar.shah

Generally in most of the shells HOME is predefined environment variable.


But if make file also has (locally defined) variable with same name then locally
defined value has high priority.
HOME = /home/sagar.shah/docs
.PHONY: display_home
display_home:
    echo $(HOME)
    echo $$HOME 
#Command:
#    make display_home
#Output:
#     /home/sagar.shah/docs
#     /home/sagar.shah/docs
Automatic Variables:
$@
The file name of the target of the rule. If the target is an archive member, then ‘$@’
is the name of the archive file. In a pattern rule that has multiple targets, ‘$@’ is the
name of whichever target caused the rule’s recipe to be run.

$%
The target member name, when the target is an archive member. For example, if the
target is foo.a(bar.o) then ‘$%’ is bar.o and ‘$@’ is foo.a.
‘$%’ is empty when the target is not an archive member.

$<
The name of the first prerequisite.
If the target got its recipe from an implicit rule, this will be the first prerequisite added
by the implicit rule.

$?
The names of all the prerequisites that are newer than the target, with spaces
between them.
For prerequisites which are archive members, only the named member is used.

$^
The names of all the prerequisites, with spaces between them.
For prerequisites which are archive members, only the named member is used.
A target has only one prerequisite on each other file it depends on, no matter how
many times each file is listed as a prerequisite. So if you list a prerequisite more than
once for a target, the value of $^ contains just one copy of the name.
This list does not contain any of the order-only prerequisites; for those see the ‘$|’
variable, below.

$+
This is like ‘$^’, but prerequisites listed more than once are duplicated in the order
they were listed in the makefile. This is primarily useful for use in linking commands
where it is meaningful to repeat library file names in a particular order.

$|
The names of all the order-only prerequisites, with spaces between them.

S(MAKE)
The value of this variable is the file name of Makefile.
For Example:
.PHONY:create_dir
create_dir:
    mkdir -p dir

.PHONY:create
create:
    touch file.txt
    $(MAKE) create_dir
 
#Command:
#    make create
#Output:
#     Directory named "dir" and File named "file.txt" will be created

Multiple Targets in a Rule:


A rule with multiple targets is equivalent to writing many rules, each with one target,
and all identical aside from that. The same recipe applies to all the targets, but its
effect may vary because you can substitute the actual target name into the recipe
using ‘$@’. The rule contributes the same prerequisites to all the targets also.
For Example:
bigoutput littleoutput : text.g
    generate text.g -$(subst output,,$@) > $@

is equivalent to

bigoutput : text.g
    generate text.g -big > bigoutput
littleoutput : text.g
    generate text.g -little > littleoutput

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