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INCLUDING SIGNAL DIODES

'_: ~IRCUITS
·1~PPLIC/~TIONS · SPECIFICATION
. i - ,/ ' _, -- ·
 TRANSISTOR
MANUA SIXTH
EDITION

CONTRIBUTORS
Application Engineering
J. H. Phelps - Manager
J. F. Cleary
J. Giorgis
E. Gottlieb
D. J. Hubbard
D. V. Jones
E. F. Kvamme
G. E. Snyder
EDITED AND PRODUCED BY R. A. Stasior
Semiconductor Products Department
Advertising & Sales Promotion
General Electric Company Others
Electronics Park W. P. Barnett
Syracuse, New York R. E. Belke
D. W. Cottle
U.S. Davidsohn
TECHNICAL EDITOR K. Schjonneberg
J. F. Cleary T. P. Sylvan

I
 The circuit diagrams included in this manual are included for
illustration of typical transistor applications and are not intended
as constructional information. For this reason, wattage ratings of
resistors and voltage ratings of capacitors are not necessarily given.
Similarly, shielding techniques and alignment methods which may
be necessary in some circuit layouts are not indicated. Although
reasonable care has been taken in their preparation to insure their
technical correctness, no responsibility is assumed by the General
Electric Company for any consequences of their use.
The semiconductor devices .and arrangements disclosed herein·
may be covered by patents of General Electric Company or others.
Neither the disclosure of any information herein nor the sale of
semiconductor devices by General Electric Company conveys any
license under patent claims covering combinations of semiconductor
devices with other devices or elements. In the absence of an express
written agreement to the contrary General Electric Company as-
sumes no liability for patent infringement arising out of any use
of the semiconductor devices with other devices or elements by any
purchaser of semiconductor devices or others.

Copyright 1962
by the
General Electric Company

II
 CONTENTS
Page

1. SEMICONDUCTORTHEORY........................ 1
Semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Conduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Space Charge Neutrality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Diffusion and Drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Diodes ............................................... 11
Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2. TRANSISTORCONSTRUCTIONTECHNIQUES.... .. 15
Metal Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Junction Formation .................................... 16
Alloy Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Grown Junction Transistors ............................. 20
Germanium Mesa Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Silicon Planar Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Encapsulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3. THE TRANSISTORSPECIFICATIONSHEET......... 28
General Device Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Voltage ............................................ 30
Current ............................................ 34
Transistor Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Temperature ....................................... 35
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Cutoff Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
High Frequency Characteristics . . . . . . . . . . . . . . . . . . . . . . . 36
Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Generic Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Explanation of Parameter Symbols . . . . . . . . . . . . . . . . . . . . . . . 38
Symbol Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Decimal Multipliers .................................. 39
Parameter Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Abbreviated Definitions of Terms ...................... 43
4. SMALLSIGNALCHARACTERISTICS............... 47
5. LARGESIGNALCHARACTERISTICS
................ 65
Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Basic Eq nations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Active Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Saturated Operation ................................... 67
Cutoff Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Useful Large Signal Relationships ....................... 69
Collector Leakage Current (IcEo) . . . . . . . . . . . . . . . . . . . . . . 69
Collector Leakage Current (IoEs) . . . . . . . . . . . . . . . . . . . . . . . 69
Collector Leakage Current (IcBa) . . . . . . . . . . . . . . . . . . . . . . 70
Collector Leakage Current-Silicon Diode in Series with
Emitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Base Input Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Voltage Comparator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

III
 Page
6. SWITCHINGCHARACTERISTICS
................... 73
Steady State Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Transient Response Characteristics ....................... 81
Transient Response Prediction . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Circuit Techniques to Augment Switching Characteristics ... 96
7. BIASING ........................................... 101
Thermal Runaway ..................................... 109
8. AUDIOAMPLIFIERS ............................... 113
Single Stage Audio Amplifiers : .......................... 113
Two Stage R-C Coupled Amplifier ....................... 113
Class B Push-Pull Output Stages ........................ 114
Class A Output Stages ................................. 115
Class A Driver Stages ................................. 116
Design Charts ........................................ 116
Preferred Types and Substitution Chart ................... 122
9. HIGH FIDELITYCIRCUITS ......................... 125
Preamplifiers ......................................... 125
Bass Boost Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Power Amplifiers ..................................... 130
Stereophonic System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Silicon Power Amplifiers ............................... 133
12-Watt Amplifier .................................... 137
NPN Preamplifier ..................................... 139
1O. RADIORECEIVERANDTUNERCIRCUITS ......... 141
Autodyne Converter Circuits ........................... 141
I. F. Amplifiers ....................................... 142
Emitter Current Control ............................. 143
Auxiliary A. V. C. Systems ............................ 144
Detector Stage ....................................... 145
Reflex Circuits ........................................ 146
F. M. Tuner ......................................... 147
A. M. Tuner . . . . ..................................... 147
Complete Radio Receiver Diagrams ...................... 148
Additional Component Information ..................... 154
11. BASICCOMPUTERCIRCUITS..................... .155
Flip-Flop Desi~ Procedures ............................ 155
Saturated Flip-Flops ................................ 155
Non-Saturated Flip-Flop Design ........................ 158
Non-Saturating Flip-Flop Design Procedure ................ 161
Triggering ............................................ 166
Special Purpose Circuits ................................ 169
Schmitt Trigger .................................... 169
Astable Multivibrator ................................ 170
Monostable Multivibrator ............................ 170
Indicator Lamp Driver ............................... 171
Pulse Generator ..................................... 171
Ring Counter ....................................... 173
12. LOGIC............................................. 175
Common Logic Systems ................................ 184
Binary Arithmetic ..................................... 188
13. UNIJUNCTIONTRANSISTORCIRCUITS............ 191
Theory of Operation ................................... 191
Parameters-Definitions and Measurement .................. 193
Relaxation Oscillator ................................... 194

IV
 Page
Ultra-Linear Sawtooth Wave Generator ................... 196
Voltage Sensing Circuit ................................ 196
Staircase Wave Generator .............................. 197
Time Delay Relay ..................................... 198
Multivibrator ......................................... 198
Hybrid Timing Circuits ................................ 199
14. FEEDBACKAND SERVOAMPLIFIERS-
TRANSISTORCHOPPERS.......................... 203
Use of Negative Feedback in Transistor Amplifiers .......... 203
Servo Amplifiers for Two Phase Servo Motors .............. 206
Preamplifiers ........................................ 206
Bias Design Procedure for Stage Pair. . . . . . . . . . . . . . . . . . . 206
Driver Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Output Stage ....................................... 210
Junction Transistor Choppers ............................ 214
15. TRANSISTORMEASUREMENTS................... 219
Introduction .......................................... 219
Reverse Diode Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
General ............................................ 220
D. C. Tests ........................................ 221
Current Measurements ............................... 226
Large Signal (D. C.) Transistor Characteristics ............. 228
Large Signal Definitions and Basic Test Circuits ........... 229
Some Test Circuits .................................. 230
Junction Temperature Measurements ..................... 233
Junction Temperature (TJ) ............................ 233
Thermal Impedance .................................. 233
Test Circuit for Junction Temperature Measurements ..... 234
Small Signal Measurements (Audio) of Transistor Parameters .. 238
Common Base Configuration ........................... 238
Common Emitter Configuration ........................ 240
Common Collector Configuration ...................... 243
General ............................................ 244
High Frequency Small Signal Measurements of Transistor
Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Input Impedance (h11,,h,.) ............................ 246
Output Admittance (hob, hoe) ......................... 248
Forward Current Ratio (htb, hre, and fhrb) ................. 250
Power Gain Measurement .............................. 256
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Measuring Power Gain ............................... 257
Neutralization ....................................... 259
Transistor Noise Measurements .......................... 261
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
Measurement of Noise Figure ......................... 262
Equivalent Noise .ciment ang_Noise Voltage ............. 264
Measurement of (e:/)½ and (i:,.2)* For Transistors ......... 266
Measurement of Noise Factor without using Signal Generator
or Noise Diode ................................... 267
Transistor Noise Analyzer ............................ 269
Charge Control Parameter Measurement .................. 270
Tn, The Effective Lifetime in the Active State ............ 270
~Effective Lifetime in Saturated State ................ 271
\..;a&,The Average Emitter Junction Capacitance ......... 272
Composite Circuit for Ta, Tb, Ca& . . . . . . . ............. 273
Qa•, Total Charge to Bring Transistor to Edge of Saturation 274
Calibration of Capacitor Con Qa• Test Set ............... 275

V
 Page
16. REGULATEDDC SUPPLYAND INVERTER
CIRCUITS .......................................... 277
Regulated DC Supply .................................. 277
Parallel Inverters ...................................... 278
DC to DC Converter .................................. 280
17. SILICON SIGNALDIODES ......................... 281
Planar Epitaxial Passivated Silicon Diode ................. 281
DC Characteristics .................................... 282
AC Characteristics ..................................... 284
Diode Assemblies ..................................... 287
18. SEMICONDUCTORRELIABILITY................... 289
Achieving Reliability .................................. 289
Design for Reliability ................................ 290
Examples of Reliable Design .......................... 292
Production for Reliability ............................. 292
Application for Reliability ............................ 294
Measuring Reliability .................................. 299
Measurement of Reliability for Applications Guidance ..... 300
Measurement of Reliability for Acceptance .............. 301
Measurement of Reliability for Control ................. 302
Past Practice, Future Trends .......................... 302
Failure Mechanisms .................................... 303
Structural Flaws .................................... 303
Encapsulation Flaws ................................. 304
Internal Contaminants ............................... 306
Material Electrical Flaws ............................. 308
Metal Diffusion ..................................... 309
Susceptibility to Radiation ............................ 309
Failure Analysis .................................... 310
Failure Distributions ................................... 310
Mathematics of Failure Distributions ................... 311
Generalized Failure Distribution ....................... 313
Acceleration Factor and Modulus of Failures ............... 315
Definitions ......................................... 316
Response Surface Relationship ........................ 317
Screening ............................................ 318
Reliability Data for Typical Transistor Types .............. 320
Explanation of Analysis and Presentation ................ 320
Reliability Data on a Germanium PNP Alloy Transistor .... 322
Reliability Data on a Silicon NPN Grown Diffused
Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
Reliability. Data on a Germanium PNP Mesa Transistor . . . 327
Reliability Data on a Silicon NPN Diffused Planar Passivated
Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
19. SILICONCONTROLLED SWITCH ................... 335
What Is It? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
What Functions can it Perform? ......................... 335
What Are Its Applications? .............................. 335
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Construction ......................................... 337
Thermal Characteristics ................................ 337
Two Transistor Analogue of PNPN ...................... 338
General Comparison with Other Semiconductors ........... 341
Comparison with Silicon Controlled Rectifier .............. 341
Comparison with Complementary SCR ................... 342
Comparison with Trigistor, Transwitch .................... 343

VI
 Page
Comparison with Four Layer Diode ...................... 343
Comparison with Unijunction Transistor .................. 344
Comparison with Binistor . . . . . . . . . . . . . . . . . . . . . . . . . ..... 344
Definition of Terms used in SCS Specifications .............. 345
Basis for Nomenclature ............................... 345
Maximum Ratings ................................... 346
Electrical Characteristics ............................. 346
Definitions ......................................... 347
Gate Characteristics ................................... 347
Ge Characteristics ................................... 347
G" Characteristics ................................... 347
Firing Characteristics ................................ 347
Tum-OH Characteristics .............................. 349
Anode to Cathode Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 349
Rate Effect-dV /dt .................................. 350
Breakover Voltage ................................... 351
Holding Current .................................... 351
Forward Voltage .................................... 351
Reverse Leakage Current ............................. 352
Blocking Leakage Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Turn-On Time ...................................... 352
Recovery Time ...................................... 353
Measurement of Electrical Characteristics .................. 355
Measurements on Tektronix 575 ....................... 355
Leakage Current Measurements ........................ 357
Dynamic Breakdown Voltage Measurements ............. 357
Tum-OH Time Measurements ......................... 358
SCS Applications ..................................... 359
Lamp Driver ....................................... 359
Basic Alarm-Voltage Sensing Circuit ................... 359
Multiple Alarm Circuit ............................... 360
Square Wave Generator .............................. 360
Sawtooth Generator .................................. 361
Pulse Amplifiers-Stretchers ........................... 361
Time Delay Generator-Pulse Actuated .................. 362
Time Delay Generator-Gate Actuated ................... 362
Time Delay Generator-AC Operated ................... 363
Schmitt Trigger ..................................... 363
Bistable Memory Element ............................ 364
Pulse Sequence Detector .............................. 364
Pulse Coincidence Detector ........................... 365
Ring Counter-Including Reset ........................ 365
Ring Counter with Independent Outputs per Stage ....... 366
Ring Counter-Loads with Common Ground ............ 366
Shift Register Configuration .......................... 367
20. EXPERIMENTERSCIRCUITS ...................... 369
21. READER'SLIST ................................... 379
Directory of Publishers ................................. 384
22. TRANSISTORSPECIFICATIONS ................... 385
Introduction .......................................... 385
GE Type Index ........................... 386
GE Transistor and Diode Selection Charts ................ 387
GE Outline Drawings .................................. 406
Registered JEDEC Transistor Types with Interchangeability
Information ........................................ 412

VII
 FOREWORD
During the past year and a half, many new processes and develop-
ments in semiconductors have been introduced. The Sixth Edition
of the General Electric Transistor Manual has been completely
rewritten and expanded by over 100 pages to include these
many improvements.
New processes and developments have been responsible for the
creation of totally new product lines. These new lines include the
General Electric Family of Silicon Planar Epitaxial Passivated
Transistors (PEP), the NPNP Silicon Controlled Switch, PEP
Controlled Conductance Diodes with ultra fast switching speeds,
and many other new transistor and diode types. These new devices,
with their unique characteristics have opened up many new areas
of applications and have ultimately produced higher reliability,
less complex circuitry and lower cost.
At the same time, General Electric has been actively engaged in a
major program to increase reliability in semiconductor devices by
several orders of magnitude. The MINUTEMAN Product Improve-
ment Program is designed to accomplish the reliability objective of
0.001 % failure rate per 1,000 hours. While this product improve-
ment program is directed specifically to the MINUTEMAN types,
process improvements developed and confirmed in this activity
are fed into other product manufacturing lines. This assures con-
stantly improved devices for circuit applications where reliability
is of utmost importance.
The addition of all these latest improvements to your Sixth Edition
General Electric Transistor Manual will assure its continued use-
fulness as your handy reference guide.

~if~ H. Brainard Fancher

General Manager
Semiconductor Products Department
Syracuse, New York

VIII
SEMICONDUCTORTHEORY

In 1833, Michael Faraday, the famed English scientist, made what is perhaps the
first significant contribution to semiconductor research. During an experiment with
silver sulphide Faraday observed that its resistance varied inversely with temperature.
This was in sharp contrast with other conductors where an increase in temperature
caused an increase in resistance and, conversely, a decrease in temperature caused a
decrease in resistance. Faraday's observation of negative temperature coefficient of
resistance, occurring as it did over 100 years before the birth of the practical transistor,
may well have been the "gleam in the eye" of the future.
For since its invention in 1948 the transistor has played a steadily increasing part
not only in the electronics industry, but in the lives of the people as well. First used in
hearing aids and portable radios, it is now used in every existing branch of electronics.
Transistors are used by the thousands in automatic telephone exchanges, digital com-
putors, industrial and military control systems, and telemetering transmitters for
satellites. A modern satellite may contain as many as 2500 transistors and 3500 diodes
as part of a complex control and signal system. In contrast, but equally as impressive,
is the two transistor "pacemaker," a tiny electronic pulser. When imbedded in the
human chest and connected to the heart the pacemaker helps the ailing heart patient
live a nearly normal life. What a wonderful device is the tiny transistor. In only a few
short years it has proved its worth - from crystal set to regulator of the human heart.
But it is said that progress moves slowly. And this is perhaps true of the first
hundred years of semiconductor research, where time intervals between pure research
and practical application were curiously long. But certainly this cannot be said of the
years that followed the invention of the transistor. For since 1948 the curve of semi-
conductor progress has been moving swiftly and steadily upward. The years to come
promise an even more spectacular rise. Not only will present frequency and power
limitations be surpassed but, in time, new knowledge of existing semiconductor mate-
rials ... new knowledge of new materials . . . improved methods of device fabrication
... the micro-miniaturization of semiconductor devices ... complete micro-circuits ...
all, will spread forth from the research and engineering laboratories to further influence
and improve our lives.
Already, such devices as the tunnel diode, the mesa transistor, and the high-speed
diode can perform with ease well into the UHF range; transistors, that only a short time
ago were limited to producing but a few milliwatts of power, can today produce thou-
sands upon thousands of milliwatts of power; special transistors and diodes such as the
unijunction transistor, the high-speed diode, and the tunnel diode can simplify and make
more economical normally complex· and expensive timing and switching circuits. Intri-
cate and sophisticated circuitry that normally would require excessive space, elaborate
cooling equipment, and expensive power supply components can today be designed
and built to operate inherently cooler within a substantially smaller space, and with
less imposing power components, by designing with semiconductors. In almost -all
areas of electronics the semiconductors have brought immense increases in efficiency
and in reliability.
In the short span of years since the advent of the transistor a variety of semi-
conductor devices have been developed. Symbols representing these devices are shown

1
SEMICONDUCTORTHEORY

in Figure 1.1. Numerous individual types are today commercially available from each
category to answer the needs of the professional electronic equipment designer, the
radio amateur, and the experimenter. It goes without saying that with time more and
newer devices will be added.

I~

NPN
TRANSISTOR
2~

4~
PNP
TRANSISTOR
Bl

NPN TETRODE
E

TRANSISTOR
(REVERSE EMITTER
::~o~sri~I
82

FIELD EFFECT
TRANSISTOR
~··
UNIJUNCTION
TRANSISTOR
Bl

7. 8. 9. 10.

$*t ~
·~ * Cf
TRANSISTOR TUNNEL BACKWARD DIODE, ZENER OR SYMMETRICAL
(REVERSE ARROWS DIODE SIGNALDIODE, BREAKDOWN ZENER
FOR PNPN DEVICE) OR RECTIFIER DIODE DIODE

'Ar '4
A -ANODE B-BASE
B -BREAKDOWN DEVICE (9 AND 10) E -EMITTER
B,-BASE ONE G - GATE
GA B2-BASE TWO GA- ANODE
C -CATHODE (7,8,9,11 AND 12 ONLY) GATE
C -COLLECTOR (1,2,3 ANO 4 ONLY I Ge-CATHODE
GATE

Ge C
SILICON
* SEE GE TUNNEL DIODE MANUAL, P 16-17
FOR ADDITIONAL SYMBOL INFORMATION SILICON
CONTROLLED CONTROLLED
SWITCH RECTIFIER

STANDARDSYMBOLSFOR SEMICONDUCTORDEVICES
Figure1.1
For the most part this chapter is concerned with the terminology and theory of
semiconductors as both pertain to diodes and junction transistors. The variety of semi-
conductor devices available preclude a complete and exhaustive treatment of theory
and characteristics for all types. Such devices as the silicon controlled rectifier and the
tunnel diode are well covered in other General Electric Manuals;* treatment of the
unijunction transistor will be found in Chapter 13 of this manual. Other pertinent
literature will be found in Chapter 21.
Although a complete understanding of the physical concepts and operational theory
of the transistor and diode are not necessary to design and construct successful tran-
sistor circuits, they can be helpful. The professional electronics engineer, the radio
amateur, and the serious experimenter can all obtain practical and rewarding benefits
from a general understanding of the basic physics and theory of semiconductors. Such
•See Reference List
2
 SEMICONDUCTOR THEORY

understanding will often aid in solving special circuit problems, will help in under-
standing and using the newer semiconductor devices as they become available, and
surely will help clarify much of the technical literature that more and more abounds
with semiconductor terminology.

SEMICONDUCTORS
Semiconductor technology is usually referred to as solid-state. This suggests, of
course, that the matter used in the fabrication of the various devices is a solid, as
opposed to liquid or gaseous matter - or even the near pedect vacuum as found in the
thermionic tube - and that conduction of electricity occurs within solid material. "But
how," it might be asked, "can electrical charges move through solid material as they
must, if electrical conduction is to take place?" With some thought the answer becomes
obvious: the so-called solid is not solid, but only partially so. In the microcosmos, the
world of the atom, there is mostly space. It is from close study of this intricate and
complicated "little world," made up mostly of space, that scientists have uncovered the
basic ingredients that make up solid state devices - the semiconductors. Transistors
and diodes, as we know them today, are made from semiconductors, so-called because
they lie between the metals and the insulators in their ability to conduct electricity.
There are many semiconductors, but none quite as popular at the present time as
germanium and silicon, both of which are hard, brittle crystals by nature. In their
natural state they are impure in contrast, for example, to the nearly pure crystalline
structure of high quality diamond. In terms of electrical resistance the relationship of
each to well known conductors and insulators is shown in Chart 1.

RESISTANCEIN OHMS PER

MATERIAL CENTIMETERCUBE CATEGORY
(R/CM3)

Silver 10-0 Conductor

Aluminum 10-5

Pure Germanium 50-60 Semiconductor

Pure Silicon 50,000-60,000

Mica 1012_101s Insulator

Polyethlene 1015_10111

Chart 1

Because of impurities the R/CM 3 for each in its natural state is much less than
an ohm, depending on the degree of impurity present. Material for use in most prac-
tical transistors requires R/CM 3 values in the neighborhood of 2 ohms/ CM•. The
ohmic value of pure germanium and silicon, as can be seen from Chart 1, is much
higher. Electrical conduction then, is quite dependent on the impurity content of the
material, and precise control of impurities is the most important requirement in the
production of transistors. Another important requirement for almost all semiconductor
devices is that single crystal material be used in their fabrication. To better appreciate
the construction of single crystals made from germanium and silicon, some attention
must be first given to the makeup of their individual atoms. Figure l.2(A) and (C)
show both as represented by Bohr models of atomic structure, so named after the
Danish physicist Neils Bohr.

3
SEMICONDUCTOR THEORY

VALENCE
BAND

VALENCE

BA(?>ND CENTRAL CORE

OR KERNEL

GERMANIUM ATOM SIMPLIFIED

(Al IBl

SILICON ATOM
=0 SIMPLIFIED
CCl IDI

BOHR MODELS OF GERMANIUM AND SILICON ATOMS

Figure1.2

Germanium is shown to possess a positively charged nucleus of +32 while the

silicon atom's nucleus possesses a positive charge of +14. In each case the total positive
charge of the nucleus is equalized by the total effective negative charge of the elec-
trons. This equalization of charges results in the atom possessing an effective charge
that is neither positive nor negative, but neutral. The electrons, traveling within their
respective orbits, possess energy since they are a definite mass in motion.* Each
electron in its relationship with its parent nucleus thus exhibits an energy value and
functions at a definite and distinct energy level. This energy level is dictated by the
electron's momentum and its physical proximity to the nucleus. The closer the electron
to the nucleus the greater the holding influence of the nucleus on the electron and the
greater the energy required for the electron to break loose and become free. Likewist..,
the further away the electron from the nucleus the less its influence on the electron.
Outer orbit electrons can therefore be said to be stronger than inner orbit electrons
because of their ability to break loose from the parent atom. For this reason they are
called valence electrons, from the Latin valere, to be strong. The weaker inner orbital
electrons and the nucleus combine to make a central core or kernel. The outer orbit in
which valence electrons exist is called the valence band or valence shell. It is the elec-
trons from this band that are dealt with in the practical discussion of transistor physics,
as it is rare for inner orbital electrons - those existing at energy levels below the
valence band - to break loose and enter into transistor action. With this in mind the
complex atoms of germanium and silicon as shown in (A) and (C) of Figure 1.2 can be
simplified to those models shown in (B) and (C) and used in further discussion.
The most important characteristic of most atoms is their valency, the ability of the
valence band electrons of one atom to bond together with the valence bands of other
atoms. This important and basic atomic action can be visualized as shown in Figure 1.3.
•Mass of electron =9.108 X 10- 18 gram.

4
 SEMICONDUCTORTHEORY

CENTRALCORE
OR KERNEL

/
-e, \
(0)
' ....__/
SHARED
ORBIT

, ...:,, ~--e-..
' , '
COVALENTOR
ELECTRON-PAIR
OF ATOMS
BOND '0Y
\ f.:i=\'
'-:!:)
I \
' ---a--"''····(}'
/
I

Figure1.3

Through orbit sharing by interchange of orbital position the electrons become

mutually related to one another and to the parent cores, binding the two atoms together
in a strong spaced locking action. A covalent bond or electron-pair bond is said to
exist. This simple concept when applied to germanium and silicon crystals will natu-
rally result in a more involved action, one the reader may find at first difficult to
visualize.
In the structure of pure germanium and pure silicon single crystals the molecules
are in an ordered array. This orderly arrangement is descriptively referred to as a
diamond lattice, since the atoms are in a lattice-like structure as found in high quality
diamond crystals. A definite and regular pattern exists among the atoms due to space
equality. For equal space to exist between all atoms in such a structure, however, the
following has been shown to be true: the greatest number of atoms that can neighbor
any single atom at equal distance and still be equadistant from one another is four.
Figure 1.4 is a two dimensional presentation of a germanium lattice structure showing
covalent bonding of atoms. (Better understanding and more clear spatial visualization
of Figure 1.4 may be had by construction of a three dimensional diamond lattice model
using the technique shown in Figure 1.5). Figure 1.4 could just as well represent a
silicon lattice since the silicon atom also contains four electrons in its outer valence
band. With all valence electrons in covalent bondage no excess electrons are free to
drift throughout the crystal as electrical charge carriers. In theory, this represents a
perfect and stable diamond lattice of single crystal structure and, ideally, would be a
perfect insulator.
But such perfect single crystals are not possible in practice. Even in highly purified
crystals, charge carriers are present to freely move about, making the crystal a poor
conductor rather than a non-conductor. At the start of the manufacturing process
modem and reliable transistors require as near perfect single crystal material as possible.
That is, crystal that exhibits an orderly arrangement of equally spaced atoms, free from
structural irregularities such as grains and grain boundaries as found in polycrystalline
structures. Polycrystals do not readily allow charge carriers to freely flow and are
impractical to reproduce with any regularity. Futhermore, surface structure varies
considerably from crystal to crystal and makes reproduction of transistors to definite
specifications difficult.

5
SEMICONDUCTOR THEORY

' I \ / \ I \/ \ I
v J X ~
/ A

'\
+4
....,,,,
;<, -
@'\
e .....
>( -
@'
e\ ->~®./_\
,,,
e ', ><-~\e '/ .... ,
x
,, ~ ..,,,,," ,, ' 'I'/ 'I ,,, '
\ I \ I \ I \ I ,/
,1 \ I \ I \ I \t
X <
/\ @'\ ©/_\ @'' @'\..
i\ J\ i,

~......
,,,,,. '

\1
@,-?-
\I
,_r
\I
..... ,,,
E) ,,,,,x,E) ,,,,,x,
-:.-<,, ,,,,,'><..,
,-
\
..... /.
E) ,,,'>--,
..... ,,,,
x,
- E) -....
- I
/,

I
/

/\ ,x ':(
1< 1\
I \,/ \ I \ I

@ @\ ©'84\ @·' @'-:\

I\

/
' ,,,,.
'>',
'
0 -' ')'~
....,
/
/
,,,.., - Q
' Q
- "'
,,"
..... ....
~
.... ....
';,< Q
,, ' Q
....,
- >,
,,
/

' Q ....
"" ',
,,

t" - l - (j" \
\\ I \ I \ / \ / \ /
/4 X X X X
' ,,,,,.I'
)(
,, ', @ @'-\
•
,,-
\/
...
;< •
-
@/\-.......,
@'\ ..X-(04....,
/
,, r
@/\
,.,<,-•-
X
/

' Q
~
.....
/
/,

'..l
\/
Q
....
,, '
~
/
/

\/
Q
.... ,,
'>~
,..... '
\1 \/ \ I \/ \/
A
,,,,,
1'\
.,, 1,
I\ /\
.,, 1,i\

TWO DIMENSIONAL
GERMANIUM
LATTICE STRUCTURE
Figure 1.4

Figure 1.5

6
 SEMICONDUCTOR THEORY

CONDUCTION
As already mentioned, to be of practical use transistors require crystal material of
greater conductivity (lower R/CM 1 ) than found in highly purified germanium and
silicon. The conductivity can be increased by either heating the crystal or by adding
other types of materials (impurities) to the crystal when it is formed.
Heating the crystal will cause vibration of the atoms which form the crystal. Occa-
sionally one of the valence electrons will acquire enough energy (ionization energy) to
break away from its parent atom and move through the crystal. When the parent atom
loses an electron it will assume a positive charge equal in magnitude to the charge of
the electron. Once an atom has lost an electron it can acquire an electron from one of
its neighboring atoms. This neighboring atom may in tum acquire an electron from one
of its neighbors. Thus it is evident that each free electron which results from the break-
ing of a covalent bond will produce an electron deficiency which can move through
the crystal as readiJy as the free electron itself. It is convenient to consider these elec-
tron deficiencies as particles which have positive charges and which are called holes.
Each time an electron is generated by breaking a covalent bond a hole is generated at
the same time. This process is known as the thermal generation of hole-electron pairs.
The average time either carrier exists as a free carrier is known as lifetime. If a hole
and a free electron collide, the electron will fill the electron deficiency which the hole
represents and both the hole and electron will cease to exist as free charge carriers.
This process is known as recombination.
Conductivity can also be increased by adding impurities to the semiconductor
crystal when it is formed. These impurities may be donors, such as arsenic which
"donates" extra free electrons to the crystal since each arsenic atom contains five elec-
trons in its valence band; or acceptors, such as aluminum which "accepts" electrons
from the crystal to produce free holes since each aluminum atom contains only three
electrons in its valence band. A donor atom, which has five valence electrons, takes
the place of a semiconductor atom in the crystal structure. Four of the five valence
electrons are used to form covalent bonds with the neighboring semiconductor atoms.
The fifth electron is easily freed from the atom and can move through the crystal.
The donor atom assumes a positive charge, but remains fixed in the crystal. A semi-
conductor which contains donor atoms is called an n-type semiconductor since con-
duction occurs by virtue of free electrons (negative charge). A two dimensional model
of n-type semiconductor is shown in Figure 1.6.
', X
\/ ', A l
I\ @I_\ @/\
@ ,,x, e ~/><..
e
' ,,, ' ,,, ........ ' ,
,'>~ ,,,x,

'..-.
\ I

,,,>-"'@+4
, 0
, - r
/',1®
' I V

/ ,,,,
, ®
'
- .... ,,, -,
W ,,Y@+4
-
OONOR ATOM\<.

, 0 - ,,,~"'
- ,,,
.....
,
I'
XI
~ .....

\ I EXCESS \ / \ /
N-TYPE SEMICONDUCTOR v'
'\ @'\ @'~\
ELECTRON \ / ' /

Figure 1.6
' ,,,
,/ @
'A..
"
,
E)-
'
-r ,
'
.>< '
/
X'
,,, ..., ,,,
/
>,
' 0
0 ,,,
,
'
'.,tI \
)I I '1
I

,
i,
' /
'
' I
X\

7
 SEMICONDUCTORTHEORY

An acceptor atom, which has three valence electrons, can also take the place of a
semiconductor atom in the crystal structure, All three of the valence electrons are used
to form covalent bonds with the neighboring atoms. The fourth electron which is
needed can be acquired from a neighboring atom, thus giving the acceptor atom a
negative charge and producing a free hole in the crystal. A semiconductor which con-
tains acceptor atoms is called a p-type semiconductor since conduction occurs by virtue
of free holes in the crystal (positive charge). A two dimensional model of p-type semi-
conductor is shown in Figure 1.7.

'\ />....,@/_\
\ I \/ \ I
X A ,'<
@1_\
@ e 'l',,x-e ..
.. ,,,,
,,,,'>(
\
\
I
I ACCEPTOR
' //

\
\ /
I
',
\
,/
I
' ,
✓><
X 1< 1,
'@'-', ,,,,'-
•..
' ....@'\...
,'
ATOM

P-TYPESEMICONDUCTOR
/
Y
8 / ' ... ,,.. '
' ,,,,"' +4-X ft; Y-+4-'<
\ ~ \ - HOLE - /
Figure 1.7 \ / , /<ELECTRON \ ,

/\ @'' @'-_\
\t \( DEFICIENCY) X

"@ 9.. ' ..><

' ' ,,,, ', ,,,, ,
.,
/
"" 9..-
,,,,

"/
/
')<'
- ?'
/
>, ...\ ,,,, ..
' I \
'v
/\ ,
>1
I

'· 'x
, '
I

To summarize, solid-state conduction takes place by means of free holes and free
electrons (carriers) in semiconductor crystals. These holes or electrons may originate
either from donor or acceptor impurities in the crystal, or from the thermal generation
of hole-electron pairs. During the manufacture of the crystal it is possible to control
conductivity, and make the crystal either n-type or p-type by adding controlled
amounts of donor or acceptor impurities. A variety of such impurities are shown in
_ _,- Chart 2. On the other hand, thermally generated hole-electron pairs cannot be con-
trolled other than by varying the temperature of the crystal.

SPACE CHARGE NEUTRALITY

One of the most important principles involved in the operation of semiconductor
devices is the principle of space charge neutrality. In simple terms, this principle states
that the total number of positive charges (holes plus donor atoms) in any region of a
semiconductor must equal the total number of negative charges (electrons plus acceptor
atoms) in the same region provided that there are no large differences in voltage within
the region. Use of this principle can frequently result in a simpler and more accurate
interpretation of the operation of semiconductor devices. For example, in explaining
the characteristics of an n-type semiconductor it is usually stated that the function of
the donor atoms is to produce free electrons in the crystal. However, using the prin-
ciple of space charge neutrality it is more accurate to say that the function of the donor
atoms is to provide positive charges within the crystal which permit an equal number
of free electrons to flow through the crystal.

8
 SEMICONDUCTOR THEORY

GROUPIN NUMBER
ELEMENT PERIODIC VALENCE APPLICATIONSIN
(SYMBOL) ELECTRONS SEMICONDUCTORDEVICES
TABLE

acceptor elements, form p-type

boron (B) semiconductors, each atom
aluminum (Al) substitutes for a Ge or Si atom
gallium (Ga) III 3 in the semiconductor crystal
indium (In) and can take on or accept an
extra electron thus producing a
hole

basic semiconductor materials,

germanium (Ge) used in crystal form with con-
IV 4
silicon (Si) trolled amounts of donor or
acceptor impurities

donor elements, form n-type

phosphorus (P) semiconductors, each atom
arsenic (As) V 5
substitutes for a Ge or Si atom
antimony (Sb) in the semiconductor crystal
and can give up or donate an
extra electron to the crystal

MATERIALSUSED IN THE CONSTRUCTIONOF TRANSISTORS

AND OTHER SEMICONDUCTORDEVICES
Chart2

DIFFUSION AND DRIFT

Carriers can move through a semiconductor by two different mechanisms: diffusion
or drift. Di6usion occurs whenever there is a difference in the concentration of the
carriers in any adjacent regions of the crystal. The carriers have a random motion
owing to the temperature of the crystal so that carriers will move in a random fashion
from one region to another. However, more carriers will move from the region of
higher concentration to the region of lower concentration than will move in the oppo-
site direction. This is shown in Figure 1.8.
Drift of carriers occurs whenever there is a difference in voltage between one
region of the semiconductor and another. The voltage difference produces a force
on the carriers causing the holes to move toward the more negative voltage and the
electrons to move toward the more positive voltage. The mechanism of drift is illus-
trated in Figure 1.9 for both n-type and p-type semiconductors. For the n-type material,
the electrons enter the semiconductor at the lower electrode, move upwards through
the semiconductor and leave through the upper electrode, passing then through the
wire to the positive terminal of the battery. Note that in accordance with the principle

9
 SEMICONDUCTOR THEORY

HIGH CONCENTRATION OF CHARGES

£
'W
DIFFUSED CHARGES

e e 0 e 0
0 e e 0 e
e e e e e
Figure1.8

of space charge neutrality, the total number of electrons in the semiconductor is deter-
mined by the total number of acceptor atoms in the crystal. For the case of the p-type
semiconductor, hole-electron pairs are generated at the upper terminal. The electrons
flow through the wire to the positive terminal of the battery and the holes move down-
ward through the semiconductor and recombine with electrons at the lower terminal.

-- @
•
ft
e +
•
fI G> DONOR ATOMS
(POSITIVECHARGE)
• +
(¼)
-
+ + e - e ACCEPTOR ATOMS
• • (NEGATIVE CHARGE)
(±) e +
• • + FREE HOLES
+
@ • e
FREE ELECTRONS

N-TYPE P-TYPE
CONDUCTION IN N-TYPE AND P-TYPE SEMICONDUCTORS
Figure1.9

10
 SEMICONDUCTOR THEORY

DIODES
H a p-type region and an n-type region are formed in the same crystal structure,
we have a device known as a diode. The boundary between the two regions is called
a ;unction, the terminal connected to the p-region is called the anode, and the ter-
minal connected to the n-region is called the cathode. A diode is shown in Figure
1.10 for two conditions of applied voltage. In Figure l.IO(A) the anode is at a negative
voltage with respect to the cathode and the diode is said to be reverse biased. The
holes in the p-region are attracted toward the anode terminal (away from the junction)
and the electrons in then-region are attracted toward the cathode terminal (away from
the junction). Consequently, no carriers can How across the junction and no current
will How through the diode. Actually a small leakage cu"ent will How because of the
few hole-electron pairs which are thermally generated in the vicinity of the junction.
Note that there is a region near the junction where there are no carriers (depletion
layer). The charges of the donor and acceptor atoms in the depletion layer generate a
voltage which is equal and opposite to the voltage which is applied between the anode
and cathode terminals. As the applied voltage is increased, a point will be reached
where the electrons crossing the junction (leakage current) can acquire enough energy
to produce additional hole-electron pairs on collision with the semiconductor atoms
(avalanche multiplication). The voltage at which this occurs is called the avalanche
voltage or breakdown voltage of the junction. If the voltage is increased above the
breakdown voltage, large currents can How through the junction and, unless limited by
the external circuitry, this current can result in destruction of the diode.

ANODE
I -+O
e + e + e + e + t1
+ P REGION ++ .. + t +
e e e e +-e +
G) @ @+-(t) tG> -
+ N REGION t- +@ -t @- -t
@ e
CATHODE
(A) REVERSE BIAS ( B) FORWARD BIAS

CONDUCTION
IN A PN JUNCTIONDIODE
Figure1.10

In Figure l.l0(B) the anode of the diode is at a positive voltage with respect to the
cathode and the rectifier is said to be forward biased. In this case, the holes in the
p-region will flow across the junction and recombine with electrons in the n-region.
Similarly, the electrons in the n-region will How across the junction and recombine
with the holes in the p-region. The net result will be a large current through the diode
for only a small applied voltage.

TRANSISTORS
An NPN transistor is formed by a thin p-region between two n-regions as shown
in Figure 1.11. The center p-region is called the base and in practical transistors is
generally less than .001 inch wide. One junction is called the emitter junction and the

11
SEMICONDUCTORTHEORY

other junction is called the collector junction. In most applications the transistor is
used in the common emitter configuration as shown in Figure 1.11 where the current
through the output or load (RL) Howsbetween the emitter and collector and the control
or input signal (VBE) is applied between the emitter and base. In the normal mode of
operation, the collector junction is reverse biased by the supply voltage Vco and the
emitter junction is forward biased by the applied base voltage VBB, As in the case of
the diode, electrons How across the forward biased emitter junction into the base
region. These electrons are said to be emitted or injected by the emitter into the base.
They diffuse through the base region and How across the collector junction and then
through the external collector circuit. Transistor action is therefore one of injection,
di/fusion, and collection.
COLLECTOR

N- TYPE COLLECTOR REGION

COLLECTOR JUNCTION
P-TYPE BASE REGION
BASE + EMITTER JUNCTION
--a-----
........ + - +-
lB +- +- + - N- TYPE EMITTER REGION

+
=_Vee (DONOR AND ACCEPTOR ATOMS
ARE NOT SHOWN)
IE f EMITTER

CONDUCTION
IN AN NPN JUNCTIONTRANSISTOR
(COMMON EMITTER CONFIGURATION)
Figure1.11
If the principle of space charge neutrality is used in the analysis of the transistor,
it is evident that the collector current is controlled by means of the positive charge
(hole concentration) in the base region. As the base voltage Vam is increased the posi-
tive charge in the base region will be increased, which in tum will permit an equivalent
increase in the number of electrons flowing between the emitter and collector across
the base region. In an ideal transistor it would only be necessary to allow base current
to How for a short time to establish the desired positive charge. The base circuit could
then be opened and the desired collector current would How indefinitely. The collector
current could be stopped by applying a negative voltage to the base and allowing the
positive charge to How out of the base region. In actual transistors, however, this can
not be done because of several basic limitations. Some of the holes in the base region
will How across the emitter junction and some will combine with the electrons in the
base region. For this reason, it is necessary to supply a current to the base to make up
for these losses. The ratio of the collector current to the base current is known as
the current gain of the transistor hrm = Io/le. For a-c signals the current gain is
= =
fJ hr. ic/ib, The ratio of the a-c collector current to a-c emitter current is desig-
nated by Cl= htb = icli •.
When a transistor is used at higher frequencies, the fundamental limitation is the

12
 SEMICONDUCTOR THEORY

time it takes for carriers to diffuse across the base region from the emitter to the col-
lector. Obviously, the time can be reduced by decreasing the width of the base region.
The frequency capabilities of the transistor are usually expressed in terms of the
alpha cuto.i frequency (fhrb). This is defined as the frequency at which ci decreases to
0.707 of its low frequency value. The alpha cutoff frequency may be related to the
base charge characteristic and the base width by the equations:
TE =~
IE
= -~
2D
= ....Q:!!!_
fhrb
where TE is the emitter time constant, QBis the base charge required for an emitter
current IE, W is the base width, and D is the diffusion constant which depends on the
semiconductor material in the base region.
The operation of the transistor has been described in terms of the common emitter
configuration. The term grounded emitter is frequently used instead of common
emitter, but both terms mean only that the emitter is common to both the input circuit
and output circuit. It is possible and often advantageous to use transistors in the
common base or common collector configuration. The different configurations are shown
in Figure 1.12 together with their comparative characteristics in class A amplifiers.

CIRCUIT CONFIGURATION CHARACTERISTICS 0

COMMON
EMITTER
(CE)
d}RL moderate input impedance
moderate output impedance
high current gain
high voltage gain
highest power gain
(1.3 K)
(5()K)
(35)
(-270)
(40 db)

lowest input impedance (350)

COMMON highest output impedance (1 M)
BASE low current gain (-0.98)
(CB) ~RL high voltage gain (380)
moderate power gain (26 db)

COMMON highest input impedance (350 K)

COLLECTOR
(CC)
(EMITTER
FOLLOWER)
dJ lowest output impedance
high current gain
unity voltage gain
lowest power gain

•Numerical values are typical for the 2N525 at audio frequencies with a bias of
(500 0)

5 volts and 1 ma., a loaa resistance of 1 OK, and a source ( generator) resistance
of lK.
(-36)
(1.00)
(15 db)

TRANSISTOR CIRCUIT CONFIGURATIONS

Figure 1.12

13
SEMICONDUCTOR THEORY

REFERENCES
Bardeen, J. and Brittain, W.H., "The Transistor, A Semiconductor Triode,'' Physics Review, Vol. 74,
No. 2, page 230, July 15, 1948.
Bragg, Sir William, "Concerning the Nature of Things,'' Dover Publications, New York, New York.
Bush, G.L., and Silvidi, A.A., "The Atom - A Simplified Description,'' Barns & Noble, Inc., New
York, New York.
•"Controlled Rectifier Manual," General Electric Company, Rectifier Components Department,
Auburn, New York ( 1961 ).
Pearson, G.L. and Brittain, W.H., "History of Semiconductor Research,'' Proc. IRE, Vol. 43,
pp. 1794-1806 (December 1955).
Shoclcley, W., "Transistor Electronics: lmpe1fedions, Unipolar and Analog Transistors,'' Proc. IRE,
Vol. 40, pp. 1289-1313 (November 1952).
•"Tunnel Diode Manual,'' General Electric Company, Semiconductor Products Department, Liver-
pool, New York ( 1961 ).

14
TRANSISTORCONSTRUCTION
TECHNIQUES

The knowledge of many sciences is required to build transistors. Physicists use the
mathematics of atomic physics for design. Metallurgists study semiconductor alloys and
crystal characteristics to provide data for the physicist. Chemists contribute in every
facet of manufacturing through chemical reactions which etch, clean and stabilize
transistor surfaces. Mechanical engineers design intricate machines for precise handling
of microminiature parts. Electronic engineers test transistors and develop new uses for
them. Statisticians design meaningful life test procedures to determine reliability. Their
interpretation of life test and quality control data leads to better manufacturing
procedures.
The concerted effort of this sort of group has resulted in many different construc-
tion techniques. All these techniques attempt to accomplish the same goal - namely to
construct two parallel junctions as close together as possible. Therefore, these tech-
niques have in common the fundamental problems of growing suitable crystals, form-
ing junctions in them, attaching leads to the structure and encapsulating the resulting
transistor. The remainder of this chapter discusses these problems.

METAL PREPARATION
Depending on the type of semiconductor device being made, the structure of the
semiconductor material varies from nearly perfect single crystal to polycrystalline. The
theory of transistors and rectifiers, however, is based on the properties of single crystals.
Defects in a single crystal produce generally undesirable effects.
Germanium and silicon metal for use in transistor manufacture IJlUStbe so purified
that the impurity concentration is less than one part in 10'0 • Donor and acceptors are
then added in the desired amounts and the material is then grown into a single crystal.

DIRECTION OF TRAVEL
__, ____ OF INDUCTION COIL AND
MOLTEN ZONE

0 GRAPHITE BOAT @ QUARTZ TUBE

@ BAR OF HIGH PURITY @ MOLTEN ZONE

SOLID GERMANIUM
{!) BAR OF LOW PURITY
@ INERT ATMOSPHERE SOLID GERMANIUM
© INDUCTION COIL

SIMPLIFIED ZONE REFINING APPARATUS

Figure 2.1

15
TRANSISTORCONSTRUCTIONTECHNIQUES

The initial purification of germanium and silicon typically involves reactions which
produce the chemical compounds germanium and silicon tetrachloride or dioxide.
These compounds can be processed to give metallic germanium or silicon of relatively
high purity. The metal so prepared is further purified by a process called zone refining.
This technique makes use of the fact that many impurities are more soluble when the
metal is in its liquid state, thus enabling purification to result by progressive solidifica-
tion from one end of a bar of metal.
In practical zone refining a narrow molten zone is caused to traverse the length of
a bar. A cross-sectional view of a simplified zone refining furnace is shown in Figure
2.1. High purity metal freezes out of the molten zone as the impurities remain in
solution. By repeating the process a number of times, the required purity level can be
reached. During the process it is important that the metal be protected from the intro-
duction of impurities. This is done by using graphite or quartz parts to hold the metal,
and by maintaining an inert atmosphere or vacuum around it. The heating necessary to
produce a narrow molten zone is generally accomplished by induction heating, i.e., by
coils carrying radio frequency energy and encircling the metal bar in which they
generate heat.
The purified metal is now ready for doping and growing into a single crystal.
A common method for growing single crystals is the Czochralski method illustrated in
Figure 2.2. In it a crucible maintains molten metal a few degrees above its melting
point. A small piece of single crystal called a seed is lowered into the molten metal and
then slowly withdrawn. If the temperature conditions are properly maintained a single
crystal of the same orientation, i.e., molecular pattern as the seed grows on it until aJl
the metal is grown into the crystal. Doping materials can be added to the molten metal
in the crucible to produce appropriate doping. The rate at which doping impurities are
transferred from the molten metal to the crystal can be varied by the crystal growing
rate, making it possible to grow transistor structures directly into the single crystal.
This is discussed in detail in the next section.
The floating zone technique for both refining and growing single crystals has
recently been introduced. It is quite similar in principle to zone refining except that
the graphite container for the bar is· eliminated, reducing the risk of contamination.
In place of it, clamps at both ends hold the bar in a vertical position in the quartz
tube. The metal in the molten zone is held in place by surface tension. Doping agents
added at one end of the bar can be uniformly distributed through the crystal by a
single cycle of zone refining. This technique has had much success in producing high
quality silicon metal.

JUNCTIONFORMATION
A junction is a surface separating two regions of a semiconductor, one with n type
and the other with p type conductivity. Since transistors consist of two closely spaced
junctions, it is necessary to establish highly non-uniform distributions of n and p type
impurities in the semiconductor lattice. The techniques used for establishing these
impurity distributions provide the basis for the different types of transistors being
made today.
Three basic techniques are used, individually or in combination, in establishing
the desired impurity distribution. The first of these is to form an alloy of the semi-
conductor and a material which acts as either a donor or acceptor in the semiconductor
lattice. The most common materials used for this purpose are indium, which is used
for making the emitter and collector regions of germanium alloy transistors such as the
2N43A and the 2N396, and aluminum, which is used for making the emitter region of

16
 TRANSISTOR CONSTRUCTION TECHNIQUES

~DD
SEED HOLDER

SEED

GRAPHITECRUCIBLE

HEATER

••
•
••• -=========-=--
•
•••••••o••••

SIMPLIFIED CRYSTAL GROWING FURNACE

Figure 2.2

17
TRANSISTORCONSTRUCTIONTECHNIQUES

germanium mesa transistors such as the 2N705 and 2N711. In these cases, an alloy
is formed with the metal and some of then type germanium. Upon freezing, a p type
semiconductor layer is deposited creating a pn junction.
A second method is to change the impurity concentration in the crystal as it is being
grown from the liquid state. Ordinarily, crystals are grown so as to produce some
constant level of impurity throughout. Because of a tendency for most impurities to
remain in the melt rather than deposit in the solid, which is also the basis of zone
refining, the concentration does not remain uniform as the crystal is grown, but in-
creases continuously due to the increasing impurity concentration in the melt. The
concentration of impurities deposited in the solid is affected by the rate at which the
crystal is grown, in the case of some impurities. By a proper selection of impurities
and the inclusion of both p and n type impurities in the melt, pn junctions can be
grown into the crystal by periodically changing the growth rate.
Diffusion is a third method of impurity control. It consists of a gradual movement
of impurity atoms through the semiconductor lattice while the semiconductor remains
a solid. Because this movement is a function of the thermal energy of the impurity
atoms, the rate of movement is temperature sensitive and appreciable movement takes
place at high temperatures. Temperatures used in diffusion range from 500°C to 800°C
for germanium and from 900°C to 1300°C for silicon.

INDIUM

~
MOLTENALLOY
\.

'
N·TYPE GERMANIUMI HEAT
REMOVED

FORMATION BY ALLOYING

SEED
N-TYPE N
GERMANIUM p

\~/
HEAT
\l/
HEAT
APPLIED APPLIED

JUNCTIONFORMATIONBY RATEGROWING

P-TYPE GERMANIUM P-TYPE

.:: :,;,-.,/:~~ ;,, ;:c;
ANTIMONYGAS...__A•·:-:-:-:-;\r·:,~-=1\:F
-::X::::F !t~;_;';";;;t;S-w
.'..:
':::,.,
~-:t:1y.·? ··.:.·,··~i/•"
. -~/i(JIV -~
"\.~ i1,/ •'•
HEAT HEAT
·.:.~sv--•: HEAT

JUNCTION FORMATIONBY DIFFUSION

JUNCTIONFORMATIONS
Figure2.3

18
 TRANSISTOR CONSTRUCTION TECHNIQUES

One diffusion technique is to place the semiconductor in a gas containing the

desired impurity and heating. A variation of this is to coat the surface with a chemical
containing the desired impurity and heating. In both cases, the impurity enters into
the semiconductor from the outside. In another case, the desired diffusion takes place
entirely within the semiconductor body which is grown with abrupt changes in the
impurity concentration. In each of the above cases, diffusion takes place from the
region of the high impurity concentration to the region of low concentration.
Diffusion generally involves times of several hours, rather than seconds as in the
case of rate growing techniques. This makes it easier to obtain good process control.
In addition, diffusion makes it possible to vary the impurity concentration over a wide
range. This is in sharp contrast to both rate growing and alloying, and together with
its good process control makes diffusion a highly attractive technique for the manu-
facture of transistors.

ALLOY TRANSISTORS
The alloy transistor is made by alloying metal into opposite sides of a thin piece
of semiconductor to form an emitter and collector region. In order to achieve uniformity
of the transistor characteristics, the pellet thickness, the quantity of metal to be alloyed,
the area of contact of the metal to the semiconductor and the alloying temperature
must be carefully controlled. Each of these variables affects the base width of the
transistor, which in turn affects most electrical characteristics. Because of the large
number of variables, thin base widths cannot be achieved consistently; therefore, a
practical lower limit exists for the base width and with it an upper limit on the oper-
ating frequency is also established. One measure of the maximum operating frequency
is fhrb; this is the frequency at which the current gain of the transistor is 3 db below
its low frequency value, commonly referred to as the alpha cutoff frequency. Typical
values of fhrbfor alloy transistors range from 1 me for the 2N43 to 8 me for the 2N396.
On the other hand, the emitter and collector regions of an alloy transistor are quite
thin and have a high electrical conductivity. Because of this alloy transistors have a
very low saturation resistance. The saturation resistance is a measure of how nearly
the transistor can be made to appear as a short circuit when it is turned on in switch-
ing circuits, and in most transistors it is made up primarily of the parasitic resistance
of the emitter and collector bodies. A typical value for the 2N396 is 1.6 ohms at 50 ma.
The microalloy transistor is a variation of the alloy transistor. In order to achieve
a thin base width without making the transistor unduly fragile, electrochemical etching
techniques are used to provide a very thin region in the middle of an otherwise rela-
tively thick pellet. Metal is then deposited on each side of this thin region and alloyed
with a very small amount of germanium. Electrically, the characteristics are those of
an alloy transistor with a thin base. Mechanically, the transistor is less fragile than it
would be if the entire pellet were the same thickness as the base region.
A variation of the microalloy transistor is the microalloy diffused transistor. In this
case, a diffused layer is established over the entire pellet surface prior to etching the
thin region in the middle of the pellet. The etching is then done predominantly on
one side so as to remove the diffused layer from the region of the collector contact.
The other side of the pellet is etched only slightly so that the emitter is adjacent to
the diffused region. Both the microalloy and microalloy diffused transistors represent
improvements in frequency response over conventional alloy transistors. Typical of
these processes are the microalloy 2N393 with fhrbof 40 me and the microalloy diffused
transistor 2N502 with f11rb of 200 me.

19
TRANSISTOR CONSTRUCTION TECHNIQUES

p-TYPE
P-TYPE COLLECTOR
EMITTER REGION
REGION

INDIUM-
GERMANIUM
ALLOY

n - TYPE
GERMANIUM

GERMANIUM PNP ALLOY TRANSISTOR

Figure2.4

GROWNJUNCTIONTRANSISTORS
Grown junction transistors diJfer from alloy transistors in that the junctions are
created during the growth of the crystal rather than by alloying after the crystal is
grown. This results in significant differences in geometry and electrical characteristics.
One technique of growing junctions into the crystal is to vary the rate of growth and
utilize the variation of segregation coefficient with growth rate. In germanium, a very
slow growth speed is used to produce p regions while rapid growth is used to produce
n regions, thus creating a series of n and p regions; thirty or more pairs of junctions
can be produced in a single crystal in this manner. While both npn and pnp transistors
can be produced by rate growing, the npn structures are inherently more attractive
and rate growing is not used for making pnp transistors. (In silicon, rate growing is not
used because it does not produce transistors competitive with those produced from
grown diffused crystals. Grown diffused transistors are discussed on the next page.)
After the crystal is grown each pair of junctions is sawed from the wafer and diced
into several hundred individual pellets. Each pellet is thus an npn transistor, requiring
only leads and proper mounting. ( See Figure 2.5.)
n

RATE GROWN PELLET

Figure2.5

20
 TRANSISTORCONSTRUCTIONTECHNIQUES

The geometry of this device is such that mechanical strength is not a function of
the base width. It is simple to produce a base width as small as desired, but it is
difficult to control this consistently, as thermal conditions are not uniform throughout
the crystal during growth. Furthermore, it is difficult to achieve a high concentration of
p type impurities in the base region. For these reasons, rate grown transistors have a
lower limit on the base width, and, therefore, a limited frequency range. The 2N78
and 2N167 are typical rate grown transistors, both of which have an fbtb of 9 me.
It is necessary to make a contact to the base region of this transistor without signifi-
cantly altering the original structure. Any portion of the base lead which overlaps the
collector or emitter regions reduces the breakdown voltage and adds capacitance to
these junctions.
Another transistor with similar geometry is the grown diffused transistor. This tran-
sistor utilizes a combination of impurity segregation during growth and diffusion.
The segregation and diffusion coefficients are such that npn silicon and pnp germanium
transistors are produced by this process. In the case of silicon, a lightly doped n type
crystal is dipped into molten silicon containing n and p type impurities. A highly
conducting n type region is grown which also contains a considerable quantity of p type
impurities. After a short time at elevated temperatures these p type impurities diffuse
from the newly grown layer into the lightly doped n type material, thus creating a p
type base region between a heavily doped n type emitter region and a lightly doped n
type collector region. This technique provides better control of the base width and a
higher concentration of impurities in the base than can be achieved by rate growing.
Such transistors will therefore operate at higher frequencies even though the base
lead overlap still limits the performance. The 2N338 is a typical grown diffused tran-
sistor with an f htb of 20 me.
All grown junction transistors are mounted and supported by contacts to their
emitter and collector regions. Various methods have been used; the most reliable is
the use of a ceramic disc which has metallized regions to which the emitter and
collector regions are alloyed. This is known as fixed-bedconstruction. The rigid disc
prevents stresses in the semiconductor material which arise from vibration of the
header leads.

GERMANIUM MESA TRANSISTORS

The limitations characteristic of alloy and grown junction transistors can be over-
come by use of mesa construction, shown in Figure 2.6 below.
ALUMINUMSTRIP[
I EMITTER
AND
EMITTERCONTACT)

GOLOSTRIPE
IBASE
CONTACT)

P-TYPE
----- PELLET I
I COLLECTOR

GERMANIUM MESA PELLET

Figure2.6

21
TRANSISTOR CONST~UCTION TECHNIQUES

The mechanical reliability is not affected by the thickness of the base region because
it is diffused into the pellet from the surface. The use of diffusion results in excellent
control of the base width. In addition, resistivity of the base and collector regions can
be varied at will over a wide range to obtain optimum device characteristics.
The metal stripes are evaporated onto the surface of the diffused pellet. One stripe
is gold which provides a non-rectifying contact to the base region; the other stripe is
aluminum which forms a rectifying contact and thus serves as an emitter. Most of the
diffused layer outside the stripes is removed by etching so as to reduce the collector
junction capacitance and give better collector diode characteristics. The fabrication is
completed by mounting the pellet onto a header and bonding small gold wires to the
metal stripes. The thermal impedance between the junctions and the header is low
since the pellet is mounted directly on the header. High speed switching transistors
with an excellent reliability record have been made with this process.
The conventional mesa transistor utilizes a collector resistivity which is a com-
promise between a high resistivity for a high BVcuo and low capacitance on one hand,
and a low resistivity for a low saturation voltage on the other hand. The need for
compromise can be largely eliminated by using a combination of high and low resis-
tivity material in a single pellet. This is achieved by growing a high resistivity film
onto a low resistivity pellet.
Such films are called epitaxial films because the atoms are aligned in a continuation
of the original crystalline structure, resulting in one single crystal pellet. The base
region is then diffused into the thin film and the rest of the fabrication is the same as
for the conventional mesa. Epitaxial transistors represent a substantial improvement
over the conventional mesas in that a higher BVcuo, lower capacitance, and lower
saturation voltage can be achieved simultaneously. These improved characteristics in
tum permit higher switching speeds and operation at higher current levels. The 2N994
is an epitaxial transistor which is similar to the non-epitaxial 2N705. Cobis 30% smaller,
however, and VcE<SAT>is 50% smaller. In addition, the 2N994 provides a 400% in-
crease in current handling capability together with a 50% reduction in switching time.

SILICON PLANAR TRANSISTORS

This transistor is made by diffusing the emitter as well as the base. A diffused
emitter is desirable because of the same control and ability to select the desired im-
purity level that makes a diffused base desirable. In addition, no mesa forming etch
is used. These differences result from the fact that silicon dioxide can be formed on the
surf ace of silicon pellets to act as a mask to prevent the diffusion of impurities into the
silicon. The base and emitter regions are formed by selectivity removing portions of
the silicon dioxide to permit diffusion into the silicon. The two regions are formed
sequentially; oxidation and selective removal of the oxide take place prior to each
diffusion. Aluminum is deposited on both the base and emitter regions to provide low
resistance, mechanically reliable contacts.
The oxide covers the junctions of the completed transistors, thereby preventing
ambient gases from reaching the junction. This results in a passivated device with
excellent electrical stability.
This protective oxide can also be formed on epitaxial films. The resulting improve-
ments in BV cuo, Cob, V c1::<sAT>and current handling capability are similar to those
achieved with germanium epitaxial transistors.

22
 TRANSISTOR CONSTRUCTION TECHNIQUES

BASE
ALUMINUM
EMITTER CONTACT
ALUMINUM DIFFUSED DIFFUSED
CONTACT EMITTER BASE

BASE
ALUMINUM
CONTACT

S 10 2 COVERING
COLLECTOR-BASE
JUNCTION

n-TYPE SILICON
(COLLECTOR)

SILICON PLANARPELLET
Figure2.7

ENCAPSULATION
The term encapsulation is used here to describe the processing from the completion
of the transistor structure to the final sealed unit. The primary purpose of encapsulation
is to ensure reliability. This is accomplished by protecting the transistor from mechani-
cal damage and providing a seal against harmful impurities. Encapsulation also governs
thermal ratings and the stability of electrical characteristics.
The transistor structure is prepared for encapsulation by etching to dissolve the
surface metal which may have acquired impurities during manufacture. Following
etching, a controlled atmosphere prevents subsequent surface contamination. The
transistor now is raised to a high temperature, is evacuated to eliminate moisture and
is refilled with a controlled atmosphere. Then the cap, into which a getter may be
placed, is welded on.
In some respects the design of the case, through its contribution to transistor reli-
ability, is as important as that of the transistor structure. Mechanically, users expect to
drop transistors, snap them into clips or bend their leads without any damage. Ther-

23
TRANSISTORCONSTRUCTIONTECHNIQUES

mally, users expect the header lead seals to withstand the thermal shock of soldering,
the junctions to be unaffected by heating during soldering, and the internal contacts to
be unchanged by thermal cycling. Considerable design skill and manufacturing cost is
necessary to meet the users expectations. Within the transistor structure, coefficients of
expansion are matched to prevent strain during thermal cycling. Kovar lead seals with-
stand the shock of soldering and do not fatigue and lose their effectiveness after thermal
cycling. Hard solders and welds maintain constant thermal impedance with time, avoid-
ing possible crystallization of soft solders.
For the stability of electrical characteristics, hermetic seals cannot be over-
emphasized. They not only preserve the carefully controlled environment in which the
transistor is sealed but they exclude moisture which causes instability. Moisture can
be responsible for slow reversible drifts in electrical characteristics as operating con-
ditions are changed. Also, while a transistor is warming up after exposure to low tem-
peratures, precipitated moisture may cause a large temporary increase in Ico. Kovar
glass lead seals are used in transistors designed for reliability. Kovar does not have the
low thermal impedance or ductility of copper, however, and therefore seal integrity is
paid for by a lower dissipation rating and a lower tolerance to lead bending.
The case design governs the transistor's thermal impedance, which should be as
low as possible and consistent from unit to unit. Very small cases minimize the junction
to case impedance while increasing the case to air impedance. Larger cases such as
the JED EC 370 mil TO-9 combine a lower case to air impedance, with a lead configura-
tion and indexing tab permitting automatic insertion of transistors into printed circuit
boards.

RELIABILITY
In principal, transistors have no known failure mechanism which should limit their
life expectancy. However, in practice, failure mechanisms do exist. To date sufficient
data has been collected to show that with careful construction techniques, transistors
are capable of operation in excess of 40,000 hours at maximum ratings without appre-
ciable degradation. There is no reason to believe this is the limit of operating life.
Since transistors can perform logical operations at very low dissipation and amplify at
high efficiency, the resulting low dissipation reduces the ambient temperature for
other components, enhancing their reliability as well. The transistor's small physical
size and its sensitivity to small voltage changes at the base results in low circuit capaci-
tances and low power requirements, permitting large safety factors in design. The
variety of manufacturing processes being used by the industry permits choosing the
optimum transistor for any circuit requirement. For example, rate grown transistors
offer low loo and low Cc for applications requiring low collector current. Alloy tran-
sistors offer high peak power capabilities, great versatility in application, and are
available in both PNP and NPN types. Mesa and planar epitaxial transistors give high
speed at high voltage ratings and with good saturation characteristics.
While reliability must be built in, it has seldom proved practical in the past to
make an absolute measurement of a specific transistor's reliability. Transistors cur-
rently are sufficiently reliable that huge samples and considerable expense in man-
power, equipment, and inventory are necessary to get a true measure of their reliability.
However, tests can readily show if a transistor falls far short of the required reliability;
therefore, they are useful in assigning ratings, in obtaining rate of degradation meas-
urements, and as a measure of quality control or process variability. Figures 2.8, 2.9,
2.10 and 2.11 show some of the considerations in designing reliable transistors.

24
 TRANSISTOR CONSTRUCTION TECHNIQUES

(D KOVAR METAL FOR BEST HERMETIC SEAL

@ RIDGE ASSURES BETTER PRECISION IN WELDING
@ COPPER CLAD STEEL FOR STRAIN FREE FABRICATIONi
SALT SPRAYRESISTANCE AND MECHANICAL STREN\JTH
@ WELDED CONTACTS BETWEEN COLLECTOR AND
EMITTER TABS,AND HEADER LEADS
@ SPECIAL ALLOYS ANO PROCESSING TO PREVENT POOR
WETTING AND CONSEQUENT INTERMITTENT CONTACT
@ SPECIAL ALLOYS BETWEEN WAFER AND SUPPORTING
WINDOW TO CONTROL STRESSES DUE TO THERMAL
EXPANSION, TO GET GOOD WETTING BETWEEN WINDOW
AND WAFER REDUCING THERMAL IMPEDANCE AND
SERIES BASE RESISTANCE, TO GET PURELY OHMIC CONTACT
(z) CRYSTAL ORIENTATION CHOSEN TO PREVENT DOT SPREADING
@ COLLECTOR DOT CENTERED EXACTLY OPPOSITE EMITTER
DOT FOR HIGH CURRENT GAIN
@ THICK WINDOW TO MINIMIZE THERMAL IMPEDANCE TO CASE
@ TWO LARGE WELDS PROVIDE HEAT PATH FROM WINDOW TO CASE
@ SHOULDER ON SEAL FOR STRENGTH
@ KOVARTO HARD GLASS MATCHEDCOEFFICIENT SEAL
@ KOVARLEADS HELP REDUCE JUNCTION HEATING DURING SOLDERING
@ GASEOUS ATMOSPHEREAVOIDS THE MIGRATION OF IONS
POSSIBLE WITH FLUID TYPE FILLERS
~ GETTER TABLET TOPERMANENTLY ABSORBANY MOISTURE
DUE TO OUTGASSING
~ SPECIAL ETCHING ANO SURFACETREATMENT RESULTS IN STABLE
Ico AT ALL TEMPERATURES, VERY LOW NOISE FIGURE, ANO
SMALL Ico VARIATION WITH COLLECTOR VOLTAGE.

ALLOY TRANSISTOR
DESIGN FOR RELIABILITY
(TYPES 2N43, 2N396, 2N525)
Figure 2.8

25
TRANSISTOR CONSTRUCTION TECHNIQUES

© KOVAR METAL HEADER FOR BEST HERMETIC SEAL

@ RAISED GLASS BEAD TO PREVENT POSSIBLE
OCCLUSIONOF CONTAMINANTS
@ CERAMIC DISK WITH COEFFICIENTOF THERMAL
EXPANSIONMATCHING THAT OF SILICON

@ GOLD STRIPS BONDEDTO CERAMIC BY TECHNIQUES

PERFECTEDFOR CERAMIC TUBE
@ SLIT IN DISKCUT TO ± 0.001 a TOLERANCE

@ BASE REGIONPLACED CLOSE TO COLLECTORCONTACT

FOR LOW THERMAL IMPEDANCEANO LOW SATURATION
RESISTANCE
(!) HARDSOLDERPREVENTS THERMAL FATIQUEPROBLEMS
@ SPECIAL NON-POROUSCERAMICIS IMPERVIOUSTO
PROCESSINGCHEMICALS
@ DISK DIAMETERSMALL ENOUGHTO PREVENT ANY
CONTACTWITH CASE

(@)BASE LEAD ATTACHED TO GOLD STRIP

GROWN DIFFUSED TRANSISTOR-

FIXED BED MOUNTING DESIGN FOR RELIABILITY
(TYPES 2N335, 2N337, 2N491)
Figure 2.9

26
 TRANSISTOR CONSTRUCTION TECHNIQUES

(]) KOVAR METAL HEADERFORBEST HERMETICSEAL

~ DIRECTMOUNTING OF PELLET TO HEADERASSURESBEST
MECHANICALANDTHERMALCHARACTERISTICS
(3) THERMOCOMPRESSIONBONDEDLEADSASSUREHIGHEST
RELIABILITY
@ GETTERTO ASSUEDRYAMBIENT
® ASSEMBLYTO ASSUREMECHANICALSTABILITYOF
GETTER
@ GAS FILLED INTERIORFOR MAXIMUMELECTRICAL
STABILITY

GERMANIUM MESA TRANSISTOR

DESIGN FOR RELIABILITY
(TYPES 2N705, 2N781, 2N994)
Figure 2.10

(DKOVAR METAL HEADER FOR BEST HERMETIC SEAL

@DIRECT MOUNTING OF PELLET TO HEADER ASSURES
BEST MECHANICAL AND THERMAL CHARACTERISTICS
@THERMOCOMPRESSION BONDED LEADS ASSURE
HIGHEST RELIABILITY

SILICON PLANAR PASSIVATEDTRANSISTOR

DESIGN FOR RELIABILITY
(TYPICAL TYPES 2N914, 2N2192)
Figure 2.11
absolute maximum ratings (25°C unless othl'rwise spet'ified)
011o1£NSIONS
WITHIN
2H2193 2N2194 2N2195 JEOEC
DUTLllffi
2N2193A 2N2194A 2N2195A TO•II
Voltase
Collector to Base Veno 80 60 45 volts
Collector to Emitter VC110 50 40 25 volts
Emitter to Base Vno 8 5 5 volts
Current
Collector le 1.0 1.0 1.0 amp
Transistor Dissipation
(Free Air 25"C) • 0.8 0.8 watts
(Free Air 25"C) •• 0.6 watts
(Case Temperature 25"C) 0 • 2.8 2.8 2.8 watts
(Case Temperature l00"C) • 0 1.6 1.6 1.6 watts
Temperature
Storage TSTO +- -65 to +300 ___. ·c
Operating Junction T1 +- -65 to +200 ..... ·c
•Derate 4.6 mw/"C increase in ambient temperature above 25°C
••Derate 3.4 mw/"C increase in ambient temperature above 25"C
•••Derate 16.0 mw/"C increase in case temperature above 25°C
electrical characteristics: (25C 0
unlcss oth<irwbc spccifhid)
2N2193
2N2193A
2N2t94
2N2194A
2N219S
2N2195A
00
~
n
s
1-C
~

~
~z
DC CHARACTERISTICS Min. Max. Min. Max. Min. Max.
I>- Colloctor to Baso Volto90 Uc= 100 p.a) Vcuo 80 60 46 volts
• Colloctor to Ernlttor Voltago Uc = 26 ma) t
Emlttor to Boso Voltage (I 11= 100 µa)
Vcco
V111110
60
8
40
6
26
6
volts
volts
)-o,4
n
~
Forward Current Tran1for Ratio
(le= 160ma, Ve • = 10 V)t hr• 40 120 20 60 20
(le= lOma, Ve• = 10 V) hi'& 30 16 00
(le= lOOOma, Vcu = 10 V)t hn 16 )-o,4 ,-..,c
Uc= 0.1 ma, Vea= 10 V) hn 16
0 00
(le=
(le=
600ma, Vcs = 10 V)t
lOma, Vea= lOV, TA= -66°C)
Baso Saturation Volto90 Uc= 160 ma, Ia = 15 ma)
hn
bra
Va • 1a•T>
20
20
1.8
12
1.3 1.3 volts
z~
• Calloctor Saturation Valta90 (le= 160 ma, Ia= 16 ma)

CUTOFF CHARACTERISTICS
Vc • ,a1.T1
Vc• cuT1
VcmcuT>
(0.36 volts max., 2N2193, 94, 96 only)
(0.25 volts max., 2N2193A, 94A, 96A only)
(0.16 volts typ., 2N2193A, 94A, 95A only)
00

~~
=
• Collector Loalca90 Current !Von= SOV)
Von= 30 V, T. = 150°C)
~Von= 60V)
loao
lono
lono 10
10
26
100
50
mp.a
p.a
mp.a ...,
Von= 60 V, T. = 150°C) lcno 25 p.a
Ernitkr Base Cutoff Current (Vaa = 5 V~ lno 60 mp.a
• Emitkr Base Loalcage Current (Vu=

HIGH FREQUENCY
3 )
CHARACTERISTICS
lno 50 100 mp.a

Current Tranafor Ratio (le= 60 ma, V ca = 10 V, f = 20 me) bro 2.5 2.6 2.6
Colloctor Capacltonce (la= O,Von= 10 V, f = 1 me) c•• 20 20 20 pf
SWITCHING CHARACTERISTICS (See Figure 1)
IV,~== 15V, V,. = 15Vl
Rise Time t. 70 70 nsec
Storage Time t. 150 160 nsec
Fall Tlmo tt 50 50 nsec
tPulse width ~300 "sec, duty cycle ~2%

CHAPTER
GENERAL@ELECTRIC

~
THE TRANSISTOR SPECIFICATION SHEET

The published transistor specification sheet is fully as important as the device it

describes since it provides the description necessary for sensible use of the subject
transistor.
Four general categories of information are presented. These are
1. a statement of broad device capabilities and intended service
2. absolute maximum ratings
3. electrical characteristics
4. generic or family electrical characteristics
Let's study each of these categories in some detail and use the specification sheet for
2N2193 through 2N2195 as a guide.

1. GENERALDEVICE CAPABILITIES
The lead paragraph found at the top of the sheet furnishes the user with a concise
statement of the most likely applications and salient electrical characteristics of the
device. It is useful in first comparison of devices as one selects the proper device for a
particular application.

2. ABSOLUTEMAXIMUM RATINGS
Absolute maximum' ratings specify those electrical, mechanical, and thermal ratings
of a semiconductor device which, as limiting values, define the maximum stresses
beyond which either initial performance or service life is impaired.
VOLTAGE
The voltages specified in the Absolute Maximum Ratings portion of the sheet are
breakdown voltages with reverse voltage applied to one selected junction, or across
two junctions with one junction reverse biased and the second junction in some speci-
fied state of bias. Single junction breakdown either between collector and base or
between emitter and base has the form shown in Figure 3.1.
CURRENT

FORWARD
CURRENT

P-N JUNCTION
FORWARD BIASED

BREAKDOWN
VOLTAGE
VOLTAGE

I
I
I
,... AVALANCHE
I CURRENT

: P-N JUNCTION
I REVERSEBIASED
I
I

TYPICALVOLTAGECURRENT
CHARACTERISTICSOF A P-N JUNCTION
Figure 3.1

30
 THE TRANSISTOR SPECIFICATION SHEET

The solid portion of the curve is the active, normally used portion of a diode or
any compound junction device. The dotted portion exhibits large dramatic changes in
reverse current for small changes in applied voltage. This region of abrupt change is
called the breakdown region. If breakdown occurs at relatively low voltage, the mecha-
nism is through tunneling or "zener" breakdown. The means of conduction is through
electrons which have ..tunneled" from valence to conduction energy levels. A more
complete explanation of tunneling is contained in the Tunnel Diode Manual.•
At higher voltage levels conduction is initiated and supported by solid ionization.
When the junction is reverse biased, minority current flow (leakage current) is made
up of holes from the N-type material and electrons from the P-type material. The
high field gradient supplies carriers with sufficient energy to dislodge other valence
electrons, raising their energy level to the conduction band resulting in a chain genera-
tion of hole-electron pairs. This process is called avalanche. While theory predicts an
abrupt, sharp (sometimes called hard) characteristic in the breakdown region, a soft or
gradual breakdown often occurs. Another possibility is the existence of a negative
resistance ..hook." The hook usually occurs when zener breakdown is the predominant
mechanism. Figure 3.2 graphically illustrates these possibilities. In practice, silicon,
because of lower leakage current, exhibits a sharper knee than does germanium.

VOLTAGE

--.::.---
,.... \ ~/ ..,1--- RESISTIVE
LEAKAGECURRENT
..,""" COMPONENT
NEGATIVE
RESISTANCE SOFT KNEE
P-N JUNCTION
REVERSE BIASED
CURRENT
AVALANCHE
CURRENT

TYPICALVARIATIONS
IN BREAKDOWN
CHARACTERISTIC
OF A P-N JUNCTION
Figure3.2
The family of the 2N2193 to 2N2195 silicon devices are measured for individual
junction breakdown voltages at a current of 100 microamperes. Vcno, the collector-base
diode breakdown voltage- with emitter open circuited or floating - is shown to be a
minimum of 80 volts for the 2N2193 and 2N2193A.
VEno,the emitter-base breakdown voltage - with collector open circuited or floating
- is specified at 8 volts minimum for the 2N2193 and 2N2193A.
The breakdown voltage between collector and emitter is a more complex process.
The collector-base junction in any configuration involving breakdown is always reverse
biased. On the other hand, the condition applied to the emitter-base diode depends
upon the nature of base lead connection. The most stringent requirement is realized
by allowing the base to float. The next most stringent requirement is connecting the
•see references at end of Chapter I.

31
THE TRANSISTOR SPECIFICATION SHEET

base to the emitter through a resistor. A more lenient measurement is with base and
emitter shorted. Finally, the condition yielding the highest breakdown voltage is that
which applies reverse bias to the emitter-base junction. The symbols for the breakdown
voltage, collector to emitter, under the foregoing base connection conditions are VcEo,
VcEn, VcEs, and VcEx respectively. On some specification sheets the letter B, signifying
breakdown, precedes the voltage designation, i.e., BVcEo,
The generic shape of breakdown characteristics differs among transistors fabricated
by different processes. Figure 3.3 is typical of the planar epitaxial 2N2193. Note that
the BVcEo curve exhibits little current flow (Ict:o) until breakdown is initiated. At break-
down a region of negative resistance appears and disappears at increased collector
voltage. The region of negative resistance is not suitable for measurement and specifi-
cation because of instability. The low current positive resistance region below (in volt-
age) the breakdown region is so low as to cause instrumentation difficulties. It is
desirable, therefore, to measure breakdown voltage at a current, in the breakdown
region, where the slope is positive. This current for the 2N2193 family is 25 ma.
Since BVcEn and BVcEx as well as BVcEoexhibit a negative resistance region, they
must also be measured in a region of positive resistance. The voltage thus measured is
always less than voltage needed to establish breakdown. For this reason it has been
suggested that these voltages be named differently than breakdown voltages. One
proposal is to designate them as "sustaining" voltages with the prefix letter L substi-
tuted for B, i.e., LVcEn, The nomenclature VcEa c• u • t.> has also been used.
1000,-.-------------------,

1001---------------------1
i _ 25 MILLIAMPERESENSINGLEVEL
BVcu

i 101------------....---------1
a
a:

I
!THESE LEAKAGECURRENTSARE
EXAGGERATEOI
Ic[o Icn Icu

BVaolSUST.I
COLLECTORVOLTAGE
Yee

TYPICAL PLANAREPITAXIALCOLLECTOR
BREAKDOWNCHARACTERISTICS
Figure 3.3

The behavior of alloy devices is sufficiently different to warrant separate considera-

tion. Figure 3.4 illustrates a typical family of breakdown characteristics. Since leakage
currents are appreciable in this class of devices they form an important part of break-
down consideration. In the specification of BVcEo, consideration must be given to Ico
multiplication. In this connection Im is approximately hFE X I ..o, This product may
exceed 100 µ.a (the usual BVcso sensing current) at voltages well below breakdown.
For this reason it is common to specify breakdown at a collector current of 600 µa.
Figure 3.4 shows the realistic increase in voltage resulting from the use of a 600 µa
sensing current. The earlier statement that BVcEo is a very conservative rating is par-
ticularly true of germanium alloy devices. It is primarily applicable to circuits with
little or no stabilization.

32
 THE TRANSISTOR SPECIFICATION SHEET

I0K

IK

100

0.1 ..__ ____ 4-I..:C:a..:C•_....:rC=DO:....II~c~ol~------ ...........

-
BVcco
COLLECTORVOLTAGE

TYPICAL FAMILY OF ALLOYTRANSISTOR

BREAKDOWNCHARACTERISTICS
Figure3.4

BVct:11 is measured with the base shorted to the emitter. It is an attempt to indicate
more accurately the voltage range in which the transistor is useful. In practice, using
a properly stabilized circuit, such as those described in Chapter 7, the emitter junction
is normally forward biased to give the required base current. As temperature is in-
creased, the resulting increase in 1.-oand hFE requires that the base current decrease if
a constant, i.e., stabilized, emitter current is to be maintained. In order that base
current decrease, the forward bias voltage must decrease. A properly designed biasing
circuit performs this function. If temperature continues to increase the biasing circuit
will have to reverse bias the emitter junction to control the emitter current. This is
illustrated by Figure 7.1 which shows that VnE 0 when I .. =
0.5 ma at 70°C for =
=
the 2N525. VBE 0 is identically the same condition as a base to emitter short as far
as analysis is concerned. Therefore, the BVcEs rating indicates what voltage can be
applied to the transistor when the base and emitter voltages are equal, regardless of
the circuit or environmental conditions responsible for making them equal. Figure 3.4
indicates a negative resistance region associated with lc&s.At sufficiently high currents
the negative resistance disappears. The 600 µ.a sensing current intersects IcEs in the
negative resistance region in this example. Oscillations may occur depending on the
circuit stray capacitance and the circuit load line. In fact, "avalanche,. transistor
oscillators are operated in just this mode.
Conventional circuit designs must avoid these oscillations. If the collector voltage
does not exceed VA (Figure 3.4) there is no danger of oscillation. V,. is the voltage
at which the negative resistance disappears at high current.
To avoid the problems of negative resistance associated with BVcEs, BVcEa was
introduced. The base is connected to the emitter through a specified resistor. This
condition falls between BVcv.oand BVc•:Rand for most germanium alloy transistors
avoids creating a negative resistance region. For most low power transistors the resistor
is 10,000!2. The significance of BVc&a requires careful interpretation. At low voltages
the resistor tends to minimize the collector current as shown by equation ( 5q), in
Chapter 5. Near breakdown the resistor becomes less effective permitting the collector
current to increase rapidly.
Both the value of the base resistor and the voltage to which it is returned are
important. If the resistor is connected to a forward biasing voltage the resulting base
drive may saturate the transistor giving the illusion of a collector to emitter short.
Returning the base resistor to the emitter voltage is the standard BVcF.atest condition.
H the resistor is returned to a voltage which reverse biases the emitter junction, the

33
THE TRANSISTOR SPECIFICATION SHEET

collector current will approach I ..o, For example, many computer circuits use an emitter
reverse bias of about 0.5 volts to keep the collector current at cut-off. The available
power supplies and desired circuit ·functions determine the value of base resistance.
It may range from 100 to 100,000 ohms with equally satisfactory performance pro-
vided the reverse bias voltage is maintained.
In discussing the collector to emitter breakdown so far, in each case the collector
current is I ..o multiplied by a circuit dependent term. In other words all these collector
to emitter breakdowns are related to the collector junction breakdown. They all
depend on avalanche current multiplication.
Another phenomenon associated with collector to emitter breakdown is that of
reach-through or punch-through. Silicon devices as typified by grown diffused, double
diffused, planar, mesa, and planar epitaxial structures (see Chapter 2) do not exhibit
this characteristic. The phenomenon of reach-through is most prevalent in alloy devices
having thin base regions, and lighter base region doping than collector region doping.
As reverse voltage is increased the depletion layer spreads more in the base than in the
collector and eventually "reaches" into the emitter. An abrupt increase in current
results.
The dotted lines in Figure 3.4 indicate the breakdown characteristics of a reach
through limited transistor. Several methods are used to detect reach through. BVczx
(breakdown voltage collector to emitter with base reverse biased) is one practical
method. The base is reverse biased by 1 volt. The collector current Iczx is monitored.
If the transistor is avalanche limited BVcExwill approach BVcno. If it is reach-through
limited it will approach BVcEs,
Note that IcEx before breakdown is less than I ..o, Therefore, if I ..o is measured at a
specified test voltage and then the emitter is connected with a reverse bias of 1 volt,
the I ..o reading will decrease if reach-through is above the test voltage and will increase
if it is below.
"Emitter Boating potential" is another test for reach-through. If the voltage on an
open-circuited emitter is monitored while the collector to base voltage is increased, it
will remain within 500 mv of the base voltage until the reach-through voltage is
reached. The emitter voltage then increases at the same rate as the collector voltage.
VaT is defined as (Vcs - I) where Ven is the voltage at which VEs =
lv.

CURRENT
The absolute maximum collector current, shown as 1 ampere for the 2N2193, is a
pulse current rating. In this case it is the maximum collector current for which hFE is
specified. In some cases the current level at which hn drops from its maximum value
by 50% is specified. In all cases judgement concerning adverse life affects is a major
consideration. Also in all cases no other absolute maximµm rating can be exceeded in
using this rating. In cases of very short, high current pulses, the power dissipated in
transition from cutoff to saturation must be considered so that thermal ratings are
not exceeded.

TRANSISTOR DISSIPATION
Transistor dissipation ratings are thermal ratings, verified by life test, intended to
limit junction temperature to a safe value. Device dissipation is shown for three cases.
The first indicates the transistor in free air at an ambient temperah1re of 25°C. The
2N2193 under these conditions is capable of dissipating .8 watt. Further, we must
derate at a rate of 4.6 mw/°C for an ambient temperature above 25°C. This thermal
derating factor can be interpreted as the absolute maximum thermal conductance

34
 THE TRANSISTOR SPECIFICATION SHEET

junction to air, under the specified conditions. If dissipation and thermal conductance
are specified at 25°C case temperature an infinite heat sink is implied and both dissipa-
tion and thermal conductance reach their largest allowable values. For the 2N2193
these are 2.8 watts arid 16 mw/°C respectively.
Both free air and infinite heat sink ratings are valuable since they give limit appli-
cation conditions from which intermediate (in thermal conductance) methods of heat
sinking may be estimated.

TEMPERATURE
The 2N2193 family carries a storage temperature rating extending from -65°C
to +300°C. High temperature storage life tests substantiate continued compliance
with the upper temperature extreme. Further, the mechanical design is such that
thermal/mechanical stresses generated by rated temperature extremes cause no elec-
trical characteristic degradation.
Operating junction temperature although stated implicitly by thermal ratings is
also stated explicitly as an absolute maximum junction tempetature.

3. ELECTRICALCHARACTERISTICS
Electrical characteristics are the important properties of a transistor which are
controlled to insure circuit interchangeability and describe electrical parameters.

DC CHARACTERISTICS
The first characteristics shown are the voltage ratings, repeated in the order of the
absolute maximum ratings, but this time showing the conditions of test. Note that
.these and subsequent electrical parameters are measured at 25°C ambient temperature
unless otherwise noted. The 2N2193 has the highest rated breakdown voltages of the
series at Vcuo = 80V, VcF.o= 50V, and VEuo= 8V.
Forward current transfer ratio, hFF!,is specified over four decades of collector
current from 100 microamperes to 1 ampere. Such wide range in collector current is
feasible only in transistors having very small leakage currents. Note that hvE measure-
ments at 150, 500 and 1000 ma. are made at a 2 % duty cycle and pulse widths less
than or equal to 300 microseconds. This precaution is necessary to avoid exceeding
thermal ratings. Both the 2N2193 and 2N2193A have a specified minimum current gain
at -55°C. A collector current of 10 ma. was chosen as being most useful to the circuit
designer who wishes to predict low temperature circuit performance.
Base saturation, VBE<KAT>, specifies the base input voltage characteristic under the
condition of both junctions being foreward biased. The conditions of measurement
specify a base current of 15 ma. and a collector current of 150 ma. Base-emitter drop
is then 1.3 volts. This parameter is of particular interest in switch designs and is
covered in further detail in Chapter 5 (Equations 5s & 5t).
Collector saturation voltage, VcE c11AT>, is the electrical characteristic describing the
voltage drop from collector to emitter with both base-emitter and collector-base junc-
tions foreward biased. Base and collector currents are stipulated. For the 2N2193
through 2N2195 these are 15 ma. and 150 ma. respectively. The quotient of collector
and base currents is termed "forced Beta."
The principal difference between "A" and "non-A" versions of the 2N2193 family
lie in their maximum collector saturation voltages. "A" versions exhibit .16 volts
typically and are specified at .25 volts maximum. The "non-A" versions are specified
at .35 volts maximum. It is interesting to note that the 1.05 volt (minimum) difference

35
THE TRANSISTORSPECIFICATIONSHEET

between VBE (RAT> and VcF: (RAT> is the level of false trigger ( noise immunity level) for
DCTL switches. In germanium alloy devices this level is generally less than .3 volt
and is seldom greater than .7 volt in other silicon devices (see Chapter 6). The wide
difference in V nE (sAT> and VcE 1RAT> is undesirable if Darlington connection of devices
is desired for saturated switching. The collector saturation· characteristic of the com-
pound device demonstrates that the lead section is incapable of saturating the output
section. Modification of the circuit to provide separate connection of the input section
collector directly to the joint collector supply will provide the needed VBE (sAT> · to
allow output section saturation.

CUTOFF CHARACTERISTICS
Chapter 6 contains a detailed study of transistor leakage currents. This examination
deals with phenomena which predominate in alloy structures. The principal differences
in planar epitaxial devices lie in the relative magnitudes of the leakage current compo-
nents. The complete protection afforded by the passivation layer reduces surface
leakage to a very small value. Further, it reduces tbe surface thermal component by
decreasing recombination velocity. Figure 6.6(D) shows the variation with temperature
of Icno for units of the 2N2193 family. It is interesting to note that the theoretical
semi-log plot of lcso vs. temperature is a straight li~e. At high .temperatures planar
devices follow predicted behavior quite well. At lower temperatures, the temperature
rate is considerably less than that which would be predicted by the theoretical model.
The 25°C Iceo and IF:eo maximum limits are both 100 nanoamperes. Icno rises to
25 microamperes at 150°C, typically, and carries a 150°C upper limit of 50 µ.a.

HIGH FREQUENCYCHARACTERISTICS
The small-signal foreward current trans(er ratio, h,., is shown as a minimum of 2.5
at 20 me. This parameter is specified for those amplifier applications requiring control
of high frequency h,., Chapter 15 treats the measurement of high frequency h,. in
detail.

SWITCHING CHARACTERISTICS
Chapters 6 and 15 on switching and measurements, respectively, discuss and define
transient response times tc1,tr, t., and t,. The circuit used to measure tr, t., and tr is
shown in Figure 3.5. The specified maximum rise, #orage, and fall times are measured
in this circuit. The base of the transistor under test is clamped at approximately -1.5
volts by the diode returned to a -1 volt bus. As the point VI n is raised in potential the
base is undamped and the transistor moved through the active region to saturation.
As noted in the referenced chapters, the switching times measured are highly circuit
-IV

,,.._..._---tt---ovour
0--------11-- .... ---"N'~----1"1

51
OHMS
Figure3.5
SWITCHING
CIRCUIT

(2N2l93 1 2N2193A,2N2194 AND 2N2194A ONLY)

36
 THE TRANSISTOR SPECIFICATION SHEET

dependent. By the time this description is published more thorough switching char-
acterization will be made available, which specify td, t,, t., and tr as a function of the
ratio of collector current to foreward base current (forced beta).

GENERIC CHARACTERISTICS
Much information about the behavior of semiconductor devices is conveyed by
showing typical behavior. This information is presented graphically and differs from
other electrical specifications by not bearing the high statistical assurance associated
with maximum and minimum limits. Statistical confidence is assigned the generic
characteristics of some devices by showing 5th, 50th, and 95th percentile points of a
given characteristic. This sort of specification is found as part of very thoroughly
characterized devices such as the 2N335 and 2N396.

600 ff--:Nl---:::;j_.-t""""'9:-

J 500
400
rr-----,----:;:,r-:::::t=~
i++- ______ _

10 20 30 40
VcE (VOLTS} VcE (VOLTS}
2N2193,A 2N2194, A

1000

900

800

700

600
0
! 500
u
M
400

300

200

100

0 5 10 15 20 25
VcE (VOLTS)
2N2195, A

Figure3.6

37
 THE TRANSISTOR SPECIFICATION SHEET

The specification sheet for the 2N2193 family includes collector family data for
the 2N2193, 2N2194 and 2N2195 and associated "A" versions. The hyperbola of con-
stant 2.8 watt 25°C dissipation is shown in Figure 3.6 to demark the area of permissible
static operation as defined by previously discussed thermal limitations. In addition, a
triangular area bounded by the collector current and collector voltage axes and a line
noted as "region defined by specification" is specified. This area is one that defines
the safe boundary for transient operation and should at no time be exceeded.
Semiconductor manufacturers go to great lengths in constructing their product
specification sheets because they realize the value of offering the designer adequate
information. H the device described therein is to be of use to the design engineer, is to
be used properly for optimum performance and reliability by the designer within the
limits specified by the manufacturer, the specification sheet must be accurate, com-
plete, and reliable. This requires precise and time consuming measurements, coupled
with costly hours of anlysis and preparation af the final specification sheet. The tran-
sistor specification .sheet is, without doubt, the most important work tool the electronics
circuit designer has at his disposal. When understood by the designer and used intelli-
gently, many labor hours can be saved.

EXPLANATIONOF PARAMETERSYMBOLS
SYMBOL ELEMENTS
A Ampere (a.c., r.m.s or d.c.), ambient, anode electrode
a Ampere (peak or instantaneous)
B,b Base electrode, breakdown
C,c Capacitance, collector electrode, cathode electrode
( Delta) A small change in the value of the indicated variable
E,e Emitter electrode
F, f Frequency, forward transfer ratio
G,g Gain, acceleration of gravity, gate electrode
h General symbol for hybrid parameter
I, i Current, input, intrinsic region of device
J, j Reference electrode
K,k Unspecified (general) measurement electrode
L Inductance
N,n n-region of device
O,o Output, open circuit
P,p Power, P-region of device
0 Charge
R,r Resistance, reverse transfer ratio
T Temperature
Time

38'
 THE TRANSISTOR SPECIFICATION SHEET

V Voltage (max., avg. or r.m.s)

V Volt (peak or instantaneous)
w Watt (Max., avg. or r.m.s)
w Watt (peak or instantaneous)
X Unspecilied (general) parameter
y General symbol for an admittance parameter
8 (Theta) Thermal resistance
Z,z General symbol for impedance, impedance parameter

DECIMAL MULTIPLIERS
Pre&x Abbreviation Multiplier Pre&x Abbreviation Multiplier
tera T 1012 milli m 10-a
giga G 1011 micro p. 10-0
mega Mor Meg me nano n 10-11
kilo· Kork 10a pico p 10-12

PARAMETERSYMBOLS
BVceo *DC breakdown voltage collector to base junction reverse biased,
emitter open-circuited ( value of le should be specified).
BVcEo *DC breakdown voltage, collector to emitter, with base open-
circuited. This may be a function of both "m" (the charge carrier
multiplication factor) and the hrb of the transistor. Specify le.
BVcER •DC breakdown voltage, similar to BVcEoexcept a resistor value "R"
between base and emitter.

BVcEs *DC breakdown voltage, similar to BVcEobut base shorted to emitter.

BVcr:v •DC breakdown voltage, similar to BVcEo but emitter to base junc-
tion reverse biased.
BVce:x *DC breakdown voltage, similar to BVc11:o but emitter to base junc-
tion reverse biased through a specified circuit.
BVEBO •DC breakdown voltage, emitter to base junction reverse biased,
collector open-circuitecl. Specify IE,

BVa DC breakdown voltage, reverse biased diode.

Barrier capacitance.

*(Common base) capacitance emitter to base, collector open.

c .. Input capacitance.

*(Common base) collector to base l Output capacitance measured

*(Common emitter) collector to emitted across the output terminals.

39
 THE TRANSISTORSPECIFICATIONSHEET

Frequency at which measurement is performed.

(Common base) small-signal short-circuit forward current transfer

ratio cut-off frequency.
(Common emitter) small-signal short-circuit forward current trans-
fer ratio cut-off frequency.

Maximum frequency of oscillation.

Gain bandwidth product frequency at which the small signal, com-

mon emitter, short-circuit, forward current, transfer ratio (hre) is
unity or zero db.

-g Negative Conductance.

*(Common base) small-signal power gain.

GrE *(Common emitter) large-signal power gain.

*(Common emitter) small-signal power gain.

Gp,.(CONV.) *(Common emitter) conversion gain.

htb (Common base)

hrc (Common collector)

Small-signal short-circuit forward
current transfer ratio, output ac
hre (Common emitter) short-circuited.

hrJ (General)

*(Common emitter) static value of forward current transfer ratio,

hFE=fa

hvE (inv.) Inverted hFE(emitter and collector leads switched)

(Common base, common emitter, common collector, general) small-

signal input impedance, output ac short-circuited.

(Common emitter) static value of the input resistance.

h,. (real) (Common emitter) real part of the small-signal value of the short-
circuit input impedance at high frequency.
hob,hoe, (Common base, common emitter, common collector, general) small-
hu.,,h ..J signal, output admittance, input ac open-circuited.
h,b, h,.., (Common base, common emitter, common collector, general) small-
h,c, h,J signal, reverse voltage transfer ratio, input ac open-circuited.
I, i Region of a device which is intrinsic and in which neither holes nor
electrons predominate.

40
 THE TRANSISTOR SPECIFICATION SHEET

DC currents into base, collector, or emitter terminal.

Base current (rms)

Base current ( instantaneous)

lex DC base current with both the emitter and collector junctions
reverse biased.

I., Collector current (rms)

Collector current (instantaneous)

lceo ( lco) *DC collector current when collector junction is reverse biased and
emitter is open-circuited.
lcEo *DC collector current with collector junction reverse biased and base
open-circuited.
*DC collector current with collector junction reverse biased and a
resistor of value "R" between base and emitter.
Icii:s *DC collector current with collector junction reverse biased and base
shorted to emitter.
*DC collector current with collector junction reverse biased and with
a specified base-emitter voltage.
lcu *DC collector current with collector junction reverse biased and with
a specified base-emitter circuit connection.

Emitter current (rms)

Emitter current (instantaneous)

*DC emitter current when emitter junction is reverse biased and

collector is open-circuited.
hes *DC emitter current with emitter junction reverse biased and base
shorted to collector.

*DC forward current.

Forward current (instantaneous).

Peak Point current.

L,/lv Peak to Valley current ration.

Reverse Current (DC).

in Reverse Current (instantaneous).

41
THE TRANSISTOR SPECIFICATION SHEET

Iv Valley Point Current.

Conversion loss - ratio of available signal power to the available

intermediate frequency power.

Ls Total series inductance.

N,n Region of a device where electrons are the majority carriers.

Intrinsic stand-off ratio (unijunction).

NF Noise Figure .

P,p . Region of a device where holes are the majority carriers.

Pt (peak) Peak collector power dissipation for a specified time duration, duty
cycle and wave shape.

Pc Average continuous collector power dissipation.

Power output.

pt (peak) Peak total power dissipation for a specified time, duration, duty
cycle and wave shape.

Average continuous total power dissipation.

Qss Stored ·base charge.

Base spreading resistance equals h,. (real) when h, e (imagi-

nary)= 0.
re1s20(rueo) Device resistance between base 1 and base 2, emitter open-circuited
(interbase resistance - unijunction).
rcE(SAT) Device resistance, collector to emitter, under saturation conditions
(saturation resistance, steady state).

RE Rectification Efficiency (voltage).

Circuit resistance between terminals K and J.

Load resistance.

r. Small signal series resistance.

Operating Temperature (ambient)

Junction Temperature

42
 THE TRANSISTOR SPECIFICATION SHEET

TsTo Storage Temperature

Circuit voltage between terminals K and J.

Peak point voltage.

Va DC reverse voltage.

VaT DC voltage reach-through (formerly called punch-through CPT),

At collector voltages above reach-through VnT
normally defined as I volt).
=
VcB - VEB, (Vzo

Valley point voltage.

Yo Small signal short circuit forward transfer admittance.

Z1J Input impedance.

ZoJ Output impedance.

•Test conditions must be specified.

NOTE: DC voltage and current terminologies ( as listed herein) are valid only
when measurements are made under non-oscillating conditions. Care
must be exercised with Avalonche Transistors as they may oscillate
when making these measurements and give erroneous readings.

ABBREVIATEDDEFINITIONS OF TERMS
I. Absolute Max. Ratings - the value when so specified is an "absolute limit" and
the device is not guaranteed if it is exceeded.
2. Applied Voltage - voltage applied between a terminal and the reference point.
*3. Constant Current - one that does not produce a parameter value change greater
than the required precision of the measurement when the generator impedance is
halved.
*4. Constant Voltage - one that does not produce a parameter value change greater
than the required precision of the measurement when the genrator impedance is
doubled.
*5. Breakdown Voltage (BV) - that value of applied reverse voltage which remains
essentially constant over a considerable range of current values, or where the incre-
mental resistance = 0 at the lowest current in avalanche devices.
6. Limits - the minimum and maximum values specified.
7. Noise Figure (NF) - at a selected input frequency, the noise figure (usually 10
log of base 10 of ratio) is the ratio of the total noise power per unit bandwidth at a
corresponding output frequency delivered to the output termination, to the portion
thereof engendered at the input frequency by the input termination, (whose noise
0

tempera ture is standard 290°K).

43
THE TRANSISTOR SPECIFICATION SHEET

8. Open Circuit - a condition such that halving the magnitude of the terminating
impedance does not produce a change in the parameter measured greater than the
required precision of the measurement.
9. Pulse - a flow of energy of short duration which conveys intelligence.
10. Pulse Average Time ( tw) - the time duration from a point on the leading edge
which is 50% of the maximum amplitude to a point on the trailing edge which is 50%
of the maximum amplitude.
11. Pulse Delay Time (t.s)- the time interval from a point on the leading edge of
the input pulse which is 10% of its maximum amplitude to a point on the leading edge
of the output pulse which is 10% of its maximum amplitude.
12. Pulse Fall Time (tr) - the time duration during which the amplitude of its
trailing edge decreases from 90 to 10 % of the maximum amplitude.
13. Pulse Rise Time (tr)-the time duration during which the amplitude of its lead-
ing edge increases from 10 to 90% of the maximum amplitude.
14. Pulse Storage Time (t.) - the time interval from a point 10% down from the
maximum amplitude on the trailing edge of the input pulse to a point 10% down from
the maximum amplitude on the trailing edge of the output pulse.
15. Pulse Time (tp) - the time interval from a point on the leading edge which is
90% of the maximum amplitude to a point on the trailing edge which is 90% of the
maximum amplitude.
16. Short Circuit - a condition where doubling the magnitude of the terminating
impedance does not produce a change in the parameter being measured that is greater
than the required precision of the measurement.
17. Small Signal - a signal is considered small when halving its magnitude does
not produce a change in the parameter being measured that is greater than the required
precision of the measurement.
18. Spike - an unintended How of electrical energy of short duration.
19. Supply Voltage (Van, Vee, VEE)-the potential of the circuit power source.
20. Thermal Equilibrium - a condition where doubling the test time does not
produce a change in the parameter that is greater than the required precision of the
measurement.
21. Thermal Resistance (0) - the temperature rise per unit power dissipation of
the junction above the device case or ambient temperature under conditions of steady-
0
state operation (where applicable, case" means device mounting surface).
22. Thermal Response Time hr) - the time required for the junction temperature
to reach 90% of the final value of junction temperature change caused by a step func-
tion in power dissipation when the device case or ambient temperature is held constant.
23. Thermal Time Constant ('Yt)-the time required for the junction temperature
to reach 63.2 % of the final value of junction temperature change caused by step func-
tion in power dissipation when the device case or ambient temperature is held constant.
24. Base Voltage (Vu1)- the voltage between the base terminal and the reference
point (J).
25. Collector Voltage (Ve1)- the voltage between the collector terminal and the
reference point (J).

44
 THE TRANSISTOR SPECIFICATION SHEET

26. Cut-off Current (IK,o, IKrn, IK,ic,IKn·, IK,x) - the measured value of (K) elec-
trode DC current when it is reverse-biased by a voltage less than the breakdown voltage
and the other electrode(s) is (are) DC open-circuited (IKJo)or:
1. returned to the reference electrode (J) through a given resistance (IKrn)
2. DC short circuited to the reference electrode (J) (IK,s)
3. reverse-biased by a specified voltage (IK,v)
4. under. a specified set of conditions different from the above (IK,x),
27. Depletion Layer Capacitance (C dep) - the transition capacitance of a reverse-
biased PN junction. (Small signal as well as DC conditions to be stated).
28. Diffusion Capacitance (C dif) - the transition capacitance of a forward biased
(with an appreciable current How) PN junction.
29. Emitter Voltage (Vv.,)- the voltage between the emitter terminal and the
reference point (J).
30. Floating Potential (VKJF)- the DC voltage between the open circuit terminal
(K) and the reference point (J) when a DC voltage is applied to the third terminal and
the reference terminal.
31. Input Capacitance (C1J)- the shunt capacitance at the input terminals.
32. Input Terminals - the terminals to which input voltage and current are applied.
33. Inverse Electrical Characteristics [XKJ(INV)] - those characteristics obtained
when the collector and emitter terminals are interchanged.
34. Large-signal Short Circuit Forward-current Transfer Ratio (hFJ) - ratio of the
change in output current (.1.Io)to the corresponding change in input current (.1.L).
35. Large-signal Transconductance (Gm) - the ration of the change in output
current (.1.1.,)to the corresponding change in input voltage (.1.V,).
36. Large-signal Power Gain (G.,) - the ratio of the ac output power to the ac
input power under the large signal conditions. Usually expressed in decibels (db).
(ac conditions must be specified).
37. Maximum Frequency of Oscillation (f..... or fmnx)- the highest frequency at
which a device will oscillate in a particular circuit.
38. Output Capacitance (C.,J)- the shunt capacitance at the output terminals.
39. Output Terminals - the terminals at which the output voltage and current may
be measured.
40. Power Gain Cut-off Frequency (fpJ) - that frequency at which the power out-
put has dropped 3 db from its value at a reference test frequency (G,,(f) =
constant)
with constant input power.
41. Reach Through Voltage (VaT) (formerly referred to as "punch through volt-
age") - that value of reverse voltage at which the reverse-biased PN junction spreads
sufficiently to electrically contact any other junction or <.'Ontact, and thus act as a
short circuit.
42. Real Part of Small Signal Short-circuit Input Impedance [h, 1 ( real)] - the
real part. of the ratio of ac input voltage to the ac input current with zero ac output
voltage.

45
THE TRANSISTOR SPECIFICATION SHEET

43. Reference Point (electrical) - the terminal that is common to both the input
and output circuits.
44. Saturation Resistance [rK1(SAT)]-the ratio of saturation voltage to the
measurement (K) electrode DC current.
45. Saturation Voltage [VK1 (SAT)] - the DC voltage between the measurement
electrode (K) and the reference electrode (J) for the saturation conditions specified.
46. Small-signal Open-circuit Forward Transfer Impedance (ztJ) - the ratio of the
ac output voltage to the ac input current with zero ac output current.
47. Small-signal Open-circuit Input Impedance (z1J)- the ratio of the ac input
voltage to the ac input current with zero ac output current.
48. Small-signal Open-circuit Output Admittance (hoJ)- the ratio of the ac output
current to the ac voltage applied to the output terminals with zero ac input current.
49. Small-signal Open-circuit Output Impedance (ZoJ)- the ratio of the ac voltage
applied to the output terminals to the ac output current with zero ac input current.
50. Small-signal Open-circuit Reverse Transfer Impedance (ZrJ)- the ratio of the
ac input voltage to the ac output current with zero ac input current.
51. Small-signal Open-circuit Reverse Voltage Transfer Ratio (hrJ) -the ratio of
the ac input voltage to the ac output voltage with zero ac input curre~t.
52. Small-signal Power Gain (Gp)-the ratio of the ac output power to the ac
input power. Usually expressed in db.
53. Small-signal Short-circuit Forward Current Transfer Ratio (htJ) - the ratio of
the ac output current to the ac input current with zero ac output voltage.
54. Small-signal Short-circuit Forward Current Transfer Ratio Cut-off Frequency
{fhrJ)- the frequency in cycles per second (cps) at which the absolute value of this
ratio is 0.707 times its value at the test frequency specified (Gp(f) = constant).
55. Small-signal Short-circuit Forward Transfer Admittance (ytJ) -the ratio of the
ac output current to the ac input voltage with zero ac output voltage.
56. Small-signal Short-circuit Input Impedance (h1J)-the ratio of the ac input
voltage to the ac input current with zero ac output voltage.
57. Forward Voltage (Vvp)-highest value of positive voltage at which the forward
current equals the maximum specified peak point current (I,.= IP),
58. Peak Point Current (Ir) - value of the static current flowing at the lowest posi-
tive voltage at which ddr= 0.
V d
59. Peak Point Voltage {Vr) -the lowest positive voltage at which d: = 0.

60. Peak to Valley Ratio ~: - the ratio of peak point current to valley point current.
61. Valley Point Current {Iv)-the value of the static current flowing at the second
d
lowest positive voltage at which d: = 0.
62. Valley Point Voltage {Vv)- the second lowest positive voltage at which~:= 0.
•Test conditions must be specified.

46
SMALL SIGNAL
CHARACTERISTICS

A major area of transistor applications is in various types of low level a-c amplifiers.
One example is a phonograph preamplifier where the output of a phonograph pickup
(generally about 8 millivolts) is amplified to a level suitable for driving a power ampli-
fier (generally 1 volt or more). Other examples of low level or small signal amplifiers
include the IF and RF stages of radio and TV receivers and preamplifiers for servo
systems.
As described in Chapter 5, Large Signal Characteristics, a transistor can have very
nonlinear characteristics when used at low current and voltage levels. For example, if
conduction is to take place in an NPN transistor the base must be positive with respect
to the emitter. Thus, if an a-c signal were applied to the base of an NPN transistor,
conduction would take place only during the positive half cycle of the applied signal
and the amplified signal would be highly distorted. To make possible linear or undis-
torted amplification of small signals, fixed d-c currents and voltages are applied to the
transistor simultaneously with the a-c signal. This is called biasing the transistor, and
the d-c collector current and d-c collector to emitter voltage are referred to as the
bias conditions. When bias conditions are chosen so that the largest a-c signal to be
amplified is small compared to the d-c bias current and voltage, the transistor is said
to be operating in small signal mode.
Transistors used in small signal amplifiers are normally biased at currents between
0.5 and 10 ma. and voltages between 2 and 10 volts. Bias currents and voltages below
this range can cause problems of distortion, while bias currents and voltages above this
range can cause problems of excessive noise and power dissipation.
For the purpose of circuit design, any component, including the transistor, can be
considered as a black-box (B-B) having two input terminals and two output terminals.
With the help of Matrix Theory the circuit designer, knowing the electrical character-
istics of the black-box, can calculate the performance of the amplifier when various
signal sources are applied to its input and various loads are connected to its output.
Although possibly foreboding in name Matrix Theory is, in fact, easy to understand
and apply. The relative ease with which it may be used in circuit analysis, com-
pared to other analysis methods, makes the understanding of it a "must" for the
circuit design engineer. When certain stipulations are made, Matrix Theory is perfectly
applicable to circuits involving active elements like the transistor. Its use is virtually
mandatory in complicated circuits involving feedback, particularly where the preserva-
tion of the sanity of the analyst is considered necessary.

-----,---- ----f', ,----

IN _[~3:_:Ji~J_ :I "'>
.,(
----t,," '-----

SERIESIMPEDANCE SHUNT IMPEDANCE AMPLIFIER

EXAMPLESOF BLACK-BOXES
Figure 4.1

47
S~ ALL SIGNAL CHARACTERISTICS

Basically, the matrix method of analysis involves the black-box concept where the
fundamental components or groups of components of a circuit (inductors, capacitors,
resistors, and active elements) are considered as black-boxes having two input and two
output terminals.
Conventionally the input terminals are on the left side of the box with the corre-
sponding output terminals on the other side. There is also a convention regarding the
input and output potentials and currents shown in Figure 4.2.

INPUT
TERMINALS
{ BLACK
BOX

BLACK-BOXSHOWING INPUT AND OUTPUT CONVENTION

OUTPUT
TERMINALS

Figure4.2

In a sensible black-box, there is a well-defined relationship between the input

voltage and current and the corresponding quantities at the output. The most often
realized and most easily handled functional relationship is linearity. A pair of linear
equations will then completely represent the black-box. As an example, consider the
following which are equations expressing the input and output voltages in terms of
input and output current
=
e1 Z11i1+ Z12i:1 (4a)
e2 = ~1it + Z::ii: (4b)
Zn, Z12,Z:it, Zit have the dimensions of impedance and are called the "impedance
parameters" of the black-box.
The matrix equation equivalent to (4a) and (4b) is

[e,]
e:1 -
[Zn
Z:n Z::i
[it]
Z12]
. or more concisely (e]
1:
= [Z] [i] (4c)

Z parameters are useful when two or more black-boxes are connected together such
that their input terminals are connected in series and their output terminals are also
in series as shown in Figure 4.3.

[Z] -----c,I
e2

e,_
___
_
8
I l
I
[Z']
BLACK-BOXESWITH SERIES CONNECTIONS
AT INPUT AND OUTPUT
Figure4.3

48
 SMALL SIGNAL CHARACTERISTICS

Because of the method of connection i1 and i2 are the same as for a single B-B. The ei's
are added, as are the e/ s.

[!:J= [Z combined] [::] (4d)

Z combined is the matrix of the single black-box which is equivalent to the two black-
=
boxes combined. E1 e1 + e1', K1 e:1+ e/. =
(4e)

!El= (cz1
+ cz·1)
[~] (4f)

Matrix theory tells us that Z + Z' is obtained by simple summing of the individual
terms of the matrixes, i.e.

Z1:1 + Z12']
Z:i-,+ 'hi'
[i•]
i2
(4g)

Therefore the two original B-B's may be replaced by one B-B having the parameters
shown in equation (4g).
If two black-boxes are to have their input terminals paralleled and their output
terminals paralleled also, then a different set of original equations is set up.
1, =Ci,+i,') 1 2=<i2+ 12'>

[Y] 12

•11
~-----
,.•-----
'2' -----~ !•2
-----c_,
[Y']
BLACK-BOXES
IN PARALLEL
Figure 4.4

The currents are now additive, voltages e1 and e: are the same for the combination as
for the individual B-B's. The currents ii and i: have to appear on the left hand side of
the two equations.

(4h)

The "y" parameters have the dimensions of conductance and are called the "admittance
parameters." So far the parallel combination of two black-boxes

[1.]= [ ~•+ ~':] = (cyJ

I:
[e•J
+ [y'J)
1:t+1:i e::
(4i)

[I] = [ Yu + Yu' (4j)

Y21 + Y:1
49
SMALL SIGNAL CHARACTERISTICS

For cascaded black-boxes yet another set of parameters called "a" parameters has
to be established and these are perhaps the most useful of any.

[a] [a'J
~-~ ----------r~-~
BLACK-BOXES
IN CASCADE
Figure4.5
Notice in Figure 4.5, e.' is the same as ea since their respective terminals are connected
together. However, ii' = -i1 but the sign is taken care of by making the basic equation
of this form

~1
1t
= au e:r-
= a:ne:i -
au!~'} [ ~•
au i, 1i
J= [al [ e2.
-12
J (4k)

So, the over-all equation for the two cascaded B-B's shown in Figure 4.5, is

[~1]
= e~'.]
h
[Al [
-1:i
(41)

For the individual B-B's the two matrix equations are

1
[ ~ ] = [al [ e~ ] and[~•:]= [a'l [ e~',] (4m) (4n)
h -b h -ls
but e:r= e1', and -i1 = ii'

therefore
1
[ ~ ] = [al [~
h
1
h
:J = [al X [a'l [ e,:,]
-t,
(4o)

[A] =
[a] X [a'] (4p)
and the "a" matrix is called the "multiplier matrix" for obvious reasons.

Matrix theory tells us that the expansion of [al X [a'l is done as follows

[a] X [a']= [au a12] X [an: a12']

a21 al!2 a21 an'
= [(au au'+ a11an'), (au a1s'+ 811a22')]
(a21an' + an a21'),(a21a12'+ 822 a22')
therefore

[
e• 1] = [(anau' + a12a21'),(a11a12'
11
+ a12an')] [ ez'
(an au' + a22a,i'), (821 a1,.'+ 822 an') -i2'
J (4q)

50
 SMALL SIGNAL CHARACTERISTICS

When inputs are "seriesed" and outputs "paralleled," a set of parameters called
the "h" parameters is obtained to represent the B-B's as shown in Figure 4.6.

[h]

[h'J
WITHINPUTS IN SERIES
BLACK-BOXES
ANDOUTPUTSIN PARALLEL
Figure4.6

For the first B-B

[::J
[;:] = [h] (4r)

for the second B-B

[::J=[h•i[:J (4s)

For the combination

(4t)

Finally the "g" parameters, those used when analyzing B-B configurations wherein
the B-B inputs are "paralleled" and the outputs are "seriesed."

/,___ :__ [9]

i2

--•~•t l
(v·--- ---._,,
E2= (e2+e2 1

BLACK-BOXES
-------~
WITH INPUTS IN PARALLEL
AND OUTPUTSIN SERIES
Figure4.7
For the first B-B

[::] = [g] [
for the second B-B
:J (4u)

[;:,] = [g'] [ ;:] (4v)

therefore for the combination

[ l1]= [ i1+ i1',]

E2
= ([g]
e2+e2
[~1]
+ [g'])
12
(4w)

51
SMALL SIGNAL CHARACTERISTICS

Knowing one set of the above established parameters, the others may be worked out,
or more conveniently, obtained from Figure 4.8.

MATRIX INTERRELATIONS

1~~[z]l
[Y] [h] [9] [a]

[z]

Yi _I_ -h12 ~ 912 °22 -!lo

Y11 2
h11 h11 922 922 °12 °12
[Y] h21 flh -921 I -I ~
Y22 lij'j lijj" 922 922 °12 a 12

llz z12
Z22 Z22 Y11
[h_] -z21 _I_ 1A_ flY
z22 z22 YII YII

[g]

[a]
-1i -yll -h22 ~ .!LL Ilg
Y21 Y21 h21 h21 921 921

NOTE: fl REPRESENTS THE DETERMINANT (llz = Z11Z22-Z2, z,2)

Figure 4.8

52 -----------------------
 SMALL SIGNAL CHARACTERISTICS

The restriction placed on the derivation of the various black-box parameters is that
the equations connecting input and output voltages and currents shall be linear. The
parameters may be complex (frequency-dependent) but the relationships must be linear.
A transistor can be considered linear when the signal excursions within it are small
compared to its bias current and voltage conditions. Under these conditions, known as
"Small Signal Operation" the transistor may be thoroughly represented as a black-box
when any one set of parameters, z, y, a, h, or g are obtained.
The matrix chosen to define a transistor by its manufacturers is naturally enough
that involving those parameters which are easiest to measure. Usually, the "h" param-
eters are measured and, more often than not, with the transistor in the common-base
configuration. The reader is referred to Chapter 15 of this manual for practical meas-
urement details. The reason why it is easier to measure the "h" parameters rather than
the others may be seen from their definition.

[h]

BLACK-BOXREPRESENTING11h" PARAMETERMEASUREMENTS
REFERREDTO IN TEXT
Figure4.9

(4x)

expanded
(4y)
(4z)
From equation (4y)
1
hn = ~ when e2 = 0
h

From equation (4z)

h:1 = ~h when e2 =0
h22 = e2i:1 when i1 = 0
=
For the transistor, hn is often called h1, the input impedance. The condition e2 0 is
the same as saying the output terminals are short-circuited to the signal. In addition,
hu is called h., the reverse voltage transfer ratio. The condition ii= 0 means open-

53
 SMALL SIGNAL CHARACTERISTICS

circuit input. hn becomes h,, the forward current transfer ratio with output short-
circuited to signal currents. And finally, bu is ho, the output admittance with open-
circuit input. h,, hr, hr and ho usually also have yet another subscript to indicate to
which transistor configuration they refer. For example: h,b is the input impedance of a
transistor with output signal short-circuited when used in the common-base configura-
tion, and hrc is the reverse voltage transfer ratio with the input of a transistor open
circuited when used in the common-collector configuration. It will be noticed that in
defining the h parameters two conditions are stipulated:
1. Output short-circuited with respect to signal.
2. Input° open-circuited with respect to signal.
The phrase with respect to signal is necessary in these two conditions, since in any
practical circuit it is necessary to provide for bias currents as in Figure 4.10.

~
,
I
I
I
--
•2

_l.
··re R4
I
R2 I
I R1R2
J RAa
R1+R2

(A) PRACTICAL
CIRCUIT (B) EQUIVALENT
CIRCUIT
Figure4.10

"Short-circuited output with respect to signal" would then mean placing a hefty
capacitor across the output terminals in the manner shown. The transistor has a fairly
low input impedance and a high output impedance, at least in the common-base and
common-emitter configurations (measurements are seldom made on a transistor in the
common-collector connection owing to its proneness to instability). It is therefore easy
to provide a high impedance current source for the input to obtain the open-circuit
input condition and a stiff voltage source for the output (i.e. short-circuit). Hence it is
easiest, in practice, to measure the h parameters. The letter h, incidentally, stands for
hybrid,"a name which reflects the mixing of input and output voltages and currents in
the two h parameter equations of the black-box.
Once the· h parameters of a transistor are known for a particular configuration, the
z, y, a, and g parameters may be obtained from the conversion table in Figure 4.8.
Corresponding h parameters of the other configurations may be found by referring
to the table in Figure 4.11 which gives the h parameters in terms of the 'T' equivalent
circuit as well.

54
 SMALL SIGNAL CHARACTERISTICS

APPROXIMATECONVERSIONFORMULAE
H PARAMETERSAND T EQUIVALENTCIRCUIT
.(NUMERICALVALUES ARE TYPICAL FOR THE 2N525 AT I MA, !5V)
SYMBOLS T EQUIVALENT
COMMON COMMON COMMON CIRCUIT
EMITTER BASE COLLECTOR (APPROXIMATE)
IRE OTHER

h J_ hib
hja 1400 OHMS hie 'b+.!L
lie •y
111 T+ii;;"" I-a

hre h121•l'bc 3.37 xio- 4 hibhob

l+h,;-hrb I-h,c
,.
(I-a)rc

_ _Mt_ _a_
hfe "21,,/J 44 -(l+htc> I-a
l+htb

I hob I
hoe hu.-z22e ?:TX 10-6 MHOS l • hfb
hoc (I-a) re

htb
I
hu 'Yu
hie
l+hft
3IOHMS -~htc 'e + (1-a)rb

~ 5X ro-4 h,c-1-~ 'b

hrb h12 •l'te l+hte - h,_ htc 'c

- _!!u_ -0.978 - l+hfb -a

hfb h21 ,a l+ht 1 hfb

hoe hoc I
hall h22•z I
22 l+hfe
0.60 X I0- 6 MHOS
-~ re
h J_ hib
hie hit I4000HMS rb+...!!...
lie 'Ync l+hfb I-a

h,c h12c •l'be 1-11,. I 1.00 1-...!L.

(1-a)rc

I I
htc h21c10 1b -(l+h11>
- l+hfb
-45 -i=;

~ 27 X 10- 6 MHOS
I
lhoch22c•z 22
I
c hot
l+hfb (1-a)rc

a ..1?fs... -hfb h:!!& 0.978

l+hfe hfc
l+hte 1-hrb _!!ti;
re 1.67 MEG
hoe hob hoc

h1b- !!!Jt
.!n I-hrc
re hob(l+htb) 12.!5OHMS
hot hoc

h !!m htc
'b hje- ~ (l+hfe) hie+ hocU-h,c) 840 OHMS
hob

Figure 4.11

55
SMALL SIGNAL CHARACTERISTICS

The h parameter equivalent circuit is shown in Figure 4.12 together with the
,.T,, equivalent circuit of the transistor.

e .------------4n C
.Le2
t
hob I
ba-------~-----~------ob
(A) HYBRID EQUIVALENTCIRCUIT
(COMMON BASE CONFIGURATION)

bc• -----------ub
(B) "T" EQUIVALENTCIRCUIT
(COMMON BASE CONFIGURATION)
Figure4.12
The "T" equivalent circuit is of interest since it approximates the actual transistor
structure. Thus r. and r., represent the ohmic resistances of the emitter and collector
junctions respectively while rh represents the ohmic resistance between the base con-
tact and the junctions. The current generator ct1 .. represents the transfer of current from
the emitter junction to the collector junction across the base region. The ,.T,, finds its
greatest use in circuit synthesis particularly when the designer is initially laying out
his circuit. He knows, for example, that the input impedance of a common-emitter
stage is approximately rb plus /3 times the total impedance appearing in the emitter
circuit (which includes r.,) - such approximations not being so easily arrived at from a
knowledge of hybrid parameters. When it is necessary, however, to analyze the per-
formance of a given circuit with a fair degree of accuracy, four-pole parameters are
extremely useful, in some cases almost indispensable. As might be expected from the
,.small signal" restriction, h parameters vary with operating point. Specification sheets

56
 SMALL SIGNAL CHARACTERISTICS

often carry curves of the variation of the small signal parameters with bias current
and voltage. Such curves are shown in Figure 4.13. These are specifically for the
2N525 and are plotted with respect to the values at an operating point defined by a
collector potential of 5 volts and an emitter current of 1 ma.
/
11
..
/
IO
r°"('lb TA•25°C
,,,,
i,
Yc•-5V
'-
~
'-
~ ~ /

" "' ,,",, /

V
V
<,;
i
~LO
~ i-
.,_n,., - :---
I'-.
r-...
~~
~~ --~ ..,.
II
-~ --.........
i h,.

_.,,/'
'/
1.;
"''\. .........
I'-..
,,
l+h,-

-- __,,...... "
O.J
'\. ....,
I'\ "'i-.,
","'~111, ...............
j;';;-..
0. I
"l.
-0.1 -o.J -1.0 -1.0 -«>
EIIITTlR CUIIIIEIIT lt(IIAI
CHARACTERISTICS
VS EMITTERCURRENT

::=T,. 2s•c 0

I
a: ll.O
i-- It•IMA

s
a:
i,,..hob
h~
~
I
~ ........
~ ~ hr, h11
~ h111t ~-.. _.., L---"
w 1.0 h111t
~ ht, h11
~~

~ hob
d
a:
h,11,

t
Ill
ii
§ 0.ll

o.,
-1.0 -s.0 -10.0 -so.o
COLLECTORVOLTAGE,
IVcl

CHARACTERISTICS VS COLLECTOR VOLTAGE

VARIATION OF "H" PARAMETERSWITH BIAS CONDITIONS

Figure 4.13

57
SMALL SIGNAL CHARACTERISTICS

Suppose, for example, the typical value of hobis required for the 2N525 at I., = 0.5 ma
and V., = 10 volts. From Figure 4.11 the typical value of hob at 1 ma and 5 volts is
0.6 X 10-0mhos. From Figure 4.13 the correction factor at 0.5 ma is 0.6 and the correc-
tion factor at 10 volts is 0. 75. Therefore,
hob(0.5 ma, 10 volts)= 0.6 X 10-0 X 0.6 X 0.75
(4aa)
= 0.27 X 10-0mhos.
Once the h parameters are known for the particular bias conditions and configuration
being used, the performance of the transistor in an amplifier circuit can be found for
any value of source or load impedance.
Figure 4.14 gives the equations for determining the input and output impedances,
current, voltage, and power gains of any black-box, including the transistor, when any
set of its four-pole parameters (z, y, a, h, or g) are known or have been calculated.

PROPERTIES
OF THE TERMINATED
FOUR-TERMINAL
NETWORK
z y h g a
1
ll +z 11z 1 Y22+Y\ /lh +hu Y\ 022+z1 a 11z\ +a 12
Zi
Zzz+ Z\ fl
1
+YnY\ h22+Yt t. 9 +ouzt G21Z\+022

t.1 +z~ Yn+Yg h11+z 9 6 9 +v22Y,a a22zv+a12

Zo flh +hzzZg
z 11+z 9 t.' +Y22Yu Vu+Yg a21zg+a11

~ ___:!!!.._ -hz1Z\ ~ _z_,_

Av 61 +zuzl Y22+Y\ h11+lfz1 V22+z1 a,2 +0i1z\

_z_21_ -yz,Yl ~ Q21

--- I
Ai z22+Z\ O+YnY\ h22+Y\ /:l+g11Z\ a22+a21z1

Figure 4.14

Let us work ari example using four-pole parameters to analyze the circuit shown in
Figure4.15.
-12V

OUT

(A) PRACTICAL
CIRCUIT (B) EQUIVALENT
CIRCUIT
Figure4.15
We will concern ourselves with the small signal gain and ignore the D.C. stability.
The black-box equivalent at signal frequency is shown in Figure 4.16.

58
 SMALL SIGNAL CHARACTERISTICS

R,

B-B'4to4

:E.
2NS25 2NS25
GROUNDED
EMITTER
5 VOLTS
@O.SMA.
GROUNDED
EMITTER
5 VOLTS
@O.SMA.
]•,•470
B-B*I B-B4t2 B-8#3

BLACK-BOXEQUIVALENTAT SIGNAL FREQUENCY

OF FIGURE 4.15
Figure4.16

B-B's 1, 2, and 3 are cascaded, so "a" parameters will be needed. We will first need to
derive the h parameters for the 2N525 which is used here under two different operating
points and two different configurations, common-emitter and common-collector. Values
obtained from Figures 4.11 and 4.13 can be tabulated as follows

TransistorType2N525 hu h12 1 + hn hn hn
OperatingConditions

CommonBase
Vc:= -5v, IE = 1 ma 31 5 X 10-' 0.022 -0.978 0.60 X 10-0

IE= 0.5 ma 31 X 2= 5 X 10-' 0.022 -0.974 0.60 X 10-0

62 X 0.92 = X 1.2= X 0.6=
4.6 X 10-' 0.026 0.36 X 10-0

CommonEmitter
Vc:= -5v, Is= 0.5 ma 2400 4.04 X 10-, 37.5 13.85 X 10-0

Vc:= -5v, IE = 5 ma 4.96 6 X 10-' 0.0176 -0.9824 2.4 X 10-e

CommonCollector
Vc:= -5v, IE = 5 ma 280 1 -56.8 136 X 10-0

The "boxed" operating conditions are those which apply to the circuit of Figure
4.15. Using the table in Figure 4.8, the corresponding "a" parameters are

OperatingConditions an 812 821 au

CommonEmitter
Vc:= -5v, Im= 0.5 ma -4.8 X 10-' -64 -3.69 X 10-1 -2.67 X 10-1

CommonCollector
Vc: = -Sv, Is = 5 ma 1 4.91 2.4 X 10 -o 17.6 X 10-a

59
SMALL SIGNAL CHARACTERISTICS

Combining B-B's 1, 2, and 3 of Figure 4.17 and neglecting B-B 4 (the feed-back
loop)

[
-4.8 X 10-',
-3.7 X 10-1,
-64 ] [l
-2.7 X 10-r X 1~-',
OJ [I,
1 X 2.4 X 10-e,
4.9]
17.6

When multiplying several matrices together, the method is to start at the right hand
side and multiply the last two matrices in the manner which has been described earlier
in this chapter. This gives one combined matrix representing the last two matrices.
This combination is then multiplied by the next matrix to the left and so on until the
whole product has been reduced to one final matrix combination.
After carrying out this procedure on the open-loop circuit, that is, no feed-back
applied (see Figure 4.16), the following "a" matrix is obtained
-70 X 10-', -11,400 X 10-']
[
-31.2 X 10- , 1
-4910 X 10-1

As a quick check on the arithmetic so far the voltage gain will be calculated for a load
of 4700 using the table in Figure 4.14.
470
11,400 X 10-, - 70 X lO~ X 47 0

-47,000 ~ -106
Av= 443 -

A negative value of voltage gain is expected since there is a total phase shift of 1r radians
over the whole circuit.
From knowledge of the "T" equivalent, a rough value for the gain can be deter-
mined. With a load of 4700, the emitter-follower stage has an input impedance of
approximately
hnc X Z1R:S 57 X 470 A:$ 27 K

This 27K in parallel with the lOK resistor forms the load of the first stage. The voltage
gain of the first stage is around
= 37.5 X 7.3 X 1<>3= 114
2.4 X 1<>3

To obtain the over-all voltage gain this figure has to be multiplied by the voltage trans-
fer of the emitter-follower which is very approximately h11b,The open-loop voltage
gain of the amplifier by this rough method is therefore about 114 X 0.98 = 112 which
differs by only a few percent from the figure arrived at with the matrix equation,
namely 106.
One might argue that this degree of accuracy was sufficient for the practical case
and why bother with matrices. However, when feed-back is applied the matrix method
offers a distinct advantage. Figure 4.17 shows this condition.

60
 SMALL SIGNAL CHARACTERISTICS

Rf

FEED-BACK

-- -
~

AMPLIFIER
-
- -
-

FEEDBACKBLACK-BOXSHOWN IN PARALLEL
WITH AMPLIFIER BLACK-BOX
Figure4.17

It is easily seen that the feed-back black-box is in parallel with the amplifier black-box.
The y parameters of each are therefore needed to effect a simple combination.
Using table 4.11, they parameters of the amplifier are obtained from the "a" param-
eters. They parameters for a series impedance (i.e., the feed-back resistor) are

[f!]
So, with Rrh equal to 10 KD, the total y matrix equals

-10-•J + [ 4.3X 10·\ 1

-1.05 X 10· ] =
10-• 0.877, 6.14 X 10-ll
5.3 X 10-•, -1 X 10-•J
[
0.877, 62.4 X 10-•
The voltage gain and the input and output impedances may be calculated with
reference to Figure 4.14. R., the signal source impedance in Figure 4.15 will be chosen
as lK. The equivalent circuit is shown in Figure 4.18.

e0 e
- -=Av - 0 -=G
eI '89

EQUIVALENTCIRCUIT OF FIGURE 4.17

Figure4.18
61
 SMALL SIGNAL CHARACTERISTICS

Figure 4.19 shows the variation of Av,Z1,Zufor three values of R,: oo•, !OK, and lK.

R. R, Av z. la
1 K!l oo* 106 2.3K 160 n
1 Kn !OK 105 son 1611
1 K!l lK 95 10.sn 2.711

OF Av, z., AND Zo FOR THREEVALUESOF R,

VARIATON
Figure4.19

*(In assigning an infinite value to R,, it must be assumed that bias for the first stage
of the practical amplifier is provided by an auxiliary means since this bias is ordinarily
available through the feed-back loop.)
As would be expected Av is affected by R, only as far as the feed-back loop loads
the output. Z1 and Zo are significantly affected though, and the reduction of Z1 with
R, affects G, the overall gain, since
G=~
1 + z.
R"

As mentioned previously the matrix parameters may be complex, i.e., frequency

dependent, as long as linearity with respect to current and voltage is maintained. The
y parameters and the h parameters are often used to analyze high frequency circuits.
Figure 4.20 provides useful design equations for this purpose.
With the exception of equation (4hh) all of the equations in Figure 4.20 are valid at
any frequency, provided that the values of the h parameters at that particular frequency
are used. At the higher frequencies h parameters become complex and the low fre-
quency h parameters are no longer valid. The matched power gain given by equation
(4ii) requires that both the input and the output of the amplifier stage be tuned, and the
input and output resistances be matched to the generator and load resistance respec-
tively. This situation is seldom met exactly in practice, but it is generally met closely
enough to permit accurate results from equation (4ii).
If the voltage feedback ratio, hr, is very small or is balanced out by external feed-
back the circuit is said to be unilateral. This means that no signal transmission can take
place from the output of the circuit to the input. Under these conditions the input
impedance of the circuit will be equal to h1 and the output impedance will be equal
to 1/hu, The power gain under matched, unilateral conditions is given by equation (4jj).
This power gain is a good figure of merit for the transistor since it is independent of
circuit conditions and transistor configuration. It represents the maximum power gain
that can be obtained from a transistor under conditions of absolute stability.

REFERENCE
• Shea, Richard F. et al, "Principles of Transistor Circuits," John Wiley & Sons, Inc. ( 1953)

62
 SMALL SIGNAL CHARACTERISTICS

INPUT IMPEDANCE (4bb)

MATCHED INPUT IMPEDANCE* Zim= Oi [D-jC] + Jbi (4cc)

io hfhr
OUTPUT ADMITTANCE Yo= e'; = ho - hi +ZQ (4dd)

MATCHED OUTPUT ADMITTANCE* (4ee)

i ht
CURRENT GAIN A·=~•--- (4ff)
1 ii l+hoZL

80 I
VOLTAGE GAIN (4gg)
Av=efs:h _.!!I_(l+hoZL)
r ZL hf
OPERATING POWER GAIN (LOW FREQUENCY ONLY, Zg:RQ,ZL•RL)

_ POWER INTO LOAD • ._ (~) (4hh}

G- POWER INTO TRANSISTOR AvA,-h _!!_ ( l+hoRL)
r RL ht
02f +b2f
MATCHED POWER GAIN * Gm • 1
( 4ii l
Oj0o~l+Df+C ]

MATCHED UNILATERAL POWER GAIN

(hr •O) (4j i)

Zg•RCJ+jXQ• OUTPUT IMPEDANCE OF GENERATOR

ZL • RL + IXL• IMPEDANCE OF LOAD

* FOR MATCHED CONDITIONS

Z1m=Rg-JX9
Zom•RL -jXL
hj•Oj+jbj
F = Or Of - br bf
hr =a,+ jb, OjOo

ht =at+ j bf
D = ✓1-F-C 2
ho=oo +jbo

TRANSISTOR CIRCUIT EQUATIONS WITH H-PARAMETERS

Figure 4.20

63
LARGE SIGNAL
CHARACTERISTICS ffi©
t:
cc
:::c
u

The large signal or d-c characteristics of junction transistors can be described in

many cases by the equations derived by Ebers and Moll. m These equations are useful
for predicting the behavior of transistors in bias circuits, switching circuits, choppers,
d-c amplifiers, etc. Some of the more useful equations are listed below for reference.
They apply with a high degree of accuracy to germanium alloy junction transistors
operated at low current and voltage levels, but are also useful for analyzing other
types of transistors.

PARAMETERS
The parameters used in the following large signal equations are listed below and
indicated in Figure 5.1.

Bu----------1-------~B
PARAMETERSUSED IN LARGE SIGNAL EQUATIONS
Figure5.1

lco lcso Collector leakage current with reverse voltage applied to the collector,
and the emitter open circuited ( Ico has a positive sign for NPN tran-
sistors and a negative sign for PNP transistors ) .
ho lt:eo Emitter leakage current with reverse voltage applied to the emitter,
and the collector open circuited ( IEo has a positive sign for NPN
transistors and a negative sign for PNP transistors).
Normal alpha, the d-c common base forward current transfer ratio
from emitter to collector with output short circuited ( a has a positive
sign for NPN transistors and PNP transistors ) . In practice, best results
are obtained if the collector junction has a few tenths of a volt reverse
bias. Since a is a function of emitter current, the value at that particular
value of emitter or collector current should be used in the large signal
equations.
Inverted alpha, same as ax but with emitter and collector interchanged.
Ohmic resistance internal to the transistor and in series with the base,
emitter, and collector leads respectively.

65
LARGE SIGNAL CHARACTERISTICS

Ia, IE, le D-C currents in the base, emitter, and collector leads respectively;
positive sense of current corresponds to current How into the terminals.
</Jc Bias voltage across collector junction, i.e., collector to base voltage
exclusive of ohmic drops ( across Re, Re); forward bias is considered
a positive polarity.
Bias voltage across emitter junction, i.e., emitter to base voltage exclu-
sive of ohmic drops ( across Re, RE) ; forward bias is considered a
positive polarity.
VF.a,Vee, VcE Terminal voltages: emitter to base, collector to base, and collector to
emitter respectively.
A=mKT 1/ A = 26 millivolts at 25°C form 1. =
q Electronic charge = 1.60 X 10-111coulomb.
K Boltzmann's constant= 1.38 X 10-23 watt sec/°C.
T Absolute temperature, degrees Kelvin= °C + 273.
m A constant of value between 1 and 2 ( m tends to be nearly 1 for
germanium transistors and varies between 1 and 2 for silicon tran-
sistors ) . <2 >

A can be determined from a semi-log plot of the junction forward characteristic

( the semi-log scale is used for the current, while the linear scale is used for the volt-
age). A portion of the plot will be linear, from which A can be determined

A --1 n (~)
.1.V (Sa)

where .:1V is the corresponding change in voltage for a .'11change in current on the
linear portion of the plot. For both silicon and germanium transistors, the best correla-
tion between theory and practice is obtained if the grounded base configuration is
used, and the other junction has a slight reverse bias.

BASIC EQUATIONS
The basic equations which govern the operation of transistors under all conditions
of junction bias are

aNho = a1Ico (Sb)

h=- I.:o (eA,/,E-1) + a1 lco (eM>c-1) (Sc)

1- CINCII l-a:sa1

as lxo (e.\i/1c -1)- lco (eAt/>c-1)

le=+ (5d)
l-a:sa1 l-a:sa1

It: + Ia + le =0 (5e)

The above equations are written for the direction of current flow shown in Figure 5.1
and the sign of I.:o and Ico as given above under Parameters. The three possible areas
of transistor operations are: 1) one junction forward biased and one junction reverse
biased (active), 2) both junctions forward biased (saturated), 3) both junctions
reverse biased (cutoff).

66
 LARGE SIGNAL CHARACTERISTICS

ACTIVE OPERATION
The transistor behaves as an active device if one junction is forward biased and
the other is reverse biased. Under normal operation, the collector is reverse biased so
f/>oin equations ( 5c) and ( 5d) is negative. If this bias exceeds a few tenths of a volt,
<<I,
eA(/,c and it can be eliminated from the equations. The collector current can then
be solved in terms of the leakage currents, current gains, and emitter-base potential,
thus giving the large signal behavior of the device.

SATURATEDOPERATION
The transistor can be operated in the normal ( grounded emitter) or the inverted
( grounded collector) connection as seen in Figure 5.2. The equations which are devel-
oped for each respective configuration will be labeled "normal" and "inverted." The
directions of base, collector, and emitter current respectively are taken as into the
transistor. Where a current flows out of the transistor, it is to be given a minus sign.
When a ( ± ) sign proceeds the equat:on, the plus applies to a PNP transistor while
the minus applies to an NPN transistor.

C E

!l
B B

(a) Normal (b) Inverted

THE NORMAL AND INVERTED CONNECTIONS
Figure 5.2

Under conditions of saturation and neglecting ohmic voltage drops, the voltage drop
between collector and emitter is given as
111 [ 1 _ .!:_~(1_-_a:-.---=-·)]
1 In a:-.
( Normal) Vet:= ( ± )T In--------- (5f)
[ 1 + {~-(1 - 111 ) ]

a.s [ 1 - ~ (1 - a.) ]
1
(Inverted) V t:c = (±) A In ----=--------In a, (5g)
[ 1+ ~: (1 - 11.s ) ]

67
LARGE SIGNAL CHARACTERISTICS

Notice that equation ( Sg) can be obtained from (Sf) by replacing le by I&, ciN by 111 in
the numerator, and 111by aN in the denominator. If the ratio of load current to base drive,
:: or :: , is very small, equations (Sf) and (5g) respectively reduce to

(Normal) VcE = (±) T1 In 111 (Sh)

(Inverted) VEe = (±) T1 In cix (Si)

The voltage given by (Sh) or (Si) is termed "offset voltage" and is an important
property in transistor chopper and other low level switching applications. Since ci,<ciN
for most transistors, the offset voltage of the inverted connection will be less than
that of the normal connection. The offset voltage c~n be made zero by forcing a current
to How from collector to emitter for a PNP transistor and from emitter to collector for
an NPN transistor.
The transistor in either mode of operation will remain saturated as long as the
bracketed terms in the numerator or denominator of equations (Sf) and ( Sg) remain
larger than one. Thus, the transistor behaves as a "closed switch," and the load current can
How through the transistor from collector to emitter or emitter to collector, depending
upon the polarity of the load supply. If either the numerator or denominator bracketed
term becomes zero, the log becomes infinite and the transistor comes out of saturation.
Since ci,<ciN, it can be seen from equations (Sf) and (5g), that both the normal and
inverted configurations will become unsaturated respectively at lower ratios of :: &
if the load current passes from collector to emitter in a PNP transistor and from emitter
t
to collector in an NPN transistor.
By differentiating equation (Sf) and ( Sg) respectively with respect to le and h,
1 4
the dynamic impedance of the saturated transistor can be found. If ( - N le ) and
CIN 111
(
1-
-a-,-a,) IE
hare muc h less than I, t hen

(Normal) _!_(
A
1- a1
le
CIN)
a1
( Sj)

( Inverted) _!_(l-a:1 CIN) (5k)

A Io aN

and (51)

Thus, the dynamic impedance is inversely proportional to the base current. Also, the
dynamic impedance of the inverted connection is larger than that of the normal con-
nection since c&N>a1. ( This is in contrast to the offset voltage where it is smaller for
the inverted mode than for the normal connection).
The body resistances RE and Re can be found by respectively plotting VcE and V Ee
as a function of In. The collector and emitter are respectively open-circuited, and the
voltage is measured with a high impedance millivoltmeter. At high values of base
current ( 1 ma and up for most signal transistors ) , VcE and VEe become linear functions

68
 LARGE SIGNAL CHARACTERISTICS

of Io. The slope of this linear portion of VcE gives RE while that of V Ee gives Re. This
technique applies only to alloy and grown transistors. For mesa and planar transistors,
the technique does not apply. The reason for this is that the collector junction overlaps
the base lead forming a forward biased diode between the collector and base contact.
This diode coupled with the le Re drop between the base contact and emitter edge
prevents the transistor from going hard into saturation. 141 For these transistors, RE and
Re cannot be found indirectly from external measurements. However, at lower base
currents ( where the internal resistance voltage drops are negligible) equations ( 5h)
and ( Si ) are valid for these transistors.

CUTOFF OPERATION
By reverse biasing both emitter and collector, equations (Sb), ( c), and ( d) can
be solved for the emitter and collector currents

(Normal) Ieo (1 - a,)

le= (Sm)
1-aNar

(Inverted) IEO(1- a.N) (Sn)

le:=
l-4N41

Equations ( Sm) and ( n) indicate that with both junctions reverse biased, the collector
current will be less than Ieo, and the emitter current will be less than IEo. Thus, for
switching circuits where low leakage currents are desired, the advantage of using the
inverted connection can readily be seen.

USEFUL LARGE SIGNAL RELATIONSHIPS

COLLECTOR LEAKAGE CURRENT (lc.:o)
For the direction of current How shown

f Iceo
-Vc?-O.I VOLT
I B =O lcEo=~ (So)
1-a.N

lcEo is the collector leakage current with the base open-circuited and is generally
much larger than lco,

COLLECTOR LEAKAGE CURRENT UcEs)

For the direction of current How shown

IcES
-VCE>-0.1 VOLT
IcEs = __l_co
__ (Sp)
1-aNaa

69
LARGE SIGNAL CHARACTERISTICS

leEs is the collector leakage current with the base shorted to the emitter and equals
the leakage current the collector diode would have if the emitter junction was not
present. Accurate values of aN and a1 for use in the equations in this section are best
obtained by measurement of lco, leEo and lezs and calculation of as and a1 from equa-
tions (So) and (Sp). The value of L:romay be calculated from equation ( 5b).

COLLECTORLEAKAGE CURRENT Ocr.a)

For direction of current flow shown

VcE>-O.1 VOLT
f IcER ler:n = (I + Alr.:oR)lco (Sq)
R
1- + ARLi:o{1-ciN)
aNci1

leEa is the collector leakage current measured with the emitter grounded and a resistor
R between base and ground. The size of the resistor is generally about 10 K. From
equation (Sq), it is seen that as R becomes very large, less approaches lezo-equation
(So). Similarly, as R approaches zero, lcEn approaches lezR-equation (Sp).

COLLECTORLEAKAGECURRENT- SILICON DIODE IN SERIES WITH EMITTER

For direction of current flow shown

t ~>-0.8VOLT

le= ( 1 + Alr.:oR- ci,AVu)loo

(Sr)
1 - aNar + ARIEO {1-aN)
R

This circuit is useful in some switching applications where a low collector leakage
current is required and a positive supply voltage is not available for reverse biasing
the base of the transistor. The diode voltage Vo used in the equation is measured at a
forward current equal to the lco of the transistor. This equation holds for values of le
larger than leo.
BASE INPUT CHARACTERISTICS

for le= 0

for Ve£> -.1 volt

Vac = lu (Ra+ Re ) +-1- ln [ le (1-aNcir) + 1 + aN (I-cir)] (St)

1 - aN A IBO(1-aN) a1(l-aN)

70
 LARGE SIGNAL CHARACTERISTICS

A comparison of equations ( 5s) and ( 5t) indicates that they are approximately
equal if REis small and ClN is smaller than a,. For this condition, the base input charac-
teristic will be the same whether the collector is reverse biased or open-circuited.

VOLTAGE COMPARATORCIRCUIT

for V.. =Ve.-

18 = [ + ( :: ) ( i =:;)]
~:c 1 (5u)

If an emitter follower is overdriven such that the base current exceeds the emitter
current, the emitter voltage can be made exactly equal to the collector voltage. For
example, if a square wave with an amplitude greater than Ve.- is applied to the base
of the transistor, the output voltage Vo will be a square wave exactly equal to V .....
Equation ( 5u) gives the base current required for this condition and indicates that the
transistor should be used in the inverted connection if the required base current is to
be minimized. This circuit is useful in voltage comparators and similar circuits where
a precise setting of voltage is necessary.

REFERENCES
cu Ebers, J.J., Moll, J.I., "Large - Signal Behavior of Junction Transistors," Proc. I.R.E., Vol. 42,
December, 1954.
(S> Pritchard, R.C., "Advances in the Understanding of the P-N Junction Triode,'' Proc. I.R.E., Vol.
46, June, 1958.
< Henkels, H.W., "Germanium and Silicon Rectifiers,'' Proc. I.R.E., Vol. 46, June, 1958.
31

m Rundenberg, H.G., "On the Effect of Base Resistance and Collector-to-Base Overlap on the Satura-
tion Voltages of Power Transistors," Proc. I.R.E., Vol. 46, pp. 1304-1305, June, 1958,

71
SWITCHING CHARACTERISTICS

An ideal switch is characterized by an infinite resistance when it is open, zero

resistance when it is closed, and an input by which it can be opened or closed. Tran-
sistors can be used as switches. The advantages which transistor switches offer over
mechanical switches are that there are no moving or wearing parts, they are easily
activated from various electrical inputs, and associated problems such as contact
bounce and arcing are essentially eliminated. The common emitter configuration is
most often used for transistor switching. The collector and emitter correspond to switch
contacts; base to emitter current performs the input function. Common emitter tran-

RATED DISSIPATION

Ic

l
E

COLLECTORCHARACTERISTICS
Figure6.1

sistor collector characteristics are shown in Figure 6.1 which illustrates a transistor in a
switching application. Near the operating point A, the transistor switch is in the open
or high resistance state. When In= 0, le= Ieo divided by 1-ci. Since 1 -ii is a small
number le may be several times greater than Ieo. A higher resistance may be achieved
by shorting the base to the emitter. Once the emitter junction is reverse biased by more
than .2 volts le approaches Ico. This achieves the highest resistance from collector to
emitter.
Operating point B corresponds to a closed switch. Ideally the voltage from collector
to emitter would be zero. In practice, however, there is always an appreciable voltage
across the transistor. The best switches are germanium alloy transistors such as the
2N525 which has about 1 ohm resistance when switched on. Germanium mesa tran-
sistors such as the 2N781 have a saturation resistance of 5 ohms or less. Silicon planar
epitaxial units such as the 2N2193A have about 1.2 ohms saturation resistance and
approach the performance of germanium alloy types. These values, however, are

73
SWITCHING C~CTERISTICS

dependent upon collector and base current levels and are normally specined as a
saturation voltage, VcE <BAT>,for given current levels. In order that a low resistance be
achieved, it is necessary that point B lie below the knee of the characteristic curves.
The region below the knee is referred to as the saturation region. Enough base current
must be supplied to ensure that this point is reached. It is also important that both
the on and off operating points lie in the region below the maximum rated dissipation to
avoid transistor destruction. It is permissible, however, to pass through the high dissi-
pation region very rapidly since peak dissipations of about one watt can be tolerated
for a few microseconds with a transistor rated at 150 mw. In calculating the Ia neces-
sary to reach point B, it is necessary to know how hn varies with le. Curves such as
Figure 6.2 are provided for switching transistors. Knowing hFE from the curve gives
Ia min since Ia min = hie . Generally Ia is made two or three times greater than Ia
FE
min

to allow for variations in hFE with temperature or aging and, as will be pointed out
later, to improve some of the transient characteristics. The maximum rated collector
voltage should never be exceeded since destructive heating may occur once a transistor
breaks down. Inductive loads can generate injurious voltage transients. These can be
avoided by connecting a diode across the inductance to absorb the transient as shown
in Figure 6.3.
Even with the diode connected, large peak power transients can occur unless the
transistor is switched off rapidly. If the transistor is switched off slowly, as soon as
the collector comes out of saturation the collector voltage will rise to the supply
voltage as the inductor attempts to maintain a constant current. At this instant, tran-
sistor dissipation is the product of supply voltage and maximum load current. Specinc
circuit components determine whether this dissipation is excessive.

lu•-IV'
Ta•2"C

IOO

--
--- ----
- -- --
/ r--- r-..
- ZNU7

;- ~
/'"
r--- r--- r--
ZNffl -
r---
Zll5ZS
-

111$14

~ -- ~ -
CCIUfflUI - ~
tcPIAI --- - -

D.C. BASE CURRENTGAIN(hn)

VS. COLLECTORCURRENT
Figure6.2
Lighted incandescent lamps have about 10 times their off resistance, consequently,
Ia must be increased appreciably to avoid overheating the switching transistor when
lighting a lamp.

74
 SWITCHING CHARACTERISTICS

A typical switching circuit is shown in Figure 6.4. The requirement is to switch a

200 ma current in a 25 volt circuit, delivering 5 watts to the load resistor. The
mechanical switch contacts are to carry a low current and be operated at a low voltage
to minimize arcing. The circuit shown uses a 2N525. The lK resistor from the base
to ground reduces the leakage current when the switch is open. Typical values are
indicated in Figure 6.4.

DIODE
IN36O5 FOR SMALL INDUCTANCE
IN91 FOR LARGE INDUCTANCE

DIODE USED TO PROTECTTRANSISTOR

FROM INDUCTIVE VOLTAGETRANSIENTS
Figure6.3

TYPICAL VALUES

125{i Ic :s 80~ A SWITCH OPEN

:Ic :s 0.2 A SWITCH CLOSED

J: 5 = IOmA • CURRENT THROUGH SWITCH

2N525 Vee = .19V SWITCH CLOSED

vbe = .48V SWITCH CLOSED

IN PUT POWER = 15 MILLIWATTS

LOAD POWER • 5 WATTS

TYPICAL TRANSISTORSWITCH APPLICATION

Figure 6.4

STEADY STATE CHARACTERISTICS

Four items - leakage current, current gain, dissipation, and saturation - which
have already been briefly mentioned, must be considered in determining the steady
state characteristics of switching transistors. At high junction temperatures, loo can
become a problem. In the off condition, both the emitter and collector junctions are
generally reverse-biased. As a rule, the bias source has an appreciable resistance per-
mitting a voltage to be developed across the resistance by Ico, The voltage can reduce
the reverse bias to a point where the base becomes forward biased and conduction

75
SWITCHING CHARACTERISTICS

occurs. Conduction can be avoided by reducing the bias source resistance, by increas-
ing the reverse bias voltage, or by reducing lco through a heat sink or a lower dissipa-
tion circuit design.
The lco of a transistor is generated in four ways. One component originates in
the semiconductor material in the base region of the transistor. At any temperature,
there are a number of interatomic energy bonds which will spontaneously break into
hole-electron pairs. If a voltage is applied, holes and electrons drift in opposite direc-
tions and can be seen as the lco current. If no voltage is present, the holes and electrons
eventually recombine. The number of bonds that will break can be predicted theo-
retically to double about every 10°C in germanium transistors and every 6°C in silicon.
Theory also indicates that the number of bonds broken will not depend on voltage over
a considerable voltage range. At low voltages, lco appears to decrease because the drift
field is too small to extract all hole-electron pairs before they recombine. At very high
voltages, breakdown occurs.
A second component of lco is generated at the surface of the transistor by surface
energy states. The energy levels established at the center of a semiconductor junction
cannot end abruptly at the surface. The laws of physics demand that the energy levels
adjust to compensate for the presence of the surface. By storing charges on the surface,
compensation is accomplished. These charges can generate an loo component; in fact,
in the processes designed to give the most stable lco, the surface energy levels con-
tribute much lco current. This current behaves much like the base region component
with respect to voltage and temperature changes. It is described as the surface
thermal component in Figure 6.5.
A third component of lco is generated at the surface of the transistor by leakage
across the junction. This component can be the result of impurities, moisture, or surface
imperfections. It behaves like a resistor in that it is relatively independent of tempera-
ture but varies markedly with voltage.
The fourth component of lco is generated in the collector depletion region. This
component is the result of hole-electron pair formation similar to that described as the
first Ico component. As the voltage across the collector junction is increased, the deple-
tion region will extend into the base and collector regions. The hole-electron pairs
generated in the base portion of the depletion region are accounted for by the first Ico
component discussed, but those generated in the collector portion of the depletion
region are not included. The number of pairs generated in the collector portion of the
depletion region and, thus, the Ico from this region depend on the volume of the
depletion region in the collector. Inasmuch as this volume is a function of collector
and base resistivity, of junction area, and of junction voltage, the fourth component
of lco is voltage dependent. In an alloy transistor, this component of loo is negligible
since the collector depletion layer extends only slightly into the collector region due to
the high base resistivity and low collector resistivity. In a mesa or planar structure
where the collector region is not too heavily doped the depletion region extends into
the collector, and this fourth Ico component may be appreciable. Since the mechanism
of lco generation here is hole-electron pair formation, this component will be tempera-
ture sensitive as well as voltage dependent.
Figure 6.5(A) shows the regions which contribute to the four components. Figure
6.5(B) illustrates how the components vary with voltage. It is seen that while there is
no way to measure the base region and surface energy state components separately,
a low voltage Ico consists almost entirely of these two components. Thus, the surface
leakage contribution to a high voltage Ico can be readily determined by subtracting
out the low voltage value of Ico, if the collector depletion layer contribution is small.

76
 SWITCHING CHARACTERISTICS

COU.[CTOII

•"HOU
O=£LECTRON
;::!! :INDICATES D4R[CTIQH CW
CARRIU DOIIFT

CROSS SECTION OF NPN PLANARPASSIVATED

TRANSISTORSHOWING REGIONS GENERATINGlco
(A)

NOT[;
CIJRVU A - IND4CAT£TH[ IIAU REGION I co
CURVESU-INOICATETH[ o,
11111 IIASl RE-
ANOSUR,Act THERMAL Ico
CUIIY£SC-INCWO( TIC SUIWact LEAKAGE
COMPONlNT
CURI/ES 0-IICLUCf: THE COLLECTOfl
CO'LETION REGION Ico
AND IIOICAT[ TH[ ll[ASUR[O l:co

BREAKDOWN
LOW VOLTAGE VOLTAGE
REGION REGION I
~ j.J
I
1 i~;t~~rg:
I
I
REGIONIco ----- _£..----/
,- B /
1
I SURFACE ;,-----------
I THERMAL
I co -- ____ A __ /
Ico " I
I
I I I I ( J
: ;' ,:✓ /
I
I
✓
I I
I
I ,,,,, I
1 I _s,_/ :
I .,,.
,,v.:_::_A~~~
..V/
SURFACE I 1/
,,,,-------- ,;,
,,,-r l.1 BASE I' -- - - - - - .Jl - ...,,",
_.J--- - - - __ .-, EGION .,----------,_,A
COLLECTOR VOLTAGE l:co COLLECTORVOLTAGE

VARIATION OF loo COMPONENTS VARIATIONOF lco COMPONENTS

WITH COLLECTORVOLTAGE WITH TEMPERATURE
(B) (C)
Figure6.5
Figur~ 6.5(C) shows the variation of Ico with temperature. Note that while the
surf ace thermal component, collector depletion region component and base component
of Ico have increased markedly, the surface leakage component is unchanged. For this
reason, as temperature is changed the high voltage Ico will change by a smaller per-
centage than the low voltage Ico.
Figure 6.6 shows the variation of loo with temperature and voltage for a number
of transistor types. Note that the curves for the 2N396 agree with the principles above
and show a leakage current less than one microampere.
The variation of current gain at high temperatures is also significant. Since hrm is
defined as le/Is, hn depends on Ico since le - h,. (Ia+ loo). If Ia= 0 i.e., if the base

77
SWITCHING CHARACTERISTICS

is open circuited, a collector current still Bows, le hr. Ico, Thus, hvF.is infinite when =
Is =0. As base current is applied, the ratio le/la becomes more meaningful. If hFE
is measured for a sufficiently low le, then at a high temperature h,.Ico will become
equal to Io. At this temperature hFmbecomes infinite since no Is is required to maintain
Io. The AC current gain h,., however, is relatively independent of Ico and generally
increases about 2: I from -55°C to +85°C. Figure 6.7 illustrates this fact.

I I I I I
-- ...
...
...
... n:-~= c,:::,

-~ i!=
I I I I I -'-
~::
1--
fOlllrdlJ2CDaaYI
C\e••IV "' z.-,u,.a,
... nPO~IBIIO
~Da:iiN
i-- tna NN.nD.QIIDl.lltat I

D
l
I ..
I
.... '
I/
'/
; v WQ••N.•IW.a•IOW =
I
-'""'~

·• ................
·~•e.c
.. 0

COLLECTORCUTOFF CURRENT TYPICAL lro VARIATION WITH

VS. TEMPERATURENORMALIZED TEMPERATURE
TO 25°C (INTERMEDIATEGRIDS (8)
ARE AT 2, 4, 6, 8)
(A)
...
...
...
- /~
Ir
Ji'.
V

r1/ ,---,

~
'I I
-,,rltl•t.MIT-

... l:l:\,1 k./,r/

·•
'
. I

I
I
I
I

. ,= //1. "'i~~
,

..
/'J I '/ ~
~I,'" / :
j //
)
V
/
-nl"IC-l4,z-
~•-·-•·
. /,I
I
1///
I

~
=~
·•.
... : //1
,'//
.
Jc .. 'lltCWUANll:I
,
,
........ ._.ne....,,.tl9Pl,n. I I
'fl
M
'I

1cm, VS. JUNCTION TEMPERATURE lr1111VS. TEMPERATURE

FOR 2N994 FOR 2N2192A,2N2194A,AND
(C) 2N2195A
{D)
Figure 6.6

78
 SWITCHING CHARACTERISTICS

The different electrical properties of the base, emitter, and collector regions tend
to disappear at high temperatures with the result that transistor action ceases. This
temperature usually exceeds 85°C and 150°C in germanium and silicon transistors,
respectively.
When a transistor is used at high junction temperatures, it is possible for regenera-
tive heating to occur which will result in thermal run-away and possible destruction of
the transistor. For the maximum overall reliability, circuits should be designed to pre-
clude the possibility of thermal run-away under the worst operating conditions. The
subject of thermal run-away is discussed in detail in Chapter 7.
A major problem encountered in the operation of transistors at low temperatures is
the reduction in both the a-c and d-c current gain. Figure 6.7 shows the variation of
h.-F.with temperature for the 2N525 and indicates that at -50°C the value of hFE
drops to about 65% of its value at 25°C. Most germanium and silicon transistors show
approximately this variation of h••e and h,. with temperature. In the design of switch-
ing circuits the decrease of h.-e and the increase of VBE at the lower temperatures must
be taken into account to guarantee reliable circuit operation.
2.0

1.0
I
I.I
V I/
V
u
: 14
/ /
~V
,/
/"
-7"
--
-------
~
h~
i--- V'
~
L-- ht,

04

02

0
-50 -30 -10 +10 +30 +50 +70 +90
JUNCTIOHTEMPERATURE (•ti

CURRENT GAIN VS. TEMPERATURE

NORMALIZEDTO 25°C
Figure6.7

As with most electrical components, the transistor•s range of operating conditions

is limited by its power dissipation capabilities.
Because the transistor is capable of a very low VoE when it is in saturation it is
possible to use load lines which exceed the maximum rated dissipation during the
switching transient, but do not exceed it in the steady state. Such load lines can be
used safely if the junction temperature does not rise to the runaway temperature
during the switching transient. H the transient is faster than the thermal time constant
of the junction, the transistor case may be considered to be an infinite heatsink. The
junction temperature rise can then be calculated on the basis of the infinite heatsink

79
 SWITCfilNG CHARACTERISTICS

derating factor. Since the thermal mass of the junctions is not considered, the calcula-
tion is conservative.
In some applications there may be a transient over-voltage applied to transistors
when power is turned on or when circuit failure occurs. If the transistor is manufactured
to high reliability standards, the maximum voltages may be exceeded provided the
dissipation is kept within specifications. While quality alloy transistors and grown
junction transistors can tolerate operation in the breakdown region, low quality alloy
transistors with irregular junctions should not be used above the maximum voltage
ratings. Many mesa and planar transistors exhibit negative resistance after breakdown.
Precautions should be taken to avoid this region or limit dissipation.
Quality transistors can withstand much abuse. 2N396 transistors in an avalanche
mode oscillator have been operated at peak currents of one ampere. 2N914 transistors
in the avalanche mode have generated an 8 ampere pulse with no apparent degradation.
Standard production units however should be operated within ratings to ensure con-
sistent circuit performance and long life.
It is generally desirable to heatsink a transistor to lower its junction temperature
since life expectancy as well as performance decreases at high temperatures. Heat
sinks also minimize thermal fatigue problems, if any exist.

•160
IWLLECTORDISSIPATION
IOOmwl!I0mw
\ COMMON
EMITTERCOLLECTOR CHARACTERISTICS
-140 FOR A TYPICALUNIT t-- r--
\Ie•-3.0ma _/
\ TYPE 2N396
~w -120 \L 1•••••f''"ra•-2.5ma i.--- TA=25•C

I::; I~ \ 1.....+--1
l.,..,l,..
Ie•-2.0mo ..-
i -JOO ~

~ f-1"
i- i--

u ..... \
\ r 8 • -l.5ma
,__.......
~ -80
w
a:
~~ ~- i- i--

i---
\ ,._ 1--

--- ----
a: 18 °-1.oma i-- ,._~
a -eo I\
,---
~ ~ ~-OBma_ i-- i--

~ -40
~
~ .... ,i,,. 1 8 •-0.6mo
I--

....... le •-0.4ma
--
8 -....- --
-
,.
.....,_
1 ....

le •-0.2ma
--
-20
r- -
---- I

0 -I -2 -3 -4 -5 -6 -7 -8 -9 -10 -II -12

COI.LECTORVOLTAGE,VcE (VOLTS)

Figure6.B(A)

A transistor is said to be in saturation when both junctions are forward biased.

Looking at the common emitter collector characteristics shown in Figure 6.B(A) the
saturation region is approximately the region below the knee of the curves, since hrz
usually falls rapidly when the collector is forward biased. Since all the characteristic
curves tend to become superimposed in the saturation region, the slope of the curves
is called the saturation resistance. If the transistor is unsymmetrical electrically-
and most transistors are unsymmetrical - then the characteristics will not be directed
towards the zero coordinates but will be displaced a few millivolts from zero. For ease
of measurement, generally the characteristics are assumed to converge on zero so that
. res1s
th e saturation ·tan ce IS
. re&<sAT> -V--le . = CB(SAT)

80
 SWITCHING CHARACTERISTICS

-200
___..,,... ----
--
-180
TYPICALCOLLECTOR
SATURATIONCHARACTERISTICS J.-1
TYPE 2N396 / a•-IOmo
-160
,..v
/
; -140
,/
w_,

-- --
V
/
-120

~ /
.!'
...
i
-100
/
/

_J"v
Ie•-Sma
_J"i..---
--
-80
,I
,,/ ,../ ---
----
I 8 •-3l'IICI

-- ---
~ -60
V v .,.,...
i..---~
V /., r8 • -2ma
8 -40
/
...
v ,,,.,.1-"" TA•2S'C

/_,,, V la•-lrna

'--
.......
~

/,/_,,

-
/L,1-'"'"
-20
,t % ;...--
0
~:::::::.
~

-----
o -20 -40 -60 -80 -100 -l20 -140 -160 -180 -200 -220 -240 -260 -280
COLLECTORVOLTAGE.\t[ (MILLIVOLTS)

Figure 6.8(8)

While the characteristic curves appear superimposed, an expanded scale shows

that VcE111AT1 depends on h for any given le. The greater le is made, the lower VcE<BAT>
becomes until le is so large that it develops an appreciable voltage across the ohmic
emitter resistance and in this way increases VcE<sAT>• In most cases the saturation
voltage, VcE<sAT>, is specified rather than the saturation resistance. Figure 6.8(B) show-
ing the collector characteristics in the saturation region, illustrates the small voltage
off-set due to asymmetry and the dependence of res 111AT> on le. Note also that rcE<SAT>
is a low resistance to both AC and DC.
In accordance with theory the collector saturation voltage, VcE<sAT>, decreases
linearly with temperature for most transistors. In the case of alloy transistors, this is a
result of the increase of Ico with temperature which increases the effective base charge
at high temperatures. However, transistors which have an appreciable ohmic resistance
in series with the collector or silicon transistors which have a low lco, generally exhibit
a positive temperature coefficient for VcE<sAT>-
The base to emitter voltage, VBE,has a negative temperature coefficient which is
about 2.0 millivolts per degree Centrigrade for both silicon and germanium transistors.
Figure 7.1 shows the emitter to base characteristics of the 2N525 at several different
temperatures. The series base resistance and emitter resistance (rb', r.') have a positive
temperature coefficient so that the m drops across these resistances can offset the
normal variation of VH at high values of base current.
The increase in Yes 111AT1 and the decrease in VeE at high temperatures can lead to
instability in DCTL circuits such as shown in Figure 6.21 and result in operation closer
to saturation in circuits such as those shown in Figure 6.23.

TRANSIENT RESPONSECHARACTERISTICS
The speed with which a transistor switch responds to an input signal depends on
the load impedance, the gain expected from the transistor, the operating conditions
just prior to application of the input signal, as well as on the transistor's inherent
characteristics.

81
SWITCHING CHARACTERISTICS

(a) TYPICAL CIRCUIT

I 81 r 82 =o.sma
11

Ic1:1 10 ma
Ir/ < hFE
7Ie1

I
I I
I I

::~~--------+
I
I
:•
I
I
1 ;'
( b)

(c)
WAVEFORM GENERATED
AT A BY SWITCH

WAVEFORMAT 8
SHOWINGFORWARDBIAS
-10v1 ---------+--i- : , ' ON BASE DURING
:
I
: I:
. I I
--- SATURATION

+IOV I l :: ( d) COLLECTOR WAVEFORM

---- - ---~-~ ---10%
I I• SHOWINGSTANDARD
1 DEFINITIONS OF
+lfd -------~- t·--·90%
ov--~+ J.: ______
I
- -'-"·-- RESPONSE Tl MES
' I I I I
1+1trl+- -+1 t5 j41
I I I •~tf+-
----+ TIME

TRANSIENT RESPONSE
Figure6.9
Consider the simple circuit of Figure 6.9(A). Closing and opening the switch
to generate a pulse as shown in Figure 6.9(B), gives the other waveforms shown. When
the switch closes, current Hows through the 20K resistor to turn on the transistor. How-
ever there is a delay before collector current can begin to How since the 20K must
discharge the emitter capacitance which was charged to -10 volts prior to closing
the switch. Also, the collector capacitance which was charged to -20 volts prior to
closing the switch must be discharged to -10 volts.
Time must also be allowed for the emitter current to diffuse across the base region.
A third factor adding to the delay time is the fact that at low emitter current densities
current gain and frequency response decrease. The total delay from all causes is called
the "delay time" and is measured conventionally from the beginning of the input pulse
to the 10% point on the collector waveform as shown in Figure 6.9(0). Delay time
can be decreased by reducing the off bias voltage, and by reducing the base drive
resistor in order to reduce the charging time constant. At high emitter current densities,
delay time becomes negligible. Figure 6.10 shows typical delay times for the 2N396
transistor.

82
 SWITCHING CHARACTERISTICS

PNP ALLOY TRANSISTOR TYPE 2N396

PULSE RESPONSEDELAYTIME
----------. td (1&S)VS Ie1 (mo)
Yee• - sv
Ic • - 5ma
RL • IKn
Re a 10 Kil

-2.5V

00~--_,......----_,..,,._o---_......,L5----...J2.L..o---_2.-'-s----_.30
Ie1 (ma)

Figure6.10
1.4
PNP ALLOY TRANSISTOR TYPE 2N396
.2 \ PULSE RESPONSE RISE TIME

.o \ tr (,iS) VS Ie 1 (ma}
Vee· 5V

-
-~ \ le a
RL a
R9 •
5mo
IKQ
10 KQ
,.
!: 0 .. \'
Q4 ~
~
0 .2
I"'---...
--~
-
"') -0.5 -1.0 -1.5 -2.0 -2.5
I91 - ma

Figure6.11(A)

The "rise time" refers to the tum-on of collector current. By basing the definition of
rise time on current rather than voltage it becomes the same for NPN and PNP tran-
sistors. The collector voltage change may be of either polarity depending on the tran-
sistor type. However, since the voltage across the collector load resistor is a measure
of collector current, it is customary to discuss the response time in terms of the collector
voltage. If all other circuit parameters are kept constant, the rise time will decrease
as the drive current is increased as shown in Figure 6.ll(A). Tum-on time (delay time
plus rise time) is shown for the 2N994, a germanium epitaxial mesa in Figure 6.ll(B).

83
SWITCHING CHARACTERISTICS

Storage time is the delay a transistor exhibits before its collector current starts to
tum off. In Figure 6.9, Ru and RL are chosen so that RL rather than hFE will limit the
collector current. The front edge of the collector waveform, Figure 6.9(0), shows the
delay time, td, followed by the nearly linear rise time, tr. When the collector voltage
falls below the base voltage, the base to collector diode becomes forward biased with
the result that the collector begins emitting. By definition, the transistor is said to be
in saturation when this occurs. This condition results in a stored charge of carriers in
the base region and in some cases in the collector region.
Since the flow of current is controlled by the carrier distribution in the base, it is
impossible to decrease the collector current until the stored carriers are removed.
When the switch is open in Figure 6.9, the voltage at A drops immediately to -10
volts. The base voltage at B however cannot go negative since the transistor is kept on
by the stored carriers. The resulting voltage across Ra causes the carriers to flow out .of
the base to produce a current lu2. As soon as the stored carriers are swept out, the
transistor starts to turn off with the base voltage dropping to -10 volts and the base
current decreasing to zero. The higher Ia1 is, the greater the stored charge; the higher
lu2 is, the faster charge is swept out. Figure 6.12 shows the dependence of storage
time on lu1 and Ia2 for the 2N396 transistor.

30 VeE (OFF) =4 VOLTS

PNP EPITAXIAL MESA
TRANSISTORTYPE 2N994
0
LL.I
ton-VS BASECURRENT
(I)
C 20 DRIVE
I

~
C
@) Ic =20ma

10
Vcc=5VOLTS

0.1 2 5 10 20
I (MA)
81

tos VS. BASE CURRENTDRIVE

FOR 2N994
Figure6.11(B)

The "fall time," tr, of a transistor is analogous to the rise time in that the transistor
traverses the active region during this time. As normally defined, fall time is the time
for the transistor to switch from 90% ON to 10% ON as shown in Figure 6.9(0).
Figure 6.13(A) shows typical fall time measurements for a 2N396. Turn off time (stor-
age plus fall time) for the 2N994 is shown in Figure 6.13(B).

84
 SWITCHING CHARACTERISTICS

192 mo
PNP TRANSISTOR TYPE 2N396
.2 5

Vee• - 5V
1.4 Ie • - 5mo
RL • = I Ktl
1.2 Re " I0Ktl

-0.5 -1.0 -1.5

I91 - mo
Figure6.12
1.0
PNP ALLOY TRANSISTOR TYPE 2N396
0.9 PULSE RESPONSE FALL TIME
Vee=-sv
Ic = -5mo tf (µ.S) VS Ie1 (mo)
0.8 • RL = IKil
Re= IOKn I (mo)

---
82
0.7 .25

0.6 ~
~
/
in
:t.

-
- 0.5

0.4
.50
0.3
.75
02
1.0

0.1

-0.5 -1.0 -1.5 -2.0 -2.5

Ie1 (ma)

Figure6.13(A)

85
SWITCHING CHARACTERISTICS

30 .---....----------..-----..-------,

PNP EPITAXIAL MESA

TRANSISTOR TYPE 2N994
Vee:::
-5.0VOLTS
Iec20ma
~ 2.0 t----'~-R....;;e;,-:::_1_1<--.----.-------t
'fl)

g
fl)
t)

I
fl)

~
I 10 ~-I------I-.J,,..----1-..:JJ4C..----;;.;;.__ ___ ~
_o =

5 10 2.0 100

Figure 6.13 (B)

TRANSIENT RESPONSEPREDICTION
A number of methods exist which enable one to predict the speed of response of
a given transistor in a given circuit. Three fundamental methods are: the equivalent
circuit approach, charge control analysis, and the diffusion equation solution. The
equivalent circuit method normally uses the equivalent circuits shown in Figure 6.14.
NPN polarity is used in the circuits.

DELAYTIME
EQUIVALENTCIRCUIT
(A)

E 1• ON DRIVE
E • 0FF BIAS
2
NOTE:
Ccb AND Cob ARE
NON-LIH£AR JUNCTION
CAPACITANCES

E t-----~ ....... 'V'\.4'"""1~.-0 C RISE AND FALL TIME

EQUIVALENTCIRCUIT
--+l:E
(B)

TRANSISTOREQUIVALENTCIRCUITS
Figure 6.14
B

86
 SWITCHING CHARACTERISTICS

The an, the common base current gain at a frequency f, is defined as

Ct?(
etn=---f- (6a)
1 +j-
fa
where ax = low frequency common-base current gain
fa= alpha cutoff frequency
Since both junctions are forward biased during storage time, the inverse character-
istics of the transistor are involved in storage prediction. The inverse characteristics
are obtained by interchanging the coUector and emitter connections in any test circuit.
They are identified by the subscript I foUowing the parameter, e.g .• hvE1is the inverse
DC beta. In the equivalent circuit approach, the. storage time is analyzed by consider-
ing both junctions as emitting junctions. The common base current gain in the normal
condition is given in equation (6a). In the inverse mode of operation,

(6b)

where
a1 = low frequency inverse common base current gain.
fa1= inverse a cutoff frequency.
Using equivalent circuits, the storage time is defined as the time required for the
collector to become back-biased - i.e., to stop emitting. As will be shown shortly, this
is also the same as requiring that excess base charge be removed.
From the equivalent circuit, the transient times can be approximated. For delay
time, the effects of the collector capacitance can be neglected if Eco is much greater
than E:1.If E1 and R (in Figure 6.14(A)) approximate a current source, then
td= c.bCE.)x E:1 (6c)
IRt

C.b (E2) is the average effective capacitance of the emitter junction between E2
volts reverse bias and the forward biased condition. A method of approximating this
capacitance will be discussed later in this section in conjunction with the charge
control parameters. In the following graphs results of the equivalent circuit approach
are shown for the common emitter configuration. Figure 6.15 gives the rise time
information.

SYMBOLS DEFINED IN FIGURE 6.9 ANO 6.14

THE INTERCEPT OF Ic ANO THE CURVE GIVES t,

f ----~~,1--------------------
hFE Ie1

I, , I +2irf 0 RLCco \n ~
2•1a 11-a,.1 hrc Iei-Ics
/
a:
Ic
~ ,. " Ier 2,r la IF' 2r la RL c,. <<I ANO hiccIea > 3Ics
u
w
.J

8
tr h FE/2'D'fa TIME ----+
GRAPHICALANALYSIS OF RISE TIME
Figure6.15

87
SWITCHING CHARACTERISTICS

If the load resistor Rt in Figure 6.9(a) is small enough that a current hn ls1,
through it will not drive the transistor into saturation, the collector current will rise
exponentially to hvEls1with a time constant, hve/2irfa, However, if Rt limits the cur-
rent to less than hvEle1the same exponential response will apply, except that the curve
will be terminated at lcs = VRt cc , the saturation current. Figure 6.15 illustrates the case

for lcs A:$ hnle1/2. Note that the waveform will no longer appear exponential but
rather almost linear. This curve can be used to demonstrate the roles of the circuit
and the transistor in determining rise time. For a given transistor it is seen that increas-
ing hvEIBt/lc will decrease rise time by having le intersect the curve closer to the
origin. Since the approximate equation assumes that hn and fa are the same for all
operating points and that the collector capacitance effects are negligible, the calcu-
lated results will not fit experimental data where these assumptions are invalid. Figure
6.ll(A) showed that the rise time halves as the drive current doubles, just as the
expression for tr suggests, since in this case capacitance effects were small; however,
the calculated value for tr using the approximate expression is in error by more than
50%. This shows that even though the calculations may be in error, if the response
time is specified for a circuit, it is possible to judge fairly accurately how it will change
with circuit modifications using the above equations.
Collector current fall time can be analyzed in much the same manner as rise time.
Figure 6.16 indicates the exponential curve of amplitude Io + hnle2, and a time con-
stant, hv1d271'fa,
Fall time is given by the time it takes the exponential to reach lcs,
THE INTERCEPTOF Ic ANO THE CURVE GIVES t f·

Ie2 hFE + 1 c
------~--------------------
,,
f I
I
I
/ I EXPONENTIALCURVE

TIME_,.

1+211fa RL Ccb \n hFE Ie2+Ics

211 fa (I- aN) hFc Ie2

hFE Ics
ft Q: -- -------------- IF 271fa RL Ccb<< I ANDhFEie2>3Ics
27Tfa hFEie2+Ics
GRAPHICALANALYSIS OF FALL TIME
Figure6.16
In the approximate expression in Figure 6.16, tr will be approximately equal to
_l_ X 108 if hn is very large compared to Ics/Ie,.
2,rfa l01
Figure 6.17 shows a curve which is useful for calculating storage time graphically.
The maximum value is hvE (101+ Ie2),where Ia2 is given the same sign as IBl, ignoring

88
 SWITCHING CHARACTERISTICS

the fact it flows in the opposite direction. The time constant of the curve involves the
forward and inverse current gain and frequency cut-off. The storage time corresponds
to the time required to reach the current hFEla1-le. It can be seen that for a given
frequency response, high hFE gives long storage time. The storage time also decreases

______
as l02 is increased or Is, is decreased.
?:'___________________ _
h FE (I91 + 102>

l~
._
z
hFElal-lc

+-
/
/ I

THE INTERCEPT OF ( hFE

AND THE CURVE GIVES
Ie, -
ts·
Ic)

ILi
IX
IX
::,
u

GRAPHICALANALYSIS OF STORAGETIME
Figure6.17

The time constant for a very unsymmetrical transistor is approximately hvt:;t 1 . It is

2 GI

seen that the generally specified normal hvE and fa are of little use in determining
storage time. For a symmetrical transistor, the time constant is approximately
t
hvE 1 . It is possible for a symmetrical transistor to have a longer storage time than
27"a
an unsymmetrical transistor with the same hvE and fa,
Using the charge control approach, the transistor is viewed from a more funda-
mental vantage point. The actual charge requirements of various regions within the
device are determined, and the transient times are found by calculating the time
required to supply the various charge components. The emitter and collector junctions
of a transistor when in the cutoff condition are reversed biased; in this condition only
leakage currents flow across the junctions, the base charge is negligible and the junc-
tion depletion layers are wide because of the reverse bias applied as shown in Figure
6.18(A). In Figure 6.9(A), this condition exists in the transistor when the switch is
open; VnE is equal to -10 volts and Vcs is equal to 20 volts. Immediately after the
switch is closed, no collector current flows since the emitter junction is reverse biased,
thus the initial base current which flows supplies charge to the emitter and collector
junction depletion layers and soon causes the emitter junction to become forward
biased and begin emitting as shown in Figure 6.18(B). The quantity of charge which
has been supplied to the emitter junction depletion region is called QE and is a func-
tion of the reverse bias voltage which was applied to the junction prior to the appli-
cation of the turn-on signal. The charge supplied to the collector depletion region
during this time is denoted Qco and is a function of the reverse bias on the emitter,

89
SWITCHINGCHARACTERISTICS

and the collector supply voltage being switched. Looking again at Figure 6.9(A), the
condition illustrated in Figure 6.18(B) exists when VBr:equals about .3 volts and Vee
equals about 10 volts.
With the emitter junction now forward biased, the transistor enters the active
region. Collector current begins to flow and the voltage at the collector begins to drop
because of the presence of the collector load resistor, RL, shown in Figure 6.9(A).
During this time a gradient of charge is established in the base region of the tran-
sistor. The slope of this charge gradient is proportional to the collector current which
is flowing. If the base current supplied is greater than the rate of recombination of
charge in the base region, the gradient will continue to rise until an equilibrium
condition is reached. If equilibrium is reached before the collector junction is for-
ward biased, the transistor will not saturate. Since the recombination rate of charge
in the base is Ic/hFe (or 1B1),the collector current will rise to hFE Ie1 if the device
does not saturate. If, on the other hand, the collector current causes the collector-base
junction to become forward biased before equilibrium is reached, the device will
saturate. The existing condition within the transistor at the edge of saturation is
depicted in Figure 6.18(C). The time required to move from the edge of cutoff to the
DIITTDI I j._C:Ol.L[CTOA
.AIHCTIOII-, I JUl«:TION

I I
EMITTER
BAK
I
I
.....-c:oLLtcTOII
I

I RJ JR I 0£PLETION REGIONS

(A) TRANSISTORCUTOFF-WIDE DEPLETION REGIONS

I
I

I I
10,-PLIED :
Oco IU't'LIEDI

I IIAIIROWD£PL£TIDN R£CIIOIIS l
( B) EDGEOF CUTOFFCONDITION
I I
I Oc SUPPUEDI

! IIAIIRDW0£PL£TIDN lltGIDNS I
(C) EDGE OF SATURATIONCONDITION
I I
I I

lliNill I
(D) TRANSISTORSATURATED
l

CHARGE DISTRIBUTION IN TRANSISTOR DURING SWITCHING

Figure6.18

90
 SWITCIDNG CHARACTERISTICS

edge of saturation is the rise time. Charge quantities involved are the base gradient of
charge Qa, which is a function of collector current Bowing, and Qc, which is a function
of Vce. Qc is the charge required to cause the collector junction to narrow and becomes
forward biased. Since measurement of Qe and Qc is frequently accomplished by
measuring the two quantities together and then separating them as shown in Chapter
15, the sum of Qs and Qc is frequently used and is called Qn*. At the edge of satura-
tion the V BE is about .3 volt and V ca is O volts if the bulk resistance of the collector
body is neglected. Since equilibrium is not established with respect to the base current,
charge in excess to that required to saturate the transistor is introduced into the base
region. The base gradient of charge remains constant since the collector current is at a
maximum for the circuit; the excess charge, Qax, is a function of the current which is
permitted to How into the base in excess of that required to saturate the transistor.
This current is called lex. Distribution of Qax in the transistor is shown in Figure
6.18(D).
In the alloy type transistor, essentially all of the stored charge is in the base region.
In devices where the collector bulk region has high minority carrier lifetime, excess
carriers can also be stored in the collector. These carriers reach the collector from the
base since the collector junction is now forward biased and base majority carriers are
free to flow into the collector region during saturation. These stored carriers have no
effect in tum-on time. Storage time, however, is the time required to remove these
stored carriers as well as those stored in the base. Both the mesa a~d planar devices
exhibit collector minority carrier storage. The epitaxial process used in General Electric
transistors 2N781, 2N914, 2N994 and the 2N2193 minimizes collector storage while
not adversely effecting collector breakdown voltage or other desirable characteristics
of the transistor. Incidentally, it may be possible to meet the electrical specification of
a given registration without using epitaxial techniques. Component manufacturer's
data should be consulted for process information.
From the various charge quantities introduced, a number of time constants can be
described that relate the charge quantities to the currents flowing; these time constants
are defined in equations (6d).

Ta=~
les

Tr=..2! (6d)
lcs

Tb=-2!!
lax

Ta is called the active region lifetime, T., is called the collector time constant, and
Tb is the effective lifetime in the saturated region. In some literature Tb has been called
T • , Where collector minority carrier storage exists the measurement method for Tb

shown in Chapter 15 does not only measure Qax/IBXbut includes much of the collec-
tor stored charge; as such, this parameter is still a valuable tool in rating the storage
characteristics of various transistors since a low Tb value indicates a low storage time.
The time constants defined are constant over large regions of device usage and are
normally specified as device constants.
To determine the transient response using the charge approach, the required charge
for the time in question is divided by the current available to supply that charge; thus,
the basic equations are as given in Equation (6e).

91
SWITCHING CHARACT£RISTICS

tc1=OE+ Oco
101
tr Oe± Oc Te I.,+ Oe
101 le1 (Be)
t. =.9.!!.,
l02
= lex
les
Tb

tr = Oe ± Oc= le +Oc Tc
le:1 le,
The simplicity of these equations is readily seen. Their accuracy is dependent upon
the assumption made in the equations that l01 and 101truly are constant. Refinements
in these equations arise from the fact that some of the charge in the base recombines
on its own and must be accounted for in determining transient speed. These refine-
ments are seen primarily in equations (6£) for rise and fall time.
tr= Oe± Oc
101- .5 les (6£)
tr= Oe± Oc
Ie1 + .5 la11
Equations (6e) and (6f) assume that the current Ie1 is sufficient to drive the tran-
sistor well into saturation. If 101is three times greater than les, these equations are
valid. For the cases where the drive-on is not large compared to les, but nevertheless
is greater than les, equations (6g) are more accurate expressions.
t. RL Oc]In (
=[TA+ hFF. ln1 )
Vee l01 - las
t. = Tb In l01 ± Ie2 (6g)
+
Ie2 Ies
tr =[TA+hFERL Oo]In (Ie2 + le 11
)
Vee 102
The lack of simplicity of these equations is also readily seen. If the drive-on current
is not sufficient to drive the transistor into saturation the collector current will rise to
h,.£ Ie with a time constant slightly greater than Ta as shown in (6g). Fall time is also
determined by using the time constant of the tr expression in (6g), but the magnitude
attempts to reach hn Ie:1in the reverse direction before it is interrupted at le= 0. Thus,
the tum-off time from the non-saturated state is
tr= [Ta
+hvE RLOc]In (102 + let)
Vee Ie2
The charge control parameters as they appear on the 2N396A alloy device are
shown in Figure 6.19(A). On the specification, transient times are defined from 10% to
90% points to make their measurements easier as shown in Figure 6.9(0). This defini-
tion, however, demands that the equations be slightly modified to accommodate these
new definitions of transient times. The modified form is shown in Figure 6.19(A) with
the 2N396A specification. Figure 6.19(B) shows the charge graphs for the 2N994.
Frequently, it is convenient to know some of the relationships between charge
control parameters and small signal parameters. Convenient approximate interrelation-
ships are shown in equations (6h).

Qe = le Ta
= le • ;;;a
_ _ 1 1
Qe - le Tc - le • 21rfaor I., • 21rfT (6h)

!.!.
Tc
= hP'E

92
 SWITCHING CHARACTERISTICS

4000
/ 0990 (MAX}
3000
/ 0 890 (TYPI
2000
/ / 0111001
1000 /
/ /
~
/ 0s,o1MAX.l 400

800
/ / /
600
/ V ,Iv 200
j

1200
400

V
/ V
l/
v/
/
/ .,
"'
:I! 100
TYPICAL

~
--;, 100
O 80
60
/
/
/
/
/
/
/
/

0 e VERSUS Ics -
i
~
~
eo
60

40
0c100VERSUS VcE INOTE I

/ V u
/ 0

v//
~
40

20
20
V
4 6 810 20 40 60 80100 • e a 10 20
VcclVOLTSI
I cs (MILLIAMPERES)
2N396A
SPECIFICATION TA• 25° Cl
••• ACTIVE REGIONLIFETIME
MIN.
I.I
TYP. MAX.
I.B ,.,
'b• SATURATED REGIONLIFETIME .65 1.2 ,..
CB[,AVERAGE EMITTER JUNCTION CAPACITANCE 12 17 pl

Id • VeE (OFF) cii£ + 1/9 X 0990 +Oc,o t, • 8/9 X Oe,o + Oc,o Ie1+I12)
Ie1 I 8, -.SI 85 Ia, -.Sies
la••b 1,,( --- +
Ies+I12

(Oe100-009ol+(oc,oo-Oa9ol • x Oe,o +oc,o

11 819
+ Iaz+.5Ias + Iaz+.5Ies

NOTE: Oc90 • Oc,oo AT Vet MINUS Oc100 AT .I Vet AS ILLUSTRATED FOR Vet •

20 VOLTS IN THE Oc,oo vs. VcE PLOT.

2N396A SWITCHING SPECIFICATION

(A)
40

so
~~
~
20
40 /'
en301-----+-----f--.a...-...._~1-1-++-,t!L- ...... i;"'
,,... ~

--,
I,
m ,o
::E •• ,/;•.
9 7

~5"I/",
::>
g Ia :
20t----+---+-~--,-"'"+-,J,,l'++----I

15t-----+----+----,,l"-""""'+-lt-t-++-----f 4
/

c., ts ~'...."'"'/
~ 10----------.....-----++-----1 0 z
.,,II' /
a' a---------------++-----1 ; /
// """"I
Cl.I
0.8
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o,7

4.__ __ _ _._.....____.__._......,t-.L.._____,
__._
0.1
0.5
, I

-I -2 -3 -4 -5-6 -8 -IO -15 o.4., •Z •I •4 • •8 •IO •ZO •30 •40 •IO •eel -tOO

VcE-VOLTS Ics • MILLIAMPERES

2N994 CHARGESPECIFICATION
(8)
Figure 6.19

93
SWITCIUNG CHARACTERISTICS

Expressions for the emitter and collector depletion layer charge can be approxi-
mated from small signal capacitance measurements on the respective junctions. If Cob
is known at some reverse bias V ca with Is: =
0, the Qc can be approximated if it is
known whether the device has alloy, grown, or diffused junctions. If the device is an
alloy transistor, then
=
Cob k Vea-t/1 (6i)
where k is a proportionality constant. The approximate depletion layer charge required
for the alloy junction voltage to move from V oa1 to V cs2 is found from equations 6j and
6k or Table 6.1.
Vcs:1
Qo =f Cob dV = rVon2
kv- 1111
dV (6j)
Vou1 • Vcs1
Vce2
Qc =2 k Vca 112IVcu1=2 k (Vcui 12 - Vca1111
) (6k)

The value of k is found from the small signal capacitance measurement and the
expression given in equation (6i); that is, the junction constant k is found for the
collector junction of an alloy transistor by multiplying the measured Cob by (Vcu)112
where Vcu is the measurement voltage. Table 6.1 gives these formulae for other struc-
tures. For grown junctions, the capacitance is proportional to Vcu-111 while for diffused

junctions - mesa and planar structures - an approximate value of Vca -o., is frequently
used. The diffused junction capacitance may, however, be proportional to voltage
functions anywhere from Vcu- 112to Vca- 111 and will vary with voltage level. Table 6.1
indicates some of the results from these considerations.

Parameter Alloy Grown Diffused

Cob k., Vuo- 111 kc Vcu- 111 kc Vcn-o.,

C1b k. Vs:a-112 k. Vsu- 111 k. Vs:u-o.,

Qo 2kc V CB 111I V CB:I l.5kc V ca•/11V ca, l.6k., Vcuo.e IVcu,

Vest Vcu1 Vcu1

Qg I
2k., VEu1/1 Vrrn:r 1.5k. V ca•talV EB:i 1.6k. Vzuo.o VsB2 I
VEn1 Vza1 Vznt

k.,* Cob Vcu 111 Cob Vce 111 Cob Vcn°·'

k.* Cab V1rn1111 Ctb Yt:n113 C1b Vza

0
·'

•The Ven or Vim in these expressions is the measurement voltage for Cob or C1b respectively.

Table 6.1
APPROXIMATE
VALUESOF Ge AND QE FROMCob AND C1b

An instance where Table 6.1 would be of value is in determining the charge re-
quirements for delay time. From equations (6d), it is seen that the delay time charge
is Qs + Qc», If the reverse bias on an alloy transistor is VI and the supply voltage is
V..,.,,then

94
 SWITCHING CHARACTERISTICS

V2
Qv. = 2k. Vv.e
112
I=
O 2k. V2
112

V2+ V.,.,
= 2k., [ (V2+ v.,.,)112 - v.,.,112]
or
Qco = 2k., Vce112
Iv.,.,•

QE + Qco = 2k. V2 + 2k ..
112
[<v2 + v., ..)
112 112
..... v., .. ]

On the 2N396A specification shown in Figure 6.19, the Qco value would be taken
from the Q0100graph by finding Qc at V2 + V.,., and subtracting Qc at V.,., from it.
CaE is specified as the average base-emitter junction capacitance and is essentially
equivalent to the capacitance at 1 volt reverse bias. The Cei;:value is thus numerically
equal to k ... Using these charge parameters, one can rapidly determine response char-
acteristics. Even if the input is not a current source, the charge requirements of the
device are useful. For example, the speed-up capacitor in RCTL (Resistance Capacitor
Transistor Logic) circuits can be estimated.
Also, since the charge graphs as shown in Figure 6.19 illustrate the effects of col-
lector current and voltage separately, a designer can readily estimate the effects of
supply voltage or load current variation on the transient response of a circuit. It is
interesting to note, for example, that at high current levels in the 2N396A specification
the depletion layer charge, Qc, is only a small fraction of Qa, whereas on a mesa device
like the 2N781 or 2N994, the collector depletion charge Qc is a large fraction of the
total base charge (Qa + Qc) at almost all operating points of interest, as .shown in
Figure 6.19 for the 2N396A and 2N994. These observations would argue that for alloy
transistors the supply voltage level which is being used need not be as critically
selected as for mesa units, and that the mesa's ability to switch rapidly is shown more
readily at low collector supply voltages.
Solution of the diffusion equation for transient speed of a transistor is beyond the
scope of this manual. Two important results of this analysis should be stated however.
First, any prediction using equations given in this section to predict a response time
approaching 1/(25 fa) should not be accepted since approximations made are not valid
at these speeds. Secondly, as Ie2 becomes larger, the error in storage and fall time
equations increases since the minority carrier density in the base, shortly after the
application of the turn-off pulse, is not as shown in Figure 6.18(D), but is more like
that shown in Figure 6.20
EMITTER COLLECTOR
JUNCTION JUNCTION
I I

BASE CHARGE DISTRIBUTION WITH LARGE le1

Figure 6.20

95
SWITCHING CHARACTERISTICS

CIRCUIT TECHNIQUES TO AUGMENT

SWITCHING CHARACTERISTICS
Some circuits have been designed making specific use of saturation. The direct
coupled transistor logic (DCTL) flip-flop shown in Figure 6.21 utilizes saturation.
In saturation V cE cRAT>can be so low that if this voltage is applied between the base
and emitter of another transistor, as in this Hip-flop, there is insufficient forward bias
to cause this transistor to conduct appreciably. The extreme simplicity of the circuit
------------3V

0.2V o.ev
VcE(sat> 2N914

DIRECT COUPLEDTRANSISTOR LOGIC (DCTL) FLIP-FLOP

Figure6.21

is seH evident and is responsible for its popularity, However, special requirements are
placed on the transistors. The following are among the circuit characteristics:
First, the emitter junction is never reverse biased permitting excessive current to
flow in the off transistor at temperatures above 40°C in germanium. In silicon, how-
ever, operation to 150°C has proved feasible.
Second, saturation is responsible for a storage time delay slowing up circuit speed.
In the section on transient response we see the importance of drawing current out of
the base region to increase speed. In DCTL this current results from the difference
between VcEcsAT> and VsE of a conducting transistor. To increase the current, VcEcsAT>
should be small and rb' should be small. However, if one collector is to drive more
than one base, rb' should be relatively large to permit uniform current sharing between
bases since large base current unbalance will cause large variations in transient response
resulting in circuit design complexity. High base recombination rates and epitaxial
collectors to minimize collector storage result in short storage times in spite of rb'.
Third, since V cE csAT>and VaE differ by less than .3 volt in germanium, stray voltage
signals of this amplitude can cause faulty performance. While stray signals can be
minimized by careful circuit layout, this leads to equipment design complexity. Silicon
transistors with a 0.6 volt difference between V cE cRAT>and V BR are less prone to being
turned on by stray voltages but are still susceptible to turn-off signals. This is some-
what compensated for in transistors with long storage time delay since they will remain
on by virtue of the stored charge during short turn-off stray signals. This leads to
conflicting transistor requirements - long storage time for freedom from noise, short
storage time for circuit speed.
Another application of saturation is in saturated flip-flops of conventional configura-
tion. Since VcE cSAT1is generally very much less than other circuit voltages, saturating
the transistors permits the assumption that all three electrodes are nearly at the same
potential. making circuit voltages independent of transistor characteristics. This yields
good temperature stability and good interchangeability. The stable voltage levels are
 SWITCHING CHARACTERISTICS

useful in generating precise pulse widths with monostable flip-flops. The section on
Hip-flop design indicates the ease with which saturated circuits can be designed.
In general, the advantages of saturated switch design are: (a) simplicity of circuit
design, (b) well defined voltage levels, (c) fewer parts required than in non-saturating
circuits, (d) low transistor dissipation when conducting, and (e) immunity to short
stray voltage signals. Against this must be weighed the probable reduction in circuit
speed since higher trigger power is required to tum off a saturated transistor than one
unsaturated.

l
Ic
_,_
RL

Eo Ecc~vcE
DIODECOLLECTOR COLLECTORCHARACTERISTICS
CLAMPINGCIRCUITTO SHOWINGLOAD LINE AND OPERATING
AVOID SATURATION POINTS
COLLECTORVOLTAGECLAMP
Figure6.22

A number of techniques are used to avoid saturation. The simplest is shown in

Figure 6.22. The diode clamps the collector voltage so that it cannot fall below the
base voltage to forward bias the collector junction. Response time is not improved
appreciably over the saturated case since le is not clamped but rises to hvEla. Typical
variations of Iu and h••v.with temperature and life, for a standard transistor, may vary
le by as much as 10: 1. Care should be taken to ensure that the diode prevents satura-
tion with the highest le. When the transistor is turned off le must fall below the value
given by (Eee - Eo)/R,. before any change in collector voltage is observed. The time
required can be determined from the fall time equations in the section on transient
response. The diode can also have a long recovery time from the high currents it has
to handle. This can further increase the delay in turning off. Diodes such as the 1N3604
or 1N3606 have recovery times compatible with high speed planar epitaxial transistors.
A much better way of avoiding saturation is to control Iu in such a way that le is
just short of the saturation level. This can be achieved with the circuit of Figure
6.23(A). The diode is connected between a tap on the base drive resistor and the
collector. When the collector falls below the voltage at the tap, the diode conducts
diverting base current into the collector and preventing any further increase in le. The
voltage drop across Rz is approximately IcRz/hFE since the current in Rz is Iu. Since
the voltage drop across the diode is approximately the same as the input voltage to
the transistor, Vcmis approximately le.Ra/hrs, It is seen that if the load decreases (le
is reduced) or hn becomes very high, Vcs decreases towards saturation. Where the

97
SWITCHING CHARACTERISTICS

change in hn is known and the load is relatively fixed, this circuit prevents saturation.
To avoid the dependence of VoE on le and hn, Ramay be added as in Figure 6.23(B).
By returning Rato a bias voltage, an additional current is drawn through Ra. Now
VcE is approximately (hie
VE
+ Ia)Ra.Ia can be chosen to give a suitable minimum Vcs.

COLLECTORCURRENT CLAMP WITHOUT BIAS SUPPLY

Figure 6.23(A)

The power consumed by Racan be avoided by using the circuit of Figure 6.23(C),
provided a short lifetime transistor is used. Otherwise fall times may be excessively
long. Ra is chosen to reverse bias the emitter at the maximum Ico. The silicon diode
replaces R2. Since the silicon diode has a forward voltage drop of approximately .7
volts over a considerable range of current, it acts as a constant voltage source making
Veg approximately .7 volts. If considerable base drive is used, it may be necessary to
use a high conductance germanium diode to avoid momentary saturation as the voltage
drop across the diode increases to handle the large base drive current.

Ihl

COLLECTORCURRENT USING BIAS SUPPLY

Figure 6.23(8)

98
 SWITCHING CHARACTERISTICS

VcE ~ 0.7V at 25° C

COLLECTORCURRENT CLAMP USING SILICON

AND GERMANIUM DIODES
Figure6.23(C)

In applying the same technique to silicon transistors with low saturation resistance,
it is possible to use a single germanium diode between the collector and base. While
this permits VcE to fall below VBE, the collector diode remains essentially non-
conducting since the .7 volt forward voltage necessary for conduction cannot be
reached with the germanium diode in the circuit.
Diode requirements are not stringent. The silicon diode need never be back biased,
consequently, any diode will be satisfactory. The germanium diode will have to with-
stand the maximum circuit VcF.,conduct the maximum base drive with a low forward
voltage, and switch rapidly under the conditions imposed by the circuit, but these
requirements are generally easily met.
Care should be taken to include the diode leakage currents in designing these
circuits for high temperatures. All the circuits of Figure 6.23 permit large base drive
currents to enhance switching speed, yet they limit both IB and Ic just before saturation
is reached. In this way, the transistor dissipation is made low and uniform among
transistors of differing characteristics.
It is quite possible to design flip-flops which will be non-saturating without the
use of clamping diodes by proper choice of components. The resulting Hip-Hop is
simpler than that using diodes but it does not permit as large a load variation before
malfunction occurs. Design procedure for an undamped non-saturating Hip-flop can be
found in Transistor Circuit Engineering by R. F. Shea, et al (John Wiley & Sons, Inc).
Ecc

STORED CHARGE NEUTRALIZATION BY CAPACITOR

Figure6.24

99
SWITCHING CHARACTERISTICS

Another circuit which is successful in minimizing storage time is shown in Figure

6.24. If the input is driven from a voltage source, it is seen that if the input voltage
and capacitor are appropriately chosen, the capacitor charge can be used to neutralize
the stored charge, in this way avoiding the storage time delay. In practical circuits,
the RC time constant in the base necessary for this action limits the maximum pulse
repetition rate.

100
BIASING

One of the basic problems involved in the design of transistor amplifiers is estab-
lishing and maintaining the proper collector to emitter voltage and emitter current
(called the biasing conditions) in the circuit. These biasing conditions must be main-
tained despite varations in ambient temperature and variations of gain and leakage
current between transistors of the same type. The factors which must be taken into
account in the design of bias circuits would include:
I. The specified maximum and minimum values of current gain (hn) at the oper-
ating point for the type of transistor used.
2. The variation of hFE with temperature. This will determine the maximum and
minimum values of hFE over the desired temperature range of operation. The
variation of hFE with temperature is shown in Figure 6.7 for the 2N525
transistor.
3. The variation of collector leakage current (Ico) with temperature. For most
transistors, Ico increases at approximately 6.5-8%/°C and doubles with a tem-
peratu're change of 9-11 °C. In the design of bias circuits, the minimum value of
Ico is assumed to be zero and the maximum value of Ico is obtained from the
speci6cations and from a curve such as Figure 6.6. If silicon transistors are used,
it is best to use the specified high temperature Ico for estimating the maxi-
mum Ico,
4. The variation of base to emitter voltage drop (V1n:) with temperature. Under
normal bias conditions, VnE is about 0.2 volts for germanium transistors and 0.7
volts for silicon transistors and has a temperature coefficient of about -2.5 milfi-
volts per °C. Figure 7 .1 shows the variation of VBF: with collector current at
several different temperatures for the 2N525. Note that for some conditions of
high temperature it is necessary to reverse bias the base to get a low value of
collector current.
5. The tolerance of the resistors used in the bias networks and the tolerance of the
supply voltages.
- ~•c
v- --
Y) /

Ill

- ,.v --- - i--

-
O"C

Zll't

-
(/ i....-- ~•c
-
0
(
/ --....-~
/
~
c- - -70't

I
+•
,-/ I) •I -2 -l -4
_, -6
EMITTERCIRIENT. SE-MILLIAMPERES

INPUT CHARACTERISTICS OF 2N525 CVc•:

= 1V)
Figure7.1

101
BIASING

Two of the simpler types of bias circuits are shown in Figures 7.2 and 7.3. These
circuits can be used only in cases where a wide range of collector voltage can be
tolerated (for Figure 7 .2 at least as great as the specified range of hvE) and where
hvsmu times Ioom•x is less than the maximum desired bias current. Neither circuit can
be used with transistors which do not have specifications for maximum and minimum
hvs unless the bias resistors are selected individually for each transistor. The circuit of
Figure 7.3 provides up to twice the stability in collector current with changes in hvE
or loo than the circuit of Figure 7.2. However, the circuit of Figure 7.3 has a-c feed-
back through the bias network which reduces the gain and input impedance slightly.
This feedback can be reduced by using two series resistors in place of R2 and connect-
ing a capacitor between their common point and ground.

+Vee

TRANSISTORBIAS CIRCUITS
Figure 7 .2 Figure 7 .3

In cases where more stability is desired than is provided by the circuits of Figure
7.2 or 7.3, it is necessary to use a resistor in series with the emitter of the transistor as
shown in Figure 7.4. There are several variations of this circuit, all of which may be
obtained by the general design procedure outlined below. The currents shown in
Figure 7.4 are those which would be measured if an ammeter were inserted in that
circuit; thus, for example, the value of Is in the figure includes Ico,

+Vee

lei: hFE Ia +{hFE +I) leo

a
hFE= I-a

BASIC TRANSISTOR BIAS CIRCUIT

Figure 7.4

102
 BIASING

For the circuit of Figure 7.4, the following equations apply:

IE = (hFE+ 1) (Is + lco) (7a)

Vu= [ (hF:~ l) +RE] It:+ VuE- lcoRe (7b)

Considering bias conditions at the temperature extremes, at the mm1mum tem-

perature, le will have its minimum value and the worst conditions would occur for
hvE = hFEmln,VaE = Vat:max,Ico = 0 or
at lowest temperature: Va= [ hFEmln
Rs + 1 + RE ] I E min+ Vat:max (7c)

and at the highest temperature of operation IE will have its maximum value and the
worst conditions would occur for hl'E = hvEmax,VaE = VuEmln,Ico = Icomax.
at highest
temperature:
V8 = [ Rs
hFEmu+ 1
+ R
m
J
I max+ V min_ I mu R8 .
t: BE co
(7d)
from these two equations the value of Rs can be calculated by equating the two
expressions:
Rs= (lt:max_ lt:mln)Rv.+ y 8 Emln_ y 8 Emax
(7e)
I max It:max l&mln
CO - hvt:max+ 1 + hnmln + 1
As an example, consider the following bias circuit design:
1. Select the transistor type to be used (2N525)
2. Determine the required range of temperature
0°c to+ 55°C
3. Select the supply voltage and load resistance
Vee= 20 volts; RL = 7.5K
4. Determine Icomax:
From the electrical specifications the upper limit of Ico is 10 µ,a at 25°C and
from Figure 6.6 Ico will increase by a factor of 10 at 55°C, thus Icomu:= 10 X
=
10 100 µ,a.
5. Determine the values of hFEmlnand hFEmax
From the electrical specifications, the range of hvE at 25°C is 34 to 65. From
Figure 6.7 hFE can change by a factor of 0.75 at 0°C and by a factor of 1.3 at
+55°C.
= = =
Thus hl"Emla 0.75 X 34 25 and hFEmax 1.3 X 65 = 85.
6. Determine the allowable range of Ii;::
In general, the variation of the circuit performance with emitter current
determines the allowable range of emitter current. In some cases the allowable
range of emitter current is determined by the peak signal voltage required
across RL.
Assume that the minimum current is .67 ma which gives a minimum voltage
of 5 volts across RL and the maximum emitter current is 1.47 ma which gives a
maximum voltage of 11 volts across RL, The allowable range of emitter current
must be modified to take into account the tolerance of the bias resistors. That is,
if the allowable range of emitter current is .67 ma to 1.47 ma, the circuit must
be designed for some narrower range of emitter current to allow for resistor
tolerances.

103
BIASING

Assuming a bias network using three 5% resistors, then

1Emln= (1 + 3 X .05) (0.67) = 0.77 ma and
1Emax = (1 - 3 X .05) (1.47) = 1.25 ma

7. Estimate the values of Vul'lmlnand VuEmax

From Figure 5.1 Vut:mlnat 55°C and IE = 1.47 ma is about 0.08 volt,
VuF.maxat 0°C and 1E= 0.67 ma is about 0.17 volt.
8. Calculate the value of Rn from equation (7e).
Rs= 4.17 RF.- 0.78K
9. Using the equation from (8), choose a suitable value of Ra and RE, This involves
a compromise since low values of RE require a low value of Ra which shunts the
input of the stage and reduces the gain. A high value of RE reduces the collector
to emitter bias voltage which limits the peak signal voltage across RL,
Choose RF.= 2.7K for which Rn= 10.4K. This gives a minimum collector to
emitter voltage of 20 - (2.7 + 7.5) 1.47 = 5 volts.
10. Calculate Vs using equation (7c).
Vn = 2.56 volts
11. If the bias circuits of either Figures 7 .5 or 7 .6 are to be used, the values of the
bias resistors can be calculated from the values of Ra, R& and Va obtained in
the preceding design by the use of the conversion equations which are given.
In these figures Rs represents a series resistance which would be present if trans-
former coupling were used in which case Rs would be the d-c resistance of
transformer secondary. In cases where capacitor coupling is used Rs will usually
be equal to zero. A comparison of Figures 7 .5 and 7 .6 indicates that the circuit
of Figure 7.6 is superior in that for a given bias stability, it allows a lower value
of the emitter resistor or larger values of the base resistors than the circuit of
Figure 7 .5. On the other hand, the circuit of Figure 7.6 gives a-c feedback
through the bias circuits which may be a disadvantage in some cases, as was
mentioned earlier in.connection with Figure 7.3.
For the circuit of Figure 7.5, assume R" = 0. Then Ra = = RE 2.7K,
=
R1 = 77K or, choosing the next lowest standard value, R1 68K. Using this
value, calculate R2 = !OK. For the circuit of Figure 7.6 as before R'1 = 68K
and R':z = !OK. Resistor R'a is calculated as 1.73K or, using the next highest
standard value, R'a = I.SK.
----------a+~c

VOLTAGEDIVIDER TYPE BIAS CIRCUIT

Figure7.5

104
 BIASING

VOLTAGE DIVIDER TYPE BIAS CIRCUIT WITH FEEDBACK

Figure7.6

Frequently, in biasing an amplifier, it becomes necessary to use techniques by

which higher input impedance or better stability are obtained than afforded by the
circuits already shown. Many different schemes have been used to accomplish these
purposes and the degree of complexity of any one method depends largely upon the
factors listed earlier in this chapter. In any design, however, considerations similar to
those in the example shown above must govern the circuit values chosen. Some bias
methods used are shown in Figure 7.7 through Figure 7.9. In Figure 7.7 a three stage
direct coupled amplifier is shown. The second and third stages of this amplifier are
biased by the preceding stages. In the direct coupled amplifier, the stability is improved
if all transistors in the amplifier are similar since the changes in bias in adjacent tran-
sistors tend to compensate for one another. Further stability is gained in this configu-
ration by the addition of the feedback loop represented by R1, R:!,and C,. C, is added
to eliminate a.c. feedback.

COMMON EMITTER DIRECT COUPLED AMPLIFIER

Figure7.7

105
BIASING

In Figures 7.8 and 7.9, biasing techniques are used which will improve the input
impedance of the amplifier being designed. In Figure 7.8, the a.c. feedback through
R1 is essentially eliminated by the existence of Gr. R1 can therefore be quite small in
order to obtain good temperature stability for the amplifier. In Figure 7.9 bootstrapping
techniques are used. Here the a.c. and d.c. feedback are quite large. Temperature
stability and input impedance can be optimized but the gain of the circuit is sacrificed
for increased input impedance.

Vo

1---oouT

Cz

DIRECT COUPLEDAMPLIFIER
Figure 7.8

OUT

Rz

BOOTSTRAPPED
AMPLIFIERS
Figure 7.9

106
 BIASING

As an example of the biasing considerations for a direct coupled amplifier, the

circuit shown in Figure 7.8 is considered. Only d.c. conditions are of interest, there-
fore resistors Ra and R1will be considered together and called Ra in the analysis. Node
equations can be written for this bias scheme
I2 = let + In2 (7£)
1st + let = hi (7g)
102+ Ie2 I.:2 = (7h)
l•:2= Ie1 + l1 (7i)
Again, these currents are those which one would measure in the lines in which they
How. In addition to these e9uations, two more equations can be written which depend
upon the transistor's action.
lei = hFEt lei + (hFEt+ 1) leo1 (7j)
le:?= hFE:!l02 + (hn:i + 1) lco2 (7k)
The relationships between the voltages, resistors, and currents in the circuit are
12= Vo- Ve1 (71)
R2
I _ Vt -Ve1 {7m)
Bl - Rt
I _ VF.1 {7n)
Et - Ra

I c-i _- Vo -R. Ve~ (7o)

I _ Vp;:i- V1 {7p)
f::l - R:.

l1 =Vi
Ro
(7q)

Substituting these voltage and resistor values into the node equations, and eliminating
lei and Ia2by use of the transistor equations (7j) and (7k), the following results
Vo - Ve, h .
R: Ft:1
(v,-
Rt
Vm) + (h + 1) I + Vo - Ve: -(hFF.2 +
FF.1 Cot hFt::1R. hF.:2
1) I
COi

(7r)
(1 + h FE!)( V, -Vn,+
R, I•COi )- - V•:1
Ra (7s)

( Vo -R.VeQ
- - I CO:! ) (l+ h ) =h
FE:! ••&:1
(VE2R
- ...V1) (7t)

VE:1- V1 = V1 - Vn1+ V1 (7u)

R. R1 R.,
To these equations, other transistor voltage relationships can be written
VE1+ VeE1= Ve1 (7v)
VE:I+ Vet::i= Vc:1 (7w)
VE1+ VaE1= Vo, (7x)
VE2+ VaE2 Vn:.1 =
= Ve1 (7y)
There are now eight independent equations (7r) through (7y), relating the voltage
and resistance values of the circuit. The circuit requirements of the particular design
now govern the remainder of the design procedure. All of the above equations are true
at all temperature extremes. The stability problem arises since the values of Ieo and
hr£ change as a function of temperature. As these values change, the voltage and

107
BIASING

current relationships within the circuit must also change so that equations (7r) through
(7y) are satisfied. In practical design, for example, the specifications for the amplifier
normally demand that the output be capable of a specific voltage excursion. This peak
to peak allowable swing at the collector of the output transistor can theoretically equal
the supply voltage, if the bias voltage, Vc:i, is exactly Vo/2. Maintaining Vc:i exactly
over the range of hFE and Ico is essentiaJly impossible, and thus the output voltage
excursion must be somewhat less than the supply voltage so that limiting does not
occur on the output waveform as the bias level changes. At the lowest temeperature of
interest, the emitter currents will be a minimum and the worst conditions would occur
for hn = hP'Bmin,VoEmax,and Ico = 0. At high temperature, the emitter currents will
have a maximum value, and the worst case is encountered for hFE = hFEm•x,VBE =
VeEmln,and lco = lco.mu
The choosing of resistor values throughout the circuit is normaUy accomplished by
considering circuit requirements in conjunction with transistor operating conditions.
Equations (7f) through (7q) may also be of value in selecting resistors. A pedectly
general biasing scheme is difficult to describe since individual circuit requirements
play an important role in every amplifier. Some considerations are mentioned earlier
in this chapter and also in Chapter 14. A general method of checking the values of
resistance chosen could be worked out by solving equations (7r) through (7y) for Vc:i
by eliminating all voltages except Vo, V0.:1,and Vov.:z.The resulting equation will be
of the form
Ve-•= K1Vo+ K: Vev.1+ KaVe•:2+ K. lco1+ K, Ico:i (7z)
- Ko
If no approximations are made, these constants can be quite lengthy. For the case of
Figure 7.18 the constants are

K1 = (1 ± ~:.: Ro [ & ( l + ~:) + RA+ h•••:•R:1]-

2
) RA ( hFv.2- ~:) (7aa)

K2= - hFv.:(hFF.1R:i- Ro) (7bb)

K3 = hv•:2RA (7cc)
K~= hvt::z(1 + hvE1)(Ro + R1R:1) (7dd)
K, = - (1 + h.-v.::)[(1 + h•••:1)(RsR'I +Rn)+ (R, R: + Re)] (7ee)

Ko= (l ± ~E:!) Ro [ R, ( 1 +~:)+RA+ hn:i R:] + (RA+!\.Ro)R:1 (7ff)

where,
RA = R1 + (1 + h•••:i) Ra (7gg)

Ro = Ra Rs + R: Ro + Ra Ro (7hh)
Re = R1 Rs+ R1Ro + RsRo (7ii)

By calculating the value of Ve2 using the worst case values for h1% VoE, and loo at
the temperature extremes the variation in Ve2with temperature can be checked. Though
this procedure is tedious, one is able to determine the stability of any given amplifier
using steps similar to those outlined for the circuit of Figure 7 .18.
Because of the circuit configuration used in this example, other types of bias
schemes can also be analyzed by setting some of the resistor values at zero. Two
different bias schemes would call for the following resistor changes: Ro= O; or Ro= 0,
and R1represents resistance seen at the base by the first transistor.

108
 BIASING

THERMALRUNAWAY
When a transistor is used at high junction temperatures (high ambient temperatures
and/ or high power dissipation) it is possible for regenerative heating to occur which will
result in thermal run-away and possible destruction of the transistor. In any circuit the
junction temperature (T1) is determined by the total power dissipation in the transistor
(P), the ambient temperature (TA), and the thermal resistance (K).
L=L+U ~
If the ambient temperature is increased, the junction temperature would increase an
equal amount provided that the power dissipation was constant. However, since both
hFE and Ico increase with temperature, the collector current can increase with increas-
ing temperature which in tum can result in increased power dissipation. Thermal run-
away will occur when the rate of increase of junction temperature with respect to the
power dissipation is greater than the thermal resistance (b. T1/ b.P K).>
Thermal run-away is generally to be avoided since it can result in failure of the
circuit and possibly in destruction of the transistor. By suitable circuit design it is
possible to ensure either that the transistor can not run away under any conditions or
that the transistor can not run away below some specified ambient temperature. A dif-
ferent circuit analysis is required depending on whether the transistor is used in a
linear amplifier or in a switching circuit.
In switching circuits such as those described in Chapter 6, it is common to operate
the transistor either in saturation (low collector to emitter voltage) or in cutoff (base to
emitter reverse biased). The dissipation of a transistor in saturation does not change
appreciably with temperature and therefore run-away conditions are not possible. On
the other hand, the dissipation of a transistor in cutoff depends on Ico and therefore
can increase rapidly at higher temperatures. If the circuit is designed to ensure that the
emitter to base junction is reverse biased at all temperatures (as for the circuit of Fig-
ure 7.10) the following analysis can be used:

Ico
+-- Vcc=-30V
--~V'v----0

Figure7.10
The transistor power dissipation will be,
P = IcoVCE = Ico(Vcc - lcoRL)= Ico Vcc - lco2 RL (7kk)
The rate of change of power dissipation with temperature will be,

~; = 1i: 0
• ~;' = (V cc - 2lcoRL) 8lco (7ll)

where 8 E!! 0.08 is the fractional increase in Ico with temperature. The condition for
run-away occurs when dP/dT =
1/K or,
(V cc - 2IcouRL) 8lcou =
1/K {7mm)
where Icou is the value of Ico at the run-away point. Solving for Icou gives,
lcou = Vee±
1
V (Vcc) - (8RL)/(8K) {7nn)
4RL

109
BIASING

In this equation the solution using the negative sign gives the value of Icou, while the
solution using the positive sign gives the value of Ico after run-away has occurred. It is
seen from the equation that the value of Ico after run-away can never be greater than
Vcc/2RL so that the collector voltage after run-away can never be less than one half of
the supply voltage V cc, If the term under the square root sign in the-above equation is
zero or negative, thermal run-away cannot occur under any conditions. Also, if thermal
run-away does occur it must occur when the collector voltage is greater than 0.75Vcc.
since when the term under the square root sign is zero, 10011 RL equals .25 V cc, As RL
goes to 0, the solution for Ico11using the negative sign is indeterminant, i.e., equal to
0/0. In this case Equation (7mm) is used and
1
=
IcoM a K Vee (700)
Since no RL exists, the current after thermal runaway is theoretically infinite, and the
transistor will be destroyed unless some other current limiting is provided. Once the
value of IcoMis determined from Equation (7nn) or (700) the corresponding junction
temperature can be determined from a graph such as Figure 6.6. The heating due to
10011 is found by substituting Icou for Ico in Equation (7kk). Finally, the ambient tem-
perature at which run-away occurs can be calculated from Equation (7jj).
In circuits which have appreciable resistance in the base circuit such as the circuit
of Figure 7.11 the base to emitter junction will be reverse biased only over a limited
temperature range. When the temperature is increased to the point where the base to
emitter junction ceases to be reverse biased emitter current will flow and the dissipation
will increase rapidly. The solution for this case is given by:

Ve =+IV
,----o vcc=-30V

IK

2N527

Figure7.11
Ico11 = (Vee - 2R~tol:1:) ± v(Voo - 2RJi,.Lr) 1
- (8RL)/(aK) (7pp)
4R~,.
where Is = Va/Ra, When RL approaches 0.
Ioou =hn l
a K Vee
(7qq)
In the analysis of run-away in linear ampliBers it is convenient to classify linear
amplifiers into preamplifiers and power amplifiers. Preamplifiers are operated at low
signal levels and consequently the bias voltage and current are very low particularly in
stages where good noise performance is important. In capacitor coupled stages a large
collector resistance is used to increase gain and a large emitter resistance is used to
improve bias stability. Accordingly, thermal run-away conditions are seldom met in
preampliBer circuits.

110
 BIASING

In contrast, power amplifiers invariably require transistors to operate at power

levels which are near the run-away condition. The conditions are aggravated by the
use of biasing networks of marginal stability which are required for power efficiency
and by the use of transformer coupling to the load which reduces the effective collector
series resistance. Since thermal run-away in power stages is likely to result in destruc-
tion of the transistors, it is wise to use worst case design principles to ensure that
thermal run-away cannot occur. The worst case conditions are with hro • 00, VBl'l = 0,
RL = 0, and Ieo = Icomu. If these conditions are applied to a transistor in the general
bias circuit shown in Figure 7.12 the total transistor dissipation is given by:

vcc=-3ov

V9=2V

Figure7.12

P = VcElc = (Vee - Va - lcoRu) ( Ico + Va +R!eoRo ) (7rr)

Equating dP/dT with 1/K and solving for l0011 as before,

Icou = (Vee - R1Va)± v(Vco - RiVa)1 - (~)/(aK) (7ss)
4Ra
where
Ri =RE+ 2Re ~= BRrcRa
Re+ Re Rc+Ru
As before, the solution of Equation (7ss) using the negative sign gives the value of
Icou, while the solution using the positive sign gives the final value of Io after run-away
has occurred. If the quantity under the square root sign is zero or negative, run-away
cannot occur under any conditions.
In class-B power amplifiers the maximum transistor power dissipation occurs when
the power output is at 40% of its maximum value at which point the power dissipation
in each transistor is 20% of the maximum power output. In class-A power amplifiers
on the other hand, the maximum transistor dissipation occurs when there is no applied
signa!. The maximum power dissipation is obtained by substituting Ico11in Equation
(7rr) and the maximum junction temperature is obtained from Equation (7jj).
In the design of power amplifiers the usual procedure is to design the circuit to
meet the requirements for gain, power output, distortion, and bias stability as described
in the other sections of this manual. The circuit is then analyzed to determine the
conditions under which run-away can occur to determine if these conditions meet the
operating requirements. As a practical example, consider the analysis of the class-A
output stage of the receiver shown in Figure 10.12. The transistor is the 2N241A for

111
BIASING

= =
which K 250°C/watt and Icomu: 16,aa at 25°C and 25 volts. Calculating the circuit
values corresponding to Figure 7.12 and Equation (7ss):
Vee= 9 v, R1:= 100 0
Va = (1000) (9)
1000 + 4700
= 1.58 V Ro= (1000) (4700) = 825 0
1000 + 4700
R1
= 100 + 2(825)
100 + 825
= 189 R:i = 8(100) (825) =713 0
. 100 + 825
Calculating Icou from Equation (7ss)
Icou= 6 ± v<fA7
3300
=.1 61 ma or 2 .02 ma

Since the quantity under the square root is positive, thermal run-away can occur. The
two solutions give the value of Ico11(1.61 ma) and the value of Ico after run-away has
occurred (2.02 ma). The fact that these two currents are very nearly equal indicates
that the change in power dissipation when run-away occurs will not be very large.
=
Using the value Icou/Icomax 100 the junction temperature at run-away from Figure
6.6(A) is about 92°C. The dissipation at run-away, calculated from Equation (7rr), is
about 187 milliwatts. The rise in junction temperature due to this power dissipation
=
is (0.25) (187) 46.7°C. The ambient temperature at run-away is then calculated to be
92 - 46.7 = 45.3°C. The above value of maximum transistor power dissipation is
calculated under the assumption that the series collector resistance is zero. In the
circuit under consideration the transformer primary will have a small d-c resistance (RT)
which will reduce the transistor power dissipation by approximately (Ic)2 RT where le is
given by the second term in Equation (7rr). Assuming that the d-c resistance of the
transformer is 20 ohms the reduction in power dissipation for the case just considered
will be 18.8 milliwatts and the ambient temperature at run-away will be increased
to 50.0°C.

112
AUDIO AMPLIFIERS

SINGLE STAGE AUDIO AMPLIFIER

Figure 8.1 shows a typical single stage audio amplifier using a 2N1414 PNP
transistor.

-----~---- -12V

- c,
+I_ 50µ.fd

SINGLE STAGE AUDIO AMPLIFIER

Figure8.1

With the resistance values shown, the bias conditions on the transistor are 1 ma
of collector current and six volts from collector to emitter. At frequencies at
which C1 provides good by-passing, the input resistance is given by the formula:
R,n = (1 + h,.) h1b, At 1 ma for a design center 2Nl414, the input resistance would
be 45 X 29 or about 1300 ohms.

The a-c voltage gain eout is approximately equal to hRL For the circuit shown, this
e1n lb

5000 .
would be ~ or approximately 172.

The frequency at which the voltage gain is down 3 db from the 1 Kc value
depends on ri:. This frequency is given approximately by the fonnula
1 + h, ..
Iow f a,1b .,._, 6.28 (ri:C1)

TWO STAGE R-C COUPLED AMPLIFIER

The circuit of a two stage R-C coupled amplifier is shown by Figure 8.2. The
input impedance is the same as the single stage amplifier and would be ap-
proximately 1300 ohms.

113
AUDIO AMPLIFIERS

Figure8.2

The load resistance for the first stage is now the input impedance of the second
stage. The voltage gain is given approximately by the fonnula
RL
A"= h ,.-h lb

More exact fonnulas for the perfonnance of audio amplifiers may be found in
Chapter 4 on small signal characteristics.

CLASS B PUSH-PULL OUTPUT STAGES

In the majority of applications, the output power is specified so a design will
usually begin at this point. The circuit of a typical push-pull Class B output stage is
shown in Figure 8.3.

Figure8.3

The voltage divider consisting of RI and R2 gives a slight forward bias of about
.14 volts on the transistors to prevent cross-over distortion. The 10 ohm resistors in the
emitter leads stabilize the transistors so they will not go into thermal runaway when
the ambient temperature is less than 55°C. Typical collector characteristics with a load
line are shown below

:IMAX.

COU£CTOR CURRENT

NO SIGNAL OPERATING
POINT

Ecc
COLLECTOR VOLTAGE

Figure8.4

114
 Aumo AMPLIFIERS

It can be shown that the maximum a-c output power without clipping using a push-
pull stage is given by the formula
Pout= I run
2
VcB where VcE =
collector to emitter voltage at no signal.

Since the load resistance is equal to RL = V CE

Imu
and the collector to collector impedance is four times the load resistance per collector,
the output power is given by the formula
Po= _2 Vcv.2 (Sa)
Rc-c
Thus, for a specified output power and collector v9ltage the collector to collector load
resistance can be determined. For output powers in the order of 50 mw to 850 mw,
the load impedance is so low that it is essentially a short circuit compared to the out-
put impedance of the transistors. Thus, unlike small signal amplmers, no attempt is
made to match the output impedance of transistors in power output stage.,;.
The power gain is given by the formula:
Power Gain ~
p
=
Pin
I'
= R
La2 Ria
0
t

Since .1_ is equal to the current gain, Beta, for small load resistance, the power gain
La
formula can be written as
p G -{J' Rc-c (Sb)
. .- Rb-b
where Re-e =collector to collector load resistance.
Rb-b =base to base input resistance.
f3 = grounded emitter current gain.
Since the load resistance is determined by the required maximum undistorted output
power, the power gain can be written in terms of the maximum output power by com-
bining equations (Sa) and (Sb) to give
(Sc)

CLASSA OUTPUT
STAGES
A Class A output stage is biased as shown on the collector characteristics below

IMAX.~
COLLECTORCURRE~ c •- • -- DC OP£RATINGPOINT

1
I •
I

v.,. zvc,
COLLECTORVOLTAGE

Figure8.5

The operating point is chosen so that the output signal can swing equally in the posi-
tive and negative direction. The maximum output power without clipping is equal to
pout---_ Vcv.- Ir
2

115
AUDIO AMPLIFIERS

The load resistance is then given by the formula

RL = Ve£
le
Combining these two equations, the load resistance can be expressed in terms of the
col1ector voltage and power output by the fonnula below
_ Vc£ 2
RL-2Po (Bd)
For output powers of 20 mw and above, the load resistance is very small compared to
the transistor output impedance and the current gain of the transistor is essentially the
short circuit current gain Beta. Thus for a Class A output stage the power gain is given
by the formula
P. G. = ff"RL = fJ2Vct:2 (Be)
R1n 2 R1nPo

CLASS A DRIVER STAGES

For a required output power of 400 mw, the typical gain for a 12 volt push-pull
output stage would be in the order of 27 db. Thus the input power to the output stage
would be about 1 to 2 mw. The load resistance of a Class A driver stage is then deter-
mined by the power that must be furnished to the output stage and this load resistance
is given by equation (Bd). For output powers in the order of a few milliwatts, the load
resistance is not negligible in comparison to the output impedance of the transistors,
therefore, more exact equations must be used to determine the power gain of a Class A
driver stage. From four-terminal network theory, after making appropriate approxima-
tions, it can be shown that the voltage gain is given by the formula
~= h1b
&
+ z. ~
=
where h1b grounded base input impedance.
=
Ze external circuit impedance in series with emitter.
The current gain is given by the formula
~= 1- + RLhob 4
4 ~

where hob= grounded base output conductance.

The power gain is the product of the current gain and the voltage gain, thus unlike
the formula for high power output stages, there is no simple relationship between
required output power and power gain for a Class A driver amplifier.

DESIGN CHARTS
Figures 8.6 through 8.15 are design charts for determination of transformer imped-
ances and typical power gains for Class A driver stages, Class A output stages, and
Class B push-pull stages. The transformer-power output charts take into account a
transformer efficiency of 75 % and therefore may be read directly in terms of power
delivered to the loudspeaker. Power gain charts show the ratio of output power in the
collector circuit to input power in the base circuit and therefore do not include trans-
former losses. Since the output transformer loss is included in the one chart and the
design procedure used below includes the driver transformer loss, it can be seen that
the major losses are accounted for.
The charts can best be understood by working through a typical example. Assume
a 300 mw output is desired from a 12v amplifier consisting of a driver and push-pull
output pair. Also the signal source has an available power output of 30 mµw

116
 AUDIO AMPLIFIERS

(30 X 10-11watts). Overall power gain required then is

P.G. = ~ = 300mw _ 300 X 10-a = lO X IO•
Pin 30 mµw - 30 X 10-11
or70 db.
To obtain 300 mw in the loudspeaker, the output pair must develop 300 mw plus
the transformer loss.
Peolleetor to eoll•t'lor = Pout
transformer eff.
= 300mw = 400mw
.75
From Figure 8.11, a pair of 2Nl415's in Class B push-pull has a power gain of
approximately 28 db at 400 mw. This is a numerical gain of 650 so the input power
required by the output stage is
Pin=~= 4oomw =.62mw
Gain 650
If the driver transformer is 75% efficient, the driver must produce
P drlYer _- P into output %
stage _ .62 mw _ 82 mw
- _ - ,
75 75
The remaining power gain to be obtained from the driver is 70 db - 28 db = 42 db.
From Figure 8.15 the 2N322 has a power gain of 42.5 db at a power output of .82 mw.
The output transformer primary impedance is obtained from Figure 8.6 on the
12 volt supply line at 400 mw output, and is 600 ohms maximum collector to collector
load resistance. Therefore a more standard 500 ohm CT output transformer may be
used with secondary impedance to match the load. From Figure 8.12 the driver trans-
former primary impedance is 40,000 ohms, but as low as a 20,000 ohm transformer can
be used and still have 42 db gain. The secondary must be center-tapped with a total
impedance of 800 to 5000 ohms. When this procedure is used for commercial designs,
it must be remembered that it represents full battery voltage, typical power gain and
input impedance, and therefore does not account for end-limit points. Figure 8.17 is a
circuit that uses the above design calculations.
1000 I
' I
DOO
....
" " ...
.... OESIGHQtART FOR
OUTPUTTRANSFCIAMER
I I I""

--
' r--.. IN CUSS 8 PUSIMI\U.
AUDIOAIIPUf'ERS ,...,.
"' '
·"'
l"'r,._

"-,
' ", ","~,.tr.,.
~,.
I "~
""-~ ..
.s,

~ ~
"'
......'(
,.... '
v~~~~ .... '
' ...
,__ ~~
"
,. ~<,i.;'-
i,.. "-.. ' '
' "r--.. " '~
~"'°<.i-1
"r--.., ' "I'." r---,
i,..~

"""
" "r-.. '~
IO 100 200 !!00

CCUECTOR TO COUECTOR LOAD-QIIIS

"-r--... '
IK 2K " !IK
I'-
....
IOK

DESIGN CHART FOR OUTPUT TRANSFORMER

IN CLASS B PUSH-PULL AUDIO AMPLIFIERS
Figure8.6

117
AUDIO AMPLIFIERS

a,

~-
I:;
~~ 200
400
300 j-....;;:: - -~
...........
--
............
..........
...........
r-,:::::__-
r-....
............
---- - ----
..........
....""-r--....
- ._M~X_!R
ACTICALPOWER
-i----
j.= .
2Nl4I3
~o: ........... ...... ..... - L--

-"....... -
Ir::? 100 r---.... ~ - l"'C'"
-
I
2Nll75
S!!i
f!:o '
'
' ...
'
80
' '\.
I
~~ 60 I'\.
' " ..... i- 2Nl4I4
Oin
o:- 40
'\. '- ' ,_
~ l"'C"
I
' "
•
II.I 2Nl4I5
30
~ 0 1=
'~

10 12 14 16 18 20 22 24 26 28 30 32 34
POWERGAIN-DECIBELS

TYPICAL POWER GAIN FOR CLASS B

PUSH-PULLAMPLIFIERS, 3.0 VOLT SUPPLY
Figure 8.7
1000
850 - --- --~- -............
r,.,..,_ ..........
,-
..__.

I'--... ........... ..........

.....
r--...~ ...........
...... ....
,-

..........
,-

....
'~
.... ....
--
i-
MAXRATEDPOWER

-r-
2Nl413

' ...
'-.
........ ........
~
["ii,.. "~
I-
I
'\ '\.
'
" L ..
.. '
'\.
~
'
i...--
-

-
2Nl414

I
' 2Nl415
' ' ''
\
' -
\
~

'\
\
I
\ \ \ 2Nll75

0
::
10 12 14 16 18 20 22 24 26 28 30 32 34
:~
I
POWERGAIN-DECIBELS

TYPICAL POWERGAIN FOR CLASS B

PUSH-PULLAMPLIFIERS,4.5 VOLT SUPPLY
Figure 8.8

i;
E
d
'~8
600
400
'300
~
-
- - - -- - -.........
..__
...........
r--...
...._
........ .....
~

.......... .......... ..........

r---...~
- ~

-
i_--
r-
MAX RATEDPOWER

2Nl41'3

" '- -
,___
..........
f
!5!!
200
' ~~
..... .....
"'\..
-~
~

i-
I
2Nl414
f!:0 100
g~
a:-
80
60
'

"''\
...
' '\
'
''
'
_,... --
I
2Nl415

I ;g \ \
' \.
"""'!;---- 2Nll75
I
0,2
~

14 16 18 20 22 24 26 28 30 32 34 36 I
POWER GAIN- OEaea.s

TYPICAL POWER GAIN FOR CLASS B

PUSH-PULL AMPLIFIERS, 6 VOLT SUPPLY
Figure 8.9

118
 AUDIO AMPLIFIERS

1ggg -- -- - -
--
600
._ -- ._ --._ ~-.__
.........
......
.......
........
....
........
.....
........
-1--
!!_AX RATED POWER

~,,,-- 2Nl413
400
300 " ' '-..
.......
'-..
r,....
" .......
'-..
"""r-...

'
'-..
./
/
,,,--
I
r--...
"
:>< 2Nl414
200 y

100
'\.
\
-
'\.
,,>,: " ,./
. ' ..- '.
'\. /
r\ I
2Nl415
' -
80
60
\
.\ \
~
...-£

I
40
30
0
26
\
\

28
I
I

30
""'
\
I

32
'I
r
34
i.---

~
2r
14 16 18 20 22 24
POWERGAIN-DECIBELS

TYPICAL POWERGAIN FOR CLASS B

PUSH-PULL AMPLIFIERS,9 VOLT SUPPLY
Figure 8.10

1000
850
600
400
-- -' I'..
....... .......
....
'"...
'

' "\.' "\. ' ' "\. ' '\.

.......
"-
-
.......
'"
~
~lnD
300
200 '\ "'\
\_ ~~
'\.
Ito. I'\
\
- -- 2Nl413

I
100
80
60
\
I
I ' I
'- '
I j_
-
--
- 2Nl414

I
2N14l5
I-.......
......
40 I I I
"-- "'-- I
2Nll75

•
:~ lj

20 22 24 26 28 30 32 34 36
POWER GAIN-DECIBELS

TYPICAL POWER GAIN FOR CLASS B

PUSH-PULL AMPLIFIERS, 12 VOLT SUPPLY
Figure 8.11

119
AUDIO AMPLIFIBRS

100 ...... ...

80 ... ...
60
'' '
'
"' "'\
40
" ' "' ...
'\ '
' '\ '\. '\

"' "'" I\
I\..
...

' I\
...,
'
'\.'rt"'~)-
r-..~,..
'\.p ~"'

"' ......
r'I,

',.t~ ~,,. ~)-

~
... ~ '6'~'tt"' ~)-......
... ' I'-.

~"' ~ ' '

I'~,>- "\
'\
', "''\.
f( "I\.. '\'
'\
' r-."
' ", ,,..."'' ''\. 'I\.
'\ i\ i\.
'\
LO
08
06
°too 200 400 sooeoo1K 2K
"' ...
''
4K
...
'
GK BK D<
I\.
r-.
''
...
' ...
"'201< I'\
'

'
50K

COLLECTOR
LOADRESISTANCE-OHMS

DESIGN CHART FOR OUTPUT TRANSFORMER

IN CLASS A SINGLE-ENDEDAMPLIFIER
Figure 8.12
__,.
----
-r
MAX RATEDPOWER
100 ·--MAX
- '
'
--r-~ ------
RATEDPOWER
--
l8-- -~ ,-.--~
'\
'\ '\ I'\'\ ----i---1i---
I\.
\ ' \ ' ''\
u,
40 "\ ' \ \ \ \
~ ,\ 1\
;--
::J~
20
\
\ \ \ \ \ 2Nll75

·~
di=
::10:
10
\ \ \ ..\ - /" ,_
.. - --
2N322
I I
~=
8 I
2Nl413
6 '1
,;' V
•
I
' ' r l/ .......
5.,, ''v1 \ ,;'
.... v-2,23
a:- 4 I
K _/

!
\./

l--\1.,K v ....I 2Nl414

2
\
\.,/ \ \ \ r'1 /
2N324
I I
T
1 \..rf1 "',/I /v I
1.0
. . --
2N508

- I
J
0.8
I I.I
0.6 '
I 'I I I I

0,4
: :
0
26 28 30 32 34 36 38 40 42 44
POWERGAIN-DECIBELS

TYPICAL POWER GAIN FOR CLASS A

SINGLE-ENDED AMPLIFIERS, 6 VOLT SUPPLY
Figure 8.13

120
 AUDIO AMPLIFIERS

efz
100
70
60
40

20
--
-- 1---
-.... --
--'- -~--~
......-- ...
l"<C'-

'

"'\
-,- ~ ....--
'\.
"'\

I\ '
\.

\ I\ I\\ I\\
' \ \' \'
-c

'\
\.
'\

'\
\
\ i\
'\
MAX RATED POWER
------,-- -.----
MAX RATEDPOWER
-------- -

_/✓
-r
2Nll75

::::iQ I\ \ ' I\\ V

V v-2N322
• I
. . ..
_/
d I;: 10 2Nl413
:E O 8 ' ' " ' ' I/
I
I
V /
I ...
5 \ \ \ \ 'I"\ _/
_.... 2N323
G.0
5
22
a'
6
4
'
\
.\. ~\ I/
K\ ' V
I 2Nl414
- .\"'' ~ / I
OU')
o::-
LLI
I\
\ \ ~
"_,v II /
i,..,--2N324
I
VT
~

T
2
G. \ \ \\'
1
1.0
~ r\~
0.8 \ \ ' ,,
0.6 '\ '\ '
\"
0.4 ::
!~
0
26 28 30 32 34 36 38 40 42 44 46
POWERGAIN-DECIBELS

TYPICAL POWER GAi N FOR CLASS A

SINGLE-ENDED AMPLIFIERS, 9 VOLT SUPPLY

-r
Figure 8.14
-- --
100 --..:- --
-- ~- -- --.--r-- MAX RATED
r..- ...
.....
---
POWER

l8-- -- -~- -~ ~ ...-\.- ~-- -------1--

' MAX RATED POWER
'----
'\ \. I\ ' \
2Nl175
\ \ \ \ \
/,,,,. I
\
\ 1
\
\
\\
\' \~/
1\ \
\ \

/
/
V
.v-2Ni22

--L.,,-2Ni23 I
I
2Nl413

\
'
\....l\-1\,.✓ V V I
/

I
I
2Nl414

I
~ ~

\ \/' \ \, ,I'\ ./
\ V\ \ \ \v J .... 2i24
r \ \ v1" \ I/
\ \At _,,.v I 2Nl415

VT
' L.,,\'
' \ IW.../
V

1 \\
I
\. \ \1
0.8
I I I
0.6 I I \ 11 I

0.4
:: :!:
0
2a 30 32 34 36 38 40 42 44 46 48
POWER GAIN- DECIBELS

TYPICAL POWER GAIN FOR CLASS A

SINGLE-ENDED AMPLIFIERS, 12 VOLT SUPPLY
Figure 8.15

121
AUDIO AMPLIFIERS

TRANSISTORS LISTED IN THE TOP ROW ARE PREFERRED TYPES AND SHOULD BE
USED IN ALL NEW DESIGNS. THEY CAN BE SUBSTITUTED FOR TYPES LISTED
BELOW THEM IN THE SAME COLUMN.

*2N322 *2N323 *2N324 *2N508 2Nl413 2Nl414 2Nl415 2Nll75

2Nl9O 2Nl91 2Nl92 2N265 2Nl87A 2Nl88A 2N241A 2Nl92

2Nl89 2Nl9O 2Nl91 2N324
2N319 2N32O 2N321
2N322 2N323
* THESE TYPES CAN NOT BE SUBSTITUTED IF APPLICATION REQUIRES
VcER> 16 VOLTS

PREFERRED
TYPES AND SUBSTITUTION CHART
Figure 8.16

INPUT

SW IZV

I O:.liMt
I
I I
L - - - - - - _J

R1,-- 220,000 OHM c,-8,.td, 12V

Rz.-- VOWM£ COHTROl. IOl>OO
OHM Cz-100..td, !IV MAXIMUMPOWER OUT AT 100/o
HARMONIC
DISTORTION-300 MW
112W AUDIOTAP£R C5, C..,-~,.td, 12V FOR USE Wint MAGNETIC CARTRIDGE
R5,--190.000 CHI Cs,-.Ol~fd OMIT R1
R4.- 10,POO OHM TR1,-GE.2N322
R5 ,-- 470 0tW mz,TR5;-G.£.2Nl415
Rg,--2200HM
T1--20K/2K CT
Tz--5000CT/ 'ltC.
R7,--27000HM
Re,--530HM ALL RESISTORS 1/2 W
ffs,Rac,r- IO OHM
Ru,-- 25K LINEAR

12 VOLT PHONO AMPLIFIER

Figure 8.17

122
 G.E.RELUCTANCE

HI LEVEL CARTRIDGE

TO SPEAKER

'-I..:~-----'"--' 9 VOLTS

'- - -
.___ ..... c_3_.,._ ___ RV7'\f'.,.---4.,_ _ _.,__..._..J\.IV\--_.,_A."V'.__.i~..._
-
___

__ J
-_
SW
:::J
FREQUENCY RESPONSE Ri,-5000 OHMVOLUME ~TROL
OF FOUR TRANSISTOR AMPLIFIER 1/2 W AUDIO TAPER R13,---47 OHM MAXIMUM POWER OUT AT 10% HARMONIC
R2,--uso,ooo OHM R14,Ris,-- 8.2 OHM OISTORTION-400MW
MAXIMUM BASS POSITION DISTORTION AT 100 MILLIWATTS
MAXIMUM TREBLE POSITION---------• R3,--470,000 OHM C1,C3,C7,Ce,-50~fd, 12V AT 100 C/S - 5-,,.
+5------------ R.4,--10,000 OHM C2,C6,--1501&fd 1 3V AT 1000 C/S-2%
R6,R9 1 -4700 OHM C4,----i 5,-dd, 12V
1
AT5000C/S-!5%
R7,--1000 OHM C5,---.021&fd
Re,--33,000 OHM TR1,TR2,-G.E.2N323
Ru,--25,000 OHM L1NEAR TR3,TR4,-G.E 2Nl415
R12,--220 OHM Ti,--- 5K/3K CT
-1!!,1---__._ __ __...___ _ ___, R51R10.-470 OHM T2,---2oon c.T.,v.c. ALL RESISTORS1/2 W

10 101 10• 104

AMPLIFIER LOADED WITH 3.ZJ\ VOICE
COIL SPEAKER RESONANCE @ 130 CPS

9 VOLT PHONO AMPLIFIER

Figure 8.18
...
~
N R13
~

R14 TR4
R10 t-V'A--, ~ I 0

i
t-C

+lei a=
CA

~RI
CRYSTAL
CARTRIDGE
INPUT

R1--10,ooc OHMS Ru---2200 OHMS C1--8mfd 6V

R2--1so,ooo OHMS R12--4700 OHMS C2-- .50 '"fd
R3--68000HMS R13--33,000 OHMS C3--.02 " PERFORMANCE DATA:
R4--SO,OOO OHMS R14--47,000 OHMS C4--.20 .. MAXIMUM POWER
LINEAR BASS R15--1500 OHMS c5--.oos .. OUTPUT@ 10%
R5--IOOO OHMS DISTORTIOiw---- 300 MW
R6--IO,OOO OHMS Ris--330 OHMS C&--,10 " DISTORTION AT
R7--IOO,OOOOHMS R17--220 OHMS C7-- IOmfd 6V 100 MILLIWATTS t
Re--50,000 OHMS R19--1200 OHMS C9--IOmfd " 60c/1-------~.o %
LINEAR R19--33 OHMS Cg--50mfd " IOOOc/1-------1.5 %
Rg--10,000 OHMS 5000c/s-------3,0 %
C10-- 50mfd "
TAPER AUDIO V.C.
R10-- 220,000 OHMS C11--50mfd ,.
T1--2K/1.5K CT
TR1,TR2,TR3-GE 2N323
TR4,TR5---GE 2Nl415 T2 100n c.T/V.C.
ALL RESISTORS1/2 W

6 VOLT PHONO AMPLIFIER

Figure 8.19
HIGH FIDELITY CIRCUITS

Transistors are ideally suited for high fidelity amplifiers since there is no problem
with microphonics or hum pick-up from filaments as there is with tubes. Transistors
are inherently low impedance devices and thus offer better matching to magnetic
pick-ups and loudspeakers for more efficient power transfer.
Transistor circuits with negative feedback can give the wide frequency response and
low distortion required for high fidelity equipment. In general, the distortion reduction is
about equal to the gain reduction for the circuit to which negative feedback is applied.
The input and output impedances of amplifiers with feedback are either increased or
decreased, depending on the form of feedback used. Voltage feedback, over one or
several transistor stages, from the collector decreases the output impedance of that
stage; whereas current feedback from the emitter increases the output impedance of
that stage. If either of these networks are fed back to a transistor base the input im-
pedance is decreased, but if the feedback is to the emitter then the impedance is in-
creased. The feedback can be applied to the emitter for effective operation with a low
generator impedance, whereas the feedback to the base is effective with a high imped-
ance (constant current) source. If the source impedance was low in the latter case then
most of the feedback current would How into the source and not into the feedback
amplifier. The feedback connections must be chosen to give a feedback signal that is
out-of-phase with the input signal if applied to the base, or in-phase if it is applied to
the emitter of a common emitter stage.
Care must be used in applying feedback around more than two transistor stages to
prevent high frequency instability. This instability results when the phase shift through
the transistor amplifiers is sufficient to change the feedback from negative to positive.
The frequency response of the feedback loop is sometimes limited to stabilize the cir-
cuit. At the present time, the amount of feedback that can be applied to some audio
power transistors is limited because of the poor frequency response in the common
emitter and common collector connections. The common collector connection offers the
advantage of local voltage feedback that is inherent with this connection. Local feed-
back (one stage only) can be used on high phase shift amplifiers to increase the fre-
quency response and decrease distortion.

PREAMPLIFIERS
Preamplifiers have two major functions: (1) increasing the signal level from a
pick-up device to about 1 volt rms, and (2) providing compensation if required to
equalize the input signal for a constant output with frequency.
The circuit of Figure 9.1 meets these requirements when the pick-up device is a
magnetic phono cartridge (monaural or stereo), or a tape head. The total harmonic
or I.M. (inter-modulation) distortion of the preamp is less than ½ % at reference level
output (1 volt).
This preamp will accommodate most magnetic pick-up impedances. The input im-
pedance to the preamp increases with frequency because of the frequency selective
negative feedback to the emitter of TRI. The impedance of the magnetic pick-ups will
also increase with frequency but are below that of the preamp.

125
 SWITCHPOSITIONS
7Q__q~y3 °7...
-=..9V
2 ±~
I TUNER OR MICROPHONE
19V

+
2 TAPE - 7 112• /SEC 0.01±.10°1.
3 TAPE - 3 3/4• /SEC
4 PHONO- RIAA

TAPE HEAD
OR
MICROPHONE
r-- 0.7 HENRY

1
I
I
~tr,:
OECODER 22K
OUTPUT
I 3V

L- ----'-----6
GE
VR-1000
STEREO
CARTRIDGE

PHONO-TAPEPREAMPLIFIER
Figure9.1
 HIGH FIDELITY CIBCUITS

The first two stages of this circuit have a feedback bias arrangement with R3
feeding bias current to the base of TRI that is directly proportional to the emitter
current of TR2. The output stage is well stabilized with a 5K emitter resistance. TR4
is used to stabilize the circuit bias conditions from 25° to 55°C (130°F) ambient and
also with variations in hn for TRI and TR2. Thus TR4 is not used as a signal ampli-
fier, but as a collector load resistor for TRI. Its resistance will decrease with either
increasing ambient temperature or increasing collector current from TRI. The increas-
ing collector current of TRI may be a result of either higher ambient temperature or
higher hn transistors. The collector to emitter resistance of TR4 will also decrease due
to the leakage current (loo) of TR4 itseH with increasing ambient temperature. The
stabilizing circuit (R2, R5, and R6) for TR4 was selected so that TR4 (as the collector
load for TRI) would have the desired temperature characteristic to stabilize the col-
lector voltage of TRI, with increasing ambient temperature up to I30°F. The collector
voltage of TRI is the base bias voltage for TR2, and TR2 biases TRI as indicated above.
TR4, in addition to its role as a temperature sensitive resistance, acts as a current
sensitive resistance and thus automatically adjusts its resistance for hn variations of
TRI and TR2 to maintain the collector voltage at TRI between .75 and 1.6 volts.
The AC negative feedback from the collector of TR2 to the emitter of TRI is
frequency selective to compensate for the standard NAB recording characteristic for
tape or the standard RIAA for phonograph records. The flat response from a standard
NAB recorded tape occurs with the Treble Control (R4) near mid-position or 12K
ohms (see Figure 9.2). There is about 5 db of treble boost with the Control at 25K and
approximately 12 db of treble cut with R4 =
0. Mid-position of the Treble Control
also gives Hat response from a standard RIAA recording. This treble equalization
permits adjustment for variations in program material, pick-ups, and loudspeakers.
+-10

-REFERENCE
I I
LEVEL (IVOLT)

----
r- R4• 25K

i
---...... R4~12K-

~-20

"' ~ R4• 0

TAPE HEAD-NORTAONICS AS0TK

VIKING TAPE DECK
TAPE SPEED 71/2' I SEC.

-50

>- - - - - - NOISE LEVEL~ 55 db BELOWREF"ERENCE

- - - - - - - -
-60 I I I I
50 IOO 500 tlCC 10 15KC

TAPE PREAMPLIFIER RESPONSEFROM NAB RECORDING

Figure9.2

The RIAA feedback network (with Treble Control at mid-position) has a net feed-
back resistance of 7 .5K to decrease the gain because of the higher level input. This
resistance has a .01 µf capacitor in parallel for decreasing the amplifier gain at the
higher frequencies in accordance with RIAA requirements. This eliminates the need to
load a reluctance pick-up with the proper resistance for high frequency compensation.
If it is desirable to build the preamplifier for phonograph use only, the compensating
feedback network would consist only of a .04 µf feedback capacitor in series with a
7.5K resistor (or a I0K Treble Control) which has a .01 µf capacitor in parallel.

127
HIGH FIDELITY CIBCUITS

The manufacturer of a piezoelectric pickup often has a recommended network

for converting his pick-up to a velocity device, so that it may be fed into an input
jack intended for a magnetic pickup.
The voltage feedback from the collector of TR2 decreases at lower frequencies
because of the increasing reactance of the feedback capacitor in series with the Treble
Control. In switch position #1 the capacitor C3 is large enough to make the voltage
feedback, and thus the gain, constant across the audio spectrum. This Bat preamp
response can be used with a tuner, F.M. decoder or microphone. The input impedance
to the preamp in #1 switch position is about 25K ohms, and 15 millivolts input level
gives I volt output. When used with an F.M. tuner or decoder the standard 75 micro-
second de-emphasis can be accomplished in this preamp by shunting the 7500 ohm
feedback resistor with .01 micro-farads.
In switch position #3 with the Treble equalization at 30K, the equalized response
is flat from 50 cycles to 7½ Kc with an NAB recording at 3¾" /second. The SIN
(signal-to-noise ratio) is 50 db.
The reference level for SIN measurements in tape recording is the maximum level
at which a 400 cycle signal can be recorded at 2 % harmonic distortion. In vacuum
tube circuitry there is a problem in maintaining high S/N at audio frequencies because
of the lower signal transfer from a magnetic pickup (tape, phono, or microphone) to
the tube grid. The lower input impedance of the transistor more nearly matches the
source for a better signal transfer and thus improved SIN.
A good SIN can be realized with a tape head inductance between .2 and I henry.
The .4 henry tape head gave a very flat response with this preamp (see Figure 9.2)
and a S/N of approximately 55 db. One has to be careful of the physical position of
the tape head or the noise output will increase considerably due to pick-up of stray
fields. For good SIN it is important that the tape head have good shielding and hum
bucking. The S/N is improved by the 100 ohm resistor in the emitter of TR2 which
reflects a higher input impedance for this stage and thus TRI has increased gain.
The preamp in the #2 (Tape at 7½" /sec.) position requires about 1.5 mv input
signal at I Kc for I volt output. Therefore a tape head with a I Kc reference level
output of 1.5 to 3 mv is desirable.
The emitter-follower output stage of the preamp gives a low impedance output for
a cable run to a power amplifier (transistor or tube) and acts as a buffer so that any
preamp loading will not affect the equalization characteristic.
The Treble Control should have a linear taper and the Level Control an audio
taper. Two 9 volt batteries will give good life in this application since the total supply
drain is approximately 4 ma DC. This 18 volts may also be obtained by suitable decou-
pling from a higher voltage supply with an 18 volt zener.
This is a high gain circuit and thus care should be used in layout to prevent
regenerative feedback to the input. Also, a switching circuit at the input will increase ·
the possibilities for hum pick-up and thus decrease the SIN.

BASS BOOST CIRCUIT

The bass boost circuit of Figure 9.3 operates on the output of the preamp (Figure
9.1). With this addition, the operator has the necessary treble and bass control to com-
pensate for listening levels, or deficiencies in program material, pick-up, speakers, etc.
This bass boost circuit gives the operator independent control of the level, or amount
of bass boost desired, or the level control can be used as a loudness control.
It is usually desirable to have some method of boosting the level of the lower

128
 HIGH FIDELITY CIRCUITS

+-- BASS BOOST

INPUT

0.7 HENRY
son o.c.
II MAXIMUM
5K

OUTPUT

BASS BOOST CIRCUIT

Figure9.3

portion of the audio spectrum as the overall sound level is decreased. This is to com-
pensate for the non-linear response of the human ear as shown in the Fletcher-Munson
curves that are often referred to in the audio industry. The ear requires a higher level
for the low frequency sound to be audible as the frequency is decreased and also as
the overall spectrum level is decreased.
Figure 9.4 shows the frequency characteristics of this bass boost circuit. With the
level control set for zero attenuation at the output there is no bass boost available, but
as the output level is attenuated, the available bass boost increases.

0 OdbLEVEL-

'.a
!, -10 t------
ww
~~
:..Ji-
g 5 -20 ~ -------- - r---.... MAX] BASE BOOST
MIN.
AT-20db
LEVEL -

~
I- >
:::::,I-
Q. :::::,
~ ~ -30
-........_____
o-

-40
-- J
MAX
MIN.
BASE BOOST
AT-40db
LEVEL -

30 100 IKC 15KC

FREQUENCY RESPONSEOF BASS BOOST CIRCUIT

Figure9.4
Figure 9.4 shows the frequency response (lower dashed curve) when the output is
attenuated 40 db and the Bass Boost Control is set for minimum (50K ohms). The solid
curve immediately above represents the frequency response when the Bass Boost Con-
trol is set at maximum (zero ohms). Thus a frequency of 30 cycles can have anything

129
ffiGH FIDELITY CIRCUITS

from zero to 27 db of boost with respect to 1 KC, depending on the adjustment of the
Bass Boost Control.
The Fletcher-Munson contours of equal loudness.level show most of the contour
changes involve a boost of the bass frequencies at the lower levels of intensity. There-
fore, this circuit combination fulfills the requirements of level control, bass boost and
loudness control. The Bass Boost Control may be a standard SOKpotentiometer with a
linear taper. The desired inductance may be obtained by using the green and yellow
leads on the secondary of Argonne transistor transformer #AR-128 (Lafayette Radio
Catalog).

POWERAMPLIFIERS
It is difficult to attain faithful reproduction of a square wave signal with a trans-
former amplifier. A high quality transformer is required and it must be physically
large to have a good response at the low frequencies. Thus, a great deal of effort has
gone into developing transformerless push-pull amplifiers using vacuum tubes. Prac-
tical circuits, however, use many power tubes in parallel to provide the high currents
necessary for direct-coupling to a low impedance load such as loudspeakers.
The advent of power transistors has sparked new interest in the development of
transformerless circuits since the transistors are basically low voltage, high current
devices. The emitter follower stage, in particular, offers the most interesting possibili-
ties since it has low inherent distortion and low output impedance.
Figure 9.5 is a direct-coupled power amplifier with excellent low frequency re-
sponse, and also has the advantage of D.C. feedback for temperature stabilization of
all stages. This feedback system stabilizes the voltage division across the power output
transistors TR4 and TR5 which operate in a single-ended Class B push-pull arrange-
ment. TR2 and TR3 also operate Class B in the Darlington connection to increase the
current gain. Using an NPN for TR3 gives the required phase inversion for driving
TRS and also has the advantage of push-pull emitter follower operation from the out-
put of TRI to the load. Emitter follower operation has lower inherent distortion and
low output impedance because of the 100% voltage feedback.
,-----4....,,tJVV-~---.,._---------0-411V

10-WATT AMPLIFIER
Figure9.5

130
 mGH FIDELITY cmCUITS

TR4 and TR5 have a small forward bias of 10 to 20 ma to minimize cross-over

distortion and it also operates the output transistors in a more favorable beta range.
This bias is set by the voltage drop across the 390 ohm resistors that shunt the input to
TR4 and TR5. TR2 and TR3 are biased at about 1 ma (to minimize crossover distor-
tion) with the voltage drop across the two 1N91 germanium diodes. The junction
diodes have a temperature characteristic similar to the emitter-base junction of a tran-
sistor. Therefore, the two diodes also give compensation for the temperature variation
of the emitter-base resistance of TR2, TR4 and TR3. These resistances decrease
with increasing temperature, thus the decrease in forward voltage drop of approxi-
mately 2 millivolts/ degree centigrade for each of the diodes provides temperature
compensation.
The 470 resistor in the emitter of TR3 aids the stabilization of this transistor stage
and also decreases distortion through local feedback.
TRI is a Class A driver with an emitter current of about 3 ma. Negative feedback
to the base of TRI lowers the input impedance of this stage and thus requires a source
impedance that is higher so the feedback current will How into the amplifier rather
than into the source generator. The resistor Rl limits the minimum value of source
impedance. The bias adjust R2 is set for one-half the supply voltage across TR5.
About 11 db of positive feedback is applied by way of C3 across R5. This boot-
strapping action helps to compensate for the unsymmetrical output circuit and permits
the positive peak signal swing to approach the amplitude of the negative peak. This
positive feedback is offset by about the same magnitude of negative feedback via R2
and R3 to the base of TRI. The net amount of negative feedback is approximately
14 db resulting from R12 connecting the output to the input. In addition, there is the
local feedback inherent in the emitter follower stages. The value for the C2 feedback
capacitor was chosen for optimum square wave response (i.e., maximum rise time
and minimum overshoot).
A ½ ampere fuse is used in the emitter of each output transistor for protective
fusing of TR4 and TR5, and also to provide local feedback since the ½ ampere type
AGC or 3AG fuse has about 1 ohm D.C. resistance. This local feedback increases the
bias stability of the circuit and also improves the declining frequency response of TR4
and TR5 at the upper end of the audio spectrum. Because of the lower transistor effi-
ciency above 10 Kc, care should be used when checking the amplifier for maximum
continuous sinewave output at these frequencies. If continuous power is applied for
more than a short duration, sufficient heating may result to raise the transistor current
enough to blow the ½ A fuses. There is not sufficient sustained high frequency power
in regular program material to raise the current to this level. Thus the actual perform-
ance of the amplifier does not suffer since the power level in music and speech declines
as the frequency increases beyond about 1 to 2 Kc.
The speaker system is shunted by 22 ohms in series with .2 µ.fd to prevent the
continued rise of the amplifier load impedance and its accompanying phase shift
beyond the audio spectrum.
The overall result, from using direct-coupling, no transformers, and ample degen-
eration, is an amplifier with output impedance of about 1 ohm for good speaker damp-
ing, low distortion, and good bandwidth. The power response at 1 watt is flat from
30 cycles to 15 KC and is down 3 db at 50 KC. At this level the total harmonic and
I.M. distortion are both less than 1 % . At 7 watts the I.M. distortion is less than 2½ %
and the total harmonic distortion is less than 1 % measured at 50 cycles, 1 KC, and
10 KC. The performance of the amplifier of Figure 9.5 is about equal for both 8 and
16 ohm loads.

131
HIGH FIDELITY CIRCUITS

This ampli6er is capable of about 8 watts of continuous output power with I volt
r.m.s. input, or 10 watts of music power into 8 or 16 ohms when used with the power
supply of Figure 9.6. This power supply has diode decoupling which provides excellent
separation (80 db) between the two stereo amplifier channels.
STANCOR
IA
I.. o--.--u-----. RT-201--o------.
8

II

ll7VAC

-=
Cl,C2, 8i C3-1500~f, 50V.

POWER SUPPLY FOR STEREO SYSTEM

Figure9.6

The power transistors TR4 and TRS should each be mounted on an adequate heat
radiator such as used for transistor output in an automobile radio, or mounted on a
3" x 3" x %2" aluminum plate that is insulated from the chassis.

STEREOPHONIC
SYSTEM
A complete semiconductor, stereophonic playback system may be assembled by
using the following circuits in conjunction with a stereophonic tape deck or phono
player.

10 WATT
PREAMP POWER a OR,sn
TRACK FIG. 9.1 AMP
FIG.9.5
STEREO
TAPE POWER
DECK
OR
PHONO
.--±11!~11-
_J_ 1
9V 9V
SUPPLY
FIG.9.6
PLAYER
10 WATT
#2 PREAMP POWER 8 OR16Sl
TRACK FIG. 9.1 AMP
FIG.9.5

BLOCK DIAGRAM OF STEREOPHONICSYSTEM

Figure9.7

132
 HIGH FIDELITY cmCUITS

SILICON POWERAMPLIFIERS
Some of the transistor power amplifiers to date have been lacking in their high
frequency performance and their temperature stability. The diffused junctions of the
2N2107 and 2N2196 permit good circuit performance at high frequency. Silicon tran-
sistors are desirable for power output stages because of their ability to perform at much
higher junction temperatures than germanium. This means smaller heat radiating fins
can be used for the same power dissipation. On the negative side, silicon has higher
saturation resistance which gives decreased operating efficiency that becomes appre-
ciable when operating from low voltage supplies.
The power handling capability of a transistor is limited by both its electrical and
thermal ratings. The electrical rating limit is a function of the transistor's voltage
capability, and its maximum current at which the current gain is still usable. The
themml rating is limited by the transistor's maximum junction temperature. Therefore,
it is desirable to provide the lowest thermal impedance path that is practical from
junction to air. The thermal impedance from junction to case is fixed by the design
of the transistor; thus it is advantageous to achieve a low thermal impedance from
case to the ambient air.
The 2N2107 and 2N2196 are NPN diffused silicon transistors. They will be
limited in their maximum power handling ability by the thermal considerations for
many applications unless an efficient thermal path is provided from case to air.
These transistors are constructed with the silicon pellet mounted directly on the
metal header, and therefore it is more efficient to have an external heat radiator in direct
contact with this header than to make contact with the cap of the transistor package.

NOTE: APPLY A LAYER OF G.E. SILICONE

DIELECTRIC GREASE it SS- 4005
OR EQUIVALENT BETWEEN THE
TRANSISTOR AND THE FIN.

WASHER {APPROX. 3/4" O.D.

LD.=.3475± .0125

ALUMINUM FIN
(ORl/16'1COPPER)

~13/64

DIA HOLES

FIN ONLY

TRANSISTOR HEAT RADIATOR

Figure9.8

Figure 9.8 shows a practical method for achieving a maximum area of direct con-
tact between the metal header and an aluminum fin for efficient heat transfer to the
surrounding air. A plain washer with two holes drilled for the mounting hardware is

133
mGH FIDELITY cmCUITS

simple but quite adequate for securing the transistor header to the fin. Since air is a
relatively poor thermal conductor, the thermal transfer can be improved by applying
a thin layer of G-E Silicone Dielectric Grease #SS-4005 or equivalent between the
transistor and the radiating fin before assembly. The fin may be anodized or flat paint
may be used to cover all the surface except for the area of direct contact with the
transistor header. An anodized finish would provide the insulation needed between
the base and emitter leads and the sides of the feed-through holes in the aluminum
fin. Figure 9.9 shows a thermal rating for the 2N2107 as assembled on the radiating fin.

,,
.'
I THERMAL RESISTANCE
I
R1 11 25°C/WATT

'
I
I
I
I"-
I
'r-....
I
I
I
',
' I"
I
I

.
I

I ,
.........
I
I
i
',
20
I

40 60
AMBIENT
80 100
TEMPERATURE - °C
120
'
140 160

THERMAL
CHARACTERISTIC
Figure9.9
+~v
[email protected]
112A
I TYPE AGC DR 3AG)

NOTE'.ALL RESISTORS 1/2 WATT

111'1
LOAD

RIZ
UK

10-WATTAMPLIFIER
Figure 9.10

134
 IDGH FIDELITY cmcurrs

The circuit of Figure 9.10 is very much like that described for Figure 9.5. The
opposite polarity is used for transistors, capacitors, and supply voltage. The 1N91
connected to the emitter of TR4 gives additional stabilization for this stage for varia-
tions in transistor beta and temperature. The forward voltage drop of this germanium
diode must be offset by D4 to minimize cross-over distortion. The 1N91 diode at the
base of TRS has a leakage current which increases with temperature in a manner
similar to the lco of TR3. D3 can thus shunt this temperature sensitive current to
ground, whereas, if it were to flow into the base of TR5, it would be amplified in the
output stages.
This circuit has about 20 db of overall negative feedback with Rl2 connecting
the output to the input. The higher hFEof the two output units should be used for TR4.
The silicon power ampliner of Figure 9.10 has an output impedance of .50 for
good speaker damping. The square wave response shown in Figure 9.11 is indicative
of an amplifier with a good transient response and also a good bandwidth. The band-
width is confirmed by the response curve of Figure 9.12. The power response at
5 watts output is Hat within ¾ db from 30 cycles to 15 Kc. The amplifier exhibits good
recovery from overload, and the square wave peak power output without distorting the
waveform is 12 watts.

2 KCSQUAREWAVE RESPONSE
Figure9.11
+2

I I I
I
Odb • 1/2 WATT
- r---....
~-2
~
0
' " :'
I\.

a:-4

•
"'
0
Q.-6
I
3~b
I'
I
J.,
~
:::
T
10 20 100 IKC IOKC 67KC IOOKC

FREQUENCYRESPONSE
Figure9.12

The 2N2107 output transistors, TR4 and TR5, were mounted on heat dissipating
fins as shown in Figure 9.8 and the amplifier operated successfully delivering 1 watt
rms 400 _, continuous power to the load with no increase in total harmonic distortion

135
IDGH FIDELITY cmcurrs

from room ambient of 75°F to 175°F (approx. 80°C). At 175°F the DC voltage across
TR5 had decreased less than 15% from its room ambient value. Operation at higher
temperatures was not attempted because of TR3 being a germanium transistor which
has a maximum operating junction temperature of 85°C.
When operated with the 2N2107 heat radiator assembly, this amplifler can safely
deliver up to 10 watts rms of continuous power to the load at room temperature. When
driving a loudspeaker with program material at a level where peak power may reach
10 watts the rms power would generally be less than 1 watt. This amplifier, when
operated with 2N2196's in the outputs, can be mounted on a smaller 2" x 2" fin because
of its increased power capabilities. The 2N2196 has a case that simplifies the mounting
on a heat radiator, and it has electrical characteristics that equal or excel the 2N2107
for this application.
The 1.M. and total harmonic distortion of this amplifier is less than ½ % at power
levels under 3 ½ watts. The total harmonic distortion measured at 50 cycles, 400 cycles,
and 10 Kc is still under 1% at 6 watts output and the I.M. distortion under 2½ %. An
nns input signal of 1 ¼ volts is required for 8 watts continuous output with a supply
furnishing 350 ma at 48 volts. This amplifier has a IO-watt music power rating when
used with the power supply of Figure 9.13. The amplifier operates with an efficiency
of 47 to 60% and has a signal-to-noise ratio of better than 98 db.

IN91

49V AMPLIFIER#2

+
C2 22K
l/2W

Cl,C2,8 C3-l~l,!50V

POWER SUPPLY FOR STEREO SYSTEM

Figure9.13

The above performance tests were with a 160 resistive load. The performance
near maximum power output will vary slightly with transistors of different beta values.
Varying values of saturation resistance for the output transistors TR4 and TR5 also
affect the maximum power output.

--
...
-- -i-...

' -Pc,VS:RL
'r-,....
~
r--
-- r-
-- ~

'r-... /-,wATT ' DISTORTION

vs:RL
i-....
_,.....
0 ID 20 30 4J l)O til.J fU 80 ~ ~ I
LOAD (RLIN OHMS)

AMPLIFIER PERFORMANCEVS. LOAD

Figure9.14

136
 IDGH FIDELITY CIRCUITS

Figure 9.14 shows the load range for maximum performance. It indicates that for a
varying load impedance such as a loudspeaker, the most desirable range is 16 to 400.
A 16!2speaker system is in this range. A 20 to 6000 auto-transformer should be used
for driving a 6000 line.

12-WATTAMPLIFIER
The amplifier of Figure 9.10 is limited in its maximum power output by the supply
voltage and the saturation resistance of the output transistors, TR4 and TRS. The
supply voltage can not be increased much beyond 50 volts at maximum amplifier signal
swing without making the Vct: rating for TRI marginal. Under these conditions the
saturation resistance becomes the limiting factor for obtaining increased power output.
The circuit of Figure 9.15 uses two transistors in parallel for each of the outputs.
This enables the saturation resistance to be reduced in half and gives 12 watts output.
The .47 ohm resistor used in the emitter of the paralleled transistors gives a more
uniform input characteristic for sharing of the input currents. These emitter resistors
also give increased bias stabilization. The rest of the circuit is the same as Figure 9.10
except the 1N91 (D4) is not used in the collector of TRI since there is no diode voltage
to offset in series with output emitter.

+50V (ii)358ma
1/2 A (TYPE AGC OR 3AG)

NOTE: ALL RESISTORS 1/2 WATT

C3 +
2O,,.f TR4 a TR6
50V - 2N21O7'S

cs
1500,if
50V
r--.---1)---1-----+-----+--;;.;;...--+-----I+ t--------o 1sn
LOAD

Cl
2Opf
20V 22
RII
o---l t--"V\.rv--.---+---t-1 TRS BTR7
2N21O7'S

Rl6 .2
.47 C6

Rl2
33K

12-WATT AMPLIFIER
Figure 9.15

137
HIGH FIDELITY CIRCUITS

The performance of the 12-watt circuit is like that given previously for the circuit
of Figure 9.10 except for the distortion vs.: power output. Figure 9.1 indicates the
increased power output and also the lower distortion which is a second advantage of
parallel operation of the outputs. Lower distortion results from parallel operation since
the signal current swing in each transistor is approximately half ed and thus confined
to the more linear portion of the transfer characteristic.

I I I I
HARMONIC
z 1.5 INTERMODULATION - - -
0
j::: {6KC
AND
a: /. 60~_
~ 1.0
fl) IOKC~/
0
50~
~ 0.5 ~ / IKC-
-=-=-- -~
0
--1- -~
2 3 4 5 6 7 8 9 10 II 12
POWER OUTPUT (WATTS)

DISTORTIONVS. POWEROUTPUT
Figure9.16

The amplifier of Figure 9.15 operates at maximum power output with an efficiency
of 67%. This circuit can be packaged with a minimum volume and weight without
component crowding, see Figure 9.17. One of the paralleled output transistors uses
the technique described in Figure 9.8 and the other makes for simplified mounting
using the 2N2196 that was discussed previously. All four of the output transistors
could be 2N2107's or all 2N2196's. Each mounting fin is %2" x 1½" x 4½" aluminum.

12-WATTAMPLIFIER
Figure9.17

138
 HIGH FIDELITY cmCUITS

If the amplifier is powered by the supply of Figure 9.13, it will provide 10 watts
of continuous output or 12 watts at Music Power Rating.
Either one of the amplifiers described will give superb performance in a stereo
system when used to drive a 16fl speaker that has at least moderate sensitivity.

NPN PREAMPLIFIER
The preamplifier of Figure 9.18 is similar to that of Figure 9.1 except NPN tran-
sistors are used and the first stage does r.ot have a compensating collector load. This
first stage does not require a temperature sensitive resistance for the collector load since
a planar - passivated transistor is used which inherently has very low leakage current
(lcBo).This preamplifier will operate at even higher ambient temperature than that of
Figure 9.1 and has equivalent overall performance including 55 db S/N. 1.2 millivolts
of input signal gives 1 volt output at 1 Kc. The input impedance is approximately
39K at 1 Kc. The equalized output from an NAB recorded tape at 71/z"/sec. is within
± 1 db from 50 cycles to 15 Kc using a .4 henry tape head. The higher input imped-
ance of this preamp gives the best equalized output for a tape head in the .4 to 1 henry
range. The value of R3 is selected or adjusted to give approximately 1¼ volts D.C. at
the base of TR2 to accommodate the production spread of hn for transistors used in
the first two stages. A switch can be added to give other equalized functions as in
Figure 9.1.

v---~ .... --------------n+1av

1.5K

20J&f +
20VI
TR3
2Nl304

._,_ BASS BOOST

0,7 HENRY
5oQMAX.D.C.

20Pf 11
20V

OUTPUT

TAPE PREAMPLIFIER
Figure 9.18

139
IDGH FIDELITY CIRCUITS

A complete semiconductor, stereophonic tape playback system may be assembled

by using the following circuits in conjunction with a stereophonic tape deck.

12 WATT
PREAMP POWER
AMP 1&n
TRACK FIG. 9.18
FIG.9.15
STEREO
TAPE POWER
DECK SUPPLY
FIG.9.13

Ii? WATT
#2 PREAMP POWER 1&n
TRACK FIG. 9.18 AMP
FIG.9.15

BLOCK DIAGRAMOF STEREOPHONICSYSTEM

Figure 9.19

REFERENCES
Jones, D.V., "Class B Power Amplifier Performance with Silicon Transistors," Audio Engineering
Society Convention Paper, presented October 1960.
Geiser, D.T., "Using Diodes as Power Supply Filter Elements," Electronic Design, June 10, 1959.
Jones, D.V., "All Transistor Stereo Tape System.'' Electronics World, July 1959,

140
RADIO RECEIVER
AND TUNER CIRCUITS

AUTODYNE CONVERTERCIRCUITS
The converter stage of a transistor radio is a combination of a local oscillator, a
mixer and an IF amplifier. A typical circuit for this stage is shown in Figure 10.1.
15K'.500O
AUTOMATIC 725
llC=l90.6)1pF r- - - -1
I

FOR ADDITIONAL INFORMATION SEE PAGE 154

AUTODYNE
CONVERTER
Figure10.1
Redrawing the circuit to illustrate the oscillator and mixer sections separately, we
obtain Figures 10.2 and 10.3.

_______ _....,__ ___ +9V

PRIMARY
SECONDARY
Figure 10.3
..,_ ______________ -o+9V

Figure10.2
The operation of the oscillator section (10.2) is as follows:
Random noise produces a slight variation in base current which is subsequently
amplified to a larger variation of collector current. This A.C. signal in the primary of
L2 induces an A.C. current into the secondary of L11tuned by Cs to the desired
oscillator frequency. C:i then couples the resonant frequency signal back into the
emitter circuit. If the feedback (tickler) winding of L, is properly phased the feedback
will be positive (regenerative) and of proper magnitude to cause sustained oscillations.
The secondary of L2 is an auto-transformer to achieve proper impedance match be-
tween the high impedance tank circuit of L2 and the relatively low impedance of the
emitter circuit.

141
RADIO RECEIVER AND TUNER cmcUITS

Ci effectively bypasses the biasing resistors R2 and Rs to ground, thus the base is
A.C. grounded. In other words, the oscillator section operates essentially in the
grounded base configuration.
The operation of the mixer section (10.3) is as follows:
The ferrite rod antenna L1 exposed to the radiation field of the entire frequency
spectrum is tuned by CAto the desired frequency (broadcast station).
The transistor is biased in a relatively low current region, thus exhibiting quite
non-linear characteristics. This enables the incoming signal to mix with the oscillator
signal present, creating signals of the following four frequencies:
1. The local oscillator signal.
2. The received incoming signal.
3. The sum of the above two.
4. The difference between the above two.
The IF load impedance T 1 is tuned here to the difference between the oscillator
and incoming signal frequencies. This frequency is called the intermediate frequency
(I.F.) and is conventionally 455 KC/S. This frequency will be maintained fixed since CA
and Co are mechanically geared (ganged) together. ~ and Ca make up a filter to pre-
vent undesirable currents flowing through the collector circuit. C2 essentially bypasses
the biasing and stabilizing resistor R1 to ground. Since the emitter is grounded and
the incoming signal injected into the base, the mixer section operates in the "grounded
emitter" configuration.

IF AMPLIFIERS
A typical circuit for a transistor IF amplifier is shown by Figure 10.4.

+9V
Figure10.4

The collector current is determined by a voltage divider on the base and a large
resistance in the emitter. The input and output are coupled by means of tuned IF
transformers. The .05 capacitors are used to prevent degeneration by the resistance
in the emitter. The collector of the transistor is connected to a tap on the output
transformer to provide proper matching for the transistor and also to make the per-
formance of the stage relatively independent of variations between transistors of the
same type. With a rate-grown NPN transistor such as the 2N293, it is unnecessary
to use neutralization to obtain a stable IF amplifier. With PNP alloy transistors, it
is necessary to use neutralization to obtain a stable amplifier and the neutralization
capacitor depends on the collector capacitance of the transistor. The gain of a tran-
sistor IF amplifier will decrease if the emitter current is decreased. This property
of the transistor can be used to control the gain of the IF amplifier so that weak
stations and strong stations will produce the same audio output from a radio. Typical

142
 RADIO RECEIVER AND TUNER CIRCUITS

circuits for changing the gain of an IF amplifier in accordance with the strength
of the received signal are explained in the A.V.C. section of this chapter.
A.V.C. is a system which automatically varies the total amplification of the signal
in a radio receiver with changing strength of the received signal carrier wave.
From the definition given, it would be correctly inferred that a more exact term
to describe the system would be automatic gain control (A.G.C.).
Since broadcast stations are at different distances from a receiver and there is a
great deal of variation in transmitted power from station-to-station, the field strength
around a receiver can vary by several orders of magnitude. Thus, without some sort
of automatic control circuit, the output power of the receiver would vary considerably
when tuning through the frequency band. It is the purpose of the A.V.C. or A.G.C.
circuit to maintain the output power of the receiver constant for large variations of
signal strengths.
Another important purpose of this circuit is its so-called "'anti-fading" properties.
The received signal strength from a distant station depends on the phase and amplitude
relationship of the ground wave and the sky wave. With atmospheric changes this
relationship can change, yielding a net variation in signal strength. Since these changes
may be of periodic and/or temporary nature, the A.V.C. system will maintain the
average output power constant without constantly adjusting the volume control.
The A.V.C. system consists of taking, at the detector, a voltage proportional to the
incoming carrier amplitude and applying it as a negative bias to the controlled amplifier
thereby reducing its gain.
In tube circuits the control voltage is a negative going DC grid voltage creating
a loss in transconductance (Gm).
In transistor circuits various types of A.V.C. schemas can be used.
EMITTER CURRENT CONTROL
As the emitter current of a transistor is reduced (from 1.0 ma to .1 ma for instance)
various parameters change considerably (see Figure 10.5).
IO

v~ • !I• I
.·
11...__
, ........ ,, ' I
I/ I I I

2
' ', /
/
I
i
I
":-..
', / -1---' .... m1!
... --...'
I
..__ .,. ...,
..,..,,.,.,_
..,,
__.,,,,
I
' r-...
GND ....._
[lllffUt-

Figure 10.5 i---- ~

I
~:-
2

.5 I 2
I,o
UIITTUII OIAS,IIA.
C•,UACTERISTICS VS. EMITTIII CIIRRl • f

The effect of these changes will he twofold:

1. A change in maximum available gain and
2. A change in impedance matching since it can be seen that both ho,,
and hu vary radically.
Therefore, a considerable change in power gain can he obtained as shown by
Figure 10.6.

143
:R uIO RECEIVER AND TUNER CIBCUITS

db
34

32
_i---- .....- Vc1•9v

--I'--..
30

28
/ v -- Ve1 .15v I'-, C\

26
V/ \
~v
24
//
...
...
22
17
GE 2NI087
AGC CURVE
I 20
%
~ 18
// POWER GAIN VS EMITTER CURRENT
INPUT MATCHED AT IE • Ima

a:
~ 16
II OUTPUT TUNED AT 455 KC
ZLOAO• ISl<J\;V, r • 5 VOLTS

D. 14 I/
12

IO

.04 2 .4 .6 B I 4 6 8
EMITTER CURRENT- ma

Figure10.6

On the other hand, as a result of Ico (collector leakage current) some current always
flows, thus a transistor can be controlled only up to a point and cannot be "cut-off"
completely. This system yields generally fair control and is, therefore, used more than
others. For performance data see Figure 10.7.
EMITTER CURRENT
PLUS AUXILIARY A.V.C DIODE
+6
+4 ~/
I
+2 .i
IDEAL CURVE ,✓•
0
..... .,,,,-•-"

- - - - --..._ /EMITTER CURRENT

m -2 ....,_ CONTROL ONLY
Q
'- (OVERLOAD
OBTAINABLE
~ -4 '\ ABOVE .IV/m
CURVE
I- \ YIELDS DISTORTION)
:,
0.. -6 \
I- \
::)
0 -9
a::
l&J
3: -10
0
a.
-12
-14

-16

-18
0.0001 0.001 0.01 0.1 1,0

SIGNAL STRENGTH IN VOLTS /METER

Figure10.7
AUXILIARY A.V.C. SYSTEMS
Since most A.V.C. systems are somewhat limited in performance, to obtain im-
proved control, auxiliary diode A.V.C. is sometimes used. The technique used is to
shunt some of the signal to ground when operating at high signal levels, as shown by
Figure 10.8.

144
 RADIO RECEIVER AND TUNER CIRCUITS

CR

Tz

0 0
nd ~,

---"\/V\,-----OA,V-C
FROMDETECTOR
½c
Figure10.8

In the circuit of Figure 10.8, diode CR1 is back-biased by the voltage drops across
R1 and R2 and represents a high impedance across T1 at low signal levels. As the signal
strength increases, the conventional emitter current control A.V.C. system creates a
bias change reducing the emitter current of the controlled stage. This current reduction
coupled with the ensuing impedance mismatch creates a power gain loss in the stage.
As the current is further reduced, the voltage drop across R2 becomes smaller thus
changing the bias across CR1. At a predetermined level CR1 becomes forward biased,
constituting a low impedance shunt across T1 and creating a great deal of additional
A.V.C. action. This system will generally handle high signal strengths as can be seen
from Figure 10.7. Hence, almost all radio circuit diagrams in the circuit section of this
manual use this system in addition to the conventional emitter current control.

DETECTOR
STAGE
In this stage (see Figure 10.9), use is made of a slightly forward biased diode in
order to operate out of the square law detection portion of the I-E characteristics. This
stage is also used as source of AGC potential derived from the filtered portion of the
signal as seen across the volume control (R9). This potential, proportional to the signal
level, is then applied through the AGC filter network C4, R7 and CS to the base of the
1st IF transistor in a manner to decrease collector current at increasing signal levels.
RS is a bias resistor used to fix the quiescent operating points of both the 1st IF and the
detector stage, while C6 couples the detected signal to the audio amplifier. (See
Chapter 8 on Audio Amplifiers.)

AVC Rg TO AUDIO
AMPLIFIER
TO COLD SIDE OF 1st LF.
TRANSFORMER
Re

Figure 10.9

145
RADIO RECEIVER AND TUNER CIRCUITS

REFLEX CIRCUITS
"A reflex amplifier is one which is used to amplify at two frequencies - usually
intermediate and audio frequencies,"*
The system consists of using an I.F. amplifier stage and after detection to return the
audio portion to the same stage where it is then amplified again. Since in Figure 10.10,

Figure 10.10 BLOCI( DIAGRAMOF RECEIVER

two signals of widely different frequencies are amplified, this does not constitute a
"regenerative effect" and the input and output loads of these stages can be split audio
-1.F. loads. In Figure 10.11, the I.F. signal (455 Kc/s) is fed through T2 to the detector
circuit CRI, C3 and RS. The detected audio appears across the volume control RS
and is returned through C4 to the cold side of the secondary of Tl.
• -

Figure 10.11
..r AUDIO
OUTPUT

D Pl.US
Since the secondary only consists of a few turns of wire. it is essentially a short
circuit at audio frequencies. Cl bypasses the I.F. signal otherwise appearing across
the parallel combination of RI and R2. The emitter resistor R3 is bypassed for both
audio and I.F. by the electrolytic condenser C2. After amplification, the audio signal
appears across R4 from where it is then fed to the audio output stage. CS bypasses R4
for I.F. frequencies and the primary of T2 is essentially a short circuit for the
audio signal.
The advantage of "reflex" circuits is that one stage produces gain otherwise
requiring two stages with the resulting savings in cost, space, and battery drain. The
disadvantages of such circuits are that the design is considerably more difficult,
although once a satisfactory receiver has been designed, no outstanding production
difficulties should be encountered. Other disadvantages are a somewhat higher amount
of playthrough (i.e. signal output with volume control at zero setting), and a minimum
volume effect. The latter is the occurrence of minimum volume at a volume control
setting slightly higher than zero. At this point, the signal is distorted due to the
• F. Langford-Smith, Radiotron Designers Handbook, Australia, 1953, p. 1140

146
 RADIO RECEIVER AND TUNER cmcurrs

balancing out of the fundamentals from the normal signal and the out-of-phase play-
through component. Schematics of complete receivers will be found at the end of this
chapter and in Chapter 20.

FMTUNER
The FM tuner shown in Figure 10.I 7 is especially suited to the home constructor
because it does not require an elaborate alignment procedure. In fact, only the local
oscillator is tuned and the only likely adjustment is either to stretch or squeeze the
local oscillator coil to give the correct coverage of the FM band. It works in the follow-
ing manner: See Figure 10.17.
A tunnel diode oscillating at approximately one-half the input signal frequency
is inductively coupled to the antenna input. When correctly tuned, the very stable
tunnel diode oscillator acts as a second harmonic mixer producing a stable inter-
mediate frequency centered at 200 Kc/sec. The intermediate frequency is amplified
by two simple amplifiers, each consisting of two transistors giving a total voltage gain
of around 100,000. The signal is then limited to give a square-wave which is being
frequency modulated in the same manner as the transmitted signal. The square-wave
is used to charge a capacitor-resistor-diode combination having a short time-constant
producing a standard-sized pulse every time the square-wave goes positive. Pulse-
minded readers will recognize this circuit as being a differentiator with the diode
clipping the negative spike produced by differentiation. There is, at this point in the
circuit, a string of similarly shaped pulses keeping step with the frequency modulated
input signal.
The average value of these pulses can be shown to be the audio originally modu-
lating the FM carrier. This average is obtained by allowing the pulses to charge a
capacitor through a resistor (an integrating circuit) the combination having a fairly
long time ronstant. The resulting output is amplified by the final transistor which
incorporates de-emphasis in its feed-back loop.
The sensitivity is only 50 µ.V/20 db quieting and the receiver, as it stands, is only
useful for receiving local stations. Addition of an RF stage would be a significant
improvement.
The tuner compares very favorably with circuits using more conventional forms
of discrimination because distortion is not dependent on the accurate alignment of
many tuned circuits. Harmonic distortion after limiting is excellent, being better
than 1%.

AMTUNER
The tuner shown in Figure 10.18 is useful for high quality reception of local AM
broadcast stations. A tuned RF stage is used to drive a Class B emitter-foJlower
detector. The natural base-emitter voltage drop of the emitter-follower is overcome
by providing a small amount of bias from a conducting germanium diode. This also
compensates for any change in the base-emitter voltage drop with temperature.
The two tuned circuits are aligned by equalizing inductance at the low frequency
end of the tuning range ( tuning capacitors at maximum value ) and trimming capacity
at the high frequency end in the conventional manner of aligning T.R.F. receivers.
Bandwidth at 6 db is approximately 25 Keis. Owing to the wide-band capability of
the tuner, difficulty might be experienced in adequately separating stations close to
one another in frequency. For this reason, a directional antenna (L1) is used in the
design so additional rejection of unwanted signals may be obtained by rotating the
antenna.

147
 L1

.,, ~0
i C,
0
AC1 3:
REFLEX
CONVERTER r-
TR1 !!I ~
n
AUDIO
'" t'fj

:-::.::.-~
---...,--,,
...
O<J :::u
~
OUTPUT *T3
450..n./V.C. J>
C, ~
0
:::u ~
'"
C,
~
'"
< ~
'"
:::u
C,
~
n
'""4

RI Rs 9v :::u
C, ~
d
C:

R1 47,000 OHMS c, ----.02JJ-f TR1 ---- 2Nl087

~ 11~
11 =i
C,
~
fl'l

R2 10,000 OHMS C2•----.Olf'f TR2----2N1121 OR 2N1087 CRt IN64G OR EQUIV. ;:

R3,R7 500 OHMS C3t----.01 l'-f TR3---- 2Nl415 G)
R4 270 OHMS C4t----.01 JJ-f T1,----- AUTOMATIC85725G OR RADIO INDUSTRIES# 8222 :::u
____ 002JJ-f T2----AUTOMATIC BS614G OR RADIOINDUSTRIES#8223 J>
R5 33,000 OHMS C5
2,000 OHMS CG
,____ · f NOMINAL SENSITIVITY: 2.0 MILLIVOLTS/METER 3:
R6
C7•----
51'
50
;~:~ (MEASURED WITH 5 MILLIWATTS REFERENCE POWER OUTPUT) (I)
VOLUME CONTROL ip. MAXIMUM POWER OUTPUT: 75 MILLIWATTS
RS 1000 OHMS Cei----.05µ.F SELECTIVITY AT ·6db : 10 KC/S
Cg•----soJJ-fd-12v SELECTIVITY AT -60db: 120KC/S
R9 4700 OHMS
RIO 100 OHMS TOTAL BATTERY DRAIN: 19 MILLIAMP$

* FOR FURTHER COMPONENT INFORMATION SEE PAGE 154

THREE TRANSISTORREFLEXRECEIVER
Figure 10.12
 Tz
RAa0 ltllUSTRIES
IN64G #8222 OR
C A AUTOMATIC
BS•725G

SW
+

R1, R14,--1500 OHM C1, Cu,--.02pfd Li,----43!5ph!IO%

R2,--- 6800 OHM C2, C3, C7,-.0lpfd L2,---- 2!50J,1h!IO%
R3, --- 27,000 OHM C4,C&,C9,C13- .0!5J,1fd CR1,CRz-, --IN64G OR EQUIV.
R4, R11,-- 470 OHM C5, --- 1!5J,1fd,12V tt.c,-,ao.&\ R/C MODEL 242
R5, --- 82,000 OHM C9, --- !50J,1fd, 3V lt.C2-89.5J
R&, --- 330 OHM C10, --- 6pfd, 12V
R7,R9--- 3300 OHM C12,--- !50pfd, 12V
NOMINAL SENSITIVITY: 200 MICROVOLTS/METER
R9, --- 10,000 OHM C14, --- 100),lfd, 12V (MEASURED WITH !5 MILLIWATTS REFERENCE POWER OUTPUT)
R10,--- 91,000 OHM TR1, --- GE 2N1086,2N1086A MAXIMUM POWER OUTPUT: 75 MILLIWATTS
R12, --- VOLUME CONTROL OR 2NI087 CONVERTOR SELECTIVITY AT -6db 8.0 KC/S
10,000 OHM AUDIO TAPER TRz,---2N292 1ST I.F. SELECTIVITY AT -60db 60.0 KC/S
R13, --- 100 OHM TR3,--- GE 2Nl69 OR 2Nll21 REFL£X TOTAL BATTERY DRAIN : 17.0 MILLIAMPS
R15,--- 120 OHM TR4, --- 2Nl415 AUDIO
* FOR FURTHER COMPONENT INFORMATION S£E PAGE 154

FOUR TRANSISTOR NINE VOLT REFLEX RECEIVER

Figure 10.13
 RADIOINDUSTRIES
•a222 OR RAj~ztz°"t,IRtES RA~~l~R1ES
PUSH-PULL
AUTOMATIC AUTOMATIC AUTOMATIC AUDIOOUTPUT
BS-7256 BS-725G BS-614G
T1 CR1

I
I
I
I
I
I

~---------------~
I
R1,Ra,·---10,ooo OHM
I
c,,-------.02,.td.
Rz, ----15,000 OHM Cz,C:s,C5, Cs, C7, C9, - .01,. fd.
R3, 1500 OHM C..,C10,·------6,.td. -6V
R4,----270 OHM Cg,-------.05,.fd. NOMINALSENSITIVITY: 200 MICROVOLTS/METER
R5,----47,000 OHM C11,C12,C13,----50,.fd.-12V CM£ASUR£DWITH50 MII.U.TTS REFatfNCE POWER)
Rs,----220 OHM C14, _____ .2,.td. MAXIMUM POWEROUTPUT: 200 MW
R7,R9, --- 2200 OHM CRl,CR2, IN64G OR EQUIV SELECTIVITY
AT-6 db : 8.0 Kc/5
R10, 1000 OHM TR1, G.E.2NI087 SELECTIVITY
AT-60 db: 6D.0Kc/S
Ru, R14,--- 4700 OHM TRz, ------G.E.2N293 ZEROSIGNAL
BATTERYDRAIN:8 M!LLIAMPS
Riz,---- VOUJMECONTROL TR5,------G.E.2Nl69 OR 2N1121
10,000 OHM112WAUDIOTAPER TR4,------G.E.2N324
R13, 68,000 OHM TR15,Tff&-----G.E. 2Nl415
R15,::_:_:_:_::=
470OHM * f.t •:5600A/2000ACT
R1t,. IOOOHM * \ •360ACT/VC
R17,Rl8,---8,2 OHM
R19, 330HM * FORFURTHURINFORIW'IONSEE PAGE154
SIX TRANSISTOR SIX VOLT BROADCASTRECEIVER
Figure 10.14
 RADIOINDUSTRIES
.v8222 OR PUSH PULL
AUTOMATIC
BS725G AUDIO OUTPUT
TR5 * T2

R1,--- 6800 OHM R19, R19, -- 8.2 OHM * LI --- 435ph ~IOo/.
Rz, --- 27,000 OHM C1,---,021'fd * L2 --- 250,uh :tl0%
R3, --- 1500 OHM C2,C3, --.Olpfd CR11 CR2,- DRll7,IN64G, OR CK706A OR EQUIV,
R4,R10,R15,- 470 OHM C4,Cs,C7,Ce 1 -.05pfd
C5, C10, -- 6pfd, 12V
** ~Cl, - l90. 6l
~c2-89.3J
RIC MODEL 242
R5, --- 68,000 OHM
R5, --- 330 OHM Cg, --- .05pfd
R7, --- 3300 OHM C11, --- .003pfd
R9,--- 10,0000HM C12,C13,C14,- 50pfd,l?V
R9, --- 82,000 OHM TR1, --- G.E. 2Nl087 CONVERTER
TR2,-- G.E. 2N293 1ST I.F. NOMINAL SENSITIVITY• 200 MICROVOLTS/ METER
R11, --- 2700 OHM
TR3,--- G.E. 2Nl69 OR 2Nll2I2NDI.F (MEASURED WITH 50 MILLIWATTS REFERENCE POWER OUTPUT)
R12, --- VOLUME CONTROL
10,000 OHM l/2W AUDIO TAPER TR4, --- G.E. 2N324 DRIVER MAXIMUM POWER OUTPUT .6 WATTS.
TR5,TR5,- G.E. 2N1415 AUDIO SELECTIVITY AT -6db : 8.0 KC/S
R13, --- 4700 OHM
* T1, --- 5,000/ 26000CT SELECTIVITY AT -60db'. 60.0KCIS
R14, ---
R16, ---
56,000 OHM
220 OHM
* T2,--- 2500CT/V.C. ZERO SIGNAL BATTERY DRAIN 7.0 MILLIAMP$.
R17,--- 33 OHM
* FOR FURTHERCOMPONENT INFORMATION SEE PAGE 154
SIX TRANSISTOR NINE VOLT BROADCASTRECEIVER
Figure 10.15
 RAOIOINDUSTRIES PUSH-PULL
41t8223 OR AUDIO OUTPUT
AUTOMATIC AUTOMATIC AUTOMATIC I
EX05460 EX05460
E.X0-3015 OR ,.- I
BS614G

2::: 12V

J+
l SW
R1, Ru,--6800 OHM C1,----.02pfd * Ti,----2000/2600 CT.
-·
R2, ---33,000
R3,---1500
OHM
OHM
C2, C3,--.0lpfd
C4,C6,C7,C9,-. lpfd
* T2,----200Q CT/VC
L1,----435phi 10%
R4, R10,R15,-470 OHM C5,----6pfd, 12V Lz,----250phi 10"•
R5,---100,ooo OHM Cg,---.05pfd ti.c 1,-19o.s1.
R6,---330 OHM c,0 .---6ptd, sv ti.c 2 ,-89.3 JRIC MODEL 242
R7, R13,--4700 OHM C11,---.003pfd
R9,---2200 OHM CR1,CR2--IN64 OR IN295 OR EQUIV.
C12,C13,C14,-50pfd, 12V
Rg,---2, 700 OHM C15---.2pfd
R12,---VOLUME CONTROL TR1,--- G.E. 2Nl087
10,000 OHM 1/2W AUDIO TAPER CONVERTER NOMINAL SENSITIVITY; 150 MICROVOLTS/METER
R14,---15,000 OHM TR2, ---G.E 2N2931ST IF. (MEASURED WITH 50 MILLIWATTS REFERENCE
R15,---220 OHM TR3 1 ---G.E. 2N169 OR 2NJl212111>l.F. POWER OUTPUT)
R17, ---2700 OHM TR4, ---G.E. 2N324 DRIVER MAXIMUM POWER OUTPUT : I WATT
R19,R19,--IO OHM SELECTIVITY AT -6db : 8.0 KC/S
TR5,TR6,--G.E.2Nl415 AUDIO SELECTIVITY AT-60db : 38.0 KC/S
R20,---33 OHM WITHCLIP-ON HEAT SINK ZERO SIGNAL BATTERY DRAIN: 10 MILLIAMPS
(BIROiER 3AL635-2R OR EQUIV.I
* FOR FURTHERCOMPONENTINFORMATION SEE PAGE 154
SIX TRANSISTOR, 12 VOLT 1 WATT RECEIVER
Figure 10.16
,-- -,----i
3.2pf-l5pf

AFC
101(
LlfllTER

CONVERTEROSCILLATES
I 1ST LF.AMPLIFER 2ND LF.AMPI..FIER I --~
AT ONE-HALF SGNAL II 200KCIS 200KC/S -------"~
150il I
FREQUENCY .CENTER FREQUENCY CENTERFREatENCY
I +
200,-.t115V I
I I /
L_ -- _J___ ,----__ I/
_L ___
NOTE: DOTTED LINES INDICATE SUGGESTED IIOOULARISREAKOOWN I

I
/
,,,
....,.:t==={] ZOO,-.f/15V
+
I
I
I -IZV I
I
L___ POWER-SUPPLY-12VOL TS
------------
__ _J
FM TUNER
Figure 10.17
RADIO RECEIVER AND TUNER CIBCUITS

EXTERNAL ANTENNA
r~A~~g:WN•w.~-----41.,..____,.l------41--
.... --,._-------e-12v
~{DOTTED.

I
I
L-lL-------1-t
II
47pf

IOK

Cl - 2 GANGCAPACITOR L1 - LOOPSTICKMILLER
BOTH SECTIONSl0pf- CAT.NO.2000, OR
36Spf MILLER CAT.NO. EQUIVALENT
2112,OR EQUIVALENT
L2 -ADJUSTABLE 22OJ'H-275J'H
MILLER PART N0.42A224
CBI, OR EQUIVALENT

AM TUNER
Figure 10.18

ADDITIONALCOMPONENTINFORMATION
TRANSFORMERS
The audio transformers used in these diagrams were
wound on laminations of 1o/s"by 1% " and a ½" stack
size, and having an electrical efficiency of about 80%.
Smaller or less efficient transformers will degrade the
electrical fidelity of the circuits.

OSCILLATORCOIL
Ed Stanwyck Coil Company #1265

VARIABLECONDENSER
Radio Condenser Company Model 242

The receiver circuits shown in Figures 10.1, 10.12, 10.13,

10.14, 10.15, and 10.16 have been designed to give opti-
mum performance with the components specified. Readers
wishing to construct any of these receivers may obtain all
standard components from local or national electronic
parts distributors. If difficulty is encountered in obtaining
the more special parts such as ganged tuning capacitors,
r.f. and oscillator coils, or i.f., interstage, and audio trans-
formers, the reader should make inquiry of
Jonec-K Company
Box 346
North Syracuse 14, New York

154
BASIC COMPUTER CIRCUITS

Computers are generally classified as either analog or digital. An example of an

analog computer is the slide rule where the numerical values involved in the calcula-
tions are represented by the distance along the scales of the slide rule. For the slide
rule, distance is the analog of the numerical values. In an electronic analog computer
the voltage or current in the circuit is used as the analog of the numerical values
involved in the calculation. Analog computers are used primarily in cases where mini-
mum cost is important and high accuracy is not required.
In a digital computer the numerical values change in discrete steps rather than
continuously as in an analog computer. An example of a digital computer is the ordi-
nary desk calculator or adding machine. In an electronic digital computer numerical
values involved in the calculation are represented by the discrete states of Hip-flops
and other switching circuits in the computer. Numerical calculations are carried out in
digital computers according to the standard rules of addition, subtraction, multiplica-
tion and division. Digital computers are used primarily in cases where high accuracy
is required such as in standard accounting work. For example, most desk calculators
are capable of giving answers correct to one part in one million, but a slide rule (analog
computer) would have to be about ¼ of a mile long to be read to the same accuracy.
The transistor's small size, low power requirements and inherent reliability have
resulted in its extensive use in digital computers. Special characteristics of the transistor
such as low saturation resistance, low input impedance, and complementary NPN and
PNP types, have permitted new types of digital circuits which are simple, efficient and
fast. Computers operating at speeds of 5 megacycles are a commercial reality, and
digital circuits have been proved feasible at 160 megacycles.
This chapter offers the design engineer practical basic circuits and design proce-
dures based on proven techniques and components. Flip-flops are discussed in detail
because of their extensive use in digital circuits.

FLIP-FLOP DESIGN PROCEDURES

SATURATEDFLIP-FLOPS
The simplest flip-flop possible is shown in Figure 6.21, however, for standard
transistor types the circuit in Figure 11.l(A) is preferable at moderate temperatures.
We shall refer to the conducting and non-conducting transistors as the on and off
,--------- -2!1V .--------- -Z!IV \tc

ZN!ll!I

SATURATED FLIP-FLOPS
Figure 11.1 (A) Figure 11.1 (B)

155
BASIC COMPUTER CIRCUITS

transistors respectively. For stability, the circuit depends on the low collector to
emitter voltage of the saturated on transistor to reduce the base current of the off
transistor to a point where the circuit gain is too low for regeneration. The 2200
emitter resistor can be removed if emitter triggering is not used. By adding
resistors from base to ground as in Figure 11.l(B), the off transistor has both junctions
reverse biased for greater stability, While the 33K resistors divert some of the formerly
available base current, operation no longer depends on a very low saturation voltage
consequently less base current may be used. Adding the two resistors permits stable
operation beyond 50°C ambient temperature .

.--------- ....... - -21SV

2N396A 2N396A

SATURATEDFLIP-FLOP
Figure11.1 (C)

The circuit in Figure 11.l(C) is stabilized to 100°C. The price that is paid for the
stability is (1) smaller voltage change at the collector, (2) more battery power con-
sumed, (3) more trigger power required, (4) a low lco transistor must be used. The
capacitor values depend on the trigger characteristics and the maximum trigger repeti-
tion rate as well as on the flip-Hopdesign.
By far, the fastest way to design saturating flip-Hops is to define the collector and
emitter resistors by the current and voltage levels generally specifled as load require-
ments. Then assume a tentative cross-coupling network. With all components specified,
it is easy to calculate the on base current and the off base voltage. For example, the
circuit in Figure 11.l(B) can be analyzed as follows. Assume Vaz= .3 volt and Vci::=
.2 volt when the transistor is on. Also assume that VEB = .2 volts will maintain the off
transistor reliably cut-off. Transistor specifications are used to validate the assumptions.
I. Check for the maximum temperature of stability.
R..Vcc 220
V& = R1+ It = 2200 + 220 (25) = 2.3 volts
Ve on= VE+ Vcmon= 2,3 + .2 = 2.5 volts
Assuming no lco, the base of the off transistor can be considered connected to
a potential,
V' a = Vcon Rt! Ra through a resistor R' a =
(2.5) (33K)
V' a = (42K + 33K) = 1.1 volts
R's -- (33K)
75K
(42K)
= 18.SK
156
 BASIC COMPUTER CIRCUITS

The Ico of the off transistor will flow through R' a reducing the base to emitter
potential. If the loo is high enough, it can forward bias the emitter to base junction
causing the off transistor to conduct. In our example, VE = 2.3 volts and Vza = .2 volts
will maintain off conditions. Therefore, the base potential can rise from 1.1 volts to
2.1 volts (2.3 - .2) without circuit malfunction. This potential is developed across
R'8 by Ico = ·!;;,i·
2 1
54 µa. A germanium transistor with Ico = 10 µa at 25°C
will not exceed 54 µ.a at 50°C. If a higher operating temperature is required, R2 and Ra
may be decreased and/or R. may be increased.
II. Check for sufficient base current to saturate the on transistor.
Va on= Vz + VBEon= 2.3 + .3 = 2.6 volts

The current through Ra= L = ;

3~ = .079 ma
V CC - V non 25 - 2.6
Th e current thr ough R1 and R2 in series is I:r = -------
R1 + R2 42K + 2.2K
=.506ma
The available base current is Ia = I:i- L = .43 ma
. Vcc - Vc OD _ 25 - 2.5 O ...
Th e coIIector current 1s le = Ri . K = 1 .2.:>ma
22
The transistor will be in saturation if hn at 10 ma is greater than
~- 10.25 -94
Ia - .43 - ..,
If this circuit were required to operate to -55°C, allowance must be made for
the reduction of hFEIat low temperatures. The minimum allowable room temperature
hll'EI
should be 50% higher or hFEmin= 36.
Generally it is not necessary to include the effect of Ico flowing through R1 when
calculating l2 since at temperatures where Ico subtracts from the base drive it simulta-
neously increases hrz. If more base drive is required, R2 and Ramay be decreased.
If their ratio is kept constant, the off condition will not deteriorate, and so need not be
rechecked.
III. Check transistor dissipation to determine the maximum junction temperature.
The dissipation in the on transistor is
(.3) (.43) (.2) (10.25)
VBEonIa+ VcEonle= lO00 + I000 = 2.18 mw

The dissipation in the off transistor resulting from the maximum Ico is
(25) (55)
Vcslco ~ IO" = 1.4 mw
Generally the dissipation during the switching transient can be ignored at speeds
justifying saturated circuitry. In both transistors the junction temperature is within 1°C
of the ambient temperature if transistors in the 2N394-97 or 2N524-27 series are used.
A saturated Hip-Hop using 2N994 germanium epitaxial transistors is shown in
Figure 11.1(0). This flip-flop is capable of 30 mes operation with a typical transition
time of 10 nanoseconds. In this circuit Qi and Q2 form the usual flip-flop configuration.
However, the trigger input is steered through either Q:i or Q, whose gain is used to
quickly saturate Qi or Q2, whichever is in the "off" state. Simultaneously it is ensured
that the cross-coupling capacitors are discharged to their rest potentials in the shortest
possible time. For those Hip-flop circuit applications not requiring the speed of the
2N994 circuit, 2N781 transistors may be used.

157
BASIC COMPUTER cmCUITS
,....________________ .,..__ ,.____ ~-sv

H
l.5KQ @
NEGATIVE
IKQ l.5Kil .lpF

TRIGGER

+3V

30 MEGACYCLE
SATURATEDFLIP-FLOP
Figure11.1 (D)

NON-SATURATEDFLIP-FLOP DESIGN
The abundance of techniques to prevent saturation makes a general design pro-
cedure impractical if not impossible. While it is a simple matter to design a flip-flop
as shown above, it becomes quite tedious to check all the worst possible combinations
of component change to ensure manufacturability and long term reliability. Often the
job is assigned to a computer which calculates the optimum component values and
tolerances. While a number of flip-flop design procedures have been published, they
generally make simplifying assumptions concerning leakage currents and the voltages
developed across the conducting transistors.

cmcurr CONFIGURATION FOR

NON-SATURATING
FLIP-FLOP DESIGN PROCEDURE
Characteristics:
Trigger input at points E
Trigger steering by Ds and R,
. Collector clamping by D1 and Ra
Connect points A, B, C, D, E as shown in
Figure 11.3 to get counter or shift regis-
ter operation
Cl and C2 chosen on basis of speed re-
quirements

Figure11.2 {A)

158
 BASIC COMPUTER CIBCUITS

The design procedure described here is for the configuration in Figure ll.2(A). No
simplifying assumptions are made but all the leakage currents and all the potentials
are considered. The design makes full allowance for component tolerances, voltage
fluctuations, and collector output loading. The anti-saturation scheme using one resistor
(R3) and one diode (D1) was chosen because of its effectiveness, low cost and
simplicity. The trigger gating resistors (RS) may be returned to different collectors to
get different circuit functions as shown in Figure 11.3. This method of triggering offers
the trigger sensitivity of base triggering and the wide range of trigger amplitude
permissible in collector triggering. The derivation of the design procedure would
require much space, therefore for conciseness, the procedure is shown without any
substantiation. The procedure involves defining the circuit requirements explicitly then
determining the transistor and diode characteristics at the anticipated operating points.
A few astute guesses of key parameters yield a fast solution. However, since the
procedure deals with only one section of the circuit at a time, a solution is readily
reached by cut and try methods without recourse to good fortune. A checking pro-
cedure permits verification of the calculations. The symbols used refer to Figure
ll.2(A) or in some cases are used only to simplify calculations. A bar over a symbol
denotes its maximum value; a bar under it, its minimum. The example is based on
polarities associated with NPN transistors for clarity. The result is that only E:1 is
negative. While the procedure is lengthly, its straightforward steps lend themselves
to computation by technically unskilled personnel and the freedom from restricting
assumptions guarantees a working circuit when a solution is reached. A circuit designed
by this procedure is shown in Figure 11.2(B).

-16V

1.2K 1.2K

220""'
T +16V T220""'

NON-SATURATEDFLIP-FLOP
Figure11.2 (B)

159
 BASIC COMPUTER CIRCUITS

The same procedure can be used to analyze existing flip-Bops of this configuration
by using the design check steps.

----------------- - IO V

IN191 INl91

2N396A

A 8
C E D

(b) INTER CONNECTION AS COUNTER

A 8 A 8 A a-~--
C E D C E D C E D

'------- .....---------1~ TRIGGER

(C) INTERCONNECTION AS SHIFT REGISTER

500 KC COUNTER-SHIFT REGISTER FLIP-FLOP
Figure11.3

160
 NON-SATURATING FLIP-FLOP DESIGN PROCEDURE

STEP I DEFINITION OF OPERATION jsYMBOLj SAMPLE DESIGN FOR 2N396 TRANSISTOR

(A) Circuit Requirements and Device Characteristics

1 Assume maximum voltage design tolerance ~e Let~e = ±5%
2 Assume maximum resistor design tolerance ~r Let ~r = ± 7% (assuming ± 5% resistors)
3 Assume maximum ambient temperature TA Let TA= 40°C
4 Assume maximum load current out of the off side Io Let Io= 1 ma
5 Assume maximum load current into the on side L Let L = 0.2ma
6 Estimate the maximum required collector current in the on l1 Let 11 < 17.5 ma
transistor
7 Assume maximum design Ico at 25°C From spec sheet Ico < 6 µ.a
8 Estimate the maximum junction temperature Ts Let Ts= 60°C
9 Calculate Ico at Ts assuming Ico doubles every l0°C or L, Ia= 6e· 01TJ = 71 µa; Let L = 100 µa
IcoTJ = Ico2:1e·01 (TJ-25 >
10 Assume the maximum base leakage current is equal to the L Let L = 100µ.a
maximum Ico
11 Calculate the allowable transistor dissipation 2N396 is derated at 3.3 mw/°C. The junction temperature
rise is estimated at 20°C therefore 67 mw can be allowed.
Let Pc= 67mw
12 Estimate hF£ minimum taking into account low temperature /jmln Let am1n = 0.94 or /Jmln = 15.67
degradation and specific assumed operating point
13 Estimate the maximum design base to emitter voltage of V1 Let V1 = 0.35 volts
the "on" transistor
14 Assume voltage logic levels for the outputs Let the level separation be > 7 volts
 NON-SATURATING FLIP-FLOP DESIGN PROCEDURE (CONTINUED)

STEP DEFINITIONOF OPERATION SYMBOL SAMPLE DESIGN FOR 2N396 TRANSISTOR

15 Choose the maximum collector voltage permissible for the v,. Let V1 < 2.0 volts
"on" transistor
16 Choose suitable diode types Let all diodes be 1Nl98
17 Estimate the maximum leakage current of any diode L Maximum leakage estimated as
end of life
< 25 µa. Let L = 40 µa at
18 Calculate L =L + L L 40 + 100 = 140 µa
19a Choose the minimum collector voltage for the "off" transistor Va Let Va > 9.0 volts
keeping in mind 14 and 15 above
19b Choose the maximum collector voltage for the "off" tran- V, Let V, < 13.0 volts
sistor
20 Choose the minimum design base to emitter reverse bias to
assure off conditions
Va Let Va = 0.5 volt
21a Estimate the maximum forward voltage across the diodes Vu Let Vo = 0.8 volt
21b Estimate the minimum forward voltage V1 Let V1 = 0.2 volt
22 Estimate the worst saturation conditions that can be tol-
erated.
22a Estimate the minimum collector voltage that can be tolerated Vs Let Vs= 0.1 volt

22b Estimate the maximum base to collector forward bias volt- Ve Let Ve= 0.1 volt
age that can be tolerated
23a Calculate V1 + V1 V10 2 + 0.2 = 2.2 volts
23b Calculate V1 + Vo Vu 2 + 0.8 = 2.8 volts
24a Calculate Va + V1 Vu C.,.l+ 0.2 = 0.3 volt
STEP DEFINITION OF OPERATION SYMBOL SAMPLE DESIGN FOR 2N396 TRANSISTOR
24b Calculate Va + Vo Vu 0.1 + 0.8 = 0.9 volt
25 Calculate Vs + Vr1 Vu 0.1 + 0.1 = 0.2 volt
(B) Cut and Try Circuit Design
1 Assume E2 Es Let Es= -16 volts± 5%; Es= -15.2 v; Es= -16.8 v
(I+
Ar) 1.o7
2a Calculate
(1 - Ar) Ki 0.93 = 115
.
(1 + Ae)
2b Calculate Ka ~:~: = 1.105
(1 - Ae)

2c Calculate -/-
min
Ka i1;:= 1 1.117 ma
2d Calculate I2+ Io+ 2L ~ 0.1 + 1.0 + 0.08 = 1.18 ma
Vo-Vr1 0.8 - 0.1 0 4 54 1
2e Calculate V Ka 0.1 + 0.1 + 15.2 = .0
a+ Vr1- Es VO ts

1 [ 2.2- 0.35
3 Calculate -R. < L1 [V10KiKa
- V1 - K1(V1- ~) ] 1.117 (1.15) (0.0454)
1.15 (0.35 + 16.8) ] = 14.03 K
4 Choose R. R. Let R. = 13K ± 7%; R. = 13.91 K; R. = 12.09 K
5 Calculate Ra> KaR. (0.0454) (13.91K) = 0.632 K
6 Choose Ra Ra Let Ra=0.68 K ± 7%; Ra=0.7276 K; !!: = 0.6324 K
R. (V10- V1) (12.09 K) (2.2 - 0.35)
7 Check Raby calculating Ra< V1- Es+ KaR. 0.35 + 16.8 + (1.117) (12.09)
0.730 K; choice of
Rasatisfactory
R. 13.91 K
8 Calculate
-Vr.- Es- LR.
Ko
-0.5 + 15.2 - (0.14) (13.91)
= 1.091 K/V
 NON-SATURATINGFLIP-FLOP DESIGN PROCEDURE (CONTINUED)

STEP DEFINITIONOF OPERATION SYMBOL SAMPLE DESIGN FOR 2N396 TRANSISTOR

Ke (V1 + Vo) - Ra (1.091) (2.0 + 0.5) K - 0.632 K _ K

9 Calculate R2 > 1 - (1.091) (0.04) - 2 .19
1-KeL
Choose Ra- If there are difficulties at this point, assume a
10
different E,. Ra Let R2 = 2.7 K ± 7%; Ra=2.889 K; Ra=2.511 K
C l l Ki2 [Va - Vu + K. Ra] (1.15)2[9.0 - 0.3 + (1.18) (2.511)]
11 a cu ate V V
,-
-
u
K1
13.0 - 2.8 = 1.51
KN, -Va (1.51) (13.0) - 9.0
12 Calculate E1 <
K1 -1/K:z 1.51 - 1/1.105 = 17.63
13 ChooseE1 E1 Let E1 = 16 volts± 5%; E1 = 16.8 volts; E1 = 15.2 volts
(E1 - Va) Ra (15.2 - 9.0) (2.511)
14 Calculate R1 <
Va - Va + K. Ra 9.0 - 0.3 + (1.18) (2.511) = 1·335 K
(E1 - V,) (ii;) (16.8 - 13.0) (2,889}
15 Calculate R1 >
V,-Vu 13.0 - 2.8 = 1.077K
16 Choose R1 Ri Let R1 = 1.2 K ± 7%; R1 = 1.284 K; R1 = 1.116 K

(C) Design Checks

l Check "'off" stability. Reverse bias voltage is given by:
VEB < -E2 + - R, - + L Ra+ L (Ra+ Ra)]
[V1- E:a VBB 15 2 + 13.91
R.+Ra+~ - - - - · 17.05
=
(2 + 15.2 + (0.04) (2.511) + (0.14} (3.14)] -0.7 volts
Circuit stable if V EB s;; - V r. The design value of Vo was 0.5 volts. Therefore, the "off"
condition is stable.
STEP DEFINITION OF OPERATION SYMBOL SAMPLE DESIGN FOR 2N396 TRANSISTOR
2 Check for non-saturation under the worst conditions.
VBE_ <E I + It - (Via-Ea) VBS _ 15 2 + 13.91 (0.9 + 15.2) = 0.19 volts
It+ Ra . 14.54
Circuit non-saturated if Vum< VH The design maximum of VH was 0.2 volts.
3 Check for stability. Calculate:
3a RA= R1 + Ra RA 1.284 + 2.889 = 4.173 K
3b Ru = R1+ ii; + Bi + It Ra 1.284 + 2.889 + .728 + 12.09 = 16.99 K
3c Ro=Ra+ It Re .728 + 12.09 = 12.82 K
3d E'1 =E1-K.R1 E'i 15.2 - (1.18) (1.284) = 13.68 volts
3e Ro=R1+Ra+Ra+R. Ro 1.116 + 2.889 + .728 + 13.91 = 18.643 K
Ro (E1 - V1) - R1 [E1 - E2 - L It - L (Ra + It)] 18.64 (16.8 - 2) - 1.116 [16.8 + 16.8 - (0.14) (13.91)
3£ lo= Ia
1.116 (18.64 - 1.116)
!!! (Ro - R.) - (.04) (.728 + 13.91)]
= 12.34ma

3g 1 16.99 (13.68 + 16.8)

l1 = R~ie (E'1 - V10)- - - (E'1- Ea) l1 (4.173) (12.82) <13·68 - 2 -2> - 1.266 ma
Re - 12.82

3h L= L +Ia+ l1 0.2 + 12.34 + 1.266

+ It/Re
{Jmln
L 15.67 + 12.09/ 12.82
0.831 ma

12.09 ( 4.173 ) ( )
- 16.8 + 16.99. 1 + 12.818 13.683 + 16.8
3i V'BE= E 2 + ~ ( 1+ :: ) (E'i- E2) 12.09 ( ) 12.09
- 12.818 13.683 - 2.2 - 0.831 16.99
Ra ( ~ ('4.173) (12.09)
- -=-
It
Re
( E'\ - V10) - L -=-
Re
RAR.
Re
- - )
RA- Ra V'uE
12.818
4.173- 0.7276) = .55V
.55V is greater than V1 = .35V, therefore the design is
satisfactory.
BASIC COMPUTER CIRCUITS

TRIGGERING
Flip-Hops are the basic building blocks for many computer and switching circuit
applications. In all cases it is necessary to be able to trigger one side or the other into
conduction. For counter applications, it is necessary to have pulses at a single input
make the two sides of the Hip-flop conduct alternately. Outputs from the Hip-Hop must
have characteristics suitable for triggering other similar Hip-flops. When the counting
period is finished, it is generally necessary to reset the counter by a trigger pulse to
one side of all Hip-flops simultaneously. Shift registers and ring counters have similar
triggering requirements.
In applying a trigger to one side of a Hip-Hop,it is preferable to have the trigger
tum a transistor off rather than on. The off transistor usually has a reverse-biased
emitter junction. This bias potential must be overcome by the trigger before switching
can start. Furthermore, some transistors have slow tum on characteristics resulting in
a delay between the application of the trigger pulse and the actual switching. On the
other hand, since no bias has to be overcome, there is less delay in turning off a
transistor. As tum-off begins, the Hip-flop itself turns the other side on.
A lower limit on trigger power requirements can be determined by calculating
the base charge required to maintain the collector current in the on transistor. The
trigger source must be capable of neutralizing this charge in order to tum off the
transistor. It has been determined that the base charge for a non-saturated transistor is
approximately Qa = 1.22 Ic/271'fausing the equivalent circuit approach, or Tc le using
charge parameters. The tum-off time constant is approximately hv1d271'faor Ta. This
indicates that circuits utilizing high speed transistors at low collector currents will
require the least trigger power. Consequently, it may be advantageous to use high
speed transistors in slow circuitry if trigger power is critical. If the on transistor was in
saturation, the trigger power must also include the stored charge. The stored charge is
given approximately by
Q. _ _!_ (l l) (
- 2,r fa
+ fal 1 - ICINCII) (is,__.k_)
hvE
using the equivalent circuit approach. Using charge parameters the stored charge is
approximately

Q. -::J
= Tb (101
where the symbols are defined in the section on transient response time.
Generally, the trigger pulse is capacitively coupled. Small capacitors permit more
frequent triggering but a lower limit of capacitance is imposed by base charge con-
siderations. When a trigger voltage is applied, the resulting trigger current causes the
charge on the capacitor to change. When the change is eq~al to the base charge just
calculated, the transistor is turned off. If the trigger voltage or the capacitor are too
small, the capacitor charge may be less than the base charge resulting in incomplete
tum-off. In the limiting case C =~; . The speed with which the trigger turns off a
transistor depends on the speed in which Qa is delivered to the base. This is determined
by the trigger source impedance and rb'.
In designing counters, shift registers or ring counters, it is necessary to make
alternate sides of a Hip-Hop conduct on alternate trigger pulses. There are so-called
steering circuits which accomplish this. At low speeds, the trigger may be applied at
the emitters as shown in Figure 11.4. It is important that the trigger pulse be shorter

166
 BASIC COMPUTER CIRCUITS

than the cross coupling time constant for reliable operation. The circuit features few
parts and a low trigger voltage requirement. Its limitations lie in the high trigger
current required.
At this point, the effect of trigger pu1se repetition rate can be analyzed. In order
that each trigger pulse produce reliable triggering, it must find the circuit in exactly
the same state as the previous pulse found it. This means that all the capacitors in the
circuit must stop charging before a trigger pulse is applied. If they do not, the result
is equivalent to reducing the trigger pulse amplitude. The transistor being turned off
presents a low impedance permitting the trigger capacitor to charge rapidly. The
capacitor must then recover its initial charge through another impedance which is
generally much higher. The recovery time constant can limit the maximum pulse rate •
.-------------------o+6V

2N708 2N708

90pf
------+-----1~--........i{-o lflr
CT ~~~~i

EMITTER TRIGGERING
MAXIMUM TRIGGER RATE EXCEEDS 2MC WITH TRIGGER
AMPLITUDE FROM 4V TO 12V.

Figure11.4

Steering circuits using diodes are shown in Figures 11.5 and 11.6. The collectors
are triggered in 11.5 by applying a negative pulse. As a diode conducts during trigger-
ing, the trigger pulse is loaded by the collector load resistance. When triggering
is accomplished, the capacitor recovers through the biasing resistor RT. To minimize

2N708
Cy

----1----o"V'V"
90pf PULSE
INPUT

COLLECTOR TRIGGERING
MAXIMUMTRIGGERRATE EXCEEOS511CWITH TRIGGER
AMPLITUDE FROM4V TO 12V. DASE TRIGGERING
MAXIMUM TRIGGERRATE EXCEEDS !SMC
WITHTRIGGERAMPLITUDE FROM 0.75 TO
Z VOLTS.

Figure 11.5 Figure11.6

167
BASIC COMPUTER CIRCUITS

bigger loading, RT should be large; to aid recovery, it should be small. To avoid the
recovery problem mentioned above, RT can be replaced by a diode as shown in 11.7.
The diode's low forward impedance ensures fast recovery while its high back im-
pedance avoids shunting the trigger pulse during the triggering period.
Collector triggering requires a relatively large amplitude low impedance pulse but
has the advantage that the bigger pulse adds to the switching collector waveform to
enhance the speed. Large variations in trigger pulse amplitude are also permitted.
In designing a counter, it may be advantageous to design all stages identically the
same to permit the economies of automatic assembly. Should it prove necessary to
increase the speed of the early stages, this can be done by adding a trigger amplifier
as shown in Figure 11.8 without any change to the basic stage.

.,..;....~---~ Cy

90pf

2N708 2N70B
36pf

~.n.n..
PULSE
INPUT

COLLECTOR TRIGGERING COLLECTORTRIGGERINGWITH TRIGGER AMPLIFIER

DIODE TO SUPPLY VOLTAGEREDUCES FOR IMC TRIGGER RATE LESS THAN I VOLT TRIGGER
TRIGGERPOWER ANDEXTENDS MAXIMUM AMPLITUDEREQUIRED.
TRIGGER RATE.

Figure11.7 Figure11.8

Base triggering shown in Figure 11.6 produces steering in the same manner as
collector triggering. The differences are quantitative with base triggering requiring
less trigger energy but a more accurately controlled trigger amplitude. A diode can
replace the bias resistor to shorten the recovery time.

9.IK Rr

IOK
IN3605 IN3605
..._ ___ _.,_-4~t-- .... -----
22Opf \ i I 220pf
BASE TRIGGERINGWITHHYBRIOGATE Cy

Figure11.9

168
 BASIC COMPUTER CIRCUITS

Hybrid triggering illustrated in Figure 11.9 combines the sensitivity of base

triggering and the trigger amplitude variation of collector triggering. In all the other
steering circuits the bias potential was fixed, in this one the bias potential varies in
order to more effectively direct the trigger pulse. By returning the bias resistor to the
collector the bias voltage is Ven. For the conducting transistor, VoB is much less than
for the off transistor, consequently, the trigger pulse is directed to the conducting
transistor. This steering scheme is particularly attractive if VoB for the conducting
transistor is very small as it is in certain non-saturating circuits such as shown in
Figure 6.23.
Care should be taken that the time constant GrRT does not limit the maximum
counting rate. Generally RT can be made approximately equal to RK,the cross-coupling
resistor.

SPECIAL PURPOSECIRCUITS
SCHMITT TRIGGER
A Schmitt trigger is a regenerative bistable circuit whose state depends on the
amplitude of the input voltage. For this reason, it is useful for waveform restoration,
signal level shifting, squaring sinusoidal or non-rectangular inputs, and for DC level
detection. Practical circuits are shown in Figure 11.10.

FREQUENCY RANGE 0- 50OKC

OUTPUT AT COLLECTOR HAS 8V
MINIMUM LEVEL CHANGE

INPUT
01 ALWAYS CONDUCTS IF INPUT
IS MORE NEGATIVE THAN -5V
02 ALWAYS CONDUCTS IF INPUT
IS MORE POSITIVE THAN -2V
AMBIENT TEMPERATURE -55°C
TO 71-C

(A)

.----------o • ~V

FREQUENCY RANGE O TO I MC
OUTPUT OUTPUTAT COLLECTOR HAS 2V
MINIMUM LEVEL CHANGE
0 I ALWAYS CONDUCTS IF INPUT
INPUT
EXCEEDS 6.BV
02 ALWAYS CONDUCTS IF INPUT
IS BELOW 5.2V
AMBIENT TEMPERATURE o•c
TO 71°C

( B)

SCHMITT TRIGGERS
Figure 11.1O

169
BASIC COMPUTER CIRCUITS

Circuit operation is readily described using Figure 11.lO(B). Assuming Ql is non-

conducting, the base of Q2 is biased at approximately +6.8 volts by the voltage
divider consisting of resistors 3.3K, I.SK and 6.8K. The emitters of both transistors are
then at 6.6 volts due to the forward bias voltage required by Q2. H the input voltage
is less than 6.6 volts, QI is off as was assumed. As the input approaches 6.6 volts, a
critical voltage is reached where QI begins to conduct and regeneratively turns off Q2.
If the input voltage is now lowered below another critical value, Q2 will again conduct.

ASTABLE MULTIVIBRATOR
The term multivibrator refers to a two stage amplifier with positive feedback. Thus
a flip-flop is a bistable multivibrator; a "one-shot" switching circuit is a monostable
multivibrator and a free-running oscillator is an astable multivibrator. The astable
multivibrator is used for generating square waves and timing frequencies and for
frequency division. A practical circuit is shown in Figure 11.11. The circuit is sym-
metrical with the transistors DC biased so that both can conduct simultaneously. The
cross-coupling capacitors prevent this, however, forcing the transistors to conduct
alternately. The period is approximately T = CT !oIOO microseconds where CT is
measured in pf (µp.f). A synchronizing pulse may be used to lock the multivibrator to an
external oscillator's frequency or subharmonic.

FREQU!!NCYRANGEI CPS TO 2!10KCPSBY

CHANGINGCr
330pf OUTPUT AT COLLECTORHAS B VOLT
MINIMUM LEVEL CHANGE
SY~ AMBIENT TEMPERATURE.55•c TO 71°C
SYNCHRONIZING
PULSES PERMIT
GENERATINGSUBHARMONICS
SYNC PULSE AMPLITUDE MUST EXCEED
l.!IV POSITIVEI RISETIME MUST BE LESS
THAN 1.011SEC.

ASTABLE MULTIVIBRATOR
Figure11.11

MONOSTABLEMULTIVIBRATOR
On being triggered a monostable multivibrator switches to its unstable state where
it remains for a predetermined time before returning to its original stable state. This
makes the monostable multivibrator useful in standardizing pulses of random widths
or in generating time delayed pulses. The circuit is similar to that of a flip-flop except
that one cross-coupling network permits AC coupling only. Therefore, the flip-flop can
only remain in its unstable state until the circuit reactive components discharge. Two
circuits are shown in Figure 11.12 to illustrate timing with a capacitor and with an
inductor. The inductor gives much better pulse width stability at high temperatures.

170
 BASIC COMPUTERCIBCUITS

INDICATORLAMP DRIVER
The control panel of a computer frequently has indicator lamps to permit monitor-
ing the computer's operation. The circuit in Figure 11.13 shows a bistable circuit
which pennits controlling the lamp by short trigger pulses.
A negative pulse at point A turns on the lamp, which remains on due to regenera-
tive feedback in the circuit. A positive pulse at A will turn off the lamp. The use of
complementary type transistors minimizes the standby power while the lamp is off.

•12V

OUTPUTAT COLLECTORS HAS8 VOLT

LEVEL CHANGE
OUTPUT P\A.5£ DURATION2,&SEC
TO I SEC
MAXIMUM INPUT FREQUENCY 250KC
MAXIMUM REQUIRED INPUT PULSE IS
!I VOLTS
DUTY CYCLE EXCEEDS 60'%
AMBIENT TEMPERATURE ·55-C TO 71-C

(A)

OUTPUT AT COLLECTORHAS
5 VOLT LEVEL CHANGE
OUTPUT PULS£ DURATIONAPPROX
600 MICROSECONDS
MAXIMUM INPUT PULSE REQUIRED
3 VOLTS
AMBIENT TEMPERATURE-55•C
TO 71°C

( B)

MONOSTABLEMULTIVIBRATOR
Figure 11.12

PULSEGENERATOR
Frequently, in computer circuits a clock pulse is required to set the timing in an
array of circuits. A pulse generator is shown in Figure 11.14 which delivers a very
fast rise time (25 nsec.) pulse of high power. The circuit is basically composed of two
parts. A multivibrator is formed by Qi and Q2 and their associated circuitry and triggers
the pulse generator formed by Qa and Q•.

171
BASIC COMPUTER cmCUITS

6.8K

6.8K

GE-E24 LAMP

TRIGGER PULSE REQUIREMENT2 VOLTS MAXIMUM.

AMBIENT TEMPERATURE-55°C TO 71°C
±
RESISTORTOLERANCE 10% AT END OF LIFE.

BISTABLE INDICATORLAMP DRIVER

Figure 11.13

IK

GE 2.N994
02.
IOOK 47012 47.Q RL !50.Q
2.2.0pf OUTPUT
470pf
+ +
-=-9V 2.!5V -=-_
GE 2.N2193
01 100.n
100n

GE 2.N2.193
04
47.Q 2.2.0pf
!5J1,h 22.on

Pulse Generator Characteristics: Amplitude - 25 volts,

Width - 200 nanoseconds, Rise Time - 25 nanoseconds,
Fall Time - 30 nanoseconds, Impedance - 50 ohms, Repe-
tition Rate - 100 kilocycles.

PULSE GENERATORWITH 0.5 AMPS. IN 25 NSEC.

Figure 11.14

172
 BASIC COMPUTER CIBCUITS

RING COUNTER
The circuit of Figure 11.15 forms a digital counter or shift register with visual
readout. The circuit operates from a 12 volt source and uses six components per stage.
The counter and indicator functions are combined to insure low battery drain. The
.22 µfd capacitor ensures that the first stage turns on after the reset button is released.
No current is drawn by the stages except when a lamp is on. As many stages as desired
may be included in a ring.

RESET N.C.

+12vo--ol.s>-- ...... --------------------

1Nl692

INl692
INl692
RECTIFIERS
PROVIDEBIAS
VOLTAGESFOR
TEMPERATURE
STABILITY.

IOK IOK

OJ µfd

INPUTo---j 1------ ..

IN1692
OUTPUT
IN1692
r-o1iui\~1
O.lµfd RING
FIRST STAGE__) SECOND STAGE LAST STAGE
OF RING COUNTER

RING COUNTERWITH VISUAL READOUT

Figure 11.15

173
LOGIC

Large scale scientific computers, smaller machine control computers and electronic
animals all have in common the facility to take action without any outside help when
the situation warrants it. For example, the scientific computer recognizes when it has
completed an addition, and tells itself to go on to the next part of the problem. A
machine control computer recognizes when the process is finished and another part
should be fed in. Electronic animals can be made to sense obstructions and change
their course to avoid collisions. Mathematicians have determined that such logical
operations can be described using the conjunctives AND, OR, AND NOT, OR NOT.
Boolean algebra is the study of these conjunctives, the language of logic. A summary
of the relations and operations of Boolean algebra follow the example of its use below.
Transistors can be used to accomplish logic operations. To illustrate this, an example
from automobile operation will be used. Consider the interactions between the ignition
switch, the operation of the motor and the oil pressure warning light. If the ignition is
off, the motor and light will both be off. If the ignition is turned on, but the starter is
not energized the warning lamp should light because the motor has not generated oil
pressure. Once the motor is running, the ignition is on and the lamp should be off.
These three combinations of ignition, motor and lamp conditions are the only possible
combinations signifying proper operation. Note that the three items discussed have
only two possible states each, they are on or off. This leads to the use of the binary
arithmetic system, which has only two symbols corresponding to the two possible states.
Binary numbers will be discussed later in the chapter.

I M L Result
I =IGNITION
I 0 0 0 V
M=MOTOR
2 0 0 I X L=LAMP
3 0 I 0 X R =RESULT
4
I =ON
0 I I X O=OFF
5 I 0 0 X V= ACCEPTABLE
6 I 0 I V X =UNACCEPTABLE
7 V N =3 =NO.OF VARIABLES
I I 0
8 I I I X 2N=e

TABLEOF ALL POSSIBLECOMBINATIONS

OF IGNITION,
MOTORAND LAMP CONDITIONS
Figure 12.1

To write the expressions necessary to derive a circuit, first assign letters to the
variables, e.g., I for ignition, M for motor and L for lamp. Next assign the number one
to the variable if it is on; assign zero if it is off. Now we can make a table of all possible
combinations of the variables as shown in Figure 12.1. The table is formed by writing
ones and zeros alternately down the first column, writing ones and zeros in series of
two down the second; in fours down the third, etc. For each additional variable,
double the number of ones or zeros written in each group. Only 2N rows are written,

175
LOGIC

where N is the number of variables, since the combinations will repeat if more rows
are added. Indicate with a check mark in the result column if the combination repre-
sented in the row is acceptable, For example, combination 4 reads, the ignition is off
and the motor is running and the warning light is on. This obviously is an unsatisfactory
situation. Combination 7 reads, the ignition is on and the motor is running ~d the
warning light is off. This obviously is the normal situation while driving. If we indicate
that the variable is a one by its symbol and that it is a zero by the same symbol, with
a bar over it and if we use the symbol plus (+) to mean "OR" and multiplication to
mean "AND" we can write the Boolean equation IML+ IML + IML =
R where R
means an acceptable result. The three terms on the left hand side are combinations 1, 6,
and 7 of the table since these are the only ones to give a check mark in the result
column. The plus signs indicate that any of the three combinations individually is
acceptable. While there are many rules for simplifying such equations, they are beyond
the scope of this book.

INPUTS

11 M

ii 1f

A PICTORIAL PRESENTATION

.. OF THE GATES REQUIRED TO

EXPRESS THE BOOLEAN
EQUATION V
A PICTORIAL PRESENTATION
OF THE GATES REQUIRED TO
EXPRESS THE BOOLEAN EOU·
ATION
nlC+IML+lML•R lt•M•Llll•M•Llll • M+U.R

Figure12.2 Figure12.3
To express this equation in circuitry, two basic circuits are required. They are
named gates because they control the signal passing through. An "AND" gate generates
an output only if all the inputs representing the variables are simultaneously applied and
an "OR" gate generates an output whenever it receives any input. Our equation trans-
lated into gates would be as shown in Figure 12.2. Only if all three inputs shown for an
"AND" gate are simultaneously present will an output be generated. The output will
pass through the "OR" gate to indicate a result. Note that any equation derived from
the table can be written as a series of "AND" gates followed by one "OR" gate.
It is possible to rearrange the equation to give a series of"OR" gates followed by one
"AND" gate. To achieve this, interchange all plus and multiplication signs, and remove
bars where they exist and add them where there are none. This operation gives us,
(I + M + L) (I+ M + L) (I+ M + L) = R
In ordinary language this means if any of the ignition or motor or lamp is on, and
simultaneously either the ignition is off or the motor is on or the lamp is off, and
simultaneously either the ignition is off or the motor is off or the lamp is on, then the
result is unacceptable. Let us apply combination 4 to this equation to see if it is accept-

176
 LOGIC

able. The ignition is off therefore the second and third brackets are satisfied. The first
bracket is not satisfied by the ignition because it requires that the ignition be on.
However, the motor is on in combination 4, satisfying the conditions of the first bracket.
Since the requirements of all brackets are met, an output results. Applying combination
1 to the equation we find that the third bracket cannot be satisfied since its condi-
tions are the opposite of those in combination 7. Consequently, no output appears.
Note that for this equation, an output indicates an unacceptable situation, rather than
an acceptable one, as in the first equation. In gate form, this equation is shown in
Figure 12.3.
Table 12.1 summarizes the definitions used with the Boolean equations above and
indicates some of the rules which were used to convert the equation represented in
Figure 12.2 to that of Figure 12.3. The more conventional symbols a, b, c are used in
place of I, M, and L.

DEFINITIONS

a, b, c, etc.
ab or a• b or (a)(b) ..
Symbols used in equations
Reads as a and b ..
.!+ b Reads as "a orb ..
a Reads as "not a..
1 Reads as "true .. or "on ..
0 Reads as "false" or "off..

LAWS

Commutative Laws Distributive Law

a+b=b+a a{b + c) =ab+ ac
ab=ba SEecial Distributive Law
Associative Laws (a + b)(a + c) = a + be
(a + b) + c = a + (b + c) De Morsan's Theorem
(ab)c = a(bc) aTT = fai>) a1i=(a+ b)

RELATIONSHIPS

1=0 0=T
a+a=a a•a=a
a+l=l a•l = a
a+a=l a•a=0
a=a =
a + ab a(l + b) = a

Table 12.1

Methods for using transistors in gate circuits are illustrated in Figure 12.4. The base
of each transistor can be connected through a resistor either to ground or a positive
voltage by operating a switch. In Figure 12.4(A) if both switches are open, both tran-
sistors will be non-conducting except for a small leakage current. If either switch A or
switch B is closed, current will flow through RL, If we define closing a switch as being

177
LOGIC

synonymous with applying an input then we have an "OR" gate. When either switch is
closed, the base of the transistor sees a positive voltage, therefore, in an "OR" gate the
output should be a positive voltage also. In this circuit it is negative, or "NOT OR".
The circuit is an "OR" gate with phase inversion. It has been named a "NOR" circuit.
Note that if we define opening a switch as being synonymous with applying an input,
then we have an "AND" circuit with phase inversion since both switch A and switch B
must be open before the current through RL ceases. We see that the same circuit can
be an "AND" or an "OR" gate depending on the polarity of the input.

---------1-------------+1ov
IOK

(A) GATE USING NPN TRANSISTORS II II

IF CLOSING A SWITCH IS AN INPUT, THIS IS AN OR GATE

11 11
IF OPENING A SWITCH IS AN INPUT, THIS IS AN AND GATE
NOTE: PHASE INVERSIONOF INPUT

+1ov--------------------
8

--~OUTPUT

( 8) GATE USING PNP TRANSISTORS

IF CLOSING A SWITCH IS AN INPUT THIS IS AN "AND" GATE
11 11
IF OPENING A SWITCH IS AN INPUT THIS IS AN 0R GATE
NOTE: PHASE INVERSION OF INPUT

BASIC LOGIC CIRCUITS USING PARALLEL TRANSISTORS

Figure 12.4

178
 LOGIC

The circuit in Figure 12.4{B)has identically the sanie input and output levels but
uses PNP rather than NPN transistors. If we define closing a switch as being an input,
we find that both switches must be closed before the current through RL ceases. There-
fore, the inputs which made the NPN circuit an "OR" gate make the PNP circuit an
"AND" gate. Because of this, the phase inversion inherent in transistor gates does not
complicate the overall circuitry excessively.
Figure 12.S(A) and (B) are very similar to Figure 12.4(A) and (B) except that the
transistors are in series rather than in parallel. This change converts "OR" gates into
"AND" gates and vice versa.

(A) GATEUSINGNPN TRANSISTORS

IF CLOSINGA SWITCHIS AN INPUT THIS IS AN "AND"
GATE
IF OPENINGA SWITCHIS AN INPUTTHIS IS AN •OR.GATE
NOTE: PHASE INVERSIONOF INPUT

(8) GATE USINGPNP TRANSISTORS

IF CLOSINGA SWITCHIS AN INPUT THIS IS AN "OR" GATE
IF OPENINGA SWITCHIS AN INPUT THIS IS AN"AND"GATE
NOTE: PHASE INVERSIONOF INPUT

BASIC LOGIC CIRCUITS

(USING SERIES TRANSISTORS)
Figure 12.5

Looking at the logic of Figure 12.3, let us define an input as a positive voltage; a
lack of an input as zero voltage. By using the circuit of Figure 12.4(A) with three
transistors in parallel, we can perform the "OR" operation but we also get phase
inversion. We can apply the output to an inverter stage which is connected to an
"AND" gate of three series transistors of the configuration shown in Figure 12.S(A).
An output inverter stage would also be required. This is shown in Figure 12.6(A).

179
 LOGIC

By recognizing that the circuit in Figure 12.4(A) becomes an "AND" gate if the
input signal is inverted, the inverters can be eliminated as shown in Figure 12.6(B)•

0
• NOR.GATE INVERTER NOTM0°GATE INVERTER
(A)INVERTERS COMPENSATEFOR PHASE INVERSION OF GATES

,------------+--------O+IOV

• TO OTHER NOT"AND"
"NOR"GATES GATE

IOK
(B)PHASE INVERSIONUTILIZED TO ACHIEVE "AND•AND"oR• FUNCTIONSFROM THE SAME CIRCUIT.

CIRCUITS REPRESENTING
(I + M + L) (T+ M + () Ci+ M + L) = R
Figure12.6

If the transistors are made by processes yielding low saturation voltages and high
base resistance, the series base resistors may be eliminated. Without these resistors the
logic would be called direct-coupled transistor logic DCTL. While DCTL offers ex-
treme circuit simplicity, it places severe requirements on transistor parameters and
does not offer the economy, speed or stability offered by other logical circuitry.
The base resistors of Figure 12.6 relax the saturation voltage and base input voltage
requirements. Adding another resistor from each base to a negative bias potential
would enhance temperature stability.
Note that the inputs include both "on" and "off" values of all variables e.g., both
I and I appear. In order that the gates function properly, I and I cannot both be posi-
tive simultaneously but they must be identical and oppositely phased, i.e. when I is
positive T must be zero and vice versa. This can be accomplished by using a phase
inverter to generate T from I. Another approach, more commonly used, is to take I
andTfrom opposite sides of a symmetrical flip-Hop.

180
 LOGIC

+20V

27K

-10
IF A OR B OR C IS RAISEDFROM ZERO TO
12 VOLTS THE TRANSISTORWILLCONDUCT.

BASIC NOR CIRCUIT

Figure12.7

"NOR" logic is a natural extension of the use of resistors in the base circuit. In the
circuit of Figure 12.7, if any of the inputs is made positive, sufficient base current
results to cause the transistor to conduct heavily. The "OR" gating is performed by
the resistors; the transistor amplifying and inverting the signal. The logic of Figure
12.3 can now be accomplished by combining the "NOR" circuit of Figure 12.7 with
the "AND" circuit of Figure 12.S(A). The result is shown in Figure 12.7. In comparing
the circuits in Figure 12.6(A) and 12.8, we see that the "NOR" circuit uses one-fourth
as many transistors and one-half as many resistors as the brute force approach. In fact if
we recall that the equation we are dealing with gives R rather than R, we see that
we can get R by removing the output phase inverter and making use of the inherent
inversion in the "NOR" circuit. In the circuit of Figure 12.7 two supply voltages of
+20 and -10 volts are used. The -10 volt supply is to insure that the transistor is
held off when Ico increases at elevated temperatures. If silicon transistors (such as the
2N708, 2N914, or 2N2193A) are used in NOR logic circuits the hold off supply may
not be necessary. Since VBEis larger for silicon devices and Ieo is very low a resistor
returned to the emitter reference may result in sufficient circuit stability .
.--------zov

ALL TRANSISTORS
2N63llA

IINERTER

(A) NOR LOGIC USING SERIES (B) NOR LOGIC USING

TRANSISTORS FOR "AND" GATE INVERSION FOR "AND" GATE
Figure 12.8

181
LOGIC

Because of the fact that a generalized Boolean equation can be written as a series
of "OR" gates followed by an "AND" gate as was shown, it follows that such equations
can be written as a series of "NOR" gates followed by a "NOR" gate. The low cost
of the resistors used to perform the logic and the few transistors required make "NOR"
logic attractive.

DEFINITIONS
IK =MINIMUM CURRENT THROUGH RK FOR
TURNING TRANSISTOR ON
IB =MINIMUM BASE CURRENT FOR
TURNING TRANSISTOR ON
Ir =BIAS CURRENT TO KEEP TRANSISTOR
OFF AT HIGH TEMPERATURES
M :::i MAX. NUMBER OF INPUTS PERMITTED
N 1r MAX. NUMBER OF OUTPUTS PERMITTED
VBE=MAX. BASE TO EMITTER VOLTAGE WHEN
THE TRANSISTOR IS ON.
VcE = MAX. COLLECTOR TO EMITTER VOLTAGE WHEN
THE TRANSISTOR IS ON.

CIRCUIT USED FOR DESIGN OF NOR CIRCUITRY

Figure12.9
A detailed "NOR" building block is shown in Figure 12.9. The figure defines the
basic quantities. The circuit can readily be designed with the aid of three basic
equations. The first derives the current IK.under the worst loading conditions at the
collector of a stage.
Vee - Vuz: - lco11Rc (12a)
R1t + NRo

182
 LOGIC

where Icou is the maximum Ico that is expected at the maximum junction temperature.
The second equation indicates the manner in which IK is split up at the base of the
transistor.
Is:= Is+ M (VcE11 ±
- VcEN Vs~: VEB)- (VBE- Vce:N)+ lcou (12b)

where V cENis the minimum expected saturation voltage, Vce:11is the maximum expected
saturation voltage and VEB is the reverse bias required to reduce the collector current
to Ico.V EB is a negative voltage. The third equation ensures that VEB will be reached
to turn off the transistor.
l0011+ (Vceu ;KV e:u)M IT (12c)

Knowing IT and choosing a convenient bias potential permits calculation of RT, In

using these equations, first select a transistor type. Assume the maximum possible
supply voltage and collector current consistent with the rating of the transistor and the
maximum anticipated ambient temperature. This will ensure optimization of N and
M. From the transistor specifications. values of Icou, VBE, VcEN, and Ia (min) can be
calculated. Ia (min) is the minimum base current required to cause saturation. Ro is
calculated from the assumed collector current. In equation (12a) solve for Is: using the
desired value of N and an arbitrary value for RK, Substitute the value for L, in equa-
tion (12b) along with a chosen value for Mand solve for lu. While superficially lu need
only be large enough to bring the transistor into saturation, increasing le will improve
the rise time.

INPUTS

1
Ir
CLAMPING DIODE REDUCES STORAGE CAPACITORS
REDUCE
STORAGE
TIME TO INCREASESPEED TIME TO INCREASE
SPEED
(A) (8)

Figure12.10

Circuit speed can also be enhanced by using a diode as shown in Figure 12.IO(A)
to prevent severe saturation or by shunting R1tby a capacitor as in 12.IO(B).The capac-
itors may cause malfunction unless the stored charge during saturation is carefully
controlled; they also aggravate crosstalk between collectors. For this reason it is pref-
erable to use higher frequency transistors without capacitors when additional speed
is required. Table 12.2 lists the characteristics of common logic systems employing
transistors.

183
LOGIC

TYPICAL CIRCUIT
NAME DESCRIPTION
( Positive signals are defined as 1 )

Logic is performed by re-

sistors. Any positive input
RTL produces an inverted out-
Resistor
a+b+c put irrespective of the
other inputs. Resistor Ro
transistor gives temperature stability.
logic ( See Fig. 12.7)
(NOR)

Same as RTL except that

capacitors are used to en-
RCTL a
hance switching speed.
~ The capacitors increase the
Resistor
base current for fast col-
capacitor lector current turn on and
transistor b minimize storage time by
logic supplying a charge equal
to the stored base charge.

DCTL
Direct
coupled
transistor
logic
a

b
=t~ a

-=- -
+
a+b
Logic is performed
transistors. VcE and VoE,
measured with the tran-
the two logic levels. Vcs
must be much less than
by

sistor in saturation, define

Val!lto ensure stability and

circuit flexibility.
Fig. 12.6)
( See

Logic is performed by

DL
Diode
logic
:3-r+b+c :~••c diodes. The output is not
inverted. Amplifiers are re-
quired to maintain the cor-
rect logic levels through
several gates in series.

Logic is performed by
diodes. The output is in-
LLL verted. The dioae D iso-
lates the transistor from
the gate _permitting R to
Low turn on the collector cur-
level rent. By proper choice of
logic voltage changes occur.
This method is also called
current switching diode
logic.

COMMON LOGIC SYSTEMS

184
 LOGIC

SUITABLETRANSISTORS SUITABLE
DIODES
FEATURES GERMANIUM SILICON SILICON
Low?ieed High~eed Low~eed High~eed High Speed
(fa<I mes,) (fa>I mes.) (fa<l mes.) (fa>I mes.)

The circuit design is 2N78• 2N705 2N335 2N706

straightforward. All logical 2Nl67• 2N711 2N656A 2N708
operations can be per- 2Nl69A 2N828 2N914
formed with only this cir- 2N398A* 2N964 2Nl613
cuit. Many transistors 2N525 2N994 2N2193
2N526•
readily meet the steady 2N635A
state requirements. 2Nl304
2Nl305
2Nl924

Faster than RTL at the ex- 2N396A• 2N705 2Nl613

pense of additional compo- 2N404 2N711 2N2193
nents and stringent stored 2N634
charge requirements.

Very low supply voltages 2N781 2N708

may be used to achieve 2N914
high power efficiency and
miniaturization. Relatively
fast switching speeds are
practical.

Several gates may be used 2N78• 2N705 2N333• 2N706 IN3604

between ampli&ers. High 2Nl67 2N711 2N337• 2N708 1N3605
speeds can be attained. 2N396A* 2N964 2N656A 2N914 1N3806
Non - inversion simplifies 2N528* 2N994 2Nl613
circuit design problems. 2N635A 2N2193
Relatively inexpensive
components are used.

The number of inputs to 2N396A• 2N781 2N335• 2N914 1N3604

the diode gate does not 2N525 2N828 2N338• 2Nl711 1N3605
affect the transistor base 2N526* 2N2192 1N3606
currentthus giving pre- 2N635
dictable performance. The 2Nl304
2Nl305
small voltage excursions
minimize the effects of
stray capacitance and en-
hance switching speed.

Table 12.2
185
LOGIC

NAME TYPICALCIRCUIT DESCRIPTION

( Positive signals are defined as 1 )

Logic is performed by
transistors which are biased
CML from constant current
sources to keep them far
Current out of saturation. Both in-
mode verted and non-inverted
logic outputs are available.

Logic is performed by
DTL
:-.r f_,..:--='7 1--= diodes. The output is in-
verted. The transistor acts
as an amplifier. This is

-~
Diode essentially an extension of
transistor
logic -~ the diode logic discussed
above.

Logic is performed by
cores and transmitted by
CDL diodes. Transistors act as
drivers to shift informa-
Core tion. Each transistor can
diode • drive many cores but not
logic successive cores in the
logic line.

Logic is performed by
silicon controlled switches
;;'"ft=rf+ ott • t which are triggered on at
4 Layer o b C the gate lead. The gates
----+IIJU can be actuated by pulse
Device or DC levels. The gates
logic have a built in memory
and must be reset.

Logic, is performed by
tunnel diode switchins
TDL bo-lW\.--e--------o
obc
OR
from low voltage to high
voltage state. Whether
circuit represents AND or
Tunnel o+b+c OR gate depends on bias
diode current through resistor R.
logic Tunnel diode biased neai
peak current for OR gate,
and close to ground fo1
AND.

COMMON LOGIC SYSTEMS

186
 LOGIC

SUITABLETRANSISTORS SUITABLE
DIODES
FEATURES GERMANIUM SILICON SILICON
Low~eed High~eed Low~eed High~ed
(fa.<l mes,) (fci>l mes.) (fci<l mes,) (fa.>l mes.) High Speed

Very high switching speeds 2N705 2N337• 2N708

are possible because the 2N711 2N338• 2N914
transistors are operated at 2N864
optimum operating condi- 2N994
tions. Although the volt-
age excursion is small the
circuitry is relatively un-
affected by noise,

High speeds can be at- 2N78• 2N705 2N333• 2N706 1N3604

tained. The impedance 2Nl67 2N711 2N337• 2N708 1N3605
and voltage levels from 2N396A• 2N964 2N914 1N3606
stage to stage are well 2N526• 2N994 2Nl613
2N635A
defined. 2Nl304
2Nl305

These core modules can 2N697 1N3604

be made very small. Speed 2Nl613 1N3605
is limited by core switch- 2Nl893 1N3606
ing speeds. 2N2193 1N3607
2N2243 1N3608
1N3609

SUITABLEDEVICES
These gates are pulse or
de actuated and the input
need not be maintained.
High output power capa-
bility is available. In gen-
eral, in the presence of
radiation, units will tum
3N58
3N59 I SiliconSwitches
Controlled

on permitting fail-safe de-

sign in this atmosphere.

l
Current Bowing through
input resistors determines
logic. Circuit is basically TD-IA Germanium
simple and very high TD-2A
TD-3A Tunnel Diodes
speed is obtainable. TD-311B

NOTE: Other peak current diodes are listed in Chapter 22.

•Military types
Table 12.2 (Continued)
187
LOGIC

BINARYARITHMETIC
Because bistable circuits can be readily designed using a variety of components
from switches to transistors, it is natural for counters to be designed to use binary
numbers, i.e., numbers to the base, or radix, 2. In the conventional decimal system, a
number written as 2904 is really a contraction for 2 X !OS+ 9 X 102 + 0 X 101 + 4 X 1.
Each place refers to a different power of 10 in ascending order from the right.
In the binary system, only two symbols are permitted, 0 and 1. All numbers are
constructed on the basis of ascending powers of 2. For example, 11011 means
1 X 2' + 1 X 2• + 0 X 21 + 1 X 21 + 1 X 1. This is 27 in the decimal system.
This notation applies also to decimal fractions as well as integers. For example, the
number 0.204 is a contraction of 2 X 10-1 + 0 X 10-• + 4 X 10-a.Similarly, the binary
number 0.1011 is a contraction of 1 X 2-1 + 0 X 2-1 + 1 X 2..a + 1 X 2_.. Using this
construction, a table of equivalent binary and decimal numbers can be obtained as
shown below.
Binary Decimal Binary Decimal
0 0 0.000 0.000
1 1 0.001 0.125
10 2 0.010 0.250
11 3 0.011 0.375
100 4 0.100 0.500
101 5 0.101 0.625
110 6 0.110 0.750
111 7 0.111 0.875

Arithmetic operations can best be described by comparative examples..

Addition Subtraction
42 101010 44 101100
+18 10010 -18 10010
~ 111100 ~ 11010

During addition, the digits in a column are added to the carry from the previous
column. The result is expressed as a sum digit which is recorded and a carry digit
which is applied to the next column. The term digit generally refers to the figures in a
decimal number; the term bit (an abbreviation of binary digit) is used with binary
numbers. If the digit being subtracted is the larger of the two in the column, the
techniques used to handle this situation in decimal subtraction are also applicable in
the binary system.
Multiplication Division
42 101010 1.35 1.0101
21 10101 5\/6.7500 101 '/ 110.11000
~ 101010 5 101
84 101010 17 111
882 101010 15 101
1101110010 ~ 1000
25 101
110

Multiplying a binary number by two is equivalent to adding a zero to its right hand

188
 LOGIC

side, just as multiplying a decimal number by 10 adds a zero. This is equivalent to

shifting the number one place to the left. In computers, this operation is done by a
shift register. Division can be readily understood since it involves the operations of
additions, subtraction and multiplication only.
Computers generally employ circuits called adders which can perform the opera-
tion of addition. Adders can also perform other arithmetic operations besides addition.
For example, an adder can perform subtraction by the use of a number's complement.
The complement is obtained numerically by interchanging all ones and zeros. In
equipment the complement can be obtained by taldng the output from the opposite
side of Hip-Bops.
The manner in which subtraction with an adder is accomplished is given by the
following example:
Problem: Calculate
1101- 1001
Complement of 1001 is 0110
=
(1111 - 1001 0110)
Add: =
1101 + 0110 10011
Add 1 =
10011 + 1 10100
Omit left hand digit to obtain
=
1101 - 1001 100

Flip-Bops can be connected in series so that the first Bip-Hop will alternate states
with each input pulse, and successive Hip-Bopswill alternate states at half the rate of
the preceding Hip-Bop. In this way the Hip-Hopsassume a unique configuration of
states for a given number of input pulses. The Hip-Hopsactually perform the function
of binary counting. A practical circuit of a binary counter is shown in Figure ll.3{B)
The count in a binary counter can be determined by noting whether each stage is in
the 1 or O condition, and then assigning the appropriate power of 2 to the stage to
reconstruct the number as in the examples above.
If it is required to count to a base other than 2, a binary counter can be modified
to count to the new base.
The rules for accomplishing the modification will be illustrated for a counter to
the base 10.
Rule Example
1) Determine the number of binary stages M=lO
{N) required to count to the desired 23 < 10<2'
new base (M) N=4
2) Subtract M from 2N 2' - 10 6=
3) Write the remainder in binary form 6=ll0
4) When the count reaches 2N·1, feed 2N-l = 23 = 1000
back a one to each stage of the counter Feedback added gives
having a one in the remainder shown in 3) 1 110
As additional pulses are added beyond the count 2N·1, they will count through to M
and then recycle to zero. This method is based on advancing the count at the point 2N-1
to the extent that the indicated count is 2Hwhen M input pulses are applied. The feed-
back is applied when the most significant place becomes a one but it is imperative that
feedback be delayed until the counter settles down in order to avoid interference with
the normal counter action.

189
UNIJUNCTION TRANSISTOR
CIRCUITS

The unijunction transistor is a three-terminal semiconductor device which has

electrical characteristics quite different from those of a conventional two-junction tran-
sistor. Its most important features are: (1) a stable firing voltage which is a fixed
fraction of the applied interbase voltage, (2) a very low value of firing current (Ip),
(3) a negative resistance characteristic which is uniform from unit to unit and stable
with temperature and life, (4) a high pulse current capability, and (5) a low cost. These
characteristics make the unijunction transistor advantageous in oscillators, timing
circuits, voltage sensing circuits, SCR firing circuits and bistable circuits.
The unijunction transistor is available in 28 distinct types to meet the needs of a
wide range of applications. Types 2N489 to 2N494 feature tight control on all param-
eters, particularly on 11(±10% limits) and Ruu (±20% limits). These types differ from
one another primarily in the limit values of 11and Ruu, Military versions of types 2N489
to 2N494 are available to meet military specifications MIL-T-19500A/75. Type 2Nl671
and 2N2160 are low cost types, suitable for applications where lower voltage ratings
and wider ranges of 11 and RBBcan be tolerated. Types 2Nl671A and 2N489A to
2N494A have guaranteed characteristics for firing Silicon Controlled Rectifiers. Types
2Nl671B and 2N489B to 2N494B have lower limits on peak point current and emitter
leakage current and are intended for applications such as time delay circuits where a
sensitive characteristic is required.

THEORYOF OPERATION
The construction of the unijunction transistor is shown in Figure 13.2. Two ohmic
contacts, called base-one ( Bl) and base-two (B2) are made at opposite ends of a
small bar of n-type silicon. A single rectifying contact, called the emitter ( E), is made
on the opposite side of the bar close to base-two. An interbase resistance, Ruu, of
between 5K and lOK exists between base-one and base-two. In normal circuit opera-

I92
4

IE
82
VBB OHMIC
Bl CONTACTS

SYMBOLFOR UNIJUNCTION TRAN- CONSTRUCTIONOF UNIJUNCTION

SISTORWITH INDENTIFICATIONOF TRANSISTOR- CROSS SECTIONAL
PRINCIPLE VOLTAGES AND CUR- VIEW
RENTS
Figure13.1 Figure 13.2

191
UNIJUNCTION TRANSISTOR CIRCUITS

tion, base-one is grounded and a positive bias voltage, VBB, is applied at base-two.
With no emitter current flowing, the silicon bar acts like a simple voltage divider
(Figure 13.3) and a certain fraction, 7J of VBa will appear at the emitter. If the emitter
voltage, VE, is less than 7J VBB, the emitter will be reverse-biased and only a small
emitter leakage current will flow. If VE becomes greater than 7J VBa, the emitter will be
forward biased and emitter current will flow. This emitter current consists primarily
of holes injected into the silicon bar. These holes move down the bar from the emitter
to base-one and result in an equal increase in the number of electrons in the emitter
to base-one region. The net result is a decrease in the resistance between emitter and
base-one so that as the emitter current increases, the emitter voltage decreases and a
negative resistance characteristic is obtained (Figure 13.5).
The operation of the unijunction transistor may be best understood by the repre-
sentative circuit of Figure 13.3. The diode represents the emitter diode, RB1represents
the resistance of the region in the silicon bar between the emitter and base-one and
Rm represents the resistance between the emitter and base-two. The resistance RB1
varies with the emitter current as indicated in Figure 13.4.
B2 IE Rat
(MA·) (OHMS)
0 4600
E I 2000
2 900
5 240
10 150
20 90
Bl Bl 50 40

UNIJUNCTION TRANSISTOR VARIATIONOF RB1 WITHh: IN

REPRESENTATIVECIRCUIT REPRESENTATIVE CIRCUIT
(TYPICAL 2N492)
Figure13.3 Figure 13.4
The large signal properties of the unijunction transistor are usually given in the
form of characteristic curves. Figure 13.5 gives typical emitter characteristic curves as
plots of emitter voltage vs. emitter current for fixed values of interbase voltage. Figure
13.6 gives typical interbase characteristic curves as plots of interbase voltage vs. base-
'i\.
7 I\.
I
\ '/ NAii l'Ckllfl

\/

I
\ \
!
I
-- -v ,I
.,,/
Jr:•IOMA

,,,..
,,,,,.
,.. -
' \ I I/ --- ~~--
... ,o ...

·,'
\ \
I\. " /
I/,/'
L.,,,,,,,,.
----
---~~- Ir:•'!.'

--~--
" ......_ ,, ,......-
" ' ' ......_
~
/
....,
......
II..
r--..
'
~r-,...
...~;.:;;
..ITT
·-·~· I

j
i...-1--~
1.,.,..,,.,..
i--...-

.
I
~ 1 1...-
..._ va'LLn,ouns
io ta ao n ,o n 40
I I I 4 I e
I I I
f I I 10 U II II .. lliltlll:IAH Y01.fAll•Y11•V0t.TI "'
lttnn• CUCCWT• 11 • IULLIAll"l;qa

TYPICAL EMITTER TYPICAL INTERBASE

CHARACTERISTICS(TYPE2N492) CHARACTERISTICS(TYPE 2N492)
Figure 13.5 Figure 13.6

192
 UNIJUNCTION TRANSISTOR cmCUITS

two current for fixed values of emitter current. On each of the emitter characteristic
curves there are two points of interest, the peak point and the valley point. On each of
the emitter characteristic curves the region to the left of the peak point is called the cut-
oJf region; here the emitter is reverse biased and only a small leakage current Hows.The
region between the peak point and the valley point is the negative resistance region.
The region to the right of the valley point is the saturation region; here the dynamic
resistance is positive and lies in the range of 5 to 200.

PARAMETERS-DEFINITION AND MEASUREMENT

1. Rua - Interbase Resistance. The interbase resistance is the resistance measured
between base-one and base-two with the emitter open circuited. It may be measured
with any conventional ohmmeter or resistance bridge if the applied voltage is five
volts or less. The interbase resistance increases with temperature at about 0.8% /°C.
This temperature variation of Ruu may be utilized for either temperature compensation
or in the design of temperature sensitive circuits.
2. '1 - Intrinsic Stand-off Ratio. This parameter is defined in terms of the peak
point voltage, VP, by means of the equation: VP = .,,Vsu + Vo ... where Vn j1;:
about 0.67 volt at 25°C and decreases with temperature at about 3 millivolts/°C. It is
found that .,, is constant over wide ranges of temperature and interbase voltage. A
circuit which may be used to measure '7 is shown in Figure 13.7. In this circuit R1, C1
and the unijunction transistor form a relaxation oscillator and the remainder of the
circuit serves as a peak voltage detector with the diode automatically subtracting the
voltage Vo. To use the circuit, the "car' button is pushed and Raadjusted to make the
meter read full scale. The "cal" button is then released and the value of '1 is read
directly from the meter (1.0 full scale). If the voltage V1 is changed, the meter must
be recalibrated.
3. Ir - Peak Point Current. The peak point current corresponds to the emitter
current at the peak point. It represents the minimum current which is required to fire
the unijunction transistor or required for oscillation in the relaxation oscillator circuit.
IP is inversely proportional to the interbase voltage. Ir may be measured in the circuit
of Figure 13.8. In this circuit the potentiometer setting is slowly increased until the
unijunction transistor fires as evidenced by a sudden jump and oscillation of the meter
needle. The current reading just prior to when the jump takes place is the peak point
current.
,-----------+---O+VBS
10-:,ov

0.2

TEST CIRCUIT FOR INTRINSIC TEST CIRCUIT FOR PEAK POINT

STANDOFFRATIO (11) EMITTER CURRENT (Ip)
Figure13.7 Figure 13.8

193
UNIJUNCTION TRANSISTOR CIRCUITS

4. VP - Peak Point Emitter Voltage, This voltage depends on the interbase voltage
as indicated in (2). VP decreases with increasing temperature because of the change
in Vo and may be stabilized by a small resistor in series with base-two.
5. VE (sat) - Emitter Saturation Voltage. This parameter indicates the forward
drop of the unijunction transistor from emitter to base-one in the saturation region.
It is measured at an emitter current of 50 ma and an interbase voltage of 10 volts.
6. Ie2 (mod) - Interbase Modulated Current. This parameter indicates the effective
current gain between emitter and base-two. It is measured as the base-two current
under the same condition used to measure VE (sat).
7. ho - Emitter Reverse Current. The emitter reverse current is measured with
60 volts between base-two and emitter with base-one open circuit. This current varies
with temperature in the same way as the Ico of a conventional transistor.
8. Vv - Valley Voltage. The valley voltage is the emitter voltage at the valley
point. The valley voltage increases as the interbase voltage increases, it decreases
with resistance in series with base-two and increases with resistance in series with
base-one.
9. Iv - Valley Current. The valley current is the emitter current at the valley
point. The valley current increases as the interbase voltage increases and decreases
with resistance in series with base-one or base-two.

RELAXATIONOSCILLATOR
The relaxation oscillator circuit shown in Figure 13.9 is a basic circuit for many
applications. It is chiefly useful as a timing circuit, a pulse generator, a trigger circuit
or a sawtooth wave generator.
,-----+-0+V1

BASIC RELAXATIONOSCILLATOR
WITH TYPICAL WAVEFORMS
Figure13.9

Conditions for Oscillation.

V1 - V1•> I V1 - Vv < I
Rt Pl R1 \'
It is found that these conditions are very broad permitting a 1000 to 1 range of R1
from about 2K to 2M. R2 is used for temperature compensation, its value may be cal-
culated from the equation:
R: E!! 0.40VRnn(units are ohms, volts)
.,, 1

The maximum and minimum voltages of the emitter voltage waveform may be
calculated from:
VE (max)= VP= 71Vaa + .67 volt
VE (min.) ~ 0.5 Vs (sat)
The frequency of oscillation is given by the equation:
f =:!! 1
R,C In ( 1 ~ )
71
and may be obtained conveniently from the nomogram of Figure 13.10.

194
 •~7~•
UNIJUNCTION TRANSISTOR CIRCUITS

RESISTANCE-RI - KILOHMS

~~ 2 ~ ~ ~ ~~ ~:J~ ~ g ~ ....
0

~• 1 I ...........__._i I 1

MAXIMUM FREQUENCY TYPES 2N4J1, 2N492

NOM>NAL FREQUENCY TY"5 7489, 2N490

FREQUENCY - f - CYCLES PER SECOND "l •0.56

0
!2

0
2

MINIMUM
NOMINAL FREQUENCY TYPES 2N 493, 2N494

1"0'1'1'1' l""""l"I' i'i'I' /,..,.,,,.i•i'i'i' l""""l"l'I

"2 ., • .,N :lddddci tiqq~~~ cigg
CAPACITANCE -C- MICROFARAOS . .

NOMOGRAM
FOR CALCULATING
FREQUENCY
OF RELAXATION
OSCILLATION
Figure 13.10

The emitter voltage recovery time, tvs, is defined as the time between the 90%
and 10 % points on the emitter voltage waveform. The value of tn: is determined
primarily by the size of the capacitor C in Figure 13.9 and may be obtained from
Figure 13.11.
_ 100
:g
z 50 MAX 80°/o
0
~ 30 1/MEAN -
~ 20
a: ,,,,,
MIN 80"/,;
u
! 10
- ..,"' -..,.~
I
--- -
\:!
... 5
- -- - 2fvE

i:,
::E
3
2
I .. ~•

---
...--
----
:l I
.
~
.001 .01 0.1 1.0 10
CAPACITANCE -C-(MICROF'ARAOS)

RECOVERY
TIME OF UNIJUNCTION TRANSISTORRELAXATION
OSCILLATORVS. CAPACITY
Figure 13.11

The pulse amplitude at base-one or base-two may be determined from the equations:
.
1f., = [VP - 1/2 VE(sat)] C
.....1.1 -
I B2(pealt> e!
tn:
IRS(mod) _ ~
'J ls<poalt>
Units are ma,
volts, mµf, µsec.
l.
7

195
UNI)UNCTION TRANSISTOR cmCUITS

ULTRA-LINEARSAWTOOTHWAVE GENERATOR
The circuit of Figure 13.12 may be used as a linear sawtooth wave generator. The
NPN transistor serves as an output buffer amplifier with the capacitor C, and resistor ~
serving in a bootstrap circuit to improve the linearity of the sawtooth. R1 and C1 give
integrator type feedback which compensates for the loading of the output stage. Opti-
mum linearity is obtained by adjusting R1, Linearity is 0.3% or more depending on
hrE of the NPN transistor.
+2ov

IK
N'\J'
OllTPUT
6V P-P

2N167
2N336

l/v1,
OUTPUT
c, RL IOV P-P
0.05 2K IKC

SAWTOOTH
GENERATOR
WITHHIGHLINEARITY
Figure13.12

VOLTAGE SENSING CIRCUIT

The high sensitivity of the unijunction transistor and the extreme stability of its
firing characteristic make it ideally suited for use in go no-go types of voltage sensing
circuits such as shown in Figure 13.13. This circuit includes a simple floating power
supply with zener diode regulation which operates from the 115 volt AC line. If the
input signal is negative the unijunction transistor will not fire and there will be no
output. If the input signal is slightly positive, the unijunction transistor will fire and
pulses will occur at the output as long as the input signal remains positive. The output
pulses are of sufficient magnitude to trigger a flip-flop, an SCR, or other pulse sensitive
devices. Note that the transformer coupled supply and output of this circuit give
complete freedom of choice in connecting the circuit to the signal source since there
are no common grounds.
Most of the output pulse energy is supplied by capacitor Ca. This capacitor is
charged rapidly through R1after each pulse and hence does not limit the response time
of the circuit. Diode D2 provides a discharge path for Ca and diode D1 and D2 clamp
the input voltage to enable Ca to charge to its steady state voltage when very large
voltages are present at the signal input. Capacitors C1 and Ca provide the initial firing
energy for the unijunction transistor and also serve as a filter for transients appearing
at the signal input and across the supply. In some cases a small capacitor will also be
required across the primary of the pulse transformer to prevent false triggering due to
transients.
The circuit is initially adjusted by shorting the signal input and setting R1 so that
the circuit is on the verge of firing. If close temperature compensation is needed R, is
adjusted so that the firing voltage does not change appreciably when the unijunction
transistor is heated or cooled. It is normally possible to adjust the temperature com-

196
 UNIJUNCTION TRANSISTORCIBCUITS

pensation so that the drift in firing voltage is within ±2 millivolts from 0°C to 55°C.
After the temperature compensation is completed it will normally be necessary to reset
R1. The long term stability of this circuit is normally better than ± 10 millivolts and
the hysteresis is normally less than 1 millivolt. The change in firing voltage with a
change in the supply voltage (~V.) will be less than 0.7 t:,.Yi/V1.The voltage stability
can be improved by adding two silicon diodes in series with R,.
3300,

INl692

+
SIGNAL
INPUT
ll
~v
~PS
24V
l/4A

VOLTAGE
SENSINGAND TRIGGERCIRCUIT
Figure13.13

STAIRCASEWAVE GENERATOR
Figure 13.14 shows a simple staircase wave generator which has good stability and
a wide operating range. The unijunction transistor Q1 operates as a free running oscil-
lator which generates negative pulses across R,. These pulses produce current pulses
from the collector of Q2which charge capacitor C in steps. When the voltage across C1
reaches the peak point voltage of Qa this transistor fires and discharges C..
Resistor R1 determines the frequency of the steps and resistor Rt determines the
number of steps per cycle. The circuit shown can be adjusted for a step frequency
.----.1..--e--------~---------.0+2ov

3300 3300

03 I A
0, 2N491 l_r lr
2N491 STAIRCASE
OUTPUT
IOV P-P

STAIRCASEWAVEGENERATOR
(FREQUENCY DIVIDER)
Figure 13.14

197
UNIJUNCTION TRANSISTOR cmCUITS

from 100 cps to 2 KC and the number of steps per cycle can be adjusted from one to
several hundred. This circuit can also be adapted to a frequency divider by cascading
stages similar to the stage formed by Q2 and Qa,

TIME DELAYRELAY
Figure 13.15 shows how the unijunction transistor can be used to obtain a precise
delay in the operation of a relay. When the switch SW! is closed, capacitor Cr is
RELAY
CONTACTS

Rr 'o-o+v,
3K-500K SWI ( 24-32V)

2N491
2N492 3300
2W

+ Cr RELAY GE A38
1001' fd 1500 S279IG200
25V DPDT

TIME DELAYCIRCUIT WITH RELAY

Figure 13.15

charged to the peak point voltage at which time the unijunction transistor fires and the
capacitor discharges through the relay thus causing it to close. One set of relay contacts
hold the relay closed and the second set of contacts can be used for control functions.
To be used in this circuit, relays must have fast operating times, low coil resistance
and low operating power.
The time delay of this circuit is determined by RT, about one second of delay is
obtained for each lOK of resistance, RT, The time delay is quite independent of tem-
perature and supply voltage.

MULTIVIBRATOR
Figure 13.16 shows a unijunction transistor multivibrator circuit which has a fre-
quency of about 1 Kc. The conditions for oscillation of this circuit are the same as for
+ v,
I I I
+25V ,..,2it,-i
I : /1·- + 12.5V
VE LV L_ +3V

v0 .-- .... ----11~.-.,... V 7 .----,- + 21 V

82 L---' L..::..._ + 16 V
IN457 2N491
-+0.7
Vo V7 - -8.SV

WITH TYPICALWAVEFORMS
UNIJUNCTIONTRANSISTORMULTIVIBRATOR
Figure 13.16

198
 UNIJUNCTION TRANSISTOR cmcurrs

the relaxation oscillator. The length of time during which the unijunction transistor is off
(no emitter current flowing) is determined primarily by R1. The length of time during
which the unijunction transistor is on is determined primarily by R2. The periods may
be calculated from the equations:

t1 = R1Cln [Vi - VE]

Vi _ Vp

t2 = R2Cln[V t ~~VE]
1

Where VE is measured at an emitter current of Iii:= Vi (~ii R:i) and may be obtained
from the emitter characteristic curves.
An NPN transistor may be direct coupled to the multivibrator circuit by replacing
the diode as shown in Figure 13.17. This circuit has the advantage that the load does
not have any effect on the timing of the circuit.

RELAY
OR
LOAD

UNIJUNCTION TRANSISTORMULTIVIBRATORUSED TO DRIVE

NPN TRANSISTOR
Figure 13.17

HYBRID TIMING CIRCUITS

The unijunction transistor can be used in conjunction with conventional PNP or
NPN transistors to obtain versatile timing circuits such as symmetrical and unsym-
metrical multivibrators, one-shot multivibrators, variable frequency oscillators and time
delay circuits. The advantages of these circuits include: (1) The output at the collector
of each transistor is very nearly an ideal rectangular waveform. (2) The circuits will
tolerate large variations in hFE or Ico of the transistors as compared to conventional
circuits. (3) The circuits are not prone to "lock-up" or non-oscillation. (4) The timing
stability is excellent. (5) A single small timing capacitor CT can be used, avoiding the
use of electrolytic capacitors in many applications.
The hybrid timing circuits can use either germanium or silicon transistors as
desired. The basic circuits for PNP or NPN transistors are shown in Figures 13.18 and
13.19. In both of these circuits, the junction transistors form a conventional flip-flop
with the unijunction transistor serving the timing and triggering functions. Each time
the unijunction transistor fires the discharge current from the capacitor CT develops a
pulse across R" which triggers the flip-flop from one state to the other.
The basic circuits as shown in Figures 13.18 and 13.19 will operate at frequencies
from about 1 cps to 500 cps and at temperatures above 75°C. Frequencies from 1 cycle
per minute to 100 KC can be obtained by proper choice of CT and RA and suitable flip-
flop design. The operating temperature range may be extended to 150°C by the use of
silicon transistors.

199
 UNIJUNCTION TRANSISTOR CIRCUITS

BASIC HYBRID TIMING CIRCUITSUSING PNP AND NPN TRANSISTORS

Figure 13.18 Figure 13.19

The basic hybrid timing circuits in Figures 13.18 and 13.19 can be adapted to
perform desired functions by connecting resistors or potentiometers between the points
in the circuit (Ci, Ct, E, G) as indicated below.
(A) Symmetrical Multivibrator-Square Wave Generator
RT
E o----V\/\,----oG (FIXED)

Vo ____JL__JL
,---<JG (VARIABLE)

Connecting the resistor between points E and G in the basic circuits gives a square
wave generator which has perf.ect symmetry. By the use of a 2 megohm potentiometer
the frequency may be varied continuously from 1 cps to 500 cps. The frequency is
f = l/2RTCr,
(B) One-Shot Multivibrator
Rr
c,o~--f\/V\, ........
-------oE (FIXED)

'--'----oE (VARIABLE)

The collector of Qi will be positive in the quiescent state. A positive pulse at the
base of Qi in Figure 13.18 or a negative pulse at the base of Q1 in Figure 13.19 will
trigger the circuit, At the end of the timing interval, the unijunction transistor will fire
and cause the circuit to revert to its quiescent state. This circuit has the advantage of a
fast recovery time so it may be operated at a high duty ratio without any loss of
accuracy.

200
 UNIJUNCTION TRANSISTOR CIRCUITS

(C) Non-symmetrical Multivibrator

11~(RTI +R1) Cr
t2~lRTZ+R1l Cr

----nE (FIXED)

The timing capacitor Cr will be charged through the resistor RTl or RT2which is
connected to the positive collector. The diodes will isolate the other resistor from the
timing capacitor. The two parts of the period (t1, ta) can thus be set independently by
Rn and Rn and may differ by as much as 1000 to 1.
(D) Non-symmebical Multivibrator - Constant Frequency

:~:: ::-~: o E

This connguration gives a multivibrator which has a constant frequency but a

variable duty cycle.
Further information on the characteristics and circuit applications of the unijunction
transistor is given in application note 90.10, "Notes on the Application of the Silicon
Unijunction Transistor." Available on written request.

201
FEEDBACK AND SERVO
AMPLIFIERS- TRANSISTOR
CHOPPERS

USE OF NEGATIVE FEEDBACKIN TRANSISTORAMPLIFIERS

Negative feedback is used in transistor amplifiers to fix the amplifier gain, increase
the bandwidth (if the number of transistors is less than three), <ureduce distortion, and
change the amplifier input and output impedances. Feedback is used in servo ampli-
fiers to obtain one or more of these characteristics.
Gain is reduced at the midband frequencies as the feedback is increased, and the
predictability of the midband gain increases with increasing feedback. Thus, the greater
the feedback, the less sensitive will be the amplifier to the gain changes of its transistors
with operating point and temperature, and to the replacement of transistors.
The output and input impedances of the amplifier are dependent upon the type of
feedback. If the output voltage is fed back, the output impedance is lowered. In con-
trast, feedback of the output current raises the output impedance. If the feedback
remains a voltage, the input impedance is increased, while if it is a current, the input
impedance is decreased.

C G _ I ( GH \
- H i+GH
R =i+GH 1
€" R-B
B= HC
H Cc G~
FEEDBACK

OUTPUT

SERVO-TYPEFEEDBACKSYSTEM
Figure14.1

A convenient method for evaluating the external gain of an amplifier with feedback
is the single loop servo-type system as shown in Figure 14.1. (The internal feedback
of transistors can be neglected in most cases.) The forward loop gain of the amplifier
without feedback is given by G and it includes the loading effects of the feedback
network and the load. H is the feedback function, and is usually a passive network.
In using this technique, it is assumed that the error current or voltage does not affect
the magnitude of the feedback function. The closed loop gain is then

C
~ = 1 +GGH = H1 ( GH )
1 + GH
where C is the output function and R is the input. If GH is made much larger than
one, the closed loop response approaches 1/H and becomes independent of the ampli-
fier gain. Thus, GH determines the sensitivity of the closed loop gain to changes in
amplifier gain.

203
 FEEDBACKAND SERVO AMPLIFIERS- TRANSISTORCHOPPERS

Since CH is a complex quantity whose magnitude and phase are a function of

frequency, it also determines the stability of the amplifier. The phase shift of CH for
all frequencies must be less than 180° for a loop gain equal to or greater than one or
the amplifier will become unstable and oscillate. Therefore, if the number of transistors
in the amplifier is greater than two, the phase shift of CH can exceed 180° at some
frequency, and stabilization networks must be added to bring the loop gain to one
before the phase shift becomes 180°.

ZF

GAIN AND IMPEDANCE

RELATION SHIPS
l.=!-.-
1

z, z,
Z1n=-1+GH i:::
(A) BLOCK DIAGRAM l+A 1 y ZL

Zon
Zo~----
1+ Ai Z 0 n
ZF

GH• AjYZL
y y' Zt+YZL

z
on IL
l RL Y=~
I

Zon
CONDITIONS'..!!,_« I·
z9 •
Z1
( B) SIMPLIFIED EQUIVALENT CIRCUIT --«GH+I
ZF

VOLTAGEFEEDBACKAMPLIFIER
Figure14.2
Figure 14.2 shows a voltage feedback amplifier where both the input and output
impedances are lowered. A simplified diagram of the amplifier is shown in 14.2(B),
which is useful in calculating the various gains and impedances. Z1 is the input im-
pedance of the first stage without feedback, and Zoais the output impedance of the last
stage without feedback. Ai is the short circuit current gain of the amplifier without
=
feedback (the current in the load branch with RL 0 for a unit current into the base
of the first transistor). Any external resistors, such as the collector resistor which are
not part of the load can be combined with Zoa• The gain and impedance equations
shown are made assuming that the error voltage (ibZi) is zero which is nearly correct
in most cases. If this assumption is not made, the loop gain of the amplifier can be

204
 FEEDBACK AND SERVO AMPLIFIERS - TRANSISTOR CHOPPERS

derived by breaking the loop at y-y' and terminating the point y with Z1o<2> The loop
gain is then itlib1 with the generator voltage set equal to zero. Since the loop is a
numeric, the voltage and current loop gains are identical. The loop gain is then
A· ( Zt' ) ( Zsr ) (14a)
I Zt' + ZF + Zi' z. + z.
where
ZL, = Zt Zon
-z--z-
L + on
=z
t'Y, an
d

Zi' = z, Z1
z,+Z1
Notice that if Z1 > > Z1and ZF > > Z1,then the loop gain is very nearly equal to GH
as given in Figure 14.2.
The input impedance of the amplifier is reduced by 1 + GH, while the output im-
pedance is also decreased.
Figure 14.3shows a current amplifier where both the output and input impedances
are increased. The loop is obtained by breaking the circuit at y-y' and terminating
points y-a with Z1.The loop gain is i,/ib and is approximately equal to
-yAiZv (14b)
z,+z.

GAIN AND IMPEDANCE

.,
RELATIONSHIPS

A1 yz 9
lg !L. z 9 +Z1
ig l+A1YZF
z1+z9
OL A1YZL
(A) BLOCK DIAGRAM o;• l+A1YZF
z1+z 9
z,n• z1\+A1[ ZF)
1

y y' Zo'" Zon/l+A1 ZF)

\ z1+z9
GH11A1YZF
.t Zon ZL z1+z 9
lg I
y• l+ZL
Zon
Og
Iga-
Zg
CONDITIONS:

(B) SIMPLIFIED EQUIVALENT CIRCUIT

CURRENTFEEDBACK
AMPLIFIER
Figure 14.3

205
FEEDBACK AND SERVO AMPLIFIERS - TRANSISTOR CHOPPERS

SERVO AMPLIFIER FOR TWO PHASE SERVO MOTORS

PREAMPLIFIERS
Figure 14.4 shows a two stage preamplifier which has a low input impedance, and
which is quite stable in bias point and gain over wide temperature ranges. In addition,
no selection of transistors is required.
Because only two stages are involved, the amplifier is stable, and frequency stabili-
zation networks are not required. The current gain io/i1n is approximately REIRF if the
generator impedance and RE are much larger than the grounded emitter input imped-
ance of Q1, RF should not exceed a few hundred ohms because it contributes to the
loss of gain in the interstage coupling network. The loss of gain in the interstage
coupling is
K- Zo1' (14c)
- Zoi' + h1e2+ hre2RF
where Zo1'is the parallel combination of R2and the output impedance of Ql. The loop
gain then is approximately
(14d)

-------------a Eee=45V

C1n

~.....0---
20µ.f

lin

22K
01 =02 =G.E. 2N335,4C30,
4C31,OR 2N336

.:-i~~FOR,!!!,_«I.
ljn Rf R4

400 CYCLE PREAMPLIFIER FOR OPERATION IN

AMBIENTS OF -55 TO 125°C
Figure 14.4

Because the feedback remains a current, the input impedance of this circuit is quite
low; less than 100 ohms in most cases. This preamplifier will work well where current
addition of signals is desired and "cross-talk" is to be kept to a minimum.

Bias Design Procedurefor Stage Pair

(Reference Figure 14.5)
1. The values of Eaa, 1£1, IE2,VcE1, and VcE2 are selected by the designer to be com-
patible with the constraints imposed by the circuit and component specifications.
Thus, IE1 and Esa must be large enough to prevent clipping at the output under

206
 FEEDBACK AND SERVO AMPLIFIERS- TRANSISTORCHOPPERS

conditions of maximum input. For designs which must operate in wide tempera-
ture environment, the bias currents and voltages (IE and VcE) of Q 1 and Q2
should be approximately equal to those used by the manufacturer for specifying
= =
the "h" parameters. (For the 2N335, IE1 IE2 1 ma and VcE 5 to 10 volts.) =
___ ....,. _____ .,_ ___ 0E1111

Figure14.5

2. For good bias stability, lt:1 R1 should be five to ten times VEn1,i.e., 3 to 5 volts;
thus, knowing lt:1, R1 can be found. Ir. should also be five to ten times larger
than Ia1.
3. R _ Ebb - V CF.I - lv.1Rt
(14e)
IE1+ la1
2
-

where
J = h-h:2 + Icuo2, I 01 = h-
IE1 + Icu01, (14f)
82
FE2 FEt

and where hFi-:1and hn2 are the typical D.C. current gains at the particular bias
conditions. Iceo is the collector-base leakage current at the temperature and
collector-base voltage being used.

4. R -
~-
IEt Rt +
Is
VF.BI
(14g)

where L is selected to be 5 to 10 times larger than lu1,

5. R~·_ Vcv.1 - Vv.111- V1rn2 (14h)

.- Ir.+ l01

6. R _ I.:1 R1 + Vcv.1 - Vt:n2 (14i)

lt:2- (L1+ l01)
3
-

1. It = Eun - Ra
l1-:2 (14j)
2 li-:2

8. (14k)

where G1 is the desired closed loop a.c. current gain. (The emitter by-pass
capacitors are selected to present essentially a short circuit impedance at the
lowest frequency of interest.)

207
FEEDBACK AND SERVO AMPLIFIBRS - TRANSISTOR CHOPPERS

Figure 14.6 shows a three stage, 400 cycle direct-coupled preamplifier with good
bias stability from -55 to 125°C. If the de conditions shown in the figure are met,
the collector voltage of Q3 is approximately
Vea= [(R1+Re+ R11)
~] (Ee - Vm) + (R1+Re+ R11)
Vu, (! 4 1)
CltR1Ra Rt
where Vu1 is the breakdown voltage of the first avalanche diode. The various ac gains
and impedances can be calculated from the equations of Figure 14.1 with the exception
that the ac feedback is now approximately

( ~·) ( !: ) (14m)

where I/Rt' =
1/Rt + 1/Roa + l/R1, and Roais the output impedance of Q3. This
assumes that the input impedance of Q 1 is much less than R, and Ro. The value of R,o
determines the closed loop gain, while the values of C.1, C.2, ft., and Ro are used to
bring the magnitude of the loop gain to unity before the phase shift reaches 180°. The
values required for these capacitors and resistors are dependent upon the maximum
expected loop gain.

Eeo•45V

~-----~
.
1,•

Oz
16V

01 •Oz• 0 3 • GE 2N335, 4C 30

Re

BIAS STABILITY REQUIREMENTS:

(l)l»R3+J1zR4 l3)Ico1<Rx+R3)« Voa

WHERE :R1IR9+R9I
Al2 Al3 • .!..£!..
WITHOUT FEEOBACK
Ioz
Rx• R1 + Re+ Rg Icoa • MAXIMUM IcoOF 01
V131• BREAKDOWN VOLTAGE OF 01
Bz• h FE2
I( 1 • h FOi

THREE STAGE DIRECT COUPLED400 .- PREAMPLIFIER

Figure14.6
DRIVER STAGE
Because the output stages of servo amplifiers are usually operated either Class B
or a modmed Class B, the driver must provide phase inversion of the signal. In most
cases, this is accomplished by transformer coupling the driver to the output stage. The
phase shift of the carrier signal in passing through the transformer must be kept small.

208
 FEEDBACK AND SERVO AMPLIFIERS - TRANSISTOR CHOPPERS

However, since the output impedance of the transistor can be quite large, the phase
shift can be large if the transformer shunt inductance is small, or if the load resistance
is large as shown in Figure 14.7. The inductance of most small transformers decreases
very rapidly if a de current flows in the transformer. Therefore in transformer coupling,
the phase shift of the carrier is reduced to a minimum if the de current through the
coupling transformer is zero, or feedback is used to lower the output impedance of
the driver.

,----i lo •hfe lln

I ---. I r,s , T
IL, a <l'.S+I•y.1.0
I IL' I I

! IILp "''! Ta
I
_L_
yRt
Ro
I - - I ya Ro+Rt
L!~~F~M.!~ S "LAPLACE
8 REFLECTED TRANSFORM.
LOAD
Lp• PRIMARYSHUNT L
I\:•LOADREFLECTED
TO PRIMARY

CARRIER PHASE SHIFT DUE TO TRANSFORMERCOUPLING

Figure 14.7

Figure 14.8 shows a modified ..long tail pair" driver. In this case QI and Q2
operate Class A, and the quiescent collector current of QI and Q2 cancel magnetically in
the transformer. Transistor Ql operates grounded emitter, while Q2 operates grounded
base. Separate emitter resistors R1 and Ri are used rather than a common emitter re-
sistor in order to improve the bias stability. The collector current of QI is approximately
hr.1 ibt, while the emitter current of Q2 is (hra1+ I) ib1,Since Q2 operates grounded
base, the collector current of Q2 is -hrb2/(hro1 + I) ib1or -hro ib1if the current gain
of QI and Q2 are equal. Thus push-pull operation is obtained.

C3 • TRANSFORMER
TUNNING CAPACITOR

01 • 02 a G. E. i:~i~
2N2108

TWO STAGE CLASS "A" PUSH-PULL DRIVER

Figure 14.8

209
 FEEDBACK AND SERVO AMPLIFIERS - TRANSISTOR CHOPPERS

RE 9,IK 01 •Oz •G.E. 2N656A, 2N2017, OR 2N2108

01 • G.E. 2N335A, 4C30
15K Ic:1• Icz • IOMA.
C4 •ADJUST TO TUNE T

"STABLE"400 CYCLEDRIVER
Figure14.9

In order to stabilize the driver gain for variations in temperature and interchange-
ability of transistors, another transistor can be added to form a stage pair with Q 1 as
shown in Figure 14.9. The gain of the driver is then very stable and is given approxi-
mately by
(14n)

OUTPUT STAGE
The output stages for servo amplifiers can be grounded emitter, grounded collector
or grounded base. Output transformers are generally not required because most servo
motors can be supplied with split control phase windings. Feedback of the motor con-
trol phase voltage to the driver or preamplifier is very difficult if transformer coupling
is used between the driver and output stages. If a high loop gain is desired, the motor
and transformer phase shifts make stabilization of the amplifier very difficult. One
technique which can be used to stabilize the output stage gain is to use a grounded
emitter configuration where small resistors are added in series with the emitter
and the feedback is derived from these resistors. The motor time constants are thus
eliminated and stabilization of the amplifier becomes more practical.
A second technique which results in a stable output stage gain and does not require
matched transistor characteristics is the emitter follower (common collector) push-pull
amplifier as shown in Figure 14.10. Also it offers the advantage of a low impedance
drive to the motor. A forward bias voltage of about 1.4 volts is developed across DI
and D2, and this bias on the output transistors gives approximately 20 ma of no signal
current. At lower levels of current the cross-over distortion increases and the current
gain of the 2N2202 decreases. D3 and D4 protect the 2N656A's from the inductive
load generated voltages that exceed the emitter-base breakdown. The efficiency of this
circuit exceeds 60% with a filtered DC voltage supply and can be increased further

210
 FEEDBACK AND SERVO AMPLIFIERS - TRANSISTOR CHOPPERS

01 =Q2 = G.E. 2N2202

2N2203
2N2204
2N2196
2N2197
+-(TUNED 7FI, 7F2,
CONTROL OR 7F3
PHASE OF
SERVO
MOTOR)
TRANSFORMER-Ni:N2:N3•1:1:1
1
DI, D2,D3,D4- INl692 S

SERVO MOTOR DRIVE CIRCUIT

(1 TO 4 WATTS)
Figure14.10

by using an unfiltered rectified ac supply. This unfiltered supply results in lower

operating junction temperatures for the 2N2202's, and in tum permits operation at a
higher ambient temperature. The maximum ambient operating temperature varies
with the power requirements of the servo motor and the type of heat radiator used
with the 2N2202. It is practical to attain operation in ambients to 125°C.
Another technique which results in a stable output amplifier gain over wide am-
bient temperature extremes and which is compatible with low gain transistors is shown
in Figure 14.11. In this case, a grounded base configuration and a split control phase
motor winding are used. The driver is coupled to the output stage by means of a step-
down transformer, and the current gain occurs in the transformer since the current
gain of the transistors is less than one. The current gain is 2aN Pi/N s1 if the drivers
are operated Class A such as shown in Figures 14.8 or 14.9. The negative unfiltered de
supply and diode D 1 are used to operate the transistor Class AB and eliminate cross-
over distortion. As the signal increases the diode Dl becomes conductive and shunts
the bias supply. The operation of the output stage thus goes from Class A to Class B.
An unfiltered de is used for the collector supply to reduce transistor dissipation.
If saturation resistance and leakage currents are neglected, 100% efficiency is possible
under full load conditions with an unfiltered supply. The transistor dissipation is
given by
P = Ee,?
4RL
[a- a 2
( I + .!h.)J
RL
+ PL (140)

where PL is the dissipation due to leakage current during the half-cycle when the
transistor is turned off, a is the fraction of maximum signal present and varies from
0 to 1, R. is the saturation resistance, RL is the load resistance, and Ec11: is the peak
value of the unfiltered collector supply voltage. If PL is negligible and R./RL 1,<<
then maximum dissipation occurs at a =
1/2 or when the signal is at 50% of its maxi-
mum. Thus for amplifiers which are used for position servos, the signal under steady-
state conditions is either zero or maximum which are the points of least dissipation.

211
 FEEDBACK AND SERVO AMPLIFIERS - TRANSISTOR CHOPPERS

CONTROL
PHASE
TO
DRIVER
TRANSISTORS Np
2
0
MOTOR

01•O2•GE ,~~203

D1 •GE IN676
Np
-» I
OR RI
1_M/\/\
Ee
0
[1LINE
N5
C IS ADJUSTED FOR MAXIMUM
STALLED TORQUE
+
WEeM
Ee T

GROUNDED
BASESERVOOUTPUT
STAGE
Figure 14.11
The peak current which each transistor must supply in Figure 14.11 is given by
. 2W
lm=-- (14p)
EcH

where Wis the required control phase power. The transistor dissipation can then be
written in terms of the control phase power

(14q)

The driver must be capable of supplying a peak current of

~(~)
Cl NP1
(14r)

where ci is the grounded base current gain of the output transistor.

Figure 14.12 shows a complete servo amplifier capable of driving a 3 watt servo
motor in an ambient of -55 to 125°C (if capacitors capable of operation to 125°C are
used). The gain can be adjusted from 20,000 to 80,000 amperes/ampere by adjusting
Rr in the driver circuit. The variation of gain for typical servo amplifiers of this design
is less than 10% from -55 to 25°C, and the variation in gain from 25 to 125°C is
within measurement error. The variation in gain at low temperature can be reduced if
solid tantalum capacitors are used instead of wet tantalum capacitors. The reason is
that the effective series resistance of wet tantalum capacitors increases quite rapidly
at low temperatures thus changing the amount of preamplifier and driver feedback.
The effective series resistance of solid tantalum capacitors is quite constant with tem-
perature. Many 85°C solid tantalum capacitors can be operated at 125°C if they are
derated in voltage.

212
 I
PREAMPLIFIER DRIVER OUTPUT

~
+GOV
0 i
~
fl
SIK =--::

~
t:,
Cl)
tz1
TO
+sov PEAK ~
UNFILTERED 0
FULL WAVE
RECTIFIED400 CYCLES ~
INPUT <>-i ~
----•
6µ.f
TO -SOV PEAK
UNFILTERED FULL
WAVE 400v
a
~
I
T1, -12.5:1 STEP DOWN(TURNS RATIO}
01, - GEIN676

NOTES: I. ADJUST RF FOR DESIREDGAIN.

i....
Cl)
Cl)
2. Cg ADJUSTED TO TUNE MOTOR FOR
01 ,02 103,-GE 2N335 OR GE 2N336
MAXIMUM STALLED TORQUE. ~
04 ,05 ,- GE 2N656A
06 ,07 ,--GE
OR 2N20l7
2N2202, 2N2203, OR 7F3
3. CGADJUSTED TO TUNE T1 .

;
-
w
w
3 WATT 400 CYCLE SERVO AMPLIFIER FOR -55 TO 125°C OPERATION
Figure14.12
gJ
Cl)
FEEDBACK AND SERVO AMPLIFIERS - TRANSISTOR CHOPPERS

JUNCTION TRANSISTOR CHOPPERS

Transistor choppers are used in the amplification of low level d.c. signals, as well
as in the conversion of d.c. signals to a synchronous a.c. voltage for driving the control
phase of two phase servo motors. The chopper converts the d.c. signal to a synchronous
a.c. voltage whose magnitude is proportional to that of the d.c. signal, and whose phase
relationship to the reference a.c. voltage is either zero or 180°, depending upon the
polarity of the d.c. voltage. This can best be seen by referring to Figure 14.13(A). The
chopper contacts close during the positive half cycle of the a.c. reference and open
during the negative half cycle. With the switch in position 1, the positive voltage E. is
tied to the resistor Ras shown in Figure 14.13(B) during the positive half cycle of the
reference. During the negative half cycle of the reference, the chopper contacts are
open and the voltage across R is zero. The capacitor removes the d.c. level such that eo
is now an a.c. square wave which in phase with the reference a.c. If the switch is in
position 2, the negative voltage E. is applied to R during the positive half cycle of the
reference voltage, and as can be seen in Figure 14.13(C), the output is 180° out of
phase with the reference a.c.

~~Wc'ls C
i-,
+ A.C.SWITCHING
VOLTAGE
l
.lR
to

+
~

IA)

REFERENCE+
A.C.OT\.
.vvA
+1-----
Es 0----------------- Es0-----------------
eR +~.r:::Lel_. -1-----
'R~LJD"
O:"S____r:::,_ __ l
-,121=:.:r---c:::r
WAVEFORMSFOR WAVE FORMSFOR
SWITCHIN POSITION
I SWITCHIN POSITION
2
IBI CCI

HALF-WAVECHOPPER
Figure 14.13

Figure 14.14 shows a single transistor replacing the mechanical chopper. When the
base voltage is made positive with respect to the collector (NPN transistor), the tran-
sistor behaves as a closed switch, and the d.c. input voltage is connected to R. During
the half cycle of the reference voltage when the base is made negative with the supply,
the transistor behaves as an open switch, and the voltage across R is zero. However,
the transistor is not a pedect switch, and an error voltage and current are respectively
superimposed on the d.c. source. During the half cycle that the switch is closed, the
error voltage introduced by the transistor is
VEc = .026 ln ciN + Is Re' {14s)
where ciN is the normal alpha as defined in Chapter 5, and Re' is the collector bulk or

214
 -~
FEEDBACK AND SERVO AMPLIFIERS - TRANSISTOR CHOPPERS

o.c.

11s-7
T
R
IOK._____.i

A.C,
REFERENCE

0 1=G,E, 2N2193
OR 2N2195
Ee= 5 VOLTS PEAK
SINE OR SQUARE
WAVE.

SIMPLE SERIES TRANSISTORCHOPPER

Figure 14.14

body resistance. The error current which is introduced when the transistor is an open
switch is
I Pl= lcso e&1 (1 - e&s) (14t)
C&N (1- C&s e&1)

where ci, is the inverse alpha and lcso the leakage current as defined in Chapter 5.
The error voltage introduced by the transistor during the "on" half cycle can be
minimized by using two transistors whose offset voltages cancel one another as shown
in Figure 14.15. The transistors must not only be matched at room temperature but
must track over the required ambient temperature extremes. This is no problem with
the G-E 2N2356 planar epitaxial transistor where two transistor pellets are both
mounted in the same TO-5 package. Initial offset voltage matches of 50 microvolts or
less, and drifts of less than ±100 microvolts over an ambient of -55 to 125°C are
easily obtainable. For the G-E 2N2356A the maximum offset between -55°C and
125°C is 50µv. For many applications the drift due to leakage current can be eliminated
by using diode D1 and resistor RAto prevent the collector-base junctions from being
reverse biased. This will eliminate any leakage current due to the base drive from
Howing in the load. As will be shown below, the emitter-collector impedance will still
be quite high.

II~ REF~ENCE

NOTE:
I. QIA QIB -GE 2N2356 OR 2N2356A (TWO MATCHED TRANSISTORS
IN ONE TO-5 PACKAGE)
2. ELECTROSTATIC SHIELDING BETWEEN PRIMARY AND SECONDARY
WINDINGS OF TRANSFORMER T MAY BE REQUIRED.
3. RealOK, Ee 11 IO VOLT PEAK (SINE OR SQUARE WAVE).

AN IMPROVED SERIES TRANSISTORCHOPPER

Figure 14.15

215
FEEDBACK AND SERVO AMPLIFIERS - TRANSISTOR CHOPPERS

..
Oz R

01 •Oz• GE 2N2193. 2N2195 OR 2Nl279 OR 2N2356, 2N2356A.

NOTES:
I.R 8 •10K
2,Ea • 7.5V PEAK SINE OR SOUAREWAVE FOR
2N2193, 2N2194 OR 2N23!16.
3.E8 •l.5V PEAK SQUARE WAVE FOR 2Nl279

SERIES-SHUNTCHOPPER
Figure14.16
A chopper configuration 14• 5> which can be used to advantage for a low source
impedance input is shown in Figure 14.16. During the half cycle when Q1 is "on," Q2
is turned "off' because its collector-base junction is reverse biased, and R is tied to the
d.c. input. On the next half cycle when Qi is turned "off," Q, is turned "on," shorting R.
The leakage current due to Qi does not How through R during this half cycle since Q,
essentially short circuits R. During the alternate half cycle when Q2 is turned "off," its
0
leakage current will flow primarily through Q. (its turned "on° and the input circuit )

if R is made much larger than the source impedance. Thus, the drift due to leakage
current is minimized. In addition, the offset voltages of the two transistors effectively
cancel, even though they occur on separate half cycles. The reason for this is that they
form a d.c. voltage which is not chopped and which is not passed by the capacitor, C.
An advantage this circuit has over the chopper circuits discussed above is that it is less
sensitive to noise pickup because the load always looks back into a low impedance.
Figure 14.17 shows a transistor chopper used for high source impedance applica-
tions or those where the d.c. input cannot be loaded. Although R. is shown as part of
the chopper circuit, it can be the d.c. source impedance.

11],.f RL to
2K

NOTES:
I. R5 CAN BE SOURCE IMPEDANCE OF 50K TO SEVERAL MEGOHMS.
2. Ee •10 VOLT PEAK SINE WAVE FOR GE 2N2195, R9•IOK
3. Ee •IOVOLT PEAK SQUARE WAVE FOR GE 2Nl279, Re•IOOK
4. 0 1 •GE 2N2195 OR 2N1279

SHUNT CHOPPERFOR HIGH IMPEDANCE SOURCES

Figure 14.17

216
 FEEDBACK AND SERVO AMPLIFIERS - TRANSISTOR CHOPPERS

Operation of this chopper is basically one of shorting node A to ground each half
cycle when the base of the transistor is made positive with respect to ground (the
collector). A zeroing adjustment for removing the transistor•s offset voltage is pro-
vided by Di, Rz. and Rawhich causes a current to flow during the half cycle from
collector to emitter [see equation (5g) in Chapter 5]. In some applications where the
2N2195 is used. the offset voltage is small enough (less than a millivolt) so that the
balance network can be eliminated.
On the half cycle of the supply which would normally reverse bias the collector-
base junction of Q, the diode D1 prevents this from occurring. The collector-base poten-
tial is then zero; however, Chaplin and Owens<0 > have shown that the emitter-collector
impedance is given by

rEc =0Icao
-026 (1 + a.~da.,- 2 a.s) (14u)

Thus the dynamic impedance is approximately 26 mv. divided by the Iceo. For silicon
transistors (even at high temperatures) this impedance can be made larger than the
load impedance so that the current at node A due to the input d.c. voltage flows into
the load during this half cycle. The maximum value of the load is then determined by
the minimum value of ro obtained from equation (14u). Also, any drifts which normally
would have been caused by the transistor leakage currents have been eliminated.
For the condition that rEc> >R,,, the peak to peak load current is given by
I _ 2 Eo.c. (14v)
p-p - R.+ 2 RL
The equivalent input current drift due to drift in transistor offset voltage (.iV) is
shown to be
Io =~v
R. for R, > > RL (14w)

A second component of the chopper drift is due to transient current spikes which
occur when the transistor switches "on.. and "off... The net area (charge) of the tran-
sients develops a potential on the capacitor C which, to the circuit, appears as an input
signal. In order to zero the output, a d.c. input current (integrated over one-half cycle)
must be provided.
Temperature drift tests made using 2N2195•s and 2Nl279•s show that with the
entire chopper of Figure 14.17 exposed to temperature, the required d.c. input neces-
sary to zero the output is less than 10-s amperes from -55 to 125°C. This is equivalent
to 1 mv of drift referred to the input for R. = 100 K.

REFERENCES
m Hurley. Richard B.• "Designing Transistor Circuits - Negative Feedback for Transistor Amplifiers:•
Electronic Equipment Engineering, Feb. 1958.
<2 > Hellerman, H., "Some Stability Considerations in the Design of Large Feedback Junction Transistor
Amplifiers.'' Conference Paper #CPSB-87, presented at the 1958 AIEE Winter General Meeting.
<3 > Blecher. F.H., "Transistor Circuits for Analog and Digital Systems," Bell System Technical Journal,
Vol. 35, March, 1956.
m Kruper, A., "Switching Transistors used as a Substitute for Mechanical Low Level Choppers.''
AIEE Transactions, Vol. 74, pt. I. March, 1955.
<5 > Giorgis, J .• and Thompson, C.C •• "Silicon Transistor Performance in a Chopper Application, ..
Applications and Industry, #37, July 1958.
<0> Chaplin, G.B., and Owens, A.R., "Some Transistor Input Sta~es for High-Gain D.C. Amplifiers,"
The Proceeding, of the I.E.E., Vol. 105, pt. B, No. 21, May, 1958.

217
TRANSISTORMEASUREMENTS

INTRODUCTION
Accurate measurements demand a thorough knowledge of measurement principles
and pitfalls. To simplify these measurements, such that they are non-discretionary
go-no go types, requires in addition, prior information about the device characteristics
and their probable distribution. Transistor measurements in particular, due to the
extreme power sensitivity of signal transistors and the active amplifier nature of the
device, impose great demands on the skill and ingenuity of the test-equipment
designer.
To obtain precision and accuracy in transistor measurements, not only must the
definition, meaning, and limits of each test be considered ( as well as the actual meas-
urement methods), but attention must also be given to the effect of the measurement
upon the device. To illustrate: the transistor is a non-linear device and under normal
D.C. bias conditions the Emitter-Base voltage drop in a Germanium transistor is about
250 millivolts. If linear (small-signal) measurements are to be made, it becomes
obvious that the rapid curvature of the forward-biased diode characteristic precludes
the usual "one order of magnitude less" argument normally applied to signal/bias
relationships for small-signal measurements and demands even smaller peak-to-peak
signal excursions.
In addition, the transistor is a current amplifier and the effect of the input signal
on the output current must be considered. Thus, prior knowledge of probable input
impedance and device current gain becomes necessary. For example, assuming an
ideal transistor at low frequency and neglecting parasitics, in measuring h,.

h •• = ~bl
lb
and h,. =~, lb
e.,=0 e.,=0
then,
eb
-h an d.1.,
••
= h r. .
lb

from the theory (see any basic transistor text) h,. = (1 ~ ao) ~ hr .. r.,
, h h .
( smce re = (l _ao ao) ) so t at 1., = reb• ;
a lso, r. = qL~
kT (see any b as1c
· transJStor
· text) wh ere k = Bo1tzmann 's Const an,t

T = temperature in degrees Kelvin, and q is the charge of the electron. Now,

kT
q = 26. X 10-a volts at room temperature; and, assuming
le = It: ( within 10% )
26 X 10-a
r., = le

i" is very much less than le, (say i.. = .1 le) for small signal measurements.
219
TRANSISTORMEASUREMENTS

Then,

or,
1
26
e; :
0
-a =0.1 le whence eb ;a 26 x 10~
so that the maximum signal swing, eh, should be in the order of 2.5 millivolts and is
largely independent of gain or collector current.

However, when the transistor is driven from a current source it is seen that since

. h ... , th en lb. eb mnx

-h-
Cb mu= lb mn max=
...
or,
. eh max 25 X 10~
lb mnx = h,. r.. e!!! 25 X 10-11
hr..mu X le
whence,
le
ib max= 1Ohfe max

Here a knowledge of the probable range of hr. expected is quite important. Thus,
depending upon whether a current source or a voltage source is used in small signal
measurements, care must be exercised to insure that small signal conditions truly exist.

REVERSEDIODE CHARACTERISTICS
General
Ieo or ho are the leakage currents within the safe operating region of reverse
voltage and are intended to yield comparative, evaluative information as to permissible
operation, surface condition and temperature effects on operation.
The breakdown voltage tests are indicative of the maximum voltage that can be
applied to the device and serve to indicate the voltage at which "avalanche-breakdown"
and "thermal-runaway" take place.
The curves of Figures 15.1 and 15.2 are arbitrary but representative ones for tran-
sistors and are included to explain what some of the reverse diode characteristic tests
mean, and the points at which they are taken. In Figure 15.1, the collector to base
reverse voltage of a transistor versus the leakage current is displayed; the points of
interest are point A, the leakage current ( leso in this case) at a specified collector to
base junction voltage, and point B, the breakdown voltage ( BVeso in this case ) at a
specified leakage current. Figure 15.2 illustrates some points which must be considered
when accurate breakdown voltage measurements are desired. The two transistors
shown have different reverse voltage characteristics. The load line of the measuring
instrument which is to approximate a constant current source may give slightly or
grossly erroneous readings if care is not exercised in measurement technique. The true
values of breakdown voltage are shown at points A. The slightly erroneous readings
are at points B on the two characteristic curves while the grossly erroneous data is at
points C.

220
 TRANSISTOR MEASUREMENTS

( EMITTER OPEN)

DESIREDBREAKDOWN
@ VOLTAGEINFORMATION

Vee BVceo (Q) SPECIFIED I CB

REPRESENTATIVECOLLECTOR-BASE
JUNCTION REVERSECHARACTERISTICS
Figure 15.1

COMPARISON OF MEASUREMENTS ON TWO TRANSISTORS SHOWING ERRORS THAT MAY

ARISE DUE TO TECHNIQUE- i.o., LOAD LINE CONSTANT CURRENT APPROXIMATION IS POOR
ANO DOES NOT MEASURE DEVICE AT SPECIFIED CURRENT

BVceo CHARACTERISTICS

Iceo

Vee REVERSE VOLTAGE

BVcno MEASUREMENTTECHNIQUES
Figure 15.2

D. C. TESTS
The following abstracts include the definitions of particular tests and the associated
simplified circuits. The current measuring ( lcso, l•:110,etc. ) circuits are discussed in
more detail in the next section.

221
TRANSISTORMEASUREMENTS

1. Icao, commonly called Ico, is the de collector current which Bows when a speci-
fied voltage, Vcao, is applied from collector to base, the emitter being left open
(unconnected). The polarity of the applied voltage is such that the collector-
base junction is biased in a reversedirection. (Collector is negative with respect
to the base for a PNP transistor.)

lcao MEASUREMENT
Figure15.3

Ico is greatly dependent on temperature and in some instances, transistors

must be handled with gloves to prevent heating the transistor by contact with
the operator's hand.
2. limo, commonly called I1m, is the de current which Bows when a specified
voltage is applied from emitter to base, the collector being left open (uncon-
nected). The polarity of the applied voltage is such that the emitter-base
junction is biased in a reverse direction. (Emitter is negative with respect to the
base for a PNP transistor). IEo also is greatly dependent on the temperature and
the same precautions apply as for Ico determination.

IEBO MEASUREMENT
Figure15.4

3. lcEo is the de collector current which flows when a specified voltage is applied
from collector to emitter, the base being left open (unconnected). The polarity
of the applied voltage is such that the collector-base junction is biased in a
reverse direction. (Collector is negative with respect to the emitter for a PNP
transistor.) lcEo is greatly dependent on temperature and the operator should
use gloves when handling transistor before measuring.

lcEo MEASUREMENT
Figure15.5

222
 TRANSISTORMEASUREMENTS

4. lcEs is the de collector current which Hows when a specified voltage is applied
from collector to emitter, the base being shorted to the emitter. The polarity
of the applied voltage is such that the collector-base junction is biased in a
reverse direction. (Collector is negative with respect to the emitter for a PNP
transistor.)

lcF.s MEASUREMENT
Figure15.6

5. hes is the de emitter current which Hows when a specified voltage is applied
from emitter to collector, the base being shorted to the collector. The polarity
of the applied voltage is such that the emitter-base junction is biased in a
reverse direction. (Emitter is negative with respect to the collector for a PNP
transistor.)

h:c11MEASUREMENT
Figure15.7

6. BVcETests-BVc1m, BVcER,BVcEs,BVcEv
A BVcE test is a measurement of the breakdown voltage of a transistor in
the common emitter configuration. For the measurement to be meaningful, a
collector current must be specified.

Figure15.8

223
TRANSISTORMEASUREMENTS

In measuring BVcE breakdown voltages, a constant value of collector

current, le, is caused to Bow in the reverse direction (collector is negative with
respect to the emitter for a PNP transistor) and the collector to emitter voltage,
VcE, is read on the meter. This voltage reading is the BVcE breakdown voltage
required.
In addition to a collector current specification, the condition of the base
lead must be specified.
a. BVcEo is the common emitter breakdown voltage (for a specified collector
current, le) when the base is left open (unconnected).
b. BVcEa is the common emitter breakdown voltage (for a specified collector
current, le) when a resistor of a specified value, R, is connected from the
base to the emitter.
c. BVcEs is the common emitter breakdown voltage (for a specified collector
current, le) when the base is shorted to the emitter.
d. BVcEv is the common emitter breakdown voltage (for a specified collector
current, le) when the base is biased with a voltage with respect to the
emitter.
e. BVcEx is the common emitter breakdown voltage (for a specified collector
current, le) when the base is terminated through a specified circuit to the
emitter.
It should be strongly emphasized that BVcE, by itself, is meaningless
unless (1) a collector current is specified, (2) the condition of the base lead is
specified (by the use of a third subscript), (3) and, if the measurement is for
BVcEa or BVcEv,a definite resistor, R, or a definite voltage, V, are specified,
or for BVcEx a definite circuit is specified.
7. BVcso is a measurement of the breakdown of the collector-base junction with
the emitter open. A collector current, le, must be specified.

j ~Ic-~vc•
_____
___________
r

..,_
,----

J:

IL-
l _
-- --- ----,

----
CONSTANT-CURRENT:
GENERATOR
________
I
I
__,

BVcso MEASUREMENT
Figure15.9

The emitter is left open (unconnected) as specified by the third subscript.

A collector current, le, is caused to flow through the collector-base junction
and the voltage drop Vcs is the breakdown voltage, BVcso, Polarity is such
that the collector-base junction is biased in a reverse direction (collector is
negative with respect to the base for a PNP transistor).

224
 TRANSISTORMEASUREMENTS

8. VaT (reach through). Reach through voltage is that voltage which, when ap-
plied from the collector to base, causes the collector space charge layer to
expand into the emitter junction.

SIMPLE GO-NOGO VaT MEASUREMENT

Figure15.1O

In Figure 15.10, if, when switch .,S" is closed, le does not increase, the
punch through voltage is greater than Vcc. Punch through may also be meas-
ured by the use of the circuit shown in Figure 15.11.

VTVM
INPUT
R >10 MEG VTVM

ALTERNATEGO-NOGO VaT MEASUREMENT

Figure15.11

If Vt:a is less than 1 volt, then VaT > (Vee -1) volts.
The above VaT tests are go-no go in character. By making Vee variable
actual values may be determined; for example, in the circuit shown in Figure
15.12 one can adjust Vee until the VTVM reads 1.0 volt, then VaT equals
Vcs -1 volts.

+
VTVM

VaT MEASUREMENT
Figure 15.12

225
TRANSISTORMEASUREMENTS

CURRENT
MEASUREMENTS
I. General
In this section the elaboration of the basic circuit into actual test equipment
(both qualitative and quantitative) is delineated. The necessity of saving time
in measurement is considered of importance; and means that constant voltage
and constant current techniques will be used. (Constant within the accuracy
requirements desired.)
Certain problems arise concommitant with constancy. A voltage source, by
definition, makes it difficult to limit the current through the ammeter in the
event of device failure; and current sources have large open-circuit voltages prior
to test, which can be damaging to the operator; and, due to circuit capacity, if
the device has an extremely short thermal time constant, the unit under test
may be damaged from the large instantaneous currents that can flow.
For the above reasons voltage and current "clamps .. are resorted to in
order to have the required constancy and are discussed, with their limitations,
in conjunction with each class of test.
2. Clamp Circuits
In the circuits shown in Figures 15.13 through 15.16, the measurement of
lcso is accomplished. In Figure 15.13, the basic form of the circuit is shown.
There is some error in this simple arrangement in establishing the test voltage
conditions since there is a small voltage drop across the meter. Also, if a unit
is shorted or has an excessively high leakage current, the microammeter may
be damaged. For meter protection the circuit of Figure 15.14 is used. The
diode used here is a large area diode which has a reverse leakage current
greater than that which is intended to be measured. If a 1N91 is used the
maximum leakage current which could be measured would be approximately
10 µa since this is the maximum reverse current which the 1N91 will conduct
when a small reverse voltage is impressed across it. To avoid this current
limitation and still protect the microammeter the circuit shown in Figure 15.15
is used. This circuit is basically a form of bridge so that if the drop through
the limiting resistor is not enough to bring the reference point (the collector)
below the clamp voltage, current flows through the diode and the voltage
at the reference is that of the clamp supply less the forward drop in the diode.

VOLTAGE.----4..-o • µA~---. VOLTAGE

SUPPLY
SUPPLY

BASIC lcso lcno CIRCUIT WITH

CIRCUIT METER PROTECTION
Figure 15.13 Figure 15.14

226
 TRANSISTORMEASUREMENTS

When the drop through the limiting resistor exceeds the allowed value, the
current through the diode tries to reverse; thereupon, the diode becomes
back biased and the reference point is driven by a current source, where
Jlimit= Vprote.-tloll
Rrefer,mo
( h' h lS• cons1'der ed a fau }t con d"1tlon,
W IC
• but meter protection
•

is accomplished by this current limiting).

Since the current under fault conditions is greater than the desired limit
(and it is desired to keep the overload on the ammeter as small as possible) it is
desirable to make the protection voltage much larger than the clamp voltage;
preferably 10 times larger. The reverse current of the clamp diode at the clamp
voltage must be considered, for it adds to the meter overload, and must have
a breakdown voltage much greater than the clamp supply. When the currents
that are being measured are appreciable (in the order of milliamps) the addi-
tional currents flowing through the reference (clamp) supply must be considered.
Thus if 1 MA is the limiting current allowed, the clamp bleeder should carry
much greater currents ( > 10 MA) so that the clamp voltage does not change.
Where the test voltage is fairly low the drop through the ammeter or reading
resistor must be considered for this subtracts from the supply to the tested
device.
The go-no go test equipment of Figure 15.16 is designed to indicate only
that the device possesses specified, or better, characteristics. Generally this type
of equipment is designed individually for each requirement and has only
limited flexibility.
From the Figure 15.16 circuit go-no go BVcno tests can be made by using
a current source whose value is that at which BVcoo is defined. In this case the
Vcs voltmeter will indicate that the voltage is less than (Icuo is excessive), equal
to, or greater than the required test BVcuo voltage (lcso is less than the allowed
current limit). The current for the voltmeter must be considered, and its
accuracy at the limit point (VT) must be checked to put the reject-line on the
meter at the correct point. Once this has been done the readings are as
accurate as the initial calibration and the stability of the power supply. To
prevent overloading the voltmeter and to avoid the large open-circuit voltages
at the test point, the current source is often voltage-clamped where the desired
test voltage is less than that of the clamp. When this is done the circuit bears
a close resemblance to the lcuo test circuit of Figure 15.16.
CURRENT LIMITING RESISTOR
RREF
VOLTAGE LOW CURRENT
VPRO--;ECTION
SOURCE DIODE

VTEST-
OR
CLAMP
SUPPLY I
- CLAMP
VOLTAGE

R
COMPLETE lcso GO-NOGO lcuo
TEST CIRCUIT TEST CIRCUIT
Figure 15.15 Figure 15.16

227
TRANSISTOR MEASUREMENTS

LARGE-SIGNAL(DC) TRANSISTORCHARACTERISTICS
The large-signal transistor characteristics may be divided into two categories with
the line of demarcation being the difference between high-frequency pulse response
and the DC parameters useful in control-circuit and some computer applications. The
pulse response characteristics are discussed in a later section.
In the following curves Figures 15.17 and 15.18, the significant points of interest
are described on the transistor family of curves where le vs. VCE is plotted for various
Is values.
RANGE
EXPANDED
TO ILLUSTRATE
POINTS

SPEC. Ic
l VARIOUS
VALUES OF
Ia

VcE (SAT)
SPEC Ic

VcE

KNEES IN Ia FAMILY WILL APPROXIMATELY DESCRIBE A

FORWARD DIODE CURVE.

Ve&csAT> AND RcsAT>- FUNCTIONS OF IR AND le

Figure 15.17

IctMAXl
le (MAX) STEADY STATE IS AT
POINT OF INTERCEPT OF
VcE(SAnKNEES AND ALLOWED
DISSIPATION CURVE.

'- MAX POWER

"-....._ / DISSIPATION
.J( _
- CURVE

le cuAX> STEADYSTATE
Figure 15.18

228
 TRANSISTORMEASUREMENTS

LARGE SIGNAL DEFINITIONS AND BASIC TEST CIRCUITS

I. hvE is the static value of the forward transfer current gain in the common
emitter connguration and is measured as shown in Figure 15.19. It is the DC
collector current, le, divided by the DC base current, Is; hFE ={!.

Vee

hFE MEASUREMENT
Figure15.19

The collector voltage, VcE, and the collector current, le, must be specified. A
Go-No Go test for hFF:may be used, as shown in Figure 15.20.

,--
1
____ _____
_. I_c_-ir--...,- --- - - -7
I
I I
I I
I CONSTANT CONSTANT
CURRENT
I
CURRENT ~
I GENERATOR ~ GENERATOR I
I I
I I
I I
L-------.J L-------- _J
GO-NOGO hFE CIRCUIT
Figure15.20

In the method shown in Figure 15.20, Ia is adjusted to give the base current
required for an hn of the required value, le is adjusted to the specified value:
le
Is=-
hn
If VCE as read on the meter is less than that given in the test specifications,
then the hFE for the transistor is greater than that required. If VCEis greater
than the value specified, then h.,.Eis less than the required value.
2. VcE <BAT>is the voltage from collector to the emitter, VcE, for a given le and Is
while biased in the collector saturation region. The test is very similar to that
for hrE in Figure 15.20. le and Ia are adjusted to their specified values and VcE
as read on the meter connected from collector to emitter is VcE <sAT>·

229
TRANSISTORMEASUREMENTS

3. V BE is a measurement of the base to emitter voltage, V BE, when in the common

emitter configuration and biased according to instructions given in the test
specifications. A circuit similar to Figure 15.20 for hFE may be used with the
addition of a voltmeter (VTVM) between base and emitter.
4. hrn is the equivalent (slope intercept) resistance equal to This test i.:£.
is generally made at a specific Io which is sufficient to saturate the device
when it is driven by a specified le. This information finds maximum applica-
bility in switching and computer applications.
5. hrn is equivalent to hrn except with the transistor operated in a grounded-base
configuration. This resistance is an indication of the forward drop in the
emitter, and finds application in some power transistor considerations, in bias
requirements for some small-signal transistors, and in some regulated power
supply applications.
6. le uAx must be considered for two different applications,
a. Steady state-le max. is determined by the intercept of the curve of the
"Knees" of the collector saturation points with the maximum allowable
power dissipation curve.
b. The second consideration of le max. involves the duty-cycle of the on
times for switching applications and is dependent on the duty cycle of
the circuit being used.

II~POWER L,~
\ VARIOUS

\ \ ~ l:c MAX AT DIFFERENT DUTY CYCLES

\ \ I '
\\ '
' '- NOTE: DRIVING POWER IN THE
'- '' (C) MW BASE MAY NEED TO BE
, SUBTRACTED FROM MAXIMUM
/ , .__(B) MW ALLOWED POWER (DEPENDING
....._ ON PERCENTAGE OF TOTAL)
/ ......_
(A) MW IN ORDER TO PLOT POWER
/ \ .I MAX "STEADY STATE" CURVES AT LEFT.
/ C

le aux CHARACTERISTICS
Figure15.21

SOME TEST CIRCUITS

Methods of test and equipment for almost all parameters may be divided into
two basic categories: (a) quantitative and evaluative equipment for engineering,
and (b) Go-No Go equipment for use when the limits of allowed variance of a
particular parameter have been determined and specified. The equipment required
for the engineering measurements of DC parameters consist primarily of precise power
(current and voltage) supplies, and reliable and precise (as well as often very sensitive)
voltmeters and ammeters. The following section will be devoted to both quantitative
and Go-No Go equipments and circuits in use.

130
 TRANSISTORMEASUREMENTS

1. hFE measurement is accomplished in the circuit of Figure 15.22. The potenti-

ometers are adjusted in the base and collector circuits to establish the proper
measurement conditions; namely, since hFE is a function of both Ve& and le,
these two quantities must be specified. When the desired le and VcE conditions
are established the hFE can be determined. As has been stated hn = ~:; thus
two current reading resistors, R, and R2,are inserted into the base and collector
circuitry respectively. R, is made very much smaller than Rs, and R, is made
very much smaller than Re. Using a Helipot, Ra, whose resistance is much
larger than R2,the voltage drops across R1and ~ can be compared. When R1 is
equal to &, for example, and a null is established on the VTVM when the
.
Hehpot reads twenty thousandths ( 20 ) of full scale then the hFE
1000
=
1000
20
=
or 50. If R1 10 R:, a greater range of the Helipot can be used and, in the ex-
2
ample above, a null would be established at two hundred thousandths ( ~ )
10 0
1000 .
on the Helipot indicating hFE =
200
X 10 = 50. On the physical test
equipment the Helipot could be calibrated in hn for direct reading.

NOTE: IN ALL OF THE hFE AND VCEISATJ TEST CIRCUITS, IT MAY BE

NECESSARY TO "CLAMP" THE BASE AND COLLECTOR SUPPLIES
TO PREVENT DAMAGE TO EXTREMELY SENSITIVE AND LOW-
POWER UNITS.

l
VTVM
(NULL) IN hFE (HELIPOTI
,___---4 J' DETECTOR
R3>>R2
01FFERENTIAL R1 MAYBE SOME MULTIPLE
MILLIVOLTMETER LOW
CURRENT AND SENSITIVE OF R2 AND ACT AS
MULTl PLIER OF hFE
READ ON R3

QUANTITATIVE hFE MEASUREMENT

Figure15.22

2. hFt: Go-No Go equipment is normally built using a constant collector current

and classifying hn according to required base current as shown in Figure 15.23.
When the desired VcE and le measurement conditions are known, a circuit can
be built as shown to classify the devices. If Vc& reads below the specified
measurement condition, the hFt: is greater than that established by the fixed
resistors and supplies; if the VcE reads higher than that established as a
measurement condition, the hFE is lower than that established by the circuit.

231
TRANSISTOR MEASUREMENTS

:Cc=SPECIFIED
CONSTANT

CLASSIFIES hFE BY
VCE INDICATION

hv1: CLASSIFIER
Figure 15.23

3. The VcE <11AT> measurement, Figure 15.24, is often made by applying a speci-
fied le to the transistor and increasing Ia until an abrupt change in VcE indi-
cates that the collector voltage has dropped below the knee of the collector
curve; however, in specifications both le and In are specified. In is usually
sufficient to saturate the device; and, in Go-No Go testing, noting that VcE is
below some specified voltage, or that it is within certain specified limits is
normal procedure. The latter being of particular importance in computer
applications where maximum and minimum VcE <RAT> values are relied upon.
Two circuits in which measurements can be performed are shown in
Figure 15.24.
ONEORMORE
I.e's MAYBE
SPECIFIED

IN PLACE OF THE VTVM MILLIVOLTMETER SHOWN ABOVEA REFERENCE (NULL)

COMPARATOR MAYBE USED FOR GO-NO GO TESTS

IN91'S
FOR METER PROTECTION t
20µ.A
CENTER-ZERO
METER

Ve-.:<SAT> MEASUREMENT
Figure 15.24

232
 TRANSISTORMEASUREMENTS

JUNCTION TEMPERATUREMEASUREMENTS

JUNCTION TEMPERATURE (TJ)

The measurement of junction temperature, depends on one of two temperature-
sensitive mechanisms inherent in the junction device. These are the exponential rise
of the reverse diode saturation current, and forward diode voltage decrease with tem-
perature. In most instances experience has shown that calculated theoretical changes
of Ico and VF are too gross (due to rather large "second-order" effects) to be sufficiently
accurate indices of junction temperature; and the test device must, in fact, be calibrated.
This requires that the unit be temperature cycled in an oven (allowing sufficient time
for the device to stabilize at each temperature or using a large, high thermal-
conductivity heat sink) and a plot of the desired index vs. temperature be made. Power
is applied to the device in the forward direction, or through the application of bias
current. This power is then momentarily switched off and the built-in thermometer
checked by a suitably gated meter. The oUtime is either kept negligibly small when
possible, or else considered in determining the average input power.
Both the Ico and VF methods are alike in having a large possible error due to the
thermal response-time of the device. If the temperature at the junction declines
rapidly, the resultant apparent value of TJ will be lower and fall somewhere between
the true T, and that of the thermal mass.
The reverse-current method suffers the additional handicap of charge-storage in
the junction when the forward current is reversed. This charge must be swept out by
the reverse voltage before a true indication of Icno can be obtained, a race between
charge and thermal decays results. In the large area device of relatively small effective
lifetime, the error will probably not be large, but the current metering system must
be gated to prevent the charge-decay currents from registering. No peak-reading
detectors can be used; although if the charge decays rapidly enough compared to the
measuring time, and TJ is reasonably constant during this interval; an average reading
metering system is sufficiently accurate, if suitably calibrated.
In the case of the small-area, long lifetime device the problem is more difficult.
The masking effect here precludes reverse measurements and only forward measure-
ments are feasible; there are still storage problems, but switching presents the major
difficulty. Fast-acting mercury relays are generally used to prevent contact bounce
and carry the required currents without large contact drops.
There are decided advantages to using forward voltage drop as the T, index from
the point of view of the circuit requirements. Since the detector (meter) circuit is
driven by a voltage source the system is less liable to pick up extraneous hum that
can plague the reverse-current measurements. (Particularly when Icno is low, as in
silicon devices, where the current reading resistor is necessarily large.) Unfortunately,
however, the change of v •.is comparatively small and the "thermometer" is therefore
relatively insensitive. This may require differential amplifier techniques in the detector
circuit for precise measurements of T,.

THERMAL IMPEDANCE
Once a means of measuring T, has been developed, the measurement of thermal
impedance is readily accomplished. The simplest means of measuring the case tem-
perature - such as a thermocouple or large heat sink - may be used, and different
powers are fed into the transistor while measuring T,. By defining thermal resistance as
the input power required to raise TJ to some arbitrary temperature, (say 70°C) and

233
TRANSISTORMEASUREMENTS

measuring this power at different ambients, sink or case temperatures, we may write
the following definition:
if X watts= 70°C T1 from 25°C T.1nk
and y watts= 70°C T1 from 45°C T.1nk
Then,
45° - 25° 20 oc
Rt hum a I = x-ywa tt s -x-y per watt
we can draw a derating curve through these intercepts as shown in Figure 15.25

I?
01?
lox
11!'"
------- I
POWDI / T[lll'[UIVII[
~•-- : llERATING CU11V1:
~ y !
o:
- - - - - -:-
I
- - - - I
I
151.0Pf • Kl

l
_
I
I
I
I

POWERVS. TEMPERATUREDERATINGCURVE
Figure15.25

TEST CIRCUIT FOR JUNCTION TEMPERATUREMEASUREMENTS

1. Description of Operation:
Under certain conditions, the forward drop of a semiconductor junction
varies linearly with temperature. By setting up these conditions and using a
test circuit similar to that of Figure 15.26, it is possible to determine the
temperature of a transistor collector junction for various power dissipations in
the transistor.

----==-=----~,-,,....------<le,..a:1"'\
R4 I 2 \~../ 3
3
,R3 0 '14N.O. *E I
SCOPE
_
IN495 I
I
R6
IOK,l/2W
I II
.
IE SUPP2LY
~
1""
I I
7 !1
W.E.2758 [lrK_2
__________ R_2
___ KI.....,, W.E.2758

8 3K,5W,WW 8

CRI IS USED TO
R5 ,.__...,__, SUPPRESS OSCILLATIONS
IIOV 601'\J 15K,5W,WW.
CR2
IN93
R3
2K,5W,W.W.

NOTE: POLARITIES SHOWN FOR NPN. TO

USE FOR PNP, REVERSE POLARITY
OF POWER SUPPLIES AND DIODE
CR3.

THERMAL MEASUREMENTS TEST CIRCUIT

Figure 15.26

234
 TRANSISTORMEASUREMENTS

The circuit shown is one of several variations which can be used. Kl is a

mercury relay (W. E. 275 B type) which interrupts the circuit in which the
transistor is heated. K2 is another relay of the same type that puts the transistor
in a temperature measuring circuit when it is not in the heating circuit. The
relays operate at 60 cps. The transistor under test is heated for about 80% of
the time and its forward drop (temperature) measured during the other 20%.
If the scope were put directly on contact No. 3 of K2, the presentation would
be similar to that shown in Figure 15.27.

HEATING MEASURING HEATING

TIME I TIME I TIME

T_I I I I
t 1 - K2
12 -Kl
13 -KI
CLOSES
OPENS
CLOSES
t4-K2 OPENS

OSCILLOSCOPE
PATTERN
Figure15.27

In this presentation, V, is the forward drop of the collector junction while

it is in the measuring circuit, and Vcs is the collector to base voltage while in
the heating circuit. The scope vertical amplifier is normally set to the range
that will best show the variations in V,. Under this condition, Vcs is of such
magnitude that it would overdrive the scope and cause distortion of the V,
presentation. To prevent this situation, a clamp consisting of R4 and CR3, is
inserted between the scope and contact No. 3 of K2. This minimizes the
possibility of overdriving, but still allows the monitoring of V,. Since Vr varies
linearly with temperature, the changes in junction temperature can be deter-
mined by measuring the changes in V,.
Now, back to the conditions mentioned earlier. The first of these is that
the measuring current (I,) through the junction during the measurement must
be held constant. This requirement is met by using a power supply (PS) with
V = 100 volts and a high resistance (Rl).
Another condition is that I, be set to such a value that dV ,/dT will be a
constant over a wide range of temperature T. Based primarily on calibration
tests of several types of transistors, I, should be adjusted to give a V r = 500 mv
at 27°C for silicon junctions and a V, = 200 mv at 27°C for germanium junc-
tions. This is accomplished by adjusting the value of RI. Once the conditions
are met, the .final requirement is that the value of dV ,/ dT be known.

235
TRANSISTORMEASUREMENTS

dV ti dT for different transistors can be determined by placing the units in

an oven, adjusting It to the value specified in above paragraph and then
measuring Vt at different oven temperatures. Sufficient time must be allowed
for the junction temperature to reach that of the oven as mentioned earlier.
This would be the most accurate value of dV ti dT to use since it is deter-
mined for each transistor on an individual basis. A more convenient, but less
accurate method, would be to take the average value of several transistors of
the same type. Here the accuracy of the value of dVt!dT would be dependent
on the spread, but in general would be within the accuracy of the temperature
measuring circuit described.
2. Procedure for Determining Junction Temperature
a. Determine dV t I dT for the transistor collector junction.
b. With Ve = 0, and IE = 0 connect transistor to terminals CBE of test circuit.
Handle transistor in such a manner that its temperature is not raised above
ambient (use gloves, etc.). Adjust RS for time relationships shown in
Figure 15.27.
c. Adjust RI for a reading of Vt on the scope equal to 500 mv + (27° - T
amb.) X dVtldT.
d. Set Ve and Jg to desired bias conditions.
• (11Vt)
e. Note change Ill Vt. TJunc=Tomb+ dV,/dT
3. Procedure for Determining Thermal Resistance from Junction to Ambient
a. Determine junction temperature as above.
b. Measure power input to the transistor to give this temperature rise.
(Pia= VeEmax. X IE max. X duty cycle).
c. Thermal Resistance from junction to ambient (8JA)is then computed,
TJ - T ambient
8
JA = Pin
EXAMPLE:
A 2N657 transistor (a silicon NPN mesa with pellet mounted directly
on flat metal header) is calibrated in an oven with I, adjusted to give a
V, (Vea) of 500 mv at 27°C. The slope dV,/dT was found to be 2.50
mv/°C. It was desired to find what power was required to raise the junction
125°C above ambient and to determine the thermal resistance from junction
to ambient at 149°C; room temperature = 24°C.
1. The transistor was connected to the terminals provided on test set up.
Ve= 0 and le= 0.
2. RI was adjusted to give a V, of 500 + 3 ° (2.5 mv /° C) or 507 mv.
(This took a resistance of nearly 20 megohms.)
3. For the junction temperature to rise 125°C, the voltage V, in step 2
would have to drop by 313 mv (125 X 2.5). Vea supply was set at 25v.
11:was then increased slowly until V, dropped to (507 - 313) or 194 mv.
4. The voltage from C to E read with a Weston analyzer was found to be
20.0 volts. (This is an average voltage). The current in the emitter,
read with a Weston analyzer in the emitter current lead, was found
to be 33.3 ma. (Average value.)

236
 TRANSISTORMEASUREMENTS

Thus the power dissipated in the transistor was approximately equal to

20.0 X 33 834 p Iav X En
.8 or mw. in= duty cycle
. TJ-T ...
5. Smee 0 JA - p
In

then eJA _
149-24
834
= 0
.149 C/mw
4. Procedure for Determining Thermal Resistance from Junction to Sink
The thermal resistance from junction to sink is a useful parameter for com-
puting operating junction temperature of a sink mounted transistor from the
input power and sink temperature. Junction to sink thermal resistance can be
calculated using the same procedure as used for eJA with the exception that
sink temperature is now used instead of ambient temperature. The heat sink
will be more efficient if it is placed in contact with the surface on which the
pellet is mounted. For instance, units which have the pellet mounted on the
header (such as the 2N657) should have the heat sink placed in contact with
the header, giving an excellent thermal path. The contact between the sink
and the transistor header could be achieved by holding the unit tightly against
a 2" x 2" x % " piece of copper by a steel washer clamped down on the tran-
sistor flange. Holes are only large enough so that the insulated transistor
leads can pass through. Silicone grease is spread over all contact surfaces to
provide a better thermal path between the transistor header and the copper.
The sink temperature can now be measured by placing the thermocouple
between the bottom of the copper £in and the nut as indicated in Figure 15.28

TRANSISTOR

THERMOCOUPLE

THERMOCOUPLE
PLACEMENT
Figure 15.28

Once case temperature is established, e.is can readily be obtained by using

the same procedure as used to £ind 0 JA,

237
 TRANSISTORMEASUREMENTS

SMALL SIGNAL MEASUREMENTS(AUDIO) OF TRANSISTOR

PARAMETERS
The two most familiar matrices (the Z and Y) proved to be difficult to apply to
transistors in practice, for driving the collector of a transistor with a current, in
measuring ~s, required large source impedances; and driving the input to the
transistor with a voltage source, as in measuring Yno, could produce large errors due
to the current sensitivity of the device. (Base currents when multiplied by h,.. could
cause current clipping in the collector.)
To overcome these disadvantages the h or hybrid matrix was proposed and became
commonly used. The device characteristics that make the h matrix most useful at audio
and low R.F. frequencies change appreciably as the frequency is increased. Above
· 30 MCS the terminal requirements become increasingly difficult to obtain; measure-
ments at these higher frequencies will be discussed in next section, (High Frequency
Small Signal Measurements of Transistor Parameters).
Consider the terminal requirements of the h matrix, and how they may be
obtained in practice. The matrix is described as follows:
=
hu =
e,/it when e2 0 (Input impedance, short circuit output)
h,2 = ei/ei when it= 0 (Reverse voltage ratio, open circuit input)
= =
hn i:,/it when e2 0 (Forward current gain, short circuit output)
hn = i1/e, when ii= 0 (Output admittance, open circuit input)
These matrix quantities are defined for either common base, common emitter or
common collector configuration. Originally 270 cps was the audio frequency used in
parameter determination, but today 1 Kc is used more frequently although both are
still common.
In establishing the correct a.c. conditions several considerations are of importance.
In establishing these conditions, the desired percentage of accuracy will be used as
the factor which will determine how well the ideal measurement conditions are
realized. 1/(Desired Percentage of Accuracy) will be called (DPA)-1 ; thus, if the
desired accuracy is 5% then .~S = 20 or (DPA)- = 20. The following notes on each
1

measurement show where errors may be introduced and indicate what conditions must
be established for measurements to be of desired accuracy.
COMMON BASE CONFIGURATION

8 9 +&noise
VTVM
t----ozv
o

Vee

t
CURRENT
SOURCE
l h1b MEASUREMENT
Figure 15.29

238
 TRANSISTOR MEASUREMENTS

For desired accuracy,

Zv Zr:Z,.' ~ (DPA)-1h
~ Zc + Z.,Zr:'+ z, Zr/7' lb <MAX>
"'c ~ (DP A)- hob IIAX (for all tests)
1

enol• e < <es h1b MIN

hrb = e,~
z, SHIELD
rJWv,,
____ fr',...''.____,
.._'+.. __ __, l Zo

C ,,.(
l_z. l
.........
* l\~:·:::r~R
r ,I T
rl

-½ ~ Rz I
lE L _j
CURRENT
SOURCE
v••

hrb MEASUREMENT
*
Figure15.30

z. = effective leakage impedance

For desired accuracy,
e 1 <<V.-b
le Rs <<V.-b
z.> > z~~zt, ~ (DPA)-1 h,b uAx
eDohe < <10-•
ell

,L~ (DPA)- hob 1

MAX

3. htb (h:nb) htb =~11

JUMPER FOR
CALIBRATION
OF hp, • 1.0
,----7
I / I

SIGNAL -Ar VTVM Ozt"Dnoln

GENERATOR

1 f
IE
CURRENT
SOURCE

hrb MEASUREMENT
Figure15.31

239
TRANSISTOR MEASUREMENTS

. V-i
12=RL
For the desired accuracy use the same considerations as for h1b and,
wC>>Rl >> I,
hob MAX
(RL is normally less than or equal to 1000 average)
zgZ,' ~ (DPA)- 1 R
zg+ z.,:'- L

i, <<Ic
4• h ob(h22b
) h ob =-egi" ;. Ir ~
e.. smce
-R
L
. . . 11
le IS sma .

SHIELD

6
---------, 89

~+-J- VTVM

hob MEASUREMENT
Figure15.32

For the desired accuracy use the same considerations as for hrb and,
e, hob llJN RL > >enohe
z.>> -h 1 ~ (DPA)- 1 RL
ob MIN

Ueno + (1 + hFn) le] RL < <V cc

QwL ~ (DPA)- 1 RL at measuring frequency
To satisfy some of the above RL requirements and yet have Zt large enough
to have sufficient sensitivity; a parallel resonant circuit of low series R is
bridged across Rt to reduce the D.C. drop.
COMMONEMITTER CONFIGURATION
When considering practical measurements of grounded emitter parameters it is
also necessary to consider the D.C. bias requirements. It immediately becomes
apparent that each transistor will require base bias adjustments to obtain specified
base conditions. Since it would be preferable to avoid this time consuming operation
and particularly so when many units must be measured, a Quasi grounded emitter
circuit is used. Through the use of high Q, parallel resonant circuits, the device sees
a grounded base bias supply and an A.C. grounded-emitter configuration. Of course
this technique is applicable to fixed-frequency measurements only. It is also necessary
to consider the current multiplication of input measuring currents appearing in the
collector circuit. To maintain small signal requirements steps are taken to insure that
these collector signal currents will be much less than the D.C. bias currents. (See
Introduction, to this chapter.)
1. hie (h1le)

240
 TRANSISTOR MEASUREMENTS

h,e MEASUREMENT
Figure 15.33

Coils used are high Q toroids in which D.C. saturation must be considered
when certain bias conditions are used.
For the desired accuracy,
iir<<-hro1-"- MAX

IaR1 <<V.,"
Z.,ZpZ, > (DPA)-i h 1
Zvz, + Zvz, + zpz, = " MAX

l <<re at specified IE
"'
C1
where re~ klT ~ 26 n at IE= 1 ma (see Introduction this chapter)
Q E

wC1>>
hoe
enol •e <<h,. MIN ia
The press-to-read switch is incorporated to prevent charging C1 to VE
when no transistor is in the socket. Otherwise, the discharge of the capacitor
may destroy a unit as it is inserted into the socket for test.
2.

z,

9
I

-=-
PUSH TO
READ

Vee

-!-
hre MEASUREMENT
Figure 15.34

241
TRANSISTOR MEASUREMENTS

C1, Ct, and R1are the same as for h,o

For desired accuracy,
le~ <<Vee
ec <<Ve.,

z.>> z1:+~ (DPA)- h,.

7z., 1
uu

e11olH < <hro MIN ec

,L~ (DPA)- hoe 1

MAX

3. h (h )
fe :t•
h
re = ici:z; • =Rte2
b

JUMPERTO CALIBRATE ri,.•I

~02+0 .....

RL Zv ~-VTVM

~~

h,., MEASUREMENT
Figure15.35

For the desired accuracy, use the same considerations as for h,. and,
C1101u <<ic Rt
1
Rt<<-h--, oe MAX
RL is generally about 50 0

4. h°" (h22• ) hoo =-eair ;. 11 ~

Co
-R
L

_,9
r-
1
I L
I
Zp •OwL
I
I
: R1
IL __

hoe MEASUREMENT
Figure15.36

242
 TRANSISTOR MEASUREMENTS

Ze, R1,R2,Ci, and Cs same as for hr.,

For the desired accuracy,
ZP> > hr., MAX (R., + R1.)
enolH <<ho.MIS RLe,
Cc <<.V.,.,

COMMON COLLECTORCONFIGURATION
Common Collector Parameters may be calculated from measurements of common
base and common emitter. Notice that the two parameters not identical to those in
common emitter configuration are in one case almost equal to h,. and in the other
almost equal to 1.
1. h,.,=h,.
2. h,., (hurr}

- PRESS-TO-READ

h.. MEASUREMENT
Figure15.37

Driving conditions are the same as for h ••; however, ee < <V Ee, also
h •• ~ 1.0 and deviations from unity are difficult to measure.
i2 • e,
3. h ,.,=-:-;12=R-
1, L

Vee

SIGNAL
GENERATOR -i
VTVM
~+Ono111

Zp•QwL

hr.. MEASUREMENT
Figure15.38

243
TRANSISTOR MEASUREMENTS

zpDriving
~
considerations are the same as for hr. if RL
(DPA)- (R. + RL)
hrc hro
1

~
is kept small; otherwise,

1
hrc =1+ htb

4. hoc= hoo
GENERAL
Some of the parameters mentioned are particularly difficult to measure, the
terminal requirements difficult to obtain, or particularly sensitive to temperature.
When measuring hrb it is found that as this parameter approaches unity, the difference
is increasingly hard to detect. Instead, hre could be measured and hrb calculated; or an
attempt to measure 1 + hrb could be made instead. A circuit for measuring 1 + hrb
is shown in Figure 15.39.
i1 • e2
1 + h fb =--:-, 11 =RL
lr
CALIBRATE lthJb = 1.0
WITH JUMPER

Vee

SIGNAL r-, ~
GENERATOR::r

r ! e 2 +enolu
VTVM

+ hrb MEASUREMENT
l
Figure15.39

Considerations for obtaining accuracy are,

z:+zt~ (DPA)- (hsb + RL) 1

zp (DPA)- RL
~ 1

enoho << (1 + htb MAX) RLir

wC,,>> hoeIIAX
However, since RL appears in the collector loop, the collector is not really short
circuited, and RL must therefore be kept quite small. On the other hand, it must be
insured that i, < <IE (in the order of 0.1 ma RMS for 1.0 ma IE), Now the maximum
current that will flow through RL will be i1 when hrb = 0, therefore in practice
i, RL= 10-• X 10s or about 10 MV at most. Since, too, it is preferable to measure up
to hrb = =
.999, the ability to measure 1 + hrb max. X iir RL about 10 microvolts is
necessary. Some available VTVM's do not have sufficient sensitivity for this measure-
ment and either selective VTVM's or pre-amplifiers must be used; at this point, noise
and "pick-up" become important considerations.
Similar important considerations also arise in measuring h, •. In order to maintain
the collector signal current within the required small signal level, one must start with
10""'amps and a reading resistor of 500 max, assuming 1.0 ma D.C. collector current.
This output signal of 5 mv is the maximum signal level in the collector. To measure h,.

244
 TRANSISTORMEASUREMENTS

up to 1000, one would have to insert a base signal current of 10-7 amps; and calibrating
by inserting this signal into the 500 resistor, it develops that only 5µ.v of signal are
available and the permissible noise background is less than 0.5 µ.v.
To illustrate a method whereby most of these difficulties may be eliminated by a
different technique of measuring, the circuit of Figure 15.40 is considered.

DECADE OF IKO EACH STEP

0.1 % DEPOSITED
CARBONRESISTORS

STEP

TENTHS

DECADEOF IOOSl EACH STEP

hie =NUMBER OF UNITS

INDICATEDBY DECADE
BOXES+ I UNIT

NOTE: BY INSERTINGA 20db

ATTENUATORBETWEEN
THE SIGNAL GENERATOR
AND THE DECADES,THE
READINGSOF hte ARE
MULTIPLIED BY 10.
1VTVM

ALTERNATEhro MEASUREMENT
Figure15.40

In this instance a constant signal voltage (say lOV) and a Unit of resistance are
used that will limit the signal current to that permissible in the collector circuit. At
500 and 0.1 ma a reference signal of 5 MV exists, which is readily measurable. The
Unit of resistance is 100 K. Now units of resistance are inserted in the base circuit (AC)
until the collector current returns to the Reference level. The number and fractions
thereof of Units of resistance will read h,. directly; and the result is that a calibrated
decade resistance box is used to read hro. At 1 KC accuracy is not limited by the
resistors, but rather by the ½ to 1 % resetability of the VTVM pointer. By using a
selective VTVM with an expanded scale, such as the Hewlett-Packard 415B,
(V.S.W.R. indicator) resetability and accuracy can be improved to better than 0.2%.
The limitation now is the accuracy with which the temperature of the unit under test
can be maintained since h,o is temperature sensitive.

245
TRANSISTOR MEASUREMENTS

HIGH FREQUENCYSMALL SIGNAL MEASUREMENTSOF

TRANSISTOR PARAMETERS
GENERAL
The subject of high frequency h parameter measurements is considered in this
section. Measurements from 100 kc to above 300 Mc are considered.
1. Common Base - Common Emitter:
Several considerations must enter into making a small signal measurement
other than the high frequency techniques. Of importance is the time required
and, in common emitter measurements, the effect of the DC shunt paths. For
both of these reasons, all of the common emitter measurements are made in the
Pseudo grounded emitter configuration where, to D.C., the circuit appears
common-base. This was described in the last section. All of the considerations
described there are equally applicable at high frequencies.
2. Broad-Band Measurements:
Common base broad-band measurements are feasible up to 100 mes with
care in circuit layout and due attention to socket capacity, etc. Common
emitter measurements are broad-band in a very limited sense. By picking a
sufficient number of spot frequencies data are obtained to draw a curve of
parameter vs. frequency. The spot-frequency approach results directly from
the circuits which will be described.

INPUT IMPEDANCE:(h,b, h,.)

I. 200 kc to 5 mes:
For this measurement the British Wayne-Kerr Model B601 Bridge was
found to be the most suitable. By using suitable multiplier taps it will measure
from a few ohms to more than one megohm of R parallel and reactances of
± several hundred µµ.f with reasonable accuracy. However, some reactance
errors arise in measuring low parallel R values, due to inductance inside the
bridge.
A receiver is used as the bridge detector. A unit with a few µv sensitivity
and a frequency range of 200 kc to 5 mes. This detector sensitivity is manda-
tory, since the maximum signal voltage the bridge applies to the input of the
transistor must be less than 5 mv, if overdriving the unit and distortion are to
be avoided. Since small-signal conditions are to be maintained, the AC cur-
rents permissible should be at most 10% of the DC bias currents. Assuming
1.0 ma Ii:: and 50 ohms of h,b then the maximum input signal voltage is
10_. X 50 = 5 mv. Now for common-emitter operation, (assuming 1 + hrb
of .01), the base current is 10-11amps. For 500 ohm of h,o the maximum signal
=
swing is 10-11X 5 X 1()2 5 mv. These figures are arbitrary, but realizable, and
show the need for care. A suitable substitute is to incorporate means of reading
the AC current in the collector; and, abiding by the 10% rule, the input signal
is adjusted to the maximum permissible. The signal generator used is a Tektronix
190 with the attenuator fixed to limit the input signal to the bridge. Since the
Tektronix 190 starts at 375 kc this is the lowest frequency measured. Another
generator, such as the Hewlett-Packard 650-A will extend the low frequency
range. Test circuits are in plug-in boxes, for connecting to the bridge and are
shown in Figure 15.41(A).

246
 TRANSISTORMEASUREMENTS

2. 1 to 100 mes:
At higher frequency the small signal terminal requirements of h param-
eters (viz. Open and Short circuits) are progressively more difficult to obtain.
In general, the input impedances are lower due to decreasing current gain
and shunt reactance effects. The requirements of low driving signal voltage
and the detector sensitivity demanded are even more stringent.
The Wayne-Kerr Model 701B Admittance Meter is used with a Halli-
crafter SX-62A receiver as the null detector. Mathematical conversion from
the parallel admittances to the required series R. ± jX. will be necessary. The
generator used here is a Measurements Corp. Model 80 with a 2 me to 420 me
frequency range. Since the Wayne-Kerr Model 701-B bridge has a 3: 1 step-
down fransformer built in, the signal input to the bridge is limited to 10 mv
maximum. The circuits used in measurements are shown in Figure 15.41(B).

SIGNAi. G(N R[C[IYU

T[llTAo•ux
190 IOU[CTOltl

~TUT COICIC[CTOllt

(A) UP TO 5 MC/S

""'t.~:iaT[JI
l)(T(Cl'OOI ___F°'~IIMT
~-:,_.
1111
TUIIIIC&I.
O.Dl! '=
4.111 - ~

11.1•
111>1

••YJC--•ut• ()ltECTOII

···~[
IICLGUt. 1101 Q.R. CQ SOIIC
TIKTAOlfll AOIUTTIJI« UNIT'Lr-.
e1,o •llc&-A

( B) UP TO 100 MC/S

h1b AND h1. MEASUREMENT

Figure 15.41

247
TRANSISTORMEASUREMENTS

3. 30 Mes and Higher:

Two different Rohde and Schwartz Diagraphs are being used above 30 Mc.
One, Model ZDV, BN3561 operates from 30 to 300 Mc; another, Model ZDD,
BN3562 operates from 300 to 2400 Mc. These diagraphs measure the imped-
ance or admittance of an unknown by measuring the reflection coefficient
between a reference and an unknown transmission line. All shorts and opens
at advanced frequencies can be established by using transmission lines of the
appropriate length; that is, an open quarter-wave line is an a.c. short and an
open half-wave line is an a.c. open. The system used is basically a 50 n
system and measurement of h1b or h,e may be read directly from the Smith
chart display of the diagraph.

OUTPUT ADMITTANCE(hob, ho.)

1. 200 kc to 5 mes:
The same equipment is used here as for the h,b measurements. However,
as much as 1.0 volts rms (although less is preferable) can be applied at the
collector. The slope of the characteristic is reasonably constant over a large
range of Vr.,,
A conversion from RP ± jXP to G ± jB is necessary. Circuits are in plug-in
boxes.

l90 RECEIVER ORCUITSARE IN

SIG
GEN (DETECTOR) PLUG-IN BOXES

~
~

350KC-IMC

hob AND ho. MEASUREMENTUP TO 5 MC

Figure15.42

2. 500 kc to 200 mes:

The Boonton Radio Corp. Model 250 RX meter is used to make these
measurements. The bridge measures RP ± CP and has a built-in signal gen-
erator and heterodyne detector. The "RX" meter measures RP from 15!? to
over 100 kO and -80 pf to +20 pf (with means of extending this range by
adding external reactance).
Since D.C. currents of up to 50 ma may flow through the bridge, the

248
 TRANSISTOR MEASUREMENTS

shunt-feed problems are alleviated somewhat, and the entire bias supply is
"Boated" with respect to the bridge as follows:
THE ho1,/ Yob SWITCH IS A SELECTED
LOWLOSS,LOWC ,LOWL TOGGLE TYPE
HI LO

1 1
RX METER

_________,.
1--::i... Vee
+
0.05,a. fd 0.05,a.fd ~
+

hob AND hoe MEASUREMENTUP TO 200 MCS

Figure15.43

The built-in positive feed-back in the common base configuration, due to

"overlap" capacity, etc., will often make the resistance term appear negative.
The bridge, of course, is not designed to measure -R. Yet by balancing the
bridge at R = 10k, for example, and rebalancing with the unit inserted one
can calculate the effective -R term. The built-in capacity is sufficient to
warrant great care to prevent any more from being added by the external
circuit, and a shield between emitter and collector should be included in the
physical circuit. A comparison of the measuring circuit of Figure 15.44, and
that of an oscillator clarifies.the above requirement for minimum capacitance.
Also note that hob may not be measurable at some frequencies, and an a.c.
by-pass may be switched in, in order to measure the parallel equivalent of
Yob,which is also useful in determining hrb at high frequencies.

hob TEST CIRCUIT OSCILLATOR CIRCUIT

Vee

+
COMPARISONOF hob TEST CIRCUIT WITH THAT OF AN OSCILLATOR
Figure15.44
3. 30 Mes and Up:
The Rohde and Schwartz Oiagraph is also used on output measurements
at higher frequencies. However, since the diagraph is a 50 n system, the reso-
lution above 2.5 kn is difficult; thus, on some devices the real part of hob
and hH may be difficult to determine except to say that it is less than ~ 0
25 0
or .4 millimhos.

249
TRANSISTOR MEASUREMENTS

FORWARD
CURRENTRATIO(hfb, hre ANDfhfb)
Maintaining a high impedance, broad band current source in the presence of
capacity is difficult. The problem arises in determining what signal current is being
injected into the transistor, i.e., in calibrating the unity input current. It is convenient
to assume that when the current is jumpered into the collector reading resistor to
calibrate the set, this current will then How into the transistor too. However, even
5 p.p.fof capacity of the emitter socket has a capacitive reactance of only 1.5 k ohms
=
at 20 mes, which is not a good current source if RL 25 ohms and h1b 2000. This =
can cause a 10% current change, and much larger errors in frequency when meas-
40
uring fbtb, (the slope of hrb with frequency is relatively small) since a. -
l+j_!_.
f11tb
Another factor rises which must be considered. The input impedance of the tran-
sistor looks inductive below fbtb, and at some point becomes resonant with the
terminal capacity. If the real part of h1b is larger than the reactive part, then the
Q of the circuit exceeds unity and more current Hows in the emitter. At this juncture,
the current gain appears to exceed unity. It is the nature of hrb to return to unity at
high enough frequency, as an examination of the equivalent circuit will show. Of
course, hrb could be measured at many frequencies while resonating out the terminal
capacity for each step. This is done for h,. and f11th,but is time-consuming. Time
consuming, too, is the recalibration operation in fbtb measurements, but this time has
been reduced as much as possible in the circuit shown in Figure 15.46. The switch-
ing is made automatic, and the gain is changed to correct for the difference between
hrb-o (low frequency) and unity. This too is automatically switched between calibrate
and measure positions. With a flat 3 db pad (General Radio type), the detector
becomes a reference indicator. Now the frequency is found where both readings
are equal.
The phase of h,b at any frequency may be found by using a parallel (and as
nearly identical as possible- but without the transistor) channel as a reference. The
two channels are amplitude and phase balanced without the transistor. The transistor
is then inserted, amplitudes rebalanced, and the peak vector voltage between the

190
SIGNAL
GENERATOR
REFERENCE
METER

PENTODE
AC
CURRENT
SOURCE WIDEBAND
'~-----'-' AMPLIFIERS

2000

h,. AND fao MEASUREMENT UP TO 10 MCS

Figure15.45

250
 TRANSISTORMEASUREMENTS

channels measured. An Advance Electronics Corporation "Vectrolizer" is used. This

consists of a peak reading diode differential detector and D.C. amplifier/voltmeter.
The usual considerations of signal currents in the collector still apply. Lead-length
is critical in this equipment and disc type by-pass capacitors are preferable.
1. hre and fae to 10 mes is measured in the arrangement shown in Figure 15.45.
2. hrb, fhrband phase of ct to 100 mes is measured as shown in Figure 15.46.
Two basic methods of calibrating unity current are shown in Figure 15.47.
CHANNEL I

"DISTRIBUTED"
WIDE-BAND
AMPLIFIERS
50.0.
(D
SIGNAL
GENERATOR
MODEL 80

fs~ ~
~R

fc
l
VE Ve
NULL

SIGNAL
SPLITTER

CURRENT
SOURCE PHASE
50.0. t
,------41~-- .. COAX.
,~-----7•--_
ATTENUATOR
''-'-----~· AMPLIFIER
DIODE
TRAIN
5o AS ABOVE VOLTMETER
50

CHANNEL2
NOTE:CALIBRATE OUTPUT NULL WITH COAXIAL RELAYS IN POSITION (D ,MEASURE IN POSITION @

hrb, fhrb, AND PHASE OF ct MEASUREMENTUP TO 100 MCS

Figure 15.46

i---+ 0--------00

METHODS OF CALIBRATING UNITY CURRENT

Figure 15.47

251
TRANSISTORMEASUREMENTS

Signal generators used are either the Tektronix Model 190, up to 50 mes,
or the Measurement Corporation Model 80 up to 100 mes, and beyond. The
distributed amplifiers used are the Hewlett-Packard Model 460A or the
Spencer-Kennedy Model 201, the latter having a 200 mes cut-off frequency.
Detectors are the Hewlett-Packard Model 401-B or the Boonton Electronics
Company Model 91-B. The "Vectrolizer" has already been described.
Finite termination trans£er constants can be measured on the diagraph
which when coupled with a knowledge of the other h parameters measured
will yield the hrh, hrb, hre or hre, The computation involved is somewhat long
and tedious and with any large number of measurements would almost require
a computer. In the measurement of h,. at high frequencies another test facility
has been developed which will perform this measurement at certain fixed
frequencies. 20, 40, 100, and 200 mes are currently used. This measurement
is essentially used to determine the ft of a device where f, is equal to h,. times
the frequency of measurement if the h,. vs. frequency characteristic is de-
creasing at 6 db/ octave at the frequency of measurement. f, is defined as the
frequency at which h,. = 1.
a. ft Measurement
In a high frequency mesa transistor, the ft point or the frequency where
h,. = 1, usually occurs at a frequency in the order of several hundred
megacycles which makes measurement of this quantity quite difficult. This
is in addition to the. device parasitics interfering with the measurement.
To avoid such difficulties, hr.,· (the short circuit current gain of a transistor),
is measured at a fixed frequency somewhat below the hr. = 1 value. The ft
point can then be very closely approximated by applying the relationship
of ft = (h,.) (fmmur.d) as mentioned. In the particular test set described
provisions were made to check hre at two fixed frequencies an octave apart.
This, in effect, tells:
1. If the particular transistor under test has any useful gain at these
frequencies.
2. If the transistor is following the theoretical 6 db/octave slope.
3. If the second condition holds, what the value of ft is.
For example, two sets of similar design will be described for two dif-
ferent types of mesa transistors. The fixed frequencies of one are 100 and
200 mes, and the other, 20 and 40 mes.
Problems which must be avoided in the measurement off, are:
1. The signal level applied to the base must not be too high for a small
signal measurement.
2. The signal fed into the base must be a suitable current source.
3. The output reading load must be well defined.
To illustrate where these problems arise, consider the errors in calibration
in the input circuit of Figure 15.48, and in the output circuit of Figure 15.49
when the transistor is inserted. Combining these two terms results in Figure 15.50
where the total relationship of measured hr. as compared to actual hr. is shown.
The object of this measurement is to get the measured value of hre to equal
or to approximately equal the actual hr. :value. Therefore, both the input and
output error terms must be minimized; i.e., the variation of the input loop
impedance when changing from the calibrating load to the input impedance

252
 TRANSISTOR MEASUREMENTS

--=
ib lz11 + zLI 1,+ !~I
ical
iz,+ ··1. 1,+ ;;: I
BASE
ERROR C' ~~ I )
+
TERMS
Figure15.48
ib = ical

11+ ~1
Z11
IF h ..,....!£..
( I !~I)
fo jb

I+
ic =(ib) (h,,)= (ical)
II+- Ihie
211
h,,

I I = ic
(YL;
h,.)
i1
t
i1 = ic
(1,+I ~71)
-

( II+{;-I) I h ) h (ACT.)

COLLECTOR
I ~i:
I+ I (
I,+;z\ 10

ERROR h
i,
(MEAS.) • -. -
1o
TERMS 1cal

Figure15.49 hfe (MEAS.) SHOULD= h 10 (ACT.)

I ~~ I ) (
I+ )
I + z•:I I + ~: I
i1
~=h, (MEAS.)= ( h I hfe (ACT.)
, cal o I I

253
TRANSISTOR MEASUREMENTS

hfe (MEAS.)=

ERROR TERMS IN h,. MEASUREMENT

Figure15.50

of the transistor under test must be minimized and the magnitude of the output
admittance, hH, as compared to the load must be minimized. In other words,
h,. d hoe b <
Z« an YL must e 1.
The signal current generator uses a 10 K ohm series resistor to the base of
the transistor and is placed through a double sided copper clad shield which
tends to reduce the shunt capacitance across the resistor since at high fre-
quencies shunt or stray capacities lower the impedance of a current source. To
compensate for the residual capacitance in the test set described and therefore
raise the current source's effective impedance at the base of the transistor
socket, a high Q parallel resonant circuit is placed to ground. (One of the
methods which can be used to tune the resonant circuit is to install it physically
in the test circuit and then connect an RX Bridge as closely as possible to the
base terminal of the transistor socket. Set the CP dial on the RX meter to O pf.
Tune the capacitor in the test set and the RP dial on the RX meter until the
meter on the RX bridge nulls. Then read the RP dial. This is the effective
impedance which normally is from 4 to 8 K ohms depending upon the fre-
quency of the test set.)
Some mesa transistors tend to exhibit an output impedance, 1/hoe, in the
order of from 50 to 100 ohms at high frequency. Therefore, in order to measure
this type of transistor with accuracy the magnitude of the load admittance
terms, YL, must be greater than 100 millimho (or RL < 100). In order to
realize this condition, transmission line techniques are applied. Not only does
the transmission line transform the 3 KO resistance of the R.F. millivoltmeter
used as a detector to approximately 1 ohm, but the standing wave voltage
transformation permits operation at lower signal levels. Effectively a quarter
wave transmission line is placed from the collector of the transistor socket to
the R.F. millivoltmeter. In practice, it is found much easier to cut a piece of
cable shorter than the actual quarter wave length and use a variable ceramic
capacitor at the R.F. voltmeter end of the cable to ground. When adjusted,
this capacitor electrically extends the line to exactly a quarter wave length.
With mesa transistors in a psuedo-grounded emitter configuration which
is used in this circuit, a mesa transistor may break into oscillation. Therefore,
a series RC circuit, using a 10 ohm resistor, is placed from collector to ground.
This effectively lowers the collector impedance at frequencies other than the
frequency of interest and discourages unwanted oscillations.
Figure 15.51 is the diagram of the test set. High frequency construction
techniques are used. Shielding is of utmost importance, and the input circuit
must be isolated from the output circuit to avoid leakage of signal which
could cause a calibration error. (In this case, the base from the collector.) In

154
 TRANSISTOR MEASUREMENTS

p
BNC

~
BNC

?
- R1

VEE

20MC 40MC 100 MC 200MC

C1 3-12pf 3-12pf l.5-7pf l.5-7pf

C2 0.lp.f 0.lp.f 0.0lp.f 0.0lp.f

C3 0.lp.f 0.1,...f 0.0lp.f 0.01,...t

C4 3-12pf 3-12pf I .5-7pf I .5-7pf

L1 IOp.h 2.2ph 0.68ph 0.15p.h

L2 82p.h 47p.h 4.7p. h 4.7p.h

R1 2-soon 2-soon 2.2K 2.2 K

IN SERIES IN SERIES
1
*CRI SHOWN FOR PNP OPERATION OF CIRCUIT (3-IN540 S IN SERIES)

DIAGRAM OF hre TEST SET

Figure15.51

constmcting this test circuit, double sided copper-clad board is used. Com-
ponents are physically placed such that lead length is kept to a minimum.
To eliminate lead inductance of the transistor under test, a socket is used
which allows close connection of the circuit to the transistor header. A rectifier,
CR-1, is connected from emitter to ground to insure that C-2 does not
charge-up when the test socket is empty. This prevents destroying the next
transistor to be tested. In Figure 15.51 the circuit is connected for PNP opera-
tion of the test set. A switchable attenuator box is used instead of the range
switch of the R.F. millivoltmeter. The R.F. millivoltmeter used in this test
set has about a 1 db non-linearity from scale to scale and within a scale. To
avoid this error and still use the instrument, an alternate method is required
using a single point on the voltmeter (say full scale on the 3 mv scale) and
working around that level with a switchable attenuator.

255
TRANSISTOR MEASUREMENTS

I
6db I I0db 1 20db
\-----\ I \------\ I \-----\
(Y.o¼o ~ ~ ~
I a---,,,v"'~ I
31.2 I I
1so 150 I I s1.2
I I

ATTENUATOR
BOX
Figure 15.52

Figure 15.52 shows the attenuator box. Three switchable pads are incor-
porated enabling any combination of the three pads to be used. This in effect
keeps the R.F. millivoltmeter on the same scale (3 mv scale) and within that
scale, the pointer is always no less than % of full scale. The design formulas
for these pads were taken from Reference Data for Radio Engineers using
unbalanced 7f' networks keeping the input and output impedances equal to
50 ohms.

POWER GAIN MEASUREMENT

GENERAL
In a practical and useful amplifying device there is one question of paramount
importance, how much will it amplify at the frequency (or band of frequencies) of
interest? In short, what is the power gain? Obviously where the amplifier has insuffi-
cient gain to fulfill the minimum requirements, the device is of only passing interest.
Other important considerations may include Hat frequency response, amplifier stability
with temperature variation and other environm·ental changes, effective operating life
of the device and total power consumption. Power gain, however, is still of primary
interest and will be discussed in this section.
From the standpoint of the circuit designer the power amplifier should, among
other things, be a unilateral device with no internal feedback of any sort, and have
equal input and output driving point impedances. It should contribute no noise of its
own to the signal being amplified, have a perfectly flat gain/frequency response, and
a large gain-bandwidth product. Transistors, however, are not unilateral devi_pes.
Depending upon the circuit configuration being used (common base or common
emitter) and the particular frequency, the internal feedback may be either negative
or positive, and may even shift phase from one to the other. This effect is not unique
to transistors, of course, but these internal aspects do necessitate some thought in
defining Power Gain. Consider the case of an amplifier with positive feedback. When
the feedback power is great enough to overcome the associated circuit losses, the
device will oscillate. Describing the power gain of an oscillator is, of course, mean-
ingless. With no signal applied and any signal at all out of the device, its apparent
gain, according to the usual definitions, is infinite! This suggests the need for addi-
tional constraints in the definition of gain. Gain may be described under neutralized
or unilateralized conditions, with attendant problems of defining measurement of the

256
 TRANSISTOR MEASUREMENTS

degree of unilaterality. Gain may also be defined with certain boundary conditions,
or stability criteria, for example, when gain is measured with only that feedback
required to make the output driving-point impedance appear infinite. This will be
discussed later.
Problems of gain measurement break down into three specific phases:
a. Means of measuring input and output powers of the transistor.
b. Determining the effects of the circuit on the device.
c. Determining the effects of the device upon the circuit.
To be still more specific: in (a.) the generator and load impedances are adjusted
to match (either resistively or complex conjugate) the transistor for maximum power
gain. It must also be insured that the device is not over-driven either current or
voltage-wise. In other words, assurance must be maintained that small signal condi-
tions apply. Due to the extreme signal sensitivity of the usual low-power transistor,
the measuring of A.C. powers in the order of 1 to 10 microwatts (A.C. currents in the
order of microarnperes and A.C. voltages of a few millivolts) is of concern. As a result
the measurement problem is more complex than may be immediately apparent.
In (b.) spurious paths or parasitic strays can introduce unwanted feedback, and the
particular terminations used must not permit the transistor to operate in a region where
internal feedback can cause potential unstability. This is the "gain" of an oscillator
paradox. The ideal way to guarantee that the above conditions do not exist is to
measure the two port impedances when terminated at the other end by the apparent
required match, to see that no signs of negative-resistance exist. This latter condition
leads to (c.).
In any circuit with R, L, and C components, a basic loaded Q is present. Assume
that this circuit is the complex conjugate match for a transistor. When this transistor
is inserted, its output conductance appears across the circuit and the circuit Q should
decrease to half the original value. Now consider what would happen were the
device to have positive feedback. With enough feedback the output of the transistor
has a negative resistance component which absorbs some of the circuit losses and the
Active Q now increases. Even if this feedback is internal, rather than caused by
unknown and uncontrolled strays, it is difficult to state with confidence the true gain
of the transistor. However, a means of using the bandwidth of the circuit as a criterion
of stability is available. Thus, the Active Q may be made less than that of the circuit
Q alone. This approach will not suffice for negative feedback where the solution
relies on the neutralizing techniques which are to be discussed shortly.

MEASURING POWERGAIN
Power Gain depends on the particular definitions used and the frequency or band
of frequencies being considered. These definitions are as follows:
2
1. G = ( ~2 ) RL or G =Pout; where ~=current amplification gain
h R1 Pin h
This is the low frequency case and is the actual gain between R1rea and
lnblt'= J:-2.L_
R1o• d and is maximum when Rir..n = Rtnputand R1.= Ruut1m1,Pnvnl
where Eo = open circuit generator voltage. 4 "" 0

2. Grranedur.. : (circuit gain or available power)

GTran•dur•ris the output to available power ratio. The closeness of matching
conditions to the two-port impedances of the amplifier will determine how
closely Gr approaches Gmu aYAI IAblo,

257
TRANSISTORMEASUREMENTS

3, Gani lab le:

This is the gain of the transistor with only the real part of its input and
output impedances matched to the load and generator.
4. Gmazlmum aYal labJe,!

The real parts are matched and the reactances are tuned out, that is, the
same impedance but of opposite phase. This is the complex-conjugate match
and is the most true gain obtainable. Close attention is required to distinguish
between this and Pseudo gains which may appear larger due to positive
feedback.
All of the above definitions, with the possible exception of (1) may be considered
as classes and are often divided into sub-classes as determined by the considerations
mentioned earlier when discussing the phases of the measurement problem. As to the
particulars of each measurement set: while it may be possible to measure the
current amplification gain in (1) and (3), it is usually easier to have switchable Ro and
RL so arranged that the available generator power is kept constant and an output volt-
age is obtained proportional to the power in the load. It should be noted that this circuit
is also applicable to (2) as long as a resistive generator is desired or necessary. The
device, potentially unstable if complex-conjugate matched, may be usably stable if
only one terminal is complex matched and the other resistively terminated. For prac-
tical reasons the generator is usually the resistive match as shown in Figure 15.53.

WITH R, >>Rz, 2(Az+R3l »R2 Z\ •O•L >>R, MAX.

Rr• Rs• R... AIID•IF Eo.,,RflP,-,, R•+A 1• A,

TKtN~~,f'"l\

GEIERATOR

AN EXAMPLE o,TIIS TYPE

o, EQUIPMENTSUITAIIL[ FOR THEIOOKCTO 511C :SSOIC
RANGE.

POWER GAIN
MEASUREMENTCIRCUITS
IIMlly
Figure 15.53

258
 TRANSISTOR MEASUREMENTS

Measurement of (2) often takes the form of the circuit shown in Figure 15.54.
This is a Functional I.F. Test.

I.F. TRANSFORMER
(B1-FILAR WOUND)

BIAS RESISTORSCHOSEN FOR

IE• I.OMA FOR AVERAGEUNIT.

FUNCTIONALI.F. POWERTEST
Figure15.54

To reproduce the measurements from set to set, the transformer loaded imped-
ances, losses, and bandwidth must be specified. The layout is standardized and pre-
cision resistors and meters are used to establish the D.C. bias conditions. Since gain
varies with temperature, means of controlling or at least monitoring temperature
should be included. The use of attenuators to set relative levels on the VTVM is
encouraged, rather than relying on the linearity and accuracy of the VTVM.
For complex-conjugate matching, and also for a simple method of measuring high-
frequency gain, the .,,.network has proven very useful as an impedance transformer.
With care, the losses in the network can be kept low (in the order of 1 db). It should
be remembered that this network acts as a filter, and bandwidth measurements
should not be made. Where bandwidth is important the use of variable link coupling
networks will prove more satisfactory.
In the following circuit, Figure 15.55, the detector is coupled into the generator
at the calibrate jack. The network is then adjusted for a maximum reading. Assuming
the losses of the input network are constant with small variations of match, and the
input impedance of the transistor is close to the 50 ohms of the detector, the output
will be the zero db reference setting, and only the losses in the output network are
important. By keeping these losses small with proper network design, the losses can
then be considered as part of the transistor's gain.

NEUTRALIZATION
The need for neutralization arises when internal feedback exists. The device is not
unilateral and variations of load affect the input impedance. This fact enables one to
devise methods of determining when neutralization has been accomplished. There are
two accurate measuring techniques. One uses a resonant load and sweeps the input

259
TRANSISTOR MEASUREMENTS

HIGH FREQUENCYMATCHINGNETWORKS
CALIBRATE

DETECTORUSED: BOONTON ELECTRONICSCORP.

MODEL 91-B (0.003 V FULL SCALE
SENSITIVITY I
i DETECTOR 7
HIGH FREQUENCYPOWERGAIN
Figure 15.55
I
1
I
L---
11
, -=-
-
---
!!Oil
-
DC
CHOPPER
AMPLIFIER
- ______
I
I
1
I
J

with a variable frequency signal current source. As the signal goes above and below
the resonant frequency, the load becomes first capacitive and then inductive. If a high
impedance sensitive detector is used to look at the input voltage, the changing
impedance is seen at the input due to reflected load changes. At frequencies up to
5 or 10 mes such detectors are available, but in the VHF range a different approach
is used. The second approach, applicable at most frequencies, is to measure the feed-
back voltage appearing at the input when a signal is applied at the output. This is
precisely what is done in measuring hrb,
In both methods some out of phase feedback is applied in parallel with the device,
so as to cancel either impedance changes or feedback voltage. Means of amplitude
and phase control will need to be incorporated in the neutralizing network to avoid
over-compensation. Simplified circuit diagrams are illustrated in Figure 15.56 to show
some of the various feedback schemes used. The feedback networks are lumped-
constant types at lower frequencies and transmission line types at VHF.
COMMON BASE

WHICH
WHEN
REDRAWNIS:
INPUT
------ .......
,

R'

L ___ L~
J __ JI
RIC FEEDBACK, NEUTRALIZING
NETWORK
SOMETIMESR/L
USED INSTEAD

COMMONEMITTER
NOTE:
FEEOBACKMAY OFTEN
BE TAKEN FROMA "TERTIARY"
WINDINGOR LINK COIL.
OUTPUT

NEUTRALIZATIONMEASUREMENTS
Figure 15.56

260
 TRANSISTORMEASUREMENTS

To check the true gain of a transistor, unilateral amplifiers are used in the feedback
path to supply the power consumed in the feedback (neutralizing) network, thereby
not loading the transistor's output, as shown in Figure 15.57.

+-
VARIABLE LINE STRETCHER
GAIN TO ADJUST PHASE
AMPLIFIER

SCHEMATIC OF TRUE GAIN MEASUREMENT

Figure 15.57

TRANSISTOR NOISE MEASUREMENTS

GENERAL
The noise output from an amplifier consists of two parts:
1. Output due to noise generated at the input-terminals.
2. Output due to noise generated inside the amplifier itself.
Part 1 of the noise power output is predictable since the available noise-power in
any resistor is
=
Pn kTB (15a)
where,
k = Boltzman' s constant
=
T Absolute temperature (°K)
=
B Effective bandwidth
and this effective bandwidth is

B=i;i~(f)df (15b)
0
By measuring the gain with frequency, integrating and dividing by the maximum
gain, the equivalent rectangular power pass-band is found. Since noise-power at the
output consists of two parts, and one of these may be predicted, this may be used
to specify the noisiness of an amplifier. The index used for this purpose is called the
noise factor and is defined
Total Noise Power Out
F
Power gain X Noise Power due to Source Resistor (15c)

261
TRANSISTOR MEASUREMENTS

or,
PN
F= G • Pn
.
Bu t smce, =
G (Ps)out h p . . al
(Ps)in , w ere s 1ssign power
(Ps)tu ( Signal)
F= PN - Pn - Noise In
(Ps)out p - (Ps)out - ( Signal) (15d)
(Ps)1n • u PN Noise out
Noise Figure (NF) = 10 log F
Expressed in terms of voltage and resistance, the available noise-power can be
written
En1 -
Pn= 4 R« =kTB (15e)
or,
En= ✓ 4kTBR, (15£)
At room temperature, 4 kT = 1.6 X 10-20 joules.

MEASUREMENTOF NOISE FIGURE

In equation (15f) En is the noise voltage at the input. Now a signal is added at the
input ('Y times En) such that the output level with signal is much greater than the noise
output. This value 'Y is the signal-to-noise ratio and "calibrates" the output level of
the entire measuring system. When the signal is removed, the output level should
drop to .!_of this calibratedlevel provided the amplifier is perfect. Since the amplifier
"V
contributes some noise, the level will not drop that far. The ratio between the actual
level of noise background and the ideal case is the noise factor and the noise figure
may be read on the db scales of the VTVM used. Since the noise voltage fluctuates,
sufficient capacitance must be added across the meter movement of the VTVM to
integrate the noise voltage with time. If an average-reading meter (calibrated in RMS
of a sine wave) is used, then the meter will read 11% lower on noise than on sinusoidal
signals, and the "calibration" signal must be reduced accordingly for correct measure-
ments~ If a troe RMS meter or bolometer is used, this correction is unnecessary.
Since the unknown signal is present during the calibration process, the measured
Noise Figure is not the true Noise Figure.
AcCt')rdingto equation (15d)
Signal)
(
F- Noise In (15g)
- (Signal)
Noise out
The input during calibration is S' 1n= (Ps)1n+ Pn
The noise input is N',n = Pn
and,
~ - I+ (Ps)1n
N'1n - Pn (15h)
The apparent output signal S'out = G [(Ps)1n+ Pn] + PE
The apparent output noise N' out = GPn + PE
where PE is the noise generated in the transistor.
Therefore,
S' ;ut = G [(Ps)1n+ Pn] + PE
N out GPn + PE (15i)

262
 TRANSISTOR MEASUREMENTS

The measured noise factor

S',tn l + (P11)1n l + ~
F»=~= Pn - N,n (15j)
S out G [(Ps)tn + Pn] + PE - l + Soul
N'oul GPn + Pr. N u1 0

since G (Ps),n is the true output signal = Sout

and GPn + PE is the true output noise= Nout
By re-arranging equation (15j)
~ l + Nout l + Nin
F If = ~ • Soul = F Sin (15k)
Soul l + Nin l + Nout
Noul Sin Sout
or the true noise factor
l + Nin
S,n
F = F )I N (151)
+~
1
Soul
From equation (151 )it is seen that if Sou1is much greater than the noise background
level F approaches Fu since this also implies S, n> > N, n,
One other complication is that the noise output of the transistor under test is far
below the level of sensitivity of most commercially available meters, so that an amplifier
must be used to raise the noise level to a readable level. Unfortunately, this amplifier
can contribute noise of its own and degrade the readings.
It is easily shown that the total noise factor of a cascade system is
Fr - 1 Fa - 1
FT=F1+--c;-+ Ci Gr+..... (15m)
So that G should be made as high and F :1 as low as possible to avoid these errors.
(Removing the device under test while observing the noise background will supply a
quick check on post-amplifier degradation. The output level should drop 20 db or more.)
A much more convenient way to make noise factor measurement is to use a noise
diode. It is known that the output noise current from such a no!se diode is:
Is' =
2q Inc B (15n)
q = electron charge
Inc = plate current in diode
B = effective bandwidth
If the source resistance is R,, the available noise power is
l:l Ra: 2q Inc B R 1
S I= -4- = 4 (150)
This is the noise power generated by the diode alone. The noise power due to Re is
N, =kTB (15p)
and this is in addition to S,.
The excess noise generated in the amplifier is NE and the power gain is G and if M
is defined as the ratio of noise power output with diode turned on to noise power out-
put with diode turned off
then,
( kTB + 2q lo: B Rs G + NE) (15q)
M
kTBG + NE

263
 TRANSISTORMEASUREMENTS

or,
2q Inc BR,G
M-1 =--4 ___ (S)
kTB G + N •: = N out
(15r)

and since,

(Ns) = In kTB
(15s)

we have,
~) 2q Inc B R11
(
F =~
~)
-- 4
M-1
(15t)

( N out

=
But at T 290°K (l7°C),
4
\\=
20 (volts)-'
So equation (15t) can be written as
_ 20 Inc Rii
F (15u)
- M-1
Usually Mis chosen to be equal to 2
therefore the noise factor is,
=
F 20 Inc R11 (15v)

EQUIVALENTNOISE CURRENTAND NOISE VOLTAGE

Because of the internally generated noise, the output noise current is not zero when
the input is open, and for the same reason the output noise voltage is not zero when the
input is short-circuited. Since the noise current and noise voltage output are solely
dependent on the transistor it seems that a noise specification based on those two
quantities would be more generally useable. In the following derivation the relation-
ship between open circuit noise current, short-circuit noise voltage and noise factor
will be shown. A noisy amplifier may be substituted by a noise-less amplifier with
equivalent noise-current and noise-voltage sources connected to the input, as shown
in Figure 15.58.

Rg NOISY NOISELESS
AMPLIFIER AMPLIFIER

THEVENIN'S EQUIVALENTOF NOISY AMPLIFIER

Figure15.58

The total noise-power at point A is proportional to

~ 4 kTB + es:1 + :---:i
1T =~ R/ ls
(15w)
The first term is the noise-current generated in R11 and since the noise factor,
F_ all noise
- noise due to Ri:

264
 TRANSISTOR MEASUREMENTS

then,
F-1 et? WRir {15x)
- + 4 kTB R, + 4 kTB
1
B = effective bandwidth =-GlJAxJo
f ~(f)df
where,
G{f) = gain as function of frequency
=
GY,.x maximum gain
Defining,
e:1?
R...... 4kTB =
(15y)
i:.-.2
J.,qv = --.....=-
2qB
equation (15x) will be,
F - 1 + R..11v + 2q l1111v
{15z)
- R 11 4 kT
and since,
2
4
=
~T 20 (volts)-1 at T 290°K, =
F =
1 + _!lR:v
+ 20 lo,1v Ric (15aa)
In Figure 15.58 the noise-voltage source may be thought of as a lossless resistor R,.,1.,,
and the current source as a parallel shot noise generator due to an equivalent DC
current l.q...
To find the optimum value on the noise factor the derivative of F equation {15x)
is taken with respect to R", and this optimum noise factor is found to be

Fopt =1 + ~ ' ..:_= 1 + 2'\J20 Roqvleqv

2kTB {15bb)
for,
- _ ✓-==-
e;1;2 1-R ..,1v
Rg-Ro 11t- = ✓-- =h-2
201 ..,1..
(15cc)

From equation (15bb) it is seen that the optimum noise factor can be found analytically
if e:./'and i:-.2 are known. This is also the noise factor which will be measured if a meas-
urement is made with a source resistance R..p,,
Combining equations (15x) and (15bb).
F = l + F ..pa2-1 [_&_
pt
+ Ropt]
R.. Ric
{15dd)

Therefore, if Fnpt and R..11t arc given, the noise factor can be found for any source
resistance Ri:,

'
Defining a factor k, as
k = _!_
2
[~
R..pt
+ R..,,, ]
R11 4
equation (15dd) becomes k
F = 1 + (F .. 1,1 -1) k
(15cc) 2

FACTOR k VS.~ .25 .5 I 2 3 4 5678

Ru,,t
Rg
Figure 15.59
Ropt--+

265
TRANSISTORMEASUREMENTS

For example, the optimum noise figure (NF)opt is given as 1.5 db or Fopt =
1.4. The
optimum source-resistance is 10000. What is the noise factor in a circuit where
Rg = 8 kO. The ratio RRir
npt
= 8, and from the Figure 15.59, k is found to be 4.
Therefore, the noise factor will be ·
F = l + (Fopt -1) k = l + (1.4 -1) <4 = 2.6
NF= 4.1 db

MEASUREMENTOF (eN1)* AND (1;1)* FOR TRANSISTORS

The schematic in Figure 15.60 is used to measure (el'l1)*.

METER
TRANSISTOR NARROW
---ATTENUATOR.-.--. UNDER BANDPASS
TEST FILTER

SET UP TO MEASURE(er.S)'lz
Figure15.60

Rg must be chosen so as to be much smaller than the input resistance of the

transistor.
It is known from transistor-analysis that
ro ,
Reqv ~
2 + lb
To make ::••" in equation (15aa) the dominant term,

Roqv>>Re or Rr<< ~
The measurement-procedure is as follows:
a. The back-ground noise-level is noted.
b. The signal generator is connected through a suitable attenuator, and the level
of the generator is adjusted until the device output level is 20 db above back-
ground level.
c. The required input level is measured from which en can be determined.
To measure the equivalent noise-current, an almost identical circuit is used. The
only difference being Re replaced by a high resistor inserted in series as shown in
Figure 15.61.

r ATTENUATOR
TRANSISTOR
UNDER
NARROW
BANDPASS
METER

t Rg
V
TEST FILTER

GENERATOR

SET UP TO MEASURE (iN2)1/z

Figure15.61

266
 TRANSISTORMEASUREMENTS

A condition which must be satisfied is

~
J4 kTB
R,/
<< 4. /
\J
ry
ls

If the background noise level is Vn and the input voltage V gives E volts out, then
equivalent noise-current is
. V VN
b,= Re •y
It should be strongly emphasized that eN and 6 must be measured under the same
operating conditions to have any practical significance, and also the necessary correc-
tion must be made for the lower meter reading on noise.

MEASUREMENTOF NOISE FACTORWITHOUT USING SIGNAL GENERATOROR

NOISE DIODE
The concept of equivalent noise current and equivalent noise voltage can be used
to measure noise factor without a signal generator or noise diode. Since the noise factor
depends on the source resistance, and every resistor is a thermal noise source by nature,
the source resistance can be utilized as a noise generator.
The method is based on three measurements, from which the noise factor can be
computed
1. The noise voltage at the output, input open-circuited.
2. The noise voltage at the output, input short-circuited.
3. The noise voltage at the output, the desired source resistance connected to the
input.
One necessary condition in this method is that the input resistance to the device
be known, or be measurable.

v=:r
,n

EQUIVALENT NOISE CIRCUIT

Figure15.62

'\Jes" is the noise voltage generated in the source resistance R 1

'\Je. • is the equivalent noise voltage, input shorted

'\J(io')' is the true equivalent noise current, input open
'\Je,n"is the noise voltage generated in the input resistance
The above circuit, Figure 15.62, is re-drawn as a current equivalent in Figure 15.63.

267
TRANSISTORMEASUREMENTS

NOISE CURRENTEQUIVALENTCIRCUIT
Figure15.63
The relationships between currents and voltages are,
- -e• - -e 2 - -.
i•- ir •j•-__!_•j•-~
ir - Rirll , s - Rg2 , In - Rial
The total current flowing into the parallel combination of Rir and R1n
2
p
T
=
e/ +1 es2+ (i0 ')ll + e1n1
Rir R1n
(15££)

The measured open circuited equivalent noise voltage is due to

eo1 =
(io')1 R1a1 + e1n2 (15gg)
Combining (15ff) and (15gg) gives
77
lT (15hh)

The noise factor

02

F = iT2 el+R/ es'+ R,n1

e
- 1 + es + eo
- 1 - 1( )•
Rir (15ii)
i,2 e/ - e/ es" R1n
R/
From this last equation it is seen that F can be expressed in terms of voltage ratios;
and, therefore, only output voltages have to be measured.
Equation (15ii) is not too useful since we can not measure e, separately.
The noise factor may also be expressed as,
F = [total voltage across parallel R, and R,nT'
[voltage across parallel R, and R1ndue to iir1'

(15jj)
F=il[R~R;J
=et[R~i•RJ
268
 TRANSISTOR MEASUREMENTS

Multiplying both sides of (15jj) by ei;' and solving for es"

- - e"t
es" =F R1n es"
2

(15kk)
e"
2
(R,n + R")2 eT 2
Substituting the identity,
eo1 eo1 es"
e/
==-=-.-=-
es1 e, 1
and equation (15kk) into equation (15ii), and solving for F,

eT
es2
2
( l +~)'Z
R,n
F=l-------'- (1511)
2

l + eo (Rr)
es" R,n
2

According to equation (15cc),

Ropt= ~
and since,
vw
e1l = el
and,

(15mm)

and equation (38) becomes,

1
F =-------,---,(
1+
R,,,.........,),......,,....-
Ir
1

Ropt (15nn)

~output voltage when R1 is connected to input

~output voltage, input terminals shorted
'\Jeo output voltage, input terminals open
2

Ropt= R1n
eo
g
R,n = input resistance of transistor.
Thus, the measurement of noise factor is accomplished without the use of a noise
generator or diode.

TRANSISTOR NOISE ANALYZER

A more convenient way to measure equivalent noise voltage and current is to use
the Quan Tech Transistor Noise Analyzer Model 310. This is an instrument where
equivalent noise voltage and current can be read directly at three different center
frequencies, namely at 100 cps, 1 Kc, and 10 Kc. The noise voltages and currents are
read in volts pet square toot cycle (V / Vcycle) and Amperes per square root cycle
(Al \I cycle).

269
TRANSISTORMEASUREMENTS

Example:
Transistor 2Nl23
VcF.=-5V
IF. =1 mA
Equivalent short-circuited noise voltage ~ =
1.8 X 10-0V/ V cycle
=
Equivalent open-circuited noise current I; 2.5 X 10-12 A/ v cycle
(measured at 1 Kc)
This gives
1.8 X 10-e
= =
Ropt 2 _5 X 10_12 720 fl
and
_ eN is _ 1.8 X 2.5 _
F opt - + 2 kT - + 8 - 1.564
=
Optimum noise figure 1.94 db.

CHARGECONTROLPARAMETER
MEASUREMENT
The measurement of the charge parameters (described in Chapter 7) are discussed
in this section. The four parameters which are currently specified on G.E. specification
sheets are measured in the manner shown in the following paragraphs. NPN configura-
tion is used for circuit layouts, but PNP measurements can be accomplished by revers-
ing the polarity of Vin and Vee, One consideration which should be mentioned before
the actual circuits are introduced is that of measurement accuracy. In any measure-
ment of switching speed, determination of the pulse voltage magnitudes and the bias
voltages is extremely critical. In these parameter measurements, an attempt was made
to minimize the number of critical pulse and bias voltage measurements necessary.
Ta,THE EFFECTIVE LIFETIME IN THE ACTIVE STATE
The circuit used to measure r. is shown in Figure 15.64. Inasmuch as the circuit
contains no dissipation limiting resistor, extreme caution should be used to assure that
Vcc • le does not exceed the dissipation limits of the device.
Vee

PULSEWIDTH1i50USEC TEK TYPE

REP.RATE;.2KC TEKTRONIX 545SCOPE
TYPE 131
V l/2W1 I% CARBONFILM AMPLIFIER
IN~

RUTHERFORDPULSE
GENERATOR,
MODELB-7
"-IOK
-~
, .., ..
TEKTRONIX
CURRENTPROBE
P6016

Ta TEST CIRCUIT
Figure 15.64

To perform the actual measurement, the following steps are taken:

1. Before the device is inserted into the test socket, V ,namplitude is set to below
+.3 volts.
2. Vcc is set to +4 volts. (This voltage may be lowered when dissipation is an
important factor, but should not be made lower than +2 volts.)

270
 TRANSISTORMEASUREMENTS

3. A Tektronix Type 131 Amplifier and Tektronix Type 545 Oscilloscope (or
equivalent) are set up so that the collector current at which measurement is
desired produce a scope deflection equal to 3 cm. The current at which the
measurements should be made is that le for which the device dissipation rating
is approached by the Vcc • le product. This point is used for the measurement so
that the Ta obtained will be the true minimum and be accurate for "worst-case"
design techniques.
4. The device is now inserted into the test socket. CAUTION: If the base lead
accidently touches the collector lead during insertion, the device may be
destroyed, unless an electrically current-limited power supply is used.
5. The input voltage is now increased until the le deflection is 3 cm (or the desired
Io value).
6. Ta is the time constant of the resulting pulse waveform as shown in Figure 15.65.
It is NOT necessary to record the input pulse amplitude.

I
TURN ON__J
OF v,N 1

Ta MEASUREMENTWAVEFORM
Figure15.65

Tr., EFFECTIVELIFETIME IN SATURATEDSTATE

The test circuit for measuring Tb is shown in Figure 15.66
PULSEWIOTH•IOUS
REP.RATE• 2 KC

V1N2 f"-i TO TEKTRONIX545

V1N1_f7__

RUTHERFORD
PULSE
GENERATOR,
MODEL8-7

Tb TEST CIRCUIT
Figure 15.66

The following steps are taken to perform the Tb measurement:

1. Vee is chosen to be approximately one-half the transistor's breakdown voltage
(about 10 volts for most alloy switching transistors).
2. R 1, is chosen so the current flowing when the transistor is saturated is equal
to a median current. (For alloy types where 100 ma is the maximum current
permissible, RL could be from 200 ohms to lK for Vee =
10 volts. In switch-
ing transistors of the mesa type, Vee =
10 volts and RL =
lK are common
conditions.)

271
TRANSISTORMEASUREMENTS

3. R1is normally from 2 to 5 times larger than RL,

4. Vin is the quantity varied in order to make the n, measurement. The transistor
is saturated at two different values of V 1n,and the change in storage time is
measured. Ease and accuracy of the measurement may be enhanced with the
use of a Rutherford Model B7 pulse generator since Vin may be varied by the
built-in decade attenuator.
5. The unit is inserted into the test circuit.
6. Two values of Vin are chosen which fulfill the conditions that the circuit
fJ {forced /J, forced hFE,or Vee R1/V1nRL) is not more than ¼ of the device hFE,
7. The storage time portion of the trace is observed as shown in Figure 15.67.
Only .its and V 1ns/V1n1need be recorded . .6.tsis observed as the V 1nvalue is
switched between V1n1and V1112 by manually switching the generator's pulse
amplitude.
4
8. " is obtained by using the relationship that ,.. = : )
In(~·
V1n1
=
(ll V 1112 2.72 V 1n1,then n, = .its.)
f..,_.V1N2
TURN OFF At I
..__
_____ 7,
---i---- - - -___
POINT............. 5

'Tb MEASUREMENT
WAVEFORM
Figure15.67

Ca£,THE AVERAGEEMITTERJUNCTIONCAPACITANCE
Figure 15.68 is circuit used to measure CeE, It should be noted that the input pulse
used is to reverse bias the base emitter diode and is not of the polarity which would
tum the base-emitter diode on. To obtain the actual value of C,n~,the following steps
are taken
LOW CAPACITANCEPROBE
PULSE WIDTH=.I USEC __ ,._ __ .,TO TEKTRONIX
REP.RATE:: 2 KC 545
OPEN

:.:u-
RUTHERFORD
MODEL B-7

CumTEST CIRCUIT
Figure 15.68

272
 TRANSISTORMEASUREMENTS

I. Normally, Vin is from 10 to 20 volts and depends somewhat on junction break-

down voltage, i.e., IO volts may be too high for a low breakdown unit.
2. Insert the transistor into the test socket.
3. VeE transient is observed on the oscilloscope as shown in Figure 15.69. The
value of CaE is obtained from the relationship shown below the curve.

TIME (p.S)

=
VaE
J (OFF)
C BE dV

Ce£ MEASUREMENT WAVEFORM

Figure 15.69

4. One measurement of capacitance is made to determine measurement gear

capacity by performing the same steps with the test socket empty. Measurement
gear capacitance is subtracted from the measured CaE to determine the
actual CeE.

COMPOSITECIRCUIT FOR 'Ta, 'Tb, Ces

The similarity of the -ra, Tb, and CBEtest circuits allow that they may be combined
in one flexible test circuit as shown in Figure 15.70. The appropriate R1and RL condi-
tions allow for the various parameter measurements.
.--- .... Vee

RL "O, IOOQ ,200'1,500'1,

IK, OR OPEN.
MUST BE CAPABLE OF ATTACHING
CURRENT PROBE FOR RL =O.

SOCKET MUST HAVE LOW

CAPACITANCE i. e. < I pf

COMPOSITE CIRCUIT FOR Ta, Tb, ANO C 8 E

COMPOSITECIRCUIT
Figure 15.70
TRANSISTORMEASUREMENTS

Qs*, TOTAL CHARGETO BRING TRANSISTORTO EDGE OF SATURATION

The circuit used to measure Qn* is shown in Figure 15.71. Capacitor, C, is chosen
to supply adequate charge to the device being tested without requiring an excessive
Van pulse. For alloy transistors a 5 to 100 pf variable capacitor with the capability of
switching in additional capacitance, in steps of 100 pf, is used. Mesa transistors require
a 3 to 50 pf range. It is important that low inductance capacitors be used. General
Radio precision capacitors, Hammarlund type air dielectric capacitors, or their equiva-
lents are satisfactory. In any case, excessive capacity between the base lead and circuit
ground must be avoided.
Vee

TO TEKTRONIX 545
(OR EQUIVALENT)

Ga* TEST CIRCUIT

Figure15.71

Qa• is a function of collector voltage variation and collector current. Thus, meas-
ments are made for various Vcc and Rr. combinations. The following steps are taken
to obtain Qs • data.
1. Vcc is determined first. Several values of Vcc will be necessary to determine the
full Qa* picture; however, data is taken for one Vee value and various Rt values.
Vcc values of interest range from BVcEo value to a value of 1 or 2 volts.
2. The unit is now inserted into the test socket.
3. The product C(V an - VnE) is the charge which is placed into the transistor to
bring it to the edge of saturation. A value of Vanis chosen which is sufficient to
permit enough charge to pass into the base of the transistor to bring it to the
edge of saturation. This, of course, will also depend upon the range of capaci-
tance available. Van is normally between 5 and 20 volts, so that Van> >VnE,
The capacitor used should be carefully chosen for large variation so as to render
the test set more valuable.
4. With Vee and Van adjusted, data can be taken. Record the values of Vee and
VIn, A typical oscilloscope pattern is shown in Figure 15.72.
Vee------

____ -- __ ------ _ ___ _.c90¾ FROM Vee

V TO VcE SAT.
CE (SAT.l------------~ '
Gs* COLLECTORWAVEFORM too¾
Figure15.72

274
 TRANSISTORMEASUREMENTS

As C is increased, the peak of the waveform will approach VcE<RAT), Ceois

the value of capacitance necessary for the peak to reach 90% of the waveform
from V cc to V eE<IIAT>,while Cu,ois the value of capacitance necessary for the
peak of the waveform to reach VcE111AT>.
5. Q11*00and Q11*100 are the products of Ceo(Vin - V11&) and C,no(V,n - VaE) re-
spectively. Qn* values are then plotted against les (i.e., Vee - VeF.<RAT>)as shown
~~~reIBn &

00•,o~
00*9ojvcc2

00*,oo\_
00*9ojVcc1
0990
09• f (COLLECTOR CURRENT)
Oc• f IVOLTAGE)
Ics tMA)

011* PLOT VS. lcs

Figure 15.73

These plots are generally linear over a wide collector current and voltage
range for alloy and diffused transistors. The intercept on the Qe• axis is called
Qc and is the part of Qu• which varies with collector voltage. The part of Qe•
which varies with lcs is called Qe. Thus, Qo• Qu + Qc.=
Qe and Qe can also be plotted separately if desired.

CALIBRATIONOF CAPACITOR,C, ON Qe* TEST SET

A simple method of calibrating the capacitor on the Qe • test set is available if the
circuit in Fi~e 15.74 is used. The fact that the reactance of the capacitor at 1.59 me
(frequency chosen for convenience) is large compared to 100, permits the 10 ohm
resistor to be used as a current measuring device. Looking at the equations
Xe= (21rf C)-1
=
V,n I Xe

CALIBRATION OF CAPACITORON ae*TEST SET

____ ,.H.P. MOD
4OOC VTVM

0
o---------vt----------41------"'.I SOCKET

I VOLT RMS 50n

1.59 MC/S

CAPACITORCALIBRATION
Figure 15.74

275
TRANSISTORMEASUREMENTS

or,
C = (2,r f Xc)- 1

I
-271' f Vin
If V 1n = 1 volt RMS and f = 1.59 me, then,
C =(I) 10- 1

Using the 10 ohms to measure current,

I =
Va/10 ohms
therefore,
C =
Va (10-11).
Thus, the VTVM reading, Va, is used to calibrate C, and .1 mv RMS indicates 1 pf, etc.

C
B o
o- .... ,._ ___ -ut- ___ ...,.,__ __ --u +--INPUT I VOLT RMS
1.59 MC/S
ADD E
SHORT--+ 47k

o---.,._ _______ __..,__

___ __.~VR OUTPUT TO

H.P. MODEL
400C VTVM
NEWREFERENCE

-
STRAY CAPACITANCEMEASUREMENT
Figure15.75

If it is desirable to know the stray capacitance from the base to emitter in the
test circuit, a similar measurement can be made as shown in Figure 15.75. The variable
capacitor is set at a known value, say Ci, so
Cetra:r = Va ( 10-8) - C1
Note that in this determination of stray capacitance the normal circuit reference
has been changed. Care must be taken to insure that the old reference is not shorted to
the new test reference.

276
REGULATED DC SUPPLY
AND INVERTER CIRCUITS

REGULATED
DC SUPPLY
The regulated supply of Figure 16.1 is a conventional circuit using a series regu-
lating element. With QI mounted on a 2" x 2" x %2" aluminum fin the circuit can
operate in an ambient temperature up to 70°C. At higher ambient temperatures a heat
radiator should be used on Q2, or a higher Zener regulating voltage could be used to
decrease the dissipation in Q2.
TRIAD
IA F-92A

REGULATEDDC VOLTAGESUPPLY
Figure16.1
Q 1 requires a V ct:a capability equal to the unregulated output voltage of the bridge.
The voltage rating for Q2 must be equal to the difference between the regulated out-
put and the Zener voltage.
Figure 16.2 shows equal regulating ability for all load currents to 350 ma, and
2 % voltage regulation at 400 ma. Improved regulation can be achieved by using a
Darlington connection for either, or both, QI and Q2.
The peak-to-peak output ripple of the circuit in Figure 16.1 is approximately .24
volts at 400 ma load current and decreases to .01 volts at no load. The output imped-
ance is less than 3 ohms from DC to 20 cycles and then decreases to less than 1h ohm
at 200 cycles and beyond. The output voltage has no overshoot with step load functions.

u~ =Ii-----+--
0
I ~______,________1
I
100
1~._______.__...1
1~____.____.1
200
~~_______._____
300 400 500
LOAD CURRENT(MILLIAMPERES}
OUTPUT VOLTAGE VS. LOAD CURRENT
Figure 16.2

277
REGULATED DC SUPPLY AND INVERTER CIRCUITS

PARALLEL
INVERTERS
The parallel inverter configuration shown in Figure 16.3 provides an output that is
essentially a square wave. By rectifying the output voltage, the circuit makes an
efficient DC to DC converter in applications such as power supplies. An AC input can
be rectified to provide the primary power for the inverter, in which case it will func-
tion as a frequency changer. A square wave drive to this inverter causes Ql to conduct
half the time while Q2 is blocking, and vice-versa. In this manner, the current from
the supply will flow alternately through the two sides of the transformer primary and
produce an AC voltage at the load.

DC TO AC (SQUAREWAVE)INVERTER
Figure16.3

It may be desirable to incorporate the feedback diodes D1 and D2 if the circuit is

to be lightly loaded or operated under open circuit conditions. For reactive loads these
diodes can conduct to supply the out of phase portion of the load current. When the
inverter switches from Q 1 to Q2 an inductive load prevents the main load current
from reversing instantaneously, so transformed load current must flow through D2 and
back into the DC supply until the load current reverses. The feedback diodes prevent
the voltage across either half of the primary winding from exceeding the supply volt,
age. These diodes not only maintain a square wave output under all load conditions,
but also decrease the voltage requirements for Ql and Q2.
The DC source should have a low transient impedance, and a capacitor on the
output of the DC supply is usually required so it can accept power as well as supply
power. It is often important to have this capacitor (C1) right at the inverter itself as
shown in Figure 16.3 since the inductance of the supply leads of a few feet in length
represents an undesirable impedance during the µ.sec switching intervals.
For a driven transistor inverter, it is desirable to select a transformer and core
with a volt-second saturation capability that is at least two times the actual circuit
requirements. The leakage inductance should be held to a minimum since the trans-
former will be subjected to rapidly changing currents during the switching interval.
Bi6lar transformer winding is usually used to obtain tight coupling between the two
primary windings. Since the inverter output transformer (T3) cannot be allowed to
saturate, its design must either incorporate an air gap, have a high ratio of saturation
to residual flux density, or be used with predictable reset circuitry.
The inverter circuit of Figure 16.3 was operated using two stacked AJ-H12 (Arnold)
C-cores (4 mil), in transformer T3. The core gap spacing was .02 inch. This gives about
a 2: 1 volt-second capability at 400 cycles.
The square wave inverter drive is easily obtained with a transistor multivibrator
that uses a unijunction transistor to stabilize and control the frequency as in Figure
16.4.This circuit provides a symmetrical square wave drive which avoids second
harmonics in the output and also a DC component in the inverter, tending to saturate
the transformer.

278
 REGULATED DC SUPPLY AND INVERTER CIRCUITS

16.4V

33
1500 1500

+
+24 TO 32V
(SOMA AT
2e voe>

47fi

0 1-GE 2Nl671A UNIJUNCTION

03 0 4 -GE 2N526
D1 Dz-GE 4JZ4 XS.2B (8.2V, IWATT)
D3 D4 -GE INl692
Tl-GE 9T93Y1338
~Tl
~
65--.66 67--.68
SQUARE WAVE INVERTER DRIVE CIRCUIT
Figure16.4

The circuit of Figure 16.4 is a slightly modified "hybrid-multivibrator," described

in more detail in Chapter 13. The unijunction transistor provides a source of short,
precisely timed negative pulses with the period between pulses depending on the
C1R2time constant. These pulses are coupled to the common emitter resistor of a con-
ventional transistor flip-flop (Q3 and Q4). Each pulse from the unijunction transistor
will tum off the transistor which is on in the Hip-flop and the resulting square wave
of voltage at the collectors is coupled to the inverter by a small transformer. D3 and
D4 are used to prevent the emitter-base voltage of Q3 and Q4 from exceeding ratings
when a transistor is turned off.
The multivibrator free runs at about 100 cps, but is synchronized and controlled
by the unijunction at the higher operating frequencies at which it is designed to
operate. The Zener diodes form a simple shunt regulator to keep the collector-emitter
voltage of the transistors within ratings. This circuit has good frequency stability with
variations in supply voltage and ambient temperature, due to the inherent stability of
the unijunction. The circuit has an operating frequency range of 400 cycles to 3200 cps
in an ambient temperature up to 70°C. The output impedance of this square wave
generator is about 8 ohms and the open circuit voltage is about 4 volts peak.
With the circuit of Figure 16.4 driving the inverter of Figure 16.3, the inverter
output voltage waveform across the load is shown in Figure 16.5. The efficiency of
the square wave inverter (Figure 16.3) is 80 to 85% in the 400 to 3200 cycle frequency
range.

279
REGULATED DC SUPPLY AND INVERTER CIRCUITS

(a) 400 cycles

(b) 3200 cycles

INVERTER
OUTPUT
VOLTAGE
(VERTICAL SCALE 50 VOLTS/CM)
Figure16.5

DCTO DC CONVERTER
A full wave bridge (1N538's) between the secondary and the 500 ohm load of
Figure 16.3 will rectify the 3200 cycle square wave shown in Figure 16.5(b) to give
90 volts DC output. With 100 µ.f electrolytic capacitor across the load, the ripple is
less than ½ volt peak-to-peak. The overall DC to DC efficiency is about 80% with
16 watts output.

REFERENCES
"General Electric Silicon Controlled Rectifier Manual.'' 2nd Edition ( 1961 ).
"Notes on the Application of the Silicon Unijunction Transistor," G-E Application Note 90,10.

280
SILICON SIGNAL DIODES

Semiconductor diodes are used extensively in all types of electronic circuitry. The
various application chapters in this manual illustrate many of the applications in which
diodes are used, from detectors in radio receivers to gating and logic elements in com-
puter circuits. The first semiconductor diodes, made before the invention of the tran-
sistor, were silicon point contact diodes used as detectors in radar receivers. Later,
germanium point contact diodes and gold bonded diodes were introduced which
could be used in a variety of applications. The demand for high operating tempera-
tures and low leakage currents led to the development of the silicon alloy junction
diode and the silicon diffused mesa diode. The reliability and superior electrical char-
acteristics of the silicon diode together with declining prices has caused it to be used
in place of germanium diodes in an increasing number of applications.

PLANAR EPITAXIAL PASSIVATEDSILICON DIODE

Silicon diodes can be made using any of the techniques described in Chapter 2
for transistor fabrication including alloying, growing, meltback or diffusion. On the
basis of inherent reliability and overall electrical parameters, however, the planar
epitaxial passivated (PEP) diode structure has proven superior to all others. Some of
the significant advantages of the PEP silicon diode include:
1. High forward conductance due to use of epitaxial material.
2. Low, uniform, leakage currents due to passivated surfaces.
3. Low capacitance due to small planar junction.
4. Low reverse recovery time due to accurate control of lifetime with gold doping.
5. High reliability due to passivation and rugged mechanical structure.

CUT AWAYVIEWOF
PEP SILICON DIODE
Figure17.1

281
SILICON SIGNAL DIODES
The cross-section and mechanical structure of a PEP silicon diode in a glass package
is shown in Figure 17.1. Fabrication of the diode starts with a wafer of low resistivity
single crystal silicon. A thin epitaxial layer of high resistivity silicon is grown on the
wafer. A layer of silicon oxide is formed over the entire wafer and the oxide is removed
from small circular "windows" by means of photographic techniques. The planar
junctions are then diffused through the windows in the oxide. Gold is plated on the
back of the wafer and diffused into the wafer at a temperature determined by the
required reverse recovery time. The wafer is cut into pellets each forming a complete
diode, and contacts are made to the front and back of the pellets. Each pellet is then
mounted in a glass package and the package is sealed.
Formation of the junction under a stable silico~ oxide layer results in a passivated
diode which is immune to contaminants which plague other types of silicon diodes.
The effectiveness of the passivation is substantiated by a tight distribution of reverse
leakage current, a parameter which is usually very sensitive to surf ace conditions, and
by the close correlation between the measured values of the electrical parameters and
the theoretical values. The use of an epitaxial structure reduces the bulk resistance of
the diode and thus makes it possible to achieve simultaneously a high conductance
together with a low capacitance and a low reverse recovery time.

DC CHARACTERISTICS
The characterization of the PEP silicon diode is greatly simplified by the close
correlation between the theoretical and the actual parameters. The d-c characteristics
are generally specified by means of the following parameters and characteristic curves.
1000
--- I
SHADED AREAINDICATES
25° C GUARANTEEDLIMITSOF
CONTROLLEDCONDUCTANCE .....
- TYPES IN3605
IN3606
,,V
~

Vi'
_/ ,_

100
- IN3608
IN3609
V'
/
.I
V
,,/ ,,
,,
/ ;/ I
10 I
/ tAlv I
f

I
'f
/
)

). F II
~
I

,
I

I ~ J
) J ~ I
0.1
, I
I Ji I
I
I
J I
/1sooc /2s 0
c j -55°C

I
QOO
V V I
0.2 0.4 0.6 0.8 1.0 1.2
FORWARDVOLTAGE-VF-VOLTS

TYPICALFORWARD DC CHARACTERISTICSOF PEP SILICON DIODES

Figure 17.2
282
 SILICON SIGNAL DIODES

1. Forward Voltage. The maximum value of the forward voltage, VF, is generally
specified at one or m~e values of forward current, IF, For controlled conductance
diodes such as the 1N3605, 6, 8, and 9 both the minimum and maximum values of
forward voltage are specified at six values of forward current. The relationship between
the forward voltage and forward current for a typical PEP silicon diode is shown in
Figure 17.2 at three values of ambient temperature. The shaded area indicates the
guaranteed range of forward characteristics for the controlled conductance types at
25°C. The tight control of forward conductance is very desirable in the design of
diode logic circuits where it permits greater design margins or additional logic stages
(see Reference 1).
The forward d-c characteristics of the PEP silicon diodes closely follow the theo-
retical equation
I
F
=I s
[ exp q (VF - 1•. Rs) - 1]
.,,KT (17a)

where
Is =
diode saturation current
=
Rs diode series ohmic resistance
q =
electronic charge (1.60 X 10-•ecoulomb)
K =
Boltzmanns constant (1.38 X 10-ta watt sec/°K)
T =
absolute temperature ( °K)
The parameter .,.,in the equation is dependent upon the impurity gradient in the junc-
tion and the carrier lifetime in the semiconductor material. At low values of forward
current, carrier recombination in the junction depletion layer is the predominant
factor in determining the relationship between forward voltage and current and .,.,e! 2.
At high values of forward current the relationship between forward current and voltage
is determined primarily by minority carrier diffusion and .,.,~ 1. The characteristics of
the PEP silicon diode can be approximated with reasonable accuracy by assuming that
.,.,= 2 over the entire current range. At 25°C this gives .,.,KT/q = .052 volt. The
dynamic resistance, ro, of the diode at a forward current, IF, is given by the equation
KT + R
r D -- 71 (17b)
q IF 8

2. Breakdown Voltage. The breakdown voltage, Bv, is normally specified at a

reverse current of 5 µ.a. The breakdown voltage increases with temperature up to the
point where the reverse leakage current becomes comparable with the current at which
the breakdown voltage is measured.
3. Reverse Current. The reverse current, In, is specified at a voltage below the
breakdown voltage. The reverse current increases exponentially with temperature as
indicated by the equation.
Ia = IHo exp a (T - To) (17c)
where Ia is the reverse current at temperature T, Ino is the reverse current at tempera-
ture To, and 8 is the fractional increase of Ia with temperature. For the PEP silicon
diodes 8 e:! .055/°C. The reverse current will increase by a factor of ten when the
temperature is increased by 2.30/8 =
42°C. At low values of reverse voltage the
reverse current is proportional to the square root of the voltage owing to the spreading
of the depletion layer. At values of reverse voltage comparable to the breakdown
voltage, the reverse current increases rapidly due to avalanche multiplication and
localized breakdown effects.

283
SILICON SIGNAL DIODES

AC CHARACTERISTICS
1. Capacitance. The capacitance normally specified for a diode is the total capaci-
tance which is equal to the sum of the junction capacitance and the fixed capacitance
of the leads and the package. The capacitance, Co, is specified at a frequency of 1 me
with zero applied bias. Since the typical capacitance of the PEP silicon diode is less
than 1 pf it is necessary to use a three terminal bridge configuration to achieve an
accurate measurement. The junction capacitance is inversely proportional to the square
root of the reverse voltage and increases linearly with temperature.
2. Rectification Efficiency. The rectification efficiency, Rt:, is defined as the ratio
of DC load voltage to peak rf input voltage to the detector circuit, measured with 2.0
volts rms, 100 me input to the circuit. Load resistance is 5K and the load capacitance
is 20 pf. The rectification efficiency is determined primarily by the conductance, reverse
recovery time, and capacitance, and provides an indication of the capabilities of the
diode as a high frequency detector.
3. Transient Thermal Resistance. The transient thermal resistance of a diode is
presented by a curve showing the instantaneous junction temperature as a function of
time with constant applied power. This curve permits a determination of the peak
junction temperature under any type of pulsed operation. By means of a simple
analytical procedure, described in Reference 2, this curve can be used to determine
the peak junction temperature under any type of transient operation and hence pro-
vides a valuable method of insuring the reliable operation of diodes in pulse circuits.
4. Forward Recovery Time. If a large forward current is suddenly applied to a
diode, the voltage across the diode will rise above its steady state value and then drop
rapidly, approaching the steady state value in approximately an exponential manner.
This effect is caused by the finite time required to establish the minority carrier density
on both sides of the junction. The forward recovery time is the time required for the
diode voltage to drop to a specified value after the application of a step of forward
current. The forward recovery time increases as the lifetime or the resistivity of the
semiconductor material is increased. For a given diode the forward recovery time
increases as the magnitude of the forward current step is increased, and decreases as
the forward current flowing prior to the current step is increased. If the amplitude of
the forward current step is sufficiently small the effect of the junction capacity will
predominate and prevent the diode voltage from overshooting its steady state value.
For most diodes, particularly the PEP silicon diodes, the forward recovery time is much
smaller than the reverse recovery time and can be neglected in most applications.
lal APPllED
VOLTAGE
·:1
...
_____
_
lb) DIODE v, --===---==-
VOLTAGE

:._________
C
le) DIODE
CURRENT

TYPICAL DIODE REVERSETRANSIENT WAVEFORMS

Figure17.3

284
 j

SILICON SIGNAL DIODES

5. Reverse Recovery Time. When a forward biased diode is subjected to a reverse

voltage step, a large reverse current will flow for a short time as a result of the stored
charge consisting of the minority carriers on both sides of the junction. The typical
voltage and current waveforms involved are shown in Figure 17.3. Initially, a current
1•. is flowing in the diode and a voltage VF appears across it. When the reverse voltage
step occurs at t =
0 a reverse current I,1 flows which is determined by the magnitude
of the applied voltage and the loop impedance of the circuit. At the same time the
forward voltage decreases by an amount approximately equal to (IF + I,1) Rs due to the
reversal of the current through the diode. The reverse current remains constant at I,1
for a time tn (the constant current phase) and then rapidly decreases, approaching the
d-c reverse current value. At the same time the diode voltage goes negative and
approaches the value of the applied reverse voltage.
The reverse recovery time of a diode, t,r, is specified as the time between the
application of reverse voltage and the point where the reverse current has dropped
to a specified value, I,2. The specification must also include the forward current, IF,
the initial reverse current, I,1, and the loop impedance of the test circuit. The specifi-
cation of the reverse recovery time of diodes is difficult to use for circuit design pur-
poses because the recovery time is given only for one arbitrary test circuit and bias
condition. Due to the wide variety of possible circuit arrangements and bias conditions
encountered in diode applications, it is impossible for the manufacturer to control and
specify the reverse recovery time corresponding to each special condition encountered.
10
I

5
\
\
2
~
\~ '
,......ta,
VS Ir1 /It

H°
'
H
----"4--- \

\
''\'
-\--
\
...
,,
0.5
\ \ \ r--....
. y ...........
\ '\
~"
\

\ \

\
'"
0.2 I\ \ \ i\ r------.....
~

r--.. r--....
\
~ '~ \ \
0.2

CURVEFORDETERMINING
T\ME UNDERVARIOUS
REVERSE
RECOVERY
DRIVECONDITIONS
"' 0.4
~
0.6
~
0.8
t/T
~ i\..
1.0 1.2

Figure 17.4
285
SILICON SIGNAL DIODES

IF
12 50 MA
~ 40 MA
30 MA
/ ~ ~/ 20MA
V
./ ~ v/
:::::::
/ v ... /
.,,,,,....
--: c::::
t::--- 10 MA

--
./
i-
_,.,,,,,. ~ ~

:::::
-- c:::: V
i---- i--
i---

-- ~
--
----
i--- ~

:::::
l.....-"

------ -i-- ..---

i-

i-- / ....
/

----
~

-
--- ---- --
i,..--

---
~

--
i---
i---
- ----
2

0
-50 -25 0 25 50 75 100 125 150
JUNCTIONTEMPERATURE-TJ-DEGREESCENTIGRADE

EFFECTIVELIFETIME OF PEP SILICON DIODES

VS. TEMPERATUREAND FORWARDCURRENT
Figure17.5

However, for most design requirements an accurate estimation of the reverse recovery
time can be obtained by use of a quantity called the effective lifetime, T, and the
ratio of the forward and reverse currents. Figure 17.4 can be used for this purpose
together with Figure 17.5 which gives the typical effective lifetime of the PEP silicon
diode as a function of temperature for various values of forward current.
The use of Figures 17.4 and 17.5 in estimating the reverse recovery time of a PEP
silicon diode can be best described by means of the following design example.
Problem: Estimate the typical recovery time to 5 ma reverse current (1112) when
the forward current is 20 ma (Iv) and the initial reverse current is 15 ma
(Ir1) at a temperature of 75°C.
Solution: Enter the left side of Figure 17.4 at Ir1/Ir 15/20 0.75 and follow= =
horizontally (dotted line) until the t. vs. I,1/Ir line is reached. From the
t/T scale on the horizontal axis, it is seen that t. 0. 31T. The tb portion =
of the curve is estimated by moving downward parallel to the general
contour lines until reaching the line corresponding to Ir2/Ir 5/20 = =
0.25. The total switching time is thus 0.44T".From Figure 17.5 the effec-
tive lifetime at Iv= 20 ma and T, = 75°C is 6.0 nsec, hence the calcu-
lated values are:
constant current phase t,. (0.31) (6.0) = 1.86 nsec. =
reverse recovery time trr =
(0.44) (6.0) 2.64 nsec. =
For additional material on the reverse recovery time of diodes see References 3 and 4.

286
 SILICON SIGNAL DIODES

DIODE ASSEMBLIES
The PEP silicon diodes are available in matched pairs and matched quads for use
in applications where close matching in the forward characteristics is required. These
units are sealed in small epoxy packages to preserve the identity of the diodes and
minimize temperature differentials between diodes. The diodes used in these assem-
blies have all the high performance capabilities of the standard PEP silicon diodes
and in addition are matched to within very close limits for VF over a range of forward
current fi:om 100 µa to 50 ma and over a range of temperature from -55°C to +12s 0 c.
These assemblies are used in discriminators, gating circuits, choppers, ring modula-
tors and ring demodulators where the highest performance and reliability are required.

REFERENCES
m Kvamme, E.F., "Controlled Conductance Applications," G-E Application Note 90.40.
12 > Gut.1:willer, F.W., Sylvan, T.P., "Power Semiconductor Ratings Under Transient and Intermittent
Loads," G-E Application Note 200.9.
<1 > Chen, C.H., "Predicting Reverse Recovery Time of High Speed Semiconductor Diodes," G-E
Application Note 90.36.
<oKo, W.H., "The Reverse Transient Behavior of Semiconductor Junction Diodes," IRE Trans. ED-8,
March 1961, pp. 123-131.

287
SEMICONDUCTOR
RELIABILITY

Of the many advantages which arise from the use of semiconductor devices in
place of vacuum tubes, probably the most fundamental has been their long, reliable
life expectancy. Early in semiconductor device development this was more anticipation
than realization; but, by now, average failure rates of less than 0.01 % per 1000 hours
have been demonstrated in actual usem and life tests of longer than 40,000 hours (see
Figure 18.9 - F and G) have shown that "wear-out" in semiconductors, if it actually
exists, does not occur in the normal useful life of most electronic equipments.
Reliability is a measure of how well a device or a system can be expected to satisfy
a set of performance requirements for a given period of time under a specified set of
operating conditions. To be exact, this measure is the probability of successful perfor-
mance. The basic reliability problem consists of two essentially different, but related,
subproblems. This fact is frequently overlooked in current reliability thinking. The
first, and by far the most important of the subproblems is that of designing, producing,
and applying the device so that it actually will have the required reliability. The
second subproblem, and the one which frequently receives all the attention, is the
measurement of the reliability. It is not implied that measuring reliability is not im-
portant; but it is necessary to realize that the measurement of reliability in itself does
not increase reliability. This difference becomes particularly important when the eco-
nomic feasibility of lot acceptance tests to demonstrate extremely low failure rates is
considered.
In both the achievement and measurement of reliability, there are major differences
between systems and devices. In general, the system or equipment has to perform a
somewhat narrowly defined function under a relatively narrow set of conditions for a
relatively fixed period of time. For devices such as semiconductors which are mass
produced, the ranges of applications, operating conditions, and required length of
life are extreme. One transistor type in one application may be employed as a small
signal i-f amplifier in a missile whose useful life is measured in minutes, and in another
application may be employed in an air conditioned well maintained computer in a
high level flip-flop where years of life are required. This diversity necessitates extreme
care in the design, production, and evaluation to assure that the device will provide
the required performance.
It is the purpose of this chapter to explain the factors which determine semicon-
ductor reliability, and the techniques used in its measurement and to illustrate these
with typical device reliability characteristics.

ACHIEVING RELIABILITY
The achievement of reliability can only be realized through the proper application
of devices which have been properly designed and properly 1>roduced. Any attempt to
make one or two of these elements bear all the burden will result in higher costs and
less than optimum performance. For example, placing excessive reliance on safety
factors in application will result in heavier, bulkier, and more costly equipment which
frequently will be slower in operation or be marginal in some other operational char-
acteristic. Similarly, in device design, the specifying of a critical process in order to

289
SEMICONDUCTORRELIABILITY

obtain high performance will be paid for by uncertain yield and reliability. One
aspect of the interdependence of these three factors in reliability which frequently is
not sufficiently appreciated is the importance of feedback, feedback from the users of
components to the producers and feedback from the production organization to the
design organization. Most manufacturers have quite tight feedback paths between
production and design. However, feedback from the "field" is generally much more
difficult. A characteristic of many General Electric semiconductor devices is the means
of permanent lot identification of each unit - which means that if at any time a unit
should fail or exhibit unusual behavior, production records can be analyzed to deter-
mine possible causes. As this type of feedback continues, "field" experience can be
factored into both production and design.

DESIGN FOR RELIABILITY

Mechanical Ruggedness
Mechanical ruggedness is a reliability must, not only for the end use but for the
handling necessary to incorporate the device into an equipment. Mechanical rugged-
ness is achieved in design through incorporation of rigid assemblies, low mass, low
moments of inertia, and through elimination of mechanical resonances in the normal
range of vibration and shock excitation.
Thermal Ruggedness
As important as mechanical ruggedness is thermal ruggedness. This is the ability
to withstand rapid and extreme changes in temperature - whether caused by internal
power dissipation or by external environmental changes. <11> The principles which are
followed to assure reliability here are
1. The use of materials with matched temperature coefficients of expansion, and
the use of hard solders to reduce the likelihood of metal fatigue
2. A low thermal resistance between junction and case to reduce thermal rise
under power dissipation
3. The use of matched coefficient oxide seals in the headers to maintain a hermetic
seal over wide temperature ranges. (Hard glasses and special metal alloys such
as Fernico, Kovar, or Rodar are used to make these seals.)

Surface Protection
Surface protection is one of the most critical factors in the design and production
of semiconductor devices. General Electric device designs make use of one of two
basic principles of surface protection - encapsulation in an inert atmosphere with a
getter to maintain a satisfactorily low partial pressure of moisture; and passivation
which is a process of deactivating and isolating the silicon or germanium surface with
a chemically bonded protective film which shields the active surface from the influence
of the gaseous environment and any contaminants which might come in contact with
the surface. The first of these - internal atmosphere control - provides stability by
initially establishing an internal atmosphere which gives satisfactory performance and
then maintaining this condition by means of the getter. The getter is a material whose
selective absorption characteristics have been chosen to provide maximum capacity
for the removal of water vapor. The actual internal gaseous environment and getter
must be selected specifically for each semiconductor design to optimize performance
and reliability.
Passivation protects the surface of the semiconductor device by deactivation and
by isolation. <3 > Deactivation is the satisfaction of the unsaturated bonds of the semi-

290
 SEMICONDUCTORRELIABILITY

conductor surface atoms by the formation of stable chemical bonds with a surface
protecting film. The satisfaction of these unsaturated bonds greatly reduces the effect
that electric fields have on the semiconductor behavior.
Isolation provides further stability by reducing the intensity of the electric fields
reaching the semiconductor from charges residing on the outer surface. The thicker
this passive layer or film, the greater the isolation. Furthermore, the passivation film
will reduce the field intensity at the outer surface caused by the voltage across the
junction depletion layer. This will reduce the tendency for surface contaminants to
ionize and thus lead to still further device stability. Even in the case of passivated
surfaces, the surrounding environment will exert some small influence and so for
maximum stability it is desirable to provide a hermetic encapsulation.
In the case of the controlled environment method of surface protection it is obvious
that hermetic encapsulation is essential. For these reasons, almost all transistors are
hermetically sealed. Matched coefficient oxide seals give maximum assurance of a
hermetic seal over wide temperature ranges. Although the use of copper leads and
compression seals reduces the likelihood of lead breakage under severe installation
conditions, it appreciably increases the danger of seal leakage and early failure
caused by the influx of moisture and other contaminants. The cap to header weld,
another important element of the seal, must be designed through proper shaping of
cap, header, and welding electrode to give further assurance of a hermetic seal while
eliminating the harmful effects of weld splash in internal contamination.
Post Fabrication Processing
The factors brought out so far have dealt with the construction of the device.
Certain elements of the design involve post fabrication processing. The most important
of these is the stabilization performed on each unit. This is usually a high temperature
bake for a period of days, the length of time depending on the device type.
The most important results of the high temperature bake is bringing the surface
and the internal environment into equilibrium. In the case of devices using internal
atmosphere control through getters, it is important to bring the internal surfaces of
the device, the getter, and the internal gas itself all into equilibrium. Even though
caps and headers may be prebaked at very high temperatures prior to fabrication,
there is a certain amount of moisture and other gases that will be gradually evolved
after fabrication. Furthermore, the getter will start acting on the gases in the unit as
soon as it is welded. It is important to complete these changes and reach equilibrium
prior to final testing so that the finished product will be stable. High temperature
baking will in most cases accomplish this in a matter of a few days or a week.
In the case of devices where surface protection is provided by passivation, the
stabilization bake is of much less importance. However, even well passivated units
responds to a small degree to changes in internal atmosphere. A high temperature bake
accelerates this process to give the ultimate in stability to the finished product.
Reduction of Critical Processing
One of the responsibilities of product design when considering reliability is to
reduce the critical nature of the manufacturing operation. When fabrication operations
are critical, the vigilance of inspectors and quality control personnel must be increased
and even then, some marginal units will slip through. By designing the product so
that normal production tolerances will not produce early failures, the likelihood of
marginal or poor units being delivered to the customer is greatly reduced. Poor units
. can then only be produced when the process is out of control and this situation can
be readily monitored by the quality control function.

291
SEMICONDUCTOR RELIABILITY

Many of the factors previously mentioned in connection with design for reliability
also are important in connection with reducing the critical nature of manufacturing.
For example, matched coefficient oxide seals are more easily produced without leaks
than are compression bonds, resistance welding of the cap to header seal produces a
more consistent seal than solder seals. The shaping of cap, header, and electrodes
reduces the probability of weld splash contaminating the surface, the use of hard
solders eliminates the need for fluxes and thus greatly reduces the chances of surface
contamination. Gettering and passivation reduce the criticalness of many steps in
production providing a major reduction in the probability of fabricating faulty units
which could fail in operation.

Examples of Reliable Design

Figures 2.8 through 2.11 show how these reliability design principles have been
incorporated into General Electric transistors.

PRODUCTION FOR RELIABILITY

Device reliability cannot be obtained through a design alone. The manufacturing
operations must be established and maintained to assure that the design is actually
followed - that is, the process must be kept in control. The most important factors
pertaining to this element of reliability are workmanship, materials, environment,
tools, screening, and quality control.

Workmanship
Of all these, workmanship in the broad sense is the most important since the skill
and attitude of every operator, maintenance man, inspector, and foreman contributes
to the overall quality. Even in those cases of high level mechanization where need
of human judgement and skill are greatly reduced in the direct fabrication steps, main-
tenance and control personnel, incoming material inspectors, and many others require
high levels of skill to achieve reliability in the product. Factors which contribute to a
high level of workmanship are morale, careful selection and training of personnel,
managerial attitude toward quality (for example in General Electric Semiconductor
Products Department, there are no piece rates; the emphasis is on making transistors
right rather than making them fast), and performance feedback. This last point will
be amplified in the section on quality control.

Materials
The quality of the materials going into the finished product can be maintained at
a high level through a combination of vendor control and incoming inspection. Vendor
control starts with an evaluation of the vendor's product and of his facilities for con-
sistently producing a high quality material. The second step is to maintain a rating
on his performance combining price, service, and quality. This affords a factual basis
for the selection of the best source for each material and a measure of the consistency
of performance.
Most materials, particularly the direct materials can be subjected to an incoming
inspection in the normal manner. A random sample of each lot can be taken and
tested for the required characteristics. Failure to meet the requirements is cause for
lot rejection. In those cases where screening is practical, failed lots may be screened
to eliminate the faulty material and then resubmitted.
There are certain materials where this normal method is not applicable. Such situ-
ations arise in connection with the ultra-pure water used for cleaning and with gases

292
 SEMICONDUCTOR RELIABILITY

used in flushing and capping. The most appropriate manner by which to control the
quality of these materials (in addition to adequate "vendor control") is to monitor the
appropriate characteristics as the materials arc used. This can be done in most cases
by automatic recording monitors which have out-of-range warning indicators which
forcibly bring to the attention of the production personnel that the material is out of
limits. Typical characteristics which may be monitored are gas purity, dew point, and
water resistivity.

Environment
One of the most important factors in the manufacture of reliable semiconductors
is the manufacturing atmospheric conditions, particularly humidity and dust. To
reduce the effects of these factors to a minimum, snow-white and dry-box areas should
be used for most operations, especially those after the device has been etched and
cleaned.
The snow-white areas are rooms within rooms designed for the minimum tendency
to collect dust and maximum ability to be cleaned. All air entering the areas should
be filtered and a positive pressure should be maintained in the snow-white room so
that any airflow is outward. All entrances into the rooms should have special shoe
cleaning facilities. These areas should be vacuum cleaned regularly to remove what
dust inevitably will leak in. To assure that the snow-white facilities are in order, dust
count, temperature, and relative humidity should be monitored and recorded continu-
ously with provisions for out-of-limits warning signals.
The dry-box is a further means of controlling the atmosphere in which manufac-
turing operations are performed. This technique is used where relative humidities are
required which would be detrimental to operator health or where inert cover gases
are required. The dry-box is an enclosed chamber completely sealed with trap doors
for loading and unloading, and built in rubber arms for the operators to use for han-
dling the devices.

Tools
Another important factor in manufacturing reliable semiconductor devices is the
tooling - both design and maintenance. Important characteristics of the tooling are
that it requires little or no judgement on the part of the operator, that it be able to
be set up readily and repeatably, and that it facilitate preventative maintenance.

In-Process Inspection and Control

In-line control and inspection is the means that should be employed to assure that
the product at each stage of production is within specification. This can be accom-
plished by monitoring the operating conditions of the tools such as fuzing tempera-
tures, etch currents, by monitoring the characteristics of the water and gases being
used and the environmental atmosphere as have been described, and by inspecting
the product itself, electrically, mechanically, and visually. The importance of this
aspect of reliable production cannot be over emphasized since this is the point where
corrective action is most rapidly and effectively applied. This is the point where
quality control can prevent poor production rather than reject it. Careful records of
operators, materials, and machine maintenance will permit pinpointing and elimina-
tion of trouble spots. All reliability problems will not show up as defects detectable
by these means; however, long experience has shown that an increase in the occur-
rence of those defects which can be thus detected are generally associated with a
decrease in reliability.

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Screening
However, as the mechanisms of failure for each type of semiconductor device
become known, means can be developed to screen out potential early failures. It must
be emphasized that no two types of transistors necessarily have the same failure
mechanisms, that no two products made by two different manufacturers, even though
the same type, necessarily have the same failure mechanisms, and that no two products
made at different times, even though the same type and made by the same manufac-
turer, necessarily have the same failure mechanisms. Therefore, reliability screening
procedures must be determined separately for each product for each manufacturer
for each period of time. The screening techniques generally are combinations of
mechanical and environmental stresses utilizing device electrical parameter pedorm-
ance as criteria of quality. Almost all semiconductor products manufactured have
passed through a reliability screen to some extent, but those products for use where
the ultimate in reliability is required have very extensive screens. This subject will be
covered in detail in a later section.
Finished Product Quality Appraisal
It is not enough to set up a production line that can make a reliable product. It is
necessary to provide some means of assuring that it has made a reliable product. That
is one of the purposes of the quality control function in most semiconductor device
manufacturing operations. This can be accomplished by properly sampling each pro-
duction lot. The production lot may be defined as anything from a part of a day's
production to a full month's production, but is most often considered as a week's pro-
duction. The samples should be tested for conformance to the specified electrical,
dimensional, and workmanship characteristics. In addition, they should be subjected
to the specified mechanical and environmental and life test stresses. Certain of these
sample tests should be restrictive, that is, if the sample fails the established criteria the
lot should be rejected. Others of these tests may be for informational purposes only,
used for optimizing the line pedormance or ascertaining the degree of safety factor
between the product capabilities and the specification requirements.
A frequent characteristic of such testing is the use of failure criteria which are
unrealistically tight compared to the normal use requirements (such as allowing only
small percentage shift of the transistor current gain, or a failure definition of leakage
current one or two orders of magnitude less than which would cause ordinary circuits
to fail). This is done to provide a more sensitive control of production line performance.
Quality Control
In most semiconductor manufacturing operations the quality control function not
only carries out the end-of-line acceptance tests outlined above, but audits the many
inspection and control operations in the incoming material and in-process areas as
well, to make certain that they are being properly carried out. This provides an inte-
grating means of tying together the great number of reliability factors important in
production. A feature of General Electric transistors which makes this integration
more effective is the date coding of each unit. Each transistor has embossed in its cap,
just prior to main seal weld, a symbol which permanently identifies the time of pro-
duction. This identification can be used to relate reliability problems with the many
variables which are monitored at the various points in production. As has been pre-
viously mentioned this can also help to identify causes of failure in the field.
APPLICATION FOR RELIABILITY
A pedect semiconductor device can exhibit very poor reliability if it is misapplied.

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Reliable performance in equipment can only be achieved by selecting a device whose

characteristics match those required by the function to be performed. This matching
starts with the function to be performed and includes consideration of the environ-
mental conditions and length of time of operation, the basic circuit configuration, the
operating biases, the circuit margins allowed for, and the characteristics of the device
itself. It is obvious that this matching process involves many interacting steps. Thus,
to optimize the overall reliability requires much cut and try. For example, too much
conservatism in circuit margins or derating on the device may make the individual
sections of the equipment very reliable; but because the performance of the individual
sections has been reduced, more sections are required resulting in an equipment with
less overall reliability. (II)
Function
The first step in applying semiconductors for reliable performance is to determine
the circuit function to be performed. In many cases this is merely a matter of enumer-
ating certain input, output, and transfer functions. However, in general, and for truly
optimum equipment design, this step is part of the overall systems reliability design.
There ate usually many ways of solving a systems problems involving significantly
different performance characteristics of semiconductors with resulting significantly
different reliabilities. Control systems can be all electronic or they can be electro-
mechanical. The requirements on the semiconductor devices are much different and so
might be the overall reliability. A communications system can be strictly analogue or
it can make use of pulse code modulation. Again the requirements on the semicon-
ductors and the overall reliability will differ drastically. The application of semi-
conductor devices for optimum reliability· starts with the recognition of their particular
characteristics and the incorporation of this into the overall system design.
Time
The second matching step _has to do with time. The length of time that the equip-
ment must perform may in many cases be the least controllable of the matching factors;
however, frequently the length of time that a portion of the equipment must operate
can be adjusted to improve a match. The element of time enters, in this manner, into
the question of whether the equipment is subject to preventative maintenance, is
reparable, or is a throw-away. Frequently when designing equipment from which very
long life is expected, appreciable improvement in reliability can be achieved by utiliza-
tion of the throw-away design since, if potting of the equipment or subassemblies is
used, much better thermal characteristics can be obtained in the packaging. This, as
will be shown below, will be beneficial. Furthermore, ability to withstand mechanical
abuse will be greatly improved. The throw-away design will also frequently reduce
the number of sockets and connectors which further improves overall reliability.
Environmental Conditions
Some portions of the environmental conditions in which the semiconductor device
will be required to function are sometimes beyond the control of the equipment
designer. Generally, however, he has control over most conditions over at least a lim-
ited range. Generally speaking the ruggedness of semiconductor products minimizes the
concern regarding the mechanical conditions which might be encountered in equipment.
However, occasionally, it is found that unusual combinations of equipment packaging
arrangements may set up resonances which will cause excessive stress in shock or vibra-
tion. These must be guarded against. Furthermore, there are some special application
where such environments as high level acoustic noise or nuclear radiation are to be
encountered. In these cases, particular attention must be given to selection of devices

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best able to withstand these stresses as well as to protective measures which may be
taken to reduce the level of the stresses.
The most important environmental factors which must be considered in reliability
design are associated with temperature. Over the useful operating range, the higher
the temperature the higher the failure rate is a safe rule. Furthermore, temperature
cycling will tend to increase the failure rate relative to temperatures within the cycling
range. (This will be discussed in detail in the section on failure mechanisms.) Once
again, therefore, it is necessary to balance requirements on the system such as ambient
temperature control or cooling against the improvement in failure rates to be obtained.
Circuit Configuration
The recommendations so far have dealt primarily with the impact of the device on
the system. Let us now consider the circuit design itself. A basic concept that should
be followed for the design of reliable equipment is to make use of circuit configura-
tions which have prime dependence upon the most stable semiconductor device char-
acteristics and least dependence upon those characteristics which are least stable.
Those transistor electrical characteristics which are most stable for most transistor
types, both over temperature and time, are common base forward current gain (hrb,
hvo), the common base breakdown voltage (BVceo), the input V-1 characteristic - either
common base or common emitter (V•:n, V ov.),and the output V-1 characteristic in the
"on" condition - either common base or common emitter (Vcn1KAT), VcEcKn1).The least
stable characteristics are the leakage currents (Icno, lcF.o,Ic1m,etc.), the common emitter
breakdown voltage (BVcF.o),and the common emitter forward current gain (h, .., hFE).
Consideration of this list points to the advantage of digital or on-off circuits which
are primarily dependent upon the Vn•: and VcE1KAT> and must only be designed for a
minimum value of hFEand a maximum value of leakage current. Where analog circuits
are required, biasing methods which place most emphasis on hFn and a minimum on
hvt: and Icoo should be used. (See Chapter 7 on Biasing.) Feedback can frequently be
advantageously employed, both within a single stage and around several stages, to
minimize the effect of current gain variations and essentially reduce the requirement
on this parameter to being above some minimum value.
Operating Biases
A second circuit consideration for reliability is the choice of operating bias condi-
tions. This is a very confused and uncertain area for two reasons:
1. The effect of voltage, current, power (temperature gradient within the device),
and junction temperature on reliability depend considerably on the failure
mechanisms to which the various devices may be susceptible
2. The ratings, which are usually used as the reference point for operating condi-
tions for any particular device, are not consistently established relative to reli-
ability either from device to device, manufacturer to manufacturer, or even
stress to stress. It is obvious from this that blanket derating rules are of little
value.
If we look at rating practices for the individual stresses we would find that
1. Voltage ratings usually are established as the breakdown voltage in one or more
configurations leaving no margin of safety (furthermore, in some cases BVct:Kor
BVcE11,which are always larger than BVct:o, are specified and thus the ratings
are not always applicable to all circuit conditions)
2. Maximum collector current is sometimes rated at a level at which the forward
current gain drops to a uselessly low level, completely unrelated to reliability

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3. Storage temperature is usually rated at the low end on the basis of what the
customer would like to see (-65°C or· -55°C), but sometimes at the lowest
value where internal moisture condensation will not cause malfunction. At the
upper end it is usually rated on the basis of life tests although the expected
failure level may vary widely.
4. Power is almost always rated on the basis of life test but with a wide range of
expected failure level.
Because of the variation in susceptibility of different failure mechanisms to the
different stresses, because of the variations of the existence of different failure mecha-
nisms in different device types, and because of the inconsistencies existing in the estab-
lishment of device ratings, derating should be applied with discrimination.
Caution should be applied in the matter of transients. Even though the average
voltage, or the average current, or the average power are well within ratings, extreme
care should be exercised to insure that voltage spikes (particularly important in con-
nection with inductive loads) and excessive peak currents do not occur. Either of these
can cause local hot spot temperatures which when repeated over a period of time can
cause irreversible shift of parameters and ultimately outright failure.
Considering derating generally, there are several ways in which it can improve
equipment reliability. If we assume we are concerned only in the area well away from
voltage breakdown and hot spots due to excessive current, then we can say, further,
that reducing the voltage while increasing the current has the advantages of lowering
the impedance level so that surface effects are of much less importance.
Keeping the total power low will keep the junction temperature to a minimum and
thus reduce the total junction temperature swing for which the circuit must be de-
signed. These advantages will exist independent of improvement in failure rates which
in the usual range of conditions will decrease with a decrease in stress.

Circuit Margins
A third factor in the design of reliable circuits involves circuit margins - the limit-
ing values of critical parameters at which the circuit will cease to perform satisfac-
torily. The wider the limit, obviously, the less likelihood there is that a parameter will
exceed the limit and cause an equipment failure. On the other hand, wider limits
usually result in lower performance which may decrease overall equipment reliability
through a smaller system safety factor or through added complexity of more stages.
An optimum must be established in determination of circuit margins.
A variation of this same problem of optimization has to do with the circuit per-
formance considering all components simultaneously. One approach has been to assume
that all components have their limit values in the worst direction simultaneously and
design for adequate performance on this basis. Since the likelihood of this extreme
combination happe9ing in practice is infinitesimal, it is clear that this is too conserva-
tive for circuit reliability and may result in a less than optimum reliability design for
the equipment and the system. Since the actual distribution of parameter values in
temperature and time are rarely if ever normally distributed, the formal regression
techniques cannot be applied. However, techniques have been developed which make
more realistic assumptions than the "worst case" design. 161

Device Selection
This section describes the selection of the proper device for the application. The
first step is to determine which devices have the electrical characteristics required. An

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important rule to be followed is not to permit any parameter to have a critical role in
circuit performance unless it is controlled by the specification. Reliance on typical,
nominal range, or the observed distribution of small samples may be found to have
been misplaced when production quantities are ordered.
If the distribution of a parameter is important it should also be specified by such
means as a median control or by the use of dual min-max limits such that at least
x percent fall within a tight set of limits and y percent fall within a looser set of limits
(y>x). An example for hFE might be that 80% fall between 45 and 74 and that 99%
fall within 30 and 90. The importance of specifying all critical parameters has been
mentioned. It is equally important that parameters which are not important not be
specified since this will only increase cost and reduce availability.
The selection of a device must also he based on its anticipated performance under
the anticipated operating conditions. The first guide to this is the set of ratings for
each device. However, it has been clearly pointed out that ratings are not at all con-
sistent. Therefore, prior to even a preliminary selection, reliability data should be
obtained. Since the user rarely, if ever, has time or money to obtain this information
from his own testing, the device manufacturer must be able to furnish it. An evaluation
of this data should be performed considering the life test conditions and end of life
limits vs. the operating conditions and circuit margins anticipated in the circuit design.
The derating factors which are to be used here, of course, should be based on as much
factual data as the device supplier and the equipment designer have available to them
and should consider the failure mechanisms to which the device is susceptible. Further-
more, mechanical and environmental test data ·should be obtained to ascertain that the
device has sufficient safety factor to withstand those stresses to be encountered in
the equipment.
It has been mentioned previously that the matching of device to function is a trial
and error process since each step influences every other step. Thus, having made the
first selection based on the above considerations the process should be repeated, re-
evaluating each compromise in the light of succeeding decisions.
Manufacturing Precautions
An extremely important aspect of application which has not previously been men-
tioned does not have to do with the equipment design, but its manufacture. Some of
the most severe abuse that a semiconductor device encounters is received in the
handling during acceptance, installation, and testing in the users plant. Semiconductor
devices are mechanically rugged but the accelerations experienced when they are
dropped even a little distance onto a hard surface can run into the thousands of G's
and can harm units which are far stronger than necessary for the actual use conditions.
Handling procedures for semiconductor devices should include provisions for prevent-
ing such drops and, in areas where the chances are still high, for cushioning the fall
(such as foam rubber on a bench top where considerable handling is carried out).
Another means by which mechanical damage sometimes can be inflicted is the
cutting of leads with a V shape cutting edge. At the time of separation of the portions
of the leads, there is a high axial acceleration which is transmitted up the leads of the
device proper. Tools for cutting leads should have a pure shearing action. Ideally
there are no axial forces - in practice, very little. Machine shears are usually of this
design. Cutting pliers which have one face vertical should be used for hand work;
the vertical face of the pliers should face the semiconductor device.
Ultrasonic cleaning in the past has caused much trouble. When high energy ultra-
sonic vibrations are applied to semiconductors in the usual cleaning apparatus, the

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probability is very high that a resonant frequency within the device will be excited.
The accelerations which are then induced in the resonant portion of the device may be
tens or even hundreds of times higher than the acceleration at the point of contact to
the cleaning bath. Precautions which should be taken are to use the lowest level of
excitation that provides satisfactory cleaning (3 psi average has been found satisfactory
in many applications), and to monitor the pressure level over all the useful area of the
bath since in most installations there are wide variations from point to point and time
to time. It is also beneficial to use mass loading of the circuit board by the holding
fixture to reduce the amount of acceleration transmitted to the device, to select an
operating frequency as far removed as possible from any important internal resonant
frequencies of the components on the circuit board, and to provide maximum stabili-
zation of the exciter.
Another important manufacturing step which requires care is soldering. Damage
to semiconductor devices by machine soldering is no problem since the temperatures
and times which provide satisfactory soldering will not raise the internal temperatures
above safe values. However, with hand soldering irons, particular care must be taken
since the soldering iron temperature is much higher than most semiconductors can
withstand. Precautions must be taken to prevent the device from coming to equilibrium
with the soldering iron. This can be done by holding the device lead with a pair of
pliers between the body and the point of application of the soldering iron and by
keeping the soldering time to a minimum.
In handling semiconductors particular attention should be given to minimizing
lead bending near the body of the device. Two types of damage may be caused -
fatiguing of the leads themselves and cracking of the glass seal. Repeated insertion of
devices into test equipment sockets, lead straightening, and mounting in the final
equipment are operations which should be particularly guarded in this respect.
One of the most insidious forms of damage that devices suffer is that from tran-
sients in test equipment. These transients can cause instantaneous failure or they may
cause performance degradation. If the transient occurs at the beginning of the meas-
urement cycle, the device will appear as a failure or as having changed characteristics
from previous measurements. If, on the other hand, the transient occurs at the end of
the measurement, the damage may not be detected until further measuremnts are
made or until the device is installed in an equipment. Whenever possible, all device
leads should be short circuited during test equipment function switching, during card
or tape punching (for automatic readout equipments), and at the time of application
of biases.

MEASURINGRELIABILITY
The previous section was devoted to the achievement of reliability; this section
will present information on how reliability can be measured.
The measurement of reliability can only be made, in the strict sense, by observing
the performance of devices of interest in the finished equipment in actual use. For
most purposes this is, of course, impractical as the information would be available
too late to do anything if performance were unsatisfactory. Therefore, measurement of
reliability must be carried out in some other way - but always it should relate to the
ultimate measurement, performance in the finished equipment in actual use. How and
when the measurements should be made depends upon what specific objectives are
most important. Short of the final use test, the most appropriate method of measure-
ment would be by simulated use conditions in actual circuits and for the length of time

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that operation is required. This is still not practical for many purposes, particularly
from the standpoint of the semiconductor device manufacturer. He must measure the
reliability of his products when he doesn't even know in what circuits they will be
used and when he only knows generally what the operating conditions will be.
The device manufacturer has three reasons for measuring reliability. He needs a
knowledge of this characteristic for the control of his production line as it is just as
important that he knows what the product failure rate is as that he know the produc-
tion line yield. Since almost all vendor-buyer contracts have either an explicit or an
implicit reliability requirement for lot acceptance, measurements must be made to
determine eligibility for product shipment. Finally, circuit and systems designers need
information on levels of reliability as a function of time, as a function of stress level,
and as a function of circuit margins. Reliability measurements made in standard life
test racks will not provide exact information but will give strong guidance for those
who must convert this information into design decisions.

MEASUREMENTOF RELIABILITY FOR APPLICATIONSGUIDANCE

Measurement of this purpose is best done by attributes since an equipment de-
signer is primarily interested in whether a circuit will work or not and device stability,
in itself, is usually not significant. The practicality of this measurement depends upon
the required reliability. In those cases where failure rates of the order of 0.001 % per
1000 hours are required, the sample sizes become so large that it is only in the most
unusual circumstances that such measurements can be made.* A practical factor
should be noted here; the measurement, testing and handling errors in even well de-
signed and highly supervised measurement systems is at or above this level so that
the problems of measurement at these degrees of reliability are more than just sample
size. On a practical basis, reliability at the level of 0.001 % cannot be measured but
must be estimated from data taken at higher stress levels.
At lower levels of reliability (failure rates in the order of 0.1 % ) direct measurement
becomes feasible, though expensive. For purposes of guidance to equipment designers
it is not necessary to demonstrate this on a lot by lot basis but only as an average over
a period of time. Thus long term (six months to one year) tests can be performed in
which a small sample is put on test each production period. The results can be com-
bined to give an average estimated failure rate for the particular product. If these
small samples are put on test each period, at several stress levels (power, voltage,
current, temperature), it is possible to perform a statistical regression analysis which
will determine the relationship between failure rate and stress level. The data can be
analyzed to determine, at each stress level what the relationship is between failure
rate and the values of the critical parameters which are called failure. Similarly, the
occurrence of failure in time can be analyzed to determine the form of the failure
distribution.
In using this information, the circuit and systems designers must recognize that
there are some factors which must be considered in relating the life test failure rates
to in-use failure rates. Some of these life test factors are
1. Measurement errors on life tests
2. Test equipment failures which degrade units (oscillations on life racks, tran-
sients in measurement equipment)
•For example, with a sample of 230,000 trnnsistors operating for 1000 hours, no failures could he
allowed for a 90% confidence estimate of 0.001 % failun• rates; if one failure wt•re to he allowed,
the sample size would have to he 390,000. On the assumption of n constant failure rate, for 10,000
hours - about 15 months - one-tenth the snmple size would he required. For a decreasing failure
rate, which most devices exhibit, the reduction in sample size would not he as great.

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 SEMICONDUCTOR RELIABILITY

3. Usually the definition of failure is tighter than the value of the parameter
which would really cause malfunction
4. Usually the stresses - power, voltage, etc. - are more severe than in actual
equipment
5. Whereas in actual application there is a significant probability that, if a
parameter degrades, the other components in the circuit or in the system will
have enough margin of performance to compensate for it, in life testing no
compensation is considered.
To summarize, what is needed for measurement of reliability for applications
guidance are long term, low stress, multi-level life tests spread out over a large pro-
duction period. The data thus gathered must be analyzed (by attributes) to obtain the
most possible information relating failure rate to stress level, definition of failure,
and time.

MEASUREMENTOF RELIABILITY FOR ACCEPTANCE

In almost every vendor-buyer contract there is an explicit or implicit requirement
that the product have some acceptable level of reliability. Reliability measurement
for this reason has considerably different requirements from that for applications
guidance. The purpose of this measurement is to provide assurance that the reliability
of the lot in question is not significantly poorer than that agreed to by the two parties.
To be useful for lot acceptance, measurement must be made on each production (or
shipping) lot, it must be performed in a reasonably short time (1000 hours is the cur-
rently accepted time), the stress conditions must result in failures similar to those
which occur in use, and the results are most readily used if the measurement is in
terms of attributes (failures vs. survivors).
It is well known that the sensitivity of an attribute sampling plan is dependent
upon the number of failures which on the average will be observed. By sensitivity is
meant the ability to differentiate between lots having average reliability and those
that are much worse - or much better. There are only a limited number of ways in
which the number of expected failures can be increased: increase time on test, increase
sample sizes, tighten definition of failure, increase stress levels, and make use of
product history.
The length of time on test is limited by factors of cost of inventory and logistics,
1000 hours appears to be a practical maximum with a need to reduce it. Sample sizes
have been previously discussed; for low failure rate levels the required sample sizes
are very large and costly. Tight definitions of failure will produce more failures; how-
ever, unless the failures produced correlate with failures to looser definitions actually
important in the equipment, the test is worthless. The limit in this matter is reached
when measurement errors produce an appreciable portion of the failures. Stress levels
can also be made high. Here again, the failures produced must correlate with failures
occurring in actual use conditions. At any stress level where the predominant failure
mechanism differs from that at use conditions the results of tests at the high stress
conditions will not be meaningful. The final method listed, used of product history,
makes use of the premise that, if a production line is in continuous operation and is in
control, the lot to lot variations will be small and that the main concern is with slower
variations. There are many methods of using this principle. The simplest is to accept
each lot based on the performance of it and some predetermined number of preceding
lots. Other methods make use of sequential sampling or other continuous sampling

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techniques but the broad principle is the same. One safeguard required in using
product history is assurance of production homogeneity.
In practice, acceptance tests are designed by compromising on these five factors.
Expected failure rates are set in the range of 0.1 % to 10% in 1000 hours by selection
of test conditions and definition of failure. Recently, use of product history has been
incorporated for the lower failure rates to reduce testing costs. One practical method
which has been employed to reduce testing costs for small lots without sacrificing
reliability assurance has been the establishment of a Bonded Warehouse. Instead of
performing life test and mechanical and environmental tests for each purchase order
of 10 or 100 or even 1000 units to a particular specification, large lots, determined by
production considerations, are accepted or rejected based on a single sample. Tests
are performed under the surveillance of a government inspector or other surveillance
agency as appropriate. Accepted lots are placed in a separate segregated warehouse.
Shipments are then made to the particular specification directly to the customer. The
customer receives the test report if requested.
MEASUREMENTOF RELIABILITY FOR CONTROL
This type of reliability measurement has a lot in common with measurement for
acceptance. It must be performed on a lot basis (production lot), to be effective the
results must be known in a very short time, and the stress conditions should be care-
fully tailored to the prevalent failure mechanisms so that the most physically significant
conclusions can be reached. In the case of measurement for control, attribute analysis
is not necessary since the main requirement is to be able to ascertain whether the
product reliability is remaining constant, improving, or degrading. Direction and rate
of change of the parameter, rather than magnitude, is important.
PAST PRACTICE,FUTURE TRENDS
In the past the three -objectives of measurement of reliability have usually been
combined into a test most closely related to the acceptance requirements with test
conditions selected to protect the maximum ratings. This, of course, did not satisfy
the control requirement because the time required for decision (125 hours for first
read-out and 1000 hours for final decision} was too long for useful line control. The
average number of failures usually was 0, l, or 2 which meant that product reliability
could change radically without showing as a significant change in the test results, and
the tests were general purpose tests which were not specifically related to the prevail-
ing failure mechanism. From the standpoint .of application guidance, the test was not
long enough (10,000 to 50,000 hours would be more reasonable), the stress levels were
too high (users couldn't live with, in general, the failure rates expected at these levels),
and the test conditions were not selected so as to permit regression analysis to relate
failure rate to stress.
The trend for future measurement of reliability is to separate the three objectives,
or at least use two sets of tests in place of one. Each of these would be optimized to
achieve its particular objectives. The one set of tests would be for acceptance and
control with test conditions selecte<;lto highlight the most important failure mecha-
nisms. The analysis techniques and criteria of performance would be chosen as either
attribute or variables, dependent upon the typical device performance, so as to max-
imize the sensitivity of the test to product change. The duration would be chosen to
be one or at most a few days. The second set of tests would be directed to the prob-
lems of the user, optimized to provide application guidance. The form would be a
small scale response surface (multi-level) test designed for maximum analysis efficiency.
The stress levels would range from full rating downward. Small samples would be put

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on test from each production interval and continued on for an extensive period of time.
Analysis would be performed periodically (such as every six months).
This approach to the reliability measurement problem would result in the manu-
facture of more reliable equipments because of the improved feedback for control of
device manufacture and because of the improved guidance provided to circuit and
systems designers.

FAILURE MECHANISMS
Frequently in the preceding discussion reference has been made to failure mecha-
nisms, the physical and chemical processes which cause semiconductor devices to fail.
An understanding of failure mechanisms is essential for the design, production, and
application of semiconductors if the maximum reliability is to be obtained. Figure
18.1 shows the major failure mechanisms which affect semiconductor devices and also
shows the stresses which are most likely to indicate their presence in a device.

. TEMPERATURE ELECTRICAL MISCELLANEOUS

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• •
STRUCTURALFLAWS
-WEAKPIUITS • • • • • • •
-WEAK CONNECTIONS
• • • • • • • • •
-LOOSE PI\RTICLES
• • • •
-THERMAL FATIGUE
• • •
ENCAPSULATIONFLAWS
• • • • • • •
INTERNAL CONTAMINANTS
-ENTRAPPED FOREIGNGASES • •
-OUTGASSING
• •
-ENTRAPPED IONIZADLE
CONTAMINANTS • •
- BASE liANOAITY
CARRIERTRAPPING • •
•IONIC CONDUCTION
• • • • •
-CORROSION

MATERIALELECTRICALFLAWS
• • • •
-JUNCTION IMPERFECTION • • •
METALDIFFUSION
SUSCEPTABILITYTO
• •
RADIATION •
FAILURE MECHANISMSAND ASSOCIATEDSTRESSES
Figure18.1
STRUCTURALFLAWS
The Structural Flaws classification includes weak parts such as cracked pellets and
nicked base or emitter leads, weak connections such as poor base lead welds, loose
particles either conducting or non-conducting, and thermal fatigue. The failures in-
- eluded in this group may be due to design weakness, to production faults, or to
misapplication. The weak parts and connections and loose particles terms are self
explanatory. These can best be stimulated and detected by monitoring the device in
an operating circuit either under shock or in vibration. The latter would be particu-
larly effective if run at a resonant frequency for that portion of the device which is
weakest. This is not easy to do, however, in most devices because of the high resonant
frequencies involved, therefore a shock test is preferred. For applications encounter-
ing extreme levels of mechanical stress, static force (centrifuge) may be the only means

303
SEMICONDUCTOR RELIABILITY

of uncovering weak parts or connections. Thermal stresses frequently will show up

these faults through mechanical stresses and strains established by differential thermal
expansion. Applied power may similarly be useful because of the thermal gradients
set up.
Thermal Fatigue
Thermal fatigue has been covered under Achieving Reliability. m The most impor-
tant requirement of the stresses to be used to detect faults of this type is that the
internal temperature of the device change rapidly. This change may be brought about
by external means or by internal power dissipation. The latter is preferred.
Since the number of cycles required to show failure may be quite large, the dura-
tion of each cycle should be as short as possible. Frequently a five or six minute cycle
can be used. Depending upon construction, the parameter which is most sensitive to
failure may be 811 (thermal resistance), hFt: (current gain), or Vci-:1~AT>· In general, the
last is the most useful.

ENCAPSULATIONFLAWS
The second major classification of failure mechanisms is encapsulation fiaws. These
may consist of poor cap welds~ cracked lead feed-throughs, permeability of plastic
encapsulant, or imperfect passivation. The primary way in which these flaws may affect
device performance is through the effect that moisture and oxygen which may leak in
have on the device surface performance (see Figure 18.2).m Other gases which might
penetrate may affect device performance but the fact that these two are so universally
present gives them prime position. Since the parameters which are most affected by
the surface changes are leakage current (Icao is generally most important) and common
emitter current gain (hFt: or h,.), these are usually monitored as indicators of the
presence of this class of failure mechanism. However, other specialized measurements
are required to pin point the actual mechanism as being a particular type within
this class.
Leak Detection
Humidity cycles (such as found in MIL-STD-202) and detergent pressure bomb
tests are useful to detect flaws of this nature regardless of the type of construction.
However, for certain types of construction, there are more sensitive (and more quanti-
tative) measurement methods. m The best known is the Radiffo* which makes use of
krypton 85 as a tracer gas. It is claimed that this is sensitive down to a leak rate of
10-13 cc/sec at standard temperature and pressure. However, in production, testing
time limits the useful sensitivity to about 10-11 cc/sec. There are certain other limita-
tions. The device must not retain any radioactivity when there are no leaks (this rules
out most potted devices); if there are very large leaks in the hermetic enclosure, the
tracer gas which has been forced in during exposure will escape prior to measurement
and the very bad will appear good. This situation does not exist if there is a material
within the hermetic seal which will retain any tracer gas which is forced in. In the
majority of General Electric' s gettered products, this is the case. Thus, General Electric
is able to use Radiffo for 100% screening of most of its products - detecting gross
leakers as well as marginal seals. For those cases where it does not detect gross leakers,
Radiffo must be supplemented by a detergent pressure bomb test using Ic,m, Ifmo, or
junction to cap leakage current as a detector of moisture penetration. This supple-
mentary test has a sensitivity which overlaps the Radiffo sensitivity.
•Manufactured by the Consolidated Electrodynamics Corporation, Analytic and Control Division,
Pasadena, California.

304
.r
SEMICONDUCTOR RELIABILITY

CONDUCTIONCAUSEDBY MOBILE SURFACE

Iceo CHARGES,CURRENT DOES NOT SATURATE

Vee
PNP GERMANIUMTRANSISTORWITH EXCESSIVE MOISTURE

11
Iceo PRESENCEOF AN N+SURFACERESULTSIN
LOW CARRIERGENERATION,CURRENT
SATURATES.

Vee

PNP GERMANIUMTRANSISTORWITH SLIGHT MOISTURE

PRESENCEOF A"P"SURFACE RESULTSIN INCREASED

11
JUNCTION AREA, PARTIALLY PINCHEDOFF" BY
LEAKAGE CURRENT THROUGHTHE HIGHRESISTANCE
Iceo P INVERSIONREGION,AS VOLTAGE IS INCREASED,
LESS IS MPINCHEDOFF" AND LEAKAGE CURRENT
INCREASES.

Vee
PNP GERMANIUMTRANSISTORWITH EXCESSIVE OXYGEN

Iceo

RELATIVE HUMIDITY
LEAKAGE CURRENTAS FUNCTIONOF RELATIVE HUMIDITY

INVERSION LAYERS AND THEIR EFFECTS ON

JUNCTION LEAKAGECURRENT
Figure18.2

A caution should be expressed here that detergent pressure bomb is not a satis-
factory method of leak detection when grease or oil is used to provide temporary
protection to the junction.
Two other methods of leak detection that have been used for hermetically sealed
devices make use of helium. In one method helium is sealed into the unit at the time
of encapsulation and then the units are tested for leakage of helium from the inside
of the unit. The second method is a form of pressure bomb. The units are subjected
to a helium environment at high pressure. If leaks exist some helium will be forced in.
Then the units are tested for leakage of helium from the inside of the unit. The sensi-
tivity of this method is reportedly about 10-h cc/sec standard. Both of these methods
suffer from the weakness that gross leaks will tend to release helium before the sensing
instrument can be applied and so gross leakers will not be detected. Thus something
similar to detergent pressure bomb is required here also.

305
SEMICONDUCTORRELIABILITY

In some unusual circumstances, stresses such as corrosion (salt spray) or abrasion

(sand or dust) may cause failures because of inadequate or faulty encapsulation.
Chipped paint which allows corrosion of the cap to occur is the only form of this which
is common and this rarely proceeds to the point where device failure occurs. Special
requirements should be given special consideration in these matters.

INTERNAL CONTAMINANTS
One of the most important of the classifications of failures mechanisms is that of
internal contaminants. They can be roughly classified as moisture, other foreign gases,
and ionizable materials. They affect device operation through the induction of inver-
sion layers in the semiconductor material itself, through modification of the surface
oxides which may alter recombination center densities and rates of recombination,
through irregularities at the junctions themselves, and through ordinary surface
conduction.
Entrapped Foreign Gases
One form of failure mechanism of this general classification is that of entrapped
foreign gases. This is of most importance in greased units since the grease will protect
the junction for a time. Thus, at the time of manufacture a unit will appear to be good.
Later as the moisture penetrates through the grease to the juncion, it will affect the
unit's performance. Greases which are not penetrated by moisture eventually do not
exist. Leakage current (Icno particularly), and current gain (hn and h,.) are normally
the most sensitive parameters for the entire class of internal contaminant failure mecha-
nisms. Failure caused by entrapped foreign gases is most rapidly brought about by
high temperature storage. Even on non-greased units, high temperature operation or
storage may cause slow changes in the surface conditions resulting in shifting of
parameters.
One other factor should be considered here. Even though units work well at room
temperature and at elevated temperatures, they may fail at or below freezing because
of condensation of internal moisture. This can be detected by low temperature leakage
current measurements. Extreme care should be taken in this measurement since con-
densation external to the device may produce misleading data.
Outgassing
Outgassing is probably the most important failure mechanisms for non-gettered,
non-passivated devices. All surfaces have absorbed moisture and other gases. Under
the influence of high temperatures, these gases will gradually be released until the
concentration of gas within the enclosure is in equilibrium with gas in the surface.
Experience with ungettered units has shown that this equilibrium point, even with
processes which use very high temperature bake prior to capping, is high enough to
produce semiconductor device failure through excessive leakage current. High tem-
perature storage is the most useful stress in this case.
Entrapped lonizable Contaminants
Entrapped ionizable contaminants is a term describing a class of failure mecha-
nisms in which ionizable materials in the presence of moisture and voltage ionize at a
rate which is a function of temperature. These ions migrate under the influence of the
voltage and may set up inversion layers. 181 Figure 18.3 is a pictorial representation of
this action. Bar type devices generally are more susceptible to this migration failure
than alloys or mesa types because of the narrow base at the surface (collector to emitter
short). In rectifiers this inversion layer may short the junction to one of the ohmic

306
 SEMICONDUCTORRELIABILITY

contacts. An interesting relationship exists between temperature and degradation with

this mechanism of failures. For temperatures at and somewhat above room tempera-
ture, the degree of degradation which will ultimately be achieved will increase with
temperature. However, if the temperature is increased still further, the rate of recom-
bination of ions, due to thermal energy, overtakes the rate of ionization and the degree
of degradation is reduced. The relationship between degradation and temperature is
IONIZED
;-----coNTAMIN7ATS
SILICON
OXIDE /_N C~ANNEL
+++++++
+++++++ ---------
- - - - - - - - - -+- - -~- ::1--+-
= = =-=-==-t...-~.;"~•--:...+ +__-:..":f==-
--+ - - - - - - -¥ ++ +'"=1-~1- -+ - - ::J.- -
=----=-=±= +++++=,
_+___ +_ - -- .±±.++...±.± -==+-=-=-
+ - El - - - ---<1 +
==+-=-N=----_- +-+ P++-' -=J 11~==:
- - - - - - - - '=F-=I=""=F~ -Fl = =---=.. =
=.=:::
~ -£-.:-+:-:
+ + -=.++I
=-=
==-+-:...
-_-:..-
EMITTER BASE COLLECTOR
CHARGE Vee
DEPLETION LAYER

N CHANNELING IN AN NPN BAR STRUCTURE

Figure18.3

non-monotonic with a maximum depending on voltage, geometry, and degree of con-

tamination (for some practical silicon devices it is in the range of 150°C to 200°C).
If voltage is removed and temperature maintained, the ions will recombine and the
contaminant molecules will redistribute themselves essentially in the original manner.
The mechanism is reversible.
The stress which is most useful in detecting this mechanism is a combination of
temperature and voltage. When taking the units off test for measurement, the voltage
should not be removed until the units are cooled off. Leakage current (generally lcso)
is the best indicator of failure for this mechanism.

Ionic Conduction and Corrosion

Ionic conduction and corrosion are extreme cases of entrapped ionizable contami-
nants. When the level of moisture and contaminant reach a certain level, failure can
occur due to ordinary conduction on the surface of the oxide film without the need
of the induced inversion layers. When the amount of contaminant is even greater,
actual chemical corrosion may take place. In this last case the failure may sometimes
show up as an "open" rather than as excessive leakage. In all these cases, high tem-
perature and voltage would point up the fault.
Base Minority Carrier Trapping
Base minority carrier trapping is a somewhat different form of failure. This is
dependent upon the density of surface states (allowed energy levels within the band
gap) and on the difference in time constants between the slow surface states in the
oxide layer on the surface (milliseconds to days) and the fast surface states within the
surface of the semiconductor (microseconds). These factors in tum are influenced by

307
SEMICONDUCTORRELIABILITY

the surface treatment (degree of oxidation, etc.) and on gases in the enclosure. Initially
the fast surface states act to keep the current gain low through high surface recombi-
nation. However, if a bias current is passed through the base continuously for a period
of time the fast surface states will become filled and will remain filled. To maintain
charge neutrality the slow surface states within the oxide layer, will slowly be emptied.
Once this has been brought about, the current gain will be raised appreciably because
the fast surface states are now maintained in a filled condition by the charge in the
slow surface states. The stress which brings this about is primarily current. An increase
in temperature will increase the rate at which this action takes place. However, if the
temperature is raised beyond a critical point the amount of degradation will decrease
due to the increase in speed of response of the slow surface states. If current is re-
moved the slow and fast surface states will re-establish the original equilibrium and
the unit is essentially as it was originally. The higher the temperature the faster the
original equilibrium is re-established. The most critical parameter to monitor for this
mechanism is current gain (hFE,h, ..) although Icno is also informative.

MATERIAL ELECTRICALFLAWS
A fourth major failure mechanism category is material electrical-flaws.These flaws
consist principally of junction imperfections. The junction imperfections may consist
of two types, those which produce failure at high currents and those which produce
failures at high voltages (Figure 18.4). Alloy or diffusion may result in an unequal
penetration of the semiconductor by the doping agent resulting in the base having
one or more relatively narrow separations between emitter and collector. These points
will receive higher than average current densities which will generate local hot spots.
As total current is increased, these local hot spots may reach temperatures where further
diffusion or alloying will occur, resulting ultimately in a shorted base (collector to
emitter). In some device designs, currents above ratings, such as under pulse condi-
tions, can cause this same type of failure, even with no junction imperfections because
of the distribution of current in the base region.

INDIUM
COLLECTOR

HIGH CURRENTDENSITIES

Go

CURRENTSENSITIVEJUNCTIONIMPERFECTION

HEAVYMETAL
:tlolPURITIES
OlfFUSEOTRANSISTOR

VOLTAGE SENSITIVE JUNCTION IMPERFECTION

Figure 18.4

308
 SEMICONDUCTORRELIABILITY

If the resistivity of the semiconductor material near the collector junction is not
uniform, the depletion region will expand irregularly, as voltage is applied, giving
rise to differences in voltage gradients in this region. 111> Differences in voltage gradients
in turn will affect the collector multiplication factor producing unequal current distri-
bution. This will only be important at high voltages approaching BVcEo or above.
Below that point, the multiplication factor is so close to unity that variations in it
would have no detrimental effect. However, near breakdown, the high local currents
and high voltages can generate local hot spots which can lead to cumulative degrada-
tion and ultimate failure.
High current operation and high voltage operation at room temperature are respec-
tively the best means of detecting the current and voltage sensitive junction imperfec-
tions. When these faults exist and are strongly stimulated, the results are usually
catastrophic so that monitoring for opens and shorts should normally be adequate.
If life test racks are used which do not allow burn out (through protective circuits)
monitoring should be for changes in current gain (h.,.,.)or breakdown voltage (BVcw,).

METAL DIFFUSION
Another failure mechanism classification is metal diffusion. Whenever two metals
are in intimate contact, whether compression bonded, alloyed, diffused, or welded, a
disequilibrium is established. In accordance with the general laws of diffusion, the
metals on each side of the interface will diffuse so as to establish an equilibrium condi-
tion. The rate at which this takes place is a function of temperature and the diffusion
constants in the metals involved. Two general types of problems may exist; diffusion
of dopants and ohmic contact material into the semiconductor material, and diffusion
of ohmic contact materials and lead materials into each other. In the first type this
may cause a decrease of base width with a resulting reduction in reach-through volt-
age (for some abrupt junction types) or a change in the resistivity profile which might
result in a change in avalanche breakdown or other parameters. In the second type,
changes which have been observed are weakening of base or emitter leads by the
creation of brittle alloys and increases in ohmic resistance through the forming of high
electrical resistivity alloys. In general these types of failures are of minor concern
since even if the failures could occur, the rate of diffusion is so low that it would not
occur in the useful life of most equipment.

SUSCEPTIBILITY TO RADIATION
A failure mechanism which is only important in special applications - but then is
vital - is that of susceptibility to radiation. There are two modes of failure
1. Temporary malfunction caused primarily by transient gamma radiation pulses
2. Permanent degradation resulting primarily from the total fast neutron
dosage. no.,1,
The temporary degradation is due to both volume and surface ionization resulting
in excessive leakage currents. These leakage currents may in some circuits produce
permanent damage through thermal nm away. Some decrease in current gain is some-
times observed during the transient burst.
Gamma radiation may cause permanent degradation as well as temporary if the
total dosage becomes high enough. However, in the usual case, the fast neutron total
dosage reaches the degradation level first. Degradation in this case is the result of
decrease in the base minority carrier lifetime which in turn causes the current gain
to decrease. Since this is a volume phenomenon, it is relatively predictable as opposed

309
SEMICONDUCTORRELIABILITY

to the transient leakage current effects which, because of the surface contribution,
are relatively unpredictable. Exposure to a radiation environment is the only sure
means of determining the ability of a device to perform in a particular radiation
environment. Since this is extremely expensive and available time on appropriate
reactors is so limited, a reasonable approach to this failure mechanism problem would
be a unified, industry wide, semiconductor device evaluation program. Up to the
present, no such program exists.

FAILURE ANALYSIS
Both in the production of semiconductors and in their use, it is important that
failures be carefully analyzed. Failure analysis when it is correlated with use (or test)
conditions and with manufacturing variables can be the most powerful tool in improv-
ing reliability. It normally will indicate whether the failure was due to misapplication
or operating abuse (screwdriver mechanics), to poor workmanship or materials, or to
inadequate device design. This obviously is a start on the road to correction.
Since failures are relative rarities and since they are so vital in learning how to
improve reliability, it is important that failure analyses be performed by properly
trained personnel carrying out a thoroughly thought-out plan. Otherwise, not only
may the real reason for failure be obscured but incorrect conclusions may be drawn
which may lead to much wasted effort or even to a decrease in reliability. The subject
of failure analysis is too complex to cover here in any detail. The most important areas
of analysis that may be used to isolate the causes of failure are
1. Complete summary of operation and production history (as complete as
possible)
2. Measurement of electrical parameters, including static characteristic curves
3. Special tests, more than one of which may be run in a sequence, such as
(a) low temperature lcRo
(b) non-operating high temperature storage
(c) high temperature with back bias
(d) high temperature with forward current
4. Radiflow leak detection (where appropriate)
5. Gas analysis (mass spectrometer)
6. Special tests on the opened unit, more than one of which may be run in a
sequence such as those listed above in number 3
7. Visual examination
8. Reprocessing and testing; such as rewash, re-etch, etc.
9. Metalographic Analysis.
Of course only those steps need be performed which are meaningful and only enough
of them to draw a conclusion.

FAILURE DISTRIBUTIONS
Reliability, as defined at the beginning of this chapter, is the probability of satis-
factory performance for a specified period of time. If an appropriate statistical model
of this probability as a function of time can be found, it can be used to advantage in
improving reliability. Systems and circuit designers can take advantage of this to esti-
mate reliability when optimizing their designs; it can also be used in planning main-
tenance systems and in determining the logistics requirements. Device manufacturers
can use this reliability model to optimize life test acceptance plans, to screen produc-

310
 SEMICONDUCTORRELIABILITY

tion so as to weed out potential failures, and to provide clues to failure mechanisms
whose elimination will ultimately lead to product improvement.

MATHEMATICS OF FAILURE DISTRIBUTIONS

There are many terms used in analyzing and describing the reliability of devices
or systems. These are given and defined below:
Reliability Function - R(t) The probability of a unit (system, equipment, device)
from a population surviving up to time, t. (also called survival function)
Cumulative Failure Function - F(t) The probability of a unit from a population
failing before time, t.
Probability Density Function of Time to Failure - f(t) The limiting value of the
ratio of the probability of failure in the time interval, t+ 6 t, over 6 t as 6 t
approaches zero.
Instantaneous Failure Rate - Z(t) The limiting value of the ratio of the proba-
bility of failure in the time interval, t+ 6 t, having survived to time, t, over
6 t as 6 t approaches zero. This is the conditional probability density function.
These are all related and knowing any one as a function of time permits the others
to be determined.
=
f(t) limit F (t ± 6 t) - F(t)
b.t
b.t • 0

R(t) = 1 - F(t) = I - J}<x) dx

Z(t) = f(t) = f(t)

R(t) I - F(t) I - f
f(t)
]<x) dx

Relationships such as these are only useful if the observed probability of survival,
R(t), or the more commonly used term, instantaneous failure rate, Z(t), can be
expressed in mathematical terms and if the product characteristics are consistent
enough to make calculations meaningful. Extensive testing by many semiconductor
manufacturers have resulted in three mathematical models being found applicable
over certain portions of the useful life of the devices. These are the Weibull, <12 •13 • 10 the
exponential,<111•1111 and the lognormaJ.07 • 1R> Figure 18.5 shows these three distributions
in the form of the density function, f(t), and the instantaneous failure rate, Z(t). It will
be noted that the exponential distribution is the same as the Weibull with the shape
factor, fJ, equal to unity and the mean life, 0, equal to the scale factor ci. For the case
of the exponential distribution the instantaneous failure rate, Z, is constant in time
and equal to the reciprocal of mean life ( Z(t) = X =¾).
For the Weibull distribution, the failure rate is decreasing continuously for values
of Pless than unity and increasing for values of fJ greater than unity. In some situations
it may permit a better fit of the model to the data if a delay time, t, is introduced. This
means that no failures occur until after a time, t. This delay is usually symbolized by
-y. This changes the equations for the Weibull in Figure 18.5 to

R(t) = ex{- (t ~ -y)tl etc.

The lognormal distribution has two parameters, the standard deviation, " and the

311
SEMICONDUCTOR RELIABILITY

f(t) ' r--.._

........
........
,..,,,,_
Z(t)
A

.......
---
TIME (t) TIME (t)

f(t) " 7iexp r<t~ Z(t)" ½•'A

F(t)= I-exp [(i~ R(t) "exp E<f~
EXPONENTIAL DISTRIBUTION

TIME (t) TIME (t)

f(t)
~.,a-07 exp rt fa]
•r---a-j Z(t)::
J3t<a-1)
-a--

F(t)= I-exp t(:~ R(t) =exp t<~)]

WEIBULL DISTRIBUTION

Z(t)

TIME (t) TIME (t)

f(t) " ~ exp r_..Lel!!!::l!:.>2'1 ..!.exp r_...!..( ..l!!!.=.f:.fl

o-h21r [ 2 a- J Z(t>= t [ 2 tr 'J
F(t) ·-'
a-V2Ti
- ['.L EJ_(-e121
0
X j
exp
2
lnx
CT
dx l
t
col.exp [..L( lnx-1'12] dx
X [2 O'

R(tl•I-F(t)

LOG NORMALDISTRIBUTION

FAILURE DISTRIBUTION MODELS

Figure 18.5

mean, µ.. In practice, the practical parameters used are rr and elL. This latter is the
median life, the time by which one-half the units are expected to have failed. For the
lognormal distribution, the median life is a more convenient measure of central ten-
dency than the mean life because, unlike the latter, the median is independent of the

312
 SEMICONDUCTORRELIABILITY

standard deviation. The lognormal differs from the other distributions in that over one
portion of time the failure rate is increasing while over another portion the failure rate
is decreasing. In fact, the instantaneous failure rate, Z(t), is zero both at time zero
and at infinity.

GENERALIZED FAILURE DISTRIBUTION

The general shape of the failure distribution density function, f(t), is shown in
Figure 18.6 by the solid line. The descriptive terms for regions A through F refer to
the instantaneous failure rate, Z(t), associated with the density function.
INSTANTANEOUS
FA!WRE RATE,ZCII
.,, .,,
~
c:,
z z lE
;i ! ~
w
a:
~
0
t!
~
0
u
I
..,
5
;!;
~
~
A B F

1111
~ wo;:.~::;1P
------ j •
..__________oESIGN (WEAROUTI
TIME TO r--- FAILURES
FAILURE
PROBABILITY
OENSITY
FUNCTION

TIME TO FAILUREIll

GENERALFAILUREPROBABILITY
DENSITYFUNCTION
Figure18.6

The delay (A) is due to the fact that the definition of failure almost always incorpo-
rates a safety factor beyond the initial parameter values and it takes some finite time
for any units that are initially good to degrade to this end point limit. Of course, the
lower the stress level, the longer this would be. At high stress levels this might be so
short that it might not be seen. Region B is the transition region as the first units begin
to degrade beyond the design margin. Region C covers the time that failures due to
workmanship faults drop out. This generally is a decreasing failure rate and has been
so observed in transistors, vacuum tubes, and other components. Two distributions
have been found to fit regions A, B, and C very well. They are the Weibull distribu-
tion with a shape factor, {J, less than unity and a delay term, 'Y, and the lognormal
distribution. On transistor data, it has been found that these two can be equally well
fitted to large quantities of data on many transistor types.
In Region D the failure rate appears to be essentially constant and relatively low.
It can be hypothesized that this constant failure rate condition occurs because of the
overlap of the decreasing failure rate of the workmanship failures and the increasing
failure rate of the wearout failures of Region E and F. These overlapping distributions
are shown by the dotted lines.
This generalized failure distribution model assumes that eventually everything
wears out. In some component parts such as batteries or light bulbs the wearout
mechanism is the exhaustion of a non-replaceable material. In transistors it is not so
clearly defined. However, it may be the eventual leakage into the encapsulation of
enough moisture to degrade this surface (even for well passivatd units this is possible)
or it may be mechanical fatiguing of leads or mountings, or diffusion of doping mate-
rials or impurities into the semiconductor material. From the physical laws associated
with these possible failure mechanisms, it is likely that the failure distribution in

313
SEMICONDUCTOR RELIABILITY

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PRODUCTION PERIOD:
1958-1961
OVENSlORAGE(1!)I00°C
TOP NO.•NO.OF FAILURES
BOTTOMNO.•NO.OF UNITS
LIMITS:
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1961
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SAMPLE SIZE UNITS
LIMITS:
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L2 INITIALUPPER
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200 400 600 BOO 1000
HOURS
FAILURE RATE OBSERVATIONS
Figure 18.7

314
 SEMICONDUCTOR RELIABILITY

regions E and F follow a lognormal distribution. un Considerable data from high stress
level life tests show this pattern. Based on this, region E is the increasing failure rate
portion of the lognormal distribution whereas region F has a decreasing failure rate.
Figure 18.7 presents four sets of failure rate observations which illustrate various
portions of the general failure distribution model. Curve A shows regions A, B, and C
for a germanium PNP alloy transistor life tested at shelf storage (25°C). Curve B
shows the failure rate of an NPN silicon grown diffused transistor operated at full
power rating (500 mw). Here the delay is so short that it is not observed in the opera-
tion of the life test. Curve C shows the long term performance of a PNP germanium
allow transistor tested at rated storage temperature (I00°C). This illustrates regions
A, B, C, and D. The final curve, D, illustrates wearout, region E. The data was obtained
from storage life tests at conditions well beyond the ratings on the same PNP ger-
manium alloy type as that in curve A. The storage test was run at 135°C compared to
a maximum rating of 100°C.
PUTTING FAILURE DISTRIBUTIONSTO WORK
It has been pointed out that in regions A, B, and C both the Weibull and the log-
normal distributions can usually be fitted to transistor life test data equally well. From
a physical standpoint, the lognormal distribution appears to be more reasonable in
that discontinuities such as those introduced by a delayed Weibull are not likely in
nature. On the other hand, from the standpoint of the development of screening tech-
niques and of improving sampling plans, the errors introduced by the use of the
Weibull are small. The advantages of the Weibull as a working tool are primarily the
completeness with which the shape factor, fJ, describes the rate at which the failure
rate changes and the simplicity of the equations relating probability of failure to
average failure rate, instantaneous failure rate, and mean life. ua,
In the next section, consideration will be given to bum-in for the improvement of
reliability. An important factor in selecting the stress conditions for burn-in is the
Weibull fJ, the set of burn-in conditions with the lowest fJ (less than unity) will bring
about the greatest improvement in failure rate in the least time. On the other hand,
a fJgreater than unity indicates an increasing failure rate in which case a burn-in actu-
ally will make the resulting product less reliable.
In the matter of sampling plans, the knowledge of the Weibull parameters of the
failure distribution can lead to savings in testing costs if the distribution has a fJ
appreciably less than unity (and no appreciable delay). For example, if the beta is 0.5
which is typical, testing time can be cut to one-half by increasing the sample size by
only 40% without changing the basic sampling plan. The result is a savings of 30%
in the number of socket hours required. On the other hand, if the distribution has a
delay, 'Y, or an increasing beta, this is a clear warning that reduced hour testing is
dangerous and should be avoided. Much work is presently being directed, industry-
wide, to greater use of the knowledge of failure distributions, particularly in the field
of life test sampling plans.

ACCELERATION
FACTORAND MODULUSOF FAILURE
Frequently through this chapter there has been mention made that high stresses
generally will cause more failure than low stresses. It has also been pointed out that
the definition of failure also determines the probability of failure. The subject of this
section is the relationship between the probability of failure, stress level, definition of
failure, and time. Much must be learned before this relationship can be based on solid
theory; but a start has been made in its empirical determination.

315
SEMICONDUCTORRELIABILITY

DEFINITIONS
Before continuing, two terms must be defined: accelerationfactor and modulus of
failure. In the past the term acceleration factor, has been used to mean the ratio of
failure rates at two stress levels or the ratio of times to obtain the same cumulative
failure at two stress levels or the ratio of cumulative failure at a particular time at two
stress levels. This one term can unambiguously mean all three of these ratios if - and
only if - the instantaneous failure rate is constant over all time and if we are only
concerned with low cumulative failure levels (say less than 10%). However, as has
been shown in the previous section, constant failure rates are not the general rule.
Therefore, more generally applicable definitions of terms relating failur~, time, and
stress level are needed if they are to be meaningful. Consider, first of all, the ratios of
the failure rates. Referring to the generalized failure probability density function
shown in Figure 18.6, it can be seen that the multi-valued nature of the instantaneous
failure rate (increasing, decreasing, increasing, decreasing) would lead to an ambigu-
ous and generally meaningless factor if ratios of instantaneous failure rates were related
to stress levels. For this reason no such term should be used.
Next let us consider acceleration factor. Acceleration is generally regarded as the
speeding up of a process or action. For this reason it is logical to apply the term,
acceleration factor (A) to the ratio of the time of occurrence of a specified cumulative
failure level at one stress level to the time of occurrence of the same cumulative failure
level at a higher stress. Figure 18.8 shows hypothetical cumulative failure distribu-
tions for two life tests at different stress levels. These are the cumulative distributions
associated with the general failure distribution model of Figure 18.6 with different
time scales. The two equations for A below Figure 18.8 illustrate how the accelera-
tion factor is determined. It is seen that, as the name implies, it is the factor by which
the time to observe a particular level of failure is speeded up or accelerated with the
increase of stress. From the illustration, it can be seen that this is not necessarily a
constant factor as the level of cumulative failure is changed. The third ratio which
has been loosely called acceleration factor concerns the ratio of cumulative failure
levels at a particular time. A new term should be used for this. It is the modulus of
failure (M) and is defined as the ratio of the probability of failure prior to a specified
time at one stress to the probability of failure prior to the same time at a lower stress.
The two equations for M below Figure 18.8 illustrate how the modulus of failure is
determined. It is the factor by which the level of failure is increased with the increase
in stress. The curves illustrate that this too is not a constant factor as time is varied.
A question which might be raised is why we need two different terms. To answer
this let us first consider how the two might be applied. The first example is an equip-
ment design problem where there is a specified operating time. The question to be
answered is how operating stresses affect the failure level. Since we have a fixed time,
the factor we need is the modulus of failure, M. In a second example, a device manu-
facturer is interested in performing an accelerated life test for lot acceptance purposes.
He is interested in observing in one week the same level of failure that normally
would take 3 years to occur. Here the failure level is fixed, the factor we need is the
acceleration factor, A. Since in general neither A nor M is constant over all time and
all levels of failure for a given device type and pair of stresses, it is clear that they
are not generally equal nor related by a constant factor. Therefore, we must have the
two factors for use in the different kinds of problems.
So far only stress vs. failure rate and time have been mentioned. The same kinds
of relationships would hold if instead of two stress levels, we used two levels of defini-
tion of failure, the more stringent definition of failure taking the place of higher stress.

316
 SEMICONDUCTOR RELIABILITY

IOOr-------------------------------.

I
I
I
I
I
I
-------•----- ---- - ---
1
LOW STRESS (SL)

LL.
F1 M::=---~---......,.i------,L---------------~----'
t3 t4 t5
TIME TO FAILURE ( t)

t5(F4,SL) F504,SH)
A( F4 'SH ,SL)•------- M(t4,SH ,SL )a__,_ ____ .;...
t2 (F4, SH) F3(t4, SL)
ACCELERATION
FACTORAND MODULUSOF FAILURE
Figure18.8

RESPONSESURFACE RELATIONSHIP
Figure 18.1 showed that there are many stresses which induce failure. It would be
highly desirable, particularly from the circuit designer's viewpoint to know not only
how each stress alone affects the probability of failure but also how the stresses in
combination affect it. The response surf ace relationship provides the answer to this
question. A response surface relationship can be considered as a multi-dimensional
"surface" relating the probability of failure to many stresses at a given time. F(t1) is a
function of voltage, current, power, ambient temperature, junction temperature, cycling
rate, etc., at time (t1). A response surface can also be solved for the time to observe a
given percent failure as a function of the stresses but since the first form is generally
more applicable to the user's needs, that is the one most commonly solved.
To determine the relationship mentioned above requires considerable testing and
analysis. This is particularly true when the stresses near those the circuit designer
might employ are considered. If the device is worth using, the failure level will be so
low at the use condition that extremely large sample sizes are required. Furthermore,
limitations on testing accuracy and reliability provide a limit of significance inde-
pendent of the sample sizes. Investigations are currently underway to determine means
of making use of stability data under these circumstances; however, at present the
solution is to test at high levels and to extrapolate the relationship down to the low
levels. There is, of course, a major weakness in this approach in that there is no assur-
ance that the failure mechanism which is accelerated at high stress levels is the one

317
SEMICONDUCTORRELIABILITY

that is important at low stress levels. For example, it is possible that at high power,
the failure mechanism may be the excessive shift in current gain brought about by
minority carrier trapping. At low power, failures may be caused by moisture leaking
into the case through faulty seals. Although this type of risk exists with extrapolations
there is presently little alternative within the realm of economic feasibility.
One important safeguard which should be included within response surface evalua-
tion program is a field service performance feed back. Long term service in actual
equipment with comprehensive reporting on failures and failure mechanisms can pro-
vide the cross check on the extrapolated estimations that is needed. Such information
over a period of time can build up an understanding of the relationships between high
and low performance that can make extrapolations very useful.

SCREENING
The constantly increasing transistor reliability requirement is imposing a more
and more severe responsibility on transistor manufacturers to eliminate not only poor
designs and poor workmanship but even the so called freaks. Freak transistors may be
considered to be the result of unusual combinations of factors which elude ordinary
detection but will in use fail relatively early in life relative to most of the units. On
large scale production lines, it is unreasonable to expect that this freak rate will be
reduced to a level acceptable for some of the more severe reliability requirements.
Even in those cases where the reliability requirements are no more severe than good
production techniques can satisfy (for example 0.1 % to 0.01 % failure in 1000 hours),
the assurance of this quality on either a lot basis or on a production history basis is
not generally economically feasible. An approach to this problem which both increases
the likelihood of detection of freaks and at the same time provides an indirect means
of measuring reliability is screening (or post fabrication processing). Broadly, this con-
sists of performing a sequence of inspections, measurements, and tests on all units,
each with a set of criteria for rejection, then submitting all of the units remaining to a
low level operating bum-in. This last provides final screening and, simultaneously, a
measurement of the quality of the product.
In setting up the screening sequence, it is important to keep in mind what is being
sought - freaks. Since these are generally unpredictable it is necessary to provide a
screen that will stand a very good chance of detecting the freaks regardless of the form
they take. Of course an understanding of the product can lead to an optimization
through the knowledge of tendencies for one type of freak or another to occur, but too
much reliance should not be placed on this knowledge. The screen should consist of
inspections, measurements, and tests. Inspections and measurements are screening
operations which do not affect the individuals but merely measure some significant
characteristic. Tests are screening operations which apply a stress to the units in order
to determine the unit's strength. In applying these stresses, it is important not to
destroy units which would provide satisfactory performance in ordinary use and, even
of more importance, not to damage good units in such a way that they appear satis-
factory but have a reduced life expectancy. A knowledge of the product including
data on long term life tests at high stress conditions provides guidance in this respect.
Below is a general outline of a screen sequence which might be used. (Steps 1
through 7 are primarily inspections and measurement).
I. Visual inspection - lead condition, critical dimensions (an example is misalign-
ment of cap and header leading to greater tendency for development of leaks), paint
or plating, etc.

318
 SEMICONDUCTORRELIABILITY

2. Electrical parameters screened - so as to eliminate tails of tailed distributions

and to provide ample safety margins within specification limits
3. Static characteristics observed - on oscilloscope, rejecting units with irregulari-
ties or excessive instability; observe both breakdown characteristic (off) and the satura-
tion characteristic (on)
4. Measurement of internal dewpoint - through low temperature lcuo, when
applicable
5. X ray - for proper placement of internal structure
6. Leak detection - both Radilla and detergent pressure bomb
1. Diode leakage current (Iceo) stability, short term (such as 10-30 seconds)
(Steps 8 through 13 are primarily testing)
8. Mechanical stress - this may be monitored shock or repetitive tapping, centri-
fuge, etc., to look for intermittents or weak parts or connections
9. Voltage stress - probably a high back bias with high temperature; if operated
in avalanche this can detect junction flaws.
10. Current stress - high power at lowest possible collector voltage
11. Thermal fatigue - rapid 50% duty cycle, high power, high current
12. Temperature stress - this might be high temperature storage only or it might
be cycled high and low (-65°C) slow cycle (2 hours each cycle)
These ..life tests" generally will produce results in a few days or a week if there is
any weakness to detect.
13. Burn in - this would normally be on operating life test at power and voltage
between rated conditions and expected use condition. The duration of this test might
be from a few days to several weeks or even months. This test is intended to do three
things: catch delayed failures from the accelerated tests, stabilize the transistors, and
monitor final performance. On the premise that stability is essential for reliability, this
portion of the screen can be used for reliability assurance. If more than a prescribed
number of units change characteristics more than a specified amount, the lot can be
assumed to be of substandard quality even after screening and should be rejected.
The screen inspections, measurements, and tests and the criteria of rejection must
be tailored to each situation. Not only will the differences in transistor types affect the
design of the screen; but, in addition, the required level of reliability and the allowable
total cost will affect it. As the importance of eliminating potential failures increases,
the duration of tests, the number of measurements, and the severity of rejection criteria
will increase. This will generally increase the number of good units that will be rejected
and will rapidly increase the cost. The balance between effectiveness of the screen and
the efficiency will be determined by the balance between reliability requirement and
cost.
The screening principles outlined have been applied to several different products at
General Electric. No one screen has made use of all the steps shown in the sequence;
however in some cases other tests have been included. The most comprehensive screen
and the one whose effectiveness has been· most carefully evaluated has been applied to
the Minuteman version of the 2N335 (North American Aviation, Autonetics Division
Type 703). The screen consisted of electrical measurements, Radiflo leak detection,
monitored repetitive shock test, high power cycled operation, and high temperature
storage. Following this there was a bum-in at 348 mw (rated 500 mw) for one week.
When units which were acceptable after this sequence were operated for 2700 hours at

319
SEMICONDUCTORRELIABILITY

348 mw and compared on the same test to units not subjected to the screen, there was
found a reduction in cumulative failure of 8 to 1. The tests are continuing to strengthen
the measure of product improvement for long life operation.

RELIABILITY DATA FOR TYPICAL TRANSISTORTYPES

EXPLANATIONOF ANALYSIS AND PRESENTATION
The reliability data shown on the following pages are the results of both the rou-
tine quality control acceptance testing performed on the particular production lines
and of special evaluation testing programs. The characteristics shown are on specific
products which are representative of the General Electric product lines. There is one
PNP germanium alloy (the 2N524 family), one NPN silicon grown diffused (the 2N335
family), one PNP germanium mesa (the 2N705 family), and one NPN silicon planar
diffused (the 2Nl613 family).
Two methods of analysis and presentation of reliability data are used, an attribute
analysis of a large number of life test samples and variables analysis of a single sample
(in some cases a few similar samples have been combined). As an aid in understanding
these data, let us consider Figure 18.9, (A) and (D). Figure 18.9(A) is a plot of the
average failure rate as a function of time to failure. The theoretical average failures rate
is the average of the instantaneous failure rate, Z(t), over the interval of time consid-
ered. Empirically it is determined by dividing the percentage of those transistors which
started on test in a particular time interval and failed by the duration of that interval.
The unit of measure of time used is that in which it is desired to express the average
failure rate. As an example, let us calculate the average failure rate (in percent per
thousand hours) between 7,000 and 10,000 hours. From Figure 18.9(A) it can be
determined that there were 286 transistors which started that interval. Of these, 2
failed for a percentage of 0.7%. Dividing this by 3 (3 units of 1000 hours each) yields
0.23% per 1000 hours average failure rate. The failure rate calculated by this means
is shown by the heavy solid line.
Since such estimates have a sizeable element of uncertainty in them, it is desirable
to indicate intervals within which there is a specified likelihood that the true values
exist. These intervals are called confidence intervals. Since we are making an attribute
analysis, the binominal distribution can be used to determine the limits of these inter-
vals. 0111 The eighty percent confidence intervals are shown in these figures by the
shaded area. This may be interpreted to mean that of all the failure rates confidence
intervals shown in these figures approximately four out of five will include the true
value of the failure rate - one out of ten of the true values will be higher than the
upper limit, one out of ten will be lower than the lower limit.
A word on how the data for these figures were obtained. The data for the first 1000
hours are the results of the routine quality control life tests which are restrictive on
all General Electric products. The longer hours data are primarily the results of the
extensions of these same life tests. However, beyond 1000 hours the sample sizes are
substantially reduced. In some instances engineering evaluation data have been in-
cluded in the long term data where they were pertinent. It will be observed that as
the hours increase, the sample sizes decrease,C'fewer units having had the opportunity
to reach the longer hours. There are many other ways in which this same data could
have been presented. This method was chosen because it requires no assumptions of a
particular failure distribution, nor implies any; it is readily applied in the case of
diminishing sample sizes, and it clearly shows the various regions of the general failure
distribution model.

320
 SEMICONDUCTOR RELIABILITY

For those who would wish to plot the data on cumulative probability paper (such
as Weibull or lognormal), the following formula can be used

F(t.,) = [l- R(t.,)] 100

=[1-. _
._o'
;TT
I N,
==[.t
N,- n,]100
•=
!!1]100
0 N,
where F(t.,) is the percent cumulative failure to time t.
t1 is the duration of test up to the i 11' measurement period
is the sequence number of measurement periods and varies from Oto (a)
R(t.) is the percent survival to time, tJ
NI is the sample size starting the life test interval between t<1-1> and t,
n1 is the number of failures in the interval between to -11 and t,
a
i =o7T indicates the prodt~ct of all factors with i having values of 0 through (a)
a
I indicates the sum of all terms with i having values of O through (a)
i=0
The approximation is good for total cumulative failures less than 10%.
Let us now consider the second form of data analysis and presentation as exempli-
fied by Figure 18.9(D). This method of analysis is intended to determine the degree of
stability of the important parameters. In this form of analysis each transistor is con-
sidered rather than the few that exceed a relatively arbitrary limit. Although it is more
difficult to interpret this data into failure rate calculations for equipments and systems,
it is much more sensitive in showing trends which might anticipate the future. For
example, the situation might exist where the observed percent failure is small because
the initial distribution of the important parameters is considerably below the definition
of failure; however if the entire distribution of that parameter was increasing substan-
tially, this would indicate that a large percent of the units are heading towards failure.
Stability data is presented in terms of percentiles. A percentile is the value of the
particular parameter being considered below which the specified percentage of the
transistors are expected to fall. For example, in Figure 18.9(D) at zero hours, 95% of
transistors are expected to fall below 12.5 microamperes.
In applying percentiles to life test data, several details should be explained. In
calculating percentiles at the various measurement periods, every transistor which
started the test is included even if it has completely failed and has been removed from
test. Failures are included at one extreme or the other depending upon the mode of
failure and how it would have affected an operating circuit. The only exceptions to
this rule are transistors which were lost, damaged in measurement, or otherwise affected
independent of the life test. These units are then removed completely from the sample,
from zero hours on. If a plotted percentile leaves the range of the graph paper, the
next reasonable percentile (usually 5 percentage points up or down as appropriate) is
plotted for that and succeeding measurement intervals.
In plotting parameter distributions with time, it is necessary to keep the same
sample throughout. If samples are added or subtracted (the latter is the more likely
since some samples that might be combined in the early hours have not yet reached
the longer hours), the differences in initial distributions will cause an apparent shift in
parameters making it appear that the units are unstable.

321
SEMICONDUCTOR RELIABILITY

RELIABILITY DATA ON A GERMANIUM PNP ALLOY TRANSISTOR

(Figure 18.9)
Graph A - It should be noted that the definition of failure for this test condition is
very tight; the end of life limits are the same as the initial limits. Note the delay -
no failures for 125 hours, then a sharp rise and a gradual decrease in rate of
failure until by 5,000 hours it appears that a constant failure rate has been
obtained.
Graph B -The same general pattern at 100°C (maximum rating) but not as clear cut.
Even though the definition of failure has been loosened the failure rate is higher
in the constant failure rate region. This demonstrates the effect of higher tem-
perature stressing.
Graph C - For this operating life test at full rated power, there is no apparent delay
initially. The failure rate decreases, but slowly, until about 5,000 hours. After
that it appears constant. The reason that this test only extends to 20,000 hours
while the previous two went to 25,000 is that only the "on" time of the 50 minute
on - 10 minute off cycle is counted; actual elapsed time is approximately 23,000
hours. The last 2,000 hours give the appearance of the start of wearout; however
it will be noted that this is the result of only one failure. A study of the total
sample of graphs D and E shows no shift of the main portion of the distribution
up to this point leading to the conclusion that this is not the beginning of wearout.
Graphs D & E - These curves show that on cycled operating life test the principal
cause of failure is an increase in Iceo. However, as has been pointed out, the main
portion of the distribution is very stable. The h••Edecreased for most units initially
but over the last 10,000 hours was quite stable.
Graphs F & G - The units represented by these curves are early engineering samples
utilizing the molecular sieve getter which has made this family of transistors so
reliable. On high temperature storage, the stability of both Icao and hn is out-
standing after the initial few thousand hours. Lack of signs of wearout at this
high stress level after five years of testing indicates the long life which can be
expected at normal use conditions.
4-------........
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322
 SEMICONDUCTOR RELIABILITY

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OVEN STORAGE ~ 100°c
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Iceo ~ 30V
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IOK 15K 20K 25K

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323
SEMICONDUCTOR RELIABILITY

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LOT NO.4597• 4848 98 UNITS PROOUCTION
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I I I I
SK IOK 15K 20K
® TIME IN HOURS

16
.. 2N43 FAMILY PNP GERMANIUMALLOY
LOT NO. 5394 99 UNITS PROOUCTION
14 '-PERIOD: LATE 1956 TEST CONDITIONS:
OVEN STORAGE 'ii>1oo•c 95th PERCENTILE
- MEASUREMENT CONDITIONS: .,i,
12 - Icao ~ Vee • 45V
.,"' '
' ----
10

-----~ -
.,
., I',

"
-----~
50111 PERCENTILE
~
, ......,.. T--
~ ~

i..---- I I I I

----- 5111~E!!£_E~ILE
'-
....... i'-..._

IOK 2OK 30K 4OK

© TIME IN HOURS

--,
--

2N43 FAMILY ...._

--
~ ~

PNP GERMANIUMALLOY
...._

-
LOT NO. 5394 1--
99UNITS
80 ~i~~~~g~~~~~OO: LATE 856_ 1-- ...._
OVEN STORAGE ~ ,oo•c _,._ 1-- L-
MEASUREMENT CONDITIONS: ...._
1-- 1--
11
10~1'c£•5VIc•IMAf•270CPS
Jr-~
I II
60 /
~r---~ __ 95TH PERCENTIL§_
i,..,"I',.. 1.......

I/ ""-'""'

40

If
,..... - --- 50TH PERCENTILE i- ~

-- -
20 ,__ 5TH PERCENTILE
r-i--

IOK 201< 30K 4OK

@ HOURS

RELIABILITY
DATAFOR A GERMANIUM
PNP ALLOYTRANSISTOR
Figure18.9

324
 SEMICONDUCTOR RELIABILITY

RELIABILITY DATA ON A SILICON NPN GROWNDIFFUSEDTRANSISTOR

(Figure 18.10)
Graph A - The definition of failure limits on this shelf storage test are the same as
the initial limits. As in the case of the alloy, there is an increasing failure rate
initially followed by a rapidly decreasing failure rate.
Graphs B, C, & D - All three curves show similar decreasing failure rate patterns right
from the start with the 500 mw operating test the most extreme. Any delays which
exist are not observed since the first set of measurements is made at 125 hours.
The decreasing failure rate continues right out to 10,000 hours with no failures
observed in the nearly 900 transistors (A, B, C, and D) between 8,000 and 10,000
hours.
Graphs E & F - These curves show that whether the stress is temperature alone or
cycled power (both at full rating) the leakage current (Iroo) is very stable. What
changes there are in h•••: are in an increasing direction which in most circuits is
of little concern.

1.8
I
I I I I
-3/3920 2N335 FAMILY
1.6
4/3917 PRODUCTIONPERIOD:1959-1960
SHELF LIFE lci>24°C __ _
SHADEDAREA •80% CONFIDENCE
1.41Ht--t---+------+--+----+- TOP NO. •NO. OF FAILURES - 1- -
(/) 2/413 BOTTOMNO. •NO. OF UNITS
0:
::::,
LIMITS:
~
0
X 1.2 ' ~---lf---1--+-
' Iceo ® 30 v
0 R hf• Ca)VCE11 '5.V,IE• I.MA
0 =-3/3833_~ ~---lf---1--+- END OF LIFE LIMITS SAME AS - 1-
0
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I
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, INITIAL ON h,. AND :[ceo
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~ .\~'-'
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::: "'

@ 2K 4K 6K 8K IOK
TIME TO FAILURE (HOURS)

325
SEMICONDUCTOR RELIABILITY

8/2890
36 ..... -r----+-+--+--+--+-+------+---,+-----------+---+-t--1
2N335 FAMILY
7/2882-+--+---1-t---t--ipRODUCTION PERIOD:1959-1960
Cl> 30 ____ --t ____ CYCLEDLIFE
--t_SHADED PW
AREA• 150MW
80o/o Ve20V TA 25°C i---t--t--,
CONFIDENCE
a: TOPNO. =NQ OFFAILURES
~ ~~ NO. • NO.OFUNITS
o 2.4 ._-,---,---t-lTCBO lit 30V. 41'aMAX.
8 ~@~~~~
~ 0.8 INITIAL LDWER
LIMIT
~ 1.8
~ ~++~
3 1.2 1-H,jrf-+~~
r!
a'-

2K
@

2N335 FAMILY
PRODUCTIONPERIOD: 1959 -1960
OVEN STORAGE ~ 200• C
SHADED AREA• 80o/e CONFIDENCE
Cl) TOP NO. •NO.OF FAILURES
~ 2 BOTTOM NO. •NO.OF UNITS
LIMITS:
:c

~ 1.2
er:
..,
30.8
if
-,!
0.4

2K 4K 8K

© Tl ME TO FAILURE (HOURS)

2N335 FAMILY
_____ PRODUCTION
__, C'tCLED PERIOD:
UFEPW 1959-1960
500MWVc30V ~ 25°C

1
~
16~-+--+---t!---t---1 SHADEDAREA" 80% CONADENCE
TOPNO ,. NO.OF FAIWRES
BOTTOMNO. II NO.OF UNITS
t--+--+---t--t---+---t

----------
~'2 LIMITS:
" I~ 30V 41'aMAX.
~ ht• ~"cE5V ![ !MA
a:: 0.8 INITIALLDWERLIMIT

00 2K 4K 6K
@ TIME TO FAILURE(HOURS)

326
 SEMICONDUCTOR RELIABILITY

2N335 FAMILY 2N335 FAMILY

PRODUCTIONPERIOD: 1960 PRODUCTION PERIOD: 1960
SAMPLE SIZE: 60 SAMPLE SIZE: 80
TEST CONDITION:!500MW, Vee• 30V 1°A
• 25•c TEST CONDITION:2oo·c STORAGE
CYCLED OPERATION MEASUREMENT CONDITION:
MEASUREMENT CONDITIONS
Icao<I' Vee•30V Xeao @Vea •30.V
h,. (a Yea. !5V h,.@ Vee • s.v
IE • -IMA
fE:,J~ f • IKC
iii

I
0.1 0.1
-r--,....
II!
Ill
0.
:I
"'
I
0.01
90 V r---... L.--

I
0.01 -
90

3:i
---
0
50 a:: 50
0.001,,,,,,,.. ~ 0.001
:I
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m 10 , __
u 10
~

- 00001
I/ ...... ~- ._r 0.0001
..,. I
I\.

;
160
140
'\ 90 ~ ... /v . 160
140
\ -
.......
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.... i,
I: i.,..,,-
- j

-
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! 120 ,_ ~
~ I/ ,_ ..!Q. !z 120

~ 100 ,,, ........... N 100

80 ...._ ~
_/ ~

'L---
80

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z
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.a 100

aov
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QI'\

10
,,,~~ I!-

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11'1

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. 100

80
60
I~ /
!50
10
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- -
40...- 40

sf- 60
90 - ..,
.6:
. 60
__ ...._
~
90
--
I--'

a
z
N
40 --
20
-
:,0
10 a
N
40
20
~

10
_J
--
0 4 6 10 0 4 6 8 10

© THOUSANDHOURS
OF TEST ® THOUSANDHOURSOF TEST

RELIABILITY DATA FOR A SILICON NPN GROWN DIFFUSED TRANSISTOR

Figure18.10

RELIABILITY DATA ON A GERMANIUM PNP MESA TRANSISTOR

(Figure 18.11)
Graph A - This graph shows a decreasing failure rate to about 500 hours and a con-
stant failure rate continuing out to 10,000 hours. The data is on early production
transistors.
Graph B - Recently, the rating on this type has been raised to 150°C maximum stor-
age temperature. Thousand hour data on recent production shows the product
improvement. It also shows that although the number of failures are limited,
there still is a decreasing failure rate after the initial buildup.

327
SEMICONDUCTORRELIABILITY

Graph C - The data shown on this graph is on early production units. This cycled
operating life test data indicates that out to 10,000 hours there is a decreasing
failure rate.
Graph D - More recent production showed a marked reduction in failure level. This
graph shows this for the first 1000 hours. Even more recently, the rating on this
type has been increased to 200 mw. Based on a sample size of over 400 units,
there have not been sufficient failures to establish a failure pattern. The average
failure rate for the latest product at 200 mw is compared on this graph to the
average failure rate on earlier product at 150 mw. The improvement is evident.
Graph E - The back bias life test data shown here consists actually of two life tests
combined, one at 55°C and the second at 75°C. There were approximately equal
sample sizes in each and approximately the same percent failure. The failure
rate decreases very rapidly indicating the possibility of this test as a reliability
screen.
Graphs F through I - As in previous stability data, most change occurs in tl1e first few
thousand hours with a high degree of stability beyond. Icao is the most common
source of failures; but as can be seen from the medians, the bulk of the distribu-
tions are remaining constant or even decreasing their leakage current.
7
4/1000
6 2N705 FAMILY
PRODUCTIONPERIOO:3RO QUARTER1960
OYENSTORAGE@)1oo•c
5 SHADEDAREA•80% CONFlDENCE
Cl) TOP NO.• NO.OF FAILURES
a: BOTTOM
NO.•NO.OF LNTS
~ 4
2/996
LIMITS: INITIAL END OF LIFE
0 hFE @Ic•IOMA ~• -0.3V 0.8 INT VALUE
~ Icao@5V MAXs,.a
1.3 INT VAWE
IOp.a
ij
a:
3

!
i'f
2

.ft
14/970
10/980

6K OK IOK

® HOURS

6,--..--...,..........,...-,----,----,-...-..---r---r-"""T""--r---r--ir--..--r---r--.----,---,--,
2N705 FAMILY
PRODUCTION PERIOD: 1960-1961
w 51--+-+--+----t---t-t--+--t--r OVEN STORAGE @ 150° C
12: SHADED AREA -eo•,.
CONFIDENCE

S4 g;~~~~:Es
JgiT~~:~8: NO.
~ LIMITS: INITIAL ENO OF LIFE
g 1ceo@5V 3p. o MAX 6,- o MAX
;5 3 hFE@)]:c•IOMA
~ YcE•0.3V 30 MIN. 20MIN.

@ HOURS

328
 SEMICONDUCTOR RELIABILITY

2N705 FAMILY

~
l,l,,>,il"1--~-----
8 ~~-+---+-+--+---i PRODUCTIONPERIOD:3RD QUARTER1960
CYCLEDLIFE PW 150MW VclOV. TA 2s•c
SHADEDAREA• 800/e CONFIDENCE
::, 7
0
J:
~~-+-+~1--+---i ~g;T~
•N~~ <:a.
~L~:i~i
~a--+---+----,~+--1 LIMITS: INITIAL END OF LIFE
0 ti,,~• IOMA't£•0.3V
0 0.8 INT.VALUE
~ 6 ~~-+--+~1--+---i l.31NT.VAWE
..... Icao (ii) 5V. MAX. IOJ&O
II.I
~ 5
a::
II.I
a::
::,
..J
er
LL.
4
~

4K 6K IOK
HOURS

PT• 200MW
Vc 11 IOV
CYCLE• 50/10
TA =25°C
PRODUCTION PERIOD
2nd HALF 1961
DISTRIBUTIONNOT SHOWN
0.47%

800 1000
@ HOURS

3.29
SEMICONDUCTOR RELIABILITY

2N705 FAMILY
PRODUCTION
PERIOO:
1960-1961

BACKBIAS@hs-c "eE0.2V VcE-7V}COMBINED

\ss•c VBE0,2VVCE-7V
SHADED AREA•80% CONFIOENC£
TOPNO •NO.OFFAILURES
BOTTOMNO. aNO.OFUNITS
LIMITS: INITIAL ENOOF LIFE
Iceo@ 5V a,.a MAX. s,.a MAX.
hFE@>Ic=IOMA
VcE•0.3V 30MIN. 20MIN.

OL-...1....-L..---1.-L-..L..-L.--'----L..-...1.--"
200 400 600 800 1000
® HOURS

_1_ ..
I
10
V V' 95 TH PERCENTILE

..,.,,
-/

8
I- Lo.-" - - 90 TH PERCENTILE
V
/
2N705 FAMILY
6 t-----+--+---i------+--t----t--t--+ PNP GERMANIUMMESA
0
m -----------+--+-+- ~i~~g:~~f/;029223
u
H ---1-+---+--+----t-t-----+--+--+ P~~~~~rl=~~IOD: THIRD
---1-+---+--+----t-t-----+--+---+ OVEN STORAGE • __
__________ _..,--+ TEST CONDITIONs:100°c
MEASUREMENT OVEN- - -
CONDITIONS:
4
l:cao®VcE•ISV

2-----+---+--+--+--l---+---+--+----t-+-- ________ _

1-----1-t---+--+--+-t------t----1- 50TH PERCENTILE

5 TH PERCENTILE

O.._.....___I._K
__ 2._K_._
___3._K__.___,4K---...__.5K_,.___.6K-,.__7...,K_..._8...,K_..._9...,K---'--IOK...,_...,
© TIME IN HOURS

330
 SEMICONDUCTOR RELIABILITY

200 I I I I
I
95th PERCENTILE
I I I
I I I I I I I I I I
180
2N705 FAMILY
PNP GERMANIUMMESA
LOT: 029222- 029223
160 AMT:93 UNITS
PRODUCTIONPERIOD:
THIRD QUARTER1960
140 OVEN STORAGE
TEST CONDITION IOO• C OVEN
MEASUREMfNTCONDITIONS:
hFE 0 \t• 3tN Ia •IMA
120

~ !!Dth p~..,..,."1'11 ~

80 .,,,,,..
....

60

5th PERCENTILE
40

20

0
IK 2K 3K 4K 5K 6K 7K 8K 9K IOK
@ TIME IN HOURS

10 "
V/
~
/" I
V
95 TH PERCENTILE.., /
/" /90
1

TH PERCENTILE
8
,~ / ,I
'\ / j 2N705 FAMILY
-
6
.'\ V
/
V PNP GERMANIUM MESA
LOT: 029205-029204
AMT: 87 UNITS
PRODUCTION PERIOD:
--
J
V
I THIRD QUARTER
INTERMITTENTLIFE
TEST CONDITIONS:
1960
-
,__

--
TA"25°C PW•ISOMW
0
CD
u
I Ve ••7.5V,Io a20MA
H MEASUREMENTCONDITIONS:
4
Iceo @) VcE= I5V

------
50 TH PERC£NTILE
2
- i-- r-

I I I I
- 5 TH PERCENTILE
I I

0
IK 2K 3K 4K 5K 6K 7K 8K 9K IOK
® TIME IN HOURS

331
SEMICONDUCTOR RELIABILITY

200

180
,,/
I I
95TH PE~EN~
I I I
-- -
2N705 FAMILY
V PNP GERMANIUM MESA
160 LOT: 029205-029204
AMT: 87 UNITS
PRODUCTIONPERIOD:
THIRD QUARTER 1960
140 INTERMITTEN LIFE
TEST CONDITION:
TA•25 •c,
PW• 150MW,
120 V1 •7.5, I 1=20MW
MEASUREMENTCONDITION:
hFE@Vc•3V,.Ia•IMA
...
...,oo
.&! I I I I I

50TH PERCENTILE

80
V
V

60

1/v r--,..r-,...._
40
r--,..
r---. 5TH PERCENTILE
~
-
20

0
IK 2K 3K 4K 5K 6K 7K BK 9K IOK
® TIME IN HOURS

RELIABILITY DATA FOR A GERMANIUM PNP MESA TRANSISTOR

Figure18.11

RELIABILITY DATA ON A SILICON NPN DIFFUSED

PLANAR PASSIVATEDTRANSISTOR
(Figure 18.12)
Graph A - As in most operating life tests at maximum rated power, this also displays
a rapidly decreasing failure rate.
Graphs B & C - The only appreciable change in leakage current or current gain at
full rated power out to more than 7000 hours is an increase in lc;Ru by the fringe
of the distribution.
12
2Nl613 FAMILY
1;::;:;;:;.i.---t----t---t--t PRODUCTIONPERIOD:196I
10 ~-H-+-+--+---l INTEi~{.TNM M~E Ve • sov IE • 13.3 MA
~
::,
-'"---+---+~ ~:DJg AREA ::ro/~.:&tfsCE BOTTOMNO.=NO.OF UNITS
0 8 INITIAL END OF LIFE
:c
IOMp.o 100 Mp.a
8::::: 6
.75 OF INTIAL
....
~
a:
II.I
a: 4
::,
d
~
~ 2

0.5K IK I.SK

® HOURS

332
 SEMICONDUCTOR RELIABILITY

5
4
,__ - 2Nl613 FAMILY
--
~

'3 -- J:NT. LIFE@BOOMW

Ve a60V IceoVS TIME
-- @60V LOT NO. 126404
2
-- QUANTITY - 27

I ...,...i.,
-
>
.
0
U>

>~ 10
90TH%
I
1-.,..
,/
V
I,-"...-

@
0
i7 - nyw
I 0
---
i" 6
~ 5
0 MEDIAN -
B4
t-t
'3 I '
20TH%
-
2
IOntO/a

I
IK 2K '3K 4K
@ HOURS

I I

40
-90TH%
--1---'l I
- - --- -
-----
80TH%
~
~- ~
~
r-

30 ....MEDIAN

I I
l&I
I&.
s::. -20TH%
r--i--.
~<2!!:!.!c-
20
2Nl613 FAMILY
INT OP LIFE'@ 800MW GOV- -
hFE VS TIME
--
'a) Vc=IOV ICal50MA
LOT NO. 126404 --
QUANTITY-27
IK 2K 3K 4K
@ TIME IN HOURS
RELIABILITY DATA FOR A SILICON DIFFUSED
PLANAR PASSIVATED TRANSISTOR
Figure 18.12

333
SEMICONDUCTOR RELIABILITY

REFERENCES
m Peck, D. S., Semiconductor Reliability Predictions from Life Distribution Data, Semiconductor
Reliability, p. 62, Engineering Publishers, Div. A. C. Book Co,, Elizabeth, N. J., 1961.
<:nGutzwiller, W., Thermal Fatigue and the G.E. 1N2154-60 Medium Current Silicon Rectifier,
Semiconductor Products Department, General Electric Co., Syracuse, N. Y., ( 1961 ).
c:o See Reference ( 8 ) .
w Battelle Memorial Institute, "Task 511, Leak Detection," Battelle Memorial Institute Report,
Signal Corps Contrnct DA-36-039-sc-13212.
<11> Hangstefer, J. B. and Dixon, L. H. Jr., Transistor Reliability, Electronic Equipment Engineering,
March '59 (p. 91-94), April '59 (p. 37-40), May '59 (p. 44-48), and June '59 (p. 69-72).
<11> Vezean, Waldo A., Some Applications of Monte Carlo Methods to.Failure Prediction, Proceedings
of the 6th Joint .Military Industry Guided Missile Reliability Symf}osium, Vol. 2, Feb., 1960,
pp. 22-31.
m de Mars, G., Some Effects of Semiconductor Surfaces on Device Operation, Semiconductor
Products, April '59, p. 24.
<"1 Atnlla, M. M., Bray, A. R., and Linder, R., Stability of Thermally Oxidized Silicon Junctions in
Wet Atmosphere, Proceedings of the Institute of Electrical Engineers, Vol. 106, Part B, Supp.
No. 17, pp. 1130-1137, March 1960.
10> Shockley, W., Problems Related to p-n Junctions in Silicon, Solid State Electronics, Jan. '61, p. 35.

00 > Bilinski, J. R. and Morill, R., Selecting Transistors for Radiation Environments, Electronics,
Dec. 25, 1959.
<m Miller, B., Industry Probes Nuclear Pulse Radiation, Aviation \Veek a11d Space Technology,
Aug. 8, 1960.
0 2 > Jones, L. F., Determination of Short Term Life Test Distributions, Semiconductor Reliability,
Vol. II, Engineering Publishers, Division A. C. Book Co., Elizabeth, N. J.
1131 Blakemore, G. J.; On the Use of Weibull Sampling Plans; Semiconductor Reliability, Vol. II.,
Engineering Publishers, Division A. C. Book Co., Elizabeth, N. J.
cu, Kao, J. H. K., A New Life Quality Measure for Electron Tubes; Transactions of the Professional
Group on Reliability and Quality Control of the IRE, Vol. PGRQC-7, p. 11, April 1956.
0 111 Philco Corp., Transistor Lot Acceptance Specification Based on a Constant Failure Rate, Specifi-
cation Number 43-028A, Lansdale Division, Philco Corp., 1961.
081 Epstein, B. and Sobel, M., Some Theorems Relevant to Life Testing From an Exponential Distri-
bution, Proceedings of the American Mathematical Society, Vol. 25, p. 373-381, 1954.
m, Peck, D. S., The Uses of Semiconductor Life Distributions, Semiconductor Relial,ility - Vol. II,
Engineering Publishers, Division A. C. Book Co., Elizabeth, N. J,
11" 1 Goldthwaite, L. R., Failure Rate Study for the Lognormal Lifetime Model, Proceedings of the
Seventh National Symposium on Reliability and Quality Control, Jan., 1961.
cu,, Bowker, A. H. and Lieberman, G. J., Engineering Statistics, Prentice-Hall, Inc., Englewood
Cliffs, N. J., Chapter 11, p. 372.

334
SILICON CONTROLLED
SWITCH

WHAT IS IT?
• silicon 4 layer PNPN structure ANODE
• all layers accessible
• T0-5 electrically isolated case
• military reliability
• industrial prices
• available in production quantities

WHAT FUNCTIONS CAN IT PERFORM?

Depending on the characterization it can be
used as CATHODE
• extremely sensitive NPNP controlled switch SYMBOL
(complement of SCR)
• extremely sensitive PNPN controlled switch
(SCR configuration)

l
TYPICAL
• NPN silicon transistor A JUNCTION
• PNP silicon transistor BREAKDOWN
VOLTAGES
• N type negative resistance (Trigistor, Tran-
switch) p
• S type negative resistance (Binistor) N
• four layer diode (Shockley Diode) Ge
• zener diode

WHAT ARE ITS APPLICATIONS?

• time delay generator C
• SCR trigger pulse generator STRUCTURE
• tone generator
• pulse generator
•
•
•
•
telemetry oscillator
sensitive voltage level detector
bistable memory element
binary counter
GcoGA
0 0

C O O A
• ring counter
• shift register
• relay driver BASING- BOTTOM VIEW
• indicator lamp driver
• low level SCR
• low level complementary SCR

335
SILICON CONTROLLED SWITCH

INTRODUCTION
The General Electric 3N58 series device (formerly ZJ93) is a silicon controlled
switch {SCS) designed for use in industrial and military digital computer and control
applications. It is a four layer (PNPN) device with all four layers accessible. It can
therefore be used as a PNPN controlled switch, NPNP controlled switch, NPN tran-
sistor, PNP transistor, N type negative resistance device, S type negative resistance
device (negative conductance), four layer diode, and zener diode. It is characterized
specifically as a PNPN and a NPNP device with designations 3N58 and 3N59.
Its TO-5 isolated case package, extremely high firing sensitivity, and forty volt
rating make it suitable for applications including sensitive voltage level detectors,
bistable memory elements, binary counters, shift registers, ring counters, telemetry
oscillators, time delay generators, pulse generators, tone generators, relay drivers, indi-
cator lamp drivers, SCR trigger generators, low level SCR and low level complemen-
tary SCR. The IRE semiconductor symbol for this device is shown in Figure 19.1.

A= ANODE
C = CATHODE
GA= GATE ADJACENT
TO ANODE
Ge= GATE ADJACENT
TO CATHODE

( B)

SYMBOLS FOR SILICON CONTROLLEDSWITCH

Figure19.1

This symbol offers a clear picture of the semiconductor structure of the device. In
circuit applications, however, the alternate symbol suggested by current silicon con-
trolled rectifier usage may be of help in visualizing the significance of the gates.

ALUMINUMWIRE FROM
TAB ON HEADER THE ANODE
CATHODE GATE GA

HOLES FOR HEADER LEADS

ALUMINUM WIRE
FROM GATE Ge THE----- SHADED AREAS ARE GOLD
DIFFUSED REGION
SLOT

CERAMIC DISC
METHOD OF CONSTRUCTION- TOP VIEW
Figure 19.2

336
 SILICON CONTROLLED SWITCH

CONSTRUCTION
The SCS is essentially an NPN diffused base transistor with a third junction to
form a PNPN device. The transistor structure is a bar approximately 10 mils in cross
section and 10 mils effective length. For mechanical strength, low thermal resistance,
electrical case isolation, and manufacturing ease, the bar is mounted on a ceramic disc
or fixed-bed mounting. This method of construction is shown in Figure 19.2 below.
A wafer of non-porous ceramic material which has the same coefficient of thermal
expansion as the pellet forms the base of the mechanical structure. Gold is deposited
on the disc in four areas to form electrical contacts. Header wires projecting through
holes in the disc are bonded to the disc with a gold-tin alloy. The transistor bar is
mounted across a narrow slot in the disc with the diffused base region over the slot.
The bar is alloyed into gold areas on either side of the slot. Aluminum wires alloyed
into the bar make the remaining two connections. The aluminum wire to the diffused
base forms the cathode gate (G,.). The other wire forms the anode (A) junction. Header
leads are made of kovar with a coating of 24 carat gold of 0.04 mil minimum thickness.
To ensure stability with life all parts are outgassed prior to capping in a nitrogen
atmosphere. Two gettering materials "molecular sieve" and fiber glass, used to absorb
any possible outgassing materials after capping, are firmly held at the top of the cap.
They absorb water vapor as well as many organic vapors. The case meets the T0-5
outline and has all leads electric-ally insulated from the case. The lead locations and
packaged dimensions are shown in Figure 19.3.
DIMENSIONS WITHIN
JEDECOUTLINE
r
,260MAX .ISOMIN
T0-5
.2SOMIN INOTEI)
j_
I01I h Thiszoneis a,ntrolled!or Iulo,
matichandling.
Thevariation in actual
1.s~ a~ I dizmeWwithinthiszoneshallIIGImud
.010.
4 LEADS ~370MAX__.,j
I01I :t1 Musuredtrcmmu.diamdircl
.017 !·is~OIA .360MIN theactualdeYiat.
INOTE3) 11111111 Thespecifiedleaddiameterap.
pliesin thezonebet'fflll .050and.250
fromthe baseseal 8etffln .250and.5
maximum cl .021diameterisheld.Outside
cflheseZ1111eSlheleaddiimetetisnot
controlled.

I 1
-1.200t.010 ~

T0-5 PACKAGE DIMENSIONS

Figure19.3

THERMAL CHARACTERISTICS
Since PNPN devices tend to turn on more readily at high temperatures the silicon
control switch is characterized to remain non-conducting, i.e., "block" current at its
maximum rated voltage while at its maximum rated junction temperature. Its dissipa-
tion rating is designed to avoid exceeding this maximum junction temperature. The
transient thermal resistance curve in Figure 19.4 permits calculation of the maximum
junction temperature for pulsed input power.

337
SILICON CONTROLLED SWITCH

0.24

0.22 ,,,,..- -
0.20
/
~
2
.....
!-> 0.18
/_
:/
I
... /
r
.., 0.16

zu
.!
0.14
/
Cl)
in 0.12
I
V
IIJ
a:
.J 0.10
ct
2
a:
II.I
~
0.08 I
I-
z..... 0.06
I
iii
z 0.04 /
! ./"I.I'
0.02

-- -L-----

TIME- SECONDS
10 100

TRANSIENTTHERMAL RESISTANCEJUNCTIONTO CASE- SCS 3N58 SERIES

Figure19.4
For single load pulses separated by more than 10 seconds the rise in junction tem-
perature (Th) is given by
Th= P rT
where rT is the transient thermal resistance at the time of the end of the pulse of power
P. For example, for a 20 microsecond pulse of 1 watt power Tb = (1000) (.005) = 5°C.
For repetitive pulses of equal amplitude the maximum junction temperature can
also be calculated from the transient thermal resistance. The method is covered in
detail in the General Electric Silicon Controlled Rectifier Manual.* However, a con-
servative estimate of maximum junction temperature is given by
T,max=TA+ p .!.
T
RT+ p rT
where P is the pulse power, TA the ambient temperature, t the pulse width, .,. the
period between pulses, RT the steady state thermal resistance, and rT the transient
thermal resistance at time t.
For pulses shorter than 20 microseconds the thermal mass of the junction controls
heating. The junction thermal mass is 2 X 10-0 joules per degree centigrade, i.e.,
2 X 10-0 watt-seconds will raise the junction 1°C. Illustrating this, a .1 µfd capacitor
charged to 40 volts on discharging into the SCS will raise the junction temperature by
T _ CV" •
" - 2
I
2 X 10-0
= 1oe
(.I) (1600) = 4 ooc
(4) (104 .

TWO TRANSISTOR ANALOGUEOF PNPN SWITCH

The two transistor analogue shown in Figure 19.5 is very useful in understanding
the operation of PNPN structures such as the SCS.
•See Chapter 1 Reference List

338
 SILICON CONTROLLED SWITCH

A
A
p

N o,
NPN

C
PNPN NPN-PNP TRANSISTOR
STRUCTURE EQUIVALENT ANALOGUE

TRANSISTORANALOGUEOF PNPN SWITCH

Figure19.5

The PNPN structure is considered to be equivalent to an NPN and PNP transistor

interconnected in a positive feedback configuration. The specific characteristics of each
junction can now be interpreted in transistor terms, taking advantage of the circuit
theory developed for transistors. Transistor and SCS terminology will be used inter-
changeably as required.
When the anode is positive with respect to the cathode the center junction (corre-
sponding to the transistor collectors) is reverse biased. In this case it can be shown
that anode to cathode current (IAc)is then given by IAc = 1- ~ro h
hl h:l
where Ieo is the
leakage of the center junction and hr.1 and hr.2 refer to the gains of Q, the NPN tran-
sistor and Qi the PNP transistor respectively. When hhl • hr.2 < 1, IAc is a relatively
small current hence the PNPN is said to be "blocking."
When h, .., • h,d = 1 the loop gain is unity and IAc as defined, becomes infinite.
In practice it increases to a value limited only by circuit impedance. At unity loop gain
PNPN structures turn "on" at a speed determined by the effective frequency response
of the two transistors. The condition (11 + (I: = 1 commonly used in PNPN literature
is identical to hr.1 • h, ..2 = 1. Current gain h, .. is a function of Vm:, le, VBEand tem-
perature as shown in Figure 19.6. These variables, alone or in combination may be
used to increase h,.. sufficiently to achieve unity gain.

I.c VeE TEMP.

PARAMETERSCONTROLLING
hr ..
Figure 19.6

The rise in hr .. with Vct: is the result of approaching the breakdown voltage of the
collector junction. As h,., increases it causes le to also increase. Therefore, raising the
anode voltage near breakdown results in unity loop gain and the device turning on.
The usual method of turning on the device is to increase le by applying a base current
to either transistor. In this manner the device may be turned on when the junction
voltages are well below breakdown. It is also possible to tum on the device by apply-

339
SILICON CONTROLLED SWITCH

ing forward bias voltage only. Theoretically, for a transistor, Ic =

h, .. Ico when the
base current is zero. Therefore, le increases from Iro to h, .. lco as the emitter junction
is forward biased. This latter value of le may be adequate to yield unity loop gain in
a PNPN device. Since h, .. and Ieo both increase with temperature then the sensitivity
to turn on increases with temperature. Anode to cathode characteristics for forward
bias are as shown in Figure 19.7.
+

FORWARDBIAS
( BLOCKING DIRECTI ON)

VAC +
ANODE TO CATHODE BLOCKING CHARACTERISTICS
Figure19.7

It is seen that only a small leakage current exists for low blocking voltages. As volt-
age is increased until it approaches the center junction breakdown, h, .. increases due
to its dependence on voltage. Unity loop gain is reached and VAc no longer increases.
It does not drop, however, until the loop gain can be unity due to h,., dependence on
current alone. As L. builds up to meet the above criteria V"c is essentially constant.
Unity gain may also exist with various combinations of I" and V.,c. This generates
plateaus in the "negative resistance" region between the breakdown voltage and the
forward conducting region, leading to partial switching if the chosen load line inter-

I
sects a plateau. Partial switching is avoided by turning the device on by a gate input
or by using a lower impedance load.

I: GATES FORWARD
BIASED
HIGH AGATE CURRENTS'
GATE ZERO I GATES REVERSE
CURRENT I i+-

I
v ✓
I I
I

---✓
BIASED
I

VAC +
BLOCKING CHARACTERISTICS
Figure19.8

Reverse biasing the gates raises the collector junction breakdown. Applying forward
bias to either or both emitter junctions lowers the breakdown voltage until in the limit
the characteristic resembles that of a forward biased diode. Once turned on the PNPN
switch stays on until the "holding current" is reached. At this current, loop gain falls
below unity and the switch turns off.
To tum off the SCS, the anode current must be reduced below the holding current.
This can be achieved either by actually reducing I., or by increasing lH, The usual
techniques for reducing I-' include reverse biasing the anode, diverting I., by a shunt
current path or incorporating the SCS in an under-damped tuned circuit.

340
 SILICON CONTROLLED SWITCH

To raise the holding current, loop gain is reduced by reverse biasing the gates.
Because of the inherent regeneration in a PNPN device, reverse bias is not easily
attained. In fact while the voltages seen on the device leads may show reverse bias,
because of resistance in series with the leads, the junctions may remain forward biased.
If, as is the case with the SCS, the PNP analogue transistor has much lower gain than
the NPN, the SCS can be turned off by diverting only a fraction of the anode current
through the NPN base lead (G,.). (For reasons discussed later this only applies to low
anode currents.) On the other hand, very nearly the full anode current is required by
G., to turn off the SCS.
When the anode is negative with respect to the cathode, the middle junction is for-
ward biased; the other two junctions reverse biased. The reverse biased junctions will
share the voltage on the basis of their breakdown voltages or leakage currents. Should
one of these junctions be shunted by a resistor as is common in many biasing circuits,
the full reverse voltage would be applied to the other junction. Figure 19.9 shows the
breakdown voltages that can be expected under various conditions of emitter junction
shunting.

RESISTOR '
SHUNTING /

I
0 2 EMITTER //

'v/
/
/
0 1 EMITTER
t
BOTH
SHORTED Q EMITTER
2
SHORTED \ BOTH
GATESOPEN
EMITTERS
SHORTED
REVERSEANODE TO CATHODECHARACTERISTICSAS A FUNCTION
OF GATE CIRCUIT
Figure19.9

GENERAL COMPARISON WITH OTHER SEMICONDUCTORS

The SCS can be used in some applications in place of four layer diodes, trigistors,
transwitches, unijunction transistors, controlled rectifiers and binistors. Therefore the
extensive literature on these devices is directly applicable to the SCS. Since the SCS
may replace such a variety of devices, the importance of the designer's viewpoint is
evident. That is, how he intuitively visualizes the mode of operation of the device,
channels his thoughts into specific circuit configurations. With this in mind, the com-
parisons that follow are aimed at offering the greatest insight into the similarities be-
tween these devices without dwelling on minor specification differences.

COMPARISONWITH SILICON CONTROLLEDRECTIFIER

The 3N58 is characterized essentially as a sensitive SCR. Figure 19.10 shows the
symbol equivalence.

341
SILICON CONTROLLED SWITCH

ODE GA(NOCONNECTION)~NODE

G~E GAT
~
Ge CATHODE CATHODE
scs SCR

CORRESPONDENCE
BETWEENSCS AND SCR SYMBOLS
Figure19.10

The SCS, being designed for low level logic and general industrial control and
computer switching, is characterized by low leakage current, anode currents below
0.5 amperes, voltage ratings below 60 volts, low holding currents, sensitive well defined
firing conditions and small physical size. Within these constraints both devices can
perform the same functions.
Some SCR applications apply a reverse bias to the gate junction. Generally the
gate must be clamped to avoid excessive dissipation. The SCS maximum gate current
ratings apply to the reverse bias on the gates as well as forward bias to fire. The SCS
firing sensitivity permits a high resistance to be connected in series with the gate to
minimize dissipation without the necessity for clamping diodes.
A 40 volt reverse bias can be applied to GA. To take advantage of this the SCR
circuitry can be adapted to a "complementary" configuration as suggested in the next
section.

COMPARISONWITH COMPLEMENTARYSCR
A PNPN structure always blocks in one direction only, i.e., when the P end is
biased positive. The complementary SCR therefore also blocks in the same direction
as the conventional SCR. It diHers from a conventional SCR in that the gate is adjacent
to the anode and fires the SCR when a negative pulse is applied to it.
ANODE ANODE
ALTERNATE
G SERIES DIODE
• --k" _ ..., GATE
(GATE)1 ..,-

( NO CONNECTION)
CATHODE CATHODE

S]_REVERSE
SERIESDIODEENHANCES
b
-,- VOLTAGECAPABILITIES
(SEE TEXT)

SCS COMPLEMENTARY SCR

CORRESPONDENCE
BETWEENSCSAND COMPLEMENTARY
SCRSYMBOLS
Figure19.11
An SCR is generally required to withstand reverse voltage. When the SCS is reverse
biased the cathode junction breaks down at about four volts. Higher reverse voltages
are therefore blocked by the anode junction. If a DC gate signal return exists between

34.2
 SILICON CONTROLLED SWITCH

GA and A, it is in parallel with the anode junction and appears as a reverse leakage
current. This is shown in Figure 19.9. This leakage current through the load can be
avoided by connecting a diode in series with the cathode as shown in Figure 19.11.
An alternate method is to connect a diode in series with the gate as shown. In this
case the gate can be used to tum off the SCS while Ge is used to tum it on.

COMPARISONWITH TRIGISTOR,TRANSWITCH
The trigistor and transwitch are similar in that they are PNPN devices capable of
stable blocking or conducting states without a maintaining input being required. They
can be switched to either state by an appropriate input. In SCR terminology the SCR
can be turned on and off from the gate. A positive pulse turns it on; a negative, off.
( COLLECTOR)
ANODE COLLECTOR

(BASE)

CATHODE EMITTER
(EMITTER)
SC S TRIGISTOR,TRANSWITCH
CORRESPONDENCEBETWEEN SCS AND TRIGISTOR, TRANSWITCH SYMBOLS
Figure19.12

The SCS can also be turned on and off by gates as indicated in Figure 19.12 above.
Ge will only tum off anode currents below about 4 ma. For anode current up to 50 ma
the load may be connected to cathode and GA used for tum off.

COMPARISONWITH FOUR LAYER DIODE

The four layer diode can be considered to be an SCS with no gate leads as shown
in Figure 19.13. The SCS, however, is not characterized in narrow ranges of forward
breakover voltage.
POSITIVE POSITIVE
TERMINAL TERMINAL
ANODE ADJUST
FOR DESIRED
BREAK<r,/ER
VOLTAGE

Ge
(NO CONNECTION)
CATHODE

scs FOURLAYER DIODE S CS EQUIVALENT

(Al FOURLAYERDIODE
181 (Cl

CORRESPONDENCEBETWEEN SCS AND

FOUR LAYER DIODE
Figure 19.13

343
SILICON CONTROLLED SWITCH

A diode of any desired breakdown voltage within the ratings of the SCR can be
synthesized as shown in Figure 19.13(c) by adding a voltage divider across the SCS.
When the anode voltage reaches the desired breakover voltage the divider is arranged
to supply the required gate firing input. Better stability with temperature and voltage
transients will result from returning the cathode end of the divider to a negative bias
voltage. In some applications it may be more convenient to connect the divider to
CArather than Cc.

COMPARISONWITH UNIJUNCTION TRANSISTOR

Physically the two components are different. However, both devices are capable
of generating negative resistances. The unijunction transistor is uniquely suitable for
timing and oscillatory applications based on RC charging networks. It uniquely com-
bines very low leakage current, low current to fire, circuit variable "breakover voltage"
and self-compensation for temperature or power supply variations. Its controlled high
holding current makes it suitable for delivering high energy pulses for SCR firing
circuits. The SCS on the other hand has a very low holding current making it more
suitable for low power bistable circuits. It can also be used for SCR firing provided the
load is AC coupled or some other precautions are taken to turn the SCS off. Figure
19.14 shows the voltage divider necessary to synthesize the unijunction transistor.
(BASE 2)

(EMITTER)
ANODE

BASE I

SC S EQUIVALENT UNIJUNCTIONTRANSISTOR

CORRESPONDENCE
BETWEENSCS AND
UNIJUNCTION
TRANSISTOR
Figure19.14

COMPARISONWITH BINISTOR
The binistor is very similar to the SCS in that both devices have leads connected
to all four semiconductor layers. The binistor is characterized specifically as a tran-
sistor with an extra control lead. While this characterization leads to many useful and
novel circuits it does not suggest to the circuit designer the SCR, trigistor, transwitch
and unijunction transistor applications of which the device is capable. Figure 19.15
shows the one-to-one correspondence between the binistor and SCS.

344
 SILICON CONTROLLED SWITCH

(INJECTOR)
INJECTOR
ANODE

COLLECTOR

(BASEi

CATHODE EMITTER

scs BINISTOR

CORRESPONDENCE
BETWEENSCS AND BINISTOR
Figure 19.15

In general, circuits designed for the binistor will operate with the SCS without
any circuit modification. SCS circuits, however, are capable of higher voltage, higher
dissipation operation.

DEFINITION OF TERMS USED IN SCS SPECIFICATIONS

BASIS FOR NOMENCLATURE
PNPN devices available at present do not have a common nomenclature. In part,
this is due to their different construction ranging from the two terminal four layer
diode to the four terminal binistor. SCR nomenclature on the other hand reflects the
surge problems associated with rectifier applications. SCS nomenclature permits the
reverse characteristics of all three junctions to be specified. The anode forward char-
acteristic and gate firing characteristics can also be specified fully. Figure 19.16 illus-
trates the principles used in assigning symbols.

A
f
:r

t--' v,

(HOLDING)

4>··
I VH
-v
Yao (BREAKOVER)
Xao
Ge VaoslSTATIC)
C Nt~~E- -P=E VeoolDYNAMIC)

ANODE TOCATHODE CHARACTERISTICS

NOTE -ABSENCE OF G INDENTIFIESANODE TO CATHODE
SYMBOLS.DOT IDENTIFIES OPERATINGPOINT.
BRACKETSINDICATEMEANINGOF SUBSCRIPTLETTER.

REVERSECHARACTERISTICS FORWARDCHARACTERISTICS

>--- VQAIa...-- - - - - - - --vo,. Io, ...

GA

Ge
N
>---Va

)---Vcu:
~
REVERSE~ AT !!fil
!CATHODE
GATE)
.
Ia----------V,VHIFtH

Ioc- - - - - - - --Vo,e

VOLTAGE
lGFC

ATGA: E TO FIRE
7ci'f"l4C>OEGil'El -

SCS NOMENCLATURE NOTE: G IDENTIFIESGATESYMBOi.$. LAST LETTER

IAOR Cl MAYBE DROPPEOIF NO AMBIGUITY
RESULTSIN SPECIFICCHARACTERIZATION.F
Figure 19.16 MEANS"FORWARD"
"FORWARD"
AS APPLIEDTO ANOOEAND
OR"FIRE"ASAPPLIED TO GATES.

345
SILICON CONTROLLED SWITCH

MAXIMUM RATINGS
Anode Blocking Voltage - With the anode forward biased, the anode blocking
voltage is the minimum static voltage at which the SCS will remain non-conducting. It
is the maximum voltage at which the SCS leakage current will not exceed a specified
value indicated in the anode blocking current rating.
Anode Reverse Voltage - With the anode reverse biased the anode reverse voltage
is the maximum voltage at which the SCS leakage current will not exceed a specified
value. The gates are generally biased as in the Anode Blocking Voltage Test. Where
the biasing resistors mask the true voltage breakdown of the junctions additional data
is supplied.
Gate to Cathode Reverse Voltage - The maximum voltage at which the gate leak-
age current will not exceed a specified current. All other leads are open circuited.
Continuous D.C. Forward Current -The forward current is the maximum anode
to cathode current when the device is turned on and is primarily limited by the dissi-
pation rating of the SCS. Gate current ratings are defined separately. This current can
be exceeded as is implied by the peak current forward current rating if precautions
are taken to limit the maximum junction temperature.
Peak Recu"ent Forward Cu"ent - Maximum forward anode to cathode current
when the device is on with specified time and temperature conditions. Peak current is
recurrent at 400 cps unless otherwise specified. For shorter duration peak currents
such as are characteristic of capacitor discharge the thermal mass rating determines
the permissible peak current.
Peak Gate Current - Maximum gate current with same time temperature and
recurrence as peak recurrent forward current. The same rating applies whether the
gate is forward or reverse biased.
Average Gate Cu"ent- Average gate current rating applies to both forward and
reverse gate current and is limited primarily by dissipation.
Operating Temperature Range-The operating temperature range is the range in
which the SCS will exhibit blocking characteristics under specified biasing conditions.
Life tests are used to ensure no failure mechanisms or degradation characteristics over
this temperature range.
Storage Temperature Range - Storage temperature range defines the temperature
range in which life tests have shown no failure mechanisms or degradation char-
acteristics. The SCS will not necessarily exhibit its blocking characteristic over the
whole range.
Dissipation -The maximum total power dissipation in an ambient of 25°C. The
rating applies to operation with free air cooling unless otherwise specified.

ELECTRICAL CHARACTERISTICS
Anode Blocking Cu"ent (I a) - Is is the anode current in the forward biased anode
while blocking voltage at a specified junction temperature and specific gate biases.
Gate Reverse Cu"ent (la lac laA)- Io is the leakage current in a reverse biased gate
with other electrodes connected as specified. Ioc is the leakage of the cathode junction;
IoA of the anode.
Gate Cu"ent to Fire (la, Ia,c Ia,A)- lov is the gate current required in the direc-
tion of forward gate bias to turn on a blocking anode under specified circuit conditions.
Gate Voltage to Fire (V aF V a,c V arA) - Vov is the gate voltage at which the SCS
turns on under specified circuit conditions.

346
 SILICON CONTROLLED SWITCH

Anode Forward Voltage (V ,) - Voltage from anode to cathode after SCS has fired
with specified gate biases and temperature.
Anode Holding Current (111)- lu is the minimum anode current at which SCS will
not turn off under specified circuit conditions and temperature.
DEFINITIONS
Fire - Undergo the transition from forward blocking to saturation. This is the
"turning on"of the SCS.
Static Voltage -A voltage which is applied gradually. Specifically a voltage applied
at a rate that if the rate were doubled there would be no change in the measurement
under test.
Dynamic Voltage - A voltage applied rapidly enough to induce changes in meas-
urements made under static conditions. Specifically, the breakover voltage is a func-
tion of the rate of rise of anode voltage.

GATE CHARACTERISTICS
The SCS has two gates: Ge and GA,Ge is the gate adjacent to the cathode and GA
is the gate adjacent to the anode. Both of these are effective in firing the SCS, therefore
it is essential that the conditions of both be specified in defining firing sensitivity.
Ge CHARACTERISTICS
Since the SCS is fabricated from an NPN transistor structure, Ge characteristics are
identical to common emitter input characteristics. The characteristics are shown in
Figure 19.17.

REVERSE BREAKDOWNVOLTAGE4 TO 6V REVERSE BREAKDOWNVOLTAGE 70 TO 120

rb' AT Io= 50p.A " 1000a rb' AT Io .. IOMA 11 40.Q
rb' AT Io= I MA "50A rb' AT lo " I MA ,.zoo.a
r
rb' AT 8 • -IMA • 5K rb' AT Ia z -IOMA •200.Q
dVGFc/dT " -2MV/ °C TURN OFF GAIN a I
TURN OFF GAIN • 2 TO 6

Ge CHARACTERISTICS GACHARACTERISTICS
Figure19.17 Figure19.18
When Ge is forward biased rh' shows the variation common to transistors. Minority
current How modulates the base resistance decreasing it at high currents. When Ge is
reverse biased modulation ceases and rb' increases. The reverse current out of Ge is
limited to about 1 ma before the gate is clamped to the cathode via the 5 volt emitter
breakdown voltage. This reverse current will tum off the SCS when IA<2 ma and G ...
is open, or IA<4 ma when GAis shorted to A.
GA CHARACTERISTICS
GA is the collector of the NPN transistor and therefore has a series "saturation"
resistance. Its characteristics are shown in Figure 19.18.
While reverse biasing G" readily turns off anode currents of 50 ma, turn off gain is
unity. The 2000 effective series resistance requires approximately 10 volts of reverse
bias to develop a 50 ma gate current. The tum off gain is essentially unaffected by
opening or shorting Ge.
FIRING CHARACTERISTICS
Four limit combinations of gate biasing are possible as shown in Figure 19.19.

347
SILICON CONTROLLED SWITCH

GATES OPEN Ge SHORTED GA SHORTED BOTH GATES

SHORTED

BREAKOVER VOLTAGE
0 TO 20 70 50 80
Vao VOLTS
REV£RSE VOLTAGE
80 80 4 0.5
VR VOLTS

IH MA 0 0.5 TOI 2 TO 3 2 T03

Iao MA(TO FIRE) 0 0.5 2 4

10 TO 60
IoFc MA (TO FIRE) -To1,.A
,.A

VGFC VOLTS (TO FIRE) 0.4 T00.6 0.5 TO 0.8

0.2 TO
IoFA MA(TO FIRE) 0 TO e,.A I.OMA

VGFAVOLTS (TO FIRE) 0.4 TO 0.6 0.6 T00.9

TYPICAL ANODE CHARACTERISTICSFOR SPECIAL

GATE BIASES
Figure19.19

It is significant that shorting out an emitter junction does not destroy the PNPN
characteristic. Figure 19.20 shows the location of Cc and A wires on opposite sides of
the bar. Anode current can readily forward bias Cc due to the cross-base resistance.
Similarly GA can be forward biased due to the ohmic "saturation resistance .. inherent
in this structure.

~
GOLD
REGION

EXPANDEDVIEW OF SCS STRUCTURE

Figure19.20

The shorted configurations are useful in decreasing sensitivity in the presence of

noise, high temperature, or dV/dt problems. SCS type 3N58 is essentially a "gates
open" characterization. The extremely low Ico of the center junction gives a 40 volt
minimum blocking voltage at 150°C while simultaneously offering very high sensitivity.
A negligible gate current is required to fire. Typically, forward biasing Cc is sufficient.
SCS type 3N59 is characterized with Cc shorted. This configuration offers high block-
ing and reverse voltage. Sensitivity is decreased sufficiently that a forward bias gate
current is always required to fire.

348
 SILICON CONTROLLED SWITCH

1.5 I I I I I I
3N58--- ..............
3N59-

~ 1.0
..J
0 - ........
>
I
r-""'... ,_..._
~

~0.5
-i- ..
,.. i,..,,_
"""'~ -........
i.....__
.. ....
I"" ,._

-50 0 50 100 150

TEMPERATURE-°C
FIRING VOLTAGE

1.0
....
t
(/)
........ I
""- ~~tvs9
~
iii 0.5
0
~'~) 1""'-
0:: ,...,
;
0::
3N58 (µ.A)
......_
0
0
u.
I&.
0
t-1
-0.5
-50 0 50 100 150
FIRING CURRENT

TYPICAL GATE FIRING CHARACTERISTICSVS. TEMPERATURE

Figure19.21
Figure 19.21 indicates the change in firing characteristics with temperature. The
firing voltage decreases with temperature as can be expected from the transistor
analogue analysis. The 3N59 firing current also decreases with temperature showing
the increased tendency to tum on at high temperatures. The typical 3N58 fires with
less than 0.1 ,ua input current over the whole range of temperature.
TURN-OFF CHARACTERISTICS
As was indicated in discussing gate characteristics Ioc reverse is limited to approxi-
mately 1 ma. Only currents in the range of 4 ma can be turned off with Ge. Turn off
gain is about 2.
G.t can tum off anode currents of 50 ma but the required gate voltage may be
impractical at this current level. Tum off gain is approximately 1.

ANODE TO CATHODE CHARACTERISTICS

Some anode to cathode characteristics or simply "anode characteristics" depend
strongly on gate biasing. These have been discussed in the gate characteristics section
to a large extent. Other anode characteristics such as the forward conducting voltage,

349
SILICON CONTROLLED SWITCH

the holding current, and reverse leakage are relatively independent of gate biasing.
The dV /dt or rate-of-rise of anode voltage problem, speed of turn-on, and recovery
time during turn-off will also be discussed in this section.
RATE EFFECT- dV/ dt
When anode blocking voltage is applied the capacitance of the middle junction
becomes charged. If the voltage is applied slowly the charging current is small and
can be ignored. If the anode voltage is applied rapidly, the charging current, as it flows
through the emitter junctions, may raise h,,. sufficiently to cause turn-on. Figure 19.22
indicates the middle junction capacitance is under 5 picofarads.
5.0 ,---.----------~----r---r--
SCS CENTER JUNCTION
.....
CAPACITANCE
4.0 ~- .......
--.----.----y----.---1----t---+---t---t
~
0. 90-TH PERCENTILE
~ 3.0 MEDIAN
6 10-TH PERCENTILE
2.0

IOV 20V 30V 40V 50V

VOLTAGE VAc (Ve)

CENTERJUNCTIONCAPACITANCE
Figure19.22

Another way of looking at this problem is to consider the equivalent analogue

transistors as being charge controlled devices. If the input charge is supplied at a rate
slow compared to the recombination time of the transistors, the SCS will block. If it is
supplied rapidly the transistors will only turn-on if the charge supplied is comparable
to the charge required to turn them on. The latter charge is determined by the fre-
quency response of the transistors.

w
C>
.:!
.J
0
i----
>
a: ....... __ !J_=~_12s
c
0

w
>
i4
w
a:
m.__ __________ _
dV 8 /dt-VOL TS/ SECOND

TYPICAL DYNAMIC BREAKOVER

CHARACTERISTICS
Figure19.23
Figure 19.23 illustrates typical SCS behavior. At "static" voltages the forward
breakover voltage is a function of gate biasing resistance. As dV / dt is increased the
breakover voltage drops to a plateau determined by the charge requirements discussed
in the previous paragraph. The gate resistor shunts some of the charge around the

350
 SILICON CONTROLLED SWITCH

emitter junction increasing its tolerance to dV/ dt. At high temperatures the device is
more sensitive therefore the dV/ dt charge introduced is more effective in lowering
the breakover voltage. The typical data in Figure 19.24 illustrates the above facts.
The breakover voltage shown is the plateau value using a 1 nanosecond risetime
voltage source.
MINIMUM DYNAMIC BREAKOVER
VOLTAGE IN

-3N58 CONFIGURATION 13V

-3N59 CONFIGURATION 35V
-3N58 CONFIGURATION WITH
VGc = -IV 50V
-3N59 CONFIGURATION WITH
VeA = +IV 80V

STATIC BREAKOVER VOLTAGE 80V

TYPICAL DYNAMIC BREAKOVERVOLTAGECHARACTERISTICSAT 25°C

Figure19.24
BREAKOVERVOLTAGE
The maximum breakover voltage is the breakdown voltage of the center junction.
Gate biasing and dV / dt invariably lowers this voltage. The breakdown voltage increases
0
with rising temperature but is within 10% of its 25°C value from -65°C to +1so c.
HOLDING CURRENT
Figure 19.25 shows the variation of holding current with temperature. The exist-
ence of le at 150°C indicates the device is still able to block in the forward direction.

I....
~

I I I I I I I I I I 1.5 I I I I I I
I I
3N58 .l.J...L 3N59 l.LL
90th PERCENTILE
"" .. I
90 th PERCENTILE

I.0
MEDIAN
,~10th PERCENTILE <t 1.0
' ......... ,, " MEDIAN
,10th PERCENTILE
717 ~ .... ,,
.... /V I:r .... . / "' ---....
....
~
'/ .... ~ ........
..._ H ....
... ....
... -....
7' ....c
0.5""' ,..._
/
- ... -~ - 0.5 ....
....~
,
--
-- -- ~

...._

-so 0 50 100 150 -50 0 50 100 150

TEMPERATURE-°C TEMPERATURE-°C

HOLDING CURRENT 111VS. TEMPERATURE

Figure19.25
FORWARDVOLTAGE
The forward voltage is relatively insensitive to temperature as shown in Figure
19.26. In calculating dissipation at high peak currents a conservative approximation
=
for V., is V., 1.1 + 5 IA,

351
SILICON CONTROLLED SWITCH

3.0

~ 2.0
.J
0
>
IF= I00MA
I
I
I
..
I I I I
--
I
IF=50MA
~ 1.0

-50 0 50 100 150

TEMPERATURE-°C
FORWARDCHARACTERISTICS
VS. TEMPERATURE
Figure19.26
REVERSELEAKAGECURRENT
At 25°C and rated voltage the leakage current is typically below 1 nanoampere
and never exceeds 0.1 microampere. At 150°C essentially all units still have under
1 microampere leakage.
BLOCKING LEAKAGECURRENT
The leakage current in the forward or blocking direction can be higher. At 25°C
and rated voltage it is essentially identical to the reverse leakage. As Figure 19.27
shows>at 150°C leakage currents are typically 0.5 microamperes.
c:x15
r-
-m
~

~10
w J

a: I
a: J
::> 1,/
0
90th PER~ENTILE
C) 5 ,,.j
z ~I"--,..._
.: ,.
~
u MEDiAN~
r-..._ ~
g 1 I I I
,;...._
m I.J.oot"""" , .... -
-50 0 50 100 150
TEMPERATURE - °C
BLOCKINGCURRENTVS. TEMPERATURE
Figure19.27
TURN-ON TIME
While fab is approximately 30 mes for the effective NPN transistor, the PNP is
significantly slower, fabbeing about 1 me. Delay and rise time of anode current depend
both on the gate and load currents. Figure 19.28 shows typical waveforms seen as the
currents are varied.

352
 SILICON CONTROLLED SWITCH

✓VBB
~ ~ IG ~ O_.
O VA~ \, ____~F
;
::c
I
I
'~;;;o Ge
? ~--sc_s___3_N_5_a
o I
__
z
a::
::,
-----------
TIME--+
I- ( a) ( bl
CIRCUIT DEPENDENCEOF TURN-ON TRANSIENT
Figure19.28
At low anode currents and high gate currents the SCS equivalent circuit is an NPN
transistor with its collector coupled to the load by a diode as shown in Figure 19.28(b).
The fast response time of the NPN drives it into saturation before the PNP transistor
becomes effective regeneratively. A gate current barely adequate to turn on the SCS
will result in a long delay time prior to a rapid turn on. For intermediate gate and load
currents the 3N58 may exhibit partial tum on followed by rapid regenerate tum on.
The 3N59 is fired by turning on the PNP section. Since it is inherently slow a large
gate current is necessary to minimize delay before firing. However, once the PNP
section becomes active, loop gain increases rapidly resulting in a tum-on time of less
than 20 nanoseconds. Figure 19.29 tabulates tum-on time to final load current for the
3N58 as a function of load current, gate current and temperature.

GATE CURRENT=20µ A GATE CURRENT=100µ A

LOAD CURRENT MA LOAD CURRENT MA

I 10 100 I 10 100

25°c 2.1 1.8 1.8 0.7 0.7 0.8

125 °C 1.7 1.6 1.7 0.7 0.7 0.8

TURN-ON TIME OF 3N58 (MICROSECONDS)

Figure19.29
RECOVERYTIME
Recovery time has been measured as a function of anode current and temperature.
Recovery time increases with both anode current and temperature as shown in Figure
19.30. There is no simple way to substantially speed up recovery time, consequently
the maximum speed of the SCS is limited to about 100 kcs.

353
SILICON CONTROLLED SWITCH

30 ,,
0
l&J
en
::l..
--
--
--
I
_ scs 3Nsa
_ IA=IOOMA
- ffo=IOK
I I

~~
,,
90th PEI cENTIL E
,, ~.,

t!J20 ~Iii""'"
:E ~.,,,,.
... L..oo.,,,,. ,,,,.
>-
~
~i-- ...
,,,,..... ~""""
--
-- --
___..
~ 10 MEDIAN .........

--
0 ~ J.-
0
l&J ·10th PERCENTILE
~ I I I I I I . .
-50 0 50 100 150
TEMPERATURE-DC

30
0
---- I I I I •

---
l&J SCS 3N58
en
::l..
~ 20
:E
---
----
IA=IOMA
R6 =1OK
I I I I I
"
..,.,.
,

---
I
.:: 90th PERCENTILE I.,.,
>-
~
L.K'

--
i.,,,,...-
~ 10 MEDIAN ~I •"
I I I~
0 -i--
0
l&J -- i- ... ~
1.-1-"r'I
~
i,-1""""

-
L.-

~ 1
10th PERCENTIL.E
I I I I I I • I
• 1-1-

-50 0 50 100 150

TEMPERATURE-DC

30
90th PERCENTILE
0
l&J
en \ ~ --MEDIAN
::l..
I
l&J 20
_ SCS3N5A
\\ ~10th PERCENTILE

"
:E
I- - IAc:IMA \
\
'\
' "
>-
~
l&J
- Rt; =IOK
\ \
\
' \
10
~

> \ \ \ ~.,,,,.
0 \ ~i-- .....

---
0 .,,,
l&J S• "" 7
~

-50 0 50 100
"
---... ...-

150
TEMPERATURE-DC
RECOVERY
TIME
Figure 19.30

354
 SILICON CONTROLLED SWITCH

MEASUREMENTOF ELECTRICALCHARACTERISTICS
The test conditions given in defining and specifying the electrical characteristics
suggest appropriate test circuits. It is possible, however, to perform semi-quantitative
measurements on the Tektronix 575 Curve Tracer rather than construct the special
test circuits. In particular the holding current, breakover voltage, forward voltage drop,
gate voltage and current, and junction breakdown voltages can be measured in this
manner. The appropriate control settings on the Tektronix 575 and the resulting typical
traces are discussed below.
The remaining electrical characteristics should be measured with special circuits
in order to obtain the necessary accuracy. For example, leakage currents are too low
in value to obtain desired accuracy on the Tektronix 575. Thus a Keithley ammeter and
associated circuitry may be used.
MEASUREMENTSON TEKTRONIX575
The control settings to measure the various characteristics on the Tektronix 575
are given in Figure 19.31. These suggested settings should be suitable for most units
at room temperature. Typical waveforms corresponding to these settings are shown in
Figure 19.32.

TEKTRONIX 575 SETTINGS FOR SCS ELECTRICAL TESTS

TEST SOCKET
COLLECTOR SWEEP BASE STEP GENERATOR SENSITIVITY
CONNECTIONS

a: l&I l&I
UNIT TEST •I- • 0::
~~
~;
0 0:: 0 l&I 0 ..J
I- UJ C, UJ Ill Z I-
~ <> zO
0 UJ
Ill I- ii: "'
I- z
C, ~~ ii: 4.
UJ 0
4. 0
UJ 0:: ~o 2~
UJ

0
..J
..J "'
m
I-
iLI.I "'
.J
0
4.
0 Ill
..l(i;
LI.I
g
.J "'
0::
0:: Ill
l&I -
111111
LI.I
"'
.J
0
4.
I- l&I
1/1..J
l&I
Ill
I- l&I
I/IN
I- ....
0:: •
1&1°' -~
> :::E o::o
0 0:: a: ~>

IH/Ve A Ge C + IOOK 0-200 IOK - OFF 0.1 10

VR A Ge C - IOOK 0-200 IOK - OFF 0.01 10

3N5B
VGe Ge
NO
CONN.
C - 2K 0-20 0.01 1.0

VF A Ge C + IK 0-200 IOK + .002 10 0.2

FULL
IGFIVGF Ge A C + IK 0-20 IOK + 10 CLOCK- 0.01
WISE
0.1

IH /Ve Ge-C GA A - IOOK 0-200 IOK - OFF 0.2. 10

VR Ge-C GA A + IOOK 0-200 IOK - OFF 0.01 10

3N59 NO
VGA GA CONN. A + IOOK 0-200 0.01 10

VF Ge-C GA A - IK 0-200 IOK - 0.2 10 0.2

FULL
lGFIVGF GA Ge-C A - IK 0-20 IOK - 10 CLOCK-
WISE
0.5 0.2

Figure 19.31

355
~ rn

~
°'
WAVEFORMSFOR :CH
SCS-3N58
VERTICAL SCALE-0.1 MA/ DIV
,.- WAVEFORM FOR VF
SCS-3N58
VERTICAL SCALE-10 MA/DIV I
j

I
r~ ....

i
(a) HORIZONTAL SCALE-IOVOLTS/DIV , (d) HORIZONTAL SCALE-0.2 V/DIV n
v80 .. a2v
I
VF (:IF a SOMA )"l.2V
I
I
~i-..
i
~
IH,. 0.24 MA VF (IF1:IOOMA)=l.4 V

~
/

0
WAVEFORMFOR VGFa :CGF rn

~=
SCS- 3N59 SCS- 3N58 I
VERTICAL SCALE- 0.2 MA/DIV I VERTICAL SCALE-0.01 MA/DIV '
(b) HORIZONTALSCALE-10 VOLTS/DIA

v80 1188V
• (e ) HORIZONTAL SCALE -0.1 V / DIV
I
•J
,
VGF "0.52V
,_.-,
:IH "0.48 MA IGF 11 0.0 MA

WAVEFORMFOR VGC
SCS-3N58 SCS-3N59
VETRICAL SCALE-0.01 MA/DIV VETRICAL SCALE-0.5 MA/DIV
(C) HORIZONTAL SCALE-1.0 V/DIV
,Jr-. (f ) HORIZONTAL SCALE -0.2 V / DIV
'/
I
V6c•5.9 VOLT VGF"0.8 V j
(READINGAT I 6 c• 201'A) IGF"0.8 MA I .,
I

'
WAVEFORMSFOR ELECTRICALTESTS ON TEKTRONIX 575 CRO
Figure 19.32
 SILICON CONTROLLED SWITCH

LEAKAGE
CURRENT
MEASUREMENTS
The fundamental circuit for making leakage current measurements is shown in
Figure 19.33. In particular the case of blocking current measurement is illustrated.
One simply adjusts the power supply until the VTVM reads 40 volts. The voltage must
be increased slowly to 40 volts to avoid firing the unit in the blocking condition. For
the same reason one may wish to set the meter initially in the "short-circuit., position
since only the lOK resistor limits the load current for the "on .. condition.

VTVM
SET TO
40V

KEITHLEY
METER

-=-LEAKAGE
CURRENTUsIn) MEASUREMENTS
Figure19.33

For measurements on the 13Al Rn= lOK. For the 3N59 unit Rn= 0. To measure
the reverse leakage current simply reverse the battery polarity from that shown in
the circuit.
DYNAMIC
BREAKDOWN
VOLTAGE
MEASUREMENTS
For these measurements a step voltage input with 800 n impedance is applied to
the SCS. This voltage was applied by means of a mercury relay switch with a rise time
of about LO nanoseconds. The basic circuits employed are shown in Figure 19.34.

s, s,

(bl
(al

CRO
CRO

CIRCUITFOR 3N 58 CIRCUITFOR 3N!l9

DYNAMIC
BREAKOVER
VOLTAGE MEASUREMENTS
Figure19.34

357
SILICON CONTROLLED SWITCH

In Figure 19.34 S1 is the mercury relay switch, Rn is lOK for both the 3N58' and
3N59. With no bias applied, the potentiometer, the lOK series dropping resistor, and
the 22.5 volt battery are removed for the 3N58. For the 3N59 Rn is also removed. The
CRO is a Tektronix 545 and a 0-100 volt regulated power supply was used to obtain
the anode to cathode voltages. The operation of the circuit is as follows. The voltage
from the power supply is increased until the unit conducts. The voltage applied to the
unit is a rectangular pulse. The power supply voltage is then decreased until the unit
just blocks again (this may be as low as 1/10 of the upper conduction voltage). This
value is then the "true" dynamic breakover voltage. The difference in the two values
is due to the fact that the collector capacitance develops and holds a charge while the
voltage is "slowly" increased. This charge minimizes the dV / dt effect.
TURN-OFFTIME MEASUREMENTS
In order to measure the tum-off time of the 3N58 one may use the circuit shown in
Figure 19.35. The operation of the circuit is as follows. When the switch touches the
upper position (that shown in the figure) capacitor C:i charges. At the same time C1
(which was previously charged to 10 volts) drives the anode to -10 volts and then
begins to discharge. If the SCS turns off, the anode voltage will rise to + 10 volts. C1 is
adjusted to the minimum value for turn-off and the tum-off time is measured.

•
HORIZON'mL SCALE• O.&,.stC/DMSION
To •0.9,.S

,-------------.----0+1ov

c1
.01Mf
IOIC

-6V

TURN-OFF TIME CIRCUIT FOR 3N58

Figure19.35

When the switch touches the lower position, C2 discharges driving the unit into
conduction again. At the same time, C1charges again so that the cycle may be repeated.
Note that the turn-off time, to, is defined as that time when the anode voltage
reaches zero or ground potential. This is illustrated in the waveform accompanying the
circuit. For precision one must use a decade capacitor with small incremental steps as
C1. As an example of suitable values, the following were found to give adequate results.
IA= 1 ma, RL = lOK: C1 = 0 - 200 µµf
IA= 10 ma, RL = lK: C1 = .009 - 0.015 µf
IA= 100 ma, RL = 10012: G, = 0.1 - 0.25 µf

358
 SILICON CONTROLLED SWITCH

SCS APPLICATIONS

+6V +6V INPUT

680K
L

3N58
I0-14V
RMS
(NC)
(u~ ,,,,.
L

3N58
,o~;v
(NC)
1(
A' A A
A A

220K
- 220K
-

ALTERNATE ALTERNATE
INPUT INPUT
ON /liTOV OFF AT OV
OFF AT-6V ON AT-6V

NOTE - Connecting A or A' to the appropriate gate permits lamp control by positive
or negative inputs. Lamp #344, 10 volts, 15 ma - Lamp #330, 14 volts, 80 ma.
LAMP DRIVER
(INCANDESCENT LAMP OPERATE ON AC WITH 3DµA MAXIMUM INPUT LOADING)
Figure 19.36
----1-----------1---------u + 12V

ALARM
RELAY
200Sl

ALTERATE
INPUT
A

IOOK Ge
IK TOIM
SET

Temperature, light, or radiation sensitive resistors up to 1 megohm readily trigger

alarm when they drop below value of preset potentiometer. Alternately, 0.75V at input
to 100K triggers alarm. Connecting SCS between ground and -12V permits triggering
on negative input to GA,
BASIC ALARM- VOLTAGESENSING CIRCUIT
Figure19.37

359
SILICON CONTROLLED SWITCH

_____ .,..._____________ ...,. _______ """"""l.----u+l2V

RELAY II 344 344 344

IOK 101( IOK

Any of several inputs pulls in common alarm relay with lamps giving visual indication
of triggering input. Low resistance lamps decrease input sensitivity. (See Figure 19.19.)

MULTIPLE
ALARMCIRCUIT
Figure 19.38

3.9K
0.2r1f
C
OUTPUT

220pf 220pf

IOK 22K
T SYNC 22K

NOTE -R1C determine half the period; RaC the remainder.

R1 =
Rs for square wave output.
Transient-free square or rectangular pulses are generated with equal and oppositely
phased outputs. Synchronization and phase control readily feasible.

SQUAREWAVEGENERATOR
Figure19.39

360
 SILICON CONTROLLED SWITCH

IOK

3-40V
SUPPLY VOLTAGE

Amplitude and frequency are variable with potentiometer setting. Frequency alone is
variable with supply voltage.
SAWTOOTHGENERATOR
Figure 19.40
-----------------~+24V

IOK

IOK

vo-f INPUT
2.0V
1.5MA

Positive or negative pulses are amplified without inversion. Low anode current is used
to ensure tum off.
PULSE AMPLIFIERS- STRETCHERS
Figure 19.41

361
SILICON CONTROLLED SWITCH

+24V 0------------- ......

.----------
IOOK
R

l.f"~0.01
i•o~•
3.0V
I.OK

470K

-6V
Short negative pulse initiates delay. When Ge becomes forward biased by voltage
divider connected to timing network RC the SCS fires terminating the delay. R, C, or
-6V bias can be varied to modulate delay. Replacing lM resistor with zener diode will
minimize dependence of delay on bias voltage. A transient free output is available
at GA,
TIME DELAY GENERATOR - PULSE ACTUATED
Figure19.42
,------------------ .... ----n+12v

IOK

---------1 r-o OUTPUT

47K

Lf

A negative gate to NPN transistor permits C to charge through R. When the' anode
becomes forward biased C discharges yielding negative and positive outputs. The 10
megohm resistor connected to Ge insures firing regardless of how large R is. Maximum
R is determined only by delay stability requirements with temperature.

TIME DELAY GENERATOR

- GATE ACTUATED
Figure19.43

362
 SILICON CONTROLLED SWITCH

IN3606
12V RMS
INPUT

IMEG

IN3606

The switch is normally closed charging C and causing the SCS to block. Delay is
initiated by opening the switch and discharging C through R. Since R is connected for
only half of each cycle the delay is lengthened beyond the RC time constant. Follow-
ing the delay the SCS conducts alternate half cycles.

TIME DELAY GENERATOR

- AC OPERATED
Figure19.44

INPUT

( NC)

=
SCS conducts when input exceeds +lV. It stays on if l1n 0.1 ma. It turns off when
= =
l1n 0. On turning on, VA is approximately -0.25V for 6.8K load. VA -3V for lK
load.
SCHMITT TRIGGER
(OUTPUT IS IN PHASE WITH INPUT)

Figure 19.45

363
SILICON CONTROLLED SWITCH

orr--,v
-
-7.r=,v
OFF

The output is in phase with the input signal.

BISTABLE MEMORY ELEMENT

Figure19.46
----------0+12v

3.9K

(NC)

WV ..fl.
(NC)

IK

The resistor divider connected between Qa and Q2 supplies In to Qa after input A trig-
gers it. It also prevents input B from triggering Q:iuntil Qa conducts. Consequently the
first B input pulse after input A is applied will supply current to Rr,.

PULSE SEQUENCEDETECTOR
Figure 19.47

364
 SILICON CONTROLLED SWITCH

2.ov
IL

.f1.

Unless inputs A and B (2 to 3V amplitude) occur simultaneously no voltage exists

across RL, Less than 1 microsecond overlap is sufficient to trigger the SCS. Coincidence
of negative inputs is detected with gates CAinstead of Cc by using the SCS in a com-
plementary SCR configuration.

PULSECOINCIDENCEDETECTOR
Figure19.48

+24Va-------------------------

1,1
SL 2N2193A

INPUT IOK

FIRST STAGE LAST STAGE

Low input power triggers counter. During normal counting the common anode voltage
never exceeds 3 volts. When the last stage turns off the anode rises towards +24 volts
turning on the first stage. The zener also resets the counter.

RING COUNTER
- INCLUDINGRESET
Figure19.49

365
SILICON CONTROLLED SWITCH

2N525

ltl
...n.. IOK

0.01

(NC) (NC)

FIRSTSTAGE LAST STAGE

Two independent load resistors R,. and R,.' are available at each stage. The output at
R,.' is free from commutating transients. The input pulse provides a dead band equal
to its width.
RING COUNTERWITH INDEPENDENT
OUTPUTSPER STAGE
Figure19.50

2N525

INPUT

l•I
Jl_

FIRST STAGE LAST STAGE

Triggering at G-' permits loads with c:ommon ground.

RING COUNTER- LOADSWITH COMMONGROUND

Figure 19.51

366
 SILICON CONTROLLED SWITCH

.--------------41-----~+ 15 V

o-~.-------------t-----t11--------~1-----a1----0+12v
INPUT
PULSE

3N59

INPUT STAGE FIRST STAGE SUBSEQUENT

STAGE

IN3606 IN3606

STAGEPULSE INPUTS

+121-..I
+6

The bistable input stage drives the first shift register stage. The charge on the cou-
pling capacitor determines which of the coincident shift pulses triggers the SCS pro-
ducing a shift to the right. Load resistors have a common ground.

SHIFT REGISTER CONFIGURATION

Figure19.52

367
EXPERIMENTERS
CIBCUITS

2000.n.
MILLER HEAD
LOOP PHONES
STICK
#6300
OR
EQUIV.

220K
ONE TRANSISTORRADIORECEIVER
Figure 20.1

MILLER 2K./\.
LOOP PHONES
STICK
*6300
OR
EQUIV.

TI-PRI 200KO
SEC. I K.n.
ARGONNE
3V ARIOO OR
+ ~- ......
,___Eo_u_iv_.
_,

TWO TRANSISTOR RADIORECEIVER

Figure 20.2

2NI07

365 2.5K EARPHONE

JJJ.tfd

'--------------4~+3
THREE TRANSISTOR RADIO RECEIVER
Figure 20.3

369
 r=
t!j
~ ~
~
I
I
;z
25µ.f I
6V I ;1
ti TO 5µ. f
I 6V
=
en
n
r ;
I
n
c::
.-c
I ~

68K ~, PHONE I
JACK
I en

(CRYSTAL I
PHONES} I

• • • BUILD RECEIVER
• TO THIS •POINT
•IF I • • • +•
FOR RELAY OPERATION IN REMOTE CONTROL
ONLY SPEECH RECEPTION IS DESIRED...., APPLICATIONS ADD THIS RELAY CIRCUIT.
c,-.021.dd(FOR 1300 C.P.S. TONE SELECT) I
R,-15 TO 47K (ADJUST TO OPTIMUM SENSITIVITY)
T-LAFAYETTE TR-98 INTERSTAGE TRANSFORMER OR TELEX
T-42 (PART#C-8642)DRIVER TRANSFORMER,OR EQUIVALENT.
L 1- 25 TURNS~ .26 WIREON CTC (CAMBRIDGE THERMIONICS CORP.)
TYPE LS6 (114" DIA.) CEAAMIC FORM WITH RED AND WHITE DOT CORE.
L 1-50p.h RF CHOKE. NATIONAL CO. TYPE R33-50
z
L:,-TYPE U50-21 TOROID COIL. (TOROTEL, INC., 5512 E. 110TH. c,
KANSAS CITY 37, MO.)

NON- TONE-
SELECT SELECT

CITIZENS BAND RECEIVER

Figure 20.4
 EXPERIMENTERS CIRCUITS

2000.n..
G.E. 2Nl07 HEAD
AUDIO PHONES

iUT -T+
3V
-
SIMPLE AUDIO AMPLIFIER
-
Figure 20.5

1µ.fd(3V) 2N107
2000.n
INPUT+ -
I 2Nl70
HEAD

J
PHONES

- 330K
R +3V

NOTE: ADJUST R FOR OPTIMUM RESULTS

DIRECT COUPLED"BATTERYSAVER"AMPLIFIER
Figure20.6

KEY

2NI07

+
1.5V

.47 100

3.0, I\.,
SPEAKER~ PHONES

CODE PRACTICEOSCILLATOR
Figure 20.7

---------------------- 371
 EXPERIMENTERS CIRCUITS

[
-=.45V
KEY

TO i~:~~
SPKR,iJ:i-- 100.ll ....__
____ ~--~-~IK_:_.n
_ _,

.~.
POS.I PHONES
POS.2 PHONES-SPEAKER
POS.3 SPEAKER

-
P-S
WIRINGDETAILS OF SW (BACK VIEW)
2
(MALLORY TYPE 3123J)

UNIJUNCTION TRANSISTOR CODE

PRACTICEOSCILLATOR
Figure20.8
NOTES:
RATE-ADJUSTABLE FROM 40(LOW LARGO) TO 220(HIGH PRESTO) BEATS PER MINUTE
R1-ADJUSTS HlGH RATE LIMIT 20K
R2 -ADJUSTS LOW RATE LIMIT --"·"-"v----------.-~ "'-er,
1
R 3 -IRC TYPE 013-328 RI
POTENTIOMETER (LOG TAPER) _h
150.0. -=..22 l/2V
SPKR-UTAH MODEL SP358 3.4 .{l V.C.
SIZE 3 1/2" MAGNET I OZ.
(HOWEVER,ANY SPEAKER
-!:
CAN BE USED). 2N2I60
UNIJUNCTION

25VDC
I20V NOMINAL
601'\J
<a)APPROX.4MA

UNIJUNCTION TRANSISTOR METRONOME

Figure20.9

372
 EXPERIMENTERS CIRCUITS

J
I2v~

GE 1485

U2.3V Ca (12.3V@
0.5 AMP) 0.5AMP)

R 1 - VARY FROM 47K TO 82K FOR DESIRED FLASH RATE

HIGH POWER LIGHT FLASHER

(FOR BOATS, AIRCRAFT, EMERGENCY VEHICLES, BARRICADES)
Figure 20.10

METER 0- .5 MA
CALIBRATED
0-6000 RPM

GE-4JZ4 X 8.28
e av NO.OF
IW CYLINDERS
4 6 8
CI (SEE C I IN ,,_fd. FOR 2
33 22 15
CYCLE ENGINE • •
CHARTS)
CI IN ,,_fd. FOR 4
CYCLE ENGINE .6B ·47 ·33

GENERAL AUTOMOTIVE IGNITION INFORMATION

TWO CYCLE FOUR CYCLE

4 CYL. 6 CYL. 8 CYL. 4 CYL. 6 CYL. 8 CYL.
SPARKS/REV. 4 6 8 2 3 4
SPARKS/SEC. AT 600 RPM 40 60 80 20 30 40
TIME/SPARK AT 600 RPM 25 MS 16.7 12.5 50 33.3 25
SPARK/SEC. AT 6000 RPM 400 600 800 200 300 400
TIME/SPARK AT 6000 RPM 2.5MS 1.67 1.25 5.0 3.33 2.5
CAMSHAFT SPEED TO EQUAL EQUAL EQUAL HALF HALF HALF
CRANKSHAFT SPEED
CAM DEGREES/SPARK 90° so• 45° 90° so• 450
CRANKDEGREES/SPARK 90° so• 45° 1800 120° 90°

ULTRA-LINEAR HIGH PRECISION TACHOMETER

(FOR AUTOMOTIVE TYPE IGNITION SYSTEMS)
Figure 20.11

373
EXPERIMENTERS CIRCUITS

IOK

+
-=-sv

15% FLASH DURATION60 FLASHES PER MINUTE

+
~6V

25% FLASH DURATION60 FLASHES PER MINUTE

22K

+
-=-Gv

50% FLASH DURATION 60 FLASHES PER MINUTE

FLASHER CIRCUITS
Figure 20.12

374
 EXPERIM£NTERS CIRCUITS

EVEREADY + ,,...,_
- __ .,.
itt:724 OR
EQUIVALENT 6V

SHURITE METER
0-3MA. F.S.760n
( J.B.T.INSTRUMENTS,
INC. NEW HAVEN 8,
CONNECTICUT}

NPN TEST SOCKET

INSTRUCTIONS FOR TRANSISTOR TEST SET

BATTERb
0
wefts INSERT 560 OHM RESISTORBETWEEN E AND C (EITHER SOCKET). IF METER
N T READ FULL SCALE, REPLACE BATTERY ( EVEREADY TYPE 724 OR
EQUIVALENT)
LEAKAG~ TEST: INSERT TRANSISTOR IN APPROPRIATE SOCKET. METER READING INDICATES
ONDITION WITH RESPECT TO LEAKAGE.
GAJN
TEST'DEPRESS GAIN BUTTON AND NOTE INCREASE IN METER DEFLECTION. AN IN-
CREASED DEFLECTION TO THE RIGHT EQUAL TO AT LEAST ONE DIVISION ON THE
GAIN SCALE COMPARED TO THE DEFLECTION DURING LEAKAGE TEST INDICATES
ACCEPTABLE CURRENT GAIN.
OPENSAND ~~~ tE~t) A SHORTED TRANSISTOR WILL BE INDICATED BY A FULL SCALE
MET L7!T N IN LEAKAGE TEST. AN OPEN TRANSISTOR WILL BE INDI-
CATED BY NO METER DEFLECTION IN BOTH LEAKAGE AND GAIN TESTS.

TRANS.ISTORTEST SET
Figure 20.13

375
EXPERIMENTERS CIRCUITS

.ee!!!l
Sl-3 POLE 6 POSITION NON-SHORTING S3-S4 NORMALLY OPEN PUSH-
SELECTOR SWITCH SWITCHES
M - IOOaA FULL SCALE METER
S2-4 POLE 2 POSITION SWITCH
RM-METERS INTERNAL RESISTANCE

ADJUST
TO SELECTOR
WHEN RESULT
TEST SWITCH SI
TO POSITION
Ico VcR • 6V I READ METER DIRECT
Ic Ia• 20,,_A 2 READ METER DIRECT
Ic Ie•IOO,,.A 3 READ METER DIRECT
IcEO VcE• 6V 4 READ METER DIRECT
IcES VcE• 6V 5 READ METER DIRECT
:IEo VEo•6V 6 READ METER DIRECT
CALCULATE:
:IC
hr£ I. 9 •20,,.A 2 hFE •re• METER READING
20"1
CALCULATE:

hFE I.e•IOO,,.A 3 hf'E •

:Ic
x; - METER READING
l00,a,A

CALCULATE: WHERE:
Ic1 - Ic2 :Ic1 • METER READING
h,, :t 8 •20,,.A 2 hh • 6 I.c2•METER READING
4x10-
WITH S4 CLOSED

CALCULATE:
h • I.c1 -:Ic2
h,- Ie•IOOp.A 3
" 2ox10- 1

WITH 1500 RESISTOR CONNECTED TO

6V.
BATTERY -- 4
C-E OF TEST SOCKET.FULL-SCALE METER
DEFLECTION WILL RESULT WHEN Ss
IS PRESSED.

SAFE AND SIMPLE TRANSISTOR TESTER

Figure 20.14

376
 EXPERIMENTERS CIRCUITS

The 100 µa meter is in a network which results in a nearly linear scale to 20 µa,
a highly compressed scale from 20 µa to 1 ma and a nearly linear scale to full scale at
10 ma. The network permits reading Ico, I.:o, Ict:11,and Ic•:o to within 10% on all tran-
sistors from mesas to power alloys without switching meter ranges or danger to the
meter movement.
By making Rm + R, equal to 12K the scale will be compressed only 1 µa at 20 µa.
Potentiometer R:1should be adjusted to give 10 ma full scale deflection. The scale can
then be calibrated by comparison with a standard conventional meter.
If the NPN-PNP switch is in the wrong prsition, the collector and emitter junctions
will be forward biased during the Ico and L-:otests respectively. The high resulting cur-
rent can be used as a check for open or intermittent connections within the transistor.
The test set also pleasures hF•:with 20 µa and 100 µa base current. Depressing the
h,.. button decreases the base drive 20% permitting hto to be estimated from the cor-
responding change in collector current. The tests are done with a 330f? resistor limiting
the collector current to approximately 12 ma and maximum transistor dissipation to
approximately 20 rnw. Therefore, this test set can not harm a transistor regardless of
how it is plugged in or how the switches are set.
"Battery test" has been designed to give full scale meter deflection of 10 ma when
the battery voltage is 6 volts. This is achieved by connecting 150 ohms from C to E
of the test socket. This test assumes precision resistors.

TONE-FREQUENCY
SENSITIVITYCONTROL

SELECTIVE
CIRCUIT

G-.x
11Lx'
I. WAVEMETER I. KEYINGMONITOR NOTE:
2.PARASITIC 2, CODEPRACTICEOSC. AN8 OR16OHMLOUDSPEAKER MAYBE USED.
DETECTOR BUTFOROPTIMUMSOUNDOUTPUTA HIGHER
SPEAKERIMPEDANCEIS NEEDED.

SENSITIVE BROADBAND CW KEYING MONITOR-

CODE PRACTICE OSCILLATOR- SENSITIVE AURAL/VISUAL
PARASITIC DETECTOROR WAVEMETER
Figure 20.15

377
EXPERIMENTERS cmCUITS
+12V
(AUTO FRAME)
330
+ 50 MFD
25V

0.33 + SMFD
sov
- 25V
AMPLIFIER
2N32I

330
6.2K

11 11
IN9I
NOTE:11 RIGHT
11 11 11
AND LEFT -I2V RIGHT
TAPPED OFF FROM RIGHT -I2V
AND LEFT FLASHER 11 11
LIGHTS ON AUTO DASH- LEFT
-I2V
BOARD. DIODES PREVENT
SHORT CIRCUIT. (A)

11 11
LEFT
+I2v
330 11
RIGHT
11

+I2v
IN9I

0.33
sov 4.7K

+ 50MFD
25V
330
6.2K

-12V
(AUTO FRAME)
NOTE: "RIGHT" AND ( B)
11 11
LEFT +12V TAPPEDOFF
FROM RIGHTAND LEFT FLASHER
LIGHTSON AUTO DASHBOARD.
DIODESPREVENT SHORTCIRCUIT.
Provides audible tum signal indication to insure signals are off after turn. Allows
driver to keep attention on road at all times. Dash indicator lights need never be
consulted.
AUDIBLE AUTO SIGNAL MINDER
Figure20.16

378
READER'S LIST

The following list of publications includes books pertaining only to semiconductors

and closely related subjects. This list has been compiled so the interested reader can
see just what books are available to him, the price, and where further information
regarding the books may be obtained. Prices as shown may or may not be accurate
since prices are always subject to change.
Some books here listed contain quite extensive bibliographies. For example, the
Handbook of Semiconductor Electronics,edited by Lloyd P. Hunter contains 68 pages
of references covering the period from 1936 through 1955. Such books as Principles of
TransistorCircuits and TransistorCircuit Engineering edited by Richard F. Shea also
contain extensive reference lists.
ABC's of Transistors Design of TransistorizedCircuits
Sams $1.25 for Digital Computers
Advances in Semi-conductorScience Pressman, A. I.
Brook, H., - General Editor Rider (1959) $9.95
Pergamon (1959) $15.00
An InternationalJournalfor Transistor ElectricalEngineering Materials
and other Solid-State Devices Dekkar, A. J.
Crawford, F., Editor-in-Chief Prentice-Hall (1959) $6.50
Pergamon $40.00/annum Electric Conduction in Semiconductors
An Introduction to the Theory and and Metals
Practiceof Transistors Ehrenberg, W.
Tillman, J. R., and Roberts, F. F. Oxford (1959) $10.10
Wiley (1961) $8.00 ElectronicSemiconductors
Spenke, E.
Basic Electronics- Vol. 6 McGraw (1958) $11.00
VanValkenburgh, Nooger & Neville
Rider (1960) $2.90 Electronic Tubes and Semiconductor
Basic Radio - Vol. 5 (Transistors) Elements- UniversalVade-Mecum
Tepper, M. Pergamon Vol. 1 (1961) approx. $20.00
Rider (1960) $1.90 Vol. 2 (1962) approx. $20.00
Basic Theory and Application of Electronsand Holes in Semiconductors
Transistors Shockley, W.
Technical Manual 11-690 VanNostrand (1950) $9.75
Department of the Army - Electron Tubes and Semiconductors
u. s. Govt. (1959) $1.25 DeFrance, J. J.
Basic Transistors Prentice-Hall (1958) $9.00
Schure, A.
Rider (1961) $5.50 Experiments in Electronics
Evans, W. H.
British TransistorManual Prentice-Hall (1959) $6.75
Bradley, E. N.
Norman Price Pub. Ltd. (1959) 12s6d
also Wehman $3.00 Feedback and Stability of Junction
TransistorCircuits
loawa State College of Agriculture &
Crystal Rectifiers Mechanical Arts,
Torrey, H. C. and Whitmer, C. H. (Engineering Experimental Station,
McGraw (1948) $8.50 Ames, Iowa) (1954) $1.25
CrystalRectifiersand Transistors FundamentalPrinciplesof Transistors
Molloy, E., Editor Evans, J.
British Book Service (1954) $3.60 VanNostrand (1958) $6.75

379
READER'S LIST

Fundamentals of Transistor Physics Philips Gloeilampenfabrieken,

Gottlieb, I. M. Semi-conductors
Rider (1958) $3.50 Philips (1959) 3.50 fl
Fundamentals of Transistors Photo and Thermoelectric EDects in
(2nd. Edition Revised & Enlarged) Semiconductors
Krugman, L. M. Tanc, J.
Rider (1958) $3.50 Pergamon
Physics of Semiconductors
Handbook of Semiconductor Electronics (revised & enlarged edition)
Hunter, L. P., Editor Joffe, A. F.
McGraw (1956) $14.00 Academic Press (1960) $12.50
Handbook of Transistor Circuit Design Pin-Point Transistor Troubles in
Pullen, K. A. 12 Minutes
Prentice-Hall (1961) $13.00 Garner, L. E.
Coyne (1959) $5.95
International Transistor Practical Transistors and Circuits
Substitution Guidebook Kendall
Pullen, K. A. Wehman $1.00
Rider (1961) $1.50 Practical Transistor Servicing
Introduction to Junction Transistor Caldwell, W. C.
Theory Sams (1960) $2.95
Middlebrook, R. D. Preparation of Single Crystals
Wiley (1957) $8.50 Lawson, W. D., and Nielson, S.
Introduction to Semiconductors Academic Press (1958) $8.80
Dunlap, W. C. Principles of Transistor Circuits
Wiley (1957) $11.75
Shea, R. F.
Introduction to the Theory and Practice Wiley (1953) $12.75
of Semiconductors
Shepard, A. A. Principles of Semiconductor
Ungar (1959) $4.75 Device Operation
Jonscher, A. K.
Introduction to Transistor Circuits Wiley (1960) $5.00
(2nd. Edition)
Cooke-Yarborough, E.H. Principles of Semiconductors
Interscience (1960) $3.50 Scrogg_ie,M. G.
Iliffe (1961) 21s
Industrial Transistor and Semiconductor
Handbook Principles of Transistor Circuits
Tomer, R. B. (2nd. Edition)
Sams (1961) $4.95 Amos,S. W.
British Book Service (1961) $5.25
also Rider (1959) $3.90
Junction Transistor and Its Applications Progress in Semiconductors
Wolfendale, E., Editor Gibson, Alan F. and others
Macmillan (1958) $7.50 Wiley (1956) Vol. 1 $8.00
Junction Transistor Electronics (1957) Vol. 2 $10.50
Hurley, R. B. (1958) Vol. 3 $8.50
Wiley (1958) $12.50 (1960) VoL 4 $10.50
(1961) Vol. 5 $11.00
Junction Transistors in Pulse Circuits
Neeteson, P.A. Properties, Physics, and Design of
Macmillan (1960) $5.50 Semiconductor Devices
Shive, J. N.
VanNostrand (1959) $9.75
Metallic Rectifiers and Crystal Diodes
Conti, T. Radio, Television, Industrial Tube,
Rider (1958) $2.95 Transistor and Diode Equivalents
Modem Transistor Circuits Handbook
Carroll, J. M . Babani, B. B.
McGraw (1959) $8.50 Bernards (1960) 9s6d

380
 READER'S LIST

Rectifying Semiconductor Contacts Semiconductors - 3rd. Edition

Henisch, H.K. Wright, D. A.
Oxford U. P. (1957) $11.20 Methuen (1958) 8s6d
Reference Manual of Transistor Circuits Semiconductor Surface Physics
Mullard Overseas Ltd. (1960) 12s6d Kingston, R. H., Editor
Univ. of Pa. (1956) $8.50
Repairing Transistor Radios
Libes, S. Semiconductors: Their Theory and
Rider (1960) $3.50 Practice
Gaudet, G., and Meuleau, C.
Essential Books (1957) $18.90
Selected Semiconductor Circuits
Handbook Servicing Transistor Radios
Schwartz, S., Editor 8 Volumes
Wiley (1960) $12.00 Sams $2.95 each
Semiconducting III-V Compounds Servicing Transistor TV Receivers
Hilsum, C. and Rose-Innes, A. C. Sams (1961) $4.50
Pergamon (1961) $10.00 Solid State Physical Electronics
Semiconductor Device Physics VanDerZiel, A.
Nussbaum Prentice-Hall (1957) $9.75
Prentice-Hall (1962) $8.25
Semiconductor Devices The Physical Theory of Transistors
Turner, R. P. Valdes, L. B.
Holt (1961) $6.95 McGraw (1961) $10.95
Semiconductor Devices and Theory of Noise in a Multidimensional
Applications Semi-conductor with a P-N Junction
Greiner, R. A. Solow, M.
McGraw (1961) $12.50 Catholic University of Am. Press
Semiconductor-Diode Parametric (1957) $1.25
Amplifiers The Surface Chemistry of Metals and
Blackwell, L. A., and Kotzebue, K. L. Semiconductors
Prentice-Hall (1961) $6.75 Gatos, H. C., Editor
Semiconductor Reliability Wiley $12.50
Shwap, J. E., and Sullivan, H. J., 1'he Transistor
Editors Bell Telephone Laboratories, Inc. (1951)
Eng. Pubs. (1961) $8.50
Transistor Audio Amplifiers
Semiconductors Shea, R. F.
Hannay, N. B., Editor Wiley (1955) $7.00
Reinhold (1959) $15.00
Transistor (Audio Frequency) A. F.
Semiconductors Amplifiers
Schon, M., and Welker, H. Jones, D. D., and Helboume, R. A.
lnterscience (1958) $16.50 Philosophical Library (1957) $6.00
Semiconductors Transistor Circuit Analysis
Smith, R. A. Joyce, M. V., and Clarke, K. K.
Cambridge (1959) $12.50
Addison-Wesley (1961) $10.75
Semiconductors - Vol. 1 Transistor Circuit Analysis & Design
Desirant, M., and Michaels, J. L.,
Editors Fitchen, F. C.
Academic Press VanNostrand (1960) $7.50
Semiconductors and Transistors Transistor Circuits
Schure, A. Cattennole, K. W.
Rider (1961) $2.90 Macmillan (1959) $14.00
Semiconductors and Transistors Transistor Circuits
Warschaver, D. M. Turner, R. P.
McGraw(1959) $7.00 Gernsback (1957) $2.75

381
READER'SLIST

Transistor Circuits and Applications Transistors and Crystal Diodes

Carroll, J. M. Bettridge, B. R.
McGraw (1957) $8.00 Wehman (1954) $1.00
Transistor Circuit Engineering Transistors and Other Crystal Values
Shea, R. F ., Editor Scott, T. R.
Wiley (1957) $12.00 Oxford U. P. (1955) $7.20
Transistor Circuit Handbook Transistors and Their Applications in
Garner, L. E., Jr. TV and Radio-Electronics
Coyne $4.95 Coyne $1.50
Transistor Circuit Manual Transistors in Radio, Television and
Lytel, A. Electronics - 2nd. Edition
Sams (1961) $4.95 Kiver, M. S.
Transistor Electronics McGraw (1959) $7.95
DeWitt, D., and Rossoff,A. L. Transistor Substitution Handbook-
McGraw (1957) $8.00 Revised
Transistor Electronics Sams (1961) $1.50
Lo, A. W., and others Transistor Techniques
Prentice-Hall (1955) $12.00
Staff-Gernsback Library, Inc.
Transistor Engineering Reference Gernsback (1956) $1.50
Handbook
Marrous, H. E. Transistor Techniques
Rider (1957) $9.95 Leahrman, H.
Gernsback (1957) $1.50
Transistor Handbook
Bevitt, W. D. Transistor Technology
Prentice-Hall (1956) $9.00 Biondi, F. J ., Editor
Bell Telephone Laboratories
Transistor Logic Circuits VanNostrand Vol. 1 & 2 $17.50 each
Hurley, R. B. (1958) Vol. 3 $12.50
Wiley (1961) $10.00
Transistor Theory and Circuits
Transistor Physics and Circuits Made Simple
Riddle, R. L., and Ristenbatt, M. P. Pollack, H.
Prentice-Hall (1957) $10.00 Am. Electronics (1958) $1.75
Transistor Profects Transistor Theory and Practice
Radio-Electronics Magazine (2nd. revised edition)
Gemsback (1960) $2.90 Turner, R. P.
Transistors Gernsback (1958) $2.95
Coblenz, A., and Owens, H. L. Transistors Work Like This
McGraw (1955) $6.50 Lehrburger, E.
Transistors Roys Publishing (1957) $2.50
Gartner, W.W. Tube and Semiconductor Selection
VanNostrand (1961) $12.50 Guide
Transistors Kroes, T. J.
Gillie, A. Cleaver-Hume (1961) 12s6d
Prentice-Hall (1959) $7.95
Transistors
StaJf-Gernsback Library, Inc.
Gemsback (1961) $1.95 Vacuum Tube and Semiconductor
Electronics
Transistors Millman, J.
RCA Laboratories (1956) $4.50 McGraw (1958) $10.75
Transistors and Active Circuits Vacuum-Tube Circuits and Transistors
Linvill, J. G., and Gibbons, J. F. Arguimbau, L. R.
McGraw (1961) $14.50 Wiley (1956) $10.25

382
 READER'S LIST

DIRECTORYOF PUBLISHERS
Academic Press, Inc. Essential Books, Inc.
111 Fifth Avenue 1600 Pollitt Drive
New York 3, New York Fair Lawn, N. J.
Addison-Wesley Publishing Co., Inc.
Reading, Massachusetts (Ungar) Frederick Ungar Publishing Co.
131 East 23rd Street
American Electronics Co. New York 10, New York
1203-05 Bryant Avenue
New York 59, New York Gernsback Library, Inc.
154 West 14th Street
(Roy) A. N. Roy Publishers New York 11, New York
30 East 7 4th Street
New York 21, New York Holt, Rinehart & Winston, Inc.
383 Madison Avenue
Bernards (Pub.) Ltd. New York 17, New York
77 The Grampians (Sams) Howard W. Sams Co., Inc.
Western Gate, 1720 East 38th Street
London, W.6 Indianapolis 6, Ind.
(See Bobbs-Merrill Co., Inc.)
Bobbs-Merrill Co., Inc.
1720 East 38th Street Iliffe Books Ltd.
Indianapolis 6, Ind.
(see Howard W. Sams Co., Inc.) Dorset House
Stamford Street
British Book Service Ltd. London, S. E. 1
Kingswood House Interscience Publishers, Inc.
1068 Broadview Avenue 250 5th Avenue
Toronto 6, Canada New York 1, New York

(Rider) John F. Rider, Publisher, Inc.

Cambridge University Press 116 West 14th Street
32 East 57th Street New York 11, New York
New York 22, New York
(Wiley) John Wiley & Sons, Inc.
Catholic University of America Press 440 4th Avenue
620 Michigan Avenue, N. E. New York 16, New York
Washington 17, D.C.
Cleaver-Hume Press, Ltd. Macmillan Co., Publishers
Publishing Division 60 5th Avenue
31 Wrights Lane New York 11, New York
Kensington, London, W. 8 McGraw-Hill Book Co., Inc.
330 West 42nd Street
Constable & Co., Ltd. New York 36, New York
10-12 Orange Street
London, W. C. 2 Methuen & Co., Ltd.
36 Essex Street, Strand
Coyne Electrical School London, W.C.2
1501 Congress Parkway
Chicago 7, Illinois Mullard Overseas, Ltd.
Mullard House
Torrington Place
D. VanNostrand Company, Inc. London, W. C.1
120 Alexander Street
Princeton, New Jersey Norman Price Publications, Ltd.
283 City Road
London, E. C. 1
Engineering Publishers
350 Morris Avenue - Box 2 Oxford University Press
Elizabeth, N. J. 1600 Pollitt Drive
(Books distributed by Reinhold) Fair Lawn, New Jersey

383
READER'SLIST

Pergamon Press, Inc. Reinhold Publishing Corp.

122 East 55th Street 430 Park Avenue
New York 22, New York New York 22, New York
Philip's Gloeilampenfabrieken,
Tech. & Scientific Lit. Dept. University of Pennsylvania Press
Kastanjelaan, 3436 Walnut Street
Eindhoven, Netherlands Philadelphia 4, Pa.
Philosophical Library, Inc. U. S. Govt. Printing Office
15 East 40th Street Washington 25, D. C.
New York 16, New York
Prentice-Hall, Inc. Wehman Bros.
Route9W. 712 Broadway
Englewood Cliffs, N. J. New York 3, New York

AdditionalBookListings:
Basic Transistor Course
Kenian, P. R.
Gemsback
Fundamentals of Semiconductors
Scroggie, M. G.
Gemsback $2.95
How to Fix Transistor
Radios and Printed Circuits- 2 Vols.
Lane, L. C.
Gemsback $3.20 per Vol.
or $5.90 both.
Servicing Transistor Radios
D'Airo, L.
Gernsback $2.95
Simplified Analysis and Application
of the Junction Transistor as a
Circuit Element
Crib, B. F.
Philamon Laboratories, Inc.
(Westbury, L. I., N. Y.) (1957) $ .50

384
TRANSISTOR
SPECIFICATIONS

INTRODUCTION
This chapter consists of three parts:
Part 1 - G.E. TRANSISTOR AND DIODE SELECTION
CHARTS ................................... Beginning on page 386
Part 2 - G.E. TRANSISTOR AND DIODE OUTLINE
DRAWINGS ............................... Beginning on Page 406
Part 3 - REGISTERED JEDEC TRANSISTOR TYPES WITH
INTERCHANGEABILITY INFORMATION ..... Beginning on page 412
Part 1 begins with a numerical type index of the more than 280 General Electric
transistors and diodes as described in the Selection Charts that follow. The index gives
the page where more complete electrical specifications can be found. Mechanical and
physical specifications of any General Electric transistor or diode herein listed will be
found in Part 2, Outline Drawings. Outline drawing numbers appear either directly
under Selection Chart titles, or directly following the type number.
Part 3, the Registered JEDEC (Joint Electron Devices Engineering Council)
Transistor Types Section has been completely revised and brought up to date. The
chart contains over 1200 transistors numerically listed with pertinent electrical data
given for each transistor. Comparable General Electric replacement type numbers along
with outline drawing numbers will be found in the far right column.
Additional electrical and physical information for any General Electric Transistor
or Diode is available on individual specification sheets (See Chapter 3). Such informa-
tion may be obtained on request from the Semiconductor Products Department of the
General Electric Company.

TO FIND GENERALELECTRIC TURN TO PAGE

Numerical Type Index.......................................... 386
Silicon Unijunction Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Silicon Planar Passivated Transistors - TO-5 Pkg. . . . . . . . . . . . . . . . . . . . . 388
Silicon Planar Epitaxial (PEP) Transistors - TO-5 Pkg. . . . . . . . . . . . . . . 389
Silicon Planar Epitaxial Passivated ( PEP) Switches - TO-18 Pkg.. . . . . . 390
Silicon Planar Amplifiers -TO-18 Pkg... . . . . . . . . . . . . . . . . . . . . . . . . . . 390
Silicon Planar Switches -TO-18 Pkg. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
Silicon Mesa NPN Power Transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
Silicon Grown Diffused NPN Transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . 394
Silicon NPNP Low Current Controlled Switches . . . . . . . . . . . . . . . . . . . . . 396
Germanium Mesa Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
Germanium Alloy PNP Transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
Germanium Alloy NPN Transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
Germanium Rate Grown NPN Transistors. . . . . . . . . . . . . . . . . . . . . . . . . . 401
Silicon Signal Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Tunnel Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
Back Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
Registered JEDEC Transistor Types with Interchangeability Information . 412

385
 TYPE INDEX
TYPE PAGE TYPE PAGE TYPE PAGE TYPE PAGE

Diodes 2N323• ..... : . 398 2N657 ........ 392 2Nl671A 387

2N324• ....... 398 2N657A ...... 392 2Nl671B 387
1N3063 ....... 402 2N332 ........ 394 2N696 ........ 388 2Nl694 ....... 401
1N3218 ....... 404 2N332A ...... 394 2N697 ........ 388 2Nl711 ....... 388
1N3218A . . . . . . 404 2N333 ........ 394 2N698 ........ 388 2Nl889 ....... 388
1N3219 ....... 404 2N333A ...... 394 2N699 ........ 388 2Nl890 ....... 388
1N3219A . . . . . . 404 2N334 ........ 394 2N705 ........ 397 2N1893 ....... 388
1N3804 ....... 402 2N334A ...... 394 2N706 ........ 390 2Nl924 ....... 399
1N3805 ....... 402 2N335 ........ 395 2N706A ...... 390 2N1925 ....... 399
1N3808 ....... 402 2N335A ...... 395 2N708 ........ 390 2N1926 ....... 399
1N3807 ....... 402 2N335B ...... 395 2N710 ........ 397 2Nl983 ....... 388
1N3808 ....... 402 2N338 ........ 395 2N711 ........ 397 2Nl984 ....... 388
1N3809 ....... 402 2N338A ...... 395 2N711A ...... 397 2Nl985 ....... 388
4JF1-MTD-l 404 2N337 ........ 395 2N711B ...... 397 2N2017 ....... 392
MTD-2 404 2N337A ...... 395 2N717 ........ 391 2N2049 ....... 388
MTD-3 .. 404 2N338 ........ 395 2N718 ........ 391 2N2160 ....... 387
MTD-4 .. 404 2N338A ...... 395 2N718A ...... 391 2N2106 ....... 392
4JFI-TD-l .... 404 2N377 ........ 400 2N719 ........ 391 2N2107 ....... 392
TD-IA ... 404 2N385 ........ 400 2N719A ...... 391 2N2108 ....... 392
TD-2 .... 404 2N388 ........ 400 2N720 ........ 391 .2N219.2 ....... 389
TD-2A · ... 404 2N394 ........ 398 2N720A ...... 391 2N2192A . . . . . 389
TD-3 .... 404 2N394A ...... 398 2N725 ........ 397 2N.2193 ....... 389
TD-3A ... 404 2N395 ........ 398 2N753 ........ 390 2N2193A . . . . . 389
TD-4 .... 404 2N396 ........ 398 2N759 ........ 390 2N2194 ....... 389
TD-4A ... 404 2N396A ...... 398 2N760 ........ 390 2N2194A . . . . . 389
TD-5 .... 404 2N397 ........ 398 2N781 ........ 397 2N2195 ....... 389
TD-SA ... 404 2N404 ........ 398 2N782 ........ 397 2N2195A . . . . . 389
TD-310 .. 404 2N404A ...... 399 2N828 ........ 397 2N2196 ....... 393
TD-310A . 404 2N413 ........ 399 2N834 ........ 390 2N2197 ....... 393
TD-311 .. 404 2N414 ........ 399 2N914 ........ 390 2N2201 ....... 393
TD-311A . 404 2N427 ........ 399 2N915 ........ 390 2N2202 ....... 393
TD-311B . 404 2N428 ........ 399 2N916 ........ 390 2N2203 ....... 393
4JF2-BD-l 405 2N448 ........ 401 2N956 ........ 391 .2N2204 ....... 393
BD-2 405 2N449 ........ 401 2N960 ........ 397 .2N2243 ....... 389
BD-3 405 2N461 ........ 399 2N961 ........ 397 2N2243A . . . . . 389
BD-4 405 2N489 ........ 387 2N962 ........ 397 3N58 ......... 396
BD-5 405 2N489A ...... 387 2N964 ........ 397 3N59 ......... 396
BD-8 405 2N489B ...... 387 2N965 ........ 397 3N60 ......... 396
BD-7 405 2N490 ........ 387 2N966 ........ 397 4C28 ......... 394
4JF2-BD-501 . . 405 .2N490A ...... 387 2N994 ........ 397 4C29 ......... 394
BD-502 .. 405 2N490B ...... 387 2Nl057 ....... 399 4C30 ......... 394
BD-503 .. 405 2N491 ........ 387 2Nl086 ....... 401 4C31 ......... 394
4JF4-MP-l 403 2N491A ...... 387 2Nl086A . . . . . 401 4D20 ......... 394
MP-2 403 2N491B ...... 387 2Nl087 ....... 401 4D21 ......... 394
MQ-1 .... 403 2N492 ........ 387 2Nl097 ....... 399 4D22 ......... 394
MQ-2 .... 403 2N492A ...... 387 2Nl098 ....... 399 4D24 ......... 394
Transistors 2N49.2B ...... 387 2Nll21 ....... 401 4D25 ......... 394
2N493 ........ 387 2Nll44 ....... 398 4D26 ......... 394
2N43A ....... 398 2N493A ...... 387 .2Nll45 ....... 399 7Bl .......... 393
.2N44A ....... 398 2N493B ...... 387 2Nll75• ...... 399 7B2 .......... 393
.2N45 ......... 398 2N494 ........ 387 .2Nll75A ..... 399 7B3 .......... 393
2N78 ......... 401 2N494A ...... 387 2Nl217 ....... 401 7Cl .......... 393
2N78A ....... 401 2N494B ...... 387 2Nl277 ....... 395 7C2 .......... 393
2Nl87A ...... 401 2N497 ........ 392 2Nl278 ....... 395 7C3 .......... 393
2Nl89 ........ 401 2N497A ...... 392 2Nl279 ....... 395 7D1 .......... 393
2Nl69A ...... 401 2N498 ........ 392 2Nl302 ....... 400 7D2 .......... 393
2Nl86A ...... 398 2N498A ...... 392 2Nl303 ....... 399 7D3 .......... 393
2Nl87A• ..... 398 2NS08• ....... 399 .2Nl304 ....... 400 7El .......... 393
2Nl88A• ..... 398 2N524 ........ 399 .2Nl305 ....... 399 7E2 .......... 393
2Nl89• ....... 398 2N525 ........ 399 2Nl306 ....... 400 7E3 .......... 393
2Nl90• ....... 398 .2N528 ........ 399 2Nl307 ....... 399 7Fl .......... 393
2Nl91• ....... 398 2N527 ........ 399 2Nl308 ....... 400 7F2 .......... 393
2Nl92• ....... 398 2N634 ........ 400 2Nl413• ...... 399 7F3 .......... 393
2N241M ..... 398 2N634A ...... 400 2Nl414• ...... 399 7F4 .......... 393
2N292 ........ 401 2N635 ........ 400 2Nl415• ...... 399 USAF2Nl67 A . 401
2.N.293 ........ 401 2N835A ...... 400 2Nl510 ....... 401 USN2N388 . . . . 400
2N319• ....... 398 2N838 ........ 400 2Nl805 ....... 400
2N320• ....... 398 2N636A .. : . . . 400 2Nl613 : . . . . . . 388
2N321• 398 2N656 ........ 392 2Nl814 ....... 399 •see Preferred Types
2N322• 398 2N858A ...... 392 2Nl871 ....... 387 Chart on Page 122

386
 SILICON UNIJUNCTION TRANSISTORS<2>
See Outline Drawing No. 5
Intrinsic Max. Max. Max. Min. Min.
Standoff Emitter Peak Point Emitter Emitter Base One
lnterbase Ratio Revene Emitter Saturation Revene Peak Pulse
Resistance Cunent Current Voltage Voltage Voltage
RBB '1J IEO IP VE (SAT) VOBl
IE=50ma
Vaa=3v lz=O Vaa=10v TJ=150°C Vaa=25v VaB=lOv TJ<150°C
Type Kohms VB&2 µ.a µ.a Volts Volts Volts Comments
2N489ll) 4.7-6.8 .51-.62 10 20 20 5.0 60 - Applications include the fol-
2N489A 4.7-6.8 .51-.62 10 20 15 4.0 60 3.0 lowing:
2N4898 4.7-6.8 .51-.62 30 5 6 4.0 60 3.0 • Frequency Dividers
2N490<1> 6.2-9.1 .51-.62 10 20 20 5.0 60 - • High Sensitivity Trigger
Circuits
2N490A 6.2-9.1 .51-.62 10 20 15 4.0 60 3.0 • Hybrid Multivibrator
2N490B 6.2-9.1 .51-.62 30 5 6 4.0 60 3.0 Circuits
• Lowest Cost SCR(3) Fir-
2N491<1> 4.7-6.8 .56-.68 10 20 20 5.0 60 - ing Circuits
2N491A 4.7-6.8 .56-.68 10 20 15 4.3 60 3.0 • One Shot Multivibrators
2N491B 4.7-6.8 .56-.68 30 5 6 4.3 60 3.0 • Pulse Genera tors
• Precision Voltage Sensing
2N492< 1> 6.2-9.1 .56-.68 10 20 20 5.0 60 - Circuits
2N492A 6.2-9.1 .56-.68 10 20 15 4.3 60 3.0 • RegenerativePulseAmpli-
fiers
2N492B 6.2-9.1 .56-.68 30 5 6 4.3 60 3.0
• Ring Counters
2N493(t) 4.7-6.8 .62-.75 10 20 20 5.0 60 - • Sawtooth Oscillators
2N493A 4.7-6.8 .62-.75 10 20 15 4.6 60 3.0 • SCR<a> Phase Control
Circuits
2N493B 4.7-6.8 .62-.75 30 5 6 4.6 60 3.0
• SCR( 3 ) Regulated Power
2N494< 1> 6.2-9.1 .62-.75 10 20 20 5.0 60 - Supplies
• Stable Relaxation Oscil-
2N494A 6.2-9.1 .62-.75 10 20 15 4.6 60 3.0
lators
2N494B 6.2-9.1 .62-.75 30 5 6 4.6 60 3.0 • Stable Time Delay Cir-
2Nl671 4.7-9.1 .47-.62 30 12(4) 25 5.0 30 - cuits
• Staircase Wave Genera-
2Nl67IA 4.7-9.1 .47-.62 30 12(4) 25 5.0 30 3.0 tors
2Nl671B 4.7-9.1 .47-.62 30 5 6.0 5.0 30 3.0 • Solid State Time Delay
Circuits
2N2160 4.0-12.0 .47-.80 30 12( 4 ) 25 - 30 3.0
NOTES: <1>Available as USAF TYPF.S (MIL-T-19500/75) (2) See also Chapter 13 (3) See General Electric Silicon Controlled Rectifier Manual COT1=25°C
Test conditions in italics
w
00
00

SILICON PLANAR PASSIVATEDTRANSISTORS<

1, 4 >

T0-5 Package (See Outline Drawing No. 4)

Min. Max. MAXIMUM POWER DISS. MINIMUM hFE

_a C
C a -c 0. u C E
c: E t-EC .. EC u C C
E3 ::t.
51-)a>
~~
~oE ~oE a> 0 .!:::u Ea ~3:'n E~ E~
w
o_
~II
II w
J1e ~1/\1/\

!:1l: ~iiii :iiii

II
~11'111'1 ]El/\
-11
~iiuti gii
11'1
o-
8
11111
<•
Q)~
';;8
,,,_ ~ii ~iii -:ii
u!:l II~ II 11 ~ii
u~llti
r,/1
r,, QCJ
.c-> >~!= >!=~ >!=~ .a:--> Q ..
-t-
l>lw
>- &:~@ &:8@ -> !=>~ !=~ -> ->
Vea
Type<a> Volts Volts Volts Min. Max, Volts µ.a Volts Watts Watts Comments
2N696(7) 20-60 40 1.5 1.3 - 30 100 5 0.6 1.0 - - - - -
2N697< 7 > 40-120 40 1.5 1.3 - 30 100 5 0.6 1.0 - - - - -
2N698 20-60 80 5.0 1.3 15- 75 IS 1 0.8 1.7 - - - - - High Voltage 2N696

2N699 40-120 80 5.0 1.3 35-100 60 200 5 0.6 1.0 - - - - - High Voltage 2N697.

2Nl613 40-120 50 1.5 1.3 30-100 60 IO 1 0.8 1.7 35 20 20 20 - Lower leakage 2N697.

2Nl711 100-300 so 1.5 1.3 50-200 60 10 7 0.8 1.7 75 35 35 40 - High beta 2NI613.

2Nl889 40-120 80 5.0 1.3 30-100 75 15 1 0.8 1.7 35 20 20 - - High Voltage 2Nl613.

2Nl890 100-300 80 so 1.3 50-200 - 1 0.8 1.7 - - - - - Higher voltage 2Nl711.

2Nl893 40-120 100 s.o 1.3 30-100 90 15 1 0.8 1.7 35 20 20 - - High voltage 2Nl613.

2Nl983 - 30 0.25(11) - 70-210 30 200 5 0.6 1.0 - - - - - Very high beta for hi,rh
ff:in,.Iov.: noise ampli-
er ctrcuats.
'i
,:
..u
• Q,
:a>-
.
2Nl984 - 30 0.25(11) - 35-100 30 200 5 0.6 1.0 - - - - - Amplifier Circuits.
:r·
2Nl985 - 30 0.25(6) - 15-45 30 200 5 0.6 1.0 - - - - - Amplifier Circuits.

2N2049 - 50 0.4(11) 0 9( 5 )
.I 75- 60 10 1 0.8 1.7 - - 60 - - Very hi((h beta for high gain,
Low noise amplifier circuits.
NF=3db Max.
 SILICON PLANAR EPITAXIAL PASSIVATED (PEP) TRANSISTORS<
1, 4 >

TO-5 Package(See Outline DrawingNo. 4)

2N2192 100-300 40(2) 0.35 1.3 - 30 15 5 0.8 1.6 75 35 15 35 15

Similar to 2Nl7ll, but lower
Vcs (SAT).
2N2192A 100-300 40(2) 0.25 1.3 - 30 15 5 0.8 1.6 75 35 15 35 15

2N2193 40-120 50( 2 ) 0.35 1.3 - 60 25 8 0.8 1.6 30 20 15 20 15

Similar to 2Nl613, but lower
VcE (SAT).
2N2193A 40-120 50(2) 0.25 1.3 - 60 25 8 0.8 1.6 30 20 15 20 15

2N2194 20-60 40(2) 0.35 1.3 - 30 25 5 0.8 1.6 15 - - 12 - Similar to 2N696, but lower
VcE (SAT).
2N2194A 20-60 40(2) 0.25 1.3 - 30 25 5 0.8 1.6 15 - - 12 -
2N2195 20 Min. 25(2) 0.35 1.3 - 30 50 5 0.6 1.6 - - - - - Industrial types.
2N2195A 20 Min. 25(2) 0.25 1.3 - 30 50 5 0.6 1.6 - - - - -
2N2243 40-120 80(2) 0.35 1.3 - 60 15 7 0.8 1.6 30 20 15 15 - Similar to 2Nl893 but lower
VCE(SAT,)
2N2243A 40-120 80(2) 0.25 1.3 - 60 15 7 0.8 1.6 30 20 15 15 -
NOTES: Test Conditions in Italics. (1) Typical ft for all types ~ 130 Mc. (2) VcEo
(3) Storage temperature on all types is -65 to +300° C. Operating junction temperature on all types is -65 to +200° C, except on
2N696, 2N697, and 2N699. On these types the rating is -65 to +175° C.
(4) For switching and amplifier applications. (6 ) le"" IO ma, and I b.., 1 ma. (6 ) le"" 5 ma. and I b = .5 ma.
(7) Also available in military types.
 SILICON PLANAR EPITAXIAL PASSIVATED (PEP) HIGH SPEED SWITCHES<3 >
TO-18 Package (See Outline Drawing No. 8)

MINIMUM MAXIMUM MAXIMUM

VCEB VcEo Vzao lcao
hn Volts Volts Volts Var: (SAT> Vcs (SAT> toa tott Cob@ Vea
Min. Max. lc=10ma lc=lOma TJ=150°C
@le @Yem @le@Rue @lo @Im lu=I ma la=l mo @Vca
Type ma Volts ma ohms ma p.a Volts Volts Volts p.a nsec nsoc pf Volts Comments

10 1.0 30 10 100 15
2N706 20 Min. 20 - 3 0.9 0.6 30 - - 6 10 Economy Units.
to 1.0 10 10 10 10 15
2N706A 20-60 20 15 5 0.9 0.6 30 40 75 5 5 Economy units. High speed.
10 1.0 30 10 30 10 20
2N708 30-120 20 15 5 0.8 0.4 15 40 70 6 10 Low leakage current.. High speed.
10 1.0 to 10 10 10 15
2N753 40-120 20 15 5 0.9 0.6 30 40 75 5 5 High bet.a. High speed.
10 1.0 10µ.a 0 - 100 20
2N834 25 Min. 30( 1) - 5 0.9 0.25 30 35 75 4 10 Low saturation voltage.
10 1.0 30 10 30 10 20
2N914 30-120 20 15 5 0.8 0.25 15 40 40 6 10 Ult.ra-higb speed. Low saturation voltage.

SILICON PLANAR PASSIVATED AMPLIFIERS-TYPICAL ft~300 MC.

TO-18 Package (See Outline Drawing No. 8)

1.0 5.0 1.0 too 30

2N759 36-90(2) - 45 8 - 1.0 10 - - 8 5 These devices are well suited Cor afplica-
tions where the 2N335 and 2N33 have
1.0 5.0 1.0 been used and higher Crequency devices or
100 30
2N760 76-333(2l - 45 8 - 1.0 10 - - 8 5
smaller packages are required.

10 5.0 10 100 60
2N915 40-160 - so 5 0.9 1.0 30 - - 3.5 10 These devices are intended for non-sat-
orating switching circuits, amplifier and
10 1.0 30 10 15 and oscillator circuits.
2N916 50-200 - 25 5 0.9 0.5 10 - - 6 5
 SILICON PLANAR PASSIVATED SWITCHES<
3>
TO-18 Package (See Outline Drawing No. 8)
lc=l50 mo lc=l50mo
la=l5 mo la=l5 mo
150 10 100 10 - 1 ma 30
2N717 20-60 40 - 5 1.3 1.5 100 - - 35 10 Electrically equivalent. to 2N6Q6.
150 10 100 10 - 1 ma 30
2N718 40-120 40 - 5 1.3 1.5 100 - - 35 10 Electrically equivalent. to 2N697.

2N718A
150
40-120
10 100 10
50
- - 100
7 1.3 1.5
60
10 - - 25 10 Electrically equivalent. to 2Nl613.
150 10 100 10 - 1 ma 60
-
2N719 20-60 80 - 5 1.3 5 200 - 20 10 Electrically equivalent. to 2N698.
150 10 100 10 30 100 75
2N719A 20-60 80 60 7 1.3 5 15 - - 15 10 Electrically equivalent. to 2N698.
150 10 100 to - - 1 ma 60
2N720 40-120 80 5 1.3 5 200 - - 20 10 Electrically equivalent. to 2N699.
150 to 100 10 30 too 90
2N720A 40-120 100 80 7 1.3 5 15 - - 15 10 Electrically equivalent. to 2Nl893.
150 10 100 10 - - 100 60
2N956 100-300 so 7 1.3 1.5 15 - - 25 10 Electrically equivalent. to 2Nl7ll.
NOTES: Test. conditions in lt.alics. (1) VcBS (2) bee @ I Kc. (3 ) Typical ft for all t.ypes ~ 350 me.

POWER DISSIPATION
PT ( Free Air @ 25°C)

300 MW 360 MW 400 MW 500 MW

2N7o6 2N708 2N717 2N718A

2N706A 2N914 2N718 2N720A
2N719A 2N915 2N719 2N759
2N753 2N916 2N720 2N760
2N834 2N956
 SILICON MESA NPN POWER TRANSISTORS<s>
MINIMUM MAXIMUM
Power Dissipation
hvE VcEo VcEx lcao PT PT Vcm(e.u>
Vc11:=10v lc=25Oµa Free Air Cose Temp lc=200ma
lc=200ma lc=25Oµa VsE=-1.Sv Vcs=30v @25°C @25°C ls=4Oma
TJ=15O°C TJ=15O°C
Drwg.
Typo No. Volts Volts JLG Watts Watts Volts Comments

2N497(e> 2 12-36 60 250 0.8 4 5

2N497A 2 12-36 60 250 1.0 5 2
Applications include the rot-
2N498(G) 2 12-36 100 250 0.8 4 5 lowing:
• Audio Amplifiers
2N498A 2 12-36 100 250 1.0 5 2 • Blocking Oscillators
• DC to AC Inverters
2N656( 6> 2 30-90 60 250 0.8 4 5
• Linear Amplifiers
2N656A 2 30-90 60 250 1.0 5 2 • Magnetic Tape Bias and
Erase Oscillators
2N657(Gl 2 30-90 100 250 0.8 4 5 • Power Oscillators
• Power Switching Circuits
2N657A 2 30-90 100 250 1.0 5 2 • Pulse Amplifiers
2N2017 2 50-200 60 250 1.0 5 2 • Regulated Power Supplies
• Servo Amplifiers
2N2106 2 12-36 60(1) 200(2) 1.0 - 5 • Servo Drivers
• Solenoid Drivers
2N2107 2 30-90 60( 1) 200(2) 1.0 - 2
2N2108 2 75-200 60(1) 200(2) 1.0 - 2(3)
 Cose Temp.<•>
@100°C
2N2196 9 30-90 60(1) 80 250 2.0 10 2

2N2197 9 75-200 60(1) 80 250 2.0 10 2(3)

2N2201 9 30-90 100 120 200 2.0 10 1.7

2N2202 10 30-90 100 120 200 1.0 10 1.7

2N2203 11 30-90 100 120 200 1.0 10 1.7·

2N2204 12 30-90 100 120 200 1.0 10 1.7

7B1 9 12-36 60 80 200 2.0 10 1.7
7B2 9 30-90 60 80 200 2.0 10 1.7
783 9 12-36 100 120 200 2.0 10 1.7
7Cl 10 12-36 60 80 200 1.0 10 1.7
(Same ap~lications as above
7C2 10 30-90 60 80 200 1.0 10 1.7 but at higher power con-
ditions)
7C3 10 12-36 100 120 200 1.0 10 1.7
7D1 11 12-36 60 80 200 1.0 10 1.7
7D2 11 30-90 60 80 200 1.0 10 1.7
7D3 11 12-36 100 120 200 1.0 10 1.7
7El 12 12-36 60 80 200 1.0 10 1.7
7E2 12 30-90 60 80 200 1.0 10 1.7
7E3 12 12-36 100 120 200 1.0 10 1.7
7Fl 13 12-36 60 80 200 1.0 4.0 1.7
7F2 13 30-90 60 80 200 1.0 4.0 1.7
7F3 13 12-36 100 120 200 1.0 4.0 1.7
7F4 13 30-90 100 120 200 1.0 4.0 1.7
NOTES: <1> VcEROc=l6ma, R=lK) (2) TJ =125°C (3) la=l0 ma <•>See outline drawing for attachment to heatllink. <11>
Typ. ft for all types=lS MC
<11> Also available in military types.
 SILICON GROWN DIFFUSED NPN TRANSISTORS
T0-5 Package(See Outline DrawingNo.4)

MINIMUM MAXIMUM TYPICAL MAXIMUM TYPICAL

Powor
hro BVcao ICBO ftarb Diss. hH
Vca=5v lceo= Voe=30v
111=1ma SOµa hi:=O Vca=Sv Vcs=S v
f=l kc ls=O T.&=250C0 IE=l ma lc=l ma
Typo volts me fflW Comments

40(,)
'"'
4C28 9-19 2.0 12 150 15

4C29 18-40 40<•> 2.0 12 150 30

4C30 37-80 40(,) 2.0 12 150 55

4C31 76-300 40 2.0 12 150 115

4D20 Seehm 40(,) 1.0(8) - 150 15-50(10) Applications include the following:
• Audio amplifiers
4D21 Seebm 40(,) 1.0(8)
- 150 40-135(10) • Low cost industrial switches
4D22 See hFB 40<•> 1.0(8) - 150 120-250(10)

4024 Seehm 15(6) 1.0(7) - 125 15-50(IO)

4D25 See hFB 15(6) 1.0(7) - 125 40-135(10)

4D26 SeehFB 15(6) 1.0(7) - 125 120-250(10)

2N332<11) 9-22 45 1.0 10 150 14

2N332A 9-22 45 0.5 10 500 16 Applications include the following:

• Audio Amplifiers
2N333Caa> 18-44 45 1.0 12 140 31 • Ast.able Oscillators
• Chopper Circuits
2N333A 18-44 45 0.5 11 500 27 • Flip-Hop Circuits
45 • Losic Circuits
2N334C13> 18-90 1.0 13 150 38
• RF Amplifiers
2N334A 18-90 45 0.5 12 500 36
 2N335< 13l 37-90 45 1.0 150 56

2N335A 37-90 45 0.5 13 500 45

2N335B 37-90 60 0.5 13 500 45(12)

2N336 76-333 45 1.0 15 150 100

2N336A 76-333 45 0.5 15 500 75

2N337< 1a) 55(1) 45 l.0(G) 30 125 55( 11)
(Same comments as above)
2N337A 55(2) 45 0.5 30(11) 500 35(11)

2N338< 13> 99(1) 45 l.0(G) 45(11) 125 99(11)

2N338A 99(2) 45 0.5 45(11) 500 75(11)

2Nl277 18-44 40 1.0 30(11) 150 20<11>

2Nl278 37-90 40 1.0 30(11) 150 33(11)

2Nl279 76-333 40 1.0 34(11) 150 80(11)

NOTES: (1) Typical hre@ Vce=20 V, IE=l ma. (o) Vca=20 V, IE=0 (10) Pulsed measurement.
(2) Typical hre@ Vco=20 V, lc=l mo. (7) Vce=15V,IE=0 (11) VcB=5V, le= 10 ma.
(4) Iceo-=100 pa, IE-=0. Cs>Vce-=12 V, IE=0 (12) Vcs=l0 V, lc=5 ma.
(11) BVcEo @ lcaoa::::100 pa. (II) Vce=20 V, IE=l mo. (1a) Also available in military types.
 SILICON NPNP LOW CURRENT CONTROLLEDSWITCHES<
4>

TO-5 Package Isolated Case (See Outline Drawing No. 6)

MAX. ANODE RATINGS MAX. GATE RATINGS GATE INPUT TO FIRE

Max. Mox.
Is la VF In loc loA loFA VoFA loFc VoFc

u-=•
.. •~u
u
0In
u
0In t 0
II
aU I: go
~::g e >- >- >
U111
o E
0!.c
U
oe
0!.c
C11 Ill
E
CII
E

~'s
:1.0 .c .c
Ill
gu E 13- :a .. C
i:.l i:.l In

~'8 ~8
lllg
o.5
-a.x a
oU•
VI
:l"a~
.5 ciu
• to
.n~
aa
,¥
"C
,¥ e
.!!
a
Q,
+~
1111
I~
1111
0
0
E
In
>')l.
00
v-
1111
r-i
I
II
3
V
II
llil
~8
Uil Uil Uil
a!o a"' i uu
• o
uu
• Cl II uu
•
1:.1 •0 •..: •..: •..: •..:
~ci~ io8
uu.-
woo
A.u.-
w :I
A.U 0 >~ >~ ~
C,
>c::: >
0
> >c::: >c::: >c::: >c:::
Type Volts ma amp ma mw µa µa Volts ma µo µa ma Volts µa Volts

3NSB<•> 40 100 0.5 50 300 20 20 1.5 1.5 20 1.0 0.4 to 0.65

3NS9(2) 40 100 0.5 50 300 20 1.5 1.5 20 (150°C) 1.5 -0.6 to -1.2

3N6o<a> 40 100 0.5 so 300 20 20 1.5 1.5 20 0.2 (25°C) 1.5 -0.6 to -1.2 1.0 0.4 to 0.65

NOTES:
<1> For this characterization GA is electrically open, This corresponds to the conventional SCR (6) configuration. <•> See also Chapter 19.
(2) For this characterization, G~ is connected to C. This correspnds to the complementary SCR (6) configuration. (s) Derate at 2.4 mw per °C.
(3) Thi:1 characterization is for SCR, complementary SCR(6), and Binistor circuit configurations. The 3N60 meets (6) See General Electric Silicon Controlled
all specifications for tho 3N58 and 3N59. Rectifier Manual.
 GERMANIUM MESA TRANSISTORS
TO-18 Package (See Outline Drawing No. 8)
MAXIMUM MINIMUM MAXIMUM MAXIMUM
VeE Cs.t.Tl VeE1<sATl VBEI
hFE Volts Volts Volts
@le @VeE le Diss. <1> Veso Vc&s VF.BO lcBO @le @Is @le @IB @le @IB ton tou
Type ma Volts ma mw Volts Volts Volts µ.a ma ma ma ma ma ma nsec nsec Comments

2N705( 2 l
10
25min.
.3
so 150 15 15 3.5 3
10
.30
.4 - - 10
.34-.44
.4
75 200 Low current, relatively slow speed, econ-
omy units, relatively high saturation
2N710
10
25 min.
.5
50 150 15 15 2.0 3
10
.so
.4 - - 10
.34-.50
.4
75 200
voltage, high voltage.

2N711
10
20-250
.5
100 150 12 12 1.0 3
to
.50
.5 - - 10
.35-.50
.4
100 350
Low current, relatively slow speed, econ-
omy units, relatively hi,!' S11turation
voltaite, low voltaire, low eta.
10 .5 10 .5 50 2 10 .4 Economy units, relatively slow, medium
2N711A 25-150 JOO 150 15 14 1.5 1.5 .30 .55 .34-.50 75 230 current, low Jcuo.
10 .5 10 .4 50 2 10 .4 Low lceo relatively slow speed, medium
2N711B 30-150 100 150 18 15 2.0 1.5 .25 .45 .34-.45 75 200 current, higher beta.
2N725
10
20 min.
.5
50 150 15 12 2.0 3
to
.50
.5 - - 15 1.2
.34-.60 75 200
Low current, relatively slow speed, econ-
omy units, relatively high saturation
voltaize, lower voltal(e, low beta.
10 .22 10 1 100 10 10 .4 Hiith current, very low saturation, high
2N781 25min. 200 150 15 15 2.5 3 .16 .25 .34-.44 60 70 voltaae, medium to hi1rh sneed.
10 .25 10 1 100 10 10 .4 High current, medium saturation.lower
2N782 20min. 200 150 12 12 1.0 3 .20 .45 .34-.50 75 110 voltaite, medium speed.
10 .3 10 1 50 5 10 1 Hiith current. very low saturation, high
2N828 25min. 200 150 15 15 2.5 3 .25 .25 .34-.44 70 100 voltage, medium to high speed.
to 1 10 1 100 10 10 1 Medium current, high speed, low beta,
2N960 20 min. 150 150 15 15 2.5 3 .20 .70 .30-.50 50 90 hi1rh volta,re.
10 1 10 1 100 10 10 1 High speed, low beta, lower voltage,
2N961 20min. 150 150 12 12 2.0 3 .20 .70 . 30-.50 50 90 medium current .
10 1 10 1 100 10 10 1
2N962 20 min. 150 150 12 12 1.25 3 .20 .70 .30-.50 50 90 High speed, high beta, high voltage,
10 1 10 1 100 10 10 1 medium current.
2N964 40min. 150 150 15 15 2.5 3 .18 .60 .30-.50 50 90
10 1 10 1 100 10 10 1
2N965 40 min. 150 150 12 12 2.0 3 .18 .60 .30-.50 so 90 High speed, high beta, lower voltage,
10 1 10 1 100 10 10 1 medium current.
2N966 40 min. 150 150 12 12 1.25 3 .18 .60 .30-.50 50 90
to .25 10 .4 100 8 10 .4 Very high speed, high dissipation, high
2N994 45-140 150 200 15 15 4.0 3 .18 .45 .34-.44 35 45 voltage, medium current, high beta,
low saturation.
NOTES:Test Conditions in Italics. <1>25°C Ambient Free Air. (2) Also available in military types.
 GERMANIUM ALLOY PNP TRANSISTORS<
1>

TYPICAL MINIMUM MAXIMUM

Power
hPE fbtb BVcma ICBO Diss.
Vcs=1v @ lc=600µ.a
lc=20ma Res=10K @VCB
Drwg.
Types No. me Volts p.a Volts mw Comments

2N43A(lO) l 3~5 1.3 30 16 45 240 See 2N525.

2N44AhO) l 18-41 1.0 30 16 45 240 See 2N524.
2N45 l U-23 1.0 30 16 45 155
2Nl86A 1 19-31 0.8 25 16 25 200
2Nl87A l 25-42 1.0 25 16 25 200 Not. recommended
2Nl88A 1 3~5 1.2 25 16 25 200 for new designs.
See 2N508, 2Nl175
2Nl89 l 25-42 0.8 25 16 25 200 and 2Nl413 series.
2Nl90 l 34-65 1.0 25 16 25 200
2Nl91 1 53-121 1.2 25 16 25 200
2Nl92 1 72-176 1.5 25 16 25 200
2N241A 1 50-125 1.3 25 16 25 200
2N319 2 25-42 2.0 20 16 25 225
2N320 2 34-65 2.5 20 16 25 225
2N321 2 53-121 3.0 20 16 25 225
Audio driver and audio out.put..
2N322 2 34-65 3.0 16 16 16 200
2N323 2 53-121 3.5 16 16 16 200
2N324 2 72-198 4.0 16 16 16 200
2N394 2 20-150C2) 7.0 15 6 10 150 Medium SDeed switch.
2N394A 2 30-120C2) 7.0 15 6 12 150 Medium sneed switch and audio amoli6er.
2N395 2 20-150(2) 6.0 15 6 15 200 Medium soeed switch.
2N396 2 30-150(2) 8.0 20 6 20 200 Industrial/Military-medium bet.a. medium imeed switch.
2N396A< 10> 2 30-150(2) 8.0 20(6) 6 20 200 Same as 2N396. Mil-S-19500/64B.
2N397 2 40-150(2) 12.0 15 6 15 200 Industrial/Military-medium sneed switch.
2N404(10> 2 - 8.0 24(G) 5 12 150 Medium sneed switch-wide bet.a soread. MIL-T 19500/20.
 2N404A 2 8.0 35( 11) 5 20 150 Same as 2N404
2N413 2 20-100(2) 6.0 18(6) 5 12 150 General puroose medium snetvl switch.
2N414 2 30-120(2) 7.0 15lll) 5 12 150 Same as 2N413.
2N427 2 40-80(3) 10.0 15(6) 4 1.5 ISO Medium soeed switch and amplifier. Narrow beta spread.
2N428<•0> 2 60 Min.< 3 > 15.0 12(6) 4 1.5 ISO Medium soeed switch. High beta. MIL-S-19500/448.
2N461 2 32-199(4) 4.0 35(11) IS t,5 200 General purpose.
2N508 2 99-198 4.5 16 7 16 200 High ,min, low noise oreamolifiers.
2N524 2 25-42 2.5 30 10 30 225
2N525 2 34-65 3.0 30 10 30 225 Military/industrial.-Audio amplifier and medium speed switch. Spe-
cified hvs hold-up, high tem~ture Ico, and low temperature hP'B.
2N526<•o> 2 53-90 3.5 30 10 30 225 Guaranteed reliability index. IL-T-19500/608.
2N527 2 72-121 4.0 30 10 30 225
2Nl057 l 34-90 1.3 30(7) 16 /,5 240 See 2Nl924 series. Not recommended for new designs.
2N1097 2 34-90 3.0 16 16 16 200
Audio driver and audio output.
2Nl098 2 25-90 3.0 16 16 16 200
2N1144 1 34-90 1.3 16 16 16 175 See 2Nl097, 2Nl098, or 2Nl413 series. Not recommended for new
2Nll45 1 25-90 1.3 16 16 16 175 designs.
2N1175 2 70-140 4.0 25 12 30 200 General nurnose industrial and consumer preamplifier.
2Nll75A 2 70-140 4.0 25 12 30 200 General pu~ industrial and consumer, high gain, low noise pre-
amplifiers. wuaranteed noise fiRUre.
2Nl303<•o> 2 20 Min.<2> 7.0 25(G) 6 25 150
2Nl305(10) 2 40-200(2) 8.0 20<0 > 6 25 150 Medium speed switch. MIL-S-19500/126A.
2Nl307C•o> 2 60-300(2) 12.0 15(G) 6 25 150
2Nl413 2 25-42 3.2 25 12 30 200
General puq>ose industrial and consumer audio amplifier and medium
2NJ414 2 34-65 3.6 25 12 30 200 speed switch.
2Nl415 2 53-90 4.0 25 12 30 200
2Nl614 1 18-43 1.3 40(8) 25 65 240 See 2Nl924 series. Not recommended for new designs.
2Nl924 2 34-65 3.0 40 10 t,5 225
Military/industrial audio amplifier and medium speed switch. High
2Nl925 2 53-90 3.5 40 10 t,5 225 voltage, ~fied hPB hold-up, low temperature hvs, and high tern-
perature co. Guaranteed reliability index.
2Nl926 2 72-121 4.0 40 10 t,5 225

NOTES: Test conditions in Italics. (4) Vcs-SV, Is"" I ma, f,... l Kc. (8) VRT=60 V.
<•> All specs. at 25°C unless noted otherwise <6> BVc1ro. (ll)R ... 1 K.
(2) Vcs-lV, Jc ... JO Ma. (G) VRT. (10) Also available as military types.
(al Vcs .... 25V, Je ... 1 Ma. ( 7) VRT... 4SV.
 GERMANIUM ALLOY NPN TRANSISTORS
TO-5 Package(See Outline DrawingNo. 2)

TYPICAL MINIMUM MAXIMUM

Powor
hn fhtb BVcER ICBQ Diss.
lc=10ma R=lOK
VcE=lv lc=600 µ.a @Vcs=25v
Type me Volts µ.a mw Comments

2N377 20-60(5) 6 20(8) 20(3) 150 Not recommended for new designs. See 2N634A.
2N385 30-110( 4 ) 6 25(9) 35 150 Not recommended for new designs. See 2N634A.
2N388 60-180(2) 12 20(8) 10 150 Medium Speed Switch. Guaranteed Maximum Switching Speed.
USN2N388 60-180C2) 12 20C8) 10 150 Medium Speed Switch To MIL-T-19500/65.
2N634 15 Min.Cl) 8 20 IOC3) 150 Not recommended Cor new designs. See 2N634A.
2N634A 40-120 8 20(10) 6 150 Medium speed switch and audio amplifier having close control or hFE from
10 ma to 200 ma, guaranteed minimum hFE at -55°C, mmdmum lcso at 71°C.
2N635 25 Min.Cl) 12 20 10Ca) 150 Not recommended for new designs. See 2N63SA.
2N635A 80-240 12 20(10) 6 150 Medium speed switch and audio amplifier havint close control or hFB from
10 ma to 200 ma, guaranteed minimum hFE at -55 C, maximum lceo at 71°C.
2N636 35 Min.Ci) 17 15 10(3) 150 Not recommended for new designs. See 2N636A.
2N636A 100-300 17 15(10) 6 ISO Medium speed switch and audio amplifier havini close control or hFE Crom
10 ma to 200 ma, guaranteed minimum hFE at - 5 °C, maximum lceo at 71 °C.
2Nl302 20 Min. 4.5 25(8) 6 ISO Medium Speed Switch.
2Nl304 40-200 8 20(11) 6 ISO Medium Speed Switch.
2Nl306 60-300 12 15(11) 6 150 Medium Speed Switch.
2Nl308< 12> 80 Min. 17 15(11) 6 150 Medium Speed Switch.
2Nl605 42 Min.(7) 16 24(11) 5(G) 150 Medium Speed Switch.

NOTES: (1) Ic-200 ma, VcE=.75 V. (6) lc=30 ma, VcE= 1.0 V. (u) lc=400 µa.
(2) lc=30 ma, VcE=.5 V. (&) Vee= 12 V. (JO) le= 100 µa.
(3) Vco=20 V. (7) lc=20 ma, VcB=.25 V. (11) VRT.
(4) Ic=30 ma, VcB=.75 V. (8) lc=SOµ,a. (12) Also available in military types.
 GERMANIUM RATE GROWN NPN TRANSISTORS
(See Outline Drawing No. 3)

MINIMUM MAXIMUM MAXIMUM TYPICAL

Power Power
hPE BcEo lcso Gain Dissipation fbtb
VcE=l v ls=O
lc=l ma lc=300 µ.a Vcs=15 v @ 455 kc
Type volts µa db mw me Comments

2N78 45-135 15 3 26.0-31.0 65 9 Preamplifier Switch. Lamp driver. Schmitt

trig~r. Waveform restoration. DC level de-
tection.
2N78A(7) 45-135 20 3 26.0-31.0 65 9 Applications same as 2N78.
2Nl67A 17-90(1) 30 1.5 - 75 9 Trigger circuits. Gate circuits. Logic circuits.
USAF2Nl67A 17-90( 1) 30 1.5 - 75 9 Mil. Spec. Mll.rS-19500/11.
2Nl69 34-200 15(3) 5 24.0-31.0 65 8 Reflex circuits. IF amplifiers. DC coupled
Audio amplifiers.
2Nl69A 34-200 25(3) 5 23.5-31.0 65 9 General Purpose Low Level switchl4).
2N292 8-51 15( 3) 5 21.0-26.0 65 5 IF Amplifiers.
2N293 8-51 15(3) 5 23.5-28.0 65 8 IF Amplifiers.
2N448 8-51 15( 3 ) 5 18.5-23.0 65 5 IF Amplifiers. Obsolete-Use 2N292.
2N449 34-200 15( 3) 5 21.5-25.0 65 8 IF Amplifiers. Obsolete-Uae 2Nt69.
2Nl086 17-200 9(3) 3(6) 23.0-29.0(6) 65 9 Autodyne Converter.
2N1086A 17-200 9(a) 3(6) 23.0-27.0(CI) 65 9 Autodyne Converter.
2Nl087 17-200 9(a) 3(11) 25.0-29.0(6) 65 9 Autodyne Converter.
2Nll21 34-200 15 5 26.5-30.5 65 8 Reflex circuits. IF Amplifiers. DC coupled
Audio Amplifiers.
2Nl217 40-100(2) 20 1.5 - 75 9 Starvation Switch.
2N1510 8-90 70( 3 ) 5 - 75 9 High Voltage Neon Indicator Circuits.
2Nl694 15-45(2) 20 1.5 - 75 9 Decade Counter. Low Level Switch. Amplifiers.

NOTES: (1) lce18ma., Vcs=l V. Ca) BVcERL R=IOK. (11)Vco=5 V. <7> Also available in military types.
(2) lce12 ma., Vcse1l V. (4) MAX VCE(BAT).., .4 V. (6) Conversion Gain @ 1600 Kc.
 SILICON SIGNAL DIODES
MAXIMUM MAXIMUM
Reveno Current
la ......
GI
E
->
.. \0
GI
u
C
J:
C =11, •u
ca
0 .! >11:
"a ua 8> ~GI
:,•

!-=>
&g,
A.
a
u
0:08
Q

oE
~ C
0
;:
u.!
'!In
Forward
-0 Z!o_ ~_; a,.
Voltage
V"M'
di7 u
i::~ t!.> .! :jj II
~.:::& ·U
Cl.Ci
t1
o.2
M.ln

Drwg. 2s c
0
1so c
0

Typo No. Volts j&a p.a Volts pf nsec mw ma Comments

IN3604 14 1.0 @SO ma .05 @SOV 50 @SOV 75 2 2 250 115 Very high speed, high conductance, computer diode.
Subminiature package .

1N3605 14 See Table I .05 @30V 50 @30V 40 2 2 250 115

1N3606 14 See Table I .05@ 50V 50 @SOV 75 2 2 250 115 Coot.rolled conductance, very high speed diode. Sub-
miniature glass package.
1N3063 14 See Table II .1 @50V 100@ 50V 75 2 2 250 115

1N3607 15 1.0@ 50 ma .05@ 50V 50 @50V 75 2 2 150 115 Very high speed, high oooduct.aoce diode in micro-
miruature package.

IN3608 15 See Table I .05 @30V 50 @30V 40 2 2 150 115 Controlled oooductaoce, very high speed diode in mi-
1N3609 15 See Table I ,05 @50V 50 @50V 75 2 2 150 115 crominiature package.
 Note- above ratinp also
• apply to diodes in pall'S, and •
quads.

I:!.Vr-Max. Forward
Voltage
difference between diodes
In pairs or quads
(TA=-55°C to +125°C)
lt==0.1 lr=lO
to 10 ma to 50 ma
mv mv
4JF4-MP-l 16 1.0@ SOma .OS @SOV so @ sov 75 10 20
Matched pairs in molded package.
4JF4-MP-2 16 1.0@ 10 ma .10 @30V 100 @ 30V 40 10 so

4JF4-MQ-l 16 1.0@ soma .OS @SOV SO @SOV 75 10 20

Matched quads in molded pack.age.
4JF4-MQ-2 16 1.0@ 10 ma .10@ 30V 100@ 30V 40 10 so

TABLE 1 TABLE l

Forward Voltage Forward Voltage

Vr Vr
It Min. Max. It Min. Mox.
ma mv fflY ma mv mv
0.1 0.490 o.sso .25 .sos .575
0.25 0.530 0.590 1.0 .550 .650
1.0 0.590 0.670 2.0 .610 .710
2.0 0.620 0.700 10.0 .700 .850
10.0 0.700 0.810

20.0 0.740 0.880

i TUNNEL DIODEsm

MAXIMUM
Max.
Peak Point Valley Point Peak Serles Negative Typlcal Resistive
Current Current Capacitance Voltage Resist. Conductance Cutoff Frequency
IP Iv C VP Rs -G fro
Drwg.
Type No. ma ma pf mv ohms mhos X 10- 1 Kmc Comments

4.JFl-TD-1 17 1.0 ± 10% 0.18 10 65 Typ. 4.0 8Typ. 2.3

TD-IA 17 1.0 ± 2.5% 0.14 5 65 ± 7 4.0 8.5 ± 1 3.2
TD-2 17 2.2 ± 10% 0.48 25 65 Typ. 3.0 18 Typ. 2.2
TD-2A 17 2.2 ± 2.5% 0.31 10 65 ± 7 3.0 19 ± 3 3.0
Low cost, gnmmil purpose
TD-3 17 4.7 ± 10% 1.04 50 65 TYD, 2.0 40 Typ. 1.8 switching oscillator, ampli-
fier, and converter, circuits
TD-3A 17 4.7 ± 2.5% 0.60 25 65± 7 2.0 41 ± 5 3.4 below 1 Kmc. Subminia-
TD-4 17 10.0 ± 10% 2.20 90 65 Typ. 1.5 80Typ. 1.6 ture axial package.
TD-4A 17 10.0 ± 2.5% 1.40 50 65 ± 7 1.5 85 ± 10 2.8
TD-5 17 22.0 ± 10% 4.80 150 65 Typ. 1.0 180 Typ. 1.6
TD-SA 17 22.0 ± 2.5% 3.10 100 65 ± 7 1.0 190 ± 30 2.6
1N3218 19 1.0 ± 10% 0.22 10 60Tyo. 4.0 8.5 ± 3.5 1.5
1N3218A 19 1.0 ± 10% 0.22 5 60 Typ, 4.0 8.5 ± 3.5 3.0
1N3219 19 2.2 ± 10% 0.48 20 60 Typ. 3.0 17.5 ± 7.5 1.8
1N3219A 19 2.2 ± 10% 0.48 10 60TYD. 3.0 17.5 ± 7.5 3.4 Microwave oscillator ampli-
4.JFl-TD-310 19 4.7 ± 10% 1.0-l 10 100 Tyo. 2.5 30 Typ. 2.7 fier and converter circuits.
TD-310A 19 4.7 ± l.M 5 lOOTyp. 2.5 30 Typ. 5.5
Ultra hi.gl1
circuits.
speed comtuter
icrownve pac age.
10%
TD-311 19 10.0 ± 10% 2.2 20 90Typ. 2.0 70 Typ. 2.7
TD-311A 19 10.0 ± 10% 2.2 10 90Typ. 2.0 70 Typ. 5.4
TD-311B 19 10.0 ± 4% 1.3 9 86 ± 11 1.5 70 Typ. 6.1
4.JFl-MTD-1 15 1.0 ± 10% 0.22 10 65 Typ. <l.O 8Typ. 2.3
Microminiature, very low
MTD-2 15 2.2 ± 10% 0.48 25 65 Typ. 3.0 16 Typ. 2.5 inductance package for thin
film circuits and micromin-
MTD-3 15 4.7 ± 10% 1.04 50 65 TYD. 2.0 30 Typ. 2.6 iat.ure equipments.
MTD-4 15 10.0 ± 10% 2.2 100 65TYD. 1.5 60 Typ. 2.3
NOTES: <1> See General Electric TunMI Diofk Manual.
 BACK DIODEsm
Max. Revene Min. Rovene Max.
Peak Paint Voltage Total
Forward Voltage Forward Voltage Current Capac.
Vr1=90 mv ±10 mv Vn Ip Vat VIU C
Drwg. when hr1= (at ln=3 lr1) (la=lpmox) <la=l mo)
Typo No. ma mv ma mv mv pf Commcnb
4JF2-BD-l 18 10.0 120 1.0 440 440 20
-BD-2 18 5.0 130 0.5 420 465 10
-BD-3 18 2.0 170 0.2 400 465 10 Germanium. Very low for-
ward drop, highs~ switch-
-BD-4
-BD-5
18
18
1.0
.5
170
160
0.1
0.05
380
350
465
465
10
10
i:f diode. Submmiature ax-
· package.
-BD-6 18 .2 160 0.02 330 465 10
-BD-7 18 .1 160 0.01 300 465 10
Vr1=200 mv ±20 mv
when In=
(ma)

4JF2-BD-501 17 10.0 325 1.0 800 - 8 Gallium Arsenide. Low for-

ward drop, h~ s~ switch-
-BD-502 17 5.0 325 .5 800 - 8 iog diode. S miniature ax-
-BD-503 17 2.0 325 .2 800 - 8 ial package.

NOTES:
(1) See General Electric Tunnel Dicxu Manual.
TRANSISTOR SPECIFICATIONS

OUTLINEDRAWINGS

0 r~r~
~(: .151
ITT

.020 MAX~ i.
(GLASS EXTENSION) 11

•
.370MAX
DIMENSIONSWITHIN .360MIN
JEDEC OUTLINE l--.335MAX
T0-5 I_ .325MIN
1011 h Thiszoneis controlled
for auto-
matichandling.Thevariationin actual
diameter
withinthiszoneshallnote1ceed
.010.
ICOTI21 Measured
frommax.diameter
ol
theactualdevice.
1011 31 Thespecified
leaddiameter
ap-
pliesin the zonebetween .050and.250
fromthebaseseat.Between .250and.5
maximum. ()f.021diameter
isheld.Outside
of thesezonesthe leaddiameter is not
controlled.leadsmaybeinserted,without
damage. in .031holeswhiletransistor
enters.371holeconcentricwithleadhole
circle.
APPROX WEIGHT: .05 OZ
ALL DIMENSIONSIN INCHES

.575MAX.
• .235MAX.

1.s· nn____LEAD
EMITIER-uir-
.-t:002•
DIA.•.017 -:OOI•
l
--1~.0481"COLLECTOR
1-,192~

406
 TRANSISTOR SPECIFICATIONS

.37OMAX
DIMENSIONS WITHIN

0
.360MIN
JEDEC OUTLINE .335MAX
TO-:S .325MIN

lllltl 11 Thiszoneis controlled

lot &Uto-
matichandlin1.The r,ri,ticxlin actuzt
CNmdetWdhin thiszone notf1ettd
111111
.010.
1111n
21Mruurfdfromm11.diameter
of
the actualdewtef.
IIOTIJ1 Thespecillf1l le~ dramftrrIP·
plies in the IOl1tbctWttn.050and.250
fromlht basestit. llft11tt11
.250and IS
muimumof .021dramdrr1shel:I.Out!ldf
of tbtse - lht If~ dramttrrIS not
controlltd.
ltidsmr,be 1nst1tfd.•ilh0ul
dama&r,rn .031holeswh1lftrznmtor
enters.371holfconctntnc•dh ~ b:>lf
cudf.

•
. 370MAX
DIMENSIONSWITHIN .360MIN
JEDEC OUTLINE.. . .TO-33 .335MAX
.325MIN

11C111 is Clll1Jo:lcd
Is TllisZ!111t forn!G-
lllllicfllndl:q.Tbtari&1icD ill aduil
N1ie1ttllilltb tllis1t1111slllll aotIXCCfd
.010.
11C111l1 llmaredlrcmmu. diameter
of
l1ltactuildmc:t.
11C111 11 Thi ~lied Ind dilmderap-
brlffll1 .050and.250
l)lia in the 111111
ITomIllebul sat. Bchlffn250and 1.5
muimum i1held.Outside
ol.OZIdiameter
olthese1011Htheluddialllfflfisaot
conlrc!ltd.
B2
E LEAD
4
LEA

81
EMITTER.. .E } LEAD2
BASEONE
•. BI GOLDLEADS
BASETW0
.. 82 .017~:ggf
INOTE3)
DIMENSIONSWITHIN
JEDEC OUTLINE
T0-5

IICl1lbTtls111111isCllllmllldba
l:lltic:llal&&,Tl:lari&ti»iaadllal
a:x!rtwbi:l!l:is1t1111sllalaoteiacd
.CIO.
lffl II llasme:llnx:I -. dilaUf ol
llltll!mldna.
IICl1ll1ThlSlleCilildadmmda1P-
plialllllll11111bclllUll.0SOad.250
flcmllll bm sal. lletwun.2SOand.5
m,dmum o1.o2Idtnm ishtld.Oatsidt
ollhallllnCStheludanftffisnot
a:allollfd.

I
-,.ioot.010
I
I- 0
407
TRANSISTOR SPECIFICATIONS

.020 IIAX.:-f j.-

lGLASS [)(TENSION) 11
,.
CUT TO O zoo•
FOft USE 1H SOCl<ETS.
LEADS TINNED DIA. .0111
MOUNTING POSITION -ANY
WEIGHT: .05 OZ.
BASE CONNECTED TO TRANS1STDR SHELL.
DIMENSIONS IN INCHES.

IIOTI
.
DIMENSIONS WITHIN
JEDEC OUTLINE
T0-18

b Mai.diamtterleadsat a ca,,ne
,230 MAX
.209 MIN
l,__J95 MAx__J
I .1711 MIN 7 e
plane.OSH.001-.000belowbase SUI .210 MAX
ta be •11hin.007al their trllt klcalioo ,170 MIN
ta mu. widthtabandtothemu.
relative
130 dilmetermeasuredwith a suitable
pge. Wh(neaie is not used.~re•
men!wdlbemadeat baseseat.
IIG1I:b Leaddilmeteris controlledin
the zonebetwttn.050and150 fromthe
base seal.Btt-,, .250and endof lead
amu.al.021 is held.
.!500 MIN
~.~!~~ 1~ =:~~.:!'~!
andSilNraclini
Ille smaller lrOffl
d1amfler
tilt larEtrdiameter. 3 LEADS
,01!1 MAX
.016 MIN
APPROX WEIGHT .015 OZ !NOTE21
ALL DIMENSIONS IN INCHES

575 ALL DIMENSIONS IN

.IWC INCHES AND ARE
• REFERENCE UNLESS

F
_·::_As_x·_......,t--T-"'0-L-ER_AN_c_E_D-.------

0 1,003 MAX.
,H7MIN,
!LEADS
.017!:ggf
(NOTE II

.505 MAX.
,497MIN.

in the mnebetween
IOTIt, lead dilmeteris cuntrolled .050and.250lromthe
baseseat.Betwttn150andendof lud a mu. of .021is hild.

408
 TRANSISTORSPECIFICATIONS

.33!1 IIAX..j
.32s 11111. I
IIOtl II LeaddumeltriSconw!ledinllle ,__....., _____
'
IJ2!1MIN
_

zone lietween.050Ind .250frClnIllecap

OI !we sat Sci- .250llld 1.125OI
I.GI 1 11111.GI.021is bel1
~MAX
IIOtl II Clearance
iSprovided to bendall
leadsIOIowrhudcircuitiywithoutinw•
luia&withbat sinkmccmlit& dlmis.
C111

ALL DIMENSIONSIN IMCHES

AND ARE REFERENCE
UNLESSTOLERANCED

IIGTIII Leiddi&IIIIICI
is conbolledin the
1011ebttwccn.050alld.250IIClnIlle bas1
ieal Sci- .250111d tndol leadI mu.
.021iSheld.
IIOTIZIOonol~tuinsetta #2·56
sludineuessGl.045.
IOTI la Cluranceis provided
lo bend
baseand cmittelluds l0r Mltiud cir•
Cllitlywitllocltinterltrin&willlhutsink
rnountina
onchassis.

ALL DIMENSIONSIN INCHES

AND ARE REFERENCEUNLESS
TOLERANCED
'll2-&6N.C.
CH0TE21--+------,
.200 :!:.010 -Jl--=1-

rf
.S7511AlC.9
__J
.SS5 MAX.
.S25UIN, l

0 •on 11Allleads 11e protected

.
..1...
CXl8e=1s8=
~~lowi~1
endolleadamax.ol.021
is held.
.065

'
.s,z 1·52

409
TRANSISTOR SPECIFICATIONS

t
A52
10n h Lead
zonebetween
diameter inthe
is controlled
.050and.250fromthecap
MAX.
or baseseat Between .250andendof
t
.300
leada max.of .021is held.
IOtl 2a Provisionis made forthedevice
to beefectrically
insulated frommounting
surfaceasshown below. Forthis service
a clearance
holeof.281is recommended.
•on 31Allexposed metalparts, including
hardware,but not including leads,are
nickelplated.
1.500
WN.

A37MAX.
,424tlN .

•200

ALL DIMENSIONS
ARE REFERENCEUNLESS TOLERANCED

'.,.2:------J~------

NOTE: .IOSDIAMAX
ALLDIMENSIONS
IN INCHES

F.no:t.on l_.1_
-B-- -~
j-- ---,--
-j.010:1:.001

AU-INSIOICSWIIICMIS
-IISIOIII &Ill A[F[A[NCt UICI.Ill '101.IIWICIO

410
 TRANSISTOR SPECIFICATIONS

L,.10+••,+•·•oJ
1 ..,N . ..,N
7 1-·•72

l DIMENSIONS ARE NOMINAL (INCHES)

2. DOTS OR LINE INDICATE CATHODE END
3. LEADS ARE GOLD PLATED, DIAMETER
.020 ! .001, SPACING .100 NOMINAL

•__ , _ _L
DOS
n-.-"'----1!--MAX.

~~ AW
+.ooz +A0Z
-.001 IMOI~~ J00MAJC.,-----""""--..1 •AOI

4D ALL 0IIIIIDISIQNS IN INCHES.

DIIIEMSIONS
ARE RU'ERENCEUNLESST0LERANCED.

.005 MAX
.075 MIN COLOR CODE FOR
TYPE DESIGNATION
(COUNTER·CLOCKWIS£)

.195 MAX
.182 MIN

.__ ___ ...__....__ HORIZONTAL

CONTACT
SURFACES
NOTES:
L ALL DIMENSIONSIN INCHES.
2. DIMENSIONSARE REFERENCES UNLESS TOLERANCED.
3. WELD FLASH ALLOWED(THIS IS NOT A CONTACTSURFACEI.
4. INSULATION- DO!!QI ALLOWCLAMPS.

411
 7

REGISTEREDJEDEC TRANSISTORTYPES MARCH 1962

For explanation of abbreviations,see page 440
MAXIMUM RATINGS ELECTRICAL PARAMETERS
JEDEC Pcmw BVce MIN. MIN. MIN. MAX. Closest Dwg.
No. Typo Use @25°C BVce• lcma T,°C hfe-hPB* @lcma fhfb me Gedb lco (µa) @Vee GE No.

2N22 Pt. 120 -100 -20 55 1.9a

2N23 Pt 80 -so -40 55 1.9a
2N24 Pt 120 -30 -25 so 2.2a
2N25 Pt. 200 -50 -30 60 2.Sa
2N26 Pt 90 -30 -40 55
2N27 NPN so 35* 100 85 100 1
2N28 NPN so 30* 100 85 100 .5
2N29 NPN so 35* 30 85 100 1 15 30
2N30 Pt Obsolete 100 30 7 40 2.2a 2T 17T OldGll
2N31 Pt Obsolete 100 30 7 40 2.2a 2T 150 25 Old GllA
2N32 Pt Obsolete 50 -40 -8 40 2.2a 2.7 21T
2N32A Pt Obsolete 50 -40 -8 40 2.2a 2.7 21T
2N33 Pt Obsolete 30 -8.5 -7 40
2N34 PNP Obsolete so -25 -8 so 40 .6 40T 2Nl90 1
2N34A PNP Obsolete 50 -25 -8 50 40 .6 40T 2Nl90 1
2N35 NPN 50 25 8 so 40 .8 40T 2Nl69 3
2N36 PNP 50 -20 -8 so 45T 40T 2Nl91 1
2N37 PNP 50 -20 -8 so 30T 36T 2Nl90 1
2N38 PNP 50 -20 -8 so 1ST 32T 2Nl89 1
2N38A PNP so -20 -8 50 18T 34 -12 -3 2Nl89 1
2N41 PNP so -25 -15 so 40T 40T -10 -12 2Nl90 1
2N43 PNP AF 240 -30 -300 100 30 1 .s -16 -45 2N43, 2N525 1, 2
2N43A PNP AF 240 -30 -300 100 30 1 .15 -16 -45 2N43A, 2N525 l, 2
2N44 PNP AF 240 -30 -300 100 25T 1 .5 -16 -45 2N44, 2N524 1, 2
2N45 PNP Obeolete 155 -25 -10 100 25T .5 34 -16 -45 2N44 1
2N46 PNP 50 -25 -15 so 40T 4T -10 -12 2Nl414 2
2N47 PNP so -35* -20 65 .975a -5 -12 2Nl414 2
2N48 PNP so -35• -20 65 .970a -5 -12 2Nl414 2
2N49 PNP 50 -35* -20 65 .975 -5 -12 2Nl414 2
2NSO Pt. so -15 -1 so 2a 3T
2N51 Pt 100 -so -8 so 2.2a -350 -7
2N52 Pt. 120 -so -8 so
2N53 Pt -so -8
2N54 PNP 200 -45 -10 60 .95a 40T 2Nl098 J6V 2
2NSS PNP 200 -45 -10 60 .92a 39T 2Nl097 16V 2
2N56 PNP 200 -45 -10 60 .90a 38T 2N320 4
2N59 PNP 180 -25* -200 85 90T* -100 35T -15 -20 2Nl415 2
2N59A PNP 180 -40• -200 85 90T* -100 35T -15 -20 2Nl415 2
2N59R J>NP 180 -50* -200 85 90T* -100 35T -15 -20
 MAXIMUM RATINGS ELECTRICALPARAMETERS

JEDEC Pcmw BVcB MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use @25°C BVce• lcma T.1°C hre-hPE* @lcma fhfb me Gedb lco (µa) @Vee GE No.
2N59C PNP 180 -60• -200 85 90T• -100 35T -15 -20
2N60 PNP 180 -2s• -200 85 6ST• -100 35T -15 -20 2Nl415 2
2N60A PNP )80 -40* -200 85 6ST• -100 35T -15 -20 2N1415 2
2N60B PNP 180 -so• -200 85 6ST• -100 35T -15 -20 2Nl925 2
2N60C PNP 180 -60* -200 85 6ST• 100 35T -15 -20 2Nl926 2
2N61 PNP 180 -2s• -200 85 45T* 100 35T -15 -20 2Nl415 2
2N61A PNP 180 -40* -200 85 45T* 100 35T -15 -20 2N1415 2
2N61B PNP 180 -so• -200 85 4ST• 100 35T -15 -20 2Nl924 2
2N61C PNP 180 -60* -200 85 4ST• 100 35T -15 -20 2Nl924 2
2N62 PNP so -35* -20 .975aT
2N63 PNP 100 -22 -10 85 22T 1 39T -6 -6 2Nl924 2
2N64 PNP 100 -15 -10 85 45T 1 41T -6 -6 2Nl415 2
2N65 PNP 100 -12 -10 85 90T 1 92T -6 -6 2N324 4
2N66 PNP lW -40 .SA 80 .2 -300 -40
2N67 PNP 2W -25* -I.SA 70 23T
2N68 PNP 2W -2s• -I.SA 23 -150 ma
2N71 PNP IW -so -250 60 .25 20
2N72 Pt 50 -40 -20 55 2.5
2N73 PNP 200 -so 2Nl614 1
2N74 PNP 200 -so 2Nl614 1
2N75 PNP 200 -20 2Nl614 1
2N76 PNP Obsolete 50 -20• -10 60 .90a 1.0 34 -10 -20 2N322 4
2N77 PNP -25* -15 85 55 .70 44T -10 -12 2N324 4
2N78 NPN RF/IF 65 15 20 85 45• 1 5 27 3 15 2N78 3
2N78A NPN RF/IF 65 20 20 85 45• l 5 29 3 15 2N78A 3
2N79 PNP 35 -30 -so 46 .7 44 2N321, 2N323 4,4
2N80 PNP so -25 -8 100 BOT -30 -10 2N508, 2Nll75 2,2
2N81 PNP Obsolete so -20 -15 100 20 1 -16 -30 2Nl098 2
2N82 PNP 35 at 71 ° C -20 -15 100 20 l -16 -30 2Nl098 2
2N94 NPN 30 20 5 75 40T .s 3T 25T 3 10 2N634, 2Nl69A 2,3
2N94A NPN 30 20 5 75 40T .5 6T 25T 3 10 2N634, 2Nl69A 2, 3
2N95 NPN 2.SW 25* 1.5 70 40 .4T 23T
2N96 PNP 50 -30 -20 55 35 .5 2Nl414 2
2N97 NPN so 30 10 75 .85a .5 38T 10 4.5 2Nl69 ISV 3
2N97A NPN so 40 10 85 .BSa .5 38T 5 30 2Nl69A 25V 3
2N98 NPN 50 40 10 75 .95a .8 47T 10 4.5 2Nl69A 25V 3
2N98A NPN so 40 10 85 .96a .8 47T 10 4.5 2Nl69A 25V 3
2N99 NPN so 40 10 75 .95a 2.0 47T 10 4.5 2Nl69A 25V 3
2NlOO NPN 25 25 5 50 .99or 2.5 53T 10 4.5 2Nl70 6V 3
2NI01 PNP IW -25* -1.5 70 23T
2NI02 NPN IW 25* 1.5 70 23T
2NI03 NPN 50 35 10 75 .60a .75T 33T so 35 2Nl302 2
 7

MAXIMUM RATINGS ELECTRICALPARAMETERS

JEDEC Pcmw BVcs MIN. MIN. MIN. MAX. Closest Dwg.
No. Type Use @25°C BVce• lcma T,oc hre-hrs• @lcma fhfb me Gedb lco (µa) @Vee GE No.

2Nl04 PNP 150 -30 -50 85 44 .7 33T -10 -12 2Nl415. 2Nl414 2,2
2Nl05 PNP 35 -25 -15 85 55 .7 .75 42 -5 -12 2Nl415 2
2Nl06 PNP 100 -6 -10 85 25 .8 28 -12 -6 2Nl097. 2Nl098 2,2
2Nl07 PNP AF so -6 -10 60 20 .6 -10 -12 2Nl07, 2Nl098 1, 2
2Nl08 PNP 50 -20 -15 2N322 4·
2Nl09 PNP 150 -25 -70 85 75• 30T 2Nll75 2
2Nll0 Pt 200 -so• -so 85 32 1.5
2Nlll PNP 150 -15 200 85 15 3T 33T -5 -12 2N394 2
2NlllA PNP 150 -15 -200 85 15 3T 33T -5 -12 2N394 2
2Nll2 PNP 150 -15 -200 85 15 ST 35T -5 -12 2N394 2
2N112A PNP 150 -15 -200 85 15 ST 35T -5 -12 2N394 2
2Nll3 PNP 100 -6 -5 85 45T lOT 33T 2N394 2
2N114 PNP 100 -6 -5 85 65T 20T 2N394 2
2Nll7 NPN 150 30* 25 150 .90a 1 1 10 30 2N332, 2N334 4,4
2N118 NPN 150 so• 25 150 .95a 1 2 10 30 2N333, 2N335 4, 4
2N118A NPN-G 150 45 25 ISOJ 54T 7.50 10 2N335 4
2Nll9 NPN 150 so• 25 150 .974a 1 2 10 30 2N335, 2N336 4, 4
2Nl20 NPN 150 45• 25 175 .987a ) 7T 2 30
2Nl22 NPN 8.75W HOA 150 3 100 !Oma 50
2Nl23 PNP Sw 150 -15 -125 85 so• -10 5 -6 -20 2Nl23 7
2N124 NPN 50 10• 8 75 12• 5 3 2 5 2N293 3
2Nl25 NPN so 10• 8 75 24• 5 5 2 5 2Nl67 3
2Nl26 NPN so 10• 8 75 48• 5 5 2 5 2Nl67, 2Nl69 3, 3
2Nl27 NPN so 10• 8 75 100• 5 5 2 5 2Nl67, 2N169 3,3
2N128 PNP 30 -4.5 -5 85 .95 .5 45 rmu: -3 -5 2N711 8
2Nl29 PNP 30 -4.5 -5 85 .92 .5 30 rmu: -3 -5 2N711 8
2Nl30 PNP 85 -22 -10 85 22T 39T 2Nl413, 2Nl924 2, 2
2Nl30A PNP 100 -40 -100 85 14 1 .7T 40T -15 -20 2N1413. 2Nl924 2, 2
2Nl31 PNP 85 -15 -10 85 45T 41T 2Nl413, 2Nl415 2, 2
2Nl31A PNP 100 -30 -100 85 27 1 .BT 42T -15 -20 2Nl413, 2N1924 2,2
2Nl32 PNP 85 -12 -10 85 90T 42T 2Nl175 2
2Nl32A PNP 100 -20 -100 85 56 1 IT 44T -15 -20 2Nl415 2
2Nl33 PNP 85 -15 -10 85 25 36T -12 -15 2Nl414 3
2N133A PNP 100 -20 -100 85 SOT 1 .BT 38T -15 -20 2Nl414, 2Nll75 3,2
2Nl35 PNP Obsolete 100 -12 -so 85 20T 4.ST 29T 2N394 2
2Nl36 PNP Obaolete 100 -12 -so 85 40T 6.5T 31T 2N394 2
2Nl37 PNP Obsolete 100 -6 -50 85 60T lOT 33T 2N394 2
2N138 PNP so -12 -20 50 140T 30T 2NS08 2
2Nl38A PNP 150 -30 -100 85 29T 2Nl098 2
2Nl38B PNP 100 -30 -100 85 29T 2Nl098 2
2Nl39 PNP 80 -16 -15 85 48 1 6.8 30 -6 -12 2N394 2
2Nl40 PNP 35 -16 -15 85 45 .4 7 27 -6 -12 2N394, 2N395 2,2
 MAXIMUM RATINGS ELECTRICAL
PARAMETERS
JEDEC Pcmw BVce MIN. MIN. MIN. MAX. Closest Dwg.
No. Type Use @25°C BVca• lcma T,oc hfe-hvE• @lcma fbfb me Gedb lco (µa) @Vea GE No.
2Nl41 PNP 4W -30 -.BA 65 .975aT so .4T lBT -100 -20
2Nl42 NPN 4W 30 .BA 65 .975aT · -50 .4T 26T -100 20
2N143 PNP 4W -30 -.BA 65 .975aT so .4T 26T -100 -20
2Nl44 NPN 4W 30 .BA 65 .975aT so .4T 26T 100 20
2N145 NPN 65 20 5 75 30 30 3 9 2N293, 2Nll21 3, 3
2Nl46 NPN 65 20 5 75 33 33 3 9 2Nll21 3
2Nl47 NPN 65 20 5 75 36 36 3 9 2Nll21 3
2Nl48 NPN 65 16 5 75 32 3 12 2N169 3
2Nl48A NPN 65 32 5 75 32 3 12 2N169 3
2Nl49 NPN 65 16 5 75 35 3 12 2Nl69 3
2Nl49A NPN 65 32 5 75 35 3 12 2Nl69 3
2Nl50 NPN 65 16 s 75 38 3 12 2Nl69 3
2Nl50A NPN 65 32 s 75 38 3 12 2Nl69 3
2N155 PNP B.SW -30• -3A 85 .lST 30 1 ma -30
2N156 PNP 8.SW -30* -3A 85 24* .SA .lST 33 1 ma -30
2Nl57 PNP B.SW -60• -3A 85 20* .SA .l 1 mo -60
2Nl57A PNP 8.SW -9o• -3A 85 20• .SA .1 1 ma -90
2Nl58 PNP 8.SW -60• -3A 85 21* .SA .lST 37 1 ma -60
2N158A PNP 8.SW -so• -3A 85 21* .SA .15 l ma -80
2Nl60 NPN 150 40* 25 150 .9a -1 4T 34T 5 40 2N332, 2Nl276 4, 4
2Nl60A NPN 150 40• 25 150 .9a -1 4T 34T s 40 2N332 4
2Nl61 NPN 150 40• 25 150 .95a -1 ST 37T 5 40 2N333, 2Nl277 4, 4
2Nl61A NPN 150 40* 25 150 .95a -1 ST 37T s 40 2N333 4
2N162 NPN 150 40• 25 150 .95a -1 8 38T 5 40 2N335, 2Nl278 4. 4
2Nl62A NPN 150 40• 25 150 .95a -1 8 38T 5 40 2N335 4
2N163 NPN 150 40• 25 150 .975a -1 6T 40T 5 40 2N335, 2N 1278 4, 4
2Nl63A NPN 150 40• 25 150 .975a -1 6T 40T 5 40 2N335 4
2Nl64A NPN 65 1.0• 20 BSJ 40T 8.00 30 2Nll21 3
2Nl65 PNP-M 55 1.0• 20 75J 72T 5.00 26 2Nl6CJ 3
2Nl66 NPN Obsolete 25 6 20 so 32T l ST 24T 5 s 2Nl70 :1
2Nl67 NPN Sw 65 30 75 85 11• 8 s 1.5 15 2Nl67 3
2Nl67A NPN Sw 65 30 75 85 17* 8 5 1.5 15 2Nl67A 3
2Nl68 NPN IF 55 15 20 75 20T 1 6T 28 5 15 2N293 3
2Nl6BA NPN Obsolete 65 15 20 85 23* 1 5 28 5 15 2Nl086, 2Nll21 3, 3
2Nl69 NPN IF 65 15 20 85 34• 1 BT 27 5 15 2N169 :1
2NI69A NPN AF 65 15 20 85 34* I BT 27 5 15 2Nl69A 3
2N17o NPN IF 25 6 20 so .95aT 1 4T 22T 5 5 2Nl70 3
2Nl72 NPN 65 16 5 75 22 3 9 2N2CJ3 3
2N173 PNP 40W -60 -13A 95 SST• IA .6T 40T -.Sma -40
2Nl74 PNP 40W -80 -13A 95 40T• IA .2T 39T -lOma -60
2Nl74A PNP SSW -80 -ISA 95 40• 1.2A .1 -Bma -80
2N175 PNP 20 -10 -2 85 65 .s 2 43T -12 -25 2Nll75A 2
 MAXIMUM RATINGS ELECTRICALPARAMETERS

JEDEC Pcmw BVcE MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use @25°C BVca• lcma T,°C hfe•hPE* @lcma fhfb me Gedb lco {µa) @Vee GE No.

2N176 PNP 3W -12 -600 80 25T

2N178 PNP 3W -12 -600 80 29T
2N179 PNP -20 -60 88 32T
2Nl80 PNP 150 -30 -25 75 60T .7 37T 2Nl415 2
2Nl81 PNP 250 -30 -38 75 60T .7 34T 2N526 2
2Nl82 NPN 100 2s• 10 85 2ST• 2.5 3T 10 2N634A 2
2Nl83 NPN 100 25• 10 85 SOT• 5 3T 10 2N634A 2
2Nl84 NPN 100 25• 10 85 l00T• 10 3T 10 2N635A 2
2Nl85 PNP 150 -20 -150 75 35 -100 26 15 -20 2N323 4,4
2Nl86 PNP Obsolete 100 -25 200 85 24T• -100 .ST 28 -16 -25 2Nl86A, 2Nl413 1, 2
2Nl86A PNP AF Out 200 -25 200 85 24T* -100 .ST 28 -16 -25 2Nl86A 1
2Nl87 PNP Obsolete 100 -25 200 85 36T• -100 IT 30 -16 -25 2Nl87A. 2Nl41:I 1. 2
2Nl87A PNP AF Out 200 -25 200 85 36T* -100 IT 30 -16 -25 2Nl87A l
2Nl88 PNP Obsolete 100 -25 -200 85 54T* 100 1.2T 32 -16 -25 2Nl88A, 2Nl413 l. 2
2Nl88A PNP AF Out 200 -25 -200 85 54T• 100 l.2T 32 -16 -25 2Nl88A l
2Nl89 PNP AF 75 -25 -so 85 24T• 1 .BT 37 -16 -25 2Nl89, 2Nl413 l, 2
2Nl90 PNP AF 75 -25 -so 85 36T• l I.OT 39 -16 -25 2Nl90, 2Nl414 I, 2
2Nl91 PNP AF 75 -25 -50 85 54T* 1 1.2T 41 -16 -25 2N191, 2NI415 1, 2
2Nl92 PNP AF 75 -25 -50 85 7ST• I I.ST 43 -16 -25 2NJ92, 2Nll75 1, 2
2Nl93 NPN 50 15 75 3.8 1 2 40 15 2Nl086 3
2Nl94 NPN 50 15 75 4.8 I 2 15T 40 15 2Nl086 3
2Nl94A NPN 50 20 100 75 5 1 2 20 50 18 2Nl087 3
2N206 PNP 75 -30 -50 85 47T .8 2N1414 2
2N207 PNP 50 -12 -20 65 35 1 2T -15 -12 2Nl415, 2N323 2,4
2N207A PNP so -12 -20 65 35 1 2T -15 -12 2Nl415, 2Nll75A 2, 2
2N207B PNP 50 -12 -20 65 35 I 2T -15 -12 2Nl415, 2Nll75A 2, 2
2N211 NPN 50 10 50 75 3.8 l 2 20 10 2N293, 2NI086 3, 3
2N212 NPN 50 10 so 75 7 l 4 22T 20 10 2N293, 2Nl086 3,3
2N213 NPN so 25 100 75 70 l 39 200 40 2Nl69A 3
2N213A NPN 150 25 100 85 100 1 10 Kc 38 50 20 2N636A 2
2N214 NPN 125 25 75 75 so 35 .6 26 200 40 2N635A 2
2N215 PNP 150 -30 -50 85 44 .7 33T -10 -12 2Nl415 2
2N216 NPN so 15 50 75 3.5 I 2 26T 40 15 2N292, 2Nl086 3, 3
2N217 PNP 150 -25 -70 85 75• 30T 2N321, 2N396 4. 2
2N218 PNP 80 -16 -15 85 48 I 6.8 30 -6 -12 2N394 2
2N219 PNP 80 -16 -15 85 75 .4 10 32 -6 -12 2N394 2
2N220 PNP 50 -10 -2 85 65 .8 43 2N323, 2Nll75A 4,2
2N223 PNP 100 -18 -150 65 39 -2 .6T -20 -9 2N323 4
2N224 PNP 250 -2s• 150 75 60• -100 .ST -25 -12 2N321, 2Nll75 4,2
2N225 PNP 250 -25• 150 75 60• -100 .ST -25 -12 2N321, 2Nll75 4, 2
2N226 PNP 250 -30• 150 75 35• -100 .4T -25 -30 2N321, 2Nl415 4,2
2N227 PNP 250 -30• 150 75 35• -100 .4T -25 -30 2N321, 2Nl415 4,2
 MAXIMUM RATINGS ELECTRICALPARAMETERS

JEDEC Pcmw BVcE MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use @25°C BVca• lcma T.10C hfe-hFE* @lcma fhfb me Gedb lco (µa) @Vee GE No.
2N228 NPN 50 25 50 75 50 35 .6 23 200 40 2Nl69, 2N6:l4A :1, 2
2N229 NPN 50 12 40 75 .9a 1 .55 200 5 2Nl69 3
2N231 PNP 9 -4.5 -3 55 19 -.5 20 foe -3 -5 2N711 8
2N232 PNP 9 -4.5 -3 55 9 -.5 30 foe -6 -5 2N711 8
2N233 NPN 50 10 50 75 3.0 1 100 10 2N448, 2N292 3,3
2N233A NPN 50 10 50 75 3.5 1 150 15 2N448, 2N292 3. 3
2N234 PNP 25W -30 -3A 90 8 Kc 25 -1 maT -25
2N234A PNP 25W -30 -3A 90 8 Kc 25 -1 ma T -25
2N235 PNP 25W -40 -3A 90 7 Kc 30
2N235A PNP 25W -40 -3A 90 7 Kc 30
2N2358 PNP 40 3.0A 85 300 3
2N236 PNP 25W -40 -3A 95 6 Kc 30 -1 ma -25
2N236A PNP 25W -40 -3A 95 6 Kc 30 -1 ma -25
2N2368 PNP 40 3.0A 95 300 2
2N237 PNJ> 150 45 20 85 SOT .so 10 2N525 2
2N238 PNP so -20 75 37 -20 -20 2N323 4
2N240 PNP 10 -6 -15 16 -.5 30 foe -3 -5 2N711 8
2N241 PNP Obsolete 100 -25 200 85 73T* 100 1.3T 35T -16 -25 2N241A 1
2N241A PNP AF Out 200 -25 200 85 73T* 100 1.3T 35T -16 -25 2N241A, 2Nt415 1, 2
2N242 PNP 20W -45 -2A 85 5 Kc 30 -5ma -45
2N243 NPN 750 60* 60 150 .9 -5 30 I 30
2N244 NPN 750 60* 60 150 .961 -5 30 1 30
2N247 PNP 80 -12 -10 85 60 30 37 -20 -12
2N248 PNP 30 -25 -5 85 20T• .5 SOT -10 -12
2N249 PNP 350 -25 -200 85 30 -100 -25 -25
2N250 PNP 12W -30 -2A 80 30• -.SA -1 ma -30
2N251 PNP 12W -60 -2A 80 30* -.SA 30 -2 ma -60
2N252 PNP 30 -16 -5 55 28 -10 -12
2N253 NPN 65 12 5 75 32 3 9 2N293, 2Nl121 3, 3
2N254 NPN 65 20 5 75 3 9 2N293, 2Nl 121 3,3
2N255 PNP I.SW -1s• -3 85 .2T 19
2N255A PNP 20W 15 4A 85 25• 450 5 mo 15
2N256 PNP I.SW -30* -3 85 .2T 22
2N256A PNP 20W 25 4A 85 2s• 450 Sma -25
2N257 PNP 2W -40* 85 SST .SA 7 Kc 30 -2 mo -40
2N260 PNP 200 -10• -50 150 16T 1 I.BT 38T .OOlT -6 2N332, 2N 1276 4, 4
2N260A PNP 200 -so• -50 150 16T 1 1.8T 38T .OOlT -6 2N332 4
2N261 PNP 200 -75* -50 150 IOT 1 1.8T 36T .OOlT -6 2N332 4
2N262 PNP 200 -10• -50 150 20T 1 6T 40T .OOlT -6 2N333 4
2N262A PNP 200 -30* -so 150 20T 1 6T 40T .OOlT -6 2N333 4
2N265 PNP 75 -25 -50 85 HOT* l I.ST 45 -16 -25 2N265, 2N508 1. 2
2N267 PNP 80 -12 -10 85 60 30 37 -20 -12
 MAXIMUM RATINGS ELECTRICAL
PARAMETERS
JEDEC Pcmw BVce MIN. MIN. MIN. MAX. Closest Dwg.
No. Type Use @25°C BVce• lcma T.10C hfe-hve• @lcma fhfb me Gedb lco (µa) @Vee GE No.
2N268 PNP 2W -so• 85 6 Kc 28 -2ma -80
2N268A PNP 2W -60 90 20• 2A -2ma -80
2N269 PNP 120 -24 -100 85 35 4 -s -12 2N404 2
2N270 PNP 150 -25 -75 85 70 150 35 -10 -25 2N321. 2Nl415 4,2
2N271 PNP ISO -10 -200 85 4ST l lOT 29T -5 -12 2N394 2
2N271A PNP 150 -10 -200 85 45T I lOT 39T -5 -12 2N394 2
2N272 PNP 150 -24 -100 85 60 IT 12T -6T -20 2N324 4
2N273 PNP 150 -30 -100 85 10 50 29 -6T -20 2Nl098 2
2N274 PNP 80 -12 -10 85 60T l JOT 45T -20 -12
2N277 PNP SSW -40 12A 95 SST 1.2A .ST 34T -.5 ma T -30
2N278 PNP SSW -SO 12A 95 SST 1.2A .ST 34T -.5 ma T -20
2N281 PNP 165 32 250 75.J 70T* .90 10 2Nl415 2
2N285 PNP 25W -40 3A 95 6 Kc 38 -1 ma -25
2N285A PNP 25W -40 3A 95 6 Kc 38 -1 ma -25
2N290 PNP SSW -70 -12A 95 72T* 1.2A .4T 37T -1 maT -60
2N291 PNP 180 -25 -200 85 30* 100 31 -25 -25 2N320, 2Nl414 4,2
2N292 NPN IF 65 15 -20 85 8 l ST 25.5 5 15 2N292 3
2N293 NPN IF 65 15 -20 85 8 I 8T 28 5 15 2N293 3
2N297 PNP 35W -so -SA 95 40* .5 5 Kc 3ma -60
2N297A PNP 35W . -so -SA 95 40• .5 5 Kc 3ma -60
2N299 PNP 20 -4.S -5 85 90 fo• 20 -3 -5
2N300 PNP 20 -4.S -5 85 11 .5 85 foe -3 -5
2N301 PNP nw -20 -I.SA 91 70T* lA 33T -3ma -30
2N301A PNP nw -30 -I.SA 91 70T* IA 33T -3ma -30
2N302 PNP 150 -10 -200 85 45T 7 -IT -.12 2Nl86A 1
2N303 PNP 150 -10 -200 85 75T 14 -IT -.12 2Nl86A l
2N306 NPN so 15 75 25 1 .6 34 so 20 2N292 3
2N307 PNP lOW -35 -IA 75 20 200 3 Kc IS ma -35
2N307A PNP 17W -35 -2A 75 20 200 3.5 Kc 22 7ma -35
2N308 PNP 30 -20 -5 55 39 -10 -9
2N309 PNP 30 -20 -5 55 41 -10 -9
2N310 PNP 30 -30 -5 55 28T 37T -10 -9
2N311 PNP 75 -15 85 25 -60 -15 2Nl23 7
2N312 NPN 75 15 85 25 60 15 2Nl67 3
2N313 NPN Obsolete 65 15 20 85 25 5 36max Use 2N292 3
2N314 NPN Obsolete 65 IS 20 85 25 8 39 max Use 2N293 3
2N31S PNP 100 -15 -200 85 15 100 ST -2 -5 2N396 2
2N315A PNP-A 150 30 JOOS 3ST• 5.00 25 2N396 2
2N316 PNP 100 -10 -200 85 20 200 12T -2 -5 2N397 2
2N316A PNP-A 150 30 1008 3ST• 12.0 25 2N397 2
2N317 PNP 100 -6 -200 85 20 400 20T -2 -5
2N318 PNP Photo so -12 -20 .75T
 MAXIMUM RATINGS ELECTRICAL PARAMETERS

JEDEC Pcmw BVcE MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use @25°C BVce• lcma T,°C hfe-hvE• @lcma fhfb me Gedb lco (µa) @Vee GE No.
2N319 PNP AF 225 -20 -200 85 34T• -20 2T -16 -25 2N319, 2Nl413 4,2
2N320 PNP AF 225 -20 -200 85 SOT* -20 2.ST -16 -25 2N320, 2Nl414 4,2
2N321 PNP AF 225 -20 -200 85 BOT• -20 3.0T -16 -25 2N321, 2Nl415 4,2
2N322 PNP AF 140 -16 -100 60 45T -20 2T -16 -16 2N322 4
2N323 PNP AF 140 -16 -100 60 68T -20 2.ST -16 -16 2N323 4
2N324 PNP AF 140 -16 -100 60 SST -20 3.0T -16 -16 2N324 4
2N325 PNP 12W -35 -:?A 85 30• -500 .15 -500 -30
2N326 NPN 7W 35 2A 85 30* 500 .15 500 30
2N327 PNP 335 -so• -100 160 9 .1 .3T 30 -.1 -30
2N327A PNP 350 -so• -100 160 9* 1 .2T -.1 -30
2N328 PNP 335 -35• -100 160 18 l .35T 32 -.1 -30
2N328A PNP 350 -so• -100 160 18• l .3T -.1 -30
2N329 PNP 335 -3o• -100 160 36 l .6T 34 -.1 -30
2N329A PNP 350 -so• -100 160 36* l .ST -.1 -30
2N330 PNP 335 -45• -50 160 9 l .5 30 -.1 -30
2N330A PNP 350 -so• -100 160 25T l .5 34T -.1 -30
2N331 PNP 200 -30• -200 85 SOT 44T -16 -30 2N1415 2
2N332 NPN Si AF 150 45* 25 200 9 l lOT 14T 2 30 2N332 4
2N332A NPN Si AF 500 45 25 175 9 2.5 11 .500 30 2N332A 4
2N333 NPN Si AF 150 45* 25 200 18 1 12* 14T 2 30 2N333 4
2N333A NPN Si AF 500 45 25 175 18 2.5 11 .500 30 2N333A 4
2N334 NPN Si AF 150 45• 25 200 18 1 8 13T 2 30 2N334 4
2N334A NPN Si AF 500 45 25 175 18 8.0 12 .500 30 2N334A 4
2N335 NPN Si AF 150 45• 25 200 37 1 14* 13T 2 30 2N335 4
2N335A NPN Si AF 500 45 25 175 37 2.5 12 .500 30 2N335 4
2N335B NPN Si AF 500 @ 25 175 37 2.5 12T .500 30 2N335B 4
2N336 NPN Si AF 150 45• 25 200 76 l 1s• 12T 2 30 2N336 4
2N336A NPN Si AF 500 45 25 175 76 2.5 12 .500 30 2N336A 4
2N337 NPN Si AF 125 45• 20 200 19 1 10 1 20 2N337 4
2N337A NPN-G 500 45 20 2008 35T 30.0 .10 2N337A 4
2N338 NPN Si AF 125 45• 20 200 39 l 20 I 20 2N338 4
2N338A NPN-G 500 45 20 2008 75T 45.0 .10 2N338A 4
2N339 NPN lW 55* 60 150 .9a -5 30 1 30 2N656A 2
2N339A NPN 1000 60 200S 53T 1.0 2N656A 2
2N340 NPN lW as• 60 150 .9a -5 30 1 30 2N657A 2
2N340A NPN 1000 85 15oJ SOT 30 1.0 2N657A 2
2N341 NPN lW 125• 60 150 .9a -5 30 1 30 2N657A 2
2N341A NPN 1000 125 2008 53T 30 1.0 2N657A 2
2N342 NPN lW 60* 60 150 .9a -5 30 1 30 2N656A 2
2N342A NPN-G 1000 85 60 150J 20T 30 1.0 2N657A 2
2N342B GD 1000 85 60 lSoJ 21T 6.00 50 2N335B, 2N657 A 4,2
2N343 NPN lW 60* 60 150 .966a -5 30 1 30 2N656A 2
 MAXIMUM RATINGS ELECTRICALPARAMETERS

JEDEC Pcmw BVcE MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use @25°C BVce* lcma T,°C hre-hFE* ®lcma fhfb me Gedb lco (µa) ®Vee GE No.

2N343B GD 1000 65 60 lSOJ 59T 6.00 100 2N335B, 2N656A 4, 2

2N344 PNP 40 -5 -5 85 11 30 foe -3 -5 2N962 8
2N345 PNP 40 -5 -5 85 25 30 foe -3 -5 2N962 8
2N346 PNP 40 -5 -5 85 10 60 fo1 -3 -5 2N962 8
2N348 NPN-G 750 90 so lSOJ 24T 3.00 35 6.0 2N292 3
2N349 NPN-G 750 125 40 lSOJ 19T 3.00 34 8.0 2N293 3
2N350 PNP lOW -40* -3A 90 20• -700 5 Kc 30 -3ma -30
2N351 PNP lOW -40• -3A 90 25• -700 5 Kc 32 -3ma -30
2N352 PNP 25W -40 -2A 100 30 -lA 10 Kc 30 -Sma -1@ 85°C
2N353 PNP 30W -40 -2A 100 40 -IA 7 Kc 30 -Sma -1 @85°C
2N354 PNP 150 -2s• -so 140 9 l 8 fo1 -.1 -10
2N355 PNP 150 -10• -so 140 9 1 8 fo1 -.1 -10
2N356 NPN 120 18 100 85 20 100 3T 5 5 2N634A 2
2N356A NPN-A 150 30 1008 35T* 3.00 25 2N634 2
2N357 NPN 120 15 100 85 20 200 6T 5 5 2N634A 2
2N357A NPN-A 150 30 1008 40T* 6.00 25 2N634A 2
2N358 NPN 120 12 100 85 20 300 9T 5 5 2N635A 2
2N358A NPN-A 150 30 1008 40T* 9.00 25 2N635A 2
2N359 PNP-A 150 20 400 85 300T 1.50 40 10 2NS08 2
2N360 PNP-A 150 400 85 150T 1.20 37 10 2Nl415 2
2N361 PNP-A 150 20 400 85 75T 1.00 34 10 2Nl41:l 2
2N362 PNP-A 150 18 100 85 90T 2.00 42 15 2N324 4
2NS63 PNP-A 150 32 100 85 SOT I.SO 39 15 2Nl414 2
2N364 NPN 150 30* 50 85 9 -1 l 10 30 2Nl694 2
2N365 NPN 150 30* so 85 19 -1 l 10 30 2Nl694 2
2N366 NPN 150 30* so 85 49 -1 l 10 30
2N367 NPN 100 -30* -so 75 9 1 .3 -30 -30 2Nl413 2
2N368 PNP 150 -30* -so 75 19 1 .4 -20 -30 2Nl413 2
2N369 PNP 150 -30* -50 75 49 1 .5 -20 -30 2Nl415 2
2N370 PNP 80 -24* -20 85 60T 1 30T 31M -10 -12
2N371 PNP 80 -24* -20 85 .984T 1 30T 17.6M -10 -12
2N372 PNP 80 -24* -20 85 60T 1 30T 12.5M -10 -12
2N373 PNP 80 -24* -10 85 60T l 30T 40T -16 -12
2N374 PNP 80 -24* -10 85 60T 1 30T 40T -16 -12
2N375 PNP 45W -60 -3A 95 35 IA 7 Kc -3ma -60
2N376 PNP lOW -40• -3A 90 60T lA 5 Kc 35T
2N377 NPN Sw 150 20 200 100 20• 30 6T 5 l 2N377 2
2N377A NPN 150 40 200 100 20• 200 6T 40 40 2N377 2
2N378 PNP sow -40 -SA 100 15* 2A 5 Kc -500 -25
2N379 PNP sow -80 -SA 100 20• 2A 5 Kc -500 -25
2N380 PNP sow -60 -SA 100 30* 2A 7 Kc -500 -25
2N381 PNP 200 -25 -200 85 SOT 20 1.2T 31T -lOT -25 2N320. 2Nl924 4,2
 MAXIMUM RATINGS ELECTRICALPARAMETERS

JEDEC Pcmw BVce MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use @25°C BVce• lcma T,oc hfe-hFE* @lcma fhfb me Ge db lco (µa) @Vee GE No.
2N382 PNP 200 -25 -200 85 75T 20 I.ST 33T -lOT -25 2N321. 2Nl927 4, 2
2N383 PNP 200 -25 -200 85 IOOT 20 1.8T 35T -IOT -25 2N321, 2Nll75 4,2
2N384 PNP 120 -30 -10 85 60T 1.5 IOOT 15 -16 -12
2N385 NPN 150 25 200 100 30* 30 4 35 25 2N385 2
2N385A NPN-A 150 40 200 lOOJ 70T 8.00 40 2N385A 2
2N386 PNP 12.SW -60 -3A 100 20 -2.SA 7 Kc -Sma -60
2N387 PNP 12.SW -80 -3A 100 20 -2.SA 6 Kc -Sma -80
2N388 NPN Sw 150 20 200 100 60* 30 5 10 25 2N388 2
2N388A NPN 150 40 200 100 30* 200 5 40 40 2N388 2
2N389 NPN BSW 60 200 12 IA 10 ma 60@ 100°(
2N392 PNP 70W -60* -SA 95 60 3A 6 Kc -8ma -60
2N393 PNP so -6 -50 85 20• -so 40 foe -5 -5 2N711A 8
2N394 PNP Sw 150 -10 -200 85 20• -10 4 -6 -10 2N394 2
2N394A PNP-A 150 30 200 lOOS 70T* 7.00 6.0 2N394A 2
2N395 PNP Sw 200 -15 -200 100 20• -10 3 -6 -15 2N395 2
2N396 PNP Sw 200 -20 -200 100 30* -10 5 -6 -20 2N396 2
2N396A PNP Sw 200 20 200 100 30* 10 5 -6 -20 2N396A 2
2N397 PNP Sw 200 -15 -200 100 40* -10 10 -6 -15 2N397 2
2N398 PNP 50 -105 -110 85 20• -Sma -14 -2.5 2Nl614 1
2N398A PNP 150 105 lOOJ 20T 1.00 2Nl924 2
2N399 PNP 25W -40 -3A 90 8 Kc 33T -1 ma -25
2N400 PNP 25W -40 3.0A 95 1 40 2ma -25
2N401 PNP 25W -40 -3A 90 8 Kc 30T -Ima -25
2N402 PNP 180 -20 -150 85 .96aT 1 .6T 37T -15 -20 2N320, 2Nl413 4,2
2N403 PNP 180 -20 -200 85 .97aT 1 .SST 32 -15 -20 2N319, 2N1413 4,2
2N404 PNP Sw 120 -24 -100 85 4 -5 -12 2N404 2
2N404A PNP-A Sw 150 -10 150 100 8.00 20 2N404A 2
2N405 PNP 150 -18 -35 85 35T* 1 .6ST 43T -14 -12 2N322 4
2N406 PNP 150 -18 -35 85 35T* 1 .65T 43T -14 -12 2N322 4
2N407 PNP 150 -18 -70 85 65T* -so 33T -14 -12 2N323 4
2N408 PNP 150 -18 -70 85 65T* -so 33T -14 -12 2N323 4
2N409 PNP 80 -13 -15 85 .98aT 1 6.7T 38T -10 -13 2N394 2
2N410 PNP 80 -13 -15 85 .98aT 1 6.7T 38T -10 -13 2N394 2
2N4ll PNP 80 -13 -15 85 75T .6 32T -10 -13 2N397 2
2N412 PNP 80 -13 -15 85 75T .6 32T -10 -13 2N397 2
2N413 PNP IFSw 150 -18 -200 30 6T -5 -12 2N413 2
2N413A PNP 150 -15 -200 85 30T 1 2.5T 33T -5 -12 2N394 2
2N414 PNP IFSw 150 -15 -200 60 7T -5 -12 2N414 2
2N414A PNP 150 -15 -200 85 60T 1 7T 35T -5 -12 2N394, 2N414 2
2N415 PNP 150 -10 -200 85 BOT 1 lOT 30T -5 -12 2N394 2
2N415A PNP 150 -10 -200 85 BOT 1 lOT 39T -5 -12 2N394 2
2N416 PNP 150 -12 -200 85 BOT 1 IOT 20T -5 -12 2N394 2
 MAXIMUM RATINGS ELECTRICAL
PARAMETERS
JEDEC Pcmw BYCE MIN. MIN. MIN. MAX. Closest Dwg.
No. Type Use @25°C BYco* lcma T,oc hfe-hPB* @lcma fhrb me Gedb lco (pa) @Yeo GE No.

2N417 PNP 150 -10 -200 85 140T l 20T 27T -5 -12 2N394 2
2N418 PNP 25W 80 SA 100 40* 4A 400 Kc lSma -60
2N420 PNP 25W 45 SA 100 40* 4A 400 Kc lOm lOma -25
2N420A PNP 25W 70 SA 100 40• 4A 400 Kc 15 ma -60
2N422 PNP 150 -20 -100 85 SOT l .BT 38T -15 -20 2N320, 2Nll75A 4, 2
2N425 PNP 150 -20 -400 85 20• l 2.5 -25 -30 2N394 2
2N426 PNP 150 -18 -400 85 30* l 3 -25 -30 2N395 2
2N427 PNP 150 -15 -400 85 40• l 5 -25 -30 2N396, 2N427 2, 4
2N428 PNP 150 -12 -400 85 60• 1 10 -25 -30 2N397 2
2N438 NPN 100 25 85 20• 50 2.5 10 25 2N634A 2
2N438A NPN 150 25 85 20• so 2.5 10 25 2N634A 2
2N439 NPN 100 20 85 30 so 5 10 25 2N634A 2
2N439A NPN 150 20 85 30• 50 5 10 25 2N634A 2
2N440 NPN 100 15 85 40• so 10 10 25 2N635A 2
2N440A NPN 150 15 85 40• 50 10 10 25 2N635A 2
2N444 NPN 120 15 85 1ST .ST 2T 10 2N634A 2
2N444A NPN-A 150 40 1008 30T .so 25 2N634A 2
2N445 NPN 100 12 85 35T 2T 2T 10 2N634A 2
2N445A NPN-A 150 30 1008 90T• 2.00 25 2N634A 2
2N446 NPN 100 10 85 60T ST 2T 10 2N634A 2
2N446A NPN-A 150 30 1008 !SOT• 5.00 25 2N634A 2
2N447 NPN 100 6 85 125T 9T 2T 10 2N635A 2
2N447A NPN-A 150 30 1008 200T* 9.00 25 2N635A 2
2N448 NPN IF 65 15 20 85 8• l ST 23 5 15 2N448, 2N292 3, 3
2N449 NPN IF 65 15 20 85 34• l BT 24.5 5 15 2N449, 2N293 3, 3
2N450 PNP Sw 150 -12 -125 85 30* -10 5 -6 -12 2N450, 2N394A. 7, 2
2N456 PNP so -40 SA 95 130T* IA -2ma -40
2N457 PNP so -60 SA 95 130T* IA -2ma -60
2N458 PNP so -so SA 95 130T• IA -2ma -80
2N459 PNP so -60 SA 100 20• 2A 5 Kc lOOma -60
2N460 PNP 200 -45• -400 100 .94a 1 1.2T 34T -15 -45 2N524 2
2N461 PNP 200 -45• -400 100 .91a l 1.2T 37T -15 -45 2N461 2
2N462 PNP ISO -40• -200 75 20• -200 .s -35 -35 2N1614, 2N527 1,2
2N463 PNP 37.SW -60 SA 100 20• -2A 4mc -300 -40
2N464 PNP 150 -40 -100 85 14 l .7T 40T -15 -20 2Nl614, 2N527 1, 2
2N465 PNP 150 -30 -100 85 27 l .BT 42T -15 -20 2Nl414, 2Nl924 2,2
2N466 PNP 150 -20 -100 85 56 l IT 44T -15 -20 2N321, 2Nll75 4,2
2N467 PNP 150 -15 -100 85 112 1 1.2T 45T -15 -20 2N508 2
2N469 PNP so 75 10 l IT -so -6
2N470 NPN-GD 200 15 175A 16T 2N335 4
2N471 NPN-GD 200 30 175A 16T 2N335 4
2N471A NPN-GD 200 30 175A 25T 2N335 4
 MAXIMUM RATINGS ELECTRICAL PARAMETERS

JEDEC Pcmw BVcE MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use @25°C BVca• lcma TJ°C hre-hPE* @lcma fhfb me Gedb lco (µa) @Vea GE No.

2N472 NPN-GD 200 45 175A 16T 2N335 4

2N472A PNP-A 200 45 l00S 18T 8.00 so 2N335 4
2N473 NPN-GD 200 15 175A 30T 11.0 2N333 4
2N474 NPN-GD 200 30 175A 30T 11.0 2N333 4
2N474A NPN-GD 200 30 175A SOT 11.0 2N333 4
2N475 NPN-GD 200 45 175A 30T 11.0 2N333 4
2N475A NPN 200 45 200S 35T 8.00 so 2N533 4
2N478 NPN-GD 200 15 175A 60T 11.0 4C30 4
2N479 NPN-GD 200 30 175A 60T 11.0 4C30 4
2N479A NPN-GD 200 30 175A BOT 2N335 4
2N480 NPN-GD 200 45 175A 60T 11.0 .so 2N335 4
2N480A NPN-GD 200 45 175A 60T Jl.0 2N335 4
2N481 PNP 150 -12 -20 85 SOT 1 3T -10 -12 2N395 2
2N482 PNP 150 -12 -20 85 SOT 1 3.ST -10 -12 2N395 2
2N483 PNP 150 -12 -20 85 60T 1 5.ST -10 -12 2N394 2
2N484 PNP 150 -12 -20 85 90T 1 l0T -10 -12 2N394 2
2N485 PNP 150 -12 -10 85 SOT 1 7.ST -10 -12 2N394 2
2N486 PNP 150 -12 -10 85 l00T 1 12T -10 -12 2N394 2
2N489 Si Uni SEE G-E FAMILY OF SPECIFICATIONS SECTION 2N489 5
2N489A Si Uni SEE G-E FAMILY OF SPECIFICATIONS SECTION 2N489A 5
2N4898 Si Uni SEE G-E FAMILY OF SPECIFICATIONS SECTION 2N489B 5
2N490 Si Uni SEE G-E FAMILY OF SPECIFICATIONS SECTION 2N490 5
2N490A Si Uni SEE G-E FAMILY OF SPECIFICATIONS SECTION 2N490A 5
2N490B Si Uni SEE G-E FAMILY OF SPECIFICATIONS SECTION 2N490B 5
2N491 Si Uni SEE G-E FAMILY OF SPECIFICATIONS SECTION 2N491 5
2N491A Si Uni SEE G-E FAMILY OF SPECIFICATIONS SECTION 2N491A 5
2N491B Si Uni SEE G-E FAMILY OF SPECIFICATIONS SECTION 2N491B 5
2N492 Si Uni SEE G-E FAMILY OF SPECIFICATIONS SECTION 2N492 5
2N492A Si Uni SEE G-E FAMILY OF SPECIFICATIONS SECTION 2N492A 5
2N492B Si Uni SEE G-E FAMILY OF SPECIFICATIONS SECTION 2N492B 5
2N493 Si Uni SEE G-E FAMILY OF SPECIFICATIONS SECTION 2N493 5
2N493A Si Uni SEE G-E FAMILY OF SPECIFICATIONS SECTION 2N493A 5
2N493B Si Uni SEE G-E FAMILY OF SPECIFICATIONS SECTION 2N493B 5
2N494 Si Uni SEE G-E FAMILY OF SPECIFICATIONS SECTION 2N494 5
2N494A Si Uni SEE G-E FAMILY OF SPECIFICATIONS SECTION 2N494A 5
2N494B Si Uni SEE G-E FAMILY OF SPECIFICATIONS SECTION 2N4948 5
2N495 PNP 150 -25 -50 140 9 l 8 fo • -.1 -10
2N496 PNP 150 -10 -50 140 9 l 8 fo1 -.1 -10
2N497 NPN Si AF 4W 60 500 200 12• 200 10 30 2N497 2
2N497A NPN Si AF SW 60 500 200 12• 200 10 30 2N497A 2
2N498 NPN Si AF 4W 100 500 200 12• 200 10 30 2N498 2
2N49BA NPN Si AF SW 100 500 200 12• 200 10 30 2N498A 2
 MAXIMUM RATINGS ELECTRICAL PARAMETERS

JEDEC Pcmw BYce MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use @25°C BYca• lcma T1°C hre-hPB* @lcma fhfb me Gedb lco (µa) @Yeo GE No.
2N499 PNP 30 §45°C0 -18 -50 85 6 2 10 100 -30 2N994 8
2NS00 PNP so 4s c -15 85 100 -20
2N501 PNP 2s 45°c -1s• -so 85 20• -10 100 -15 2N960 8
2N501A PNP 25 @45°C -1s• -so 100 20• -10 8 25 -15 2N994 8
2N502 PNP 2s 141°c0 -20 85 9 2 200 8 -100 -20 2N994 8
2NS02A PNP 2s 4s c -30* 100 9 2 100 -30
2N503 PNP 25 @41°C -20 -so as 9 2 100 11 -100 -20 2N994 8
2NS05 PNP 125 40 250 85J 40T 8.00 2N396 2
2NS06 PNP so -40* -100 85 25 -10 .6 -15 -30 2N320, 2N413 4, 2
2NS07 NPN so 40 100 85 25 10 .6 15 30
2N508 PNP AF Out 140 -16 -100 85 125T* -20 3.ST -16 -16 2NS08 2
2NS09 PNP 225 -30* -40 100 .96a 10 750T -5 -20
2N514 PNP sow -40 -25A 95 12* -25 -2.0 -20
2NS14A PNP sow -60 -2SA 95 12* -25 2.0 -30
2NSI4B PNP sow -80 -25A 95 12• -25 7.0T -2.0 -40
2N515 NPN so 18 10 75 4 I 2 23 so 18 2N293 3
2NSI6 NPN so 18 10 75 4 I 2 25 so 18 2N293 3
2N517 NPN so 18 10 75 4 l 2 27 so 18 2Nll21 3
2N519 PNP 100 -IS 85 15 l .s -2 -5 2N394 2
2N519A NPN-A ISO 25 1008 35T* .so 25 2N394 2
2NS20 PNP 100 -12 85 20 I 3 -2 -5 2N394 2
2NS20A PNP-A 150 25 1008 l00T* 3.00 25 2N394 2
2NS21 PNP 100 -10 85 35 l 8 -2 -5 2N397 2
2N521A PNP-A 150 25 1008 IS0T* 8.00 25 2N397 2
2N522 PNP 100 -8 85 60 l 15 -2 -5
2N523 PNP 100 -6 85 80 l 21 -2 -5
2N524 PNP AF 225 -30 -500 100 16 -1· .8 -10 -30 2N524 2
2N525 PNP AF 225 -30 -500 100 30 -1 l -10 -30 2N525 2
2N526 PNP AF 225 -30 -500 100 44 -1 1.3 -10 -30 2N526 2
2N527 PNP AF 225 -30 -500 100 60 -1 1.5 -10 -30 2N527 2
2N528 PNP 2.SW -40 100 20* -0.5 -15 -30
2N529 PNP-NPN 100 15 85 15 l 2.ST 5 5
2N530 PNP-NPN 100 15 85 20 I 3T 5 5 2N394 2
2NS31 PNP-NPN 100 15 85 25 l 3.ST 5 5 2N395 2
2N532 PNP-NPN 100 15 85 30 l 4T 5 5 2N395 2
2N533 PNP-NPN 100 15 85 35 I 4.ST 5 5
2N534 PNP 2S@S0°C -so -25 65 35 -1 -15 -50 2Nl057, 2Nl924 1, 2
2N535 PNP so -20 -20 85 35 -1 2T -IO -12 2Nl415, 2Nll75A 2, 2
2N535A PNP so -20 -20 85 35 -1 2T -10 -12 2Nl415, 2Nll75A 2, 2
2N5358 PNP so -20 -20 85 35 -1 2T -10 -12 2NS0S, 2Nll75A 2,2
2N536 PNP so -20 -30 85 100* -30 l -10 -12 2NS08 2
2N53S PNP I0W @70°C -so• 95 40 2A BT Kc -20mo -80
 MAXIMUM RATINGS ELECTRICALPARAMETERS

JEDEC Pcmw BVcs MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use @25°C BVce• lcma T,oc hfc-hvs• @lcma fhfb me Gcdb lco (µa) ®Vee GE No.
2N538A PNP lOW @70°C -BO• 95 40 2A BT Kc -20 ma -80
2N539 PNP IOW i7o°C -so• 95 27 2A 7T Kc -20ma -80
2N539A PNP lOW 70°C -80 95 27 2A 7T Kc -20ma -80
2N540 PNP IOW i7o°C -80 95 18 2A 6T Kc -20 -80
2N540A PNP IOW 70°C -80 95 18 2A 6T Kc -20 -80
2N544 PNP 80 -24• -10 85 60T 1 30T 30.4 -16 -12
2N545 NPN-GD 5000 60 175A 2ST• 4.00 2N497A 2
2N546 NPN-GD 5000 30 175A 25T* 4.00 2N497A 2
2N547 NPN-GD 5000 60 175A 35T• 4.00 2N656A 2
2N548 NPN-GD 5000 30 175A 35T* 4.00 2N656A 2
2N549 NPN-GD 5000 60 175A 35T* 4.00 2N656A 2
2N55o NPN-GD 5000 30 175A 35T* 4.00 2N656A 2
2N551 NPN-GD 5000 60 175A 30T* 4.00 2N656A 2
2N552 NPN-GD 5000 30 175A 30T* 4.00 2N656A 2
2N553 PNP 12W @71°C -80* -4A 95 40 -.SA 20 Kc -2ma -60
2N554 PNP lOW @80°C -40* -3A 90 30T* -.SA BT Kc 20 -SOT -2
2N555 PNP lOW @80°C -30 -3A 90 20 -.SA 5 Kc 34T -7ma -30
2N556 NPN 100 25* 200 85 35* 1 2N634A 2
2N557 NPN 100 20• 200 85 20• l 2N634A 2
2N558 NPN 100 15* 200 75 60* 1 2N635A 2
2N559 PNP 150 -15 -50 100 25* 10 -50 -5@ 65°C 2N705 8
2N560 NPN .50 20* -100 .10 -20 2Nl613 4
2N561 PNP sow -50 -SA 100 65T -lA .5 24.6 -500 -30
2N563 PNP 150 -25 -300 85 10• 1 .BT -5 -10 2N44 1
2N564 PNP 120 -25 -300 85 10* 1 .BT -5 -10 2N524 2
2N565 PNP 150 -25 -300 85 30* 1 IT -5 -10 2N43 l
2N566 PNP 120 -25 -300 85 30* l IT -5 -10 2N525 2
2N567 PNP 150 -25 -300 85 so• 1 I.ST -5 -10 2N43, 2N526 1, 2
2N568 PNP 120 -25 -300 85 so• 1 I.ST -5 -10 2N526 2
2N569 PNP 150 -20 -300 85 70* 1 2T -5 -10 2N241A. 2N1175 1, 2
2N570 PNP 120 -20 -300 85 70* 1 2T -5 -10 2N527, 2Nl415 1, 2
2N571 PNP 150 -10 -300 85 100• 1 3T -5 -10 2N508 2
2N572 PNP 120 -10 -300 85 100• 1 3T -5 -10 2N508 2
2N574 PNP 25W @75°C -60* -ISA 95 10• -lOA 6T Kc -7 ma -60
2N574A PNP 25W @75°C -80* -ISA 95 10• -lOA 6T Kc -20 ma -80
2N575 PNP 25W @75°C -60* -ISA 95 19* -lOA ST Kc -7ma -60
2N575A PNP 25W @75°C -80* -15A 95 19* -IOA ST Kc -20 ma -80
2N576 NPN 200 20 400 100 SOT* 30 ST 20 20 2N635A 2
2N576A NPN 200 20 400 100 20• 400 ST 40 40 2N63SA 2
2N578 PNP 120 -14 -400 85 10• 1 3 -5 -12 2N394 2
2N579 PNP 120 -14 -400 85 20• 1 5 -s -12 2N396 2
2NS80 PNP 120 -14 -400 85 30* 1 10 -5 -12 2N397 2
 MAXIMUM RATINGS ELEtTRICALPARAMETERS
JEDEC Pcmw BVcs MIN. MIN. MIN. MAX. Closest Dwg.
No. Type Use @25°C BVco* lcma y,oc hre-hPB* ®lcma fhfb me Gedb lco {µa) @Vee GE No.
2N581 PNP 80 -15 -100 85 20• -20 4 -6 -6 2N394 2
2N582 PNP 120 -14 -100 85 40* -20 14 -5 -12 2N397 2
2N583 PNP 150 -15 -200 85 20• -20 4 -6 -6 2N394 2
2N584 PNP 120 -14 -100 85 40* -20 14 -5 -12 2N397 2
2N585 NPN 120 24 200 85 20• 20 3 8 12 2N634, 2Nl302 2, 2
2N586 PNP 250 -45• -250 85 35T* -250 -16 -45 2N525, 2Nl925 2,2
2N587 NPN 150 20 200 20• 200 50 40 2N634A 2
2N588 PNP 30@45°C -15 -so 85 15 -15 2N7UA 8
2N591 PNP 50 -32 -20 100 70T 2 .7T 41T -6.5 -10 2N324. 2N526 4,2
2N592 PNP 125 -20 85 20• 1 .4T -5 -5 2Nl414 2
2N593 PNP 125 -30 85 30* .5 .6T -5 -5 2N1414 2
2N594 NPN 100 20 85 20• 1 1.5 5 5
2N595 NPN 100 15 85 35• 1 3 5 5
2N596 NPN 100 10 85 so• 1 5 5 5 2N634 2
2N597 PNP 250 -40 -400 100 40* -100 3 -25 -45 2N526, 2N527 2, 2
2N598 PNP 250 -20 -400 100 so• -100 5 -25 -30
2N599 PNP 250 -20 -400 100 100• -100 12 25 -30 2N508 2
2N600 PNP 750 -20 -400 100 so• -100 5 -25 -30
2N601 PNP 0.75 -20 -400 100 2.5 3 12 25 -30
2N602 PNP 120 -20 85 20• .5 -8 -10 2N395, 2N711 B 2, 8
2N603 PNP 120 -2C1 85 30* .5 -8 -10 2N396, 2N711B 2, 8
2N604 PNP 120 -20 85 40* .5 -8 -10 2N397, 2N711B 2, 8
2N605 PNP 120 -15 85 40T -1 20 -10 -12 2N394 2
2N606 PNP 120 -15 85 60T -1 25 -10 -12 2N395 2
2N607 PNP 120 -15 85 BOT -1 30 -10 -12 2N396 2
2N608 PNP 120 -15 85 120T -1 35 -10 -12 2N396 2
2N609 PNP 180 -20 -200 85 90T* 100 30T -25 -20 2N321, 2N324 4,4
2N6IO PNP 180 -20 -200 85 65T* 100 28T -25 -20 2N320, 2N323 4, 4
2N611 PNP 180 -20 -200 85 45T* 100 26T -25 -20 2N320, 2N322 4, 4
2N612 PNJ> 180 -20 -150 85 .96aT l .6T 37 -25 -20 2N319, 2Nl098 4,2
2N613 PNP 180 -20 -200 85 .97aT I .SST 32 -25 -20 2N320, 2Nl097 4,2
2N614 PNP 125 -15 -150 85 4.ST .5 3T 26T -6 -20 2N395 2
2N615 PNP 125 -15 -150 85 7.5T .5 ST 34T -6 -20 2N395 2
2N616 PNP 125 -12 -150 85 25T .5 9T 20T -6 -15 2N394 2
2N617 PNP 125 -12 -150 85 1ST .5 7.5T 30T 6 -15 2N394 2
2N618 PNP 45W -so• -3A 90 60• -IA 5 Kc -3ma -60
2N622 NPN 400 so• so 160 2ST* .5 .3 34T .1 30
2N624 PNP 100 -20 -10 100 20 2 12.5 20T -30 -30
2N625 NPN 2.SW 30 100 30* so 100 -40
2N631 PNP 170 -20 -so 85 lSOT 10 1.2T 35T -25 -20 2N508 2
2N632 PNP 150 -24 -50 85 IOOT 10 IT 25T -25 -20 2N324, 2N1175 4, 2
2N633 PNP 150 -30 -50 85 60T IO .BT 25T -25 -20 2N323, 2Nl415 4, 2
 MAXIMUM RATINGS ELECTRICALPARAMETERS
JEDEC Pcmw BVce MIN. MIN. MIN. MAX. Closest Dwg.
No. Type Use @25°C BVco• lcma T.10C hCe-hPE* @lcma fhrb me Gedb lco (µa) ®Vee GE No.
2N634 NPN Sw 150 20 300 85 15* 200 5 5 5 2N634A 2
2N634A NPN Sw 150 20 300 85 40• 10 5 6 25 2N634A 2
2N635 NPN Sw 150 20 300 85 25• 200 10 5 5 2N635A 2
2N635A NPN Sw 150 20 300 85 so• 10 10 6 25 2N635A 2
2N636 NPN Sw ISO 20 300 85 35• 200 15 5 5 2N636A 2
2N636A NPN Sw 150 15 300 85 100• 10 15 6 25 2N636A 2
2N637 PNP 25W -40 -SA 100 so• -3A l ma -25
2N637A PNP 25W -70 -SA 100 so• -3A Sma -60
2N637B PNP 25W -80 -SA 100 30* -3A Sma -60
2N638 PNP 25W -40 -SA 100 20• -3A 1 mn -25
2N638A PNP 25W -70 -SA 100 20• -3A Sma -60
2N638B PNP 25W -80 -SA 100 20* -3A Sma -60
2N639 PNP 25W -40 -SA 100 15• -3A 1 ma -25
2N639A PNP 25W -70 -SA 100 15* -3A Sma -60
2N639B PNP 25W -80 -SA 100 15• -3A Sma -60
2N640 PNP 80 -34* -10 85 .984aT -1 42T 28T -5 -12 2N711B 8
2N641 PNP 80 -34* -10 85 .984aT -1 42T 28T -7 -12 2N711B 8
2N642 PNP 80 -34* -10 85 .984a:T -1 42T 28T -7 -12 2N711B 8
2N643 PNP 120 -29 -100 85 20• -5 20 -10 -7
2N644 PNP 120 -29 -100 85 20• -5 40 -10 -7
2N645 PNP 120 -29 -100 85 20* -5 60 -10 -7
2N647 NPN 100 25 so 85 70T* -so 54T 14 25 2N388 2
2N649 NPN 100 18 so 85 65T* -so 54T 14 12 2N388 2
2N650 PNP-A 200 45 250 lOOJ 40T 2.00 42 15 2Nl924 2
2N6SOA PNP-A 200 45 500 lOOC .75 so 2Nl924 2
2N651 PNP-A 200 45 250 lOOJ 75T 2.50 44 15 2Nl925 2
2N652 PNP-A 200 45 250 lOOJ 160T 3.00 46 15 2Nl925 2
2N652A PNP-A 200 45 500 lOOC 160T 1.25 50 2N1926 2
2N653 PNP-A 200 30 250 lOoJ 40T 2.00 42 15 2N1926 2
2N654 PNP-A 200 30 250 lOoJ 75T 2.50 44 15 2N1414 2
2N655 PNP-A 200 30 250 lOoJ 160T 3.50 46 15 2N1175 2
2N656 NPN Si AF 4W 60 500 200 so• 200 10 30 2N656, 2N508 2, 2
2N656A NPN Si AF SW 60 500 200 so• 200 10 30 2N656A 2
2N657 NPN Si AF 4W 100 500 200 30* 200 10 30 2N657. 2
2N657A NPN Si AF SW 100 500 200 30• 200 10 30 2N657A 2
2N658 PNP 175 -16 -lA 85 25* -1 2.5 -6 -12 2N394 2
2N659 PNP 175 -14 -lA 85 40* -1 5.0 -25 -25 2N396 2
2N660 PNP 175 -11 -IA 85 60* -1 10 -25 -25 2N397 2
2N661 PNP 175 -9 -IA 85 so• -1 15 -25 -25
2N662 PNP 175 -11 -IA 85 30* -1 4 -25 -25 2N396 2
2N665
2N679
PNP 35W -so• SA (IE) 95 40* -.SA 20 Kc -2ma -30@71°C
NPN 150 20 85 20• 30 2 25 25
 MAXIMUM RATINGS ELECTRICAL
PARAMETERS
JEDEC Pcmw BVcs MIN. MIN. MIN. MAX. Closest Dwg.
No. Type Use @25°C BVca• lcma T,oc hfe-hvs• @lcma fhfb me Gedb lco (pa) @Yeo GE No.
2N680 NPN 150 20 50 85J 35T 14 2N1413 2
2N695 PNP-M 75 15 50 lOOJ 40T 350 2N705 8
2N696 NPN-PL Sw 600 60• 175J 20• 1.0 30 2N696 4
2N696A NPN-PL Sw 800 60• 200J 45T 150 .10 2N2194A 4
2N697 NPN-PL Sw 600 60• 175J 40• 1.0 30 2N697 4
2N697A NPN-M 800 60• 200 70T 150 .10 2N2193A 4
2N698 NPN-PL Sw 800 120• 200J 40T• 70.0 .005 75 2N698 4
2N699 NPN-PL Sw 600 120• 175J 40• 2.0 60 2N699 4
2N699A NPN-M 800 120• 200 70T 180 .IO 2Nl893 4
2N699B NPN-PL 870 120• 200J BOT 120 .01 2Nl893 4
2N700 PNP-M 75 25 so lOOJ IOT 500 23 2N994 8
2N702 NPN 600 25 so 175 20• 10 0.5 10 2N706 8
2N703 NPN 600 25 so 175 10• 10 0.5 10 2N753 8
2N705 PNP Sw 300 IS• 50 100 2s• 2N705 8
2N705A PNP-A 175 40 200 85J 75T 2.00 44 2N705A 8
2N706 NPN-PEP Sw 300 25• 200 175J 20 0.5 2N706 8
2N706A NPN-PEP Sw 300 25* 175J 40T 750 0.5 2N706A 8
2N706B NPN-M Sw 300 25• 175J 40T• 400 10 2N914 8
2N707 NPN IW 28 9• 10 3.5 15 2N915 8
2N707A NPN-M 300 70 200 175 30T• 500 5.0 2N915 8
2N708 NPN-PEP Sw 360 40 200J SOT• 500 .025 2N708 8
2N710 PNP-M Sw 300 15 50 100 2s• 2N710 8
2N711 PNP-M Sw 150 12 so lOOJ 30T• 360 22 3.0 2N711 8
2N711A PNP-M Sw 150 IS• 100 1008 2s• 1.5 5 2N711A 8
2N711B PNP-M Sw 150 18• 100 1008 30• 1.5 10 2N711B 8
2N715 NPN-M 500 so 175J 30T• 150 .01 2N915 8
2N716 NPN-M 500 70 175J 30T• 150 10 2N915 8
2N717 NPN-PL Sw 400 60 175J 40T• 150 1.0 2N717 8
2N718 NPN-PL Sw 400 60 l75J 7ST• 150 1.0 2N718 8
2N718A NPN-PL Sw 500 75 200J 70T• 160 .01 2N718A 8
2N719 NPN-PL Sw 400 120 175J 30T• 180 2.0 2N719 8
2N719A NPN-PL Sw 300 120 200J 30T• 100 .01 2N719A 8
2N720 NPN-PL Sw 400 120 175J 6ST• 180 2.0 2N720 8
2N721A NPN-PL Sw 500 120 200J 6ST• 110 .01 2N720A 8
2N725 NPN-M 150 15 50 20T• 2N725 8
2N728 NPN-D 500 30 175 40T• 150 5.0 2N706 8
2N729 NPN-D 500 15 3.0 175 40T• 150 5.0 2N717 8
2N735 NPN-D 1000 80 so 175 40T 40.0 1.0 2N759 8
2N736 NPN-D 1000 80 so 175 so.o 1.0 2N760 8
2N741 PNP-M 150 15 100 lOOJ 2ST• 360 22 2N960 8
2N741A PNP-M 150 20 100 100 2ST• 360 22 3.0 2N960 8
2N743 NPN-EM 300 25 200 3008 40T• 2N914 8
 ' '

MAXIMUM RATINGS ELECTRICAL PARAMETERS

JEDEC Pcmw BVcs MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use @25°C BVce• lcma T.10C hre-hvE• @lcma fhfb me Gedb lco (µa) @Vee GE No.
2N744 NPN-EM 300 25 200 3008 BOT• 2N914 8
2N753 NPN-PEP Sw 300 25 175J BOT 750 2N753 8
2N754 NPN-M 300 60 so 175J SOT 45.0 1.0 2N915 8
2N758 NPN-M 500 45 100 200A SOT 50.0 2N759 8
2N759 NPN-PL AF 500 45 100 200A 65T 50.0 2N759 8
2N760 NPN-PL AF 500 45 100 200A 150T 50.0 2N760 8
2N761 NPN-M 500 45 100 200A 35T* 50.0 2N759 8
2N762 NPN-M 500 45 100 200A 70T* 50.0 2N759 8
2N768 PNP-MD 35 12 100 100 40T* 175 25 2N966 8
2N769 PNP-M 35 12 100 lOOJ SST* 900 3.0 2N961 8
2N779 PNP-MD 60 15 so 100 90T* 480 25 2N964 B
2N779A PNP-MD 60 15 100 100 60T* 450 3.0 2N994 8
2N7BO NPN-M 300 45 175J 20T 30.0 2N760 B
2N7Bl PNP-EM 150 15 200 100 25T 3.0 2N7Bl B
2N782 PNP-EM 150 12 200 100 20T 3.0 2N7B2 B
2N783 NPN-EM 300 40 200 175 40T .25 2N914 8
2N784 NPN-EM 300 30 200 175 25T .25 2N914 8
2N796 PNP-M 150 13 100 BSA 75T* 80.0 3.0 2N634A 2
2N815 NPN-FA 75 25 200 BOT* B.00 14 10 2N635A 2
2NB16 NPN-FA 75 25 200 lOOJ BOT* 8.00 14 10 2N635A 2
2N818 NPN-FA 75 30 400 85J 25T 2.50 10 2Nl302 2
2N819 NPN-FA 75 30 400 85J 30T 5.00 10 2N634A 2
2N820 NPN-FA 75 30 400 BSJ 30T 5.00 10 2N634A 2
2N821 NPN-FA 75 30 400 85J 70T* 10.0 10 2N635A 2
2NB22 NPN 75 30 400 85J 70T* 10.0 10 2N635A 2
2N823 NPN 75 25 400 85J 40T 12.0 5.0 2N635A 2
2N824 NPN 75 25 400 85J 40T 12.0 5.0 2N635A 2
2N828 PNP-D 150 15 200 150S 40T* 400 3.0 2NB28 B
2N834 NPN-PEP Sw 300 40 200 175J 40T* 500 .50 2N834 8
2N835 NPN-M 300 25 200 175 40T• 450 .50 2N834 B
2N839 NPN-M 300 45 so 175J 35T 30.0 1.0 2N759 B
2N840 NPN-M 300 45 so 175 70T 30.0 1.0 2N759 8
2N841 NPN-M 300 45 50 175 140T 40.0 1.0 2N760 8
2N844 NPN-M 300 60 50 175 BOT* 50.0 14 1.0 2N718A 8
2N845 NPN-M 300 100 50 175 BOT* 50.0 14 1.0 2N720A B
2N846 PNP-MD 60 15 50 100S 35T* 450 25 2N960 8
2N849 NPN-M 450 25 175J 40T* 10 2N706 B
2NB50 NPN-M 450 25 175J BOT* 10 2N753 B
2N870 NPN-PL 500 100 200J 70T* 110 .01
2NB71 NPN 500 100 200J 120T• 130 .01 2NB71 B
2N909 NPN-D 400 60 175J SST 160 1.0 2N956 B
2N910 NPN-PL 500 100 200J lOOT 60.0 .025
 MAXIMUM RATINGS ELECTRICAL
PARAMETERS
JEDEC Pcmw BYce MIN. MIN. MIN. MAX. Clo101t Dwg.
No. Type Use @25°C BYca• lcma T,oc hre-hvE• @lcma fhrb me Gedb lco (µa) @Yea GE No.
2N911 NPN-PL 500 100 200J SOT 50.0 .025
2N912 NPN-PL 500 100 200J 30T 40.0 .025
2N914 NPN-PEP Sw 360 40 200J 30T 400 .025 2N914 8
2N915 NPN-PL AF 360 70 200J 40T 400 .01 2N915 8
2N916 NPN-PL AF 360 45 200J SOT 500 .01 2N916 8
2N929 NPN-PL 300 45 175J 40 30.0 .01 2N915 8
2N930 NPN-PL 300 45 175J 100 30.0 .01 2N915 8
2N956 NPN-PL 500 75 200J lOOT 200 .01 2N956 8
2N960 PNP Sw 150 15 100 20T 460 2N960 8
2N961 PNP-EM Sw 150 12 100 20T 460 2N961 8
2N962 PNP-EM Sw 150 12 100 20T 460 2N962 8
2N964 PNP-EM Sw 150 15 100 40T• 460 2N964 8
2N965 PNP-EM Sw 150 12 100 40T• 460 2N965 8
2N966 PNP-EM Sw 150 12 100 40T• 460 2N966 8
2N968 PNP 150 15 lOOJ 20T• 320 3.0
2N969 PNP 150 12 100 20T• 320 2N961 8
2N970 PNP 150 12 100 20T• 320 3.0 2N962 8
2N971 PNP 150 7.0 100 20T• 320 10 2N963 8
2N972 PNP 150 15 100 40T• 320 3.0 2N964 8
2N973 PNP 150 12 100 40T• 320 3.0 2N965 8
2N974 PNP 150 12 100 40T• 320 3.0 2N966 8
2N975 PNP 150 7.0 100 40T• 320 10
2N994 PNP Sw 200 15 150 150S 75• 3.0 2N994 8
2Nl000 NPN-A 150 40 100S 3ST• 7.00 15 2N634A 2
2Nl008 PNP-A 167 20 300 75J 90T 1.00 2Nl415 2
2NlOOBA PNP 167 40 300 BSJ 90T 1.00 2N526 2
2Nl008B PNP 167 60 300 85J 90T 1.00 2Nl925 2
2Nl009 PNP-A 150 25 20 85A 40T .so 800 2N395 2
2Nl010 NPN 20 10 2 85 35T -.3 2T 10 10 2Nl694 2
2Nl012 NPN-A 150 40 1008 SOT 3.00 25 2N635A 2
2Nl015 NPN 150@45°C 30 75A 150 10• 2A 20T Kc 20ma 30
2Nl015A NPN 150@45°C 60 75A 150 10• 2A 20T Kc 20ma 60
2Nl015B
2Nl015C
2Nl015D
2Nl015E
NPN
NPN
NPN
NPN
1so
1so
f
150 @45°C
"5°C
4s 0 c
150 4s 0 c
100
150
200
250
7.SA
7.SA
7.SA
7.SA
150
150
150
150
10•
10•
10•
10•
2A
2A
2A
2A
20T
20T
20T
20T
Kc
Kc
Kc
Kc
20ma
20ma
20ma
20ma
100
150
200
250
2Nl015F NPN 0
1so §"s 0 c 300 7.SA 150 10• 2A 20T Kc 20ma 300
2Nl016 NPN 1so 4s c 30 7.SA 150 10• SA 20T Kc 20ma 30
2Nl016A NPN 1so 4s 0 c 60 7.SA 150 10• SA 20T Kc 20ma 60
2Nl016B NPN 150@45°C 100 7.5A 150 10• SA 20T Kc 20ma 100
2Nl016C NPN 150 @45°C 150 7.SA 150 10• SA 20T Kc 20ma 150
2Nl016D NPN 150@45°C 200 7.SA 150 10• SA 20T Kc 20ma 200
 MAXIMUM RATINGS ELECTRICAL PARAMETERS

JEDEC Pcmw BVcE MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use @25°C BVce• lcma T.ioc hre-hvE• @lcma fhJ'b me Gedb lco (µa) @Vee GE No.

2Nl016E NPN 150 i45°C0 250 7.5A 150 10* SA 20T Kc 20ma 250
2Nl016F NPN 1so 4s c 300 7.SA 150 10* 5A 20T Kc 20ma 300
2Nl017 PNP 150 -10 -400 85 70* 1 15 -25 -30
2Nl021 PNP sow -100 -5 95 70T* -IA -2 mil -100
2Nl022 PNP sow -120 -5 95 70T* -IA -2 mil -120
2Nl038 PNP 20W -40 -3A 95 35* -IA -125 .5
2Nl039 PNP 20W -60 -3A 95 35* -IA -125 .5
2Nl040 PNP 20W -80 -3A 95 35* -IA -125 .5
2Nl041 PNP 20W -100 -3A 95 35* -IA -125 .5
2Nl046 PNP ISW -8 -3A 65 70* -0.SA -1 ma -40
2Nl047 NPN 40W i2s°C 80* 500 200 12* 500 15 30 71.;} 12
2Nl048 NPN 40W 25°C 120* 500 200 12* 500 15 30 7E.1 12
2Nl049 NPN 40W @25°C 80* 500 200 30* 500 15 30 7E2 12
2Nl050 NPN 40W @25°C 120* 500 200 30* 500 15 30 2N2204 12
2Nl056 PNP Obsolete 240 -50 -300 100 18* -20 .5 -25 -70 2Nl614, 2Nl924 1. 2
2Nl057 PNP Sw 240 -45 -300 100 34* -20 .5 -16 -45 2Nl057, 2Nl924 1, 2
2Nl058 NPN so 20 so 75 10 1 4 22.5 50 18 2N292 3
2Nl059 NPN 180 15 100 75 50* 35 10 Kc 25 50 40 2N635A 2
2N1067 NPN SW 30 .SA 175 15* 200 .75 500 60
2N1068 NPN IOW 30 I.SA 175 15* 750 .75 500 60
2Nl069 NPN sow 45 4A 175 10* 1.5A .5 1 ma 60
2Nl070 NPN sow 45 4A 175 10* I.SA .5 1 ma 60
2Nl086 NPN Osc 65 9 20 85 17* 1 BT 24T 3 5 2NI086 3
2Nl086A NPN Osc 65 9 20 85 17* 1 BT 24T 3 5 2Nl086A 3
2Nl087 NPN Osc 65 9 20 85 17* 1 BT 26T 3 5 2Nl087 3
2Nl090 NPN 120 15 400 85 50* 20 5 8 12 2N635A 2
2Nl091 NPN 120 12 400 85 40* 20 10 8 12 2N635A 2
2Nl092 NPN 2W 30 500 175 15* 200 .75 500 60
2Nl093 PNP-A 150 30 250 85J 125T 8.00 6.0 2Nl307 2
2Nl097 PNP AF Out. 140 -16 -100 85 SST 1 -16 -16 2Nl097 2
2Nl098 PNP AF Out. 140 -16 -100 85 45T 1 -16 -16 2Nl098 2
2Nl099 PNP 30W 80* 95 35* SA 10 Kc Bma -80
2N1100 PNP 30W 100* 95 25* SA 10 Kc 8ma -100
2N1101 NPN 180 15 100 75 25* 35 10 Kc 50 20 2N635A 2
2N1102 NPN 180 25 100 75 25• 35 10 Kc 50 40 2N635A 2
2N1107 PNP 30 16* 5 85 33 -0.5 40 -10 -12
2Nl108 PNP 30 16* 5 85 30 -0.5 35 -10 -12
2Nllo9 PNP 30 16* 5 85 15 -0.5 35 -10 -12
2Nll10 PNP 30 16* 5 85 26 -0.5 35 -10 -12
2Nllll PNP 30 20* 5 85 22 -o.s 35 -10 -12
2Nlll4 NPN-A 150 25 200 lOOJ llOT* 10.0 30 2N635A 2
2Nlll5 PNP Sw 150 -20 -125 85 35 -60 5 -6 -20 2Nll15, 2N396A 7,2
 MAXIMUM RATINGS ELECTRICAL PARAMETERS

JEDEC Pcmw BVce: MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use @25°C BVco* lcma T.ioc hre-hFE* @lcma fhfb me Gedb lco (µa) @Vee GE No.
2NU15A PNP Sw 150 -35 -125 85 35 -60 5 -6 -20 2Nlll5A, 2N656A 7,2
2Nlll6 NPN-GD 5000 60 175A 70T* 4.00 2N656A 2
2Nlll7 NPN-GD 5000 60 175A 70T* 4.00 2N656A 2
2NU18 PNP 150 -25 -50 140 9 1.0 -25
2Nlll8A PNP 150 -25 -so 140 15 1 0.1 -10
2N1119 PNP 150 -10 -so 140 6• -15 0.1 -10
2Nll21 NPN IF 65 15 20 85 34* I 8 Kc 5 15 2Nll21 3
2Nll22 PNP -25145°C -10 -50 85 35 1.0 5 -5 2N994 8
2Nll22A PNP -25 45°C -50 85 35 1.0 5 -5 2N994 8
2Nll23 PNP 750 -40 -400 100 40* -100 3 -25 -45
2Nll28 PNP-A 150 25 250 85J 120T 1.25 20 2N324 4
2Nll29 PNP-A 150 25 250 85J 165T* .75 25 2N508 2
2Nll30 PNP-A 150 30 250 85J llOT* .75 25 2Nl926 2
2Nll41 PNP 750 100 100 12 -10 750T -5 -15
2Nll42 PNP 750 100 100 10 -10 600T -5 -15
2Nll43 PNP 750 100 100 8 -10 480T -5 -15
2Nll44 PNP AF Out 140 -16 -100 85 SST I -16 -16 2Nll44, 2Nl097 2, 2
2Nll45 PNP AF Out. 140 -16 -100 85 45T 1 -16 -16 2Nll45, 2Nl098 2,2
2Nll49 NPN 150 45* 25 175 -0.9 -1 4T 35T 2 30 2Nl276 4
2Nll50 NPN 150 45* 25 175 -0.948 -1 ST 39T 2 30 2Nl277 4
2NU51 NPN 150 45* 25 175 -0.948 -1 8T 39T 2 30 2Nl278 4
2Nll52 NPN 150 45* 25 175 -0.9735 -1 6T 42T 2 30 2N1278 4
2Nll53 NPN 150 45* 25 175 -0.987 -1 7T 42.5T 2 30 2Nl279 4
2N1154 NPN 750 so• 60 150 -0.9 -5 30 5 50 2N333 4
2Nl155 NPN 750 so• 50 150 -0.9 -5 30 6 80 2N333 4
2NU56 NPN 750 120• 40 150 -0.9 -5 30 8 120
2Nll57 PNP -60* 95 38* -IOA -7.0 ma -60
2N1157A PNP -so• 95 38* -lOA -20ma -80
2NU59 PNP 20W@71°C 80* -65 -65 30* 3A lOT Kc 8ma -80
2Nll60 PNP 20W @71°C so• -65 20• SA lOT Kc 8mll -80
2Nll68 PNP 45W -so• SA (le:) 95 110T IA lOT Kc 37T -8ma -50
2Nl171 PNP -12 400 85 30* I 10 5 -12 2N397 2
2Nl172 PNP 40* -65 30 100 34T 0.2ma -40
2Nl175 PNP-A 200 35 200 85J 90T* 4.20 12 2Nll75 2
2Nl175A PNP-A 200 35 200 85J 90T* 4.20 12 2Nll75A 2
2Nll77 PNP 80 -30* -10 71 100 140 -12 -12
2Nl178 PNP 80 -so• -10 71 40 140 -12 -12
2N1179 PNP 80 -30* -10 71 80 140 -12 -12
2Nl180 PNP 80 -30* -10 71 80 100 -12 -12
2N1183 PNP lW -20 -3.0 100 20• -400 500 Kc -250 -250 -45
2Nll83A PNP IW -30 -3.0 100 20* -400 500 Kc -250 -80
2N11838 PNP lW -40 -3.0 100 20• -400 500 Kc -250 -80
 MAXIMUM RATINGS ELECTRICAL PARAMETERS

JEDEC Pcmw BVce MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use @25°C BVca• lcma T,oc hre-hFE. @lcma fhfb me Gedb lco (µa) @Vee GE No.
2Nll84 PNP IW -20 -3.0 100 40• -400 500 Kc -250 -45
2Nll84A PNP IW -30 -3.0 100 40* -400 500 Kc -250 -80
2Nll848 PNP IW -40 -3.0 100 40* -400 500 Kc -250 -80
2NU86 PNP 200 60 lOOJ SOT I.SO 2Nl924 2
2Nll87 PNP 200 60 lOOJ 85T 2.00 2Nl926 2
2Nll88 PNP 200 60 lOOJ 155T 2.50 2Nl926 2
2Nll91 PNP-A 175 40 200 85J 40T 1.50 42 2Nl414 2
2Nll92 PNP-A 175 40 200 85J 75T 2.00 44 2Nll75 2
2Nll93 PNP-A 175 40 200 85J 160T 2.50 46 2NS08 2
2Nll98 NPN Sw 65 25 75 85 17* 8 5 1.5 15 2Nll98, 2Nl67 3, 3
2Nll99 NPN 100 20 100 150 12* 20 0.7 -10
2Nl202 PNP -60 95 40* -0.SA -2.0 ma -80
2Nl203 PNP -70 95 25* -2A -2.0ma -120
2Nl213 PNP 75 -25 -100 71 -5 -12
2Nl214 PNP 75 -25 -100 7) -5 -12
2Nl215 PNP 75 -25 -100 71 -5 -12
2Nl216 PNP 75 -25 -100 71 -5 -12
2Nl217 NPN 75 20 25 40* .5 6.0 29 15 2Nl217 3
2Nl224 PNP 120 -40 -10 100 20 -1.5 30 15 -12 -12
2Nl225 PNP 120 -40 -10 100 20 -1.5 100 15 -12 -12
2Nl226 PNP 120 -60 -10 100 20 -1.5 30 15 -12 -12
2Nl228 PNP 400 -15 160 14 1.2T -0.l -12
2Nl229 PNP 400 -15 160 28 1.2T -0.1 -12
2Nl230 PNP 400 -35 160 14 1.2T -0.1 -30
2Nl231 PNP 400 -35 160 28 1.2T -0.1 -30
2Nl232 PNP 400 -60 160 14 I.OT -0.1 -so
2Nl233 PNP 400 -60 160 28 I.OT -0.1 -so
2Nl234 PNP 400 -110 160 14 8T -0.1 -90
2Nl238 PNP lW free air -15 160 14 1.2T -0.1 -12
2Nl239 PNP lW rree air -15 160 28 1.2T -0.1 -12
2Nl240 PNP lW rree air -35 160 14 1.2T -0.1 -30
2Nl241 PNP IW rree air -35 160 28 1.2T -0.1 -30
2Nl242 PNP lW rree air -60 160 14 I.OT -0.1 -so
2Nl243 PNP lW rree air -60 160 28 I.OT -0.1 -so
2Nl244 PNP lW rree air -110 160 14 .ST -0.1 -90
2Nl247 NPN 200 6.0 175A 25T 5.00
2Nl248 NPN 200 6.0 175A 20T 5.00
2Nl251 NPN 150 15 100 85 70 7.5 so 20 2N635A 2
2Nl252 NPN 2W 20 175 15* 150 10 20
2Nl253 NPN 2W 20 175 40* ISO 10 20
2Nl261 PNP -45 95 20*
2Nl262 PNP -45 95 30* -2.0 -60
 7

MAXIMUM RATINGS ELECTRICAL

PARAMETERS
JEDEC Pcmw BVcE MIN. MIN. MIN. MAX. Closest Dwg.
No. Type Use @25°C BVce* lcma T.ioC hfe-hvs• @lcma fhfb me Gedb lco (µa) @Vee GE No.

2Nl263 PNP -45 95 45* -20 -60

2Nl264 PNP so -20• so 75 15 ).5 so -20
2Nl265 PNP so -10• 100 85 25 l 6-00 100 2Nl097 2
2Nl266 PNP 80 -10• 85 10 .l 100 -10 2Nl098 2
2Nl273 PNP-A 150 15 150 8SJ SOT 2.00 2Nl097 2
2Nl274 PNP-A 150 25 150 8SJ SOT 2.00 2Nl414 2
2Nl276 NPN Si AF 150 30 25 150 lOT 10 15 37T 1 30 2Nl276 4
2Nl277 NPN Si AF 150 30 25 150 20T 10 15 39T l 30 2Nl277 4
2Nl278 NPN Si AF 150 30 25 150 33T IO 15 44T 1 30 2Nl278 4
2Nl279 NPN Si AF 150 30 25 150 SOT 10 15 45T 1 30 2Nl279 4
2Nl280 PNP 200 16 400 85 40 -20 5 -10 -10 2N396 2
2Nl281 PNP 200 12 400 85 60 -20 7 -10 -10 2N396 2
2Nl282 PNP 200 6 400 85 70 -20 10 -10 -10 2N397 2
2Nl284 PNP 150 15 400 85 30 -10 5 -6 -20 2N396 2
2Nl287 PNP 165 20• 300 85 40 1.00 10 2N526 2
2Nl287A PNP 165 20• 300 85 40 1.00 10 2N527 2
2Nl288 NPN Obsolete 75 5 50 85 so• 10 40 5 s
2Nl289 NPN Obsolete 75 .15 50 85 so• 10 40 5 15
2Nl291 PNP 20W 30 3 85 40* 0.5 5 -2
2Nl293 PNP 20W 6-0 3 85 40* 0.5 5 -2
2Nl295 NPN 20W 80 3 85 40• 0.5 5 -2
2Nl297 PNP 20W 100 3 85 40* 0.5 5 -2
2Nl299 NPN 150 20 200 100 35* so 4.0 100 40 2N377, 2N634A 2, 2
2Nl300 PNP 150 -12 -100 85 50 -10 -3 2N711B 8
2Nl301 PNP 150 -12 -100 85 50 -10 -3 2N711B 8
2Nl302 NPN 150 25* 300 100 so 3.00 6.0 2Nl302 2
2Nl303 NPN 150 30* 300 100 so 3.00 6.0 2Nl303 2
2Nl304 NPN Sw 300 20 300 100 40* 10 5 6 25 2Nl304 2
2Nl305 NPN 150 30* 300 100 70 5.00 6.0 2Nl305 2
2Nl306 NPN Sw 300 15 300 100 6-0* 10 10 6 25 2Nl306 2
2Nl307 NPN 150 30* 300 100 100 10.0 6.0 2Nl307 2
2Nl308 NPN Sw 300 15 300 100 so• 10 15 6 25 2Nl308 2
2Nl309 NPN 150 30* 300 100 150 15.0 6.0 2Nl309 2
2Nl310 NPN 120 90 20• s I.ST 7 s 2Nl510 ·3
2Nl313 PNP 180 -15 400 100 40* 6 2.5 -o.s 2N396 2
2Nl316 PNP 200 15 400 85 so• 10 -5 -12 2N397 2
2Nl317 PNP 200 12 400 85 45* 10 -6 -12 2N397 2
2Nl318 PNP 200 6 400 85 40* 10 -7 -10 2N397 2
2Nl343 PNP 150 16 400 85 15* -so 4 -6 -15 2N395 2
2Nl344 PNP 150 10 400 85 60* -20 7 10 -15 2N397, 2N396 2,2
2Nl345 PNP 150 8 400 85 30* -400 10 -6 -12 2N397 2
2Nl346 PNP 150 10 400 85 40• -14 10 -5 -5 2N397 2
 MAXIMUM RATINGS ELECTRICALPARAMETERS

JEDEC Pcmw BVcB MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use @25°C BVco* lcma T,°C hfe-hPB* @lcma fhfb me Gedb lco (pa) @Vee GE No.
2Nl347 PNP 150 12 200 85 30* 10 5 -6 -12 2N396 2
2N1348 PNP 200 40* 400 85 95* 5.0 10 2N1305 2
2Nl352 PNP 150 20 200 85 40* 2.ST -5 -30 2N526, 2Nl925 2,2
2Nl353 PNP 200 10 200 85 25* 10 1.5 6 10 2N394, 2N397 2,2
2N1354 PNP 200 15 200 85 25* 10 3 6 15 2N395 2
2N1355 PNP 200 20 200 85 30* 10 5 6 20 2N396 2
2N1356 PNP 200 30• 200 85 80* 8.0 6.0 2N397 2
2N1357 PNP 200 15 200 85 40* 10 10 6 15 2N397 2
2N1358 PNP so• 95 40* 1.2 100
2N1366 Alloy Sw 150 20* 70* 10.0 2N397 2
2Nl367 Sw 150 20• 70* 10.0 2Nl307 2
2N1370 ~&°if 150 25• 150 100 so• 2.0 2N1415 2
2N1371 PNP 150 45* 150 100 80 2.0 2N1415 2
2N1372 PNP 210 25* 200 100 45 2.0 2Nl415 2
2N1373 PNP 250 45* 200 100 45 2.0 2Nl924 2
2N1374 PNP 250 25* 200 100 70 2.0 2N1415 2
2Nl375 PNP 250 45• 200 100 70 2.0 2Nl925 2
2N1376 PNP 250 2s• 200 100 95 2.0 2N1175 2
2N1377 PNP 250 45• 200 100 95 2.0 2N1926 2
2N1378 PNP 250 12* 200 100 200 2.0 2N508 2
2Nl379 PNP 250 25• 200 100 200 2.0 2Nll75 2
2Nl380 PNP 250 12* 200 100 100 2.0 2Nl097 2
2Nl381 PNP 250 25* 200 100 100 2.0 2N1414 2
2Nl382 PNP 200 25* 200 85 80 2.0 2N1415 2
2N1383 PNP 200 25• 200 85 so 2.0 2Nl414 2
2N1389 NPN 250 50* so 175 25 15 2N696 4
2N1404 PNP 150 25* 300 85 100* 4.00 5.0 2N404 2
2Nl4-08 PNP 150 so• 100 25 2Nl924 2
2N1411 PNP 25 @45°C -5 -so 85 20* -so 5 -5 2N962 8
2Nl413 PNP AFSw 200 -25 -200 85 25* -20 0.8 -12 -30 2Nl413 2
2Nl414 PNP AFSw 200 -25 -200 85 34* -20 1.0 -12 -30 2N1414 2
2Nl415 PNP AFSw 200 -25 -200 85 ss• -20 1.3 -12 -30 2Nl415 2
2Nl420 NPN-M 60() 60* 175 140* 250 2Nl711 4
2Nl420A NPN-PL 800 60* 200 120* 200 2Nl711 4
2Nl427 PNP 25 @45°C -6 -so 85 20• -50 s -6 2N782 8
2Nl428 PNP 100 -6 -so 140 12• -5 0.1 -6
2Nl429 PNP 100 -6 -so 140 12• -5 0.1 -6
2Nl431 NPN 180 15 100 75 75* 35 50 20 2N635A 2
2Nl432 PNP 100 -45 10 100 30 2 15 -45
2Nl433 PNP -so 3.5 95 20• 2 5 0.1 -2
2Nl434 PNP -50 3.5 95 45* 2 s 0.1 -2
2Nl435 PNP -SO 3.5 95 so• 2 5 0.1 -2
 MAXIMUM RATINGS ELECTRICAL
PARAMETERS
JEDEC Pcmw BVce MIN. MIN. MIN. MAX. Closest Dwg.
No. Type Use @25°C BVce* lcma T,10C hfe-hFE* @lcma fhrb me Gedb lco (µa) @Vee GE No.

2Nl436 PNP so -15* -so 100 20• -10

2Nl446 PNP 200 25 400 85 16* 20 .8 10 30 2N524 2
2Nl447 PNP 200 25 400 85 35* 20 1.5 10 30 2N525 2
2Nl448 PNP 200 25 400 85 50* 20 2 10 30 2N526 2
2Nl449 PNP 200 25 400 85 10• 20 2.5 10 30 2N527 2
2Nl450 PNP 120 30* 100 85 20• 10 10 7
2Nl451 PNP 200 45* 400 85 45* 1.50 15 2Nl413 2
2Nl452 PNP 200 45* 400 85 60* 2.20 15 2Nl414 2
2Nl471 PNP 200 12• 200 85 160* 5.0 5.0 2N508 2
2Nl472 NPN 100 25 100 150 20 10 0.5 10
2Nl473 NPN 20 400 75 25* 400 4 100 40 2N635A 2
2N1478 PNP 250 -30* -400 100 40* -100 3 5 1.5 2N396, 2Nl415 2, 2
2Nl479 NPN 4W 60* 1.5 175 15* 200 1.5 60 10 30 2N497A 8
2Nl480 NPN 4W 100* 1.5 175 15* 200 1.5 100 10 30 2N497A 8
2Nl481 NPN 4W 60* 1.5 175 35* 200 1.5 60 10 30 2N656A 8
2Nl482 NPN 4W 100• 1.5 175 35* 200 1.5 100 10 30 2N656A 8
2Nl483 NPN 15W 60* 3 175 15* 750 1.25 15 30
2Nl484 NPN 15W 100• 3 175 15* 750 1.25 15 30
2Nl485 NPN 15W 60* 3 175 35* 750 1.25 15 30
2Nl486 NPN 15W 100* 3 175 35* 750 1.25 15 30
2Nl487 NPN 60W 60* 6 175 10• 1.5 1 25 30
2Nl488 NPN 60W 100* 6 175 10• 1.5 1 25 30
2Nl489 NPN 60W 60* 6 175 25* 1.5 1 25 30
2Nl490 NPN 60W 100* 6 175 25* 1.5 1 25 30
2Nl499 PNP 25 -25* -so 85 20• -10 5 -5 2N711A 8
2Nl499A PNP 60 20• so 100 so• 110 3.0 2N711B 8
2Nl500 PNP so -15* -50 100 20• -so 5 -5 2N960 8
2Nl501 PNP -60* 95 25* -2A -2 -60
2Nl502 PNP -40* 95 25* -2A -2 -40
2Nl507 NPN 0.6W 60* 500 175 100• 150 l 30 2N711 8
2Nl510 NPN Neon India tor 75 70 20 85 8* 1 5 75 2Nl510 3
2Nl514 NPN 2.5 l00V 8.0 Amps 175 75* 1000 Kc 25 30 2Nl924 2
2Nl524 PNP 80 24* 10 85 60* 33.0 16 2Nl924 2
2Nl525 PNP 80 24* 10 85 60* 33.0 16 2Nl925 2
2Nl564 NPN 1200 80* so 175 70 40 1.0 2N698 4
2Nl565 NPN 1200 80* so 175 120 50 1.0 2N699 4
2Nl566 NPN 1200 80* 50 175 120 50 1.0 2N699 4
2Nl566A NPN 600 80 100 200 125 200 .so 2N699 4
2Nl572 PNP 600 125 35 2N698 4
2Nl573 PNP 600 125 70* 2N699 4
2Nl574 PNP 600 125 140* 2N699 4
2Nl586 NPN 150 15 25 18 4.0 2Nl276 4
 MAXIMUM RATINGS ELECTRICALPARAMETERS

JEDEC Pcmw BVcs MIN. MIN. MIN. MAX. Closest Dwg.

No. Type Use @25°C BVco* lcma T,oc hre-hvs* @lcma fhfb me Gedb lco (pa) @Yeo GE No.

2Nl587 NPN 150 30 25 18 4.0 2Nl276 4

2Nl588 NPN 150 60 25 18 4.0 2N332 4
2Nl589 NPN 150 15 25 so 6.0 2Nl277 4
2Nl590 NPN 150 30 25 so 6.0 2Nl277 4
2Nl591 NPN 150 60 25 50 6.0 2N334 4
2Nl592 NPN 150 15 25 140 7.0 2Nl279 4
2Nl593 NPN 150 30 25 140 7.0 2Nl279 4
2Nl594 NPN 150 60 25 140 7.0 2N337 4
2Nl605 NPN 150 24 100 100 40• 20 4 5 12
2Nl605A NPN 200 40 100 100 60• 6.0 10
2Nl613 NPN-PL Sw 800 75 200 so• 160 .01 2Nl613 4
2Nl614 PNP Sw 240 -65• -300 85 18* -20 0.5 -25 -65 2Nl614 1
2Nl624 NPN 150 25 100 120• 8.0 10 2N634A 2
2Nl644 NPN 600 60 175 75• 150 1.0 2N697 4
2Nl644A NPN 600 60* 175 75• 150 1.0 2N697 4
2Nl646 PNP 150 15* lOOS 20• 3.0
2Nl671 PN Si Uni SEE G-E FAMILY OF SPECIFICATIONS SECTION 2Nl671 s
2Nl671A PN Si Uni SEE G-E FAMILY OF SPECIFICATIONS SECTION 2Nl671A 5
2Nl671B PN Si Uni SEE G-E FAMILY OF SPECIFICATIONS SECTION 2Nl671B s
2Nl672 NPN 120 40* so 2.0 25 2Nl302 2
2Nl672A NPN 120 40* 85 20• 2.0 2N634A 2
2Nl684 PNP 100 25* 100 100 8.0 20 2N397 2
2Nl694 NPN 75 20• 25 85S 30* 9.0 1.5 2Nl694. 2
2Nl700 NPN 5000 60* 1.0 Amp 200 20 1.20 75 2N656A 2
2N1705 PNP 200 18* 4.00 100 110 4.0 10 2N527 2
2Nl706 PNP 200 25* 400 100 90 3.0 10 2NS27 2
2N1707 PNP 200 30* 400 100 95 3.0 15 2NS27 2
2Nl711 NPN 800 30* 500 175 35 230 2N1711 4
2Nl714 NPN 7.5 90 1.0 Amp 175 16 7D2 11
2Nl715 NPN 7.5 150 l.0Amp 175 16 7D4. 11
2Nl716 NPN 7.5 90 l.OAmp 175 16 7D13 11
2Nl717 NPN 7.5 150 l.OAmp 175 16 7D4. 11
2Nl718 NPN 7.5 90 1.0 Amo 175 16 7G2
2Nl719 NPN 7.5 150 1.0 Amp 175 16 7G4.
2Nl720 NPN 7.5 90 l.OAmp 175 16 7Gl3
2Nl721 NPN 7.5 150 l.0Amp 175 16 7G4
2Nl726 PNP 60 20 so 100 120• 150 2N964 8
2Nl727 PNP 60 20 so 100 150* 150 2N960 8
2Nl728 PNP 60 20 50 100 100• 150 2N960 8
2Nl754 PNP so 13* 100 85 so• 75 2N711A 8
2Nl779 NPN 100 25* 100 100 40• s.o 10 2N634.A 2
2Nl780 NPN 100 2s• 100 100 4.0• 8.0 10 2N634A 2
 MAXIMUM RATINGS ELECTRICAL
PARAMETERS
JEDEC Pcmw BVcB MIN. MIN. MIN. MAX. Closest Dwg.
No. Type Use @25°C BVca• lcma T,°C hre-hPs• @lcma fhfb me Gedb lco (µa) @Vea GE No.
2Nl781 NPN 100 25• 100 100 60• 6.0 20 2N634A 2
2Nl785 PNP 45 10• so 85 60• 125 10 2N966 8
2Nl786 PNP 45 10• so 85 60• 125 10 2N962 8
2Nl787 PNP 45 IS• so 85 60• 125 IO 2N960 8
2Nl808 NPN 150 25• 300 1008 60• 4.0 5.0 2N634A 2
2Nl889 NPN-PL 800 100• 200J 10• no .01
2Nl890 NPN-PL 800 100• 200J 120• 130 .01
2NI893 NPN-PL 8w 800 120• 200J 85• 110 .01 2Nl893 4
2Nl924 PNP AF 225 -60• -500 85 30• -100 1.0 -10 45 2Nl924 2
2Nl925 PNP AF 225 -60• -500 85 47• -100 1.3 -10 45 2Nl925 2
2Nl926 PNP AF 225 -60• -500 85 65• -100 1.5 -10 45 2Nl926 2
2Nl954 PNP 200 60• 1.0 Amp lOOJ 120 20 2Nl926 2
2Nl955 PNP 200 60• 1.o Amp lOOJ 200 20 2Nl926 2
2Nl956 PNP 200 60• 1.o Amp IOOJ 120 20 2Nl926 2
2Nl958 NPN 600 60• 500 175 45 .so 2N2194A 4
2Nl959 NPN 600 60• 500 175 80 .so 2N2193A 4
2Nl960 PNP 150 IS• 200 100 25 3.0 2N781 8
2Nl961 PNP 150 12• 200 100 20 3.0 2N782 8
2Nl969 PNP 150 30• 400 100 125 10 5.0 2Nl307 2
2Nl973 PNP 800 100* 200J 100 60 .025
2Nl974 PNP 800 100• 200J 50 so .025
2Nl975 PNP 800 100• 200J 30 40 .025
2Nl986 NPN 600 so• ISOJ ISO• 50.0 5.0 2N697 4
2Nl987 NPN 600 so• lSOJ so• so.o 5.0 2N696 4
2Nl997 PNP 250 45• 500 1008 75• 3.0 6.0 2N527 2
2Nl998 PNP 250 35• 500 1008 100• 6.50 6.0 2N527 2
2N2022 PNP 150 IS• 50 lOOJ 35 3.0 2N828 8
2N2042 PNP 200 105* so .so 2Nl925 2
2N2042A PNP 200 105* 200 100 so .so 25 2Nl925 2
2N2043 PNP 200 105* 113 .75 2Nl926 2
2N2043A PNP 200 105* 200 100 113 .75 25 2Nl926 2
2N2049 NPN-PL 800 75* 200J 60* 50 .01
2N2060 NPN-PL 500 100* 200J 35* 2.0 2N2060 8
2N2085 NPN 150 33* 500 100 100 8.0 5.0 2N635A 2
2N2086 NPN 600 120• 500 3008 70* 225 2.0 2N2194 4
2N2087 NPN 600 120• 500 3008 65* 225 2.0 2N2193 4
2N2106 NPN-M AF 125 60* lSOJ 15MC .20 30 2N2106 2
2N2107 NPN-M AF 125 60* 150J 15MC .20 30 2N2107 2
2N2108 NPN-M AF 125 60* lSOJ !SMC .20 30 2N2108 2
2N2169 PNP 60 15* 1008 85• 3.0 2N781 8
2N2192 NPN-PEP Sw 800 60 1.0 Amp 300S 100• 150 lOmµa 30 2N2192 4
2~2192A NPN-PEP Sw 800 60 1.0 Amp 3008 100• 150 lOmµa 30 2N2192A 4
 MAXIMUM RATINGS ELECTRICALPARAMETERS
JEDEC Pcmw BVce MIN. MIN. MIN. MAX. Closest Dwg.
No. Type Use @25°C BVce* lcma T,oc hre-hPE* @lcma fhfb me Ge db lco (µa) @Vee GE No.
2N2193 NPN-PEP Sw 800 80 l.0Amp 3008 40* 150 10 mp.a 30 2N2193 4
2N2193A NPN-PEP Sw 800 80 l.0Amp 300S 40* 150 10 mp.a 30 2N2193A 4
2N2194 NPN-PEP Sw 800 60 l.0Amp 3008 20• 150 10 mJ&&. 30 2N2194 4
2N2194A NPN-PEP Sw 800 60 1.0 Amp 300S 20• 150 10 mp.a 30 2N2194A 4
2N2195 NPN-PEP Sw 600 45 l.0Amp 3008 20• 150 100 mp.a 60 2N2195 4
2N2195A NPN-PEP Sw 600 45 l.0AmP 300S 20• 150 100 mua 60 2N2195A 4
2N2196 NPN Power 2W so• 175 10• 1ST 75 80 2N2196 9
2N2197 NPN Power 2W 80* 175 20• 1ST 75 80 2N2197 9
2N2201 NPN Power 15W 120• 17SJ 30* lSMC 50 120 2N2201 9
2N2202 NPN Power 15W 120* 17SJ 30* lSMC 50 120 2N2202 10
2N2203 NPN Power 15W 120* 175J 30* lSMC so 120 2N2203 11
2N2204 NPN Power 15W 120• 175J 30* lSMC so 120 2N2204 12
4020 NPN Sw 150 40* 25 lS0J 33* 1.0 4020 4
4021 NPN Sw 150 40* 25 lS0J 88* 1.0 4021 4
4022 NPN Sw 150 40* 25 lS0J 185* 1.0 4022 4
4024 NPN Sw 125 15* 25 125J 33* 1.0 4024 4
4025 NPN Sw 125 15* 25 125J 88* 1.0 4025 4
4026 NPN Sw 125 15* 25 12SJ 133* 1.0 4026 4
4C28 NPN Sw 150 40* 25 12SJ 15 12.0 2.0 4C28 4
4C29 NPN Sw 150 40* 25 12SJ 30 12.0 2.0 4C29 4
4C3o NPN Sw 150 40* 25 125J 55 12.0 2.0 4C30 4
4C31 NJ>N Sw 150 40* 25 125J 115 12.0 2.0 4C31 4
7B1 NPN Power 15W 80* 175 12* 15T 50 80 781 9
7Cl NPN Power 15W 80* 175 12* 15T so 80 7Cl 10
701 NPN Power 15W 80* 175 12* 1ST so 80 701 11
7El NPN Power 15W 80* 175 12* 1ST 50 80 7El 12
7Fl NPN Power 7W 80* 175 12* 15T 50 80 7Fl 13
782 NPN Power 15W 80* 175 30* 1ST so 80 782 9
7C2 NPN Power 15W 80* 175 30* 15T so 80 7C2 10
702 NPN Power 15W 80* 175 30* 1ST so 80 702 11
7E2 NPN Power 15W 80* 175 30* 1ST so 80 7E2 12
7F2 NPN Power 7W 80* 175 30* 15T so 80 7F2 13
783 NPN Power 15W 120* 175 12* 15T so 120 783 9
7C3 NPN Power 15W 120* 175 12* 1ST so 120 7C3 10
703 NPN Power 15W 120* 175 12• 1ST so 120 703 11
7E3 NPN Power 15W 120• 175 12• 1ST so 120 7E3 12
7F3 NPN Power 7W 120• 175 12• 1ST so 120 7F3 13
ABBREVIATIONS
AF-Audio Frequency Amplifier and General Purpose PNP-EM-PNP Epitaxial Mesa
AF Out-High current AF Output PNP-M-PNP Mesa
AF Sw-Low frequency switch PNP-MD-PNP Micro-Alloyed Diffused
GD-Grown Diffused Pt-Point contact types
IF-Intermediate Frequency Amplifier Pwr-Power output I watt or more
}-Operating Junction Temperature RF-Radio Frequency Amplifier
lo IF-Low IF (262 Kc) Amplifier S-Storage Temperature
NPN-A-NPN Alloyed Si-Silicon High Temperature Transistors (all others germanium)
NPN-D-NPN Diffused Sw-High current High frequency switch
NPN-EM-NPN Epitaxial Mesa T-Typical Values
NPN-FA-NPN Fused Alloyed UNI-Unijunction Transistor
NPN-G-NPN Grown
NPN-GD-NPN Grown Diffused
NPN-M-NPN Mesa NOTE: Closest GE types are given only as a general guide and are
NPN-PL-NPN Planar based on available published electrical speci6cations. However, ·
NPN-PEP-NPN Planar Epitaxial Passivated General Electric Company makes no representation as to the
accuracy and completeness of such information. Since manu-
NPN-PM-NPN Planar Epitaxial Mesa
facturing techniques are not identical, the General Electric
Osc-High gain High frequency RF oscillator
Company makes no claim, nor does it warrant, that its trans-
PNP-A-PNP Alloyed istors are exact equivalents or replacements for the types
PNP-D-PNP Diffused referred to.
~
PRINTED IN U .S . A . 450. 19 ~ / 6 2.

GEN·ERA L • ELECTRI C
SEMICONDUCTOR
PRODUCTS
DEPARTMENT
ELECTRONICS
PARK
· SYRACUSE
I.NEWYORK

( IN CA.NADA, CANADIAN GENERAL ELECTR I C COMPANY, LTD . , TORONTO, ONTARIO • OUTSIDE THE U.S.A . , AN O CANA DA, BY:
INTERNA TI ONAL GENERAL ELECTR IC COM PANY , INC • • ELECTRONIC S DIV ISIO N , 150 EAST 42ND ST., HEW YORK, N. Y . , U .S . A .)
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