NXP level-shifting and

hot-swappable I2C/SMBus
buffers PCA951xA

I2C/SMBus buffers for backplane

multi-point and hot-swap applications
These bus buffers isolate the backplane and card capacitance to permit the design of larger
systems. They support live insertion with idle detect and precharge features, provide bidirectional
operation, and are suitable for multi-master environments.

Key features Applications

Ñ Bidirectional buffering for live insertion/removal Ñ Insertion/removal of unpowered cards into active I2C/SMBus
from backplane Ñ Increasing the number of I2C/SMBus devices
Ñ Compatible with I2C-bus standard and fast mode, Ñ Increasing the I2C/SMBus wiring capacitance beyond the
and SMBus 400-pF limit
Ñ Support clock stretching, multiple master arbitration, Ñ Supporting different operating supply voltages or logic
and synchronization voltage levels within a system
Ñ Operating power-supply voltage: 2.7 to 5.5 V Ñ Isolating sections of the I2C/SMBus
Ñ Operating temperature: -40 to +85 °C Ñ Long bus wiring or multi-point backplane traces
Ñ 8-pin SO and TSSOP (MSOP) packages
PCA951xA bus buffers allow insertion of an I/O card into a live
Key benefits backplane without corrupting the clock or data buses. They
Ñ Enable 24/7 system operation are compatible with the IPMI system-management architecture
Ñ Use I2C/SMBus in multi-point architectures and support PICMG 2.9 CompactPCI/VME and PICMF 3.x
Ñ Build expandable systems without modifying Advanced TCA cards.
current architecture
Ñ Simple implementation requires no programming The devices provide bidirectional buffering for the I2C-bus
Ñ Small footprint clock (SCL) and data (SDA) lines, so they increase fanout and
prevent corruption of the active I2C-bus data during board
insertion or removal from the backplane.

1079 NXP I2C-SMBus PCA951xA v4.i1 1 06-08-2008 17:01:15

 They are suitable for use in multi-master I2C/SMBus For PICMB applications, instead of using pull-up resistors, the
environments, since they support bus arbitration and PCA9513A supplies a 92-μA current source to the SCLIN and
contention with master devices located on any I2C-bus SDAIN pins. Including the current source in the device reduces
segments. They operate at up to 400 kHz with a supply part count and provides a consistent RC time constant while
voltage from 2.7 to 5.5 V and are not 5V tolerant due to the cards are removed or inserted into the backplane. As more
rise time accelerator except for the PCA9510A since it doesn’t cards are added, thereby increasing the bus capacitance, the
have the rise time accelerator. They are compatible with effective pull-up resistance decreases because there are more
I2C-bus standard mode (0-100 kHz), fast mode (0-400 kHz), current sources in parallel and thus maintains the RC time
and the SMBus (10-100 kHz). constant.

Control circuitry prevents the backplane I2C-bus from being On the PCA9510A, PCA9511A, PCA9513A, and the PCA9514A,
connected to the card I2C-bus until a Stop command or Bus a digital ENABLE input pin enables the device when asserted
Idle occurs on the backplane. When the connection is made, HIGH and forces the device into a low-current mode when
the bus buffers provide bidirectional buffering, keeping the asserted LOW. An open-drain READY output pin indicates
backplane and card capacitances isolated. that the backplane and card sides are connected together
(HIGH) or not (LOW).
Rise-time accelerator circuitry support the use of weaker
DC pull-up resistors while meeting rise-time requirements. The PCA9512A is similar to the PCA9511A, but without the
In the PCA9513A and the PCA9514A, the threshold for the digital ENABLED input pin and the open-drain READY output
rise-time accelerator has been moved from 0.6 V to 0.8 V, to pin. It replaces the ENABLED pin with a dedicated pin for
provide better noise margin. In the PCA9510A, the rise-time supply voltage (VCC2) on the card side. This provides level
accelerator is deactivated. shifting, with optimal noise margin, between 3.3- and 5-V
systems. The backplane and the card can both be powered
During insertion, the PCA9510A/11A SDA and SCL lines are with supply voltages ranging from 2.7 to 5.5 V with no
precharged to 1 V. This minimizes the current required to constraints on which supply voltage is higher. The PCA9512
charge the parasitic capacitance of the chip and prevents the replaces the READY pin with a digital CMOS input pin (ACC),
I2C-bus from glitching. The PCA9513A and the PCA9514A which enables when connected to VCC2 and disables when
don’t have this feature, so they can support those live-insertion connected to the ground of the rise-time accelerator current
applications where the precharge is detrimental and new for lightly loaded circuits.
resistive-tip pins are more effective.

PCA951xA devices in hot-swap application PCA9510A/11A/13A/14A application diagram

VCC
I2C master or slave devices
(2.7 V to 5.5 V)
PCA9510A/11A/12A/13A/14A C1
0.01 pF
R1 R2 R5 R3 R4
10 k7 10 k7 10 k7 10 k7 10 k7
8
VCC
3 2
SCLIN SCLOUT

BACKPLANE LINE CARD

6 7
SDAIN SDAOUT

Connectors 1 5
VME/CPCI or SCL ENABLE ENABLE READY
ENABLE READY
ATCA Tranceivers SDA GND
4

R1 and R2 are not required for PCA9513A applications since

the internal 92-μA current source maintains the SCLIN
and SDAIN lines high.

1079 NXP I2C-SMBus PCA951xA v4.i2 2 06-08-2008 17:01:17

 PCA9510A/11A/13A/14A pinout diagram PCA9512A pinout diagram
TOP VIEW TOP VIEW

ENABLE 1 8 VCC VCC2 1 8 VCC

SCLOUT 2 7 SDAOUT SCLOUT 2 7 SDAOUT

SCLIN 3 6 SDAIN SCLIN 3 6 SDAIN

GND 4 5 READY GND 4 5 ACC

PCA9510A/11A/13A/14A PCA9512A
Pin description Pin description

Pin Symbol Description Pin Symbol Description

1 ENABLE Chip enable pin. Grounding this pin puts the 1 VCC2 Supply voltage for devices on each card’s I2C-bus.
part in a low-current (<1 μA) mode. It also Connect it to the pull-up resistors of SDAUT
disables the rise-time accelerators. Isolates and SCLOUT.
SDAIN from SDAOUT and isolates SCLIN from
SCLOUT. 2 SCLOUT Serial clock output to and from the SCL bus on
the card.
2 SCLOUT Serial clock output to and from the SCL bus on
the card. 3 SCLIN Serial clock input to and from the SCL bus on the
backplane.
3 SCLIN Serial clock input to and from the SCL bus on
the backplane. 4 GND Ground. Connect this pin to a ground plane for
best results.
4 GND Ground. Connect this pin to a ground plane for
best results. 5 ACC CMOS-threshold digital-input pin that enables and
disables the rise-time accelerators on all four SDA
5 READY This is an open-drain output that pulls LOW
when SDAIN and SCLIN are disconnected from and SCL pins. ACC enables all accelerators when
SDAOUT and SCLOUT, and turns off when the set to VCC2, and turns them off when set to GND.
two sides are connected. 6 SDAIN Serial data input to and from the SDA bus on the
6 SDAIN Serial data input to and from the SDA bus on backplane/long-distance bus.
the backplane. 7 SDAOUT Serial data output to and from the SDA bus on
7 SDAOUT Serial data output to and from the SDA bus on the card.
the card. 8 VCC Power supply from the backplane. Connect it to
8 VCC Power supply. the pull-up resistors from SDAIN and SCLIN.

PCA9512A application diagram

VCC
(2.7 V to 5.5 V) CARD_VCC
C2 C1 (2.7 V to 5.5 V)
0.01 pF 0.01 pF
R3 R4 R5
R1 R2 10 k7 10 k7 10 k7
8 1
10 k7 10 k7
VCC VCC2

6 7
SDAIN SDAOUT

BACKPLANE LINE CARD

3 2
SCLIN SCLOUT

5
ENABLE READY ACC
GND
GND
4

1079 NXP I2C-SMBus PCA951xA v4.i3 3 06-08-2008 17:01:18

 Selection guide

Features PCA9510A PCA9511A PCA9512A PCA9513A PCA9514A

Idle detect Yes Yes Yes Yes Yes

High-impedance SDA, SCL, pins for VCC = 0 V Yes Yes Yes Yes Yes
Rise-time accelerator circuitry on all SDA and SCL lines - Yes Yes Yes Yes
Rise-time accelerator circuitry hardware disable pin for lightly loaded systems - - Yes - -
Rise-time accelerator threshold 0.8 vs. 0.6 V (improves noise margin) - - Yes Yes Yes
Ready open-drain output Yes Yes - Yes Yes
Two VCC pins to support level translation from 5.0 to 3.3 V with improved noise margins - - Yes - -
1-V precharge on all SDA and SCL lines In only Yes Yes - -
92-μA current source on SCLIN and SDAIN for PICMG applications - - - Yes -
5 V overvoltage tolerance Yes - - - -

Ordering information

Package Container PCA9510A PCA9511A PCA9512A PCA9513A PCA9514A

Tube PCA9510AD PCA9511AD PCA9512AD PCA9513AD PCA9514AD
SO
T&R PCA9510AD-T PCA9511AD-T PCA9512AD-T PCA9513AD-T PCA9514AD-T
TSSOP T&R PC A9510ADP-T PCA9511ADP-T PCA9512ADP-T PCA9513ADP-T PCA9514ADP-T

In Europe and Asia, add “,112” for tube orders and substitute “,118” for “-T” for tape and reel orders (e.g., PCA9511AD,112 and PCA9511AD,118).
Additional technical information can be found in Application Note AN10160 (www.standardics.nxp.com/support/documents) and additional
information on packages, including outline dimensions, MSL ratings, Theta JA can be found at www.standardics.nxp.com/packaging.

www.nxp.com/i2clogic

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© 2008 NXP B.V.
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. Date of release: July 2008
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and Document order number: 9397 750 16530
reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Printed in the Netherlands
Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

1079 NXP I2C-SMBus PCA951xA v4.i4 4 06-08-2008 17:01:19