4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM RDIMM

Features

DDR3 SDRAM RDIMM

MT36JS(Z)F51272PZ

Features Figure 1: 240-Pin RDIMM (MO-269 R/C J)

Module height: 30.0mm (1.181in)
• DDR3 functionality and operations supported as
defined in the component data sheet
• 240-pin, registered dual in-line memory module
(RDIMM)
• Fast data transfer rates: PC3-12800, PC3-10600,
PC3-8500, or PC3-6400
• 4GB (512 Meg x 72) Figure 2: 240-Pin RDIMM (MO-269 R/C E2)
• VDD = 1.5V ±0.075V Module height: 30mm (1.181in)
• VDDSPD = 3.0V–3.6V
• Supports ECC error detection and correction
• Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
• Dual rank
• On-board I2C temperature sensor with integrated Options Marking
serial presence-detect (SPD) EEPROM • Operating temperature
• 8 internal device banks – Commercial (0°C ≤ T A ≤ +70°C) None
• Full module heat spreader
• Fixed burst chop (BC) of 4 and burst length (BL) of 8
– With heat spreader JSZF
via the mode register set (MRS)
– Without heat spreader JSF
• Selectable BC4 or BL8 on-the-fly (OTF) • Package
• Gold edge contacts – 240-pin DIMM (halogen-free) Z
• Halogen-free • Frequency/CAS latency
• Fly-by topology – 1.25ns @ CL = 11 (DDR3-12800) -1G6
• Terminated control, command, and address bus – 1.5ns @ CL = 9 (DDR3-1333) -1G4
– 1.87ns @ CL = 7 (DDR3-1066) -1G1

Table 1: Key Timing Parameters

Speed Industry Data Rate (MT/s) tRCD tRP tRC

Grade Nomenclature CL = 11 CL = 10 CL = 9 CL = 8 CL = 7 CL = 6 CL = 5 (ns) (ns) (ns)

-1G6 PC3-12800 1600 1333 1333 1066 1066 800 667 13.125 13.125 48.125
-1G4 PC3-10600 – 1333 1333 1066 1066 800 667 13.125 13.125 49.125
-1G1 PC3-8500 – – – 1066 1066 800 667 13.125 13.125 50.625
-1G0 PC3-8500 – – – 1066 – 800 667 15 15 52.5
-80B PC3-6400 – – – – – 800 667 15 15 52.5

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Products and specifications discussed herein are subject to change by Micron without notice.
 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM RDIMM
Features

Table 2: Addressing

Parameter 4GB
Refresh count 8K
Row address 16K A[13:0]
Device bank address 8 BA[2:0]
Device configuration 1Gb (256 Meg x 4)
Column address 2K A[11, 9:0]
Module rank address 2 S#[1:0]

Table 3: Part Numbers and Timing Parameters – 4GB Modules (With Heat Spreader)
Base device: MT41J256M4,1 1Gb DDR3 SDRAM
Module Module Memory Clock/ Clock Cycles
Part Number2 Density Configuration Bandwidth Data Rate (CL-tRCD-tRP)
MT36JSZF51272PZ-1G6__ 4GB 512 Meg x 72 12.8 GB/s 1.25ns/1600 MT/s 11-11-11
MT36JSZF51272PZ-1G4__ 4GB 512 Meg x 72 10.6 GB/s 1.5ns/1333 MT/s 9-9-9
MT36JSZF51272PZ-1G1__ 4GB 512 Meg x 72 8.5 GB/s 1.87ns/1066 MT/s 7-7-7

Table 4: Part Numbers and Timing Parameters – 4GB Modules (Without Heat Spreader)
Base device: MT41J256M4,1 1Gb DDR3 SDRAM
Module Module Memory Clock/ Clock Cycles
Part Number2 Density Configuration Bandwidth Data Rate (CL-tRCD-tRP)
MT36JSF51272PZ-1G6__ 4GB 512 Meg x 72 12.8 GB/s 1.25ns/1600 MT/s 11-11-11
MT36JSF51272PZ-1G4__ 4GB 512 Meg x 72 10.6 GB/s 1.5ns/1333 MT/s 9-9-9
MT36JSF51272PZ-1G1__ 4GB 512 Meg x 72 8.5 GB/s 1.87ns/1066 MT/s 7-7-7

Notes: 1. The data sheet for the base device can be found on Micron’s web site.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.
Consult factory for current revision codes. Example: MT36JSF51272PZ-1G4J1.

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 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM RDIMM
Pin Assignments

Pin Assignments

Table 5: Pin Assignments

240-Pin DDR3 RDIMM Front 240-Pin DDR3 RDIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1 VREFDQ 31 DQ25 61 A2 91 DQ41 121 VSS 151 VSS 181 A1 211 VSS
2 VSS 32 VSS 62 VDD 92 VSS 122 DQ4 152 DQS12 182 VDD 212 DQS14
3 DQ0 33 DQS3# 63 NF 93 DQS5# 123 DQ5 153 DQS12# 183 VDD 213 DQS14#
4 DQ1 34 DQS3 64 NF 94 DQS5 124 VSS 154 VSS 184 CK0 214 VSS
5 VSS 35 VSS 65 VDD 95 VSS 125 DQS9 155 DQ30 185 CK0# 215 DQ46
6 DQS0# 36 DQ26 66 VDD 96 DQ42 126 DQS9# 156 DQ31 186 VDD 216 DQ47
7 DQS0 37 DQ27 67 VREFCA 97 DQ43 127 VSS 157 VSS 187 EVENT# 217 VSS
8 VSS 38 VSS 68 Par_In 98 VSS 128 DQ6 158 CB4 188 A0 218 DQ52
9 DQ2 39 CB0 69 VDD 99 DQ48 129 DQ7 159 CB5 189 VDD 219 DQ53
10 DQ3 40 CB1 70 A10 100 DQ49 130 VSS 160 VSS 190 BA1 220 VSS
11 VSS 41 VSS 71 BA0 101 VSS 131 DQ12 161 DQS17 191 VDD 221 DQS15
12 DQ8 42 DQS8# 72 VDD 102 DQS6# 132 DQ13 162 DQS17# 192 RAS# 222 DQS15#
13 DQ9 43 DQS8 73 WE# 103 DQS6 133 VSS 163 VSS 193 S0# 223 VSS
14 VSS 44 VSS 74 CAS# 104 VSS 134 DQS10 164 CB6 194 VDD 224 DQ54
15 DQS1# 45 CB2 75 VDD 105 DQ50 135 DQS10# 165 CB7 195 ODT0 225 DQ55
16 DQS1 46 CB3 76 S1# 106 DQ51 136 VSS 166 VSS 196 A13 226 VSS
17 VSS 47 VSS 77 ODT1 107 VSS 137 DQ14 167 NU 197 VDD 227 DQ60
18 DQ10 48 VTT 78 VDD 108 DQ56 138 DQ15 168 RESET# 198 NC 228 DQ61
19 DQ11 49 VTT 79 NC 109 DQ57 139 VSS 169 CKE1 199 VSS 229 VSS
20 VSS 50 CKE0 80 VSS 110 VSS 140 DQ20 170 VDD 200 DQ36 230 DQS16
21 DQ16 51 VDD 81 DQ32 111 DQS7# 141 DQ21 171 A15 201 DQ37 231 DQS16#
22 DQ17 52 BA2 82 DQ33 112 DQS7 142 VSS 172 A14 202 VSS 232 VSS
23 VSS 53 Err_Out# 83 VSS 113 VSS 143 DQS11 173 VDD 203 DQS13 233 DQ62
24 DQS2# 54 VDD 84 DQS4# 114 DQ58 144 DQS11# 174 A12 204 DQS13# 234 DQ63
25 DQS2 55 A11 85 DQS4 115 DQ59 145 VSS 175 A9 205 VSS 235 VSS
26 VSS 56 A7 86 VSS 116 VSS 146 DQ22 176 VDD 206 DQ38 236 VDDSPD
27 DQ18 57 VDD 87 DQ34 117 SA0 147 DQ23# 177 A8 207 DQ39 237 SA1
28 DQ19 58 A5 88 DQ35 118 SCL 148 VSS 178 A6 208 VSS 238 SDA
29 VSS 59 A4 89 VSS 119 SA2 149 DQ28 179 VDD 209 DQ44 239 VSS
30 DQ24 60 VDD 90 DQ40 120 VTT 150 DQ29 180 A3 210 DQ45 240 VTT

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 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM RDIMM
Pin Descriptions

Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR3
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.

Table 6: Pin Descriptions

Symbol Type Description

Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column ad-
dress and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments Table for density-specific
addressing information.
BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, or MR3) is loaded during the LOAD MODE command.
CKx, Input Clock: Differential clock inputs. All control, command, and address input signals are
CKx# sampled on the crossing of the positive edge of CK and the negative edge of CK#.
CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui-
try and clocks on the DRAM.
DMx Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH, along with that input data, during a write ac-
cess. Although DM pins are input-only, DM loading is designed to match that of the
DQ and DQS pins.
ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termi-
nation resistance internal to the DDR3 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.
RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
RESET# Input Reset: RESET# is an active LOW asychronous input that is connected to each DRAM
(LVCMOS) and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitial-
ized as though a normal power-up was executed.
Sx# Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command
decoder.
SAx Input Serial address inputs: Used to configure the temperature sensor/SPD EEPROM ad-
dress range on the I2C bus.
SCL Input Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communi-
cation to and from the temperature sensor/SPD EEPROM on the I2C bus.
CBx I/O Check bits: Used for system error detection and correction.
DQx I/O Data input/output: Bidirectional data bus.
DQSx, I/O Data strobe: Differential data strobes. Output with read data; edge-aligned with
DQSx# read data; input with write data; center-aligned with write data.

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 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM RDIMM
Pin Descriptions

Table 6: Pin Descriptions (Continued)

Symbol Type Description

SDA I/O Serial data: Used to transfer addresses and data into and out of the temperature sen-
sor/SPD EEPROM on the I2C bus.
TDQSx, Output Redundant data strobe (x8 devices only): TDQS is enabled/disabled via the LOAD
TDQSx# MODE command to the extended mode register (EMR). When TDQS is enabled, DM is
disabled and TDQS and TDQS# provide termination resistance; otherwise, TDQS# are
no function.
Err_Out# Output Parity error output: Parity error found on the command and address bus.
(open drain)
EVENT# Output Temperature event: The EVENT# pin is asserted by the temperature sensor when crit-
(open drain) ical temperature thresholds have been exceeded.
VDD Supply Power supply: 1.5V ±0.075V. The component VDD and VDDQ are connected to the
module VDD.
VDDSPD Supply Temperature sensor/SPD EEPROM power supply: 3.0–3.6V.
VREFCA Supply Reference voltage: Control, command, and address VDD/2.
VREFDQ Supply Reference voltage: DQ, DM VDD/2.
VSS Supply Ground.
VTT Supply Termination voltage: Used for control, command, and address VDD/2.
NC – No connect: These pins are not connected on the module.
NF – No function: These pins are connected within the module, but provide no functional-
ity.

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 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM RDIMM
DQ Map

DQ Map

Table 7: Component-to-Module DQ Map (PCB 0757 R/C-J), Front

Component Component
Reference Component Module Pin Reference Component Module Pin
Number DQ Module DQ Number Number DQ Module DQ Number
U1 0 2 9 U2 0 10 18
1 0 3 1 8 12
2 3 10 2 11 19
3 1 4 3 9 13
U3 0 18 27 U4 0 26 36
1 16 21 1 24 30
2 19 28 2 27 37
3 17 22 3 25 31
U5 0 CB2 45 U8 0 34 87
1 CB0 39 1 32 81
2 CB3 46 2 35 88
3 CB1 40 3 33 82
U9 0 42 96 U10 0 50 105
1 40 90 1 48 99
2 43 97 2 51 106
3 41 91 3 49 100
U11 0 58 114 U12 0 5 123
1 56 108 1 6 128
2 59 115 2 4 122
3 57 109 3 7 129
U13 0 13 132 U14 0 21 141
1 14 137 1 22 146
2 12 131 2 20 140
3 15 138 3 23 147
U15 0 29 150 U16 0 CB5 159
1 30 155 1 CB6 164
2 28 149 2 CB4 158
3 31 156 3 CB7 165
U17 0 37 201 U18 0 45 210
1 38 206 1 46 215
2 36 200 2 44 209
3 39 207 3 47 216

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 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM RDIMM
DQ Map

Table 7: Component-to-Module DQ Map (PCB 0757 R/C-J), Front (Continued)

Component Component
Reference Component Module Pin Reference Component Module Pin
Number DQ Module DQ Number Number DQ Module DQ Number
U19 0 53 219 U20 0 61 228
1 54 224 1 62 233
2 52 218 2 60 227
3 55 225 3 63 234

Table 8: Component-to-Module DQ Map (PCB 0757 R/C-J), Back

Component Component
Reference Component Module Pin Reference Component Module Pin
Number DQ Module DQ Number Number DQ Module DQ Number
U21 0 56 108 U22 0 48 99
1 58 114 1 50 105
2 57 109 2 49 100
3 59 115 3 51 106
U23 0 40 90 U24 0 32 81
1 42 96 1 34 87
2 41 91 2 33 82
3 43 97 3 35 88
U25 0 CB0 39 U26 0 24 30
1 CB2 45 1 26 36
2 CB1 40 2 25 31
3 CB3 46 3 27 37
U27 0 16 21 U28 0 8 12
1 18 27 1 9 18
2 17 22 2 10 13
3 19 28 3 11 19
U29 0 0 3 U30 0 62 233
1 2 9 1 61 228
2 1 4 2 63 234
3 3 10 3 60 227
U31 0 54 224 U32 0 46 215
1 53 219 1 45 210
2 55 225 2 47 216
3 52 218 3 44 209

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 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM RDIMM
DQ Map

Table 8: Component-to-Module DQ Map (PCB 0757 R/C-J), Back (Continued)

Component Component
Reference Component Module Pin Reference Component Module Pin
Number DQ Module DQ Number Number DQ Module DQ Number
U33 0 38 206 U34 0 CB6 164
1 37 201 1 CB5 159
2 39 207 2 CB7 165
3 36 200 3 CB4 158
U35 0 30 155 U36 0 22 146
1 29 150 1 21 141
2 31 156 2 23 147
3 28 149 3 20 140
U37 0 14 137 U38 0 6 128
1 13 132 1 5 123
2 15 138 2 7 129
3 12 131 3 4 122

Table 9: Component-to-Module DQ Map (PCB 1354 R/C-E2), Front

Component Component
Reference Component Module Pin Reference Component Module Pin
Number DQ Module DQ Number Number DQ Module DQ Number
U1 0 4 122 U2 0 11 19
1 6 128 1 9 13
2 5 123 2 10 18
3 7 129 3 8 12
U3 0 18 27 U4 0 26 36
1 16 21 1 24 30
2 19 28 2 27 37
3 17 22 3 25 31
U5 0 CB2 45 U8 0 35 88
1 CB0 39 1 33 82
2 CB3 46 2 34 87
3 CB1 40 3 32 81
U9 0 42 96 U10 0 49 100
1 41 91 1 50 105
2 43 97 2 51 106
3 40 90 3 48 99

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 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM RDIMM
DQ Map

Table 9: Component-to-Module DQ Map (PCB 1354 R/C-E2), Front (Continued)

Component Component
Reference Component Module Pin Reference Component Module Pin
Number DQ Module DQ Number Number DQ Module DQ Number
U11 0 56 108 U12 0 2 9
1 59 115 1 1 4
2 57 109 2 3 10
3 58 114 3 0 3
U13 0 12 131 U14 0 21 141
1 14 137 1 23 147
2 13 132 2 20 140
3 15 138 3 22 146
U15 0 29 150 U16 0 CB5 159
1 30 155 1 CB7 165
2 28 149 2 CB4 158
3 31 156 3 CB6 164
U17 0 36 200 U18 0 46 215
1 39 207 1 45 210
2 37 201 2 47 216
3 38 206 3 44 209
U19 0 53 219 U20 0 63 234
1 55 225 1 61 228
2 52 218 2 62 223
3 54 224 3 60 227

Table 10: Component-to-Module DQ Map (PCB 1354 R/C-E2), Back

Component Component
Reference Component Module Pin Reference Component Module Pin
Number DQ Module DQ Number Number DQ Module DQ Number
U21 0 59 115 U22 0 50 105
1 56 108 1 49 100
2 58 114 2 48 99
3 57 109 3 51 106
U23 0 41 91 U24 0 33 82
1 42 96 1 35 88
2 40 90 2 32 81
3 43 97 3 34 87

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 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM RDIMM
DQ Map

Table 10: Component-to-Module DQ Map (PCB 1354 R/C-E2), Back (Continued)

Component Component
Reference Component Module Pin Reference Component Module Pin
Number DQ Module DQ Number Number DQ Module DQ Number
U26 0 CB0 39 U27 0 24 30
1 CB2 45 1 26 36
2 CB1 40 2 25 31
3 CB3 46 3 27 37
U28 0 16 21 U29 0 9 13
1 18 27 1 11 19
2 17 22 2 8 12
3 19 28 3 10 18
U30 0 6 128 U31 0 61 228
1 4 122 1 63 234
2 7 129 2 60 227
3 5 123 3 62 233
U32 0 55 225 U33 0 45 210
1 53 219 1 46 215
2 54 224 2 44 209
3 52 218 3 47 216
U34 0 39 207 U35 0 CB7 165
1 36 200 1 CB5 159
2 38 206 2 CB6 164
3 37 201 3 CB4 158
U36 0 30 155 U37 0 23 147
1 29 150 1 21 141
2 31 156 2 22 146
3 28 149 3 20 140
U38 0 14 137 U39 0 1 4
1 12 131 1 2 9
2 15 138 2 0 3
3 13 132 3 3 10

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 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM RDIMM
Functional Block Diagram

Functional Block Diagram

Figure 3: Functional Block Diagram (PCB 0757, R/C-J)

VSS U7
RS0#
RS1# S0# R
DQS0 DQS9 RS0#: Rank 0
DQS0# DQS9# S1# e RS1#: Rank 1
DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS# BA[2:0] g RBA[2:0]: DDR3 SDRAM
DQ0 DQ DQ DQ4 DQ DQ A[15:0] i RA[13:0]: DDR3 SDRAM
DQ1 DQ U1 DQ U29 DQ5 DQ U12 DQ U38 RAS# s RRAS#: DDR3 SDRAM
DQ2 DQ DQ DQ6 DQ DQ
CAS# t RCAS#: DDR3 SDRAM
DQ3 DQ DQ DQ7 DQ DQ
ZQ ZQ
WE# e RWE#: DDR3 SDRAM
VSS ZQ ZQ VSS
DQS1 DQS10 CKE0 r RCKE0: Rank 0
VSS VSS
DQS1# DQS10# CKE1 RCKE1: Rank 1
DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS# ODT0
a RODT0: Rank 0
DQ8 DQ DQ DQ12 DQ DQ
ODT1 RODT1: Rank 1
DQ9 DQ U2 DQ U28 DQ13 DQ U13 DQ U37 n
Par_In Err_Out#
DQ10 DQ DQ DQ14 DQ DQ d
DQ11 DQ DQ DQ15 DQ DQ
ZQ ZQ CK0 CK
VSS ZQ VSS ZQ
P DDR3 SDRAM
DQS2 VSS DQS11 VSS CK0#
L CK#
DQS2# DQS11#
DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS# RESET# L
DQ16 DQ DQ DQ20 DQ DQ
U27 U36 DDR3 SDRAM
DQ17 DQ U3 DQ DQ21 DQ U14 DQ
DQ18 DQ DQ DQ22 DQ DQ
DQ19 DQ DQ DQ23 DQ DQ
VSS ZQ ZQ VSS ZQ ZQ Rank 0: U1–U5, U8–U20
DQS3 VSS DQS12 VSS Rank 1: U21–U38
DQS3# DQS12#
DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS# VDDSPD Temperature sensor/
DQ24 DQ DQ DQ28 DQ DQ SPD EEPROM
DQ25 DQ U4 DQ U26 DQ29 DQ U15 DQ U35 VDD DDR3 SDRAM
DQ26 DQ DQ DQ30 DQ DQ
DQ27 DQ DQ DQ31 DQ DQ VTT DDR3 SDRAM
VSS ZQ ZQ VSS ZQ ZQ
VREFCA DDR3 SDRAM
DQS8 VSS DQS17 VSS
DQS8# DQS17#
DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS# VREFDQ DDR3 SDRAM
CB0 DQ DQ CB4 DQ DQ
VSS DDR3 SDRAM
CB1 DQ U5 DQ U25 CB5 DQ U16 DQ U34
CB2 DQ DQ CB6 DQ DQ
CB3 DQ DQ CB7 DQ DQ
VSS ZQ ZQ VSS ZQ ZQ
DQS4 VSS DQS13 VSS
DQS4# DQS13#
DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS# Clock, control, command, and address line terminations:
DQ32 DQ DQ DQ36 DQ DQ
DQ33 DQ U8 DQ U24 DQ37 DQ U17 DQ U33 DDR3
DQ34 DQ DQ DQ38 DQ DQ
SDRAM
DQ35 DQ DQ DQ39 DQ DQ RS#[1:0], RBA[2:0], RA[13:0],
VSS ZQ ZQ VSS ZQ ZQ RRAS#, RCAS#, RWE# VTT
DQS5 DQS14
RCKE[1:0], RODT[1:0]
VSS VSS
DQS5# DQS14# DDR3
DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS#
SDRAM
DQ40 DQ DQ DQ44 DQ DQ
DQ41 DQ U9 DQ U23 DQ45 DQ U18 DQ U32 CK VDD
DQ42 DQ DQ DQ46 DQ DQ CK#
DQ43 DQ DQ DQ47 DQ DQ
VSS ZQ ZQ VSS ZQ ZQ

DQS6 VSS DQS15 VSS

DQS6# DQS15# U6
DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS#
DQ48 DQ DQ DQ52 DQ DQ Temperature sensor/
DQ49 DQ U10 DQ U22 DQ53 DQ U19 DQ U31 SCL SPD EEPROM SDA
DQ50 DQ DQ DQ54 DQ DQ
DQ51 DQ DQ DQ55 DQ DQ EVT A0 A1 A2
VSS ZQ ZQ VSS ZQ ZQ SA0 SA1 SA2
DQS7 VSS DQS16 VSS EVENT#
DQS7# DQS16#
DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS#
DQ56 DQ DQ DQ60 DQ DQ
DQ57 DQ U11 DQ U21 DQ61 DQ U20 DQ U30
DQ58 DQ DQ DQ62 DQ DQ
DQ59 DQ DQ DQ63 DQ DQ
VSS ZQ ZQ VSS ZQ ZQ
VSS VSS

Note: 1. The ZQ ball on each DDR3 component is connected to an external 240Ω ±1% resistor
that is tied to ground. It is used for the calibration of the component’s ODT and output
driver.

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 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM RDIMM
Functional Block Diagram

Figure 4: Functional Block Diagram (PCB 1354, R/C-E2)

VSS
RS0#
RS1# U7
DQS0 DQS9
DQS0# DQS9#
DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS# S0# R RS0#: Rank 0
DQ0 DQ DQ DQ4 DQ DQ S1# e RS1#: Rank 1
DQ1 DQ U12 DQ U39 DQ5 DQ U1 DQ U30 BA[2:0] g RBA[2:0]: DDR3 SDRAM
DQ2 DQ DQ DQ6 DQ DQ A[15:0] i RA[13:0]: DDR3 SDRAM
DQ3 DQ DQ DQ7 DQ DQ RAS# s RRAS#: DDR3 SDRAM
Vss ZQ ZQ Vss ZQ ZQ CAS# t RCAS#: DDR3 SDRAM
DQS1 VSS DQS10 VSS WE# e RWE#: DDR3 SDRAM
DQS1# DQS10#
DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS# CKE0 r RCKE0: Rank 0
DQ8 DQ DQ DQ12 DQ DQ CKE1 RCKE1: Rank 1
DQ9 DQ U2 DQ U29 DQ13 DQ U13 DQ U38 ODT0
a RODT0: Rank 0
DQ10 DQ DQ DQ14 DQ DQ ODT1 RODT1: Rank 1
DQ11 DQ DQ DQ15 DQ DQ n
Par _In Err _Out #
Vss ZQ ZQ Vss ZQ ZQ d
DQS2 VSS DQS11 VSS CK
CK0
DQS2# DQS11# P DDR3 SDRAM
DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS# CK0#
L CK#
DQ16 DQ DQ DQ20 DQ DQ
RESET# L
DQ17 DQ U3 DQ U28 DQ21 DQ U14 DQ U37
DQ18 DQ DQ DQ22 DQ DQ
DDR3 SDRAM
DQ19 DQ DQ DQ23 DQ DQ
Vss ZQ ZQ Vss ZQ ZQ
DQS3 VSS DQS12 VSS
DQS3# DQS12# U6
DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS#
DQ24 DQ DQ DQ28 DQ DQ Temperature sensor/
DQ25 DQ U4 DQ U27 DQ29 DQ U15 DQ U36 SCL SPD EEPROM SDA
DQ26 DQ DQ DQ30 DQ DQ
DQ27 DQ DQ DQ31 DQ DQ EVT A0 A1 A2
Vss ZQ ZQ Vss ZQ ZQ
SA0 SA1 SA2
DQS8 VSS DQS17 VSS EVENT#
DQS8# DQS17#
DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS#
CB0 DQ DQ CB4 DQ DQ Rank 0: U1–U5, U12–U16, U21–U24, U31–U34
CB1 DQ U5 DQ U26 CB5 DQ U16 DQ U35 Rank 1: U8–U11, U17–U20, U26–U30, U35–U39
CB2 DQ DQ CB6 DQ DQ
CB3 DQ DQ CB7 DQ DQ Clock, control, command, and address line terminations:
Vss ZQ ZQ Vss ZQ ZQ
DQS4 VSS DQS13 VSS DDR3
DQS4# DQS13#
DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS# RS#[1:0], RCKE[1:0], RA[15:0], SDRAM
DQ32 DQ DQ DQ36 DQ DQ RRAS#, RCAS#, RWE#, VTT
DQ33 DQ U24 DQ U8 DQ37 DQ U34 DQ U17 RODT[1:0], RBA[2:0]
DQ34 DQ DQ DQ38 DQ DQ
DQ DQ
DDR3
DQ35 DQ DQ39 DQ
Vss ZQ ZQ Vss ZQ ZQ SDRAM
DQS5 VSS DQS14 VSS CK VDD
DQS5# DQS14# CK#
DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS#
DQ40 DQ DQ DQ44 DQ DQ
DQ41 DQ U23 DQ U9 DQ45 DQ U33 DQ U18
DQ42 DQ DQ DQ46 DQ DQ
DQ43 DQ DQ DQ47 DQ DQ VDDSPD Temperature sensor/
Vss ZQ ZQ Vss ZQ ZQ SPD EEPROM
VSS VDD DDR3 SDRAM
DQS6 VSS DQS15
DQS6# DQS15# VTT
DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS#
DDR3 SDRAM
DQ48 DQ DQ DQ52 DQ DQ
VREF CA DDR3 SDRAM
DQ49 DQ U22 DQ U10 DQ53 DQ U32 DQ U19
DQ50 DQ DQ DQ54 DQ DQ
VREF DQ DDR3 SDRAM
DQ51 DQ DQ DQ55 DQ DQ
Vss ZQ ZQ Vss ZQ ZQ VSS DDR3 SDRAM
DQS7 VSS DQS16 VSS
DQS7# DQS16#
DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS# DM CS# DQS DQS#
DQ56 DQ DQ DQ60 DQ DQ
DQ57 DQ U21 DQ U11 DQ61 DQ U31 DQ U20
DQ58 DQ DQ DQ62 DQ DQ
DQ59 DQ DQ DQ63 DQ DQ
Vss ZQ ZQ Vss ZQ ZQ
VSS Vss

Note: 1. The ZQ ball on each DDR3 component is connected to an external 240Ω ±1% resistor
that is tied to ground. It is used for the calibration of the component’s ODT and output
driver.

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 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM RDIMM
General Description

General Description
DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory mod-
ules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM mod-
ules use DDR architecture to achieve high-speed operation. DDR3 architecture is essen-
tially an 8n-prefetch architecture with an interface designed to transfer two data words
per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM mod-
ule effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the inter-
nal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers
at the I/O pins.
DDR3 modules use two sets of differential signals: DQS, DQS# to capture data and CK
and CK# to capture commands, addresses, and control signals. Differential clocks and
data strobes ensure exceptional noise immunity for these signals and provide precise
crossing points to capture input signals.

Fly-By Topology
DDR3 modules use faster clock speeds than earlier DDR technologies, making signal
quality more important than ever. For improved signal quality, the clock, control, com-
mand, and address buses have been routed in a fly-by topology, where each clock, con-
trol, command, and address pin on each DRAM is connected to a single trace and ter-
minated (rather than a tree structure, where the termination is off the module near the
connector). Inherent to fly-by topology, the timing skew between the clock and DQS sig-
nals can be easily accounted for by using the write-leveling feature of DDR3.

Registering Clock Driver Operation

Registered DDR3 SDRAM modules use a registering clock driver device consisting of a
register and a phase-lock loop (PLL). The device complies with the JEDEC standard
"Definition of the SSTE32882 Registering Clock Driver with Parity and Quad Chip Se-
lects for DDR3 RDIMM Applications."
The register section of the registering clock driver latches command and address input
signals on the rising clock edge. The PLL section of the registering clock driver receives
and redrives the differential clock signals (CK, CK#) to the DDR3 SDRAM devices. The
register(s) and PLL reduce clock, control, command, and address signals loading by iso-
lating DRAM from the system controller.

Parity Operations
The registering clock driver includes an even parity function for checking parity. The
memory controller accepts a parity bit at the Par_In input and compares it with the data
received on A[15:0], BA[2:0], RAS#, CAS#, and WE#. Valid parity is defined as an even
number of ones (1s) across the address and command inputs (A[15:0], BA[2:0], RAS#,
CAS#, and WE#) combined with Par_In. Parity errors are flagged on Err_Out#.
Address and command parity is checked during all DRAM operations and during con-
trol word WRITE operations to the registering clock driver. For SDRAM operations, the
address is still propagated to the SDRAM even when there is a parity error. When writ-
ing to the internal control words of the registering clock driver, the write will be ignored
if parity is not valid. For this reason, systems must connect the Par_In pins on the
DIMM and provide correct parity when writing to the registering clock driver control
word configuration registers.

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 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM RDIMM
Temperature Sensor with Serial Presence-Detect EEPROM

Temperature Sensor with Serial Presence-Detect EEPROM

Thermal Sensor Operations
The temperature from the integrated thermal sensor is monitored and converts into a
digital word via the I2C bus. System designers can use the user-programmable registers
to create a custom temperature-sensing solution based on system requirements. Pro-
gramming and configuration details comply with JEDEC standard No. 21-C page 4.7-1,
"Definition of the TSE2002av, Serial Presence Detect with Temperature Sensor."

Serial Presence-Detect EEPROM Operation

DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to comply with JE-
DEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAM Mod-
ules." These bytes identify module-specific timing parameters, configuration informa-
tion, and physical attributes. The remaining 128 bytes of storage are available for use by
the customer. System READ/WRITE operations between the master (system logic) and
the slave EEPROM device occur via a standard I2C bus using the DIMM’s SCL (clock)
SDA (data), and SA (address) pins. Write protect (WP) is connected to V SS, permanently
disabling hardware write protection. For further information refer to Micron technical
note TN-04-42, "Memory Module Serial Presence-Detect."

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 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM RDIMM
Electrical Specifications

Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other condi-
tions outside those indicated in each device's data sheet is not implied. Exposure to ab-
solute maximum rating conditions for extended periods may adversely affect reliability.

Table 11: Absolute Maximum Ratings

Symbol Parameter Min Max Units

VDD VDD supply voltage relative to VSS –0.4 1.975 V
VIN, VOUT Voltage on any pin relative to VSS –0.4 1.975 V

Table 12: Operating Conditions

Symbol Parameter Min Nom Max Units Notes

VDD VDD supply voltage 1.425 1.5 1.575 V
VREFCA(DC) Input reference voltage command/address bus 0.49 × VDD 0.5 × VDD 0.51 × VDD V
VREFDQ(DC) I/O reference voltage DQ bus 0.49 × VDD 0.5 × VDD 0.51 × VDD V
IVTT Termination reference current from VTT –600 – 600 mA
VTT Termination reference voltage (DC) – command/ 0.49 × VDD - 0.5 × VDD 0.51 × VDD + V 1
address bus 20mV 20mV
II Input leakage current; Address in- – – – µA 2
Any input 0V ≤ VIN ≤ VDD; puts, RAS#,
VREF input 0V ≤ VIN ≤ 0.95V CAS#, WE#,
(All other pins not under test = S#, CKE, ODT,
0V) BA, CK, CK#
DM –4 0 4
IOZ Output leakage current; DQ, DQS, –10 0 10 µA
0V ≤ VOUT ≤ VDD; DQS#
DQ and ODT are
disabled; ODT is HIGH
IVREF VREF supply leakage current; –36 0 36 µA
VREFDQ = VDD/2 or VREFCA = VDD/2
(All other pins not under test = 0V)
TA Module ambient Commercial 0 – 70 °C 3, 4
operating temperature
TC DDR3 SDRAM component case Commercial 0 – 95 °C 3, 4, 5
operating temperature

Notes: 1. VTT termination voltage in excess of the stated limit will adversely affect the command
and address signals’ voltage margin and will reduce timing margins.
2. Inputs are terminated to VDD/2. Input current is dependent on terminating resistance se-
lected in register.
3. TA and TC are simultaneous requirements.
4. For further information, refer to technical note TN-00-08: “Thermal Applications,”
available on Micron’s Web site.
5. The refresh rate is required to double when 85°C < TC ≤ 95°C.

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 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM RDIMM
DRAM Operating Conditions

DRAM Operating Conditions

Recommended AC operating conditions are given in the DDR3 component data sheets.
Component specifications are available on Micron’s web site. Module speed grades cor-
relate with component speed grades, as shown below.

Table 13: Module and Component Speed Grades

DDR3 components may exceed the listed module speed grades; module may not be available in all listed speed grades
Module Speed Grade Component Speed Grade
-2G1 -093
-1G9 -107
-1G6 -125
-1G4 -15E
-1G1 -187E
-1G0 -187
-80C -25E
-80B -25

Design Considerations
Simulations
Micron memory modules are designed to optimize signal integrity through carefully de-
signed terminations, controlled board impedances, routing topologies, trace length
matching, and decoupling. However, good signal integrity starts at the system level.
Micron encourages designers to simulate the signal characteristics of the system's
memory bus to ensure adequate signal integrity of the entire memory system.
Power
Operating voltages are specified at the DRAM, not at the edge connector of the module.
Designers must account for any system voltage drops at anticipated power levels to en-
sure the required supply voltage is maintained.

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 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM RDIMM
IDD Specifications

IDD Specifications

Table 14: DDR3 IDD Specifications and Conditions – 4GB (Die Revision G)
Values are for the MT41J256M4 DDR3 SDRAM only and are computed from values specified in the 1Gb (256 Meg x 4) com-
ponent data sheet
Parameter Symbol 1600 1333 1066 Units
Operating current 0: One bank ACTIVATE-to-PRE- IDD01 1476 1386 1296 mA
CHARGE
Operating current 1: One bank ACTIVATE-to-READ- IDD11 1836 1746 1656 mA
to-PRECHARGE
Precharge power-down current: Slow exit IDD2P02 432 432 432 mA
Precharge power-down current: Fast exit IDD2P1 2 1080 1080 900 mA
Precharge quiet standby current IDD2Q2 1440 1260 1260 mA
Precharge standby current IDD2N2 1620 1440 1260 mA
Precharge standby ODT current IDD2NT 2 1206 1116 1026 mA
Active power-down current IDD3P 2 1260 1080 1080 mA
Active standby current IDD3N2 1620 1440 1440 mA
1
Burst read operating current IDD4R 2736 2466 2106 mA
1
Burst write operating current IDD4W 2826 2466 2196 mA
Refresh current IDD5B 1 3276 3186 3096 mA
Self refresh temperature current: MAX TC = 85°C IDD62 288 288 288 mA
Self refresh temperature current (SRT-enabled): MAX IDD6ET 2 360 360 360 mA
TC = 95°C
1
All banks interleaved read current IDD7 4626 4446 3726 mA
1
Reset current IDD8 504 504 504 mA

Notes: 1. One module rank in the active IDD, the other rank in IDD2P0 (slow exit).
2. All ranks in this IDD condition.

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 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM RDIMM
IDD Specifications

Table 15: DDR3 IDD Specifications and Conditions – 4GB (Die Revision J)
Values are for the MT41J256M4 DDR3 SDRAM only and are computed from values specified in the 1Gb (256 Meg x 4) com-
ponent data sheet
Parameter Symbol 1600 1333 1066 Units
Operating current 0: One bank ACTIVATE-to-PRE- IDD01 972 954 918 mA
CHARGE
Operating current 1: One bank ACTIVATE-to-READ- IDD11 1224 1188 1116 mA
to-PRECHARGE
Precharge power-down current: Slow exit IDD2P02 432 432 432 mA
Precharge power-down current: Fast exit IDD2P1 2 540 540 540 mA
Precharge quiet standby current IDD2Q2 792 792 792 mA
Precharge standby current IDD2N2 828 828 828 mA
Precharge standby ODT current IDD2NT 2 828 792 738 mA
Active power-down current IDD3P 2 612 612 615 mA
Active standby current IDD3N2 1260 1188 1116 mA
1
Burst read operating current IDD4R 2016 1800 1548 mA
1
Burst write operating current IDD4W 2070 1854 1638 mA
Refresh current IDD5B 1 3096 3096 3096 mA
Self refresh temperature current: MAX TC = 85°C IDD62 432 432 432 mA
Self refresh temperature current (SRT-enabled): MAX IDD6ET 2 540 540 540 mA
TC = 95°C
1
All banks interleaved read current IDD7 3150 3042 2520 mA
1
Reset current IDD8 504 504 504 mA

Notes: 1. One module rank in the active IDD, the other rank in IDD2P0 (slow exit).
2. All ranks in this IDD condition.

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 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM RDIMM
Registering Clock Driver Specifications

Registering Clock Driver Specifications

Table 16: Registering Clock Driver Electrical Characteristics

SSTE32882 devices or equivalent
Parameter Symbol Pins Min Nom Max Units
DC supply voltage VDD – 1.425 1.5 1.575 V
DC reference voltage VREF – 0.49 × VDD - 20mV 0.5 × VDD 0.51 × VDD + 20mV V
DC termination VTT – 0.49 × VDD - 20mV 0.5 × VDD 0.51 × VDD + 20mV V
voltage
AC high-level input VIH(AC) Control, command, VREF + 175mV – VDD + 400mV V
voltage address
AC low-level input VIL(AC) Control, command, –0.4 – VREF - 175mV V
voltage address
DC high-level input VIH(DC) Control, command, VREF + 100mV – VDD + 0.4 V
voltage address
DC low-level input VIL(DC) Control, command, –0.4 – VREF - 100mV V
voltage address
High-level input VIH(CMOS) RESET#, MIRROR 0.65 × VDD – VDD V
voltage
Low-level input VIL(CMOS) RESET#, MIRROR 0 – 0.35 × VDD V
voltage
Differential input VIX(AC) CK, CK#, FBIN, FBIN# 0.5 × VDD - 175mV 0.5 × VDD 0.5 × VDD + 175mV V
crosspoint voltage
range
Differential input VID(AC) CK, CK# 350 – VDD + TBD mV
voltage
High-level output IOH Err_Out# – – TBD mA
current
Low-level output IOL Err_Out# TBD – TBD mA
current

Note: 1. Timing and switching specifications for the register listed are critical for proper opera-
tion of the DDR3 SDRAM RDIMMs. These are meant to be a subset of the parameters for
the specific device used on the module.

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 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM RDIMM
Temperature Sensor with Serial Presence-Detect EEPROM

Temperature Sensor with Serial Presence-Detect EEPROM

The temperature sensor continuously monitors the module's temperature and can be
read back at any time over the I2C bus shared with the SPD EEPROM. Refer to JEDEC
standard No. 21-C page 4.7-1, "Definition of the TSE2002av, Serial Presence Detect with
Temperature Sensor."

Serial Presence-Detect
For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD.

Table 17: Temperature Sensor with SPD EEPROM Operating Conditions

Parameter/Condition Symbol Min Max Units

Supply voltage VDDSPD 3.0 3.6 V
Supply current: VDD = 3.3V IDD – 2.0 mA
Input high voltage: Logic 1; SCL, SDA VIH VDDSPD x 0.7 VDDSPD + 1 V
Input low voltage: Logic 0; SCL, SDA VIL –0.5 VDDSPD x 0.3 V
Output low voltage: IOUT = 2.1mA VOL – 0.4 V
Input current IIN –5.0 5.0 µA
Temperature sensing range – –40 125 °C
Temperature sensor accuracy (class B) – –1.0 1.0 °C

Table 18: Temperature Sensor and SPD EEPROM Serial Interface Timing

Parameter/Condition Symbol Min Max Units

Time bus must be free before a new transition can tBUF 4.7 – µs
start
SDA fall time tF 20 300 ns
SDA rise time tR – 1000 ns
Data hold time tHD:DAT 200 900 ns
Start condition hold time tH:STA 4.0 – µs
Clock HIGH period tHIGH 4.0 50 µs
Clock LOW period tLOW 4.7 – µs
SCL clock frequency tSCL 10 100 kHz
Data setup time tSU:DAT 250 – ns
Start condition setup time tSU:STA 4.7 – µs
Stop condition setup time tSU:STO 4.0 – µs

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 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM RDIMM
Temperature Sensor with Serial Presence-Detect EEPROM

EVENT# Pin
The temperature sensor also adds the EVENT# pin (open-drain). Not used by the SPD
EEPROM, EVENT# is a temperature sensor output used to flag critical events that can be
set up in the sensor’s configuration register.
EVENT# has three defined modes of operation: interrupt mode, compare mode, and
critical temperature mode. Event thresholds are programmed in the 0x01 register using
a hysteresis. The alarm window provides a comparison window, with upper and lower
limits set in the alarm upper boundary register and the alarm lower boundary register,
respectively. When the alarm window is enabled, EVENT# will trigger whenever the
temperature is outside the MIN or MAX values set by the user.
The interrupt mode enables software to reset EVENT# after a critical temperature
threshold has been detected. Threshold points are set in the configuration register by
the user. This mode triggers the critical temperature limit and both the MIN and MAX of
the temperature window.
The compare mode is similar to the interrupt mode, except EVENT# cannot be reset by
the user and returns to the logic HIGH state only when the temperature falls below the
programmed thresholds.
Critical temperature mode triggers EVENT# only when the temperature has exceeded
the programmed critical trip point. When the critical trip point has been reached, the
temperature sensor goes into comparator mode, and the critical EVENT# cannot be
cleared through software.

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 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM RDIMM
Module Dimensions

Module Dimensions

Figure 5: 240-Pin DDR3 RDIMM (PCB 0757, R/C-J)

Front view 4.0 (0.157)

133.50 (5.256) MAX
133.20 (5.244)
0.9 (0.035) TYP

U6
0.5 (0.02) R U1 U2 U3 U4 U5 U8 U9 U10 U11
(4X) 30.5 (1.2)
29.85 (1.175)
0.75 (0.03) R
(8X) U7
23.3 (0.92)
U12 U13 U14 U15 U16 U17 U18 U19 U20 TYP
2.5 (0.098) D 17.3 (0.68)
(2X) TYP

2.3 (0.091) TYP

Pin 1 0.76 (0.03) R 1.37 (0.054)
2.2 (0.087) TYP 1.17 (0.046)
1.0 (0.039) 0.8 (0.031) 9.5 (0.374)
1.45 (0.057) TYP TYP TYP TYP
54.68 (2.15)
TYP Pin 120
123.0 (4.84)
TYP
15.0 (0.59)
TYP
1.0 (0.039) R (8X)
(4X)
Back view
5.1 (0.2) TYP
U21 U22 U23 U24 U25 U26 U27 U28 U29 3.1 (0.122) 2X TYP

U30 U31 U32 U33 U34 U35 U36 U37 U38

3.0 (0.118) 4X TYP

3.05 (0.12) TYP

Pin 240 5.0 (0.197) TYP Pin 121

71.0 (2.79) 47.0 (1.85)
TYP TYP
7.25 (0.285)
MAX*
With heat spreader
U6
U1 U2 U3 U4 U5 U8 U9 U10 U11

U7
U12 U13 U14 U15 U16 U17 U18 U19 U20

1.37 (0.054)
1.17 (0.046)

* At clip’s edge, MAX width is

U21 U22 U23 U24 U26 U27 U28 U29 U30 8.32mm (0.328in)

U30 U31 U32 U33 U34 U35 U36 U37 U38

Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only.

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 4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM RDIMM
Module Dimensions

Figure 6: 240-Pin DDR3 RDIMM (PCB 1354, R/C-E2)

Front view
4.0 (0.157)
133.50 (5.256) MAX
133.20 (5.244)

0.9 (0.035) TYP

U6
0.50 (0.02) R U1 U2 U3 U4 U5 U8 U9 U10 U11
(4X)
0.75 (0.03) R U7 30.50 (1.20)
(8X) 23.3 (0.92) 29.85 (1.175)
U12 U14 U16 U17 U19 TYP
2.50 (0.098) D U13 U15 U18 U20 17.3 (0.68)
(2X) TYP

2.30 (0.091) TYP

Pin 1 0.76 (0.030) R 1.37 (0.054)
2.20 (0.087) TYP 9.5 (0.374) 1.17 (0.046)
1.0 (0.039) 0.80 (0.031)
TYP TYP TYP
1.45 (0.057) TYP
54.68 (2.15) Pin 120
TYP
123.0 (4.84)
TYP
15.0 (0.59)
4X TYP
1.0 (0.039) R (8X)
Back view 45°, 4X

5.1 (0.2) TYP

U21 U22 U23 U24 U26 U27 U28 U29 U30 3.1 (0.122) 2X TYP

U32 U34 U35 U37 U39

U31 U33 U36 U38 3.0 (0.118) 4X TYP

3.05 (0.12) TYP

Pin 240 Pin 121

5.0 (0.197) TYP
71.0 (2.79) 47.0 (1.85)
TYP TYP

Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000

www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.

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