SEVEN LEVEL INVERTER WITH

(m-1) * (m-2). Where n isNEAREST

the number of levels
[10].This number represents a quadratic increase in
LEVEL CONTROL
m.
Megha S Varna Jenson Jose
M-tech, Research Scholar Dept. of EEE Assistant Professor, Dept. of EEE
Jyothi Engineering College, Thrissur, Kerala, India Jyothi Engineering College, Thrissur, Kerala, India
[email protected] [email protected]

Abstract- Multilevel inverters are commonly used for

high power applications. The structure of a multilevel
inverter is to synthesize sinusoidal waveform from
several levels of voltages. This paper deals with a
novel seven level cascaded multilevel inverter. Almost
all the drawbacks of the conventional multilevel
inverters is rectified by the proposed topology. This
topology uses less number of switches as compared
with conventional topology, where it reduces the
complexity and overall size of the system which in
turn reduces the harmonics and cost of the entire
system. Fewer switches will be conducting for specific
time intervals so switching loss is also reduced in the
proposed topology. A seven level inverter simulation
is carried with the implementation of nearest level
control. The proposal is validated by extensive
simulation studies.
Index Terms— multilevel inverter, cascaded
multilevel inverter, Total Harmonic Distortion
(THD). Fig.1. m-level cascaded multilevel inverter [9]

I. INTRODUCTION
Power electronic engineers have paid great
attention to multilevel inverters as a new kind of When m is high the number of diodes required will
power converter because of their promising make the system impractical to implement
applications in industrial drives and power systems. [6].Flying capacitorwas proposed by Meynardand
A multilevel inverter is a power electronic interface Fochin 1992. Main problem of flying capacitor
that synthesizes a desired output voltage from multilevel inverter is voltage balancing.In flying
several DC voltages as inputs. Batteries, fuel cells, capacitor topology, As the number of level
solar cells, rectified wind turbines etc are used as increases number of capacitors also increases. So
DC voltage sources. A higher number of active increases the complexity and the unbalancing
semiconductor switches are used to perform the issues occurred.
power conversion in small voltage steps is the basic
Cascaded H-bridge multilevel inverter has been
concept of the multilevel inverter.
researched for high voltage applications since it has
The multilevel inverter was first introduced in advantages in number of components, high
1975. The term multilevel inverter is started with reliability, and modularity. This inverter can avoid
three level inverter. The Conventional multilevel extra clamping diodes or voltage balancing
topologies are Cascaded H-bridge inverters, capacitors[11],[9]. A single phase, m-level
Floating capacitors inverters and Diode clamped configuration of the cascaded multilevel inverter
inverters. Neutral point clamped converter (NPC) shown in the Fig.1. One of the demerits of cascade
which was introduced by Nabae[9]. In Neutral multilevel inverter is that as the number of level
point clamped multilevel inverter, depending on increases, the number of H-bridges also increases
number of levels required the number of switches [14]. This makes the modulation strategy more
and number of clamping diodes increases. complex, resulting in complex control to get a
Assuming that each blocking diode voltage rating better output voltage.
is the same as the active device voltage rating, the
Depending upon the voltage source used, Cascaded
number of diodes required for each phase will be
multilevel inverter are classified into two that’s are
symmetrical and asymmetrical Cascaded multilevel is that the left side in Fig. 2 generates the required
inverter [6]. In asymmetrical Cascaded multilevel output levels (without polarity) and the right side of
inverter dc voltages are in different proportion. So the circuit (H-bridge inverter) decides about the
the Inverters can be designed with different switch polarity of the output voltage.
technologies. To reduce the number of DC sources
in a symmetrical cascaded topology DC sources are The proposed system consists of a normal H bridge
inverter and some auxiliary switches. A stepped
replaced by the capacitors. It may cause voltage
waveform is generated at the output according to
balancing problem [7],[12]. Sun Pil Kim, proposed how the sources are being connected to the load.
a multilevel inverter with reduced number of The H Bridge is operated normally to generate
switches, in which the selection based on a set alternating voltage output. During positive half
target which can be either the minimum switches cycle, switches M1 and M2 are turned on and the
used or the minimum used dc voltage[17]. It also level selecting switches are operated to get
requires different voltage source values which are different voltage levels. To generate the negative
half cycle, switches M3 and M4 are conducting
defined according to the target selection. Another
while the level selecting switches are operated to
disadvantage of the topology is that the power get a staircase voltage at the output. To obtain the
switches and diodes also need to have a different first level, the dc source V1 must be connected to
rating which is a major drawback of the topology. the load. To generate the second level, both V1 and
V2 must be connected to the load. The rest of the
The number of high-frequency switches is sources are also connected in steps to the load in
increased in Reverse voltage (RV) topology, hence similar manner. The switches are controlled in such
reliability of the converter is decreased and the a way that respective sources are connected to the
switching loss is also more [1]. load during desired time intervals.
In the proposed topology the total switch count is
This paper presents a hybrid multilevel inverter, the 8 for a seven level multilevel inverter, in case of a
suggested topology requires less number of conventional cascaded multilevel inverter it would
components as compared to conventional be 12. Number of switches and gate driver circuits
topologies. Hence it reduces the installation area, reduced in this topology so reducing the
gate drivers needed, and consequently the cost of complexity of the overall circuit. It reduces the
the whole setup. It is also more efficient since the installation area and consequently the cost of the
inverter has a component which operates the whole setup.
switching power devices at line frequency. Nearest
level control is utilized to drive the multilevel
inverter and can be extended to any number of
voltage levels. The simulation results of the
proposed topology are also presented.

I. MODIFIED CASCADED MULTILEVEL

INVERTER

A. General Description

The proposed multilevel topology is a hybrid

multilevel inverter, which separates the output of
the multilevel inverter into two parts. One part is
named level generation part and it is responsible for
level generating in positive polarity. The other part
is called polarity generation part. The H-bridge is
responsible for generating the polarity of the output
voltage. H-bridge consisting of four switches and
these switches are operating at fundamental
frequency. The proposed seven levels inverter is
shown in Fig. 2. As can be seen, it requires eight
switches and three isolated sources. The main idea
of this proposed topology as a multilevel inverter Fig.2.modified cascaded multilevel inverter
 TABLE.I SWITCHING SEQUENCE OF THE
PROPOSED TOPOLOGY

switches S1 S2 S3 S4

levels
VDC OFF ON OFF ON
2VDC ON OFF OFF ON

3VDC ON OFF ON OFF

B. Switching Sequence

Switching sequences in the proposed

multilevel inverter are simpler as compared to
conventional topologies. There is no need to
control negative cycle so it does not generate
negative pulses. Thus, there is no need for extra Fig.3. modes of operation
conditions for controlling the negative voltage. In
table.1.shows the switching sequence of the Mode-3: In this mode, S4 is turned OFF and S3 is
proposed topology. In this, the switching transition turned ON. The output 3VDC is applied to the H-
is minimum during each mode transfer so there is a bridge. The switches which are conducting in the
reduction in the switching loss. H-bridge are M1 and M2.

C.Modes Of Operation Mode-0: It is a special mode which will develop a

zero voltage level at the output. This mode is
The output voltage of the proposed achieved with the help of H bridge.Nomally,M1
multilevel inverter has seven levels (VDC, and M2 will be conducting simultaneously to
2VDC,3VDC,0, -VDC,-2VDC,-3VDC) according to the generate the positive half cycle of the output. But if
switching states of the inverter. The output voltage the switching pulse to M2 is delayed for a small
changes its value from zero to maximum voltage time interval, the load inductance will try to
and the modes are same when the output changes maintain the current direction through it and as a
from maximum to zero. The four operating modes result, the current will flow through the anti parallel
are shown inFig.3.To produce a staircase voltage at diode of M3.During this freewheeling period, the
the output the switches must be turned ON and voltage across the load is zero. Therefore the load
OFF in a particular sequence, so that the voltage freewheeling can be utilized to generate a zero
sources will get connected to the load in a desired voltage level.
manner.
After reaching the maximum output, the level
Mode-1:The switches S2 and S4 are turned ON. The selection switches are operated in the reverse order
source voltage V1 is getting connected to the load to reach the zero level again. The operation of the
as shown in Fig.3. mode1.M1 and M2 are turned level selection switches are the same for both
ON to get the positive half cycle. All the other positive and negative half cycles of the output. The
switches are kept off. only difference is that instead of switches M1 and
M2, switches M3 and M4 are conducting in the H-
Mode-2: The switches S1 and S4 are on during this
bridge for generating the negative half cycle.
time duration and source voltage 2VDC is connected
to the load. All other switches are in OFF position
 II. CONTROL LOGIC
Continuous

v powergui

Instead of PWM method a simple control logic is Out1 g m

Out1
C E
used. In multiple carrier method for an m level Out2
IGBT/Diode Out1
Subsystem Subsystem3
inverter m-1 carriers are needed [2]-[5]. It can be

g
C
Subsystem2
IGBT/Diode2
seen from a sine wave that it takes different v1

g
C

C
m
E
durations if it is moving from one voltage level to IGBT/Diode4 IGBT/Diode5

E
Out1 g m
C E
Out2
+
IGBT/Diode1 -v
SeriesRLCBranch

g
C
Subsystem1
vdc VoltageMeasurem
Se
cnte2
op
IGBT/Diode3 Out1

m
E
Subsystem4

g
C

C
IGBT/Diode6 IGBT/Diode7

E
Fig.5. simulation model of proposed system with
nearest level control

Fig.4. Unequal step widths 40

30

another voltage level from Fig.4. So a sine wave is 20

taken and checked whether its amplitude is in
between two adjacent voltage levels. If so, the 10
V O LTA G E

corresponding source is connected to the load and 0

in similar way it is proceeded until all the source -10

voltages are connected to load.
-20

The duration of different levels at the output -30

changes each time, when the sine wave amplitude
-40
changes from one desired level to another, which 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04

makes the staircase output much more similar to a TIME

sine wave. Fig.6. Voltage waveform of modified topology

III. MATLAB/SIMULINK MODEL AND

SIMULATION RESULTS
The simulation case study has been carried out
Fundamental (50Hz) = 40 , THD= 13.66%
software to validate the result. Fig.5.Shows the
simulation model of the proposed topology. To 8
generate the seven level output voltage, Eight
M a g (% o f F u n d a m e n t a l)

IGBTs and three DC power source of 12 Volts are 6

used. Pulses are generated by using nearest level
control method. The simulated Output voltage is
4
shown in Fig.6. and the harmonic spectrum was
analysed using the FFT Window in
MATLAB/Simulink. 2

0
0 500 1000 1500
Frequency (Hz)

Fig.7. FFT analysis with nearest level control

 0.25

Fundamental (50Hz) = 42.31 , THD= 21.71%

0.2

0.15

Mag (% of Fundamental)
15
c u rre n t

0.1

0.05 10

5
-0.05

-0.1
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
0
Time 0 500 1000 1500
Frequency (Hz)
Fig.8.Current waveform of the proposed topology

Fundamental (50Hz) = 0.1252 , THD= 4.13%

100
Fig.11. FFT analysis with multicarrier PWM
control
Mag (% of Fundamental)

80

60
TheFig.10.shows the simulated model of the
proposed topology with conventional multicarrier
40
PWM method. A carrier frequency of 5 kHz is
20 generated and compared with a reference sine wave
of 50 Hz. its FFT analysis is also shown in Fig.11.
0
0 500 1000 1500
Frequency (Hz)
Total harmonic distortion (THD) of the proposed
topology with multiple carrier method is 21.71%.
Fig.9. FFT analysis of current waveform By comparing Fig.7.and Fig.11. it can be seen that
nearest level control method is better than multiple
Total harmonic distortion (THD)of the proposed carrier method .
topology is 13.66% without using the LC filter.The
current waveform of the proposed multilevel IV. COMPARISON
inverter without output filter is shown in Fig.8. and
corresponding FFT analysis is shows in Fig.9. The Compared to other topologies the proposed
resulting current THD was 4.13%, which complies topology has many advantages. The proposed
topology does not have any voltage unbalancing
with the IEEE 519 harmonic standard
problems as in flying capacitor type topology. It
has much more reduced no of switches compared to
cascaded topology. A single H bridge can generate
3 voltage levels: +VDC,0, -VDC. Therefore 7-level
Continuous
multilevel inverter requires 12 switches in cascaded
v powergui
topology.The proposed topology requires 8
|u|
Logical
switches only. It does not need any
Abs g Operator

C
m

E
Out1 Out1
auxillarydevices like clamping capacitor or
clamping diodes.The comparison between different
Sine Wave
IGBT/Diode Subsystem4 Subsystem3
>=
topology is shown Table II
g
C

Relational
IGBT/Diode2
% reduction in switches = 33.3%
Repeating
Operator v1
Sequence2
g

g
C

C
m
E

IGBT/Diode4 IGBT/Diode5
Since there is a considerable reduction in number
E

2
of switches, the various losses associated with the
Constant1 Scope1 g m
1 C E switches will also be reduced.
+v
Constant IGBT/Diode1 -
Series RLC Branch
g
C

vdc Voltage Measurement

Scope2
THD of the seven level multilevel inverter with
>=
IGBT/Diode3 Out1
Relational
m

different control strategies are shown in Table III

E

Repeating Operator1 Repeating

Subsystem2
Sequence1 Sequence3
g

g
C

Logical IGBT/Diode6 IGBT/Diode7

Operator1
E

Scope3

Fig.10. simulation model of proposed system with

multicarrier PWM control
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