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A Simplified Nearest level control (NLC)

Voltage Balancing Method for Modular
Multilevel Converter (MMC)
Prafullachandra M. Meshram, Research Scholar, Vijay B. Borghate, Member, IEEE

Abstract- In this paper, a simplified nearest level control

balancing method for modular multilevel converter is presented. B. Symbols
The proposed method, neither requires individual sorting of the
sub module voltages nor the redundancy of the switching states. n Number of SM per arm.
Once, the sorting of the sub modules is done on the basis of the
number of the sub modules to be switched on, the identifications C SM capacitance.
of the sub modules can be carried out throughout the stages of LS Arm inductance.
the implementation of the this method. The proposed method VC SM capacitor voltage.
also does not require the individual sub module status in the gate
pulse generation stage. The gate logic in the presented method Vdc Pole- to- pole dc-bus voltage.
can be implemented with the help of the switching states of the
voltage levels. Those simplifications and removing of the some of Idc DC current.
the stages by the proposed balancing method may ease and lead
to the less processor time at the implementation level. The vj Voltage with respect to fictitious
pictorial presentation further helps in consolidating the point ‘o’ of phase-j (j=a, b, c).
understanding of the different stages of the method. Rigorous
simulations are carried out for open and one of the prominent ij Output current of phase- j
closed loop applications i.e. modular multilevel converter based (j=a, b, c).
HVDC to demonstrate the validity and effectiveness of the
proposed simplified balancing method under normal and vupj , vloj Total voltage of upper and lower
emergency conditions. arm of phase-j (j=a, b, c).
SM SM Total voltage of upper and lower
Index Terms—modular multilevel converter (MMC), sub vup , vlo SMs of phase-j (j=a, b, c).
module(SM), nearest level control (NLC) method, voltage source j j
converter high voltage direct current (VSC- HVDC)
iup , ilo Upper and lower arm current of
transmission. j j phase- j (j=a, b, c).

I. NOMENCLATURE izj Circulating current of phase-j

(j=a, b, c).
A. Abbreviations Instantaneous voltage of SM-1,
vc1up ⋯ vcnup
j j SM-2... ..SM-n of the upper arm of
CHB Cascaded H-Bridge. phase- j (j=a, b, c).
IGBT Insulated gate bipolar-transistor. Instantaneous voltage of SM-1,
MMC Modular multilevel converter.
vc1lo ⋯ vcnlo
j j SM-2... ..SM-n of the lower arm of
NLC Nearest level control. phase- j (j=a, b, c).
PWM Pulse width modulation. Sup , Slo Switching functions of upper and
PSPWM Phase shifted PWM. jk jk lower arm of phase- j (j=a, b, c) for
k=SM-1, SM-2...SM-n.
SM Sub module.
SHE Selective harmonic elimination.

Original manuscript submitted on Sept. 30, 2013; revised on Dec. 31, 2013
and Feb. 25, 2014; accepted on March 31, 2014. II. INTRODUCTION
P. M. Meshram is with Department of Electrical Engineering,
Yeshwantrao Chavan College of Engineering (YCCE), Nagpur, Maharashtra, Multilevel Inverters have presented an important
India - 441110. (e- mail: [email protected].) development in recent years to reach higher power with
V. B. Borghate is with Department of Electrical Engineering, increasing voltage levels [1-5]. Large numbers of multilevel
Visvesvaraya National Institute of Technology (VNIT), Nagpur, Maharashtra,
India- 440010 (e- mail: [email protected] ) inverters topology have been investigated but few of them are
practical for industrial applications [6-12]. Diode clamped and

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cascaded H-bridge (CHB) are the most preferred choices [13-

20]. For medium- voltage (2.3, 3.3 and 4.16kV) applications
three-level neutral-point clamped is the suitable topology, but
having the constrained of mass clamping and the voltage
imbalance of dc-link capacitors in extending its use to higher
voltage levels [14], [6-19]. For applications with voltage
higher than 6 kV, cascaded H-bridge multilevel inverters are
commonly used [15], [17], [20]. Isolated sources are required
in this topology. To generate individual voltage sources,
conventional method is to employ a multi-winding transformer
with the same number of isolated secondary windings, which
is huge and expensive.
The modular multilevel converter (MMC) topology has
recently drawn huge interest in high voltage applications [21-
25], [29-44]. It is first proposed by Marquardt and Lesnicar
[22] and is regarded as one of the next-generation high voltage
multilevel converters without line-frequency transformers
[29]. The modularity, voltage scalability and common dc bus
make MMC topology favourite for high voltage applications
[31-40]. The first commercialized MMC-VSC-HVDC project
is the Trans Bay Cable Project in the U.S.A., with 216 SMs
for each arm. In addition, another MMC-VSC-HVDC project
INELFE from France to Spain built by Siemens will be
completed in 2013. It can transmit rated power 2×1000MW
and has 401 voltage levels [30], [37]. Most of the advantages
come from its scaled structure. Therefore, the voltage
balancing of multiple floating dc capacitors of the SMs
becomes a vital factor for the safe operation of MMC [24],
[31]. There have been many research efforts made to explore
the voltage balancing strategies based on level shifted
PWM[31-35], phase-shifted PWM(PSPWM)[36-38], selective
harmonic elimination(SHE)[39], and nearest level
control(NLC) [40-44]. The high switching frequency of pulse
width modulation is unsuitable for large numbers of SMs
MMC. The switching losses are predominant in high
switching frequency modulation. The voltage balancing
algorithm based on phase shifted PWM requires individual
SM balancing controller which is inappropriate for large Fig. 1. (a) Three phase n – level MMC topology
numbers SMs MMC [36-38]. However, a large amount of and (b) MMC sub – module.
switching angles in the SHE modulation is computed offline
and stored in tables, so with large number of sub modules TABLE I
MMC based HVDC, the SHE method is complicated [40-44]. SWITCHING STATES OF A CELL
Due to the conceptual and implementation simplicity of the Current Capacitor Output
S1 S2 D1 D2
NLC method, the aim is to use it in converters with a high direction states voltage
number of levels [43]. Few research papers are published on OFF ON OFF OFF iarm>0 Unchanged 0
OFF OFF OFF ON iarm<0 Unchanged 0
the NLC based voltage balancing algorithm of submodules OFF OFF ON OFF iarm>0 Charging VC
capacitor voltages of MMC with the application to HVDC. ON OFF OFF OFF iarm<0 Discharging VC
One commonly used balancing approach is based on sorting of
the voltages of the capacitors. Then the capacitors with the
highest or lowest voltages are selected to be discharged or stages of the balancing algorithm. Elimination of some of the
charged determined by the current direction [31-35], [40]. The stages can reduce the processor time in the hardware
predefined voltage deviation of the SM voltages can be set in implementation. The proposed method is pictorially presented
[41]. The SM voltages fluctuations are limited by controlling to consolidate the understanding of the balancing algorithm.
the triggering frequency [42].There are number of stages of The feasibility and robustness of the proposed method has
implementation of the balancing algorithm based on sorting. been verified by applying to one of the prominent applications
However, every stage of the balancing algorithm has not been MMC -VSC-HVDC. The comprehensive simulations have
clearly demonstrated in [40-44]. been carried out in MATLAB/SIMULINK.
This paper presents simplified NLC method of voltage This paper starts in Section III with a description of the
balancing based on sorting of the voltages of the SM MMC structure and its operation. Section IV explains the
capacitors, which can simplify and eliminate some of the NLC method.The various stages of the proposed balancing

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simplified NLC method are introduced in Section V. The

MMC-VSC-HVDC transmission system and its control
strategies are presented in Section VI. The simulation results
and how the proposed algorithm can be implemented are
described in the Sections VII and VIII, followed by the
concluding remarks in the section IX.

III. MODULAR MULTILEVEL CONVERTER

A. Basic structure
The typical structure of a MMC is shown in Fig. 1(a) and
the configuration of a sub -module(SM) is given in Fig. 1 (b).
Each SM is a simple chopper cell composed of two IGBT
switches S1 and S2, two anti parallel diodes D1 and D2 and a
capacitor C. Each phase leg of the converter has two arms,
upper and lower. Each one is constituted by n number of SMs.
In each arm, there is also a small inductor Ls to compensate for
the voltage difference between upper and lower arms
produced when a SM is switched in or out. With reference to
the SM shown in Fig. 1 (b), the output voltage VSM has two
values; VSM = VC when S1 is on and S2 is off or VSM = 0 when
S1 is off and S2 is on. Table I summarizes the switch states of a
SM and their resultant influence on associated capacitor
Fig. 2. Nearest level selection (a) waveform synthesis and (b) control
voltages. diagram.

B. Operation principle dilo Vdc

SM j
The number of levels in the phase leg depends not only on vlo = v j − Ls + (7)
the way number of SMs connected in the arm but also on the j dt 2
way converter leg is modulated. Output line-to-neutral (phase)
ij I dc
voltage has (n+1) levels in LSPWM, if topology consisting ‘n’ iup = + + izj (8)
numbers of sub-modules per arm. When PSPWM is adopted, j 2 3
2n sub-modules in each phase leg have 2n triangular
waveforms with the same frequency but a phase difference of ij I
3600/2n, then output line-to-neutral voltage has 2n+1 levels. ilo = − + dc + izj (9)
j 2 3
Based on Fig.1 (a) the mathematical equations which govern
dynamic behaviour can be expressed for each phase as [40]: where vupj is the total arm voltage on each phase j including

the total voltage of all upper SMS ( v SM ) and the voltage of

diup up j

vupj = + Ls
SM j
vup (1) the inductor LS. Vdc , Idc , iup , ilo & izj are the total dc bus
j dt j j
dilo voltage, dc current, upper arm current, lower arm current and
vloj = vloSM + Ls
j the circulating current respectively. The value of the
(2)
j dt circulating current of all the phases is zero
n
  ( iza + izb + izc = 0 ). The discrete steps in the output voltage
SM
vup
j
= ∑  Supjk vCup jk  (3) is obtained by controlling switching functions of the SMs in
k =1 the upper and lower arm of each phase according to (1) to (5).
n Similar definitions are applicable for the lower arm identified
 
vloSM =
j
∑  Slojk vClojk  (4) with the subscript ‘lo’.
k =1
Vdc Vdc IV. NLC METHOD
vj = − vup = − + vlo (5)
2 j 2 j The nearest level control (NLC), also known as the round
diup method, uses the nearest voltage level that can be generated by
SM j Vdc converting to the desired output voltage reference [44]. The
vup = −v j − Ls + (6) three phases are controlled separately based on the process of
j dt 2

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Fig. 3. Data and parameters of the MMC -VSC - HVDC transmission system.

independent comparisons. As illustrated in the Fig.2 (a) different levels of the implementation. The similar following
sampled waveform can be formed by comparing the reference sub processes are applied for the lower arm.
waveform with the existing output voltage level. Given a
A. Sorting of SMs voltages
voltage reference vref , the nearest output voltage level nnl The voltages of the capacitors of the arm SMs are sorted in
can be determined with (10) the descending order. The total number of the sub-modules are
switched on at any time are six for realizing the seven level of
1 phase to neutral voltage of the MMC. Therefore sorted
nnl = round (vref ) (10) capacitor voltages are chosen according to the requirement of
Vc the switching sequence of the SMs, i.e. when one SM from the
upper arm is chosen then five SMs from the lower arm are
where Vc is the sub module capacitor voltage. The next step chosen next two SMs from upper arm and four from lower
arm, then three from upper and three from lower arm and this
is to determine how many numbers of SMs shall be switched continues till the six from upper arm and none from the lower
on and is performed by round function. The function returns arm selection comes. The last capacitor voltage in the
the nearest integer of the input number (e.g., round (3.4) =3, descending order sorting is the minimum and the first sorted
round (3.6) =4) [42]. This nearest integer multiplied by Vc capacitor voltage is the maximum. The minimum and
corresponds to the closed level to the reference is generated by maximum values of the single capacitor voltage are chosen
the inverter [10]. The operating principle for the 11-level from the last and the first signal from the Fig. 4(a). Similarly
output voltage is demonstrated in Fig.2 (a) for the first quarter two capacitor voltages are chosen from the last and from the
cycle of a sinusoidal reference [31]. The numbers of SMs first. The procedure for choosing the three, four and the five
required are n= 10 per arm. The capacitor voltage of each SM SMs capacitor voltages are same and illustrated in the Fig. 4
V V (b-e). There is no rigmarole method in choosing minimum and
is Vc = dc = dc . The approximation error is Vdc/5. The maximum number of the capacitor voltages in the simplified
n 10
NLC method. In conventional balancing method, which is
implementation of the nearest voltage level generation is
based on sorting of the capacitor voltages [21-23], [31], [33],
illustrated in Fig. 2(b)
and [40-44], the individual sorting of the capacitor voltages
are required. Individual sorting is required comparatively
complex logic and more processor space.
V. SIMPLIFIED NLC METHOD
In the simplified NLC method, the same concept of B. Passing SM voltages by detection of the arm current
balancing i. e. on the basis of sorting the voltages of the After the detection of the arm current, selected number of
capacitors is used [21-23], [31], [33], and [40-44]. Then the SMs can be forwarded according to the direction of the
capacitors with highest voltages or the capacitors with lowest current. If the arm current is greater than zero, the SMs with
voltages are selected to be discharged or charged determined lowest voltages are selected otherwise highest SMs. The
by the current direction. Simplification at the each stage is process of forwarding the one, two, three, four, and five
done to reduce the processor time for the hardware numbers of the SM capacitors voltages according to the
implementation in the proposed method. The simplified NLC direction of the arm current is illustrated in Fig. 5 (a-e).
method in this paper has been described for the seven levels of C. Status identification of the capacitor voltages
voltages of the MMC. The pictorial presentation of the
simplified LSPWM balancing algorithm is presented here for The SMs capacitor voltages are available according to the
the consolidation of the understanding of the method at the direction of arm current. Available capacitor voltages of the
SMs can have lowest or highest values. Those available

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Fig. 4. Sorting of SMs capacitor voltages in the descending order(a) Single SM voltage (b) Two SMs voltages (c) Three SMs voltages (d) Four SMs
voltages (e) Five SMs voltages (blue solid arrow indicates maximum and red hollow arrow indicates minimum capacitor SM voltages).

Fig. 5. Minimum or maximum capacitor voltages forwarded according to the direction of arm current (a) One SM voltage (b) Two SMs voltages
(c) Three SMs voltages (d) Four SMs voltages. (e) Five SMs voltages.

outputs of the Fig. 5(a-e) are only the numbers of the SM affect the capacitor voltage of the SM. The task of the state-to-
capacitor voltages. Each of that outputs can have the value of decoder is when first level of the output voltage is available,
first, second, third, fourth, fifth and sixth SM capacitor first input should pass. When second output level, the second
voltage. The task of this controller is to pass that status of the input shall pass. State condition ‘1’ means the switch is on,
input signal of the multiport switch. For an example, when and ‘0’ means the switch is off and illustrated in Fig.9 (a-b).
input to the multiport switch has first SM capacitor value, then
it should be passed. Similarly, second, third, fourth, fifth, and
sixth SM capacitor voltage value for that input to be VI. MMC-VSC-HVDC SYSTEM
forwarded. The procedure for passing the status to each of the
MMC based VSC-HVDC is a new electrical transmission
inputs to the multiport port switch is pictorially demonstrated
based on insulated gate bipolar transistor (IGBT) and VSC
in the Fig.6 (a-d).
technology. It primarily consists of three parts; a rectifier
D. Serial passing of SMs capacitor voltages station, an inverter station and high voltage dc transmission
When only one number of SM capacitor voltage (O/P1_ 1) cable or lines. The power system considered is a MMC-
is selected the probability of appearing of the first SM HVDC system in which two VSCs are linked by 75 km dc
capacitor voltage (Vc1up) is only once and hence, it is cable. System data and parameters are showing in the Fig. 3.
straightforward be made available for the gate pulse logic. It is Both converter stations are composed of seven-level phase
not the case with the two, three, four, five and six numbers of voltage MMC connected through the step up transformers.
SM capacitor voltages are selected. When two numbers of The shunt connected low-pass and high-pass damped RLC
SMs with their lowest or highest SM voltages (O/P2_1 and filters are provided on the AC system to mitigate
O/P2_2) are selected, the O/P2_1 and O/P2_2 can have the characteristics harmonics generated by switching actions of
first SM voltage (Vc1up_21 and Vc1up_22) at different instants the converter.
of the time. Both the outputs (Vc1up_21 and Vc1up_22) are
provided to the OR gate so that whenever the first SM Controls of the MMC-HVDC System
capacitor voltage is present at any of the two inputs that shall
The control strategy of MMC-VSC-HVDC can adopt both
be made available to the gate pulse logic. The same process is
direct current control strategy [27] and vector current control
applied to get the first, second, third, fourth, fifth and sixth SM
strategy [28]. Because of its excellent dynamic performance
capacitor voltages by giving them to the OR gates. The
due to the decoupling of the d and q axis parameters, this
pictorial presentation is presented in the Fig.7 (a-b).
paper implemented the vector control strategy. The converter
E. Generation of gate pulses can implement four different control modes; active power
When first SM from the upper (five from the lower arm are control, dc voltage control, dc current control and ac voltage
on) or lower (five from the upper arm are on) is on, it will not or reactive power control.

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Fig. 6. Realization of module capacitor voltages serially (a) For one SM voltage (b) For two SMs voltages
(c) For three SMs voltages and (d) For five SMs voltages.

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Fig. 7. Collection of one, two, three, four, five and six SMs capacitor voltages (a) for two SMs and (b) for five SMs.

Fig. 8. Generation of gate pulses (a) Upper one and five lower SMS (b) Upper two and lower four SMs (c) Upper three and the lower three SMS
(d) Upper four and the lower two SMs and (e) Upper five and lower one SMs.

Fig. 9. Gate generation process for the IGBTs of the SMs (a) and (b) Status of the IGBT on (which one is ON) and (c) Switching states to decoder.

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Ldiq
= vcq − vsq − iq R − ωLid (16)
dt
The (15) and (16) are non- linear because of the existence of
multiplication terms between the (vcd, vcq) and (id, iq), so that
decoupled controller is defined by

ki
vcd = vsd (k p + )( idref − id ) − ωLiq (17)
s
ki
vcq = vsd (k p + )( iqref − iq ) − ωLid (18)
s
The decoupled controller is shown in the Fig. 10(b). If the
system operates in three phase balance steady state, ‘a’ phase
voltage phase degree is zero. Then vsd = |vsa|, and vsq = 0. The
active and reactive power flowing into the VSC converter can
be shown as follows

3 3
P = (vsd id + vsq iq ) = vsd id (19)
2 2
3 3
Q = (vsd id − vsd iq ) =− vsd iq (20)
2 2

Fig. 10. (a) Three phase network connected to VSC and (b) Vector VII. SIMULATION RESULTS
control of MMC – HVDC. The proposed simplified NLC method has been simulated
in MATLAB/SIMULINK. The performance of the simplified
A three phase view of the ac side of the VSC is shown in NLC method is tested to open loop R-L load, as well as closed
the Fig. 10 (a). The ac side dynamics can be described as loop MMC-VSC-HVDC system. The comprehensive results
follows to check the robustness of the method are discussed in
following subsections. Steps on the regulators, minor and
dia severe perturbations on the AC sides are carried out.
L + ia R = vca − vsa (11)
dt
A. Open loop response of MMC
dib
L + ib R = vcb − vsb (12) The converter rating for the open loop simulation is
dt considered as 1540 MVA with the total dc voltage VDC = 200
dic kV. Load resistance is 19.44 ohms, load inductance 0.02944 H
L + ic R = vcc − vsc (13) and the load capacitor is 0.344 mF. The load power factors
dt 0.5, 0.8 and 0.9 lagging are considered. The buffer inductor is
0.15 pu (7.734 mH). Seven level MMC is considered for the
The vector representation of above equation can be written as simulation. The effect of modulation index on SM capacitor
voltage balance is investigated by considering a load power
diabc 1 R 1 factor 0.8 lagging at modulation indices. Fig. 11 (a) and Fig.
= vcabc − iabc − vsabc (14) 11 (b) shows the upper and lower arm SM capacitor voltages
dt L L L at different modulation indices m =1 and m =0.5. For
modulation index 1, peak ac voltage output is 100 kV
where ia, ib, and ic are the currents of the system; vca,vcb and vcc (m*VDC/2 =1*100 kV), and the SM capacitor voltage is 33.33
are the converter generated voltages; vsa,vsb and vsc are the kV i.e. m*VDC/6. Similarly, the peak ac output voltage and the
system voltages of phase a, b, and c respectively. Through SM capacitor voltage for modulation index 0.5 are 50kV and
Park transfer, the (14) can be expressed as 16.66 kV respectively. The effect of load power factor on SM
capacitor voltage balance is examined for 0.5 and 0.9 lagging
Ldid and is shown in Fig. 12 (a) and Fig. 12 (b).The modulation
= vcd − vsd − id R + ωLiq (15) index is considered 0.9. It is observed that even at the low
dt power factor 0.5 lagging, the SM capacitor voltage is well

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Fig. 11. Effect of modulation index on voltage balance of SM capacitors voltages at power factor 0.8 lagging ( voltage across the SMs capacitors
voltages of the phases b and c are identical to phase a at (a) modulation index m=1 and (b) modulation index m=0.5.

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Fig. 12. Effect of power factor on voltage balance of SM capacitors voltages at modulation index m=0.9 ( voltage across the SMs capacitors
voltages of the phases b and c are identical to phase a (a) power factor 0.5 lagging and (b) power factor 0.9 lagging.

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Fig. 13. Station 1 parameters in pu (a) Supply voltage (b) Supplied

Fig. 14. Station 2 parameters in pu (a) Supply voltage (b) Active
active power and the reference power (c) Reactive power and the
power (c) Reactive power and the reference reactive power (d) DC
reference reactive power (d) Modulation index (e) DC link voltage.
voltage and the reference dc voltage (e) Modulation index

stabilized around the 1.0 sec to the expected value 30kV. The subjected to the very large values of steps (positive and
voltages of the SMs capacitors are well maintained at wide negative) which is not the practical case. Fig. 13(b-c) shows
range of modulation indices and power factors. the dynamic response to the changes in real and reactive
power commands. At t = 1.3 s large step is first applied to the
reference active power from 1 p. u. to -0.5 p. u. It is because of
B. Step response of power (P&Q) and DC voltage
the very large steps active power requires more cycles to get
The system is programmed to start and reach a steady state. stabled to its steady value and the dc voltage at the station 1 is
Steps are then sequentially applied on the reference active and also recovered around the same time that of active power to
reactive power of the station1 and the reference DC voltage of its steady value of 1 p. u. The second step on the reference
the inverter. The steady state values of active, reactive power active power is applied at the 2.5 s of +1.5 p. u. i.e. from -0.5
and dc voltage are 1 p. u. (200MW), 1p.u. (200MVAR) and 1 p. u. to 1 p. u. The recovery of the active power in this case is
p. u (200kV) respectively. To examine the robustness of the fast as compared to the first step. The dc voltage is stabilized
proposed method, the different regulators are deliberately around the same time to its steady state value of 1 p. u.

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Fig. 15. Dynamic responses at the station1: (a) supply voltages (in p.u.), (b) active power and the reference active power (in p.u.), (c) reactive power
and the reference reactive power (in p.u.), and (d) DC voltage (in p.u.).

Fig. 16. Dynamic responses at the station2: (a) supply voltages (in p.u.), (b) active power (in p.u), (c) reactive power and the reference reactive power
(in p.u.), and (d) DC voltage and the reference dc voltage (in p.u.).

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Fig. 17. Schematic of the proposed algorithm implementation for 7-level open loop MMC.

The step of -0.3 p. u. to the reference of the reactive power is

C. Dynamic response of MMC- VSC- HVDC Transmission
applied at the t = 2s, the reactive power is reached to its steady
System
state value within three cycles and the dc voltage is least
disturbed. The second step is of 0.5 p. u. applied at the For a duration of 7 cycles the first step of disturbance of
reference reactive power at the 2.7s. The actual reactive power value -0.1 p.u. at t = 1.5s on voltage magnitude at the station1
follows its command and reached to steady state within few is applied as sown in the Fig. 15(a). The second disturbance of
cycles. The capacitor voltages are well maintained at their three phase fault is applied at the t = 2.1s for the duration of 6
nominal voltage i.e. under transient and steady-state cycles at the station 2 PCC as shown in the Fig. 16 (a). The
conditions. This confirms the capability of the simplified NLC recovery time for active, reactive powers and dc voltage is less
method maintaining the SM capacitor voltages to the specified than the 0.3s to reach the steady state. Because of its
values. Fig .13 (e) shows the net dc-link voltage, subsequent to overcharging, the dc voltage is increased to 1.2 p. u. following
the disturbances, is well regulated. The ac system voltage in the second disturbance. Fig. 15(b) shows the overshoot of 1.33
the per unit at the station 1 is shown in the Fig. 13(a). The step p.u. in the active power at station 1. The damped oscillations
of 0.05 p. u. is also applied on the reference dc voltage of the in the reactive power in the station1 are observed and are
station 2. The various dynamic responses of the different shown in the Fig. 15(c). The dc voltage response at the
parameters at station 2 are shown in Fig. 14 (a-e). Though the sending end is shown in the Fig.15 (d). Similarly, the
applied steps are huge at the reactive, active power references responses of the various parameters in the station 2 are shown
and the dc voltage, the effect on the SM capacitor voltages are in the Fig. 16(a-d). Fig. 15(d) and Fig. 16(d) show that the dc
minimal. This confirms the robustness of the proposed voltage is quite well regulated even at the huge disturbances,
method. and it recovers within the 0.3s.

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VIII. EXAMPLE FOR PROPOSED ALGORITHM the controllers. The combined simplification and reduction of
IMPLEMENTATION processes at various stages of this method can lead to sixty
percent saving in memory and the computational time of the
The proposed algorithm can be implemented as illustrated
in Fig. 17. An example of open loop MMC is considered for processor at the implementation level compared to the existing
seven level output voltage. The proposed algorithm for single balancing algorithms.
phase i. e. per leg is possible to implement using Texas DSP
TMS320F2812 with 150 MHz operating frequency. This DSP
has 12- bit ADC module with 16- channels. Out of 16 ACKNOWLEDGMENT
channels, 12 channels can be used to sense the SM capacitor The authors would like to thank the anonymous reviewers and
voltages and 2 channels for upper and lower arm currents the editors for their valuable advice and comments.
through the sensors. It has 5 input-output ports (GPIO) with 56
pins, out of which 24 pins can be used to trigger the IGBT REFERENCES
switches. It has 128K× 16 memory with interfacing external [1] Jose Rodrigues, J. Lai., and FangZheng Feng, “Multilevel inverters: a
memory of 1MB. This is sufficient to write the proposed survey of topologies controls and applications,” IEEE Trans.Ind.
algorithm. The conversion time of ADC in TMS320F2812 is Eletron., vol. 49, no.4, pp. 724-738, Aug. 2002.
80 ns or 12.5MSPS (M samples per sec.). It can convert 14 [2] Burhan Gultekin, and Muammer Ermis, “Cascaded Multilevel
Converter-Based Transmission STATCOM: System Design
signals within 1120ns. The sampling frequency can be Methodology and Development of a 12 kV + MVAr Power Stage,”
increased more than 800KSPS, whereas required sampling IEEE Trans. Power Electron., vol.28, no.11, pp. 4930-4950, Nov. 2013.
frequency is 700 SPS (14×50). The switching frequency is [3] D. Peftitsis, G. Tolstoy, A. Antonopoulos, J. Robkowski, J. Lim, M.
considered 50Hz. The memory required will be around 65KB. Bakowski, L. anguist, H. Nee, "High-Power Modular Multilevel
Converters With SiC JFETs," IEEE Trans. Power Electron., vol.27,
The number of SMs and the IGBT switches required for three no.1, pp.28-36, Jan. 2012
phases are 36 (12 SM per phase i.e. per leg×3) and 72(36×2) [4] C.Newton, and M. Summer, “Multilevel Converters: a real solution to
respectively. The experimental realization of this method for medium/high voltage drives?,” IEE Power Eng. J. 1998, vol. 12, no.1,
the three phases is possible using one master and two slave pp. 21-26, 1998.
[5] Jose Rodrigues, Steffen Bernet, Peter K. Stemer, and I. Lizama , “A
DSPs. survey on Neutral-Point-Clamped Inverters,” IEEE Trans.Ind. Eletron.,
The proposed algorithm eliminates the selection stage of vol. 57, no.7, pp. 2219-2230, July. 2010.
redundancies of voltage levels. It does not require the [6] X. Lie, L. Yongdong, Wang Kui,John C Clare, Patrick W. Wheeler,
individual sorting of the SM, and the identification of the SM "Research on the Amplitude Coefficient for Multilevel Matrix Converter
Space Vector Modulation,” IEEE Trans. Power Electron., vol.27, no.8,
can be carried out throughout the stages of the implementation pp.3544-3556, Aug. 2012.
of this method. This simplification and elimination of some of [7] P. Roshankumar, p. P. Rajeevan, K. Mathew, K. Gopakumar, Jose I.
the stages may reduce the memory required and computational Leone, and Leopoldo G. Franquelo, "A Five-Level Inverter Topology
time to sixty percent as compared to the existing balancing with Single-DC Supply by Cascading a Flying Capacitor Inverter and an
HBridge," IEEE Trans. Power Electron., vol.27, no.8, pp.3505-3512,
algorithm methods. Nearest level control (NLC) method is Aug. 2012.
basically suited for high number of sub modules of the output [8] S. Theilemans, A. Ruderman, B. Reznikov, and J. Melkebeek,
voltage. This is not convenient for the low number of levels “Improved Natural Balancing With Modified Phase- Shifted PWM for
and a low modulation index, since the total harmonic Single-Leg Five Level Flying Capacitor Converters,” IEEE Trans.
Power Electron., vol.27, no.4, pp.1658-1667, April 2012.
distortion of the output is very high [10]. Therefore the [9] S. Kouro, M. Malinowski, K. Gopakumar, J. pou, L. G. Franquelo,
simplification, saving in memory and the computational time B.Wu, J. Rodriguez, M. A. Perez, and J. I. Leon, “Recent advances and
is more prominent to the high scale of the system. industrial applications of multilevel converters,” IEEE Trans. Ind.
Electron., vol. 57, no. 8, pp. 2553–2580, Aug. 2010.
[10] J. Rodriguez, L. G. Franquelo, S. Kouro, J. I. Leon, R. Portillo, M. Prats
and M. Perez, “Multilevel converters: An enabling technology for high-
IX. CONCLUSION power applications,” Proceedings of the IEEE, Vol. 97, No. 11, pp.
1786–1817, Nov. 2009.
This paper proposed simplified NLC voltage balancing [11] J. Rodriguez, S. Bernet, B. Wu, J. O. Pontt, and S. Kouro, “Multilevel
method for MMCs. This algorithm reduces processes of the voltage-source-converter topologies for industrial medium-voltage
different stages from sorting of the sub modules to the drives,” IEEE Trans. Ind. Electron., vol. 54, no. 6, pp. 2930–2945, Dec.
2007.
selection of the number of sub modules for the triggering. The [12] F. Peng, W. Qian, and D. Cao, “Recent advances in multilevel
proposed method neither requires redundancy and the converter/inverter topologies and applications,” in Proc. Conf. Rec.
individual sorting of the sub modules nor the identification of IEEE IPEC, 2010, pp. 492–501.
[13] M. Malinowski, K. Gopakumar, J. Rodriguez, and M. perez, “A Survey
individual sub module at the time of the triggering. The on Cascaded Multilevel Inverters,” IEEE Trans. Ind. Electron., vol. 57,
pictorial presentation of the simplified balancing algorithm no. 7,pp. 2197–2206, July 2010.
also helps in enhancing the understanding of different stages [14] A.H. Bhat, and N. Langer, “Capacitor Voltage Balancing of Three-Phase
Neutral-Point-Clamped Rectifier Using Modified Reference Vector,”
of the algorithm. The comprehensive investigation of this
IEEE Trans. Power Electron., vol.29, no.2, pp. 561-568, Feb. 2014.
method to one of the applications MMC-VSC-HVDC [15] S. Gautam, and R. Gupta, “Switching Frequency Derivation for the
confirms the robustness under steady state as well as transient Cascaded Multilevel Inverter Operating in Current Control Mode Using
conditions. The sub module capacitor voltages can be well Multiband Hysteresis Modulation IEEE Trans. Power Electron., vol.29,
no.3, pp. 1480-1489, March 2014.
balanced for open as well as closed loop applications. The [16] J. Chivite- Zabalza, P. Lzura-Moreno, D. Madariago, G. Calvo, and M.
results show that the proposed method is significantly more Angel-Rodriguez, “Voltage Balancing control in 3-Level Neutral-Point
accurate to the huge disturbances made at the various stages of Clamped Inverters Using Triangular Carrier PWM Modulation for

0885-8993 (c) 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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FACTS Applications,” IEEE Trans. Power Electron., vol.28, no.10, pp. (MMCC-DSCC),” IEEE Trans. Power. Electron. , vol. 26, no. 6, pp.
4473-4484, Oct. 2013. 1649–1658, Jun. 2011.
[17] S. Fazel, S. Bernet, D. Krug, and K. Jalili, “Design and comparison of 4- [39] G. Konstantinou, M. Ciobotaru and V.G. Agelidis, “Operation of a
kV neutral-point-clamped, flying-capacitor, and series-connected H- modular multilevel converter with selective harmonic elimination
bridge multilevel converters,” IEEE Trans. Ind. Appl., vol. 43, no. 4, pp. PWM,” in Proc. of 8th International Conf., on Power Electronics and
1032–1040, July/August 2007. ECCE Asia (ICPE&ECCE) Jeju, Korea, May 2011, pp. 999–1004.
[18] M. Marchesoni, and P. Tenca, “Diode-clamped multilevel converters: a [40] Jaime Peralta, Hani Saad, Sebastein Dennetiere, Jean Mahseredjian, and
practicable way to balance DC-link voltages,” IEEE Trans. Ind. Samuel Nguefeu, “Detailed and averaged models for a 401-level MMC-
Electron., vol. 49, no. 4, pp. 752–765, August 2002. HVDC system,” IEEE Trans. Power Del., 2013.
[19] N. Hatti, Y. Kondo, and H. Akagi, “Five-level diode-clamped PWM [41] Jianzhong Xu, Chengyong Zhao, Wenjing Lu, and Chunyi Guo,
converters connected back-to-back for motor drives,” IEEE Trans. Ind. “Accelerated model of modular multilevel converters in
Appl., vol. 44, no. 4, pp. 1268–1276, July/August 2008. PSCAD/EMTDC,” IEEE Trans. Power Del., 2013.
[20] S. Vazquez, J. Leon, J. Carrasco, L. Franquelo, E. Galvan, M. Reyes, J. [42] Q. Tu and Z. Xu, “Impact of sampling frequency on harmonic distortion
Sanchez, and E. Dominguez, “Analysis of the power balance in the cells for modular multilevel converter,” IEEE Trans. Power Del. , vol. 26, no.
of a multilevel cascaded H-bridge converter,” IEEE Trans. Ind. 1, pp. 298–306, Jan. 2011.
Electron., vol. 57, no. 7, pp. 2287–2296, July 2010. [43] Q. Tu, Z. Xu, and L. Xu, “Reduced switching-frequency modulation and
[21] A. Lescinar, J. Hildinger, and R. Marquardt, “Modulares stromrictherk- circulating current suppression for modular multilevel converters,” IEEE
onzept fr netzkupplungsanwendungen bein hohen spannungen,” in ETG Trans. Power Del. , vol. 26, no. 3, pp. 2009–2017, Jul. 2011.
Fachhericht, Bad Nauhein, Germany, Apr. 2002, vol. 88, pp. 155-161. [44] Gum Tae Son, Hee-Jin Lee, Tae Sik nam, Yong- Ho Chung, Uk- Hwa
[22] A. Lesnicar and R. Marquardt, “An innovative modular multilevel con- Lee, Seung- Taek Baek, Kyeon Hur, and Jung- Wook Park, “Design and
verter topology suitable for a wide power range,” presented at the IEEE control of a modular multilevel HVDC converter with redundant power
Power Tech. Conf., Bologna, Italy, Jun. 2003. modules for non- interruptible energy transfer,” IEEE Trans. Power
[23] A. Lescinar, and R. Marquardt, “A new modular voltage source inverter Del.,. vol. 27, issue 3, pp. 1611 – 1619. July 2012.
topology” presented at the 10th Eur. Conf. Power Electron. Appl.,
Toulouse, France, 2003.
[24] Fuzin Deng, and Zhe Chen, “A Control Method for Voltage Balancing
in Modular Multilevel Converters,” IEEE Trans. Power Electron., Prafullachandra M. Meshram received
vol.29, no.1, pp. 66-76, Jan. 2014. the B.E. degree from Nagpur University,
[25] M. Guan, Z. Xu, "Modeling and Control of a Modular Multilevel
Converter-Based HVDC System under Unbalanced Grid Conditions," Nagpur, India, and the M.Tech degree
IEEE Trans. Power Electron., vol.27, no.12, pp.4858-4867, Dec. 2012. from Visvesvaraya National Institute of
[26] M. Saeedifard, R. Iravani, and J. Pou, “A space vector modulation Technology, Nagpur (formerly VRCE), in
strategy for a back-to-back five-level HVDC converter system,” IEEE 1991 and 2003, respectively, and is
Trans. Ind. Electron., vol. 56, no. 2, pp. 452–466, Feb. 2009.
[27] CIGRÉ, SC B4 HVDC and Power Electronics, Working Group B4-37, currently pursuing the Ph.D. degree in the
VSC Transmission, CIGRÉ Tech. Brochure no. 269 2005. Department of Electrical Engineering, in
[28] A. Yazdani and R. Iravani, “Dynamic model and control of the NPC- the same institute.
based back-to-back HVDC system,” IEEE Trans. Power Del. , vol. 21,
He is presently working as an Associate Professor in the
no. 1, pp. 414–424, Jan. 2006.
[29] S. Alebord, R. Hamenski, and R. marquardt, “New transformer less Department of Electrical Engineering , Yeshwantrao Chavan
scalable modular multilevel converters for HVDC transmission,” in College of Engineering(YCCE), Wanadongri, Nagpur. He has
Proc. IEEE Power Electron. Specialists Conf., Jun. 2008, pp. 174-179. authored several publications in premiere power electronic
[30] Siemens AG: “The smart way HVDC PLUS- one step ahead,” [Online]. conferences such as TENCON and ICIEA.He received best
Available: https:// www.siemens.com/energy/hvdcplus.
paper presentation awards to both of his papers at an
[31] M. Saeeidifard, and R. Iravani, “Dynamic performance of a modular
multilevel back - to- back HVDC system,” IEEE Trans. Power Del., vol. International. Conference ECTI-CON 2005, Pattaya, Thailand.
25, no. 4, pp. 2903-2912. Oct. 2010. His research interests are in the areas of power electronics,
[32] U. Gnanarathna, A. Gole, and R. Jayasinghe, “Efficient modeling of VSC-HVDC, and application of control system to the VSC-
modular multilevel HVDC converters (MMC) on electromagnetic HVDC.
transient simulation programs,” IEEE Trans. Power Del., vol. 26, no. 1,
pp. 316–324, Jan. 2011.
[33] S. Rohner, S. Bernet, M. Hiller, and R. Sommer, “Modulation, losses,
and semiconductor requirements of modular multilevel converters,” Vijay B. Borghate (M’12) born in 1960,
IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2633–2642, Aug. 2010. received B.E. (Electrical), M.Tech.
[34] G. P. Adam, O Anaya-Lara, G. M. Burt, D. Telford, B. W. Williams,and (Integrated Power System) and Ph.D. from
J. R. McDonald, “Modular Multilevel inverter: pulse width modulation Visvesvaraya Regional College of
and capacitor balancing technique,” IET Power Electron., vol.3, no . 5,
pp. 702–715, Sep. 2010. Engineering, under Nagpur University
[35] G. P. Adam, O Anaya-Lara, G. M. Burt, D. Telford, and J. R. McD- Nagpur,India in 1982, 1984 and 2007
onald, “Transformerless STATCOM based on a five-level modular multi respectively.
level converter,” in Proc. 13th Eur. Conf. Power Electron. Appl., 2009, He has worked as engineer during 1984-
pp. 1–10.
[36] H. Peng, M. Hagiwara and H. Akagi, "Modeling and Analysis of 85 in Maharashtra state electricity board,
Switching-Ripple Voltage on the DC Link Between a Diode Rectifier India, before joining the Visvesvaraya Natonal Institute of
and a Modular Multilevel Cascade Inverter (MMCI)," Power Technology(VNIT), then VRCE, Nagpur ,India as Lecturer in
Electronics, IEEE Trans. Power. Electron. ,, vol.28, no.1, pp.75-84, Jan.
1985. Presently, working as an Associate Professor in
2013.
[37] M. Hagiwara and H. Akagi, “Control and experiment of pulsewidth Electrical Department, in the same institute.
modulated modular multilevel converters,” IEEE Trans. Power. His area of research includes resonant converters, multilevel
Electron. , vol. 24, no. 7, pp. 1737–1746, Jul. 2009. converters.
[38] M. Hagiwara and H. Akagi, “Control and analysis of the modular
multilevel cascade converter based on double-star chopper-cells

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