Jonnala 2016
Jonnala 2016
Jonnala 2016
Abstract—In this paper, implementation and comparisons of like Diode Clamped Multilevel Inverter having N (maximum
Nearest Vector Control and Nearest Level Control modulation number of levels) - 1 clamped diodes in addition to the circuit
techniques for 27-Level with 3-Cell Asymmetrical Cascaded H- to generate N levels, same as N-1 flying capacitors in Flying
Bridge Multilevel Inverter is presented to analyse the Capacitor Multilevel Inverter [3].
performance and application oriented complexity. Asymmetrical
type of multilevel inverters is familiar in the view of attaining
more number of levels with lesser number of cells. Hybrid
Asymmetrical Multilevel Inverter gives higher levels than other
asymmetrical inverters with no redundant switching states for
the entire operation. Modulation Strategy takes foremost
involvement in the conversion process, but the selection of
strategy is based on the type of application and topology of
inverter. This paper reviews the comparative performance
parameter analysis to choose a suitable modulation technique for
different applications. The adoptive nature of Nearest Vector
Control and Nearest Level Control strategies are analysed
through Simulation and Experimental results.
I. INDRODUCTION
In present industrial market scenario, the influence of
Multilevel Inverters is high. Because the major research work
is going to improve the quality of power from PV array and FIGURE 1. CLASSIFICATION OF INVERTERS.
utilization of batteries for mobility. To get a high quality ac
supply with required voltage magnitude, frequency and better In Cascaded H-Bridge Multilevel Inverter DC sources may
THD in output for the most of the applications are fed with be PV array, Fuel cells or Batteries; the main attractive feature
multilevel inverters [1]. The most important feature of the of one of the Cascaded H-Bridge Multilevel Inverters is
multilevel inverter is having high power operating capability provides more number of voltage levels without increasing the
with low power rated conventional semiconductors, because DC sources and power switches i.e., Asymmetrical Cascaded
they are operated in cascade [2]. H-Bridge Multilevel Inverter [4-6]. If the cascaded H-bridge
multilevel inverter is designed with equal dc sources, then it is
The multilevel inverters are classified into different called as symmetrical Multilevel Inverter otherwise
categories and they are shown in Figure 1. Among the Asymmetrical Multilevel Inverter. In this article, the
classifications, Cascaded H-Bridge (CHB) Multilevel Inverter Asymmetrical CHB MLI is utilized to implement different
(MLI) is the best and commercially accepted one, but the only Modulation Techniques to generate 27-level output with less
drawback is more number of DC sources. In other topologies number of cells.
very much simplified by reducing the computational equations Operating conditions of NLC gives that it is not a fundamental
for the time intervals of vectors. By using the function ceil to modulation strategy, so the elimination of harmonics is not
resultant reference signal gives the appropriate voltage vectors possible due to there is no procedural tracing of reference
for the operation. signal. But if the levels of the inverter is high then the
harmonics are naturally eliminated in the AC side. The main
advantages are simplicity on operation and implementation.
Implementation of these two NVC and NLC modulation
techniques are very easy because of low computational
complexity and mostly compatible with any topology based
inverters [13]. In this paper implementation and performance
analysis of NVC and NLC to 3-Cell, 27-Level Asymmetrical
CHB Multilevel Inverter in Simulation and Experimentation
with Low-Power Prototype model are discussed in sections IV
& V. For comparison purpose, simulation is carried out with
FIGURE 4. NVC STRATEGY. Low-Power and Medium-Power models.
IV. SIMULATION RESULTS
As shown in Figure 4 the resultant reference signal is
approximated with the horizontal and vertical lines of space Table 2 shows the detailed parameters used to design the
hexagon to find the ranges of vectors. In each instant of time Asymmetrical multilevel inverter with 3-Cell. For
of present vector the reference signal is approximated with ceil asymmetrical nature of operation in both Low and Medium
function and getting the nearest vector with the values by the Power models are equipped with the 1:3:9 ratios related DC
simple calculations. These operational issues can be found in Sources.
detail in [10]. The selected voltage vector is basically
represents the future voltage vector and this will provides the TABLE 2. SIMULATION MODEL PARAMETERS.
future output level generated by the inverter. Based on the level
DC Voltages 1V : 3V : 9V (3 Cells)
the control driver circuit is generates the gating pulses and
Switches IGBT / D
those pulses will controls the switches to get the required
Load R = 10Ω, L = 25mH
output level.
Modulation Strategy NVC & NLC
B. Nearest Level Control f0 50Hz
Max. Step Size 1e-6 Sec
NLC is a simple level based strategy, and the levels are
selected by the rounded function so it can be called as Rounded
Control method [12, 13]. In NVC also using the same approach Figures 6-9, are simulated results for the single phase Low-
but NLC is a level based approach and NVC is time based. The Power model with specified modulation parameters as
pulse generation is different from the NVC modulation, mentioned in the previous section of NVC modulation strategy.
because NVC is a modulation and a selected vector gives the The 27-Level Voltage waveform is shown in Figure 6. The
commands to all three phases, but in NLC 1200 phase shifted middle portion of the +ve half cycle is constant, because the
references are required to generate all the three phase pulses. output levels are selected based on the vector control strategy.
The nearest voltage level selection procedure in NLC is based One of the corner in space hexagon’s vectors are the
on the simple expression per phase is: Nearest Voltage Level responsibility for that increment, constant and decrement
(VRN) = VDC*f-round (Vref). The operation of the NLC is nature of the output. It is based on a logical approach but it has
illustrated in Figure 5. some mismatches with the reference at the trail and bad edges
of constant portions.
FIGURE 12. CELL WISE POWER SHARING WAVEFORMS WITH NLC STRATEGY.
FIGURE 9. SIMULATED FREQUENCY SPECTRUM OF VOLTAGE SIGNAL FOR NVC
STRATEGY.
V. EXPERIMENTAL RESULTS
The incremental view of the levels of NLC based TABLE 4. COMPARISON BETWEEN EXPERIMENTAL AND SIMULATED VALUES
OF THD FOR NVC AND NLC STRATEGIES.
inverter output waveform is shown in Figure 22. All 13 level
are clearly visualized. Harmonic analysis with the reference of Simulation Experimental
harmonic order in hardware results are shown Figure 23, and NVC NLC NVC NLC
(V-THD (%)) (V-THD (%)) (V-THD (%)) (V-THD (%))
the total harmonic order is somewhat higher than that of R RL R RL R RL R RL
load load load load load load load load
simulation i.e., approximately 2% higher.
6.55 6.55 3.02 3.02 10.45 10.40 5.26 5.51