Saint Jérôme de Douala . Saint Jerome Douala .

Institut Supérieur des Sciences Religieuses et Sociales University Institute of Social and Religious Sciences
Institut Supérieur des Sciences de Gestion Appliquée University Institute of Applied Management Sciences
Saint Jérôme Polytechnique Saint Jerome Polytechnic

Academic year 2018-2019 Saint-Jérôme Polytechnique

EC : Microprocessors and microcontrollers

Level  : SJP3 Continious assement #2 : Intel 8086 microprocessor Duration  : 40min

Mechatronics engineering Name:

The test consists of 20 multiple choice questions. A question may have more than one answer or no answer, simply
check the boxes next to you answer(s). Please don’t check colored boxes, they are for correction purpose.

1. The Intel 8086 ☐☐☐ c. ☐The DS (Data segment)

a. ☐ Can pre-fletch up to 7 instructions d. ☐ Is the IP (instruction pointer)
b. ☐ Is a RISC computer 8. The accumulator register of 8086 is:
c. ☐Is an 8-bits microprocessor ☐☐☐
d. ☐ can Run programs of 8085 a. ☐ The flag register
2. The BIU of 8086 ☐☐☐ b. ☐ AX register
a. ☐ is the Bus Integrated Unit c. ☐ Code segment register CS
b. ☐is made of an instruction queue and d. ☐ Stack segment register (SS)
segment registers 9. In the minimum mode of 8086 ☐☐☐:
c. ☐Sends address and fletches instructions a. ☐ The circuit is complex
d. ☐decodes and execute instructions b. ☐ Multiprocessing can be performed
3. The EU of 8086 ☐☐☐ c. ☐ NM / MX ´ is 1
a. ☐Is the Editorial Unit d. ☐ The 8086 operate alone
b. ☐ Contains ALU, control unit and 10. The register BL of 8086 ☐☐☐:
registers a. ☐Is an 8-bits register
c. ☐decodes and executions instructions b. ☐ is a general purpose register
d. ☐ Manages interrupts c. ☐ is a segment register
4. A non-maskable interrupt (NMI) ☐☐☐ d. ☐ The lower part of the BX register
a. ☐ Is a software interrupt 11. The instruction JUMP ☐☐☐:
b. ☐Has higher priority compare the a. ☐ Change the value of the SP
interrupt request (ITR) b. ☐Need a RET instruction at the end
c. ☐ A control flag c. ☐ support only immediate addressing
d. ☐Is still overflow d. ☐ is used to call a subroutine
5. In 8086, each memory location is byte- 12. A procedure ☐☐☐:
addressable. The address bus width and the a. ☐is accessed by CALL/RET instructions
memory capacity are ☐☐☐ b. ☐ Require less memory than a macro
a. ☐12-bits width and 2MB memory c. ☐ is executed faster than a macro
b. ☐ 16-bits width and 1MB memory d. ☐ Stated the origin of the program
c. ☐20- bits width and 2MB memory 13. The code MOV [0600], AX ☐☐☐:
d. ☐20-bits width and 1MB memory a. ☐Loads 0600H in the accumulator
6. The status register of 8086 ☐☐☐ b. ☐Store the AX content to the address
a. ☐ The flag register 0600H.
b. ☐ AX register c. ☐ use immediate addressing mode
c. ☐ Code segment register CS d. ☐Use the direct addressing mode
d. ☐ Stack segment register (SS) 14. REP − Used to repeat the given instruction
7. The program counter (PC) of 80866 is till: ☐☐☐
☐☐☐ a. ☐ CX=0;
a. ☐ The SP (stack pointer) b. ☐ CX≠ 0
b. ☐The BP (base pointer) c. ☐ CX = 0 or zero flag ZF = 1
 d. ☐ CX = 0 or zero flag ZF = 0 c. ☐ shift bits of a word towards the right
and copy the old MSB into the new MSB
15. JS − Used to jump if ☐☐☐ d. ☐ Used to shift bits of a byte/word
a. ☐ overflow flag OF = 1 towards left and put zero(S) in LSBs
b. ☐ if not carry CF = 0 18. The 8279 is used to ☐☐☐
c. ☐ if sign flag SF=1 a. ☐ Interface the CPU with the outside
d. ☐ if parity even PF = 1 world
16. IMUL is Used to ☐☐☐: b. ☐extends the interrupt levels of the CPU
a. ☐ multiply signed byte by byte/word by c. ☐ Interface the CPU with a keyboard
word d. ☐ be a coprocessor for the 8086
b. ☐ multiply unsigned byte by byte/word 19. The 8259 ☐☐☐
by word a. ☒ Interface the CPU with the outside
c. ☐ multiplex signed byte by byte/word by world
word b. ☐extends the interrupt levels of the CPU
d. ☐ rotate signed byte by byte/word by 1 c. ☐ Interface the CPU with a keyboard
position d. ☐ be a coprocessor for the 8086
17. SAR is used to ☐☐☐: 20. The USART ☐☐☐
a. ☐ to shift bits of a byte/word towards the a. ☐is mostly used than UART
right and put zero(S) in MSBs b. ☐support only asynchronous data
b. ☐ Used to invert each bit of a byte or transfer
word c. ☒Support only synchronous data transfer
d. ☒support both asynchronous and
synchronous data transfer