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The document provides an overview of a book about transistor circuit design published by Texas Instruments.

The book offers solutions to a wide range of basic engineering problems related to transistor circuit design.

Topics covered in the book include fundamental considerations of transistors, transistor circuit design techniques, and various transistor circuit applications.

The Engineering Staff of

TEXAS INSTRUMENTS INCII' lATE


Semic n ucter - Cem nents ivision

..'

Tr. . . sistor
CireD tDesign

McGraw-Hili
Transistor
Circuit
Design
Contributors

R. P. Abraham J. W. Kronlage
W. W. Bamsch A. G. Lambert
I. Berlin J. S. Lee
J. R. Biard G. Luecke
H. F. Cooke W. T. Matzen
R. H. Crawford P. M. Norris
R. T. Dean F. L. Opp
L. A. Delhom J. T. Pierce
G. E. Giles R. L. Pritchard
L. L. Glover J. E. Setliff
R. C. Grimes L. J. Sevin
D. B. Hall W. C. Tatom
L. K. Hill J. H. Taylor
S. W. Holcomb W. H. Tulloch
J. W. Huflhines J. P. Vergez
T. J. Huffington J. A. Walston
G. D. Johnson R. K. Walters
J. M. King E. C. Wilson
R. T. Windecker
Transistor
Circuit
Design

Prepared by the Engineering Staff of


Texas Instruments Incorporated

Edited by

Joseph A. Walston
Transistor Applications Manager

John R. Miller
Technical Publications Manager

McGraw-Hili Book Company, Inc.


New York Toronto London
TRANSISTOR CIRCUIT DESIGN

Copyright © 1963 by Texas Instruments Incorporated. All Rights


Reserved. Printed in the United States of America. This book, or parts
thereof, may not be reproduced in any form without permission of
the publishers. Library of Congress Catalog Card Number 62-19766.

63737

III
Preface

During its first decade as a transistor manufacturer, Texas Instruments Incor-


porated has received many thousands of requests for assistance with circuit design
problems. TI has responded to these queries by means of both personal communi-
cations and application bulletins having limited circulation. The pattern of recur-
ring inquiries which has emerged suggested both the need for this book and its
content.
"Transistor Circuit Design" was compiled for the practicing circuit design engi-
neer. It offers solutions to a wide range of basic engineering problems. A few of the
discussions are addressed to the tyro; most require a considerable degree of engi-
neering sophistication; all have proved to be of interest to our correspondents.
One volume cannot encompass discussions in depth of all design problems.
Accordingly, this edition is the first of a series-subject matter will be selected and
revised in response to recommendations from our readers and as required by
advances in the art. Although engineers throughout the Semiconductor-Compo-
nents division have contributed to this volume, TI's Transistor Applications branch
is responsible for its final form and will welcome suggestions and inquiries.

Information contained in this book is believed to be accurate and reliable.


However, responsibility is assumed neither for its use nor for any infringement of
patents or rights of others which may result from its use. No license is granted by
implication or otherwise under any patent or patent right of Texas Instruments or
others.

Texas Instruments Incorporated


Semiconductor-Components Division

v
Contents

Preface . ................................................... . v

Part 1. Fundamental Considerations

Classification of Junction
Transistors . ............................................. . 3
Bibliography ........................................... . 9
2 Device and Circuit Symbology. . . . . . . . . . . . . . . . . . . . . . . . . . 12

3 Transistor Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1. The Data Sheet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2. Transistor Numbering Systems. . . . . . . . . . . . . . . . . . . . . .. 26
3.3. Military Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 27
4 Nature of Transistor Quantities
and Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 29
4.1. D-C Quantities and Parameters. . . . . . . . . . . . . . . . . . . . .. 29
4.2. A-C Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 39
4.3. Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .. 51
4.4. Thermal Quantities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 55
Bibliography. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 58
5 Measurement of Electrical
Quantities and Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.1. D-C Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 59
5.2. Pulse Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 60
5.3. Small-signal Parameter Measurements and Test Circuits. 69
5.4. High-frequency Measurements. . . . . . . . . . . . . . . . . . . . . .. 72
5.5. Switching Time Measurements. . . . . . . . . . . . . . . . . . . . . .. 76
6 Equivalent Circuits and Parameter
Interrelationships. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 86

Part 2. D-C and Low-frequency Designs

7 Transistor Biasing . ....................................... 105


7.1. Establishing the Quiescent Operating Point. . . . . . . . . . .. 105
7.2. Heat Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 109
7.3. Thermal Stability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 110
Bibliography. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 122

vii
viii Contents

8 Direct-coupled Amplifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 124


8.1. Sources of Drift. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 124
8.2. Drift Equivalent Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 127
8.3. Single-ended Stage ................................ , 127
8.4. Differential Stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 133
8.5. Input Stage Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 135
8.6. Second-stage Drift. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 136
8.7. Two Design Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 136
9 Voltage Regulators ..................................... 145
9.1. Comparison Element. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 148
9.2. D-C Amplifier Element. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 151
9.3. ControlElement ................................... 151
9.4. Preregulator....................................... 154
9.5. Filling In the Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 156
9.6. Typical Voltage-regulator Design. . . . . . . . . . . . . . . . . . . .. 158
9.7. Performance Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . .. 162
9.8. Performance Analysis by Inspection. . . . . . . . . . . . . . . . .. 163
9.9. Performance Test Circuits. . . . . . . . . . . . . . . . . . . . . . . . . .. 165
Bibliography. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 166
10 Chopper Amplifiers ...................................... 168
10.1. DesignObjectives .................................. 168
10.2. Ring Modulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 169
10.3. Transistor Choppers-Practical Circuits .............. , 173
10.4. Photodiodes and Photo transistors . . . . . . . . . . . . . . . . . . .. 174
10.5. Modulated Carrier System. . . . . . . . . . . . . . . . . . . . . . . . .. 174
Bibliography. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 175
11 AGC of Audio Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 176

12 Low-frequency Harmonic Oscillators ...................... , 180


12.1. Criteria for Oscillation. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 180
12.2. Feedback Paths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 181
12.3. Design Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 183
13 Frequency Response and Stability
of Feedback Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 186

14 Operational Amplifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 193

15 Low-level Audio Stage Analysis. . . . . . . . . . . . . . . . . . . . . . . . . .. 197


15.1. Equivalent Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 199
15.2. Determination of h Parameters . . . . . . . . . . . . . . . . . . . . .. 199
15.3. Operating Point and Parameter Corrections ...... . . . .. 199
15.4. Gain and Output Power. . . . . . . . . . . . . . . . . . . . . . . . . . .. 200
15.5. A Completed Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 204
16 Class A Driver and Output Stages . . . . . . . . . . . . . . . . . . . . . . .. 206
16.1. The Ideal Amplifier ................................ 206
16.2. The Practicable Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . .. 207
16.3. Design Procedure .................................. 211
16.4. Design Example ................................... 213
Contents ix
17 Low-frequency Transformer-coupled
Class B Output Stages ................................ . 220
17.1. Distortion ....................................... . 220
17.2. Primary Design Considerations ..................... . 223
17.3. Base Bias Circuits ................ . 227
17.4. Output Transformer Design ........................ . 231
17.5. Driver Transformer Design ......................... . 231
17.6. A Typical Class B Design .......................... . 232

18 Servo Amplifiers. . . . . . . . . . . . . . . . . . . . . . . . . . . . ....... . 238


18.1. l.5-watt Class B Design ........................... . 240
18.2. 4.0-watt Class B Design ........................... . 241
18.3. 7.5-watt Class B Design ........................... . 242
18.4. lO-watt Class B Design ............................ . 243
18.5. 35-watt Class B Design ............................ . 244
18.6. 2-watt Design with High Efficiency .............. . 245
18.7. 6-watt Design with High Efficiency .............. . 248

Part 3. High-frequency Designs

19 Wideband or Video Amplifiers. . . . . . . . . . . . . . . . . . . . . . . . . .. 253


19.1. Negative Feedback ................................. 253
19.2. Frequency Characteristics of Yie, h'e, and Y'e . . . . . . . . . .. 255
19.3. Design Equations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 257
19.4. Single-stage vs. Multistage Operation. . . . . . . . . . . . . . . .. 260
19.5. Selecting the Direct Current and Voltage .............. 262
19.6. Design Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 263
19.7. Circuit Examples .................................. 266
Bibliography. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 271

20 Low-level RF Stage Stability .............................. 272


20.1. Unilatera1ization .................................. 272
20.2. Mismatching...................................... 278
Bibliography. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 297

21 Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
21.1. Transistor Noise Figure. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 298
21.2. Transistor Upper Noise-comer Frequency. . . . . . . . . . . .. 300
21.3. Experimental Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 302
Bibliography. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 306

22 RF Harmonic Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 307


22.1. Oscillator Configurations. . . . . . . . . . . . . . . . . . . . . . . . . .. 307
22.2. Tank Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 310
22.3. Active Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 313
22.4. Frequency Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 313
22.5. Oscillator Design Procedure. . . . . . . . . . . . . . . . . . . . . . . .. 315
22.6. Design Example ........................... , ....... 316
22.7. Additional Circuits and Performance ................. 319
Bibliography. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 320
X Contents
23 Frequency Heterodyning and
Multiplication ........................................... 321
23.1. VHF Mixers ...................................... 321
23.2. Frequency Doublers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 326
24 AGC of RF Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 329
24.1. Reverse AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 329
24.2. Forward AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 330
24.3. Mesa Characteristics ............................... 331
24.4. Maximum Available Power Gains .................... 334
24.5. D-C Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 341
24.6. Design Procedure .................................. 341
25 VHF Power Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 345
25.1. Selecting the Optimum Configuration ................. 345
25.2. Matching Networks ................................ 350
25.3. Design Example ................................... 351
26 Remote-control System ................................... 360
26.1. Transmitter....................................... 360
26.2. Receiver.......................................... 361
26.3. Adjustment Suggestions . . . . . . . . . . . . . . . . . . . . . . . . . . .. 362
26.4. Performance...................................... 365

Part 4. Switching-mode Designs


27 Switching Design Considerations .......................... 369
27.1. Worst-case D-C Design ............................. 369
27.2. Design Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 372
28 Digital Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. 373
28.1. Bistable (Flip-flop) Multivibrator .................... 373
28.2. Astable (Free-running) Multivibrator . . . . . . . . . . . . . . . .. 377
28.3. Monostable (One-shot) Multivibrator. . . . . . . . . . . . . . . .. 380
28.4. Schmitt Trigger .................................... 381
29 Logic Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 384
29.1. Saturated Transistor Logic Circuits. . . . . . . . . . . . . . . . . .. 384
29.2. Complementary Logic Circuits . . . . . . . . . . . . . . . . . . . . .. 398
~ ~M~ri~TI~~ .................................... ~
30.1. RC Time-base Generators .......................... 409
30.2. Design Examples .................................. 413
31 High-level Switching ..................................... 418
31.1. Power Dissipation ................................. 418
31.2. Load-line Analysis ................................. 419
Bibliography. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 422
32 Light Flashers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 423

33 Blocking Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 427


33.1. Common Emitter .................................. 427
33.2. Common Base. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 429
Bibliography. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 432
Contents xi
34 D-C Converters ........................................ . 433
34.1. Theory of Operation .............................. . 433
34.2. Transformer Considerations ........................ . 435
34.3. Transistor Considerations .......................... . 436
34.4. Starting ......................................... . 436
34.5. Circuit Configurations ............................. . 436
34.6. Practical Circuits ................................. . 438
Bibliography ........................................... . 446
35 Inverters ............................................... . 447
35.1. Frequency Stability ............................... . 448
35.2. Power Amplifier .................................. . 449
35.3. Design Procedure for 200 Watts at 60 Cycles ......... . 450
35.4. Additional Circuits ............................... . 456
Bibliography ........................................... . 461
36 Switching-mode Voltage Regulators ...................... . 463
36.1. Circuit Analysis .................................. . 463
36.2. D-C Controlled Multivibrator ...................... . 463
36.3. Driver Circuit. ................................... . 467
36.4. Series Switching Circuit ........................... . 470
36.5. Design Example .................................. . 473
37 Switching-mode Motor Control. . . . . . . . . . . . . . . . . . . . . . . . . .. 475
37.1. Advantages of Switching-mode Control .............. 475
37.2. Circuit Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 475
38 Switching-mode Servo Amplifier .......................... 481

39 Digital Servo System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 484


39.1. Analog vs. Digital Servomechanisms ................. 484
39.2. Description of System . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 485
39.3. Shaft-position Encoder. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 485
39.4. Gray-to-binary Converter. . . . . . . . . . . . . . . . . . . . . . . . . .. 487
39.5. Binary Comparator ................................ 487
39.6. Digital-to-analog Converter and Modulator. . . . . . . . . .. 488
39.7. Servo Amplifiers .................................. 492
39.8. System Stabilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 492

Appendix: Field-effect Transistor


Theory and Applications . ............................... 496
Part 1

Fundamental Considerations
Alloy Diffused or
Post Alloy Diffused
(PADn® r-- AII--'
L_~ita~I_J

Double-diffused
Double-diffused
Mesa or Diffused Epitaxial Mesa
Emitter and Base

Planar Planar Epitaxial

Electrochemical
Diffused Collector
(ECDC)

Surface-barrier (SBT) 1------1

Fig_ 1.1. Interrelationship of transistor fabricating techniques and transistor types.


1
Classification of Junction
Transistors

INTRODUCTION

Originally, junction transistors were made by one of two classical methods-the


grown-junction or the alloy-junction technique. During the past few years, how-
ever, a number of new types of transistors made by the diffusion technique have
become available, with a wide variety of descriptive names such as mesa and
planar; and more recently, the epitaxial type of transistor has been introduced. This
chapter classifies each of the transistors presently available into one of five major
categories, and describes briefly its method of construction.

CLASSICAL TECHNIQUES

The first junction transistors, of 1951, were of the grown-junction type. 1 ,2,*
This type comprises a rectangular bar, as shown in Fig. 1.2, cut from a germanium
crystal that has been grown from a melt to which suitable impurities have been
added. Emitter and collector contacts then are made to the base region, generally
located approximately midway between the two ends. Shortly after the grown-
junction technique was introduced, the alloy technique was developed;3 in this
technique, small dots of indium are fused, or alloyed, into opposite sides of a
germanium wafer of suitable conductivity, as illustrated in Fig. 1.3. Emitter and
collector contacts then are made to each of the dots, and the base contact is made
to the wafer. Silicon transistors also can be made by each of these two techniques.
Attempts to reduce the dimensions of alloy transistors for high-frequency use
subsequently led to the introduction of the electrochemical etching and plating
technique, which in turn led to the development of the surface-barrier transistor.4
Physically, the construction of this type of transistor is very similar to that of the
alloy transistor, except that depressions are etched into the wafer before the collector
and emitter dots are added, and the latter are generally of much smaller size than
in the conventional alloy transistor.
• Superscript numbers refer to bibliography entries at end of chapter.

3
4 Fundamental Considerations

e o--~ l@:iI---~ c

e~r~
_______~~____~ Oc

I
Fig. 1.2. Grown-junction-type transistor. Fig. 1.3. Alloy-junction-type transistor.

In each of these three classical methods of fabrication, the three regions of the
transistor-emitter, base, and collector-generally are of uniform resistivity.

DIFFUSION TECHNIQUE

The introduction of solid-state diffusion techniques has provided an additional


method, capable of a high degree of control, of making PN junctions and, hence,
of fabricating transistors. Moreover, the use of diffusion techniques makes it
possible to provide nonuniform emitter, base, and collector regions in such a manner
as to provide better transistor electrical characteristics than are obtainable from
the classical designs of uniform-resistivity regions.
Diffusion ofimpurities can take place from within the crystal,5 or through the
surface from an external source;6, 7 the latter process generally is termed gaseous
diffusion. It is also possible to combine diffusion techniques with one of the classical
techniques described above. For example, a nonuniform base region can be
obtained by diffusion, while the emitter and collector junctions can be made by the
alloy technique. 8 Alternatively, one PN junction can be formed by diffusion while
the other is formed by one of the classical techniques, or the entire transistor-i.e.,
the two PN junctions-also can be formed by diffusion.
As a result of this flexibility, transistors made by diffusion may assume anyone
of several different physical appearances. For example, some diffused transistors
are indistinguishable in appearance from corresponding classical structures. On

c
Cross section Top view Top view
(a) (b) (c)
Fig. 1.4. Mesa-type construction for diffused-base or double-diffused transistors: (a) cross sec-
tion; (b) top view; (c) top view.
Classification of Junction Transistors 5

the other hand, some types of diffusion transistors are of the mesa construction,
illustrated by Fig. lA, in which the semiconductor wafer is etched down in steps
so that the base and emitter regions appear as plateaus above the collector region.
Both rectangular and circular cross sections have been employed, as illustrated by
Fig. l.4b and c, respectively.

EPITAXIAL TECHNIQUE

More recently, a new technique-that of epitaxial deposition-has been devel-


oped.9 ,10 (Actually, this technique was known in the mid-1950 years, but only
since 1960 has it been applied to commercial devices.) In the epitaxial technique
as applied to transistors, a film of single-crystal semiconductor material is deposited
on a single-crystal substrate. Most of the work in epitaxial films to date has con-
sisted of depositing a layer of a semiconductor material on a substrate of the same
material-germanium on germanium or silicon on silicon. However, the deposited
epitaxial film may be of a different material from that of the substrate.
Thus far, the epitaxial technique has been used only to develop transistors in
which a thin, high-resistivity collector region is deposited on a low-resistivity sub-
strate of the same conductivity type: 10-12 a thin P-type collector region is deposited
on a P+ substrate for germanium PNP transistors, or a thin N-type collector
region is deposited on an N + substrate for NPN silicon transistors. This leads to
a family of transistors which will be termed here epitaxial collector, but known by
a variety of names, as, for example, diffused-base epitaxial mesa transistor. The
chief advantage of this type of transistor is lower saturation resistance and lower
collector storage time relative to a comparable nonepitaxial device.
However, the epitaxial technique is considerably more general, and it is possible
to deposit multiple layers of different conductivity type, to form epitaxial PN junc-
tions. For example, an N-type epitaxial collector can be deposited on an N +
substrate, followed by a P-type epitaxial-base-layer deposition. 9 , 13 The emitter
region then may be made by conventional diffusion technique or by the alloying
technique. This form of device (which is not yet commercially available) is termed
here the epitaxial-base transistor. Finally, it should be possible to extend the
epitaxial technique further to make a complete all-epitaXial transistor by epitaxially
depositing collector, base, and emitter layers. 9

PLANAR TECHNIQUE

The planar technique mentioned often in com-


mercial literature is an auxiliary technique for
making junctions by standard diffusion tech-
niques. Strictly speaking, the term planar refers
to a device in which each of the junctions-
emitter-base and collector-base in a transistor, as
shown in Fig. l.5-is brought to a common plane c
surface,14 as distinguished from the mesa struc- Fig. 1.5. Planar-type double-
ture in which one or more of the PN junctions diffused transistor.
6 Fundamental Considerations

is brought to the surface at the edge of a cylinder compnsmg the mesa, as


shown in Fig. l.4a. However, the real significance of the planar structure is
not that it is planar, per se. Rather, what is important is that, as a result of the
technique of diffusion through an oxide mask used in making a planar structure,
the junctions are formed beneath a protective oxide layer. Hence, many of the
surface problems associated with other types of transistors having junctions exposed
at the surface are avoided in this type of construction. As a result, the chief
advantage of this type of transistor is generally lower reverse currents and improved
d-c gain at low currents.
Note, however, that an equivalent structure could be fabricated in which the
junctions were formed beneath a protective oxide coating but which were not
actually planar.

CLASSIFICATION SCHEME

In this chapter, the transistor types are classified according to five major categories
-grown, alloy, electrochemical, diffusion, and epitaxial. The method of classifica-
tion employed is somewhat arbitrary- e.g., a grown-diffused transistor could be
classified as either a grown transistor or a diffused transistor! Accordingly, a
cross-referencing scheme is necessary and is provided here by means of the chart
fronting this chapter (Fig. 1.1). This chart illustrates the interrelationships among
the various techniques for producing different types of transistor structures.
Grown-junction Transistors (Fig. 1.2). DOUBLE-DOPED TRANSISTOR. The
original grown-junction transistor, formed by growing a crystal and successively
adding P- and N-type impurities to the melt during the course of growing the
crystal. 1
RATE-GROWN OR GRADED-JUNCTION TRANSISTOR. A variation of the double-
doped type described above, in which N- and P-type impurities are added to the
melt from which the crystal is grown. 15 ,16 The growth rate then is varied in a
periodic manner while the crystal is drawn from the melt. During one stage of the
growth cycle, the crystal contains a predominance of P-type impurities, whereas
during the other stage of the cycle, N-type impurities dominate, resulting in a crystal
from which NPN transistors can be cut.
MELT-BACK TRANSISTOR. A variation of the rate-grown transistor in which the
rate growing is performed on a very small physical scaleY This results in a lower
thermal time constant for the crystal-growing system, so that thinner base regions
and, hence, higher-frequency transistors can be obtained.
MELT-QUENCH TRANSISTOR. Very similar to melt-back transistor described
above. is
GROWN-DIFFUSED TRANSISTOR. A transistor made by combining diffusion tech-
niques and the double-doped process.1 9 In this case, suitable N- and P-type
impurities are added simultaneously to the melt during the course of growing the
crystal. Subsequently, the base region is fonned by diffusion during the continued
growth of the crystal.
MELT-BACK DIFFUSED TRANSISTOR. A transistor made by combining diffusion
Classification of Junction Transistors 7

techniques and the melt-back process, analogous to the combination of the grown
and diffusion techniques described above leading to grown-diffused transistors. 2o- 22
In this case, however, the impurities are added to the transistor bar by the melt-
back process, and the base region subsequently is formed by diffusion by baking
the transistor bar.
Alloy-junction Transistors (Fig. 1.3). ALLOY TRANSISTOR. Previously known
also as fused transistor, this comprises a wafer of semiconductor material of N - or
P-type conductivity with two dots containing P- or N-type impurities, respectively,
fused or alloyed into the wafer on opposite sides of the wafer to provide emitter and
base junctions, while the base region comprises the original semiconductor
wafer. 3, 23, 24
DRIFT TRANSISTOR.

1. In scientific literature, a drift transistor refers to a type of transistor having


a nonuniform, or graded, base region so that high-frequency response is
improved relative to a similar uniform-base structure. 25
2. Drift transistor, commercial: A trade name for a diffused-alloy transistor.8
DIFFUSED-ALLOY TRANSISTOR. A transistor made by combining diffusion and
alloy techniques. The semiconductor wafer first is subjected to a gaseous diffusion
to produce the nonuniform base region, and then alloy junctions are formed in
exactly the same manner as in a conventional alloy transistor.8 An intrinsic
region transistor, e.g., a PNIP unit, can be made by this technique by starting with
a semiconductor wafer of essentially intrinsic conductivity.
ALLOY-DIFFUSED TRANSISTOR, OR POST-ALLOY-DIFFUSED TRANSISTOR. Another
type of transistor made by combining diffusion and alloy techniques. In this type,
the alloy dot material contains both N- and P-type impurities. Then the emitter-
base junction is formed by the conventional alloy process, while the base region
is formed by diffusion from within the crystal. (N ote that this is the distinction
between the diffused-alloy transistor described above and the post-alloy-diffusion
technique.) The collector region comprises the original semiconductor wafer. 5, 26, 27
Alternatively, if the original wafer is of the same conductivity type as the base
region, then the emitter-base junction and the base region can be formed as
described above, while the collector junction can be formed as in a conventional
alloy transistor. 28 In this case, as in the diffused-alloy transistor, an intrinsic
region can be included between base and collector.
Electrochemically Etched and Plated Transistors (Fig. 1.3). SURFACE-BARRIER
TRANSISTOR (SBT). Comprises a wafer of semiconductor material into which depres-
sions have been etched on opposite sides of the wafer by electrochemical tech-
niques. 4 The emitter and collector base junctions, or metal-semiconductor contacts,
then are formed by electroplating a suitable metal on the semiconductor in the
depression areas on opposite sides of the wafer, while the original wafer constitutes
the base region.
MICROALLOY TRANSISTOR (MAT). A variation of the surface-barrier transistor
described above in which suitable N- or P-type impurities are first plated in the
etched depressions and then alloyed into the P- or N-type semiconductor wafer.29
SILICON-ALLOY TRANSISTOR, OR SURFACE-ALLOY TRANSISTOR (SAT). A variation
8 Fundamental Considerations

of the surface-barrier transistor described above in which a suitable metal (alumi-


num) is first evaporated into the etched depressions and then alloyed into the
N-type semiconductor wafer. 30 - 31
MICROALLOY DIFFUSED TRANSISTOR (MADT). A transistor made by incorporating
diffusion techniques with the microalloy transistor construction described above.
The semiconductor wafer first is subjected to a gaseous diffusion to provide a non-
uniform base region before the electrochemical plating process. 32 , 33
ELECTROCHEMICAL DIFFUSED COLLECTOR (ECDC) TRANSISTOR.34 A transistor made
by combining diffusion and electrochemical techniques. A nonuniform base region
and the collector-base junction are obtained by gaseous diffusion into a semicon-
ductor wafer that constitutes the collector region. Then the emitter-base junction
is obtained by the use of the electrochemical etch and plating technique, as in the
MAT. The electrochemical technique also is used to place the collector contact close
to the collector-base junction.
Diffusion Transistors (Fig. 1.4). DIFFUSED-BASE TRANSISTOR. Another type
of transistor made by combining diffusion and alloy techniques. A nonuniform
base region and the collector-base junction are formed by gaseous diffusion into a
semiconductor wafer that constitutes the collector region. Then the emitter-base
junction is formed by a conventional alloy junction on the base side of the diffused
wafer, by evaporation of a metallic stripe, for example, while the remaining portion
of the original wafer constitutes the collector region. 6, 35, 36
DIFFUSED-EMITTER AND BASE OR DOUBLE-DIFFUSED MESA TRANSISTOR. Comprises
a semiconductor wafer which has been subjected to gaseous diffusion of both N-
and P-type impurities to form two PN junctions in the original semiconductor
material. 7,37-39 The active area of the transistor (the area of the collector-base
junction) is then defined by etching away the undesired portions of the emitter and
base regions to expose a mesa (see Fig. l.4a). An intrinsic-region transistor, e.g.,
PNIP, also can be made by a variation of this process. 40
TRIPLE-DIFFUSED TRANSISTOR. A variation of the double-diffused transistor in
which the semiconductor wafer first is subjected to a deep diffusion to effectively
lower the resistivity of the collector region-e.g., to form an NN + structure for
an NPN transistor. 41 -43 The NN + wafer is then subjected to gaseous diffusion
of both P- and N-type impurities to form emitter-base and collector-base junctions
leading to an NPNN + structure. Alternatively, this may be considered as an
intrinsic-region transistor, for example, NPIN, if the original semiconductor wafer
is of very high resistivity.40
PLANAR TRANSISTOR. Comprises a semiconductor wafer which has been sub-
jected to gaseous diffusion of both P- and N-type impurities to form two PN junc-
tions in the original semiconductor material, as in the diffused-emitter and base
transistor. In this case, however, the active area of the device-i.e., the area of the
collector-base junction-is defined by oxide masking of the base diffusion, rather
than by mesa etching (see Fig. 1.5).14,44,45
Epitaxial Transistors. DIFFUSED-BASE EPITAXIAL MESA TRANSISTOR. One of the
epitaxial-collector transistor family. This transistor is made by combining diffusion,
alloy, and epitaxial techniques. First, a thin collector region is epitaxially deposited
upon a low-resistivity substrate. Then a nonuniform base region and the collector-
base junction are formed by gaseous diffusion into the epitaxial collector region.
Classification of Junction Transistors 9

The emitter-base junction is obtained from a conventional alloy junction on the


base side of the diffused wafer. 10, 11
DOUBLE-DIFFUSED EPITAXIAL MESA TRANSISTOR. Another of the epitaxial-collec-
tor transistor family. A thin collector region is epitaxially deposited upon a low-
resistivity substrate. Then base and emitter regions are formed as in an ordinary
double-diffused mesa transistor, and the collector-base junction area is defined by
etching a mesa.1O-12
PLANAR EPITAXIAL TRANSISTOR. Another of the epitaxial-collector transistor
family. A thin collector region is first epitaxially deposited on a low-resistivity
substrate. Then base and emitter regions are formed in the same manner as in the
conventional planar transistor as described above.
EPITAXIAL-BASE TRANSISTOR. A transistor made by epitaxially depositing a base
region of one conductivity type upon a collector region of the opposite conductivity
type. The emitter region then can be formed either by alioying or by diffusing,
leading, respectively, to an alloy-emitter epitaxial-base transistor or a diffused-
emitter epitaXial-base transistor. 9 , 13
ALL-EPITAXIAL TRANSISTOR. In this case, all three regions of the transistor are
obtained by epitaxial deposition. 9

ACKNOWLEDGMENT

The material presented here by no means describes original work. A number


of other semiconductor-device workers have categorized transistors in schemes
similar to that described above. In this connection, R. N. Hall,46 G. C. Dacey and
C. D. Thurmond,47 and P. Kaufmann and G. Freedman48 have written excellent
survey papers describing the methods used to fabricate transistors, in terms of the
metallurgy of PN junctions, in considerably more detail than is presented here.
The concept of the chart shown in Fig. 1.1 originated with Harry L. Owens.

BIBLIOGRAPHY

l. Shockley, w., M. Sparks, and G. K. Teal: p-n Junction Transistors, Phys. Rev., vol. 83,
pp. 151-162, July, 1951.
2. Wallace, R. L., Jr., and W. J. Pietenpol: Some Circuit Properties and Applications of
n-p-n Transistors, Bell System Tech. J., vol. 30, pp. 530-563, July, 1951. Also Proc. IRE,
vol. 39, pp. 753-767, July, 1951.
3. Saby, J. S.: Recent Developments in Transistors and Related Devices, Tele-Tech, vol.
10, pp. 32-34, 58, December, 1951.
Saby, J. S.: Fused Impurity p-n-p Junction Transistors, Proc. IRE, vol. 40, pp. 1358-
1360, November, 1952.
4. Bradley, W. E.: Part I, Principles of the Surface-barrier Transistor, Proc. IRE, vol. 41,
pp. 1702-1706, December, 1953. Tiley, J. w., and R. A. Williams: Part II, Electro-
chemical Techniques for Fabrication of Surface-barrier Transistors, ibid., pp. 1706-1708.
Angell, J. B., and F. P. Keiper: Part III, Circuit Applications of Surface-barrier Transis-
tors, ibid, pp. 1709-1712.
5. Beale, J. R. A.: Alloy-diffusion: a Process for Making Diffused-base Junction Transis-
tors, Proc. Phys. Soc., vol. 70B, pp. 1087-1089, November, 1957.
10 Fundamental Considerations

6. Lee, C. A.: A High-frequency Diffused-base Germanium Transistor, Bell System Tech.


J., vol. 35, pp. 23-24, January, 1956.
7. Tanenbaum, M., and D. E. Thomas: Diffused Emitter and Base Silicon Transistors, Bell
System Tech. J., vol. 35, pp. 1-22, January, 1956.
8. Kestenbaum, A. L., and N. H. Ditrick: Design, Construction, and High-frequency Per-
formance of Drift Transistors, RCA Rev., vol. 18, pp. 12-23, March, 1957.
9. O'Rourke, M. J., J. C. Marinace, R. L. Anderson, and W. H. White: Electrical Proper-
ties of Vapor-grown Germanium Junctions, IBM J. Research and Development, vol. 4,
pp. 256-263, July, 1960.
10. Sigler, John, and S. B. Watelski: Epitaxial Techniques in Semiconductor Devices, Solid-
State J., voL 2, pp. 33-37, March, 1961.
11. Theurer, H. C., J. J. Kleimack, H. H. Loar, and H. Christensen: Epitaxial Diffused
Transistors, Proc. IRE, vol. 48, pp. 1642-1643, September, 1960.
12. Valdes, L. B.: Characteristics of Silicon Epitaxial Transistors, Solid-State J., vol. 2, pp.
33-36, November, 1961.
13. Clifton, J. K., and H. M. Robertson: A Transistor Utilizing an Epitaxially Grown Base
and Collector Region, paper presented at Electron Devices Meeting, Washington, D.C.,
Oct. 26, 1961.
14. Hoerni, J. A.: Planar Silicon Diodes and Transistors, abstract only, IRE Trans., voL
ED-8, p. 178, April, 1961.
15. Hall, R. N.: p-n Junctions Produced by Growth Rate Variation, Phys. Rev., vol. 88, p.
139, October, 1952.
16. Bridgers, H. E., and E. D. Kolb: Rate-grown Germanium Crystals for High-frequency
Transistors, J. Appl. Phys., vol. 26, pp. 1188-1189, September, 1955.
17. Hall, R. N.: Unpublished material presented in June, 1955. See also Baker, D. W.:
High-frequency Germanium NPN Tetrode, 1956 IRE Conv. Record, part III, pp. 143-
150.
18. Pankove, J. 1.: Transistor Fabrication by the Melt-Quench Process, Proc. IRE, vol. 44,
pp. 185-188,January, 1956.
19. Cornelison, B., and W. A. Adcock: Transistors by Grown-diffused Technique, 1957 IRE
WESCON Conv. Record, part III, pp. 22-27.
20. Statz, H., W. Leverton, and J. Spanos: Unpublished material presented in 1955.
21. Lehovec, K., and A. Levitas: Fabrication of Multiple Junctions in Semiconductors by
Surface Melt and Diffusion in the Solid State, J. Appl. Phys., vol. 28, pp. 106-109,
January, 1957.
22. Phillips, A. B., and A. N. Intrator: A New High-frequency n-p-n Silicon Transistor,
1957 IRE Conv. Record, part III, pp. 3-13.
23. Law, R. R., C. W. Mueller, J. 1. Pankove, and L. D. Armstrong: A Developmental Ger-
manium P-N-P Junction Transistor, Proc. IRE, vol. 40, pp. 1352-1357, November, 1952.
24. Mueller, C. W., and J. 1. Pankove: A p-n-p Triode Alloy-junction Transistor for Radio-
frequency Amplification, RCA Rev., vol. 14, pp. 586-598, December, 1953. Also Proc.
IRE, vol. 42, pp. 386-391, February, 1954.
25. Kromer, H.: Zur Theorie des Diffusions- und des Drift-transistors, parts I, II and III,
Arch. Elekt. Ubertr., vol. 8, pp. 223-228, 363-369, 499-504, May, August, November,
1954.
Kromer, H.: The Drift Transistor, "Transistors I," pp. 202-220, RCA Laboratories,
Princeton, N.J., 1956.
26. Jochems, T. J. W., O. W. Memelink, and L. J. Tummers: Construction and Electrical
Properties of a Germanium Alloy-diffused Transistor, Proc. IRE, vol. 46, pp. 1161-1165,
June, 1958.
Classification of Junction Transistors 11

27. Edlinger, w.: High Frequency Transistor by the Alloy-diffusion Technique (in English),
Colloq. intern. sur les dispositifs a semiconducteurs, vol. 1, pp. 209-215, Editions Chiron,
Paris, 1961.
28. Lamming, J. S.: A High-frequency Germanium Drift Transistor by Post Alloy Diffusion,
J. Electronics and Control, vol. 4, pp. 227-236, March, 1958.
29. Rittmann, A D., G. C. Messenger, R. A Williams, and E. Zimmerman: Microalloy
Transistor, IRE Trans., vol. ED-5, pp. 49-54, April, 1958.
30. Rittmann, A D., and T. J. Miles: High Frequency Silicon Alloy Transistor, IRE Trans.,
vol. ED-3, pp. 78-82, April, 1956.
31. Thornton, C, J. Roshen, and T. Miles: An Improved High-frequency Transistor, Elec-
tronic Inds., Tele-Tech, vol. 16, pp. 47-49, 124, July, 1957.
32. Thornton, C G., and J. B. Angell: Technology of Micro-alloy Diffused Transistors, Proc.
IRE, vol. 46, pp. 1166-1176, June, 1958.
33. McCotter, J. D., M. J. Walker, and M. M. Fortini: A Coaxially Packaged MADT for
Microwave Applications, IRE Trans., vol. ED-8, pp. 8-12, January, 1961.
34. Bouchard, J. G. F.: The Electrochemical Diffused-collector Transistor, Proc. Nat!. Elec-
tronics Conf, vol. 17, pp. 242-249, 1961.
35. Warner, R. M., Jr., G. T. Loman, and J. M. Early: Characteristics, Structure, and Per-
formance of a Diffused-base Germanium Oscillator Transistor, IRE Trans., vol. ED-5,
pp. 127-130, July, 1958.
36. Talley, H. E.: A Family of Diffused-base Germanium Transistors, IRE WESCON Conv.
Record, vol. 2, part III, pp. 115-121, 1958.
37. Wolff, E. A., JT.: 50 Watt Silicon Diffused Power Transistor, IRE WESCON Conv. Rec-
ord, part III, pp. 40-47, 1957.
38. Aschner, J. F., C. A Bittman, W. F. J. Hare, and J. J. Kleimack: A Double-diffused
Silicon High-frequency Switching Transistor Produced by Oxide Masking Techniques,
J. Electrochem. Soc., vol. 106, pp. 413-417, May, 1959.
39. Little, W. A: A PNP High-frequency Silicon Transistor, J. Electrochem. Soc., vol. 107,
pp. 789-791, September, 1960.
40. Iwerson, J. E., J. T. Nelson, and F. Keywell: A Five-watt, Ten-megacycle Transistor,
Proc. IRE, vol. 46, pp. 1209-1215, June, 1958.
41. Buie, J. F.: A High-frequency Silicon, NPIN, Oscillator Transistor, abstract only, IRE
Trans., vol. ED-6, p. 244, April, 1959.
42. Bosenberg, W. A., and A L. Kestenbaum: A Developmental High-frequency Silicon
Transistor, abstract only, IRE Trans., vol. ED-6, p. 244, April, 1959.
43. Roach, W. E.: Designing High-power Transistor Oscillators, Electronics, vol. 33, pp.
52-55, Jan. 8, 1960.
44. Allison, D. F., R. H. Beeson, and R. M. Schultz: KMC/s Planar Transistors in Micro-
watt Logic Circuitry, Solid State Electronics, vol. 3, no. 2, pp. 134-141; September, 1961.
45. Grinich, V. H., and J. A. Hoerni: The Planar Transistor Family (in English), Colloq.
intern. sur les dispositifs a semiconducteurs, vol. 1, pp. 132-142, Editions Chiron, Paris,
1961.
46. Hall, R. N.: Fabrication Techniques for High-frequency Transistors (in English), Fortschr.
Hochfrequenztechnik, vol. 4, pp. 129-155, Akademische Verlagsgesellschaft m.b.H.,
Frankfurt am Main, 1959.
47. Dacey, G. C., and C. D. Thurmond: p-n Junctions in Silicon and Germanium: Princi-
ples, Metallurgy, and Applications, Met. Rev., vol. 2, pp. 157-192, June, 1957.
48. Kaufmann, P., and G. Freedman: An Analysis of Impurity Distributions and the Rela-
tion to Electrical Behavior of Conventional Transistor Constructions, Semiconductor
Prods., vol. 2, part I, pp. 17-23, April, 1959; part II, pp. 26-31, May, 1959.
2
Device and Circuit Symbology

Texas Instruments Incorporated, as a member of both EIA and NEMA, supports


and adheres to the standards established by these associations. Accordingly, EIA
document RS-245 is reproduced here with the permission of EIA, to assist the
reader in interpreting symbols and abbreviations as used by TI in its technical
publications.

12
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LEITER SYMBOLS AND

ABBREVIATIONS FOR
Published by
SEMICONDUCTOR DATA
ELEC1'RONIC INDUSTRIES ASSOCIATION

EJ18ineerin@: Department
SHEETS AND SPECIFICATIONS
II We.t 42nd Street, New York 36, N. Y.

NATIONAL ELEC1'RlCAL MANUFACTlJREIIS ASSOCIATION

155 E..t 44th Street, New York 17, N. Y.


(Approved by ~EMA as a ~EMA Standard on 9.'29/60)

ELECTRONIC INDUSTRIES ASSOCIATION


STANDARD R8-245
COPfdght 1961 by EI""tronic Ind~,t~ie" A,"oel~l;"n Bnd
NATIONAL ELECTmCAL MANUFACTURERS ASSOCIATION N ..tion.l ElectriC,,] Manuf.ctu,..,.o A.."';o.tI,,n
PUBUCATION No. SK 53 - 1961

Price $.80

OJ Formulated by

JEDEC Semiconductor Device Council


JEDEC RECOMMENDED LETI'ER SYMBOLS AND ABBREVIATIONS
FOR SEMICONDUCTOR DATA SHEETS AND SPECIFICATIONS
(This Standard was formulated under the cognizance of JEDEC Committee JS-12
on Military Specifications)

INTRODUCTION
This list of recommended letter symbols and abbreviations is the result of work of JS-12, Com-
mittee on Military Specifications. Published standards of the American Standards Association,
Institute of Radio Engineers and the American Institute of Electrical Engineers, Military Standards,
and common usage were all considered in the preparation. The U. S. delegates to the International
Electrotechnical Commission were consulted during the preparation, and the standards adopted by
that group are in close agreement with this list.
It is intended that the list be reviewed from time to time for additions, deletions or revisions as
progress in the field dictates.

CRITERIA AND CONVENTIONS FOR LETTER SYMBOLS


A letter symbol is a character which is used to designate an electrical or physical quantity or an
electrical parameter. This use occurs most frequently in mathematical equations (and specifica-
tions). Two or more symbols printed together represent a product (multiplication). Letter symbols
are distlnguished from abbreviations; the latter are used for the units of measurement of the quan-
tities or parameters. The chart shown below will illustrate this point.

UNIT OF
QUANTITY LETTER SYMBOL MEASUREMENT ABBREVIATION
Current I, i Amper€' AMP, amp or A, a'
Voltage V, vor E, e Volt V,v
Resistance R,r Ohm OHM, ohm or n'
Capacitance C,c Farad F,f
Inductance L (upper-case only) Henry H,h
Time t (lower-case only) Second SEC, sec
Temperature T (upper-case only) Degree I DEG,deg'

1 The abbreviation A or a is used with the metric system of multiplier prefixes, for example, J.l.A or J.&a for microampere.
2 Ohm should not be abbreviated in text. The abbreviation "0" may be used elsewhere with the metric system of mul-
tiplier prefInL
3 The abbreviation DEG or deg is not used in combination with the abbreviations for temperature seales. The abbre-
viation "0,, is usually used as the combining form for the word degree, for example, °C for degree Centigrade.

1. Letter Symbols for Electrical or Physical Quantities or Electrical Parameter.


a. Primary symbol: The letter symbol used to designate a quantity or parameter shall be a single
letter. This single letter, referred to as the primary symbol, may be modified by subscripts or
superscripts.
EXCEPTIONS:
The symbol BV for breakdown voltage, which has become accepted through long usage, has been
continued.
Symbols for frequency cutoff parameters, such as fhl' for small-signal short-circuit forward current
transfer ratio cutoff frequency (common emitter), have been formed to provide a consistent method
of establishing frequency cutoff symbols for other parameters, such as the y's and z's.
b. Secondary symbol: A SUbscript or superscript, referred to as the secondary symbol, may be
used to modify the primary symbol. The secondary symbol is used to designate special values of
states, points, parts, times, etc. An abbreviation may be used as a subscript (secondary symbol).
c. A letter symbol containing both primary and secondary letters has a unique meaning. This
meaning is not necessarily the meaning associated with the primary symbol alone, the secondary
symbol alone, or a combination meaning formed from both.

14
d. Descriptive information concerning a letter symbol may be added in parentheses after the
secondary symbol but on the same level as the primary symbol. Examples: hi. (real) and reE (sat).
The abbreviations rms, max, dc and avg are excluded from the above as this type of information is
to be presented as part of the secondary symbol without parentheses. (See paragraph 1f below)
e. Principles of application:
PRIMARY SYMBOLS

Use lower-case letters for: Use upper-ease letters for:

1. Instantaneous value of current, volt- 1. RMS, maximum, and average (de)


age, and power which vary with time. values of current. voltage. and power.
Example: i, v, p. (See Figure 1.) Examples: I, V, P. (See Figure 1.)
2. Values of four-pole matrix parameters 2. Values of four-pole matrix parameters
(ratios of terminal electrical quanti- (ratios of terminal electrical quanti-
ties), or other resistances, im pedances, ties), or other resistances, impedances,
admittances, etc., inherent in the de- admittances, etc., in the external c;r-
vice. Examples: hIB' rb, Ztb, y". cuits. Examples: Roo Z" Yo'

SECONDARY SYMBOLS
Use lower-case letters for: Use upper-case letters for:

1. Instantaneous varying component val- l. Instantaneous total values, maximum


ues and rms or effective varying com- values, and average (dc) values. Ex-
ponent values. Examples: i" I,. amples: ic, I CMAX, Ic.
2. Small signal values of parameters: Ex- 2. Static values and large signal values of
amples: rb, Yc, h jb, Zob, h th• parameters. Examples: rB, bIB, hFRa

Ie max (VARYING
COMPONENT VALUE)

Ie rms (VARYING
COMPONENT VALUE

Iemax
(TOTAL VALUE)

Ie AVG
Ie (WITH SIGNAL)
(NO SIGNAL) le (INSTANTANEOUS
TOTAL VALUE)

TIME
Figure 1. Chari of Collector Current Versus Time

15
f. Additional conventions for secondary symbols:
(1) If necessary to distinguish between .maximum, average, or root-mean-square values, the
appropriate abbreviation may be used as a subscript. Examples: I ...... ICAl"G, I"....
(2) Electrode abbreviations used as subscripts shall be as shown below:
E, e = emitter electrode
=
B, b base electrode
=
C, c collector electrode
J, j= electrode, general
The use of upper-case letters and lower-case letters for electrode abbreviations shall conform to the
following chart :
ELECTRODE ABBR
FOR USE AS
SYMBOL SIGNIFICANCE SUBSCRIPT
i,v, p Instantaneous varying
component value e, b, c.j
i,v,p Instantaneous total
value E,B,C,J
I, V, P RMS or effective vary-
ing component value e, b, c,j
I, V, P Maximum or average
(dc) value E,B,C,J
(3) The first subscript or subscript pair in matrix notation, identifies the element of the
four-pole matrix:
i or 11 = input
=
o or 22 output
=
for 21 forward transfer
=
r or 12 reverse transfer
(4) The second subscript or the subscript following the numeric pair identifies the circuit
configuration:
e = common emitter
=
b common base
=
c common collector
=j common electrode, general
2. TypeFeee
a. In textbooks and technical magazines, the use of italic type is recommended for letter symbols
and letter subscripts, whether upper or lower case. Numerals appearing as subscripts shall be
printed in roman type.
b. In specifications and technical reports prepared on a typewriter and intended for reproduc-
tion by a photo-offset process, the use of conventional typewriter type faces is recommended for letter
symbols and letter subscripts, whether upper or lower case, and for numerals appearing as subscripts.

CRITERIA AND CONVENTIONS FOR ABBREVIATIONS


An abbreviation is a shortened form of a word or word combination. Abbreviations do not en-
compass letter symbols or graphical symbols.
1. Short Word•. Short words are not usually abbreviated unless their abbreviations have been
established by long practice.
2. Spaeiug. An abbreviation is usually written with no spaces left between the letters of the abbre-
viation. The use of hyphens and slant bars is avoided where practicable.
3. Use of Period.. Periods are used only to avoid misinterpretation of an abbreviation.
4. Lettering. Upper-case or lower-case letters may be used as appropriate except where the use of
a partiCUlar case has been established by long practice. A multiletter abbreviation will not be a
mixture of upper-case and lower-case letters.
5. Sob&eripl8 and Supeneripl8. . Subscripts and superscripts are not used in abbreviations.
6. Clerit}'. Abbreviations shall be used only when their meanings are unquestionably clear. WHEN
IN DOUBT, SPELL IT OUT.
1. Word Comhinatiou. Abbreviations or word combinations shall be used as such and shall not be
separated for use singly.
8. Tenae aud Number. The same abbreviation shall be used for all tenses, and the singular and
plural forms of a given word.

--
9. Type Feee. Abbreviations and numerals shall be printed in roman type.

-----~

16
- - -- - - - ----
SYMBOLS AND ABBREVIATIONS FOR SEMICONDUCTOR DEVICES

B, b base electrode
bo when multiple base electrodes are present, each is numbered in sequence (bI, b2 ... )
BVCBO breakdown voltage, collector to base, emitter open
BV CEO breakdown voltage, collector to emitter, base open
BVcER breakdown voltage, collector to emitter, with specified resistance between base and emitter
BVCEO breakdown voltage, collector to emitter, with base short-circuited to emitter
BVEBO breakdown voltage, emitter to base, collector open
BVR breakdown voltage, reverse
C, c collector electrode
Ct. input capacitance (common base)
Cte input capacitance (common collector)
Ct. input capacitance (common emitter)
Co. output capacitance (common base)
Cae output capacitance (common collector)
C.. output capacitance (common emitter)
E, e emitter electrode
f hr• small-signal short-circuit forward current transfer ratio cutoff frequency
(common base)
f"e small-signal short-circuit forward current transfer ratio cutoff frequency
(common collector)
f.,. small-signal short-circuit forward current transfer ratio cutoff frequency
(common emitter)
f mas maximum frequency of oscillation
GPB large-signal average power gain (common base)
Gpb small-signal average power gain (common base)
Grc large-signal average power gain (common collector)
Gpe small-signal average power gain (common collector)
GPE large-signal average power gain (common emitter)
Gpo small-signal'average power gain (common emitter)
hFn static value of the forward current transfer ratio (common base)
hlb small-signal short-circuit forward current transfer ratio (common base)
hFo static value of the forward current transfer ratio (common collector)
h'e small-signal short-circuit forward current transfer ratio (common collector)
h"E static value of the forward current transfer ratio (common emitter)
hie small-signal short-circuit forward current transfer ratio (common emitter)
h'B static value of the input resistance (common base)
hi. small-signal value of the short-circuit input impedance (common base)
hIO static value of the input resistance (common collector)
hie small-signal value of the short-circuit input impedance (common coilector)
hm static value of the input resistance (common emitter)

17
hi. small-signal value of the short-circuit input impedance (common emitter)
hi. (real) real part of the small-signal value of the short-circuit input impedance (common emitter)
hOB static value of the open-circuit output conductance (common base)
h.b small-signal value of the open-circuit output admittance (common base)
hoo static value of the open-circuit output conductance (common collector)
h.. small-signal value of the open-circuit output admittance (common collector)
hoE static value of the open-circuit output conductance (common emitter)
h.. small-signal value of the open-circuit output admittance (common emitter)
h.b small-signal value of the open-circuit reverse voltage transfer ratio (common base)
h", small-signal value of the open-circuit reverse voltage transfer ratio (common collector)
h.. small-signal value of the open-circuit reverse voltage transfer ratio (common emitter)
I, i region of a device which is intrinsic and in which neither holes nor electrons predominate
IB base current (dc)
Ib base current (rms)
ib base current (instantaneous)
10 collector current (dc)
Ie collector current (rms)
ie collector current (instantaneous)
lOBO collector cutoff current (dc), emitter open
lOEO collector cutoff current (dc), base open
ICEB collector cutoff current (dc), with specified resistance between base and emitter
lCEX collector current (dc), with specified circuit between base and emitter
ICES collector cutoff current (dc), with base short-circuited to emitter
IE emitter current (dc)
I. emitter current (nus)
i. emitter current (instantaneous)
lEBO emitter cutoff current (de), collector open
IF forward current (dc)
iF forward current (instantaneous)
10 average output (rectified) current
la reverse current (de)
ia reverse current (instantaneous)
Ke thermal derating factor
L. conversion loss
N, n region of a device where electrons are the majority carriers
NF noise figure
P, p region of a device where holes are the majority carriers
PRE total power input (dc or average) to the base electrode with respect to the emitter electrode
PBE total power input (instantaneous) to the base electrode with respect to the emitter electrode
POB total power input (dc or average) to the collector electrode with respect to the
base electrode

18
PCB total power input (instantaneous) to the collector electrode with respect to the
base electrode
PCB total power input (dc or average) to the collector electrode with respect to the
emitter electrode
PeE total power input (instantaneous) to the collector electrode with respect to the
emitter electrode
P EB total power input (dc or average) to the emitter electrode with respect to the
base electrode
PEB total power input (instantaneous) to the emitter electrode with respect to the
base electrode
PIB large-signal input power (common base)
P 'b small-signal input power (common base)
PIC large-signal input power (common collector)
P" small-signal input power (common collector)
PIE large-signal input power (common emitter)
P,. small-signal input power (common emitter)
POB large-signal output power (common base)
P ob small-signal output power (common base)
Poe large-signal output power (common collector)
P., small-signal output power (common collector)
POE large-signal output power (common emitter)
P De small-signal output power (common emitter)
PT total power input (dc or average) to all electrodes
PT total power input (instantaneous) to all electrodes
R. external base resistance
Rc external collector resistance
rCE(sat) collector to emitter saturation resistance
RE external emitter resistance
RL load resistance
T temperature
TA ambient temperature
TC case temperature
t. delay time
1;, fall time
1;" forward recovery time
TJ junction temperature
Top, operating temperature
to pulse time
1;, rise time
1;" reverse recovery time
t. storage time
T... storage temperature

19
1;" pulse average time
6 thermal resistance
6'_A thermal resistance, junction to ambient
6'-0 thermal resistance, junction to case
VBB base supply voltage (dc)
VBO base to collector voltage (de)
V"" base to collector voltage (rms)
v"" base to collector voltage (instantaneous)
VBE base to emitter voltage (dc)
Vbe base to emitter voltage (rms)
Vbe base to emitter voltage (instantaneous)
VOB collector to base voltage (de)
Ve• collector to base voltage (rms)
ve• collector to base voltage (instantaneous)
Vco collector supply voltage (de)
VOE collector to emitter voltage (dc)
Vee collector to emitter voltage (rms)
Vee collector to emitter voltage (instantaneous)
VOE (sat) collector to emitter saturation voltage
VEB emitter to base voltage (dc)
V.. emitter to base voltage (rms)
v.. emitter to base voltage (instantaneous)
VEO emitter to collector voltage (dc)
V.. emitter to collector voltage (rms)
Vee emitter to collector voltage (instantaneous)
VEE emitter supply voltage (dc)
Vr forward voltage (dc)
v" forward voltage (instantaneous)
VORr dc open-circuit voltage (floating potential) between the collector and base, with the emitter
biased in the reverse direction with respect to the base
VECII' dc open-circuit voltage (floating potential) between the emitter and collector, with the base
biased in the reverse direction with respect to the collector
VaT reach through voltage
Va reverse voltage (dc)
Va reverse voltage (instantaneous)

20
3
Transistor Specifications

3.1. THE DATA SHEET

The transistor circuit designer must rely heavily upon the manufacturer's data
sheets for device information. It is therefore the manufacturer's responsibility to
present extensive design data in the simplest possible form.
Considerable thought goes into the layout of today's well-prepared, informative
data sheet. This section presents a general discussion of Texas Instruments data
sheets, detailing the information normally given and where it may be found. In
Chaps. 4, 5, and 6, each parameter normally found on a data sheet is discussed in
detail. IRE symbol notation for transistors and their associated circuitry is also
presented.
Data sheets published by Texas Instruments normally consist of eight sections.
A brief description of the device is given, followed by sections on environmental
tests, mechanical data, absolute ratings, electrical characteristics, and typical char-
acteristic curves. Typical application data and parameter measurement information
are usually included.
A typical Texas Instruments data sheet is reproduced here. Its numbered parts
are analyzed as follows:

21
N·P·N TYPES 2N1302, 2N1304, 2N1306, AND 2N1308 ~
P·N·P TYPES 2N1303, 2N1305, 2N1307, AND 2N1309 N·P·N TYPES 2N1302, 2N1304, 2N1306, AND 2N130B
COMPLEMENTARY ALLOY·JUNalON GERMANIUM TRANSISTORS COMPLEMENTARY ALLOY ·JUNCTION GERMANIUM TRANSISTORS

'"'" :!'i ELECTRICAL CHARACTERISTICS AT 2S"C AMBIENT TEMPERATURE (unle" otherwise noted)

§~~;
~~ji
PAlAMlTH AND liST CONDtTtoNI
Min
'"
Jl'P ...
.... Milo T,,, M ••
M.. Mh. T)7 Moo..
Moo .. Mioo
Mioo ,' .... M..

m ;i·ii
<oI1Idor ....I1ICUrrta
.
:;~ -..
IclO
C:IO

'no
I1ICUrrtaf
YC.=+2S"'E=O
Em,""
lenni Cumni
+. +, +3 +6 +3 +6 +. +61",
lQ=+2Sv;l c =O +, +, +2 +" +2 +6 +2 +,1 ~
Close para""", control .... tho llOfC TO·5 ...tdotI pack... IVctoCOlJIdoI-_
...... "viet ..
liaWIIty and ltable .haracllrillia ACTUAL SIZE
~~ii lreaktlownyolrogl
Ie l00ftl = +21 +21 +" +21
I
~i~~ lYuo Emitt.r-1cIlI
.,."lrOftmenttil t • .,.
pi .......downVoItage
IE=IOOflll +21 +21
;; hfE

hFE
DC ForwaniClIlTtIdTransfarlafio
Ie = lOma; Vcf=h
II(F..... nI(urI'llltTramftrluHo
Ic =200mo; Vcl=O.lSv
" 50 .
70 200
+"
IDO 3DO
+25

.. . '"
V. IesHmitter VolIDge " " " "

'-
le=lOma; 1,=O.Sma +0.15 +0.30 +0.401+0.1S+D.fS+O.ul+o.1J +0.24 +0.351+0.15+0.23+0.3
mechanical data f eEl,,'J CoIIIm,-EmJthir Safwollon
)\,fda] rall(' with ~laBK·lo·m"tal hprmptic ~"1l1 iwtwP"1I "'N' lind iI-aall. ['nit wf"ip;hl is approximatf'ly 1
Ic = lOrna; 1,=O.Sma +0.10+0.21)'
p:rllm. TItI'S(' units ml~1 JEDEC outline TO.S Ie =10ma; 1,=0.2Sma +0.10+0.20
Ie = lOmo; 1,=O.17ma +0.10+G.201
Ie = 10mo; 1,=0'13ma +0.10+0.20

'N' . . "CON@"O"'"' +"


VI" PuMh-ThloughVoJtagI· +2l +" +"
c.... Common-loa 0u!puI C~
VCI = +5.; 1,=0; f=lmt ~ ~ W
C,. Common-Ball lewlne-Bial

-
IIIpulClIjIOdIaro

o§ .. ... Vu =="+Sw;lc=O;f=ll1K
" "
~
.""
•1.. fa. Commeft-h.O\lpho-Cl!tott

-
-j

or ~'.:~I>
~. ',,~o:
'.... 4.5 U
::= ....... -+ .•' o.-~
Vcl=+Sw;lf=Tma
" " "
Swlh:~"" Speeds 1_l1li .. S!rildllnl·5pHd and SIlIntl-1a1i
abtolute maximum ratln•• at 25·C Ambient Temperature I unle" other..... i •• not.d I I, OtICI)'TJnIl 0.12 ~ ~
t. Ii. TIme 0.10 W
= =
,...
-
5Io"",Tlml 0.50 ~ ~ ~ ~
fall nl1'II ~ ~ ~ ~
2Nn06,7 I 2Nnll,' r UIIfh Ii U U U
Conutor_I ... Volt ••• o (151 (251 )0
SWIKHINO-IPIID nSf cl.cun
EmiHo._ •••• Voll.'!!_ OLARITIEt SHOWN APPLV TO "" .. 1 V~" :c::=~:

con.ctorCu.r.n!
~~~:U.TO.
~-~'QU'''''N'
:O~~ i:.~'
Tot.1 Devic. Dillip.tiol\t H'212A~
011 EQUIVALENT
-65to +100 'c
St••• '!!. T.",p ••• tu •• JI. ...'!!.
~IO. +10. ..
·V.. I.... 'in po..n....... opply 10 N_P·N de~ic •• only.
tD.'"te 2.$ mwrC ......... Ambien' of 2$°C,

TFXAS INSTRUMENTS TEXAS INSTRUMENTS


NCO" P o " " TEO INCORPORATED
"' ell, <00,'02 CA As22 ,,.,
N·P·N TYPES 2N1302, 2N1304, 2N1306, AND 2N1308
P·N·P TYPES 2N1303, 2N130S, 2N1307, AND 2N1309 ELECTRICAL CHARACTERISTICS
COMPLEMENTARY AllOY·JUNOION GERMANIUM TRANSISTORS
TYPICAL CURVES 'OR 10TH '.N.P AND N.P.N TYPIS (unle.1 oth.rwl.. noted)

CO!.UCTOII·."uml VOltAGil ••• COUICTOII ~.I""


(WtTM all .. cun.", ALA ' ......M". . ,
toUKfGf: CUI.pm
1.... _""D1O -'RY A' I,,=H_I

j "I 1/;01/.....1;;: 1
:~::~:~."'. I

j'"
1~1:~':..-
~
! "f--I
Ierlll l
i
i
;o~~L--L~
-+-T--+--

____~__~~__L-~

l'dCOlll(T(lI:CUltfNT ...

........ ImI.VOlI ... GlnCOLLlaoIICVtI .... T


{WI'""''' CUllIltNTAS .. , •• A_U.,
--u-c=~:::
(C ... _IilIIUuomUNITYAT'''twI=S.)
u,.aenANQ _ _ ","D IN: _W .... CU ••11f1 nANII'D ...no

.. /Q'"N'TtM ...... TUIII


(h,,_....LIIID roUNIfY .. ' n'CI

,.
.,I ,."
'

~L~
":I~ll IL~ml
I Vcll COLl!CTOI:·U$I! VOLTAOI_. T._AMII ...'lU........ tU.t _·C
fA - AMI,!HT nMPEIlA.T\lII_ 'C

..,
tv

~
TEXAS INSTRUMENTS TO lupnr T~E IElI ,IODU(11 rOSIIIl[. TEllS INITlUllltNTS REnnES
'NCOAPORATE:D IHE liGHT 10 IolU[(HIHGEI IT UT liME INCIDEI '0 IM'IOHDESIGN
2 •• , •
P·N·P TYPES 2N1303, 2N1305, 2N1307, AND 2N1309
COMPLEMENTARY ALLOY·JUNCTION GERMANIUM TRANSISTORS

.., C_UII Af'PltcAltONI IUCYRleAL CHARACTERISTICS AT 25°C AMBIENT TEMPERATURE (unless otherwise notedt
.I>.
COMPLIMENTARY CUR.IiNT-MODI SWJTCHES
(TYPt(Al NON·SATURATING SWITCH CASCADE
CAPAIU OF OPfilATION AT A 3..,c RATtI IclC

lno
'AlAME1P AND 11S1 CONDItiONS

CoII.dollenrwCurrent
Vel -25¥;l c 0
Emitter lenne Current
~

,
~
'p
~
M ••

~ ~ ~
--
~

,
~.

~I.

-
Vu -2Sv;le 0 ~ ~ ~ ~ ~
BVelO

IYno
(OUerto,-IOII
."akdownYoItop
Ie
EmiHar-IIM
"".down
100/,(1

VoIlPgt
... ... ~
T
INPUT
I~
- 100,,11 n n n H
+~D '. [I( forward (u",ntYronmrlatio
Ic""""'-IOma;VC1 - -tv N ~ ~ ro ~ ~ ~ ~ u m
'd.o:;:m,""-
\::0::. '. DC folWCln!turnn,T, ..5I«latio
Ie -2OOma; Yel~' -{I.3.5v N N
',-=140",_
" "
.
• • 20 "'~ .., ' ... =20 ..... _ V. BaM-Emitter Yohale
, ... ::=20 ""'...
" _20",~_ ',=140_ 'I~"O_ Ie -lOrna; I. --O.sma 1--O.l.5--IUO--O.40 ,.1.5--0.25--0.351--0.15--0.2-4--0.35 .1S --0.23-0.31
• mn Val..l] (oI1tdo,.(mitmSaIIlfGfian
V,,,",,
Ie' -lOma;l. --O.Smo --0.10--0.20
Ie=- -lOma;I.""-4.2.5mo -O.IO--O.ZO
le= --IOIna;I.=--O.17ma -{I.10--O.2D
le- -IOrna;I.~·--O.13ma --0.10--0.20
V.' 'undl-ThroughYoIl.· :n N 1l ~1l

c.. (IIIIImOll-1otII Ocrlput(opocitolK'


(OM'UMlN'''.l 'NVI.n.
("IG"-~PI!ED ,NVIIII.)
CO""UMINTA." 1"'"'" fOLlOWI'
IPO$ITIVI11IAN$,nOI IICTION ON 10TH 11$1 AND 'ALI)
e.I>
'(:.- -.5V;IE· O;f-=lm(
(ommon·Base ItVtlrse-llas
Inpul(apadtalKl
" " 201/'/,fi

'N~' ~OO"'-":'-"-"
'1u=-Sv;le=--O;f=-lmc l'/,fl

f 20 ..... _

~
iI- O
L"
$'''''''' \ , '
1'00.
OOOl~f
foth CIJnwnon.Iaw Alpha-hloff
Fnqutnty
'e,=-5v; II=lma

10
" 1l
"
."' .......
,; ,,-- """" >on 'j Q" 5tored Base Char.. 1200

lJ I.

000,., ,~=2O__
tH'30?
OlllPUT
=:JCI ..... _
.... 'L-..J
6V""'\lT lHIS07 _
-
K ~ _.
OIlTPUT-'"
SWITCHING CHARACTERISTICS
S..ttth. . . . . . (lIIItnIfIIIinSwltdlIlg·SpetdIlllClStond.....(lIa'lllftl'lircuits5llow!l)
.'V - lURNON liM! 00 m... ~'l\/ 'u .... o .. " .. t !II) "'_'" -DIIIIlyTiIllI
lise nme
StorageTimI
I 0.10
0.40
0.90
I
---F 0.01
0.21
O.~
0."

....
0.10
...•
1,-1

flIlITimI
,..
0.60 0.45 0.3.5 US ,,,,,,,
Total Swikhklg Time 1.6 1.3 1.1

. 8
C'RCUIT 'OR OETI!RlIIMIMG VALUI! 0 .. STORI!O . ACHA
0GI!
1!
,............- -- - '~~I .:~:.:=:::-s::-"

r-&:oii"-'. _ .. 010_0,'
B ::~=~~~::;;~e.ISINCIEASEDUNTIL
CI
'ruNCH·1HIIOUGH
pI IS DEnlMlNED 1'1' MEASUIING 1HE EMI".lI·IA5E ---. ::;":":':'~o, C, ••

MfASUIEMENf
:E:II~ IliA
.= v.... = 1.; tHE VA~UE Of Ve IV,I + I) _:.LJhilll V::~:I! SSOOA "ty o!:~;;c:;: •
_~~I~OL'~
' ....0.1_<_ ....

~
TEXAS INSTRUMENTS
... C 0 f< P 0 f< A , {" D
[0 ' 2 , ,.
Transistor Specifications 25

CD Description. The general classification of the transistor or series is given


first. This includes device number, material type, whether NPN or PNP, the basic
construction technique used in fabrication, the general purpose for which the device
was designed, and its outstanding characteristics. From this description, the
designer can quickly determine whether the transistor or transistor series is generally
suitable for his application. From this point on, however, the job of selecting a
specific transistor for a particular purpose involves consideration of all electrical
ratings and characteristics to make sure that the transistor fits the application in
every regard.
® Environmental Tests. The information presented here concerns those tests
to which finished devices are subjected before thorough testing for rigid adherence
to specified characteristics. The tests most often specified are temperature cycling,
aging, stabilization, and mechanical shock testing. In some cases, a particular
production process or expected device use dictates additional tests.
Transistors are subjected to these tests to ensure maximum integrity, stability,
and long life. The information is presented to indicate to the user the physical
ruggedness of the device.
CD Mechanical Data. Mechanical data includes package description as to case
type, unit weight, an outline drawing with dimensions, terminal identification, any
additional fabrication information, and a statement as to which electrode (if any)
is connected to the case.
@) Absolute Maximum Ratings. Absolute maximum ratings are those ratings
established by the manufacturer, beyond which degradation of a transistor may
occur. These ratings are based on the semiconductor material, manufacturing
processes, and internal physical construction. Test conditions are usually not
shown for these ratings. Since these ratings represent the extreme capabilities of
a transistor, they are not recommended as design conditions. The transistor will
not necessarily withstand all maximum rating conditions simultaneously.
® Electrical Characteristics. This is the portion of the data sheet to which
the designer will most often refer. Here he will find the limits to the electrical
parameters necessary for a particular circuit design. These limits are guaranteed,
and are specified as maximum and/or minimum limits. To prevent any chance of
misunderstanding, complete test conditions are specified for every parameter.
In addition to minimum and maximum parameter limits, a typical value is often
shown. This value is not guaranteed. nor is it required on the data sheet. It merely
gives the user an indication of where the mean of a distribution is located when
that particular parameter is measured on a very large number of units.
Electrical characteristics are defined as measurable properties of the device which
are inherent in its design. Consequently, quantities such as power gain, noise
figure, switching times-which are circuit-dependent-are not included under Elec-
trical Characteristics, but rather under Operating or Switching Characteristics.
Inasmuch as the numerical values of these characteristics are circuit-dependent, a
test circuit is included on the data sheet in the section entitled Parameter Measure-
ments Information. In general, these parameters are measured at nominal current
and voltage values, since exact values vary slightly with device parameters.
26 Fundamental Considerations

® Typical Characteristics (Curves). These curves are usually included, to


show the variance of particular parameters with changes in temperature, voltage,
and current. The curves are typical, and they conform to information given else-
where on the data sheet, especially data shown as Electrical, Switching, and Oper-
ating Characteristics. Often included are thermal characteristics, which include a
dissipation derating curve and possibly curves showing junction temperature
response as a function of pulse width and duty cycle.
o Typical Application Data. Practical circuit diagrams and typical perform-
ance data are usually included on the data sheet. These circuits always correspond
to the intended application of the transistor, and are intended to indicate device
capabilities as well as to provide the user with practical circuits.
® Parameter Measurements Information. This section presents circuits
necessary to test the parameters included in the Operating or Switching Character-
istics section of the data sheet. Circuit test conditions are specified. Every
parameter listed on a data sheet is subject to variation among manufacturers
because of difficult test conditions; this information is provided to help minimize
correlation problems.
Conclusion. Although much information may be included on a data sheet, it
is obvious that the manufacturer must leave much unsaid. Information is included
only after a careful appraisal of market requirements, in which cost to the user i~
the prime consideration. A conscientious manufacturer strives to present those
parameters which he knows to be most important to the design engineer, and he
strives to present them in the most usable manner.

3.2. TRANSISTOR NUMBERING SYSTEMS


TI Standard Devices. A standard TI device is one that is in production but
has not been registered with the Joint Electron Device Engineering Council
(JEDEC).
The number assigned to a standard TI device consists of the prefix TI and a
sequential number of not more than four digits (e.g., TI 2062).
TI Special Devices. A special device is one that deviates from the product data
sheets and/or the JEDEC registration specifications in any detail.
The number assigned to a special device consists of a two-letter prefix and a
sequential four- or five-digit number:

SM 1234

Material ~It~ Sequential number


G-Germanium A-Alloy (Preferably four digits)
S-Silicon C-Consumer
J -Grown junction
M-Mesa-planar
P-Power
S-Special products
Transistor Specifications 27

TI Development Devices. A development device is one that is in a preproduc-


tion stage. The number assigned to a development device consists of TIX and
a sequential number of not more than four digits (e.g., TIX 2061). (When a
development device becomes a standard TI device, the X is dropped from the prefix.)
JEDEC Type Numbers. A JEDEC type number indicates that a device has been
registered with JEDEC. The purpose of registration is to facilitate the purchase
and distribution of semiconductor devices by nontechnical individuals, and to
provide standardization in the field of electronic devices. Registration procedures
are designed to ensure that devices which differ from one another in performance
are identified by different type numbers. Type numbers are assigned in numerical
sequence as they are requested. INXXX numbers usually denote diodes or recti-
fiers, 2NXXX numbers usually denote triode devices, and 3NXXX numbers usually
denote tetrodes.
The semiconductor section of JEDEC is administered by the Semiconductor
Device Council, which consists of eight members chosen by the Electronic Industries
Association and the National Electrical Manufacturers Association. The council
receives policy direction from them. The council formulates the policies and
procedures that are followed in assignment of type designations and standardization
of electronic devices. The standardization work is carried out in the product
committees set up by the council.
One of the essential programs of the Semiconductor Device Council is type
registration. The type registration is directed by the type administrator, head of
the EIA Standards Laboratory in Newark, N.J. Registration consists of assignment
of type numbers, recording of the assignment and the defining data, and releasing
of the registration data to the entire electronics industry.
For further information concerning registration, consult JEDEC Pub!. 15, Type
Designation and Registration Procedures for Semiconductor Devices.
Other JEDEC publications particularly useful to design engineers are:
Summary of Registered Crystal Diodes, JEDEC Pub!. 3.
Summary of Registered Transistors, JEDEC Pub!. 6.
Summary of Registered Bases and Outlines for Semiconductor Devices, JEDEC
Publ. 12.
Electronics Industries Association recommended standards, specifications and
engineering publications may be obtained from
EIA Engineering Office
Room 2260
11 West 42d Street
New York 36, New York
at the prices indicated in their list.

3.3. MILITARY SPECIFICATIONS

The military services require that transistors they purchase, and those used in
equipment they purchase, be of a type they approve procured to specifications they
28 Fundamental Considerations

publish. These specifications define the parameters to be measured, the acceptable


limits, the environmental and life tests to be performed, and the statistical sampling
plan to be used. Government contractors are also directed to use the specifications
to specify parts for government equipment. Each of the military services has a
branch which issues such specifications.
A transistor procured to these specifications is identified by the letters USA,
USN, or USAF stamped on the device. When a transistor type is used by more
than one service and the specification has their concurrence, the specifications
issued by the Armed Services Electro-Standards Agency and the transistor bear a
JAN designation.
Military specifications covering transistors are designated MIL-T- or MIL-S-19500.
Military transistor types differ from regular commercial devices in that they have
demonstrated capability of passing many severe environmental tests such as shock,
vibration, high G-Ievel centrifuge, temperature cycling, moisture resistance, and
usually both storage and operational life tests. These tests are required to assure
that the transistor will continue to operate satisfactorily despite severe military
service.
Military transistor types may be procured only from qualified suppliers who have
demonstrated, by qualification testing, their ability to meet the specification require-
ments. Furthermore, these military types can be furnished only for use in military
equipment; they are not available for commercial uses.
4
Nature of Transistor Quantities
and Parameters

4.1. D-C QUANTITIES AND PARAMETERS

I CBO is the collector current when the collector is biased in the reverse (high
resistance) direction with respect to the base, and the emitter is open-circuited. This
current is made up of two components, one temperature-dependent and one voltage-
dependent. The temperature-dependent component (Is in Fig. 4.1) is called the
saturation current and results from thermal generation of electron-hole pairs, while
the voltage-dependent component (h) results mainly from surface leakage through
the collector-base junction.
I CBO is of primary concern in transistor biasing. Because of its extreme tempera-
ture dependence it can become an appreciable part of the base current in low-level
applications, and it can cause self-heating and thermal runaway in large-signal
applications.
I CBO is generally measured at two voltages, at room temperature and at some
elevated temperature. One measurement is made at a voltage low enough so that
avalanche multiplication effects are negligible; at this voltage the elevated tempera-
ture measurement is also usually made. The temperature is set high enough to
ensure that the saturation current is large compared to the leakage current. This
allows the designer to use the known temperature dependence of the saturation

--

Figure 4.1

29
30 Fundamental Considerations

current to determine the behavior of leBo at high temperature. Another measure-


ment is made at or near the maximum voltage rating of the collector-base diode,
usually at room temperature only.
Variation of leBO with Junction Temperature. As stated, leBo is made up of a
saturation component (temperature-dependent) and a leakage component (voltage-
dependent), expressed as leBo = Is + h This relationship is shown graphically
in Fig. 4.2. At low temperatures, leBO is mainly the leakage component; at high
temperatures, the saturation component becomes dominant. The temperature
dependence of Is derived from Fermi-Dirac statistics has the form!
(1)
where A and N are dependent on the physical properties of the semiconductor
material and T is absolute temperature in degrees Kelvin.

dIs
dT
= AT3e-NIT l(3
T
+ N) = Is (3 + N)
T T T
(2)

Rearranging Eq. (2),

dIs
Is
= (3 + N)T dTT (3)

It is common to express the Is temperature dependence in terms of the number of


Kelvin degrees (or centigrade degrees) temperature rise that it takes to double Is.
If we set dIs/Is = 1 in Eq. (3), we arrive at

llT = T2 (4)
3T+N
This doubling rate is also temperature-dependent; for a transistor that has a large
leakage component, however, it has been observed that some constant doubling
rate can be used as a conservative approximation over the useful temperature range.
For silicon transistors a llT of 10 Co has commonly been used, and for germanium
transistors a llT of 14 Co. However, use of this approximation for transistors that
have low leakages (such as planar transistors) can cause the designer trouble,
especially at low temperatures. From Eq. (4) we find that llT = 10 CO at 130°C

Temperature, °C
Figure 4.2
Nature of Transistor Quantities and Parameters 31

for silicon transistors (N = l4,OOooK for silicon). I::J.T = 10 Co is a conservative


approximation above l30°C for silicon transistors with low leakage currents, but
at 25°C (room temperature), we find that I::J.T = 5.97 CO. It is apparent that
applying the I::J.T = 10 Co rule of thumb to a value of I CBO measured at room tem-
perature will yield far too optimistic values of I CBO at higher temperatures.
Variation of I CBO with Applied Voltage. At low voltages, the leakage com-
ponent of I CBO varies almost linearly with applied voltage. At higher voltages, the
very strong electric field in the narrow collector-base depletion layer causes a large
increase in the kinetic energy of current carriers (holes and electrons) passing
through this region; when the carriers collide with atoms of the crystal structure,
enough energy is released to generate other electron-hole pairs, which in turn are
accelerated by the strong electric field and may collide with other atoms, generating
still more electron-hole pairs. This process is called avalanche multiplication, and
it results in a rapid increase in collector current with collector voltage.
I cEo-The collector current when the collector is biased in the reverse (high
resistance) direction with respect to the emitter and the base is d-c open-
circuited.
I CE~The collector current when the collector is biased in the reverse (high
resistance) direction with respect to the emitter, and the base is shorted
to the emitter.
I CE~ The collector current when the collector is reverse-biased with respect
to the emitter and the base is returned to the emitter through an external
resistance.
The relationship among I CEO , ICES, I CER , and I CBO can be found with the aid of
the equivalent circuit of Fig. 4.3. The resistor R from base to emitter represents
the general termination at this point. For any value of R, Ic = ICER (for R = 00,
Ic = ICEO). The current generator Is is the saturation component of I CBO , the
leakage component is accounted for by the resistance rCL, and rEL is the base
spreading resistance. For most practical transistors, the current generator IE is
obtained by recognizing that 2

(5)

Figure 4.3
32 Fundamental Considerations

where aN, al = normal and inverse common-base current gains of the transistor
(aN~ -h],B)
lEBO = reverse saturation current of the inverted transistor
CPE = emitter diode potential
q = electronic charge
=
K Boltzmann's constant
T = absolute temperature, OK
If we assume that KT/q ~ CPE, then Eq. (5) reduces to
aN -aflB
IE ~ - 1
- aNal
lEBO = ----':.....;;:..-
1 - aNal
(6)

since aNIEBO = aIls (see Ref. 2). Then from Fig. 4.3, A = al/(I - aNal). Solving
for h in Fig. 4.3, we get

(providing V OE ~ V E) (7)

and IB = Is - ,rB V+E R (8)

VE = Is(1 - A) + hpeIB + VOE/rOL ('


,
(rB + R)(rOL + rEL) + roLYEL
rB + R) roLYEL (9)

Substituting Eq. (9) into Eq. (8) and the result into Eq. (7),
1 - 1 - I
0- OER - S
[1 + h*FE (rB +(rBR)(rOL
+ R)(rOL + rEL) + ArevEL ]
+ rEL) + (1 + hpE)roLYEL
VOE [1 hpErEVOL ] (10)
+ rOL - (rB + R)(rOL + rEL) + (1 + hpE)rELYoL
Equation (10) is very cumbersome and the necessary parameters cannot be ob-
tained from a data sheet, but it is useful for qualitative analysis. If we examine
Eq. (10) with R set equal to zero and let rEL approach infinity and A approach zero
simultaneously, we find that
leER VOE (1 - hpB) = Is + h
= leBO = Is + (11)
rOL
Here our expression reduces to the sum of the thermal saturation current, Is, and
a term representing the collector-base diode leakage current, h. Letting R ap-
proach infinity in Eq. (10),

IOER = I OEO = Is(1 + hpE) + VOE


rOL
= (1 + hpE)IcBO (12)

Finally, setting R = 0,
I OER = I OES = I S ~ + h*FE, rB(roL + rEL) + ArOVEL
*
J
rB(rOL + rEL) + (1 + hFE)rOVEL
VOE rl hpErELYOL J (13)
+ rOL l - rB(rOL + rEL) + (1 + hFE)roLYEL
Nature of Transistor Quantities and Parameters 33

Equation (13) can be reduced to a more familiar expression by making the


approximation
and
which is a good approximation for a practical transistor. With these assumptions,
Eq. (l3) reduces to

ICER = Is I 1 + -VCE (1 - h*FB) (14)


- OiNOiI rCL

In each case we have the sum of a saturation current and a leakage current, which
is what we would have intuitively expected before any analysis.
Equation (10) is plotted in Fig. 4.4. This type of plot is sometimes included in
data sheets. It should be pointed out that ICES assumes that the collector-to-
emitter path is not punched through, i.e., that the collector depletion layer does not
extend into the emitter.
ICEr-The collector current when the collector is reverse-biased with respect
to the base and the base is forward- or reverse-biased with respect to
the emitter. This quantity will be approximately equal to I CBO unless
the base-emitter junction is reverse-biased by a voltage which exceeds
the breakdown rating of this junction.
BVcBo-The breakdown voltage between the collector and base electrodes
with the emitter open-circuited.
BVcEo-The breakdown voltage between the collector and emitter with the
base open-circuited.
BVCEs-The breakdown voltage between the collector and emitter with the
base short-circuited to the emitter.
BVOEg-- The breakdown voltage between the collector and emitter with
the base returned to the emitter through an external resistance.
BVOEr-The breakdown voltage between the collector and emitter with a volt-
age applied between base and emitter.
BVEBO- The breakdown voltage between the emitter and base electrodes with
the collector open-circuited.

log leER

leEO

logR
Figure 4.4
34 Fundamental Considerations

The breakdown voltage BVOBO in most transistors is due to the avalanche multi-
plication of lOBo discussed previously. BVOEO is less than BVOBO , and is quite often
less than half of BVOBO . The collector current can be written as
(15)
M is the multiplication factor that accounts for the rapid rise in leBo near BVOBO .
An expression for M has been given, 3

M= I (16)
1 - (VoE/BVOBO)n
where n is an empirical constant dependent on physical properties of a semicon-
ductor. From Eq. (15) we see that the value of M that will make lB = 0 is
M = ljhFB . Substituting this result into Eq. (16),

BVOEO = BVOB0Ct +\F~)lIn (17)

Equation (17) predicts the voltage at which the total alpha of the transistor equals
one. At this voltage, the common-emitter current gain is infinite and the collector
current increases unchecked.
It is not possible in practice to measure the true values of these breakdown
voltages, since the true value implies that they are measured at infinite collector
(or emitter) currents. The values of BVOBO , BVOEO , BVOES, etc., given in a data
sheet are measured by applying a constant current to the proper electrodes of the
transistor and measuring the voltage between the electrodes. The magnitude of
the constant current depends usually on whether the transistor is designed for
small-signal, medium-power, or power applications. When the product of the
measured current and the breakdown voltage is sufficient to cause heating of the
junction, it is customary to make the breakdown voltage measurement with a low
duty-cycle pulse (see Pulse Testing, Sec. 5.2). If the junction temperature increases,
the measured breakdown voltage decreases because the saturation current increases.
This is illustrated in Fig. 4.5.

BVCE01 BVCE02

Constant
measuring
current

Ic
Figure 4.5
Nature of Transistor Quantities and Parameters 35

Vrr-Punch-through voltage-the voltage between the collector and emitter


electrodes at which the collector depletion layer extends into the
emitter.
BVcEs-Breakdown voltage, usually limited by the avalanche breakdown effect
previously described rather than by VPT.
VEB~The d-c open-circuit voltage (floating potential) between the emitter
and base electrodes with the collector reverse-biased. This measure-
ment can determine VPT, for if punch-through occurs,
(18)
VBW- The voltage between the base and emitter electrodes with the base-
emitter junction forward-biased and the collector-base junction
reverse-biased. In Fig. 4.6, the voltage represented by the ideal
characteristic has a negative temperature coefficient; i.e., it decreases
with increasing temperature. 4 However, that part of the actual input
characteristic beyond the knee of the curve is due mainly to bulk
resistance and has a positive temperature coefficient. It is apparent
that variation of VBE with temperature depends on the bias current
level, the coefficient being negative (approximately -2.5 mv/°C) at
low emitter currents, becoming less negative as IE increases, and
possibly going positive at high values of IE.
VBE(sat)-The voltage between the base and emitter electrodes with both the
emitter-base and collector-base junctions forward-biased. This
quantity is generally measured with the base current greater than the
value needed to saturate the lowest hFE transistor of a given type. The
previous discussion of VBE vs. temperature applies here also.
VCE(sat)-The voltage between the collector and emitter electrodes with both
emitter-base and collector-base diodes forward-biased. VCE(sat) is of
particular importance in switching applications. It is the minimum
switch contact potential, and is usually measured under the same
conditions as VBE(sat). It has a positive temperature coefficient since
it is partly due to an ohmic drop across the collector bulk resistance.

F Ideal characteristic

Figure 4.6
36 Fundamental Considerations

Transistor D-C Parameters


hF~The static value of the common-emitter short-circuit current gain.
The short-circuit gain is the most important of the transistor param-
eters. In circuit analyses where reasonable approximations are made,
all parameters can be neglected at one time or another save hFE (or
hFB). Since the transistor is a current control device, we would
expect the current gain parameter to be important.
hFE Variation with Emitter Current. Figure 4.7 shows the variation of hFE
with collector current at several junction temperatures for a silicon double-diffused
mesa transistor. This graph appears on the data sheet of the TI 2N697. As Ie
increases from very small values, hFE increases to a maximum and then decreases
at high values of Ie. This can be related to hFB (the static value of the common-
base current transfer ratio) variation by recognizing that
hFE
-hFB- 1 (19)
+ hFE
and IE =.!.£
hFB
(20)

hFB can be expressed as the product of three components, 5


IhFBI = yf3M (21)
where y = emitter efficiency, the fraction of the emitter current that is carried by
minority carriers in the base side of the base-emitter transition region
f3 = transport factor, the fraction of injected minority carriers in the base
that arrive at the collector junction
M = collector multiplication factor, the number of current carriers collected
per minority carrier presented at the base side of the collector junction
140~------------~~-------------,--------------~
Pulse measurement
2% duty cycle _ _ _ TA = 150°C -+---------1
(300 j.lsec pulse width)
VcE =10v

~
~ 20r--~~~~---l--------1---------l

I c , collector current, ma
Fig. 4.7. hFE vs. Ie characteristics of 2N697.
Nature of Transistor Quantities and Parameters 37

Equation (21) is illustrated by Fig. 4.8, which is the classic one-dimensional current-
flow model of an NPN transistor. In the base of an NPN transistor, the majority
carriers are holes and the minority carriers are electrons. Three processes have
been described 6 to account for the change in hFB with emitter current. Each process
dominates at a particular current level. At very low emitter currents, the recom-
bination of electrons and holes in the emitter depletion layer is high compared to
the emitter current and lowers emitter efficiency y. As the emitter current increases,
the recombination current in the depletion layer remains constant, causing y to rise.
For still higher emitter currents, an increasing electric field develops in the base
region and accelerates the minority electrons toward the collector, increasing {3. As
the emitter current is increased further, the high minority-carrier density causes an
increase in base conductivity, lowering y. This is known as conductivity modulation.
Thus, IhFB I will pass through a maximum, then fall off at still higher currents.
The recombination centers in the emitter depletion layer are caused by crystalline
defects, both in the bulk of the crystal and at the surface. The recombination
current is composed of a volume recombination component and a surface recom-
bination component.7 In planar transistors, the surface recombination is negligible,
owing to the oxide coating over the junction. Planar transistors maintain reason-
ably high current gains at emitter currents on the order of 1 /La.
The aiding electric field which develops in the base region can be explained with
the aid of Fig. 4.9. The charge concentration gradients shown in Fig. 4.9 are valid
for step-junction transistors with uniform impurity density in the base.
In diffused transistors, a more complex situation exists; the majority impurity
concentration (acceptors) in the base sets up an electric fieldS that retards the
minority carriers (electrons) for a short distance from the emitter junction, then
accelerates them the remainder of the way to the collector. The field set up by the
current flow acts to increase the accelerating field similar to the action in step-
junction transistors. Figure 4.9 is used as an illustration because of its simplicity.
As electrons are injected into the base, they move toward the collector (by diffusion)
and establish a concentration gradient (ne). In order to maintain space-charge
neutrality9 in the base, an equal hole distribution is established (np). It must be
remembered that, even though there was an original hole concentration (no) due

~)IE (M-l)-yfHE
Holes Holes
......
IE
N P N Ie
~

"(IE ,,({3IE ~
'Yf3MIE
Electrons Electrons

Emitter Base Collector

hB
Fig. 4.8. One-dimensional transistor model.
38 Fundamental Considerations

to the impurity doping, the crystal was electrically neutral, and electrons injected
into the emitter cause an unbalance that must be neutralized by an equal number
of holes. (This must not confuse the reader into thinking that the base and emitter
currents are equal, for they differ considerably.)
Once the electron and hole distributions are set up in the base, electrons are
jerked into the collector region (by the high reverse bias at the collector junction)
at a much higher rate than holes can be injected into the emitter by the forward
bias on the base-emitter diode. The electrons that are jerked into the collector are
balanced by electrons injected into the base from the emitter, while holes that are
injected into the emitter from the base are supplied by the generation of electron-
hole pairs by the externally applied field at the ohmic (nonrectifying) base contact.
The large hole density in the base tends to induce a flow of holes in the same direc-
tion as electron flow (toward the collector). This happens until an electric field is
set up that prevents further hole movement. An electric field that prevents hole
flow in one direction will accelerate electrons in that direction; thus, this field
accelerates the minority of electrons toward the collector.
The conductivity modulation referred to previously is caused by the increased
number of charge carriers in the base. The conductivity of the base region (O"b) is
given by the formula
O"b = qp,p(Na + ne) (22)
where q = electron charge (1.6019 X 10-19 coulomb)
f.Lp = hole mobility
Na = acceptor density in the base
ne = density of emitted electrons in the base

At low currents the electron density in the P base (for NPN transistors) is
negligible compared to the hole density, and the conductivity is relatively independ-
ent of emitter current. Increasing emitter currents will eventually cause the electron
density to be an appreciable part of the original hole density (no). Thus, the
increased hole density caused by the equal increased electron density (space-charge

Emitter Base Collector

~
I O~------------------------~~~------~
~ Original doping level x
~ nor-------~----~=---------~~

~------------w----------~~

Fig. 4.9. Charge distribution in base.


Nature of Transistor Quantities and Parameters 39

neutrality requirement) will cause a rapid increase in base conductivity. This


increased conductivity will cause the emitter efficiency to decrease according to

y = 1 (23)
1 + aBW/a~PE
where W = base width
aE = emitter conductivity
L pE = diffusion length for holes in the emitter
In simple terms, the increased hole and electron densities near the emitter junction
increase the probability of electrons and holes recombining. This recombination
current causes the decrease in y.
hFB Variation with Junction Temperature. It is difficult to arrive at a general-
ized expression for the temperature dependence of hFB . The three factors (y, {3, M)
in hFB are all complex functions of absolute temperature; transistors can be designed
so that hFB has almost any desired temperature dependence. As an example, the
emitter efficiency, y, depends 1 on carrier mobility, carrier concentration, and carrier
lifetime (among other things). All these quantities are functions of temperature, 10
and the functions depend on the type of material (silicon or germanium), the type of
doping, the doping density, and even the type of construction (alloy, mesa, grown
junction, etc.).
All that can be said generally is that the temperature dependence of hFB is not
usually a prime consideration in transistor design. It is usual for hFB to fall off at
temperatures below room temperature and to increase above room temperature
(see Fig. 4.7 for an example).
hI~The static value of the short-circuit common-emitter input impedance.
In Fig. 4.10, hIE is just the slope of the line drawn through the origin and
the point of measurement P.

4.2. A-C PARAMETERS

CTc-Collector transition capacitance.


CT~Emitter transition capacitance.

A transition capacitance is formed by the diffusion mechanism of carriers in an


unbiased semiconductor junction. Diffusion creates a region about the junction

Figure 4.10 I
40 Fundamental Considerations

r bb, Cb'c
b'
b C

/
Vb'e Cb'e rb'e ree

~
e
Fig. 4.11. Transcurrent small-signal common-emitter equivalent circuit.

which is depleted of carriers, and an electrostatic potential across this depletion


region. If an externally applied voltage forces a change in this junction potential,
the charge which is thus added or removed corresponds precisely to that from a
capacitor with plates having an area and a separation corresponding to the cross
section and thickness of the depletion region and having a dielectric with permittivity
equal to that of the semiconductor material.
There are actually two types of capacitance at a semiconductor junction: a
transition capacitance, as defined above, which is primarily dependent on junction
voltage, and a diffusion capacitance, Cd, which is dependent on junction current.
The value of the hybrid-'IT collector-base junction capacitance Cbe (see Fig. 4.11) is
equal to the sum of these components:
Cd
Cbe' = CTC+T (24)

Since CTC is usually much greater than Cd/2, for high-frequency work Cbe is
approximately equal to CTC. The value of Cob, the common-base parallel output
capacitance with input open-circuited, must include header capacitance. The
expression for Cob, using the above approximation, is given by Eq. (25) if rbb is
very small.
Cob = CTC + Cheader (25)
For the emitter-base junction, the diffusion capacitance is the major component
of the hybrid-'IT emitter-base capacitance, Cbe ; the value of C6e is described by

Cbe=_l_, (26)
WTre
where wTis 2'IT/r, and r; = 25 mv/le = 25 ohms for I ma of Ie. Usually this value
of Cf,e is much larger than the value of CTE, except for low currents.

log w

6 db/octave

Fig. 4.12. Variation of Ihrel with frequency.


Nature of Transistor Quantities and Parameters 41

r---~----~----~C

e
Fig. 4.13. Modified hybrid-'1T circuit.

The effect of the collector transition capacitance in circuit design can be demon-
strated by the following example. The reverse voltage transfer ratio, hre , is given
by Eq. (27).
h _ SC/'c (27)
re - gbe
, + SC'be

where S=jw
Cbc ~ C TC
, 1 - ao
and =---
gbe
r:
This equation is derived from the hybrid-'lT small-signal equivalent circuit shown
in Fig. 4.11. It is very similar to the Giacolletto equivalent circuit. Normalizing
Eq. (27) yields Eq. (28),
(28)

The value of hre approaches asymptotically the value Cbcl Crie as indicated in
Fig. 4.12, which shows the plot of Ihrel vs. frequency. Therefore, it is evident that
a low value of CTC minimizes the high-frequency feedback voltage ratio.
A variation to the equivalent circuit of Fig. 4.11 yields the equivalent circuit in
Fig. 4.13, where CM is the familiar Miller capacity and is given by Eq. (29),
(29)
where A~c is the ratio Wce/Vbel. Here again, it is evident that minimizing Cb~
minimizes the effective capacity in the input circuit.
As a more elementary example of the effect of CTC on the design of high-frequency
circuits, it can be shown that the effects of this capacitance may be neutralized by
the circuit in Fig. 4.14. This is identical with Fig. 4.15 for a simple internal feed-
back element, Cc , where Cc is the collector capacity, and is defined as
Cc = CTC + Cd (30)

IN OUT

Fig. 4.14. A neutralizing circuit for Yre.


42 Fundamental Considerations

Fig. 4.1 S. A neutralizing


circuit for Ce•

Since the collector junction capacity is usually much larger than the diffusion
capacity that parallels it, we may say that
Cc~ C TC (31)
Therefore, the capacitance needed to neutralize the effect of Cc is given by

Cob, as defined earlier, is the common-base parallel output capacitance, with the
input open-circuited (IE = 0). Cob = Cc + Cheader is the expression for the total
capacitance between the collector terminal and the base terminal. Header capaci-
tance naturally varies with the type of header. For the TO-5 and TO-I8 (3-1ead)
package, they are as shown in Table 4.1.
Typical curves of Cob vs. voltage are shown in Figs. 4.16 and 4.17. Notice in
Fig. 4.17 that since Ccb ~ CTC and Ceb ~ CTE , the values of C TC and C TE are very
nearly equal to Cob and Cib , respectively.

7
f=l mc
IE=O
6

c~

2
-- ~
I""-- Typical unit"")

o 2 4 6 8 10
Ee. volts
Fig. 4.16. Cob vs. Eo: types 2Nl141, 2Nl142, and 2Nl143.
Nature of Transistor Quantities and Parameters 43

Table 4.1. Typical Header Capacitances


Picofarads
Capacitance
TO-5 TO-IS

ecb 0.6 0.75


eeb 0.3 0.05
eee 0.6 0.75

cies-Equivalent short-circuit common-emitter series input capacitance.


fies-Equivalent short-circuit common-emitter series input resistance.
ciep-Equivalent short-circuit common-emitter parallel input capacitance.
fiep-Equivalent short-circuit common-emitter parallel resistance.
fiep and Ciep are the measured equivalent input shunt resistance and capacitance
of the device with its output short-circuited. Chapter 5 discusses the test jigs and
instruments used to measure these parameters. The conversion to the series com-
ponents fies and Cies yields the form for hie. That is to say, Re (hie) = fie. and
1m (hie) = 1/WCies. Figure 4.18 shows the typical variation of the equivalent parallel
input values of resistance and capacitance vs. frequency for a germanium transistor
biased as indicated. Notice also in Fig. 4.l8 that the input has gone inductive at
~ 110 mc. Figure 4.19 shows the variation of fiep with bias conditions for a typical
VHF germanium transistor.

200

160

-c.
a.>
u
c
2
'uro
120 "- ~ emitter transition capacitance
(Cib,Ic=O)
c.
co

'"
u
c
0
'+=' 80
'iii f=l mc
c
ro
TA=25°C
t=

40 ~
C TC , collector tran~
I'--.
o
r-capacitance (Cob' IE=O)

t
-
1 10 100
Reverse voltage, v
Fig. 4.17. Transition capacitance vs. voltage for the 2N 1714 series.
44 Fundamental Considerations

1,400 r - - - - - - - - - - - , . - - - - - - - - - - - ,
30

1,200 I-----------I----B-ia-s-c-o-n-d-it-io-n-s-:- - - I
VcE=-lOv 20
I E = lOma

10

'+-
c-
O §<
<.;

-10

-20

-30
OL-_~ _ _L~_~~Lll ___ L-_L~~_L~_U

10 100 1000
Frequency, mc
Fig. 4.18. Ciep and riep vs. frequency: type 2Nl141.

350

""" -
IE"" 1 ma
,;.:;;--
300
~
2N1405
f= lOOmc
250

LE""zm a
E 200 ...----
-'= ~ I
o
§<
i...~ 150
/" ~
V I
100
k:::: IE- 5ma

50

o -1 -2 -3 -4 -5 -6 -7 -8 -9 -10
VeE' collector· emitter voltage
Fig. 4.19. Equivalent short-circuit common-emitter parallel input resistance riepo
Nature of Transistor Quantities and Parameters 45

Type 2N1405
VCB=-6v-
IE=2 ma

coep=
--- -
[Im(Yoe )]
=---
~
[Im(yob)]
w w

a I I
10 100 1000
Frequency, me

Fig. 4.20. Equivalent short-circuit common-emitter (or common-base) parallel output capaci-
tance vs. frequency.

100K~------------------~------------------~

Type 2N1405
V CB = -6v
IE=2 ma

100 1,000
Frequency, me

Fig. 4.21. Equivalent short-circuit common-emitter (or common-base) parallel output resist-
ance vs. frequency.
46 Fundamental Considerations

coep-Equivalent short-circuit common-emitter parallel output capacitance.


roep-Equivalent short-circuit common-emitter parallel output resistance.
roep and Coep are the measured equivalent output shunt resistance and capacitance
with the input short-circuited. Figures 4.20 and 4.21 show the variation of Coep
and roep with frequency at a given bias point. Figure 4.22 shows the variation in
roep with bias conditions for a typical VHF germanium transistor.
The application of Ciep, Coep and riep, roep is demonstrated in Sec. 5.4. It is
generally more convenient to use shunt impedances than series impedances for
interstage design. However, if a strict h-parameter analysis is used, the Ciep and
riep would have to be converted to hie as mentioned earlier and the output admit-
tances would have to be measured with the input open-circuited. ries is also useful
in the calculation of unilateralized power gain and impedance gain. It is for this
reason that ries and roep are often specified on the data sheet at the optimum small-
signal operating point and at a frequency most applicable for optimum device
performance. The equations are:
Power gain = 20 log Ihrel + 10 log 4roep
ries
(32)

and Impedance gain = 10 log 4r oep (33)


ries

Yre-Equivalent common-emitter forward transmittance with output short-


circuited.
Yie-Equivalent common-emitter input admittance with output short-circuited.
hre-Equivalent common-emitter forward current transfer ratio with output
short-circuited.

6K
f= lOOmc
IA =25°C
5K

4K
V>
E
.<::
0 3K
~
... 0

2K

lK

o -1 -2 -3 -4 -5 -6 -7 -8 -9 -10
VeE, collector-emitter voltage, volts
Fig. 4.22. Equivalent short-circuit common-emitter parallel output resistance r oep at 100 me.
Nature of Transistor Quantities and Parameters 47

1,000...--------------r--------,
2N1141

500

300

200

100~---------~~~~_+~~._-~

f, frequency, mc

Fig. 4.23. Equivalent short-circuit common-emitter parallel input resistance vs. frequency.

A comprehensive discussion ofYie, Yfe, and h,e vs. frequency is presented in Sec.
19.2, which deals with the design of wideband feedback amplifiers. The present
discussion, therefore, is limited to showing how the header capacitance affects the
measurement of h'e, and presents curves to show the variation of these parameters
with bias.
There is usually a discrepancy between VHF measurements of hfe on the General
Radio transfer-function bridge and on h fe test jigs, because the header capacitance
is usually tuned out when measuring h fe in test jigs, whereas the effect of header
capacitance may not be excluded when the transfer-function bridge is set up to
measure hfe directly. However, h'e may be calculated (h fe = Yfe/Yie) by measuring
Yle and Yie on the transfer bridge and subtracting the known header capacitance
from Yie. This procedure yields very good correlation with readings made on the
h fe test jig.
Variation of [Re (Yie)]-l for three bias conditions can be seen in Fig. 4.23. The
general variation of Yfe with bias is presented in Fig. 4.24. Figure 4.25 shows the
variation oflhfel with bias for the 2N1405.
fMb-Frequency at which Ihfbl = O.707h fbo .
fi,-Frequency equivalent of the rbCc time constant.
Jc-Frequency at which Ihfbl is minimum.
iT-Frequency at which Ihfel = 1, or is extrapolated to equal unity.
The characteristic frequencies fhfb,jb, fe, andiT are shown in Fig. 4.26. fhfb is
described by
_1_ = ~ + 2(1 + aom) (34)
fhfb fa fi,
As this equation shows, fhfb is related to two other frequencies, fa and fi,. The first,
48 Fundamental Considerations

12

2J43
~ 10 {=30mc
(5
> TA=25°C
oj
tlO
~ 8 I-- 0 - 0 0 0
(5 0 ..t: ..t: ..t:
> ..t: ..t:
E E E
.... E E E
Q)
E E E
~ E 0 ~ 00
"E 6
~
10
0 0
f..- 00- ......
N
......
10
.......
~ II II \I \I II
....u
0 -
~ ~
-
~
-
~ ~
..!!:! -?-, n
(5 4 -?-, -?-, ~
u

tl
:::.:
2

o 5 10 15 20 25 30 35 40 45 50
Ie, collector current, ma
Fig. 4.24. Contours of constant transadmittance, IYtel.

14

12 /'
~
."....-
- I E =5 ma

IE 3ma
I

10 L V
..c
""0
8

6 /I r
;(
----- IE 2ma

4
VII
I
2
if to-"
IE 1 ma

o
/J -1
I -2 -3 -4 -5 -6 -7 -8 -9 -10
VeE' collector·emitter voltage, volts
Fig. 4.25. Short-circuit common-emiHer forward current transfer ratio Ihtel at 100 mc.
Nature of Transistor Quantities and Parameters 49

40r----------.----------.---------~----------,_--------_.

6 db/octave
Asymptotes

~ 20~----------+-----------+-~~~--~~----------~----------~

_20~~~~~~ __ _L_L~~~_ _~~~~~_ _~~wu~U__ _ _ _~~~.

0.1 1.0 10 100 1,000 10,000


Frequency, mc

Fig. 4.26. Variation of MAG, Ihtel, and Ihfbl with frequency: type 2N1405.

12

I 12N743 1
I
10 !T = frequency at which Ihrel =1--
A~G
~

'"
0 TA =25°C
>
Ill-
...... ~ClCl
bO
~
8 ~

0 \~
>
~

~ 6
E
Q) /
1:)
~
.:..
0

4 \ ./ V
~~
0
u

p;:tl
2

" -f ",'3
or fT-200mc
fT lOOmc

a 5 10 15 20 25 30 35 40 45 50
Ie, collector cu rrent, ma
Fig. 4.27. Contours of constant-gain-bandwidth product, /T.
50 Fundamental Considerations

fa, is simply the frequency at which the current multiplication factor a is equal to
0.707Iaol; it is related to Jr and m by
fa =Jr(l + aom) (35)
Actually, a is equal to h{b (or a) only if the common-base equivalent-T base resist-
ance, rb, is zero. If rb is not 0, then a is related to h{b by the expression

(36)

where re is the collector resistance in the common-base T-equivalent circuit.


The quantity jb is the frequency equivalent of the rf,Ce time constant and is
modified by a constant, 2(1 + aom), where ao is the low-frequency value of a, and
m is the excess phase term (whose value is somewhere between 0.5 and 0.8 for the
2N1405 germanium transistor).
The frequency fe is the point at which Ih{bl is a minimum. It is shown in Fig.
4.26 as being 2 Gc for the 2N1405 transistor;/c is given by
(37)
The frequency fT is the frequency where Ih'el = 0 db, or can be extrapolated to
equal 0 db. To obtain Jr, the Ih'el response with frequency is usually extrapolated
at 6 db/octave to Ih'el = 1 from a measurement at which Ih'el = 2. The product
flh'el has been referred to as the gain-bandwidth product, and is equal to Jr.
Figure 4.26 showsJr as 330 mc for the 2N1405. Figure 4.27 shows the variation
ofJr with bias.
MAG-Maximum available gain.
j(max)-Frequency at which MAG is unity.
The parameters j(max) and maximum available gain MAG are best treated
together. The following equations and discussion will detail the interrelation of
these parameters with the previously defined parameters.
Maximum available gain for transistors is given by the expression
MAG = Ih,I 2rop (38)
4ris
At very high frequencies, MAG decreases 6 db/octave increase in frequency.
Since a gain slightly greater than 0 db is necessary to establish oscillation, the
frequency at which MAG = 0 db is labeled j(maxh the maximum frequency of
oscillation.
Equation (38) permits the calculation of gain from measurements of input and
output resistance and current gain. Below 100 mc, these measurements can be made
with a Boonton RX meter and relatively simple test circuits. Above 100 mc, the
General Radio 1607 A bridge should be used.
Another method of computing gain, which is simpler but somewhat less accurate,
is to determine j(max) from its relationship to Jr and jb. This method proceeds as
follows. From Eq. (38), using the common-emitter configuration,

(39)
Nature of Transistor Quantities and Parameters 51

The following relationships are valid at frequencies approachingfimax):

(40)

(true only for germanium) (41)


I (42)
and roep = 27TfTCc
Substituting Eqs. (40) to (42) into (39) gives

(43)

which simplifies to
+ fi = 1
4f(max)
(44)

where -1-c
f i- -27TriC (defined earlier)

Therefore,fimax) may be found from Eq. (44):

f:
J(max) -_ j/rfi
-4- (45)

or fimax) = (46)

Thus,fimax) can be computed from measurements offT and rtCc. The measure-
ments of/r and rtCc are discussed in Chap. 5. MAG at high frequencies is then
determined from
MAG = 20 log fimax) (47)
f
4.3. SWITCHING CHARACTERISTICS

Definition of IBI and IB2. IBl is defined as turn-on base current as shown in
Fig. 4.28. IB2 is the turn-off base current and is a transient current with its maxi-
mum amplitude occurring at the beginning of the turn-off interval. After the

+ Vce

~-----oOutput

Input C>----_---'\J\.JV___-::..-+-r + VCE"""l.r

V(in)..r1....

Fig. 4.28. NPN common-emitter switch.


52 Fundamental Considerations

stored base charge has been removed, the transistor turns off, and IB2 approaches
lOBO.
Overdrive Factor. Overdrive factor for a particular transistor operating under
a given set of conditions is defined as follows:
O.F. =~ = IBlh pE (48)
IBl(sat) IO(sat)

where IBl = the turn-on base current


IBl(sat) = the base current required to just saturate the transistor (IO(sat)/hpE)
hpE = the current gain at the specified ON conditions
For a particular group of transistors having a given hpE spread, the overdrive factor
is calculated using the minimum hpE specified for the group at the specified operating
conditions. Thus, for reliable operation the circuit must be designed using the
inequality
O.F. > IBlhPE(min) (49)
IO(sat)

The minimum overdrive factor must be greater than one.


Transistor Switching Times. The switching time definitions are shown graphi-
cally in Fig. 4.29.
td = delay time = time interval between the 10% point of the increasing circuit
input voltage waveform and the 10% point of the increasing collector current
waveform (refer to Fig. 4.29).
The delay time is mainly due to two factors:
1. Since a transistor switch should be reverse-biased to hold it OFF, the base-
emitter junction capacitance will have a voltage across it. It takes time to
discharge this capacitor and charge it to the forward voltage. The larger
the reverse bias, the longer the delay.
2. Time is required for the emitter current to diffuse across the base region.
This is represented by a base charge which must be supplied by the input
circuit.
tr = rise time = time interval between the 10 and 90% points of the increasing
collector current waveform.
The rise time, which indicates the frequency response of the transistor, is a func-
tion of the alpha-cutoff frequency. It is also a function of the amount of turn-on
current. The higher the turn'-on current, the shorter the rise time.
ts = storage time = time interval between the 90% point of the decreasing circuit
input voltage waveform and the 90% point of the decreasing collector current
waveform (refer to Fig. 4.29).
Storage time is a function of hpE and the turn-on and turn-off currents. By
definition, the collector current is saturated when the collector voltage falls below
the base voltage and thereby applies a forward bias to the collector-base junction.
This causes the collector to inject a charge into the base region. The collector cur-
rent cannot decrease until these stored charges are swept out. The higher the hpE
and the larger the turn-on drive, I Bl , the longer the storage time. The larger the
turn-off drive, I B2 , the shorter the storage time.
Nature of Transistor Quantities and Parameters 53
t=to t= t1
1 1
I

Input
voltage \-(in)j
~
)!
I I
I I
I
1
I'
1
90%

10%

OFF I
1\1
~
:~
Output 1
voltage VCEt 1
II, I ) ' [ 900
ON--
I I 1 I 1 I
VCE(off) ~ Vcc --!td~ 1 i--- ts -..j I

VCE(on) ~ VCE(sat)
I I 1 1 I I
l-jtrr- I --, tf r
1 1 1 I 1 I
Base 1 1
I I
current lEt
1 I
I 1
I
1
1
ON-- I
90%
I
Collector I
current lct
10%
OFF

Fig. 4.29. Waveforms associated with switching circuit shown in Fig. 4.28.

t, = fall lime = time interval between the 90 and 10% points of the decreasing
collector current waveform (refer to Fig. 4.29).
The fall time is also indicative of the frequency response of the device. It is, like
tr, a function of overdrive-in this case, a turn-off drive. The larger the turn-off
drive, the shorter the fall time.
TT = total switching time = td + tr + ts + t,.
Propagation Time. The time required for a discrete logic level to pass (propa-
gate) through a single logic stage is referred to as propagation time. This time is
measured from the 50% point of the incoming waveform to the 50% point of the
outgoing waveform. Since there is some finite difference between turn-on time
(tON = td + tr) and turn-off time (IOFF = ts + t,), the propagation time varies
depending on whether the logic stage is turning ON or turning OFF. Therefore,
a propagation measurement is normally made across an even number oflogic stages
as is shown in Fig. 4.30, and the measured time is divided by the number of stages.
If the incremental switching times (td' tr, Is, and t,) are known, a close approxi-
mation of tp can be obtained by using
Ip = Id + /',/2 + ts + t,/2 (50)
2
Switching measurements often indicate that
tr ~ td and
54 Fundamental Considerations

Initial Input State after


state input pulse In~
signal
OFF ON
~ 50%

ON OFF
~
I
I
I
OFF ON I
I
"Ji 50%

ON OFF ~
I I
f--2tp -I
Output

Fig. 4.30. Block diagram showing propagation time.

If this is true, then

or tp = tON + tOFF
4 2

Importance of Propagation Time. The importance of propagation time is


illustrated by Fig. 4.31, where four identical transistor switches are placed in cascade.
Stages 1 and 3 are OFF; stages 2 and 4 are ON. If the input changes stage 1 to
ON, the other stages are also changed. The output from 4 will not occur until a
time equal to 2TT after the input is applied to stage 1. If the output of stage 4 were
to be coincident in a gate with the input to stage 1, the gate must be held ON to
accommodate the large time difference of 2TT . Thus, the speed at which informa-
tion can be propagated is limited by T T.
Definition of QB

QB = total stored base charge = Qs + Qsx


where Qs = stored base charge at the edge of saturation, and Qsx = excess stored
base charge due to saturation.
In general, an approximation of Qs and Qsx for alloy transistors can be found
from the following equations:

where aN = small-signal common-base low-frequency forward current transfer ratio


WN = small-signal common-base short-circuit current gain radian cutoff
frequency
Nature of Transistor Quantities and Parameters 55

OFF tON

+
ON tOFF

+ =2TT
OFF tON
+
ON tOFF
Clock

Fig. 4.31. Propagation time. Output (responds 2TT after input)

(XI = inverted alpha (which is the same as Oi.N except that the collector and
emitter terminals are interchanged)
WI = inverted-alpha radian cutoff frequency (which is the same as WN with
the collector and emitter terminals interchanged)
1 C(sat) = collector current at the edge of saturation
1
1BX = 1Bl - hc(sat) = the excess base current
FE

4.4. THERMAL QUANTITIES

Heat Flow. To understand the flow of heat through a solid, it is helpful to


create an analogy between heat power and electric power. In order to produce a
flow of electric charge (coulombs) from one point to another, a difference in elec-
trostatic pressure (voltage) must exist. The rate of flow of charge may be given in
coulombs per second, or amperes. Whatever impedes this flow is called electrical
resistance (R) and is measured in electrical ohms (volts per ampere).
Similarly, in order to produce a flow of heat energy (joules) from one point to
another, a difference in heat pressure (temperature) must exist. The rate of flow of
heat energy may be given in joules per second, or watts. Whatever impedes this
flow is called thermal resistance «() and is measured in thermal ohms (centigrade
degrees per watt).
Figure 4.32 illustrates this analogy as it might be applied to a transistor dissipating
a constant power into an air-cooled heat sink. The total thermal resistance, ()T, is
the sum of the individual thermal resistances through which the heat power must
flow from its origin to the ambient into which it is finally dissipated. Typically this
ambient will be the surrounding air. For transistors without a heat sink, ()c-s and
()S-A merge to form a single ()C-A.
In practice, however, other factors vastly complicate this picture. Physical sub-
stances must store or release energy in order to change in temperature. In our
analogy, this effect is in some ways similar to electrical capacitance, which must
56 Fundamental Considerations

-I -
Power
(J Junction to case

E-=- AT-=- tJ Case to sink

tJ Sink to ambient

E=IR T AT=POT
RT=Rl +R2+R3 ATJ .A = TJunction - TAmbient
{)T={)J.C + {)C.S +()S.A
Figure 4.32

store or release charge in order to change in voltage. The product of a thermal


capacitance, CH , and a thermal resistance, 0, forms a thermal time constant. Each
separate material through which the heat power must flow will exhibit its own
specific heat capacitance and thermal resistance, and will introduce its own thermal
time constant.
Table 4.2 summarizes the analogy.
The instantaneous heat power, PJ, generated at the junction consists of some
steady-state value, PJ, plus some function oftime,pJ('T). Therefore, when the instan-
taneous temperature difference between the junction and the ambient must be
found, it is more convenient and accurate to use a circuit similar to Fig. 4.33. Here
a generator forces a power flow,pJ, through a network ofthermal capacitances and
resistances, creating a temperature differentialI:l.TJ_A •
The thermal circuit of Fig. 4.33 is analogous to an electrical low-pass filter, and
the pJ( 'T) portion of PJ may be rapidly attenuated as pJflows around the loop. If
pJ( 'T) contains only frequencies in the upper audio range, CHJ could completely
bypass these, and I:l.TJ_o might be computed from PJ(ma:c) alone. If lower-frequency
components of PA'T) are present, analysis of I:l.TJ_o requires an exact statement of
the function pJ and of the junction time constant, CHfiJ-o, or 'TTH. The thermal
capacitances of the case and the sink, CHO and CHS, usually bypass pJ( 'T) even at
low audio frequencies.
Of course, Fig. 4.33 is an oversimplification of the physical structures encountered
in practice. A better analog would show many time constants and parallel paths

Table 4.2
Electrical term Thermal term
EMF, volts .................... Temperature differential,
centigrade degrees
Charge, coulombs. . . . . . . . . . . . .. Energy, joules
Current, amperes. . . . . . . . . . . . .. Power, watts
Resistance, ohms ............... Thermal resistance, 0,
centigrade degrees/watt
Capacitance, farads ............ Thermal capacitance, CH ,
joules/centigrade degree
Nature of Transistor Quantities and Parameters 57

CHJ

Figure 4.33

for heat power flow, with distributed-rather than lumped-parameters. Also, the
parameters would be nonlinear with temperature. For example, the junction-to-
case temperature response is shown as resulting from only a single (h.c and a single
C HJ : a useful first approximation. Actually, it is the result of several (J's and CH's
within the transistor case, and it seldom follows exactly a simple exponential func-
tion approach to asymptote. The true junction-to-case temperature response to a
step-function power input tends to lead the value predicted from 7TH at first, and lag
behind it later. The only time of perfect agreement will be, of course, when the
!J.TJ_c reaches 63.2% of its ultimate value. Similar considerations apply to (Jc-SCHC
and to (JS-A CHS. But for most purposes, the effect of power transients on junction
temperature may be approximated with this linear thermal circuit using the familiar
techniques of electrical transient analysis.
Data Sheet Information. The data sheet may present thermal design informa-
tion in several ways:
1. A guaranteed value for (JJ-c.
2. A guaranteed value for the junction time constant. This is defined as the
time required for the junction temperature to reach 63.2% of its new steady-
state value if the case temperature is held constant and the power dissipation
is abruptly increased.
3. A maximum junction operating temperature, TJ(max). This may be assumed
equal to the maximum permissible storage temperature unless the data sheet
makes a distinction.
4. A maximum total average power dissipation at a specified case or free-air
ambient temperature.
5. Power dissipation vs. temperature derating curves.
6. Other curves, such as junction-to-case temperature drop vs. power pulse
duration and repetition rate.
If (JJ-C is not specifically stated, it may be calculated from items 3 and 4. For
example, the 2N389 data sheet gives:
Total dissipation at lOOoe case temperature = 45 watts
and Maximum junction temperature = +200 oe
Applying the analogy,
!J.TJ•c = 200 0e - 1000e = 100 CO
(JJ.c = 45100watts
CO
= 2.22 e ° /watt
58 Fundamental Considerations

Also given for the 2N389 is a graph of power dissipation for this unit mounted on
a 4- by 4- by Ys-in. copper heat sink. The derating curve for this mounting has a
slope of -0.114 watt/CO. The slope of the derating curve will be the negative of
the reciprocal of the thermal impedance. ()T will thus equal 8.78 CO/watt for this
combination. For further thermal considerations, see Chap. 7.

BIBLIOGRAPHY

1. Leighton, R. B.: "Principles of Modern Physics," McGraw-Hill Book Company, Inc.,


New York, 1959.
2. Ebers, J. J., and J. L. Moll: Large-signal Behavior of Junction Transistors, Proc. IRE,
vol. 42, pp. 1761-1772, December, 1954.
3. Miller, S. L., and J. J. Ebers: Alloyed Junction Avalanche Transistors, Bell System
Tech. J., vol. 34, September, 1955.
4. Linn, H. C., and A. A. Barco: Temperature Effects in Circuits Using Junction Transistors,
''Transistors I," RCA Laboratories, Princeton, N.J., 1956.
5. Ryder, R. M.: A Descriptive Summary of the Design Theory of Transistors, "Transistor
Technology," vol. 1, p. 217, D. Van Nostrand Company, Inc., Princeton, N.J., 1958.
6. Gartner, W. W., R. Havel, R. Stampfl, and F. Caruso: The Current Amplification of a
Junction Transistor as a Function of Emitter Current and Junction Temperature, Proc.
IRE, vol. 46, pp. 1875-1876, November, 1958.
7. Webster, W. M.: On the Variation of Junction Transistor Current Amplification Factor
with Emitter Current, Proc. IRE, vol. 42, pp. 914-920, June, 1954.
8. Tanenbaum, M., and D. E. Thomas: Diffused Emitter and Base Silicon Transistors,
Bell System Tech. J., vol. 35, pp. 1-22, January, 1956.
9. Shockley, W.: "Electrons and Holes in Semiconductors," p. 61, D. Van Nostrand Com-
pany, Inc., Princeton, N.J., 1950.
10. Gartner, W. W.: Temperature Dependence of Junction Transistor Parameters, Proc. IRE,
vol. 45, pp. 662-680, May, 1957.
5
Measurement of Electrical
Quantities and Parameters

5.1. D-C MEASUREMENTS

Breakdown Voltages. Breakdown voltages are measured at a specified current


level which is set high enough to be in the constant-voltage region of the breakdown
characteristic. Measurements in this region, however, may result in damage to the
device from excessive power dissipation. For this reason, breakdown character-
istics are usually guaranteed as a leakage current which is measured in the nearly
constant current region of the characteristic.
When a guaranteed breakdown voltage at a high current level is required, pulse-
testing techniques using a small duty cycle are usually employed. One such
pulse-testing technique is discussed in the next section.
Typical breakdown-voltage parameters measured are BVCBO (collector-base
breakdown, emitter open) and BVEBO (emitter-base breakdown, collector open).
Variations of the collector-emitter breakdown measurement include BVCER (resis-
tive termination between base and emitter), BVCEX (bias applied between base and
emitter), and BVCES (emitter-base short-circuited).
Illustrated in Fig. 5.1 are circuits for measuring BVCBO and BVCEO • BVCER ,
BVCEX, and BVCES can be measured by inserting the proper circuitry between the
base and emitter in the BVCEO test circuit. Since the circuit resistance is very high,
particularly on the BVCBO tests, the VTVM used should have 100 megohms input
impedance. In some cases it will be necessary to use a IOO-megohm VTVM on
the most sensitive scale (0-1 volt on the Hewlett-Packard 41OB) and use external
multipliers to avoid loading the test circuit.
Leakage Currents. A leakage current is measured at a specified reverse voltage
applied across the appropriate terminals of a transistor. This voltage is usually
one-half to two-thirds of the value of the breakdown voltage, BVxxx. Measure-
ment of this sort is often used to guarantee a minimum breakdown voltage.
Typical leakage parameters measured are ICBo (collector-base leakage, emitter
open), ICEO (collector-emitter leakage, base open), and lEBO (emitter-base leakage,
collector open).
Variations of the collector-emitter leakage measurement include ICER (resistive
59
60 Fundamental Considerations

+o---------------~----------------_,
High impedance
VTVM
Transistor
under test
(NPN)
t
constant
current
source

(a) Measurement of BVCBO

+o---------------~----------------_,

High impedance
VTVM
Transistor
under test
(NPN)
t
constant
current
source

(b) Measurement of BVCEO


Figure 5.1

termination between base and emitter), ICEX(bias applied between base and emitter),
and ICES (emitter-base short-circuited).
A typical ICBo measuring circuit is illustrated in Fig. 5.2 for an NPN transistor.
(Reverse all polarities for PNP transistor measurement.) The - V CB source should
have fairly high resistance so that a shorted unit will not take out the power supply.
The purpose of the silicon diode and 8.2-kilohm resistor (plus the 4-kilohm meter
resistance) is to shunt the meter at approximately a 2: I overload. The push-button
"Diode Out" switch provides a quick check on the shunting effect of the diode for
a critical measurement. A microammeter or electrometer is used to read the
leakage current.

5.2. PULSE TESTING


Pulse testing is used to minimize heating effects that might change the parameter
being measured. Parameters normally measured by this method are hFE' VCE(sat)'
VBE, breakdown voltage, and in-production testing of thermal resistance. The

0·15 p.a
+

Diode
OUT

Transistor
under test
(NPN) Figure 5.2
Measurement of Electrical Quantities and Parameters 61

following sections discuss the test circuits used to measure the above parameters
for the 2N337, 2N497, 2N1047, and 2N389 transistors. This method or a similar
method is used to test other transistors.
hFE Pulse Testing. In pulse testing for hFE, it is convenient to measure the
voltage drop across a resistor in series with the base lead. This determines the base
current,IB , at a specified collector current, Ie, and collector-to-emitter voltage, VeE.
From this information, hFE can be computed from Ie/h. Figure 5.3 shows a typical
collector characteristic for the common-emitter configuration.
In the quiescent state, the transistor under test is held at point 1 in Fig. 5.3.
During the testing cycle, the collector current is pulsed ON, driving the transistor
to point 2. The unit under test is held at this point for 300 J.Lsec, and then returned
to point 1 where it remains for a period of 14 msec. This means that the transistor is
under test conditions only 2% of the time. A pulse width of 300 J.Lsec was chosen
so that the rise and fall time of the unit under test would not be an appreciable
portion of the test cycle. This pulse width is short enough to allow a minimum of
junction heating. The measurement of hFE is made while the transistor is at point 2.
A block diagram of the hFE pulse test set is shown in Fig. 5.4.
The pulse generator produces a negative pulse which operates the switch, allowing
the collector current to flow into the unit under test. During the remaining portion
of the pulse period, the collector current is shunted to ground through the switch.
The pulse amplitude is not particularly critical but must be sufficient to operate the
switch and allow the full collector current to flow. The driving amplifier uses a
differential input with the transistor under test in the feedback loop. Point B is
the summing junction of the operational amplifier and is forced to assume the same
potential as the other input (ground) during the ON time of the pulse. This will
cause the collector of the transistor under test to be at ground. When this occurs,
the required VeE is supplied by the constant voltage supply.
The readout method shown in Fig. 5.4 permits the use ofa peak-to-peak VTVM,
measuring the voltage drop across R. A differential amplifier is connected across
R and the VTVM is connected between the output of the amplifier and ground.
For a fixed value of collector current, the meter can be calibrated directly in terms
of hFE .
co
E

Constant collector
current line fixed by ~~ Point 2 fixed by
power supply during 1/ _ intersection of
pulse testing time - constant Ie line
I and VeE line

VeE. volts
Figure 5.3
62 Fundamental Considerations

!-- 14 msec -1
6{300P~

:
I Constant

~
current
source

B A
..rL. -U- Pulse
generator

Test
transistor
Constant
voltage supply

Peak-to-peak
VTVM

Fig. 5.4. Voltage waveshapes as a function of time.

The foregoing circuit is used for different transistors merely by changing the
constant-current and constant-voltage sources to the appropriate values for the
types being tested.
VOE(sat)' Ros Pulse Testing. In pulse testing for Ros, it is convenient merely to
measure the collector saturation voltage VOE(sat) at a specified collector current 10 •
If necessary, Ros can then be computed from VOE(sat)/Io. For a given 10 value,
VOE(sat) is defined as the collector-to-emitter voltage that exists when an increase in
base current produces no change in VeE. To ensure that even the lowest beta unit
is driven into saturation, an excess of base current should be used. Figure 5.5
shows both the V OE(sat) point (for a particular I 0 value) and the Res line on a typical
collector characteristic for the common-emitter connection.

'"
E

Point 2 fixed by
intersection of /" Constant collector
constant Ie line
I current line fixed
and Res line ----- by test transistor
power supply during
pulse testing time

L_---------~ Point 1 fixed by


test transistor
power supply

VeE, volts
Figure 5.5
Measurement of Electrical Quantities and Parameters 63

In the quiescent state, the transistor under test is held at point 1 in Fig. 5.5.
During the testing cycle, the base current is pulsed ON, driving the transistor to
point 2. The unit under test is held at this point for 300 flsec and then returned to
point 1 where it remains for a period of 14 msec. This means that the transistor
is under test conditions only 2% of the time. The measurement of VCE(sat) is made
while the transistor is at point 2. A block diagram of the VOE(sat) pulse test set is
shown in Fig. 5.6.
The pulse generator produces a negative pulse which operates switch 1 and allows
the driving current to flow into the base of the transistor under test. During the
remaining portion of the pulse period, the base current is shunted to ground through
switch 1. The pulse amplitude is not particularly critical, but it must be sufficient
to operate switch I and allow the base current supply to drive the transistor under
test into saturation. The pulse observed at the collector of the unit under test is
shown in waveform C.
A readout method as shown in Fig. 5.6 enables one to use a peak-to-peak VTVM
and directly measure the VOE(sat) voltage. The pulse from the pulse generator is
integrated, and the slowly rising leading edge is used to trigger a one-shot multi-
vibrator whose pulse width is set at something less than 300 flsec (in particular, the

,·>----14
... msec----l
I I I
+j r-300 t-lsec :
I I
A

B
C
Constant Constant
current current o
source source

E
C
.A---tLJ"

Time--+

Peak·to·peak
VTVM

J
Figure 5.6
64 Fundamental Considerations

Re

-=- Vee

Figure 5.7

multivibrator pulse must terminate before the 300-p,sec pulse ends). The multi-
vibrator turns ON switch 2 (one 2N497), which forces the emitter of the 2N497 to
assume nearly the same voltage as its collector, which in turn is the same voltage
as the collector of the transistor under test. So long as VeE(sat) for the 2N497 is
very small compared to VeE(sat) for the transistor under test, the peak-to-peak VTVM
will read the desired pulse amplitude.
The foregoing circuit is used for different transistors merely by changing the
constant-current sources to the appropriate values for the types being tested.
Definition of VBE(sat). V BE is the d-c voltage that appears between the base and
emitter of a transistor when it is operating. If the transistor is operating in a
common-emitter circuit, VBE will be the voltage that appears on the base as shown in
Fig. 5.7. VBEwill be positive for NPN transistors and negative for PNP transistors.
If the ratio of the collector current Ie to the base IB is less than the hpE(P) of
the transistor, it is said to be saturated. That is, for standard conditions,
Ie
IB < hpE (1)

When the transistor is saturated, the voltage that appears on the base is called
the saturated V BE, or VBE(sat).
Measurements of VBE(sat) are made by driving a constant collector current Ie into
the collector and a constant base current IB into the base. A block diagram for
measuring VBE(sat) is shown in Fig. 5.8.
In general, the VBE of an unsaturated transistor has a negative temperature
coefficient. That is, if the temperature of the transistor goes up, the VBE will go
down.
At Texas Instruments, the pulse-testing technique is used to minimize transistor
junction heating due to power dissipation during the test. To make such a test, a
pulse generator is used to drive the collector and base current sources. This gen-
erator generates a positive pulse of approximately 300 p,sec duration and an OFF

Figure 5.8
Measurement of Electrical Quantities and Parameters 65

Figure 5.9

time of approximately 15 msec. The waveform from this pulse generator is shown
in Fig. 5.9.
The duty cycle of this type of wave is approximately 2%. Rise and fall times of
the pulses are kept between 10 and 20 }Lsec so that high-frequency harmonics will
be negligible.
The pulse generator used at Texas Instruments has a high output impedance; it
is used therefore to drive a pulse amplifier. This pulse amplifier uses two transistors
in a Darlington connection as an emitter follower (shown in Fig. 5.10).
The input impedance of this amplifier is equal to the hFE of the Darlington-
connected transistors multiplied by R L . That is,
Z(in) ~ RL(hpEQ1)(hFEQ2) (2)
The output impedance of the Darlington pair is equal to the generator impedance
Ra divided by (hFE Ql)(hpE (2). That is,
Ra
Z(out) ~ - , : : - - - " ' = - - - , - (3)
(hpE Ql)(hFE (2)
In order to drive a constant current into the collector and base of the transistor
under test, it is necessary to use a constant-current regulator that will regulate with
a load voltage variation from zero to 10 volts. A simple current generator is shown
in Fig. 5.11.
This current regulator is basically an emitter-follower. The resistor Rl and the
reference diode D form a voltage divider between the power supply and ground.
The reference diode will keep the voltage constant between the base of the transistor
and the power supply. The VBE of a transistor is nearly constant over its operating
range. The voltage drop across ~2 will be equal to the reference voltage of the
zener diode Vz minus the VBE of the transistor,
(4)

Jl
Output

Fig. 5.10. Emitter-follower amplifier.


66 Fundamental Considerations

Fig. 5.11. Current regulator.

The current that flows through the resistor R2 to give this voltage drop is equal
to the base and collector currents of the transistor,
IR2 = IB + Ie (5)
Ie, being the load current, is equal to IB times the hpE of the transistor,
Ie = I~PE (6)
Solving these equations for Ie in terms of Vz, VBE, hpE, and R 2 , we have
I _ (Vz - VBE)hpE
(7)
e- (1 + B)R2
If the hpE of the transistor is large with respect to 1, this equation will reduce to

Ie = Vz - VBE (8)
R2
The voltage drop across the load cannot exceed the voltage of the power supply
minus V z. Rl is chosen to give a good operating current through the diode.
Since there is no capacity in this current regulator, its response is very fast.
Driven with a pulse source, it will produce an output of constant-current pulses.
Peak voltage can be read using a rectifier, filter capacitor, amplifiers, and d-c
meter as shown in Fig. 5.12.
In this circuit, the input pulse is amplified by the first amplifier A 1 . The gain of
Al must be a known constant value. The diode D rectifies these pulses and
charges the capacitor C. The reverse resistance of the diode and the input resist-
ance of the amplifier are about 100 megohms each. This gives a parallel combined
resistance of approximately 50 megohms through which the capacitor must dis-
charge. A small capacitor will, therefore, give a large time constant. The amplifier
A2 has a gain of one and will have the same voltage as the capacitor at its output.
The readout meter M is a 20,OOO-ohmjvolt d-c meter.

Jl Jl
Figure 5.12
Measurement of Electrical Quantities and Parameters 67

Jl

Figure 5.13

The pulse test circuit used at Texas Instruments is built up using the above
described circuit elements. Figure 5.13 shows a simplified drawing of the complete
pulse VBE test circuit.
In this test circuit, the pulses from the pulse generator are amplified by the pulse
amplifier. The output from the pulse amplifier drives the collector (Ic) and base
(IB ) current regulators. The current pulses drive the collector and base of the
transistor under test. The peak-reading amplifier circuit is used to read the VBE(sat)
voltage pulses that appear on the base of the transistor under test.
Breakdown Voltage Pulse Testing. Although the following pulse measurement
discussion covers a particular breakdown voltage, BVOER, all breakdown voltage
measurements can be made using similar pulse-testing procedures. Only slight
changes of the transistor connection in the pulse circuit will be required.
BVOER is defined as the breakdown voltage from collector to emitter with a turn-
off resistor connected between the base and emitter of the transistor. This break-
down voltage is found to be considerably smaller for large currents than for small
currents. BVOER is, therefore, measured at current values near the maximum
operating range.
Figure 5.14 shows a circuit that can be used to measure the BVOER of transistors.
This circuit uses a constant-current generator to drive a predetermined 10 into
the collector, and a meter to measure the breakdown voltage. The resistor R is
used to turn the transistor OFF. This circuit will measure BVOER, but it may
damage the transistor because of excessive power dissipation. This power dissipa-
tion is equal to BVOER times 10 • Typical values may be
BVOER = 100 volts
10 = 100 rna
Power = (100)(0.10) = 10 watts
Thus 10 watts might be dissipated in a I-watt transistor.

Figure 5.14
68 Fundamental Considerations

In order to reduce this power dissipation, Texas Instruments uses the pulse-
testing technique. To make this test, a pulse generator is used to drive the collector
current source. This generator has a positive pulse output of approximately 300
p,sec duration and an OFF time of approximately 15 msec. The resultant waveform
is shown in Fig. 5.9.
The duty cycle of this wave is about 2%. The power dissipated in the transistor
using the pulse technique will be 2% of 10 watts, or 0.2 watt. This power should
not damage a I-watt transistor.
To obtain a pulse source with enough power to drive a BVOER test set, a pulse
generator is used to drive an emitter-follower amplifier. The amplifier uses two
transistors in a Darlington connection as an emitter-follower (shown in Fig. 5.10).
The pulse output from the amplifier is used to drive a constant-current regulator
(Fig. 5.11).
Peak voltage can be read using a rectifier, filter capacitor, follower amplifier, and
d-c meter (Fig. 5.12). Amplifier Al is not required for large breakdown voltage
measurements.
The BVOER test circuit used at Texas Instruments is composed of the above-
described circuit elements; a block diagram of this test set is shown in Fig. 5.15.
In this test circuit, the pulses from the pulse generator are amplified and used to
drive the current regulator. These current pulses are driven into the collector of
the transistor under test. The amplitude of the voltage pulses that appear on the
collector is equal to BVOER . These pulses are integrated by R1Cl and then read on
the meter with the peak-reading network. The meter reads directly in B VOER volts.
Thermal Resistance Test Set. The forward voltage drop of a silicon diode at
25°C will range from 0.5 to 1.0 volt at low currents. This voltage drop reduces as
a linear function of temperature until the drop is about 0.2 volt for most diodes.
That is:

This phenomenon can be used to measure the change in collector junction tem-
perature of silicon transistors. A similar phenomenon exists for germanium
transistors and is used in the same manner.
The thermal resistance from junction to case of the transistor, OJ_O, is defined as
the collector junction to case temperature differential, IJ.TJ _o, per watt of dissipation
in the transistor.
o _ IJ.TJ _o
J-O - P

Figure S.lS
Measurement of Electrical Quantities and Parameters 69

I
I
I
I
I
I
I
I
______ ..JI

SI

Figure 5.16

A block diagram of a thermal resistance test set is shown in Fig. 5.16.


This test set uses the pulse technique. It uses about 2% of the test time to drive
current through the base-collector diode in the forward direction, measuring the
change in the forward voltage drop as the transistor is heated; 98% of the test time
is used to dissipate power in the transistor.
IB is adjusted to about 100 /-ta. Ve is adjusted to the specified VeE of the tran-
sistor under test. AR1 is a peak-reading amplifier. It will detect pulses on its input
and give an output d-c voltage level that is equal to the peaks of the input pulses.
AR2 is a differential amplifier. The gate opens the emitter of the transistor under
test 2% of the time and shorts it to the Ve power supply 98% of the time.
To start the test of a transistor, switch S1 is put in the position shown. The tran-
sistor is inserted and the amplifier AR1 will have an output equal to the forward
voltage drop of the base-collector diode. This voltage is stored on the capacitor
C and will remain there during the remainder of the test. S1 is then switched to
the other position. R is adjusted until the proper current flows through the tran-
sistor. The power dissipation in the transistor will be indicated on the wattmeter
M 1 . The change in voltage drop across the base-collector diode will be indicated
on the voltmeter M 2 , which can be calibrated in degrees centigrade.
To obtain the thermal resistance of a transistor, the power must be left on the
transistor long enough for it to reach an equilibrium temperature.

5.3. SMALL-SIGNAL PARAMETER MEASUREMENTS AND TEST CIRCUITS

The subject of h parameters is exhaustively covered in the literature. The inten-


tion here is not to discuss these parameters, but rather to show the basic test circuits
for the four h parameters currently being used by Texas Instruments in an attempt to
achieve a higher degree of correlation between company and customer. A brief
70 Fundamental Considerations

0.1 mv Cal
20 db amplifier

~P.f
and
1,000'" filter
0.1p.f Test

Fig. 5.17. hr. test set.

discussion of these parameters may be found in the Equivalent Circuits section of


this manual, Chap. 6.
Definition of h fe . The parameter hte is used at Texas Instruments since it
appears to be a more universally accepted and more useful measurement than hfb.
Values of hfb can be derived from h fe by using the following formula:
-hfe
hfb - 1 + h fe
The basic test circuit for hIe is shown in Fig. 5.17. A similar circuit can be derived
for measuring hfb.
The ratio h fe is defined as the small-signal short-circuit forward current transfer
ratio.
h _ die at Vee = constant (9)
fe - dh

Holding h to a fixed value of 1 [La alternating current will result in a test set
capable of reading directly in hIe. A calibration level of 10 mv was chosen so that
direct readings of hIe from 10 to 100 can be obtained on the lO-mv scale. Ifreadings
higher than 100 or lower than 10 are required, these may be obtained by changing
to a higher or lower range.
0.1 mv Cal
20 db amplifier
and
1,OOO"'filter

Vc
Fig. 5.18. hib test set.
Measurement of Electrical Quantities and Parameters 71

Definition of h ib • The basic test circuit for h ib is shown in Fig. 5.18. This
parameter is defined as the short-circuit input resistance.

at Veb = constant (10)

As with h(e, if a fixed value of input current is used, the output meter will give
a direct reading of hib • The calibration level of 10 mv remains so that direct readings
of hib from 10 to 100 ohms are obtained on the lO-mv scale.
Definition of hob. Figure 5.19 shows the basic test circuit for hob, the small-
signal value of the open-circuit output admittance.
_ die
h ob - -- at ie = constant (11)
dVeb

In this measurement the input voltage is held constant at 1 volt, and the current
is read as the voltage drop across the I-kilohm resistor.
h _ output reading, volts/! kilohm (12)
ob - 1 volt
hob = output reading, mv, and will be a direct reading in f-tmhos
Thus, a value of hob from 0.1 to 1 f-tmho is read directly on the lO-mv scale. The
calibration level for this parameter is the same as the previous ones, 10 mv.
Definition of hrb • The basic test circuit for h rb is shown in Fig. 5.20. The ratio
hrb is defined as the small-signal value of the open-circuit reverse voltage transfer
ratio.
h rb = dVeb at ie = constant (13)
dv cb
The output voltage is held constant in this measurement, so that variations of
input voltage will give a direct reading of h rb on the output meter. Direct readings
of hrb from 100 to 1,000 (X 10-6) are read on the lO-mv scale.

Test
20 db amplifier
Test and
transistor Cal 1,000N filter
0.1 mv

0.001 0.001
/.If /.If
1K
1%
Vc
Fig. 5.19. hob test set.
72 Fundamental Considerations

Test
20 db amplifier
Test and
transistor Cal 1,000'" filter
0.1 v
0.1 mv
O.l.u f
10v

0.001 0.001
.uf .uf

Vc
Fig. 5.20. hrb test set.

These test circuits should give good correlation since the basic test circuit is the
same as that used by Texas Instruments for production testing. The recommended
readout meter is a Ballantine 310A or equivalent. The 1,000-cyc1e filter used is a
UTC BMI-lOOO. Use of the 20-db amplifier will allow direct reading of all
parameters on one meter scale. The noise level of the amplifier should be low in
comparison to the readings observed on the meter. The recommended signal
generator is a Hewlett-Packard 200CD.

5.4. HIGH-FREQUENCY MEASUREMENTS


Measurements Using Commercial Test Equipment. Measurements of small-
signal a-c transistor parameters in the high-frequency range (> 1 me) are usually
made using commercially available test equipment. However, this test equipment
is not often designed for testing production quantities. Texas Instruments has
found four items of commercial test equipment which are convenient for quantity
testing. The following list indicates the parameters measured and the frequency
range used with each piece of test equipment:
1. Wayne-Kerr, model B60l:
Frequency range: 15 kc to 5 me.
Parameters measured: Yib, Yob, Yie, Yfe, and hfb (requires standard adapters).
Also used to measure Cob, Cil» and CTE at 1 me.
Measurement range: Capacitance 0.01 to 20,000 pf.
Resistance 10 ohms to 10 megohms.
2. Wayne-Kerr, model B801:
Frequency range: 1 to 100 me.
Parameters measured: Yib,Yob,Yie, and yoe (requires the building of adapters).
Measurement range: Capacitance 0 to 235 pf.
Conductance 99.9 to 0.1 mmho.
3. General Radio transfer function and immittance bridge, type 1607-A:
Frequency range: 25 to 1,500 me with reduced accuracy above 1,000 me.
Measurement of Electrical Quantities and Parameters 73

Parameters measured: Yi, Yo, Yr, Yr, Zi, Zo, Zr, zr, hi, ho, hr, and hr for all con-
figurations (common emitter, etc.).
Measurement range:
Voltage and current ratios. . . . . . . . . . . . . . . . .. 0-30 ohms
Transimpedances Zr . ...................... 0-1,500 ohms
Transadmittance Y r . . . . . . . . . . . . . . . . . . . . . .. 0-600 mmhos
Impedance Zi ............................ 0-1,000 ohms
Admittance Y i . . . . . . . . . . . . . . . . . . . . . . . . . . , 0-400 mmhos
4. Boonton RX meter:
Frequency range: 0.5 to 250 mc.
Parameters measured: admittances such as Yi, Yo, and ho.
Commonly used to obtain parallel input and output resistance and capaci-
tance (rp, Cp ). Requires printed circuit board adapters.
Measurement range: Capacitance +25 to -100 pf.*
Resistance 15 ohms to 00.
Ih{eIMeasurement. The measurement of Ih{el at some higher frequency than
1,000 cps is useful for two purposes: A design engineer using the devices in the
common-emitter configuration in a high-frequency application needs this informa-
tion for proper design, and the information obtained is useful in the calculation of
power gain. The formula used in calculating power gain, assuming a conjugate
match loss less neutralization, is

Ap = Ih{el db + 10 log (4r~r,es ) (14)

where r o is the parallel output resistance with the input shorted and ries is the series
input resistance with the output shorted.
If Ih{el is read directly in decibels, then the calculations of power gain are con-
siderably simpler. If required, Ihrel can be converted to a numerical value by ap-
plying the following formula:

Ih{e Inumeric = ant!'1og (Ihfel20db) (15)

A first approximation of the gain-bandwidth product,fT> is often obtained by


measuring Ih{el at some frequency well above the frequency at which Ih{el has fallen
°
3 db (fhfe), and extrapolating to Ihfel = db at the rate of 6 db/octave or 20 db/
decade. For greatest accuracy, the test frequency should lie about halfway be-
tween Ihfe and the expected fro fr can also be obtained by multiplying the numeri-
cal measured gain by the test-point frequency if this frequency is well above the
upper comer frequency (fhfe).
The measurement of Ihfel at frequencies above 30 mc and below 1,500 mc
is often made using a General Radio transfer function and immittance bridge, type
1607-A. For measurements up to and including 100 mc, the basic measuring cir-
cuit shown in Fig. 5.21 can be used; however, extreme care in the circuit layout is
required if measurements are to be made above 30 mc. This circuit should
* Negative reading indicates inductance.
74 Fundamental Considerations

In
disk
(microwave
resistor)

VeE
Fig. 5.21. High-frequency hr. test set.

be built in a metal box, preferably brass. At frequencies above 20 me the use of


feed-through capacitors CFT in addition to the bypass capacitors C1 and C2 is
recommended. All leads should be kept as short as possible, and shielding be-
tween input and output is essential. The chokes Ll and L2 are chosen so that they
will be self-resonant at or slightly above the measuring frequency.
To calibrate the test set, a short circuit is inserted between collector and base,
and the signal generator output is adjusted until a convenient reference level is ob-
tained on the output meter. The input signal level is kept low enough to avoid
exceeding true small-signal conditions.
The readout meter should have a 50-ohm termination and a direct-reading
decibel scale, and should be capable of operating over the desired frequency range.
It is desirable to use at least one range higher than the lowest range of the meter,
since this will allow a - db reading.
Cob Measurement. The capacitance between the collector and base (Cob)
consists of two parameters, a collector transition capacitance and a collector dif-
fusion capacitance. The collector transition capacitance C TC is due to the space-
charge region at the collector-base junction. Neglecting a small ohmic drop, the
entire reverse bias applied between the collector and base appears across this
junction. Since a high electric field is maintained here, all free charge carriers are
swept out of a narrow region, leaving only the nuclei and bound electrons. This

EBaliantine

Basic divider circuit


E _ EgR 2 Basic Cob test circuit
R-;-
Ballantine-
1
where R 2 « R 1 Xcob = 27r[C o b

Figure 5.22 Figure 5.23


Measurement of Electrical Quantities and Parameters 75

space-charge region has a charge per unit volume which is equal to the impurity
concentration times the electronic charge q. This collector junction capacitance
shunts the output circuit, and in this respect it is very similar to the plate-to-grid
capacitance of a vacuum tube, and limits high-frequency gain in exactly the same
manner. Collector diffusion capacitance Cdc varies directly as the collector cur-
rent, and effectively parallels C TC so that Cob = C TC + Cdc.
The capacitance between the emitter and collector leads can be neglected since
it is reduced by l/(h fe + 1) at the collector-base terminals.
The capacitance between the collector and base of a transistor can be determined
by applying a high-frequency signal to the collector and measuring the current
passed by the Cob at the transistor. This measurement is valid provided the fol-
lowing requirements are met: The signal is a high-frequency low-level source, the
emitter circuit is open to the a-c signal, and the reactive component Xob is approxi-
mately equal to the impedance Zob of the transistor.
Figure 5.22 shows the basic voltage-divider circuit of the Cob test. If R2 is
negligible (~100 ohms) compared to R1 (~10 kilohms), then 11 is proportional
to E g / R1 and EBallantine = E gR 2/ R 1.
Texas Instruments recommends the use of a circuit similar to the one shown in
Fig. 5.23, or a Wayne-Kerr bridge model B60l, for measuring Cob. In the circuit
of Fig. 5.23, a l-mc signal is fed across the divider network Cob of the transistor
and the 100-ohm resistor. The Ballantine meter reads the alternating current
across the 100-ohm resistor. The recommended readout is a 310 Ballantine
or equivalent. The test set should be wired to minimize stray capacitance. A test
socket made of Teflon® is desirable.
riep, Ciep, r oep , and coep Measurement. Measurement of input and output resist-
ance at some frequency other than 1,000 cps is desirable in a good many cases. If
a designer plans to use the devices in the megacycle ranges, this information
is necessary for the proper design of IF strips, high-frequency tuned amplifiers,
and other applications of this type. The easiest way to make these measurements
is with the Boonton RX meter and printed circuit test boards.
Figure 5.24 shows the circuit used with the RX meter to measure roep and Coep,
the parallel output resistance, common emitter, and the parallel output capacitance,
common emitter. These two values are read directly from the dials of the RX
meter in terms of resistance and capacitance.
Figure 5.25 shows the circuit used to measure riep and Ciep- riep is the parallel
input resistance, common emitter, while Ciep is the input capacitance, common

Ve O OLow vB1 0 OLow


I I I I
Ve:
VB
rB~002 RX meter

v': y02[;B RX meter

OHigh
OHigh Vc c
Fig. 5.24. roepcoep. Fig. 5.25. riepCiep'
76 Fundamental Considerations

emitter. These parameters are read directly from the RX meters. In design of IF
strips, these parameters are far more useful than the equivalent series parameters,
but for the calculation of power gain, the series input resistance is easier to use.
Formulas for converting the parallel measurements to series resistance and series
capacitance are:

Parallel input and output impedance can also be measured in the common-base
configuration. Also, these parameters can be measured with desired input or out-
put terminations.
The RX meter circuit board details are shown in Figs. 5.26 and 5.27.

5.5. SWITCHING TIME MEASUREMENTS

The Complete System. Transistor switching times are usually measured in a


system as shown in Fig. 5.28.
The resultant waveforms for an NPN transistor in this system are shown in
Fig. 5.29.
The accuracy of switching time measurements is affected by the rise time of the
test system. Since the transistor is connected between the pulse source and the
oscilloscope, the response of these test instruments will cause an increase in the
measured transistor response time.
Equation (16) can be used to determine the transistor rise time if the system rise
time is known.

( ::)2 (ti~~eOf)2
measured transistor
+ ( t~~eOf
test system
)2 (16)

The system rise time can be observed by removing the transistor and shorting
the base-to-collector terminals on the test setup. Then by using the system rise
time and the measured rise time of the transistor, the per cent error can be com-
puted, using

% error = 100 [ Ir measured (17)


vi (trmeasured)2 - (trsystem)2

If trsy'tem < 1f2trmeasured, then

% error - 50 ( Ir system )2 (18)


trmeasured

This relationship is shown graphically in Fig. 5.30. From this we see that to have
an error ofless than 5% the equipment must be at least three times faster than what
is being measured.
Coaxial Line Generators. A pulse generated by a coaxial line pulse generator
is dependent upon the electric charge stored in a coaxial cable. The length of the
Measurement of Electrical Quantities and Parameters 77

(see note 3

~+---~--+----;

E C

See note 1
~

See note 4

r----2,i------t
1#

Test board

1~
21.8

c ~-It-- . To RX meter
general terminal
'------~ To RX meter
high terminal
Schematic diagram
hRTYP
Corners of cutout
to be sharp
as possible

Notes: Note:
(1) Mount bottom of subminiature socket flush with (A) Bottom view shown.
copper side of board. Cement in place. (B) Shaded portion indicates
(2) Leads of capacitor to be short as possible. copper.
Solder in place as near to RX meter ground
terminal as possible without interference. Material:
(3) Symbolize board as shown with approximate Grade FF·91 Phenolic -h thick
size of characters shown. Decals permissible. with 2 at copper one side.
(4) Mark collector end of socket red.
(5) Shaded portion indicates copper.

Fig. 5.26. RX meter roepcoepo


78 Fundamental Considerations

See note 3

E C
1
.....- - - - t - - - - - YHE

See note 4

E G

11
Test board

To RX meter 222-
GND terminal 16

To RX meter
L...;;;;....._~ high terminal
Schematic diagram

Corners of
cutout to be
sharp as
possible

Notes: Note:
(1) Mount bottom of subminiature socket flush with (A) Bottom view shown.
copper side of board. Cement in place. (B) Shaded portion indicates
(2) Leads of capacitor to be short as possible. copper.
Solder in place as near to RX meter ground
terminal as possible without interference. Material:
(3) Symbolize board as shown with approximate Grade FF-91 Phenolic lothick
size of characters shown. Decals permissible. with 2 oz copper one side.
(4) Mark collector end of socket red.
(5) Shaded portion indicates copper.
Fig. 5.27. RX meter riepCiep.
Measurement of Electrical Quantities and Parameters 79

Coaxial cable

I I
o
Vee supply
External

II trigger

Scope
Dual trace

Plug-in

Transistor test circuit


Fig. 5.28. Typical switching time test setup.

cable determines the pulse width, and the amount of charge determines the pulse
amplitude. A circuit diagram of a typical coaxial generator is shown in Fig. 5.31.
A very fast rise pulse is generated using this method, by the closing of the relay
contacts. The trailing edge of the pulse, however, must propagate to the open end
of the cable and back. This length of cable attenuates the high-frequency com-
ponents of the pulse, causing a long fall time for wide pulses. Figure 5.32 shows
the relationship among the pulse width, type of pulse-forming cable, cable length,
and pulse fall time.
Transistor Circuit Termination. It is important that the test circuit properly
terminate the input pulse from the generator. The terminating resistor Ro in Fig.
5.33 must be located as close as possible to the output end (not the signal generator

I
90%
t
10% I
I
I
I
I
\I
I
I
Input
voltage
t

I
I I
10%
I Vee
I I
Collector
I I
I voltage
I
I
90%
I I
I
I I ! VeE(sat)
I I I I I
td f-- tr -l I--- ts -4- tf -l
td = delay time ts = storage time
tr = rise time tf =fall time
tON=td+tr t OFF = ts + tf

TT = tON+ tOFF

Fig. 5.29. Switching time definitions.


80 Fundamental Considerations
10%
I
~
J
3%
V
2% /
~
~
0%
10 5 4 3 2 1
Indicated time (with transistor)
Ratio of S t' .
ys em rise time (without transistor) Fig. S.30 • Test system error.

end) of the cable, to keep the signal at a constant impedance level throughout its
path, to prevent reflections. As a further precaution against reflections, the lead
length from the cable termination to the transistor input should be as short as
possible.
Figure 5.33 shows how the proper termination resistance can be maintained when
the base-driving resistance is low.
Coupling Capacitor. When the d-c level of the transistor test circuit must be
isolated from the pulse generator, the coupling capacitor must be chosen to elimi-
nate droop (see Fig. 5.34). The per cent droop may be determined from
%D = 100 (1 - ctlRC) (19)

v Pulse amplitude and polarity,


determined by value of V

Open (50 n coaxial) (50 n coaxial)


(
pulse·forming cable connecting cable
+------------ t}-------------

\. .\ \~ -= "-output connector
Mercury·wetted·contact relay
enclosed in a coaxial fitting
Connector for pulse· Test
forming cable circuit
Output waveform

~~ ~ Fall time due t~ response of


vt 2"/I pulse·formlng cable

-12t
to
p ~
-- t
tp= propagation time of
pulse·forming cable
to =time of relay contacts closing
Fig. S.31. Coaxial pulse generator.
Measurement of Electrical Quantities and Parameters 81

500
150
'"., (u//
".
~
~

~ V ~ '"
100 u
~G·\.
Q)

.:= U VJ

£,~
0
c
.c ~G' 200 ro
., c:

., 7 ~0-Yf>\~
blJ
c: ~I-" ~~
.!!1 50 ~
~ :E
~ ""0
Q)
::0 ~ ~I-"
.~

ro / Q)

-- --
". L.,..oo
U
J.;"'"
100 .!!!
:J
./ ./ CL
/'
./ ". ./
20 ~ V I'
./ """~ 50
0.1 0.2 0.5 1.0 2.0 5.0 10.0
Fall time of pulse, nanosec
Fig. 5.32. Fall time of pulse vs. pulse width.

Problem: Effective termination less


than 50n because of
( loading by base-emitter
Pulse junction.
50 n connecting cable r. A~----'
~~g~e:ne:r~at~o:r~~~~~~~~~~r-~~--;

Vee

Solution:
Base-emitter junction has
negligible effecton
(
line termination.
Pulse 50 n connecting cable
generator o!------------

Pulse amplitude from generator Vee


must be increased to 5 times
the original value to compensate
for loss in the termination network.
Fig. 5.33. Termination resistance.

From pulse To test


generator circuit
Fig. 5.34. Pulse droop.
82 Fundamental Considerations

where C = capacitance, f-Lf


R = total loading effect, ohms (including transistor)
I = pulse width, f-Lsec
% D = % droop at end of pulse
If I < ~oRC, then

%D-IOO;C

Therefore, to maintain less than 1% droop,


C> lOOt (20)
- R
Figure 5.35 shows some typical values of R and C used in test circuits.
Even though the value of the coupling capacitor is large enough to eliminate
droop, there remains the problem of d-c level shift due to the charging of the
coupling capacitor (see Fig. 5.36). When

Ip + I' ~ RC

this level shift is proportional to the duty cycle of the input pulse,
S = Eptpfp
where S = d-c level shift
Ep =
pulse amplitude
Ip =
pulse width, sec
fp = pulse repetition rate, pulses/sec
From this we see that it is best to use a duty cycle of less than 5%.

10.0 .-------.--------.------"7"'"-,.

Q)
g Q) 2.0 I------I-----~r_f_--~
'" en
~3
16 c.. 1.0 I------t---T-~r--+~
~o
Uc..
_0
o
Q)"Q
e
.2 ~ 0.2 f - - - - - -
~ ......
E V 0.1 f-----~_7f_
::J ~

E.8
c
~

0.02 JL---~--~I'-~---t------1
0.01 L -_ _--iIl.'---'L-_ _ _ _L..-_ _ _ ~

0.01 0.1 1.0 10.0 Fig. 5.35. Minimum value


Pulse width, p.sec for coupling capacitor.
Measurement of Electrical Quantities and Parameters 83

O~--~r--~~---o

Fig. 5.36. D-c shift with capacitor coupling.

Bypass Capacitors. Even though power supplies with good regulation are
used for V BB and Vee in Fig. 5.37, their recovery time and lead inductance may
prevent the voltage from remaining constant at the test circuit. Therefore, C2 and
C3 must be used to provide adequate high-frequency bypassing at the V BB and Vee
terminals of the test set.
All leads should be kept as short as possible to keep inductance low. Even so,
some larger capacitors, especially paper and electrolytic types, will cause ringing,
owing to their series inductance. A low-inductance mica or ceramic capacitor may
be used in parallel with the larger one to reduce ringing. Sometimes the combina-
tion of capacitors will resonate and make the ringing worse. In this case several
combinations should be tried while the point to be bypassed is monitored with a
scope.
Emitter-Base Breakdown Protection. The emitter-base breakdown voltage
rating should not be exceeded in the test circuit. One solution is to keep VBB low
enough to prevent emitter-base breakdown, but a low value of VBB will cause
variations of the turn-off current with variations in VBE(on).
Assume that a high value of VBB (10 volts) is used in Fig. 5.38a to maintain a
constant turn-off base current with variations of VBE(on) of different test transistors.
The turn-off current from the base is a transient current and will cease when the
charge is removed from the base region. Therefore, the voltage at the base tends
to rise toward the value

A------....------o Output

Pulse
input

Fig. 5.37. Bypass capacitors.


84 Fundamental Considerations

ft-----<.......-oOutput

t----o+

Input Vee

(a)
A---p__-o Output

...----0+
Input

(b)
Fig. 5.38. BVEBO protection circuit.

If IVBE(Oml > IBVEBOI, a fast computer diode may be used to clamp the voltage at
the base to a value lower than BVEBO of the test transistor. Figure 5.38b shows a
IN916 diode used for this purpose. For a PNP transistor, the diode polarity would
be reversed.
Scope Probe Adjustment. Most scopes require the use of probes to reduce
the capacitive loading on the circuit and increase the input resistance. The probes
must be adjusted so that the RC product of the probe is equal to the RC product
of the scope input circuit (see Fig. 5.39).
When properly adjusted, the phase shift is at a minimum and the frequency
response is flat (within the passband of the scope). Figure 5.40 shows the effect
of this adjustment on a pulse ..
It is important to have a nearly perfect pulse for making this adjustment.
Instructions are furnished in the operating manual for the particular scope probe
used.

r--------,
I Probe Cp I
I I Scope
I I
I A~,-L~~+~-=-=-==-=-=-==-~-=-==-=-~.
I Rp I
L _ _ _ _ _ _ _ _ ....l

Cp is adjusted so
that CpRp=CsRs
where C s = C(in)+ Ccable
Fig. 5.39. Probe compensation circuit.
Measurement of Electrical Quantities and Parameters 85

Cp too large Cptoo small C p correct value

Fig. 5.40. Scope probe compensation.

Grounding of Scope Probe. With fast rise pulses it is important to have


a ground at the scope probe, in addition to any other grounds to the scope chassis.
Figure 5.41 shows the results of a probe used with and without a ground connec-
tion near the signal test point. Short ground and signal leads are necessary
throughout the circuit to prevent this type of ringing.

Scope probe not grounded Scope probe properly grounded

Fig. 5.41. Scope waveforms.


6
Equivalent Circuits and Parameter
Interrelationships

One of the first steps in analyzing and designing transistor circuits is to repre-
sent the transistor by a satisfactory equivalent circuit. Many equivalent circuits
are in use. Each is used to represent a different type of transistor at different
operating conditions. In general, equivalent circuits may be divided into two types:
those which regard the transistor as a black box upon which measurements are
made, and those which regard the transistor as being made up of physically real-
izable active and passive components. The following discussion illustrates several
of the more common equivalent circuits used in transistor circuit design.
The equivalent circuits in this chapter represent the a-c or incremental equivalent
circuits, as opposed to the d-c or static representation. All the small-signal
parameter symbols with which we are dealing will be given in lower case to
distinguish them from static parameter symbols, given in upper case.
The Two-terminal Network. Consider a two-terminal black box. At one
frequency, the behavior of a linear device may be specified in terms of two measure-
ments: one an open-circuit voltage, the other a short-circuit current. Equivalent
circuits, good at the frequency of measurement, may then be drawn for the device
(as shown in Fig. 6.1).
voc-Open-circuit voltage.
i.c-Short-circuit current.

isc
Y=-
Voc

Fig. 6.1. Two-terminal network.

86
Equivalent Circuits and Parameter Interrelationships 87

loop ~ "Black box"

Fig. 6.2. Four-terminal network.

The Four-terminal Network. A set of measurements may be made on a linear


four-terminal device similar to those made on the two-terminal device. The three-
terminal transistor is considered a special case of a four-terminal device, with two
terminals common to both input and output. Consider the black box of Fig. 6.2.
It is possible, by making appropriate measurements of the various voltages and
currents, to arrive at a useful equivalent circuit for any linear device, active or
passive. The voltages and currents are shown to establish the measurement
convention.
Figure 6.3 is shown to illustrate that a three-terminal network is just a special
case of the four-terminal network of Fig. 6.2.
Two statements may be made concerning Figs. 6.2 and 6.3:
1. There are only two independent voltages and two independent currents.
2. If any two quantities are fixed by external means, then the other two are
fixed by the black-box parameters. Note that generally we are not free to
specify any two quantities arbitrarily; the quantities picked must be com-
patible with the black-box parameters. Of the six possible circuit repre-
sentations relating the voltages and currents, three have proved particularly
helpful in describing junction transistors: (a) open-circuit impedance
measurements, (b) short-circuit admittance measurements, and (c) a com-
bination of the two, hybrid parameter measurement.
Open-circuit Impedance Parameters. Two equations may be used to define
the black box as given in Fig. 6.2:
(1)
(2)

+
- "Black box"
-- +

=Vi
[ 1 V2=

- -
Fig. 6.3. Three-terminal network: a special case.
88 Fundamental Considerations

Figure 6.4

From Eqs. (1) and (2), if the output is open-circuited or i2 = 0,


V1
Z11 =~ input impedance (3)
11

V2
Z21 = --;-
It
forward transfer impedance (4)

If the input is open-circuited or it = 0,


V1
Z12 = --;-
12
reverse transfer impedance (5)

V2
Z22 = -;-
12
output impedance (6)

i1and i2 are independent variables.


Z21 may be read as "the voltage in (loop) 2 due to the current in (loop) I." Each
of the other three Z parameters may be treated in the same manner. All the
electrical properties of Fig. 6.4 may be calculated by using the impedance param-
eters. Current gain of the black box shown in Fig. 6.4 is given as an example.

Ai = ~2
11

From Fig. 6.4 see


(7)
If Eq. (7) is substituted into Eq. (2),

i2
it
= (8)

Short-circuit AdmiHance Parameters. The black box of Fig. 6.2 may also be
represented by the following two equations:
it = Y11 V1 + yi2V2 (9)

i2 =Y21V1 + Y22V2 (10)


These are known as the short-circuit admittance equations with V1 and V2 as the
independent quantities.
Equivalent Circuits and Parameter Interrelationships 89

From Eqs. (9) and (10) with the output shorted or V2 = 0,


yu =it- input admittance (11)
VI

i2
Y2I =- forward transfer admittance (12)
VI

If the input is shorted or VI = 0,


reverse transfer admittance (13)

output admittance (14)

Like the z parameters, all the electrical characteristics of a black box are known
if the y parameters are known.
Since z parameters are open-circuit parameters, a network can best be charac-
terized by z parameters whose input and output may easily be open-circuited (e.g.,
low z circuit). A similar statement can be made about the y parameters. Since
y parameters are short-circuit parameters, a network can best be characterized by y
parameters whose input and output may easily be short-circuited.
Hybrid Parameters. A third set of very useful parameters combines part of
the open-circuit measurements and part of the short-circuit measurements to form
a hybrid parameter system.
The hybr~d or h parameters may be defined by the following equations:
VI = huit+ h I2V2 (15)

i2 = h21il + h22V2 (16)


With the output short-circuited or V2 = 0,

input impedance (17)

forward transfer current ratio (18)

If the input is open-circuited or it = 0,


reverse transfer voltage ratio (19)

output admittance (20)

The admittance parameter set finds its chief usefulness at very high frequencies,
where open-circuit measurement may lead to difficulties. It is almost impossible
to avoid stray capacitance between transistor elements, and with open-circuited
terminals these may cause regenerative effects which are often very unstable and
90 Fundamental Considerations

unpredictable. If only short-circuit parameters are measured, then the stray (or
parasitic) capacitances merely act as shunt reactances to ground, and do not enter
into the active transistor measurements.
Of the three sets of parameters listed, the h parameters are the most often used
in general transistor audio work and low-frequency video.
Comparison of z,.y, and h Parameters. Representation by hybrid parameters
is the most useful scheme for two reasons. First, the h parameters are easy to
measure. It must be remembered that h parameters are measured at some bias
point; therefore, the terminals of the device cannot merely be shorted for a short-
circuit measurement or opened for an open-circuit measurement. The short and
open circuits must take place with regard to the biasing network attached to the
transistor. The z and y parameters require either all open-circuit or all short-
circuit measurements. Since the input impedance is rather low and the output
impedance is rather high for a transistor (common base and common emitter), one
type of measurement for both input and output is difficult. The Zll and Z21 meas-
urements require the output to be open-circuited, which is difficult to do, particu-
larly at high frequencies; it is equally difficult to short the input circuit for the Y12
and Y22 measurements. With the hybrid parameters, however, it is necessary only
to short-circuit the output or open-circuit the input; this is easily accomplished at
both low and high frequencies.
The second advantage of h parameters is that the input impedance, output
admittance, and current gain of the device as used in a circuit approximate hll' h22'
and h21' respectively, if certain assumptions are made. As an example: current
gain = h2t!(1 + h22RL)' If RL is small compared to Ijh22' then the current gain
of the device in the circuit equals h21 .
Representation of Equivalent Circuits. In four-terminal network theory, the
small-signal parameters (z, y, and h) are characterized by numerical subscripts; in
transistor circuit work, these parameters are usually designated by letter subscripts.
The first subscript designates whether the parameter is input or output, forward
or reverse; the second subscript indicates the transistor configuration. The follow-
ing shows the relationship between the numerical and literal designations.
11 = i ............................... Input parameter
12 = r . .............................. Reverse parameter
21 = f. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Forward parameter
22 = o . .............................. Output parameter
Common-base configuration ............ b
Common-emitter configuration ......... e
Common-collector configuration.. . .... c

Using letter subscripts, hoe would designate the output h parameter for the com-
mon-emitter configuration.
Representation of Equivalent Circuits. The h-parameter equations having
been written and defined, it is necessary to show how an equivalent circuit is derived
from the equations.
Common-base Equivalent Circuit. The hybrid equivalent circuit for the h
parameters of the common-base configuration (Fig. 6.5a) is shown in Fig. 6.Sb.
Equivalent Circuits and Parameter Interrelationships 91

e c

bo---------+---------~------+-----~b

(a) Common·base configuration (b) Hybrid equivalent circuit

Fig. 6.5. Common-base configuration and hybrid equivalent circuit: (a) common-base con-
figuration; (b) hybrid equivalent cjrcuit.

The reverse voltage transfer ratio, h rb , appears as a voltage generator in the input
circuit; the forward current transfer ratio, hfb' appears as a current generator in
the output circuit. By calling VI and V2, and i l and i2 of Eqs. (15) and (16), Veb and
Veb, and ie and ie, respectively, and adding the base subscript b to the h parameters,
the equations (for input and output) relating the h parameters for the common-
base configuration become
(21)
(22)
Common-emitter Equivalent Circuit and Equations. The hybrid equivat.ent circuit
for the h parameters of the common-emitter configuration (Fig. 6.6a) is shown in
Fig.6.6b.
The reverse voltage transfer ratio, hre , appears as a voltage generator in the input
circuit; the forward current transfer ratio, h{e, appears as a current generator in
the output circuit. By calling VI and V2, and i l and i2 of Eq. (15) and (16), Vbe and
Vee, and ib and ie, respectively, and adding the emitter subscript e to the h param-
eters, the common-emitter equations (for input and output) relating the h parameters
for the common-emitter configuration become'
Vbe = hieib + hrevee (23)
ie = h{eib + hoevee (24)
Common-collector Equivalent Circuit and Equations. The hybrid equivalent

b ~------~------Oc

eo---------~----------~-------4----__oe

(a) Common· emitter configuration (b) Hybrid equivalent circuit

Fig. 6.6. Common-emitter configuration and hybrid equivalent circuit: (a) common-emiHer
configuration; (b) hybrid equivalent circuit.
92 Fundamental Considerations

b r-------~--~-oe

co---------~--------~------~~----oc
(a) Common-collector configuration (b) Hybrid equivalent circuit
Fig. 6.7. Common-collector configuration and hybrid equivalent circuit: (0) common-collector
configuration; (b) hybrid equivalent circuit.

circuit for the h parameters of the common-collector configuration (Fig. 6.7a) is


shown in Fig. 6.7b.
The reverse voltage transfer ratio, hre , appears as a voltage generator in the input
circuit; the forward current transfer ratio, hfe , appears as a current generator in
the output circuit. By substituting Vbe for Vi, Vee for V2 and h for h in Eq. (15) and
by substituting h for h, ie for i2, and Vee for V2 in Eq. (16), and adding the collector
subscript c to the h parameter of Eqs. (15) and (16), the common-collector equa-
tions (for input and output) relating the h parameters for the common-collector
configuration become
Vbe = hieh + h reVee (25)
ie = hfch + hocvec (26)
Electrical properties of the equivalent circuits such as current gain and input
impedance are given at the end of this chapter.
Two equivalent circuits will now be shown for the z and y parameters. The first
circuit is in terms of voltage generators, while the second has been constructed in
terms of current generators. The reader will recall that any two-terminal network
may be represented by either a voltage generator in series with an impedance or a
current generator in parallel with an impedance.
T-equivalent Circuit. The second main type of equivalent circuit (physical
representation) is illustrated by the representation of the T-equivalent circuit. The
common-base configuration is given in Fig. 6.10 to define the basic component values

(a) (b)
Fig. 6.8. z-parameter equivalent circuit.
Equivalent Circuits and Parameter Interrelationships 93

Y21
--VI
Y22

(a) (b)
Fig. 6.9. y-parameter equivalent circuit.

of the equivalent circuit. The common-base parameters are related to the common-
emitter configuration in Fig. 6.11.
a = the fraction of emitter current that becomes collector current. a ranges
typically from 0.90 to 0.999.
rb = ohmic resistance of the base contact and of the base region. This compo-
nent can range from tens of ohms to several hundred ohms.
rc = incremental value of resistance of the collector junction, which is a reverse-
biased diode. Its value ranges typically from one to several megohms.
re = incremental resistance of the forward-biased emitter-base diode. Its resist-
ance is a function of the emitter current and is given approximately by
~KI
re = qIE
where K = Boltzmann's constant
T = temperature, OK
q = electronic charge
Substituting values for K, T, and q (at room temperature KT/q = 26 mv),
~ 26
re = - (27)
IE
where IE is given in milliamperes, and re is given in ohms.
The common-emitter configuration is given in Fig. 6.11.

ie
-
E 0-------''1 v-+-----<>c
ic

Fig. 6.10. T-equivalent circuit, common base.


94 Fundamental Considerations

1-'" a ib

B -ib

rb rc(l- a)
- ic
C

Fig. 6.11. T-equivalent circuit, common emitter.

Parameter Conversion Tables. Figures 6.5 (hybrid equivalent circuit) and


6.10 (T-equivalent circuit) give two basic equivalent circuits. By using these
equivalent circuits and standard network theory, analyses of transistor circuits may
be made. Tables 6.1 to 6.8 give the electrical properties of the equivalent circuits.
Conversion tables between sets of equivalent circuits are also given. Manufacturer's
data sheets on particular transistors usually present the h-parameter values for the
CB configuration or the CE configuration, or a portion of each. These data sheets
seldom provide all the needed values in a form suitable for direct substitution into
the equations of the configuration being analyzed; therefore, it becomes necessary
to convert the h-parameter values given for one configuration to the values suitable
for another configuration.
The relations given in these tables are exact; in cases where an approximate form
is also given, it is designated by -. Refer to Fig. 6.2 for the definition of the basic
voltages and currents listed.
The following information is given in Tables 6.1 through 6.8:
Table 6.1:
a. Common-base h parameters in terms of common-emitter, common-collector,
and T parameters.
b. Common-collector h parameters in terms of common-emitter, common-
base, and T parameters.
Table 6.2:
a. Common-emitter h parameters in terms of common-base, common-collector,
and T parameters.
b. T parameters in terms of common-emitter, common-base, and common-
collector parameters.
Table 6.3:
a. Input impedance, output impedance, current gain, and voltage gain in
terms of h and T parameters.
b. Insertion power gain, transducer power gain, available power gain, and
operating power gain in terms of h parameters.
Table 6.4:
a. z parameters in terms of h parameters.
b. y parameters in terms of h parameters.
Equivalent Circuits and Parameter Interrelationships 95

Table 6.5:
a. Common-emitter z parameters in terms of common-collector and common-
base z parameters and T parameters.
h. Common-emitter y parameters in terms of common-collector and common-
base y parameters and T parameters.
Table 6.6:
a. Common-base z parameters in terms of common-emitter and common-
collector z parameters and T parameters.
h. Common-base y parameters in terms of common-emitter and common-
collector y parameters and T parameters.
Table 6.7:
a. Common-collector z parameters in terms of common-emitter and common-
base z parameters and T parameters.
h. Common-collector y parameters in terms of common-emitter and common-
base y parameters and T parameters.
Table 6.8:
Input impedance, output impedance, voltage gain, and current gain in terms
of z and y parameters.
'0
0- Table 6.1

h Common -emitter. Common-collector T-equivalent drcuit


parameter

hib
(1 + hre)(1
hie
- hre) + hiehoe -
""'~
1 + h,e
re + (1 - ah

hiehoe - hre(1 + hre) ~ hiehoe _ hre h'e(1 - hre) + hichoe ~ hre _ 1 _ hichoe _r_b_~~
hrb
(1 + h'e)(1 - hre) + hiehoe 1 + h,e hiehoe - h,chrc h'e re + rb re

- h'e(1 - hre) - hiehoe h'e hrc(I + hre) - hiehoe = _ 1 + h'e -a


h(b
(1 + h'e)(1 - hr.) + hi.hoe ~ - 1 + h,. hichoe - h'ehrc - h'e

hob
(1 + h'e)(1
hoe
- hre) + h;.hoe
""'~
-I+ho•
hoc
h;ehoe - h'ehre ~
hoc
h,e' --""'-
re + Tb - re

h
Common-emitter Common-base T-equivalent circuit
parameter
hib hib TeTe Te
hie hi. rb+ ~rb+--
(1 + h(b)(1 - hrb) + hobhib ~ 1 + h(b re + Te - aTe 1 - ex

hre 1 - hre 1 + h(b ~1 Te - aTe ~ 1_ re


(1 + h(b) (1 - hrb ) + hobhib Te + Te - arc (1 - a)re

hrb - 1 -1
~_~
hre -(1 + h,e) --.,.-.,...,---:'----,--.,...--:,-- "'" - - - Tc
(1 + h(b)(1 - hrb) + hobhib - 1 + h(b Te + Te - arc 1- a

hoc hoe hOb =~ --~-.-


(1 + h(b)(1 - hrb) + hobhib - 1 + h(b
Table 6.2

h
parameter Common-base Common-collector T-equivalent circuit

hib hib rere re


hie -::----:---:-:-::--::.,-::---:--:--=-- hie rb + ~rb + ---
(1 + hfb)(1 - hrb) + hobhib - 1 + hfb re + re - arc 1- IX

hre hibhob - hrb(1 + hfb) ~ hibhob _ hrb re re


1 - hrc
(1 + hfb)( 1 - hrb) + hObhib 1 + hfb re + rc - arc (I - IX)rc

-hfb(1 - hrb) - hobhib = -hfb arc - re ~ __IX_


h'e
+ hfb)(1 - hrb) + hobhib - 1 + hfb -(1 + h'e)
(1 re + rc - arc 1- IX

hoe
hob =~
hoc --~--
(I + hfb)(1 - hrb) + hobhib - 1 + hfb re + re - arc (I - a)re
T
Common -emitter Common-base Common -collector
parameter

h'e(1 - hre) + hiehoe =~ hiCho~ - hre{1 + h'e) - 1+


_ - h,e
IX -hfb --
(1 + h'e) (1- hre) + hiehoe - 1 + h'e hiehoc - h'chrc h'e
h'e + 1 1 - hrb h'e
rc
hoe hob hoc
hre 1 - hrc
re hib - (I + hfb) hrb
hoe hob hoc

rb hie _ hre(l + h'e) hrb hie + h'c(l - h rc )


hoe hob hoc
'Cl
...... a h'e + h re _ hfb + hrb h,e 2- hrc
1 + h'e 1 - hrb h,c
Table 6.3

Input impedance Output impedance

h parameter Zi = ~ = hi _ hrhrZL Zo=~=


I
1+ h,ZL
h"-~
ii I,

hi + Zg
Common-base
T-equivalent
circuit
re + fb C' -+
rc
ar,
rb
+ RL)
+ RL
~ re + 'bel - 0' ) fc + fb ( I -
fe
arc+ r,
+ fb + Rg
) ;;;;: rc

Common-emitter
T-equivalent r, +
r,(r, + RL) r,
r,+-- rc - arc + fe ( 1 + , ar, - r , ) ~--
r,
rc - arc + re + RL I-a re + fb + Rg 1- a
circuit

Common-collector
T-equivalent r, +
r,(r, + RL) :;::;;:;rb+---
Ye + RL r, + (ro + Rg) rc - arc
circuit Ye - arc + re + RL I-a rc + rb + Rg

Insertion power gain Transducer power gain


( power into load ) ( power into load )
power generator would deliver directly maximum available generator power

h parameter
where Zg and Gi = h?(R, + RL)2 Gt = 4h?R gRL
ZL are pure [(hi + Rg)(l + hgRL) - hfh,RJJ2 [(hi + Rg)(l + h,RL) - hth,RLJ2
resistance

Current gain Voltage gain

A _~ _ _ _ I
h parameter hf__ Av=~=
ii - 1 + hoZL
l - Vi
h, - -"'ZL-C +hihgZ L)

Common-base
arc + rb (ar, + r,)RL aRL
T-equivalent IX

circuit fc + fb + RL r,(r, + r, + RL) + r,(r, - ar, + RL) T, + r,(l - a)

Common-emitter
-(arc - r,) a -Car, - r,)RL aRL
T-equivalent --
circuit
fc - arc + re + RL I - a r,(r, + R L) + rb(r, - ar, + r, + RL) - r, + rb(l - a)

Common-collector I
r, I rcRL
T-equivalent =-- ::::=::--- - - - - ----
circuit
fc - arc + Te + R,L I-a r,(r, + RL) + rb(r, - ar, + r, + RL) 1 +re+rb--
I - a
RL

,
Available power gain Operating power gain
( maximum available output power ) ( power into load )
maximum available generator power power into transistor

h parameter
where Zg and Ga = h?Rg 01 ::::; AvAi = Vo~o = (_hl_)h' _ -",-(I + haRlc)
ZL are pure (hi + Rg)[ha(hi + Rg) - hlh,l Viti I + haRe RL hi
resistance

98
Table 6.4

Common-emitter Common-base Common-collector

Zl1b !:J.h !:J.h 1


- - -
hoe hob. hoe

Z12b
!J.h - hre
---
hrb
-
1 + h'e
hoe hob hoe

!:J.h + h'e -hlb 1 - hre


Z21b ---
hoe hob hoe

d 1 -
d
Z22b - -
hoe hob hoe

d 1 -
d
Y11b - -
hie hib hie

Y12b
hre - !J.h
--- --
hrb 1 -h'e
-- - +
hie hib hie

Y21b ----
!:J.h + h'e hlb hre - 1
---
hie hib hie

!J.h !:J.h 1
Y22b - - -
hie hib hie

!J.h = hiho - h,h,


d = (l + h,)(l - hr) + hiho ~ 1 + h,

Table 6.S

z parameter Common-collector Common-base T-equivalent circuit

ZUe Zl1 - Z12 - Z21 + Z22 Z11 re + rb


Z12e Z22 - Z12 Zl1 - Z12 r.

Z21e Z22 - Z21 Zu - Z21 re - arc

Z22e Z22 Z11 - Z12 - Z21 + Z22 r. + re(l - a)


y parameter Common-collector Common-base T-equivalent circuit

re + rc(l - a)
Y11e Y11 Y11 + Y12 + Y21 + Y22 !J.
re
Y12e -(Y11 + yu) -(Y12 + Y22) --
!J.
,.
re - arc
Y2i. -(Y11 + Y21) -(Y21 + Y22) ----
!J.
re + rb
Y22. Y11 + Y12 + Y21 + Y22 Y22 ---
!J.

99
Table 6.6

Z parameter Common-emitter Common-collector T-equivalent circuit

Zllb Zll Zll - Z12 - Z21 + Z22 re + rb


Z12b Zll - Z12 Zl1 - Z21 rb

Z21b Zll - Z21 Zll - Z12 rb + arc


Z22b Zll - ZI2 - Z2I + Z22 Zll rb + rc

Y parameter Common -emitter Common-collector T-equivalent circuit

rb + rc
Yllb Yll + YI2 + Y2I + Y22 Y22 - --
!J.

rb
YI2b -(YI2 + Y22) -(Y2I + Y22) --
!J.

Y2Ib -(y2I + Y22) -(YI2 + Y22) -+


- rb -arc
-
!J.

re + rb
Y22b Y22 Yll + YI2 + Y2I + Y22 - --
!J.

Table 6.7

Z parameter Common-emitter Common-base T-equivalent circuit

Zllc Zll - ZI2 - Z2I + Z22 Z22 rb + rc


Z12c Z22 - ZI2 Z22 - Z21 rc(l - a)

Z2Ic Z22 - Z2I Z22 - ZI2 rc

Z22c Z22 Zll - ZI2 - Z2I + Z22 re + rc(1 - a)

y parameter Common-emitter Common-base T-equivalent circuit

Yllc Yll Yll + YI2 + Y21 + Y22 re + rc(1 - a)


!J.
-rc(l - a)
YI2c -(Yll + Y12) -(Yll + Y22)
!J.
rc
Y2Ic -(yll + Y22) -(Yll + Y12) --
!J.

rb + rc
Y22c Yll + YI2 + Y2I + Y22 Yll - --
!J.

100
Table 6.8

Parameter Input impedance Output impedance Voltage gain Current gain

Z
;:"z + ZUZL ;:"z + Z22Zg Z21Z L -Z21

Z22 + ZL Zu + Zg f>z + ZUZL Z22 + Z[,


yzz + Y L yu + Yo Y21 Y21 YL
y -
;:"y + yuh ;:"y + Y2Z Y • YZ2 +h ;:"y + YUYL

;:,.Z = ZUZ22 - Z12Z21

;:"y = YUY22 - Y12Y21

101
Part 2

D-C and Low-frequency Designs


7
Transistor Biasing

7.1. ESTABLISHING THE QUIESCENT OPERATING POINT

The Meaning of Bias. In a vacuum-tube amplifier, bias refers to the d-c voltage
applied to the grid of the tube to establish its operating point on the dynamic charac-
teristic curve. In a transistor amplifier, bias can be considered to be the direct
current applied to the input terminal of the transistor (base or emitter) to establish
an operating point on the load line of the output characteristic curve.
In these discussions we refer to the output (collector) current and the output
voltage (VCE or VCB ) as the bias point. When setting the bias, we are interested in
maintaining control of the collector current rather than the base or emitter current;
hence our interest is in the stability of the bias point and not the actual bias current.
For vacuum-tube amplifiers it is relatively simple to draw a load line on a set of
common-cathode characteristic curves (IB vs. VB), select an operating point, and
establish it by either a fixed grid bias supply voltage or a resistor in series with the
cathode. A similar approach is possible with transistors: One can draw a load
line on a set of common -emitter characteristic curves (ICvs. V CE), select a desirable
value of quiescent collector current, and calculate the proper value of base resistance

+
~vcc

(a)
Figure 7.1

105
106 D-C and Low-Frequency Designs

Bo---JV
hIE
~~~--~~----oC
-Ie

E E
Figure 7.2

to establish the required base current. This approach leads logically to a circuit
like that in Fig. 7.1. The base resistance, R 1 , is chosen by assuming that the base-
to-emitter voltage (VBE) of the transistor is zero: i.e., Rl = Vee! lB. Designs of
this type have both simplicity and a charming element of unpredictability. If Rl
(and hence, I B ) is fixed, there is nothing to prevent Ie from varying in accordance
with the current gain, hFE' of the transistor. This type of biasing is very roughly
analogous to fixed-bias vacuum-tube amplifiers; but while there are many advan-
tageous applications for fixed-bias vacuum-tube amplifiers, a similarly biased
transistor stage should not be used in any application. Generally, a graphical
approach to bias network design is oflittle use in transistor circuitry for the follow-
ing reasons: (1) There is a wide variation in common-emitter characteristics between
devices; (2) the characteristics of each device vary widely with temperature; and
(3) the common-base characteristics do not quite describe the transistor in a
practical circuit. It is more useful to do an analytical bias design, using equivalent
circuits for both the transistor and the external circuit.
Transistor Equivalent Circuit. The equivalent circuit used in this discussion
(Fig. 7.2) is an approximation of the general hybrid two-port representation of the
transistor. The parameters shown in this circuit are the common-emitter d-c h
parameters.
The approximation to this circuit is shown in Fig. 7.3. The quantity hOE can be
neglected because it will generally be quite small compared to any external con-
ductance connected between the collector and emitter terminals. Generally, hRE
is negligible at low frequencies, and hIE is replaced by the voltage drop VBE across
a diode to represent the base-emitter input characteristic.
External Circuit. Any network connected external to the three terminals of the
transistor can be reduced to a T equivalent as in Fig. 7.4. As an illustration of
this, take the general bias circuit of Fig. 7.S and reduce it to the T network of Fig.
7.4. If these two circuits are to be equivalent, then we can apply Thevenin's

B O---~P----:-t--t ~---oC

VEE
--.l
E Figure 7.3
Transistor Biasing 107

theorem to each pair of terminals. Considering only the external circuit, the
resistance between the base and emitter terminals with all external voltage sources
reduced to zero is

(1)

Between base and collector terminals,

(2)

and between emitter and collector,

RE + Rc = R2 + R3 + (R4 + R5)(R6 + R 7 ) (3)


R4 + R5 + R6 + R7
Solving Eqs. (1), (2), and (3) simultaneously,

RE = R2 + R7(R4 + R 5) (4)
+ R5 + R6 + R7
R4
R6(R4 + R 5)
R c = R 3 + --....:....:...--=----'"'-- (5)
R4 + R5 + R6 + R7

and RB = Rl + RsR7 (6)


R4 + R5 + R6 + R7
Examining each pair of terminals for open-circuit voltages, we find that
T7'
"BB = "cc R4 + R5 R7
T7

+ R6 + R7
(7)

and V; '
CC = V;CC R4 + R6 + R7 (8)
R5 + R6 + R7
The circuit of Fig. 7.5 is perfectly general in that the equivalent of any single-stage
bias network can be obtained from Eqs. (4) through (8) by setting the appropriate
resistors equal to zero or infinity.

co----~~----------~
Re +1
-=-Vce

RB VBB +
BO-----'~.----+--1III~_--+ -=- Vee

Eo---"'\

Figure 7.4 Figure 7.S


108 D-C and Low-Frequency Designs

C
- ICQ Rc

h;EIB _- V~c

IB
B ....-

- VBEl E IE RE
~

Figure 7.6

SeHing the Bias. By combining the internal and external equivalent circuits as
in Fig. 7.6, an expression for the bias-point collector current, I oQ, can be obtained.
From Fig. 7.6,
ICQ = hFEIB + (1 + M'E)IoBo (9)

IB = VBB - VBE - IoBoSI + hpE)RE (10)


RB + (1 + hFE)RE
Combining Eqs. (9) and (10),

I OQ - M'E(Vjm - VBE) + (1 + hFE)IoBo(RB + RE) (11)


- RB + (1 + hFE)RE
Equation (11) by itself does not yield the necessary information to bias a transistor
in any given application; there are too many variables which must be arbitrarily
chosen. However, the apparently arbitrary choice of IOQ and RB or RE is often
restricted by the particular application. For example, if a low-noise amplifier is
desired, a value of IOQ would be chosen such that IOQ/hFB is at or near the optimum
value of emitter current recommended by the data sheet for minimum noise figure.
R B would also be chosen such that it is large compared to the recommended
optimum signal source resistance, so that it does not appreciably affect the source
resistance. The problem is then to solve Eq. (11) for the necessary value of emitter
resistance. But this is no small problem, since we would also like a value of
emitter resistance that would keep IOQ within certain reasonable limits.
The parameters hpE, VBE, and lOBO are all extremely temperature-dependent, and
we must investigate Eq. (11) to see what happens to IOQ at the highest and lowest
operating-junction temperatures. Inspection of Eq. (11) shows that minimum IOQ
will occur when VBE, R B, and RE are at a maximum and I CBO, hpE, and VIm are at
a minimum. If minimum lOBO = 0, then hFE = hFE. Using overlines to indicate
maximum (most positive) values and underlines to indicate minimum (most nega-
tive) values,
I > hFE(YBB - VBE) (12)
_OQ = RB + RE(1 + hFE)
This condition generally occurs at the lowest junction temperature.
Transistor Biasing 109

Similar reasoning shows that maximum IOQ occurs with minimum VBE and RE
and with maximum lOBo, ME, V~B' and RB. Assuming ME approaches infinity as
a maximum,
I < Vim - YBE + lOBo(RB + BE) (13)
OQ= BE
This condition generally occurs at the highest junction temperature. Notice that
the sign convention of these equations is correct for NPN transistors. The varia-
tions in R B, R E, and VBB are due to resistance and power-supply tolerances and
are of concern where such circuits are to be mass-produced.
If IOQ is to be held within the bounds of a given lOQ and lOQ, Eqs. (12) and (13)
may be combined to specify an R E .
RE > bFE[ VBE(l + C) - YBE(l - D) + lOB;RB(l - D)] + loQRB(l + C)
- llFE(1oQ - IOBo)(1 - B)(l - D) -loQ(l + llFE)(1 + A)(l + C) (14)
where RE = R E (1 + A) (15)
BE = RE (1 - B) (16)
VBB = VBB(l + C) (17)
and !:im = VSB(l - D) (18)
A and C are the tolerance limits on RE and Vim at the highest ambient temperature,
and Band D are the limits at the lowest temperature. It is interesting to note that
for Eq. (14) to have any meaning, the denominator must be positive and greater
than zero. This imposes the condition
- (1 + A)(1 + C) ~ 1\ -
IOQ> (1 _ B)(1 _ D) ~ + bF~}loQ + lOBO (19)

Equation (19) gives the minimum variation within which IOQ can be held under
specified temperature extremes and resistance tolerances. This provides a quick
check on whether a given set of limits on I CQ is possible, but says nothing about
the practicality of such limits.

7.2. HEAT DISSIPATION

Two thermal requirements must be met for satisfactory transistor operation:


1. The greatest instantaneous heat released at the junction must flow through
the thermal impedance to the highest ambient temperature ever encountered
without raising the junction above its maximum rated temperature. In
other words, for Fig. 7.7,
Tjunction(max) = Tambient(max) + D.TJ_A(max)
2. The circuit must be stabilized against thermal runaway.
The instantaneous power released at the junction depends upon the instantaneous
110 D-C and Low-Frequency Designs

C HJ

Figure 7.7

values of ia, VaE, iE, and VEE. For the general case, it consists of a steady-state
component P J and a time-varying component pJ(r). The lowest frequency present
in the electrical signal will usually be the fundamental frequency of the Fourier
expansion of pJ( r).
(20)
In many designs the transistor carries only d-c and/or audio-frequency signals, and
the power-transient peaks do not exceed about one-tenth second. From Sec. 4.4,
since a conservative design results from taking CHJ = 0, a good rule of thumb for
transistors operating within these limits is
(21)
This expression would apply to the power stages of most audio amplifiers. It is
also useful for estimating the peak tJ encountered in voltage-regulator designs.
For the latter purpose, PJ(marc) is taken to be the maximum steady-state Vasla
product to be met in normal operation, while pJlpeak) is the peak instantaneous
VaEia product that might be imposed by a transient condition. For the estimate
to be conservative, the transistor case temperature must not change appreciably
during the transient.

7.3. THERMAL STABILITY

Thermal Runaway. The second requirement for satisfactory operation con-


cerns thermal stability. A rise in junction temperature alters the transistor param-
eters in a direction that increases collector current. This increased current, in turn,
may cause increased dissipation and higher junction temperature. If a transistor
is to avoid thermal runaway, the rate at which heat released at the junction increases
with a rise in junction temperature must not exceed the rate at which the amount
of power which can be dissipated changes as the temperature changes. We may
derive this criterion in the following way:
Thermal runaway consists of a repetition of three physical processes:
1. A change in ia results in a change in pJ(released).
2. A change in pJ(releasecf) results in a change in tJ.
3. A change in tJ results in a change in ia.
Each process may be considered as a black box defined by an input, an output, and a
transfer function. This is diagrammed in Fig. 7.8.
Transistor Biasing 111

I ~:~ I ~~~_______A_P~'I _________

Figure 7.8

Ifthe loop gain around this network is unity or greater at any frequency, that is, if

IliCl !ltJ2 !lpJ3 > 1 (22)


1ltJ1 !lpJ2 !lic3 =
then thermal runaway is possible.
It will be convenient to evaluate each term of Eq. (22) as a derivative, and write
the stability criterion as
dicl dtJ2 dpJ3 <1 (23)
dtJ1 dpJ2 diC3
Equations (22) and (23) assume that the transistor is not subject to thermal
feedback from another heat source dependent upon the transistor currents:
e.g., two transistors in Darlington connection mounted upon the same heat
sink. For these cases, Fig. 7.7 is no longer sufficient. The expression for
(!ltJ2/ !lPJ2)(!lPJ3/i!lc3) becomes quite complicated and will not be presented here.
Approximations which circumvent this problem can usually be made for individual
cases.
At any instant in its operation, the transistor must be in one of three conditions:
1. The transistor is ON and is not in saturation: i.e., the emitter diode is
forward-biased, the collector diode is reverse-biased, and transistor action
is taking place.
2. The transistor is ON and is in saturation: i.e., the emitter and collector diodes
are both forward-biased.
3. The transistor is OFF: i.e., the collector diode is reverse-biased, the emitter
diode is reverse-biased or unbiased, and no appreciable transistor action is
occurring.
Thermal stability is of importance only in the first and, occasionally, the last cases.
Before discussing the application of Eq. (22), it will be helpful to examine in detail
the form of its constituent derivatives.
Description of dtJ2/ dpJ2. Since tJ is a function of both pJ and the definite inte-
gral of pJ with respect to time, dtJ2/ dpJ2 will also contain time-dependent terms.
In other words, at any instant of time, T = X,
dtJ2 / dtJ2/ dT (24)
dpJ2 r=:C = dpJ2/ dT
112 D-C and Low-Frequency Designs

If the thermal impedance can be considered to be purely resistive, these time-


dependent terms vanish and

dtJ2 = ()T (25)


dpJ2
(dPJ3/dic3)(diCl/dtJl) for an OFF Transistor. For a transistor in the OFF
condition,
dpJ3 diCl dfcBX dfEBX
----
dic3 dtJl
= VCB--+ VEB--
dtJ dtJ
(26)

This assumes that the fR drops caused by f CBX and by fEBX are too small to affect
the values of VCB and VEB.
dicd dtJl 'for an ON Transistor. As far as the transistor is concerned, all
circuitry external to it may almost always be reduced to one of the three-terminal
networks shown in Figs. 7.9 and 7.10. These circuits are simply extensions of the
network of Fig. 7.4.
ZBB, Zce, and K are used principally to describe active external circuit elements
linking ic to iB: e.g., amplifier feedback loops. If the stage is isolated or if only
passive elements are present, these terms may vanish.
These network parameters strongly influence the thermal stability of the stage.
If the transistor is directly affected by active elements in the external circuitry-as
for example, a stage in a direct-coupled amplifier with an overall feedback loop-
then the parameters of Figs. 7.9 and 7.10 may become both complex and negative.
Such a feedback loop may keep the stage thermally stable until an overload else-
where in the amplifier opens the loop. Then the sudden shift of values may cause
quick runaway.
The choice between Figs. 7.9 and 7.10 depends upon the base supply impedance.
For a low impedance, Fig. 7.9 is usually preferred; for a high impedance, Fig. 7.10
may be more convenient. When the network representation of Fig. 7.9 is feasible,
diCl/dtJl may be evaluated in a convenient and useful form for an ON transistor
by separating the circuit elements as shown in Fig. 7.11.

ie Z zeeiB Vee ie Z zceiB· vee


c~ll_ c~ll_

.
~B Z zBBie V'BB iB
B~II_ Bo--.------~~~

iE ZE iE
E 0--"'''--------1'" Eo----'----"'\

Figure 7.9 Figure 7.10


Transistor Biasing 113

Figure 7.11

In Fig. 7.11, the entire circuit external to the transistor is represented on the right
of the dashed line as an equivalent-T network: three impedances, ZE, Zo, and ZB,
and four supply voltages, V~o, V~B' ZooiB' and ZBBio. On the left is an equivalent
circuit for the transistor itself, in which the principal temperature-sensitive param-
eters have been isolated. The basic equations are:
= hFBiE + lOBo
io (27)
iB + iE + io = 0 (28)
VD = iE(ZE + rE) + rE) + VEB + ZBBiO
- iB(ZB (29)

. hFB(VD - VEB) + 10Bo(ZB + rE + ZE + rE) (30)


10 = (1 + hFB)(ZB + rB) + ZE + rE + hFBZBB

(31)

where S, the current stability factor, is defined by


S= ~_ ZB + rB + ZE + rE . (32)
- MOBO - (1 + hFB)(ZB + rE) + ZE + rE + hFBZBB
The network in Fig. 7.10 may also be used to derive diod dtJl. The circuit is
shown in Fig. 7.12, and the basic equations are:
io = hFBiE + lOBo (33)

io + iB + iE = 0 (34)

IBB + Kio = iB + iZB (35)


VD = iE(rE + ZE) + ZBi ZB - iBrB (36)
114 D-C and Low-Frequency Designs

-iZB

Figure 7.12

. hFB(VD - ZslBB) + ICBO(ZB + rB + ZE + rE) (37)


and
IC = (1 + hFB)(ZB + rB) + ZBKMB + ZE + rfg
Then,
diCl= S (dI
- - -CBO
+IE. dhFB9
--
dtJ1 dtJ dtJ

+ [(1 + hpB)(ZB + rB) ~


+ ZBKM'B + ZE + ri;J
(38)

where s= dic _ ZB + rB + ZE + rJ; (39)


- dIcBO - (1 + hFB)(ZB + rB) + ZBKhpB + ZE + ri;
If the base is driven from a constant-current source (i.e., if ZB = 00),
1
(40)
S = 1 + hFB(l + K)
and dim = s(dICBO + iE dhFB) (41)
dtJ1 dtJ dtJ
Simplifying Assumptions. At the expense of a conservative design, several
simplifying assumptions may be made:
1. At high junction temperatures,
(42)
A conservative design results when this substitution is made in the numer-
ator of the fraction in the first pair of brackets in Eqs. (31) and (38). It may
also be possible to assume
hpBZBB - -ZBB (43)
and MBZBK- -ZsK (44)
without serious loss of accuracy.
Transistor Biasing 11 5

2. lOBo consists of at least two components: an ohmic leakage between collector


and base, and the diode saturation current. For a reasonably clean junction,
the saturation current usually dominates at high temperatures, and over a
small !:::..tJ can be approximated by
lOBO ~ Nf.(Bt} (45)

dloBo ~ Bl (46)
~= OBO

B = ln2 (47)
!:::..To
where !:::..To is the number of centigrade degrees rise in junction required
for lOBo to double. !:::..To is a complex function of temperature, but for silicon
transistors operating near their upper temperature limits, !:::..To ~ 10 Co. If
lOBo doubles every 10 CO rise, then

oBo _ 006931
dldtJ (48)
-. OBO

For germanium transistors, To ~ 14 Co, and

dloBo ~ 0.04591oBo (49)


dtJ
These approximations must be used with some caution, since surface states
at the junction can produce erratic lOBO at elevated temperatures. Also,
lOBO may be strongly dependent on VOB at voltages near avalanche break-
down.
3. Since the first pairs of brackets in Eqs (31) and (38) enclose negative
quantities, Idi m /dtJ11 maximizes for an NPN transistor when the sum in
the second pair of brackets reaches its most negative value. Theoretical
considerations of the transistor suggest that

ddVD ~ - 0.0025 volt/CO (50)


tJ
For a PNP device, the sign of this quantity is positive. The two other
quantities in the second brackets are often either of opposing sign or so
small that they can safely be ignored.
4. The conservative minimum limit of rJ: is, of course, zero. (The evaluation
of r~ and of dhpB/ dtJ will be discussed at the end of this chapter.)
Thus, for NPN silicon transistors, Eq. (38) may be reduced to

~: = S ~.069310BO + iE ddt;j +
0.0025
(1 + hpB)(ZB + rs) + ZE + hpBZBB (51)
Equation (37) becomes
diol ~ . dh pB) 0.0025 (52)
-tJ1
d =S 0.06931oBo + IE
dtJ- + (1 + h*FB)(ZB + rB') + Z E + KZsh*FB
116 D-C and Low-Frequency Designs

Notice that Eq. (38) differs from Eq. (31) only in that the quantity KZ has been
substituted for ZBB. To avoid duplication, the derivations which follow will be
based only on Eq. (31). The corresponding results from Eq. (38) may be obtained
by replacing ZBB with KZB. Also, the equations will show only the constants for
NPN silicon transistors.
dPJ3/ die3 for an ON Transistor. The power dissipated in an ON transistor can
be found from Fig. 7.9 or 7.10:

PJ = ie(Vce + iBZee - ieZe + iEZE) + VBEiB (53)

dPJ3 = TT'
-d.
le3
vee + Z ee ~Ie-d.
Ie
.~
diB + lB - 2Z·
ele + Z E ~IE + Ie-d·
. diE) + lB-d.
Ie
. dVBE + VBE-.
Ie
diB
die
(54)
Substituting,
dpJ3 _ v:'ee + VBE-d.
diB
die3 Ie

.l
- Ie 2Ze - Zee (-1
hpE
+ -.
diB) -
die
ZE (55)

At the high junction temperatures which aggravate runaway, current gains are
usually large, and

(56)

If no inductance is present in Ze or ZE, then for the NPN case


dpJ3 < V,' (57)
die3 = ee

This is a very useful worst case approximation.


Complex Impedances. Complex electrical and thermal impedances can
strongly affect thermal stability. Figure 7.13 gives two such examples. Both
circuits may be quite stable if the electrical reactances are ignored. But it is
intuitively obvious that if L is made large enough in the first circuit, the rate at
which iB can change with time will become so slow that the transistor could run

+ +

(a) (b)
Figure 7.13
Transistor Biasing 117

away in the meanwhile. Similarly, as C becomes infinite in the second circuit, ZE


approaches zero and S may become large enough for instability. The fact that
runaway does not occur instantaneously for small values of L or C is due, in part,
to the complex nature of the thermal impedance: as the rate of change of PJ with
time increases, D.tJ2/ D.pJ2 usually decreases.
It has been customary for both the literature and the design engineer to ignore
these reactive effects. The temptation is strong: an exact analysis is virtually
impossible. The success of this philosophy may have resulted from three things:
(1) A design which is conservative on the basis of a resistive analysis alone is usually
safe from reactive troubles; (2) a fast thermal runaway may not be recognized for
what it is; and (3) reactive thermal runaways are sometimes oscillatory, and the
blame gets placed on an unknown electrical feedback path. As transistor circuit
design becomes more sophisticated, these problems may become more serious.
Quiescent Stability. The first requirement for any circuit is that thermal run-
away will not occur at an infinitely slow rate. Equation (22) must be satisfied for
the zero-frequency, or quiescent, condition. This is a simple mode to evaluate,
since all capacitive and inductive reactances are effectively open and short circuits,
respectively. The thermal circuit has the simplicity of Fig. 7.7, and if the network
of Fig. 7.9 were used with a silicon transistor, Eq. (22) would become approximately

l> Vec - 2IcQ(Rc + RE)


OT (1 + hFB)(RB + rfJ) + RE - ZBB

[(RB + rB + RE)~.0693IcBO + IEQ d~;;) + 0.0025J (58)

where ICQ and IEQ are quiescent currents.


If this expression is solved for RE , a rather unmanageable quadratic results. But
if ZE is neglected in Eq. (56), then

OT (Vec - 2IcQRc) ~RB + rB) 0.0693IcBo + IEQ d~~B + 0.0025J


+ ZBB - (1 + hFB)(RB + rB)
RE > --------------;--------,--::-.------
, t
1 - OT (Vcc - 2IcQRc) ~.0693IcBo + IEQ dhl'B)
dtJ (59)

Of course, these inequalities-and the ones which follow-must be evaluated for


the peak junction temperature that might be reached during any signal conditions
in order to assure stability while the transistor cools down afterward.
Now let us expand the application of Eq. (58).
Dynamic Stability. Since a stage restricted to quiescent operation has rather
limited application, some study must be made of the effects of a signal. At very
low signal frequencies, the problem approaches the quiescent stability case. Now,
however, I CQ is actually the slowly varying instantaneous value of the collector
current. But if ic is changing, at what magnitude will it impose the most stringent
stability requirement?
11 8 D-C and Low-Frequency Designs

Equation (58) can be put in the form

iT > (Vee - 2ieRT)(M + NiE) (60)

where (61)
0.0025
M = 0.0693SleBo + (1 + h*FB)(RB + rB') + h*FBZBB + R E (62)

and N = SdhpB (63)


dtJ
If -iE = ie, the right-hand side ofEq. (60) maximizes with respect to ie when
. ( t ) _ Vee M _ Veo 0.069310BO + 0.0025/(RB + rB + R E)
10 wors case - 4RT + 2N - 4RT + dhFBI dtJ (64)

providing that N =I=- f(i o), M =I=- f(ie) and RT =I=- f(i e). The first two conditions do not
often exist; nevertheless, they offer a useful first approximation. If 00 > ie > 0,
Eq. (64) may be substituted into Eq. (60) to give
J.- > (Vco N - 2MRT)2 (65)
(}T -8NR T
In an actual circuit, of course, io may never reach this worst-case value. If Eq. (64)
gives io < 0, the actual worst instability will occur when io = O. This is often the
case for class B stages. Note that the inequality signs restricting ie must be reversed
for PNP transistors.
Equation (65) will often serve for the analysis of the power stage of a voltage
regulator. The equivalent circuit of the regulator, however, is more likely to be
that of Fig. 7.10.
At high frequencies, the fluctuations ofPJ become so rapid that they are com-
pletely averaged out by even the shortest junction time constant. For the a-c
component of pJ, the thermal impedance is effectively zero and the concept of an
instantaneous stability varying with the instantaneous operating point becomes
useless. Instead, the problem may be analyzed as a special case of quiescent
stability, where 10Q is then the average value of the collector current.
It can be shown that for a distortionless class A stage carrying a sine- or square-
wave signal, the average value of (Vee - 2ioRT)(M - ioN) over one full cycle
increases as the signal level falls. This is to be expected, since PJ decreases with
increasing signal level while the average collector current remains constant. Thus,
for a particular leQ, the no-signal state imposes a more stringent stability require-
ment than do high-frequency signals.
For class B operation, however, the average collector current increases with
signal level. Also, because of the nature of the push-pull action, the reflected load
impedance must be included in Re for a dynamic analysis. For a resistive load,
the collector current waveform which will produce maximum instability for the
maximum time is a square wave of amplitude Iwe, where
Transistor Biasing 119

I _ vae M
(66)
we - 4(RE + Re) + 2N
This equation is subjected to the same restrictions as Eq. (64). And again, for the
half-cycle that the transistor is ON, Eq. (65) describes the worst stability conditions.
However, at these frequencies, the observed stability will be some average of the
instantaneous stability throughout the signal cycle. A conservative approximation
might be

;T>; [(Vae - 2IweRT)(M - IweN ) + (2Vae)(O.0693IeBx)


+ O.0693IEBXVEB(OffrnaX)] (67)
or, making the required substitution,
1 (VaeN - 2RTM)2 I
()T> -16NRT + O.0693VeeleBx + O.0347VEB(offrnax/EBX (68)

Rapid Runaway. Thus far we have explored the behavior of Eq. (22) at very
slow rates of thermal ·runaway. But a complete analysis would seem to require
that we examine Eq. (22) for every possible combination of values of ie, diel dT, and
r::ie dT. This would be a formidable task, practicable only with an electronic
computer. Sometimes such herculean effort can be avoided. Inspection often
reveals that the problem may be reduced to a small number of worst-case situations
treating only resistive components. If each of these is stable at peak junction
temperature, the circuit should be unconditionally stable. Selection and validity
of these worst-case situations will depend upon the electrical and thermal time
constants of the circuit. The magnitude of these will suggest the values of dpJI dT
and dieldT which should be explored. For particular values, equivalent resistive
networks may be substituted for each complex impedance; the analysis proceeds
along the line of Eq. (65).
To illustrate this approach, consider the transformer-coupled audio amplifier of
Fig. 7.14. The magnitudes of the transformer inductances and the bypass capacitor

- - - - - - - - - - - - - - + vee

Figure 7.14
120 D-C and Low-Frequency Designs

Figure 7.15

are assumed to be satisfactory down to perhaps 20 cps. For our purposes this circuit
may be rearranged as in Fig. 7.15. Here,
LSI = inductance of the driver transformer secondary
rSI = d-c resistance of the driver transformer secondary
LP2 = inductance of the output transformer primary
rP2 = d-c resistance of the output transformer primary
RB = RIR 2 /(R I + R 2)
To predict very slow rates of thermal runaway, Eq. (58) will be satisfactory if
() = ()T
Re =rP2
RB = rSI + R!J
RE=R3
and V~e = Vee
It is intuitively obvious that if runaway is sufficiently rapid, because of the quick
change of currents LSI and L p2 will present high impedances compared to r~ and
Ri, while C will present a low impedance compared to (R3 + RB). To predict
instabilities of this type, Eqs. (64) and (65) might be used. Now, however,
() < ()J.e

R R' RBR3
e = rP2 + L + R' R
B + 3

1 ) RBR3 ]
and Vee
I
= Vee + IeQ [,
RL - R3 1 + hFE
(
+ RB + R3

Runaway at faster rates is still less likely, because while RB has already reached
a maximum, the effective value of () will continue to decrease as die/ d-r increases.
Slower rates, however, may be possible. The shift of RE from R3 to zero will de-
crease stability, and the change of RB from (rSI + RB) to (rSI + rn will do so if
r,j> R B. Stability should be checked for the rates of die/dr at which these imped-
ance shifts occur. One way this may be done is to note the frequencies, /0, at
which X LS1 = rJ and Xc = R3 + RH. A suitable value for () is found for each fre-
Transistor Biasing 121

quency, using a thermal circuit similar to Fig. 7.7 and letting pJ = Po sin 2'17!aT.
Conservative resistive equivalents of each electrical impedance may be selected in
a similar way. Stability can then be evaluated for each of these sets of quantities.
This crude approximation will serve to indicate whether or not a detailed analy-
sis is needed. It is often easier, however, to stop at this point, build the circuit,
and test it.
Evaluation of dhFB/dtJ. For many transistors, the approximation 1 + hFB ~
1/(1 + hFE) is valid. This allows a simple estimate of dhFB/ dtJ:
dh';'B MFB hFB2 - hFBl 1/(1 + hFE2 ) - 1/(1 + hFE1) (69)
dtJ ~ !::..tJ - IJ2 - IJ1 ~ IJ2 - IJ1

In general, the lower the average value of hFE over a given !:l1J, the greater the
absolute magnitude of dhFB/dIJ. Thus, Eq. (69) should be evaluated from low hFE
transistors over a narrow temperature range just below the expected maximum junc-
tion temperature. Figure 7.16 will allow a quick estimate of M FB .

1,000
N l!')
0
0 0 0
I I I

"
~
~
"~ "~
~ ~
<I <I <I

100~---------+----~~---+-----4--~-7~~------------------;

10~----~~--~-T-7~~-----------------r----------------~

AhFB~-_I_- _ 1 _
1+hFE2 l+hFEl

Fig. 7.16. AhFB vs. AhFE•


1 22 D-C and Low-Frequency Designs

Base Emitter

Collector
Figure 7.17 Figure 7.18

Evaluation of rB. The term rB as used in this chapter is not exactly the familiar
ohmic resistance term of transistor equivalent circuits. The best definition of this
quantity is an explanation of how it arises.
Figure 7.17 shows a cross section of an idealized double-diffused mesa transis-
tor. Leakage currents flowing from the collector into the base region on the left
side of the wafer meet with little resistance between the collector junction and the
base lead. Currents on the right side, however, must move some distance hori-
zontally through the base to reach the lead, meeting a comparatively large resist-
ance. For lumped-parameter representation, it is convenient to define an average
effective value, rB, of this bulk resistance.
Precise measurement of rB is probably impossible, but for many transistor
geometries the simple test circuit shown in Fig. 7.18 can give an approximation.
Vee and VEE are adjusted to bias the transistor to its usual d-c operating conditions.
A small l-kc alternating current flow into the collector and out of the base is
superimposed upon the direct currents. The high-Q LC pair in the emitter lead
prevents any a-c flow out of this terminal. Under these conditions, the emitter
will acquire a floating a-c potential which is an average of the collector junction-
to-base IR drops. The signal current, is, can be found from
. VBG
IS=R (70)

Then a very simple one-dimensional current flow in the base leads to


, 3VEB 3VEBR
rB~ -.-=--- (71)
Is VBG

BIBLIOGRAPHY

Articles
Benedict, Robert P.: Transient Heat Flow, Electro-Techno!' pp. 93-112, December, 1961.
Kraus, Allan D.: Heat Flow Theory, Elec. Mfg., pp. 123-142, April, 1959.
Kraus, Allan D.: Extended Surfaces for Heat Transfer, Electro-Techno!' This is an excellent
series of articles beginning February, 1961, and extending at least through July, 1961.
Luft, Werner: Taking the Heat off Semiconductor Devices, Electronics, pp. 53-56, June 12,
1959.
Transistor Biasing 123

Walston, Joseph A.: Thermal Considerations in Transistor Circuit Design, TI Application


Report, 1962.
Webber, K. L.: Temperature Stabilization of Transistors in Class B Amplifiers, Proc. IRE
Australia, pp. 726-733, December, 1959.
Books
Brown, A. I., and S. M. Marco: "Introduction to Heat Transfer," 3d ed., McGraw-Hill Book
Company, Inc., New York, 1958.
Eckert, E. R. G., and R. M. Drake, Jr.: "Heat and Mass Transfer," 2d ed., McGraw-Hill
Book Company, Inc., New York, 1959.
Jakob, Max: "Heat Transfer," 2 vols., John Wiley & Sons, Inc., New York, 1949, 1957.
Lin, H. c., and A. A. Barco: Temperature Effects in Circuits Using Junction Transistors,
"Transistors I," RCA Laboratories, Princeton, N.J., 1956.
McAdams, W. H.: "Heat Transmission," 3d ed., McGraw-Hill Book Company, Inc., New
York, 1954.
Schneider, P. J.: "Heat Conduction," Addison-Wesley Publishing Company, Inc., Reading,
Mass., 1956.
8
Direct-coupled Amplifiers

This chapter provides detailed information on the nature of the sources of drift
in transistors, and presents techniques for the design of low-drift circuits for use in
the input stages of direct-coupled amplifiers. Although only the common-emitter
configuration is considered, the approach is applicable to any circuit in which drift
may affect circuit performance.
The minimum detectable signal of an amplifier is determined by the spurious
signals originating within the amplifier. Noise and/or pickup define this limit for
a-c amplifiers; d-c drift is usually the determining factor for direct-coupled ampli-
fiers. It is customary to specify drift in terms of the change of input voltage or
current required to maintain constant output conditions when the parameters of
the amplifier vary. If several stages are cascaded, the equivalent input drift for
the amplifier will be determined by the input stage, providing that stage has
moderate gain.

8.1 . SOURCES OF DRIFT

The major sources of drift in a transistor are changes in the d-c properties of
the collector-base and emitter-base diodes and the d-c transfer ratio. Figure 8.1 is
a T-equivalent circuit which has been modified to include both the d-c and small-
signal a-c characteristics of a transistor.

B
Fig. 8.1. Equivalent circuit for direct current and low-frequency alternating current (NPN).

124
Direct-coupled Amplifiers 125

The small-signal elements re, re, rb, and a are the conventional T parameters
evaluated at the desired operating point. The VEE battery, leo current generator,
and d-c transfer ratio, a, are included to provide the proper direct currents and
voltages at the operating point.
The total instantaneous currents ie, iB, and iE are made up of two components.
The design quiescent currents are denoted by Ie, lB' and IE while the incremental
deviations from the quiescent values are denoted by Me, MB , and l1iE •
Emitter-Base Diode. Figure 8.2 shows the VI characteristic of a typical forward-
biased emitter-base diode. In the equivalent circuit, the base-to-emitter terminal
voltage is approximated by
VBE = VEE + IBrb + lEre (1)
The ideal diode incremental resistance, r~~ given by
,,_ kT (2)
re - -
qIE
is included in reo
Collector-Base Diode. The reverse-biased collector-base diode is represented
by the true saturation-current generator leBO, and the small-signal collector resist-
ance re. The current in re when d-c bias is applied to the collector includes the
diode leakage current. The symbol leBo denotes total passive reverse current and
is given by
leBO = lOBO + Vesge (3)

where

Current Transfer Ratio. Figure 8.3 shows an exaggerated static plot of the
collector current generator transfer ratio, A. Over a range of values of iE near the

Fig. 8.2. Emitter-base diode forward characteristic.


1 26 D~C and Low-Frequency Designs

/
a=l~/
/ Slope= Ct

/
/
--.l------7~--
atliE /
--1---------- I
/ I I
I
/ I I
/ I I
// I I
/ -l r-tli E
~ I I

Fig. 8.3. Collector current generator static characteristic.

design operating point, the AiE current generator of Fig. 8.1 may be approximated by
(4)
where a is the static or d-c value of the transfer ratio at the operating point and €X
is the conventional smail-signal T parameter.
Temperature Effects. Figure 8.4 shows the collector current generator static
characteristic for two temperatures. For constant emitter current, the change in
the collector current generator may be attributed to a change in value of the d-c
transfer ratio, a.
(5)
where the subscripts refer to the two temperatures. In the emitter circuit, a change
in temperature causes a change in the VBE battery and also a voltage change, due

Fig. 8.4. Effect of temperature on collector current generator.


Direct-coupled Amplifiers 127

to shifts in re and rb. For constant-emitter current, the change in base-emitter


voltage is
(6)
For constant collector-base voltage, changes in the passive component of collector
current due to variations of leBo and gc may be expressed by
(7)

8.2. DRIFT* EQUIVALENT CIRCUIT

The input drift of a transistor stage may be calculated using the equivalent circuit
of Fig. 8.1 by taking into account the changes in the various parameters as indicated
by Eqs. (5) to (7). However, such a calculation is cumbersome, owing to the
presence of the terms representing the reference-temperature operating point.
The small-signal equivalent circuit of Fig. 8.5 follows directly from Fig. 8.1 by
the removal of the currents and voltages which define the operating point. The
Ll VBE battery in the emitter circuit is defined by Eq. (6), the LlloBo current generator
by Eq. (7), and the Sci1E current generator by Eq. (5) and Fig. 8.4.
Since the drift produced by changes in re, rb, and rc is included in Ll VBE and LlloBo,
the explicit dependence of these parameters on temperature has been omitted from
this circuit. The variation of small-signal gain due to changes in these elements and
in a may be considered separately if necessary. This equivalent circuit may be used
directly to calculate the small-signal gain of a transistor stage at frequencies down
to and including d-c, and to predict shifts from the design operating point due to
changes in temperature.

8.3. SINGLE-ENDED STAGE

Analysis. The single-ended common-emitter stage of Fig. 8.6a may be analyzed


for equivalent input drift by using the circuit in Fig. 8.6b. Input current and voltage
drift are, respectively, the values of LliB and LlVl required to maintain Llio at zero as
the parameters of the circuit vary.
* The term drift as used refers to shifts in the doc operating point of an amplifier due to changes
in the circuit parameters, and has no connection with the terms drift field or drift transistor. None
of the transistors considered are drift transistors.

t::.ic
v-......-----oc

B
Fig. 8.5. Equivalent circuit for drift and low-frequency alternating current (NPN).
128 D-C and Low-Frequency Designs

M eBo + !J.CiIE
I-a I-a
.-----(-1----,

(a) (b)
Fig. 8.6. (a) Single-ended common-emitter stage; (h) drift equivalent circuit.

The input voltage drift is given by


A
I..lVI =- are + rb I..lAV;BE - rbre + rere (A-I
I..la E
AT)
+ I..l.I.CO (8)
are - re are - re
and the input current drift is

MB =- LlVBE _ re (SalE + LlloBo ) (9)


are are - re
For most transistors, the current transfer ratio increases with rising temperature.
Thus, LlaIE in Eq. (9) is normally positive and adds to M oBo along with LlVBE/re.
In most cases re is large enough so that Ll VBE/re may be neglected. As would be
expected from the definition of equivalent input drift, Eqs. (8) and (9) are inde-
pendent of the collector load resistor, RL . Also, since
(10)
Eqs. (8) and (9) are insensitive to variations in the small-signal parameters re, rb,
and reo
As a good approximation, the expressions for equivalent input voltage drift and
equivalent input current drift may be written, respectively, as
(Moo Lla \
LlVI - -LlVBE - (rb + re) '-a- + ~ IE} (11)

and (12)

For high-gain transistors, a is very near unity, and changes only a few per cent over
the useful temperature range of the device; it may, therefore, be considered a
constant.
Input Voltage Drift. Figures 8.7 and 8.8 show static plots of VI VS. temperature
for various constant values of io; Fig. 8.7 is for a silicon grown-junction transistor
and Fig. 8.8 is for a germanium alloy transistor. The slope of these curves is
predominantly due to Ll VBE/ LlT. The departure from a straight line in the germa-
nium unit is due to the M oBo term in Eq. (11).
Direct-coupled Amplifiers 129

0.30'-----'----'---""---"----'--......1..---'---"----'----'
o 10 20 30 40 50 60 70 80 90 100
Temperature, °C
Fig. B.7. Equivalent input voltage drift, single-ended stage silicon transistor.

0.25

0.20

0.15

~
~ 0.10

-0.05'-----~----~------'------'-----~---~
o 10 20 30 40 50 60
Temperature, °C
Fig. B.B. Equivalent input voltage drift, single-ended stage germanium alloy transistor.
130 D-C and Low-Frequency Designs

For transistors with no body resistance, and holding iE constant, the expression
for the change in VBE with temperature is
~VBE Eg - V BE 5 k (13)
----;s;r - T + "2 q
where Eg is the energy gap, and both Eg and VBE are functions of temperature.
Typical values of this coefficient lie between 2.0 and 3.0 mvICC for both germanium
and silicon; for a germanium transistor at room temperature and VBE = 0.1 volt,
Eq. (13) predicts a value of 2.3 mvICC .
Input Current Drift. Figures 8.9 and 8.10 are static plots of iB vs. temperature
for various constant values of io. In the silicon transistor (Fig. 8.9), lOBo is negligible
at all temperatures considered and the input current drift is due to the variation
of a. For the germanium transistor (Fig. 8.10), ~iB is principally due to lOBo at
moderate and high temperatures, with a being the controlling factor at low
temperatures.
The saturation-current temperature characteristic may be approximated by
lOBO = NeBT (14)
where N and B are constants which vary from unit to unit and with material type.
For a germanium transistor, leakage current is negligible and M oBo - M oBo . The
temperature coefficient of lOBO for small excursions of temperature is

(15)

where (loBo)T is the value of lOBO at reference temperature.


For larger temperature increments, the number of degrees required for lOBO to
double in magnitude is useful. This coefficient is given by
8T<= 0.693 (16)
- B
20
18
16
14
12
'"~ 10
.~
8
6
4
2

0 10 20 40 50 60 70 80 90 100
Temperature, °C
Fig. 8.9. Equivalent input current drift, single-ended stage silicon transistor.
Direct-coupled Amplifiers 131

iB - lco(J.la)
iB (J.la) 2N1273
leo (J.la)

----
30 r-_____ ..... ""-

.
leo"lS -_

--
r-_ _-.-.._. rna - - __
I -_
~ ---_
-- -------'-- .:...
ieo,,15rn

10
- - - - _ 1.0rna

-----£~~
---
0.2 rna
-----
0.05 rna

-10

-20 - - - is-leo
- iB

-30 - - - leo

o 10 20 30 40 50 60
Temperature, °c
Fig. 8.10. Equivalent input current drift, single-ended stage germanium alloy transistor.

When the transistor is to operate over an extreme temperature range the change
in lOBO is approximately equal to the value of lOBO at the highest temperature.
From Figs. 8.9 and 8.10 the temperature dependence of a is such that fjJxIE is
approximately a linear function of temperature for both germanium and silicon.
Typical Drift Parameters. Figure 8.11 is a plot of tl VBE/ tlT vs. 10 for typical
transistors of each type; typical values of tlaIE / tlT are plotted vs. loin Fig. 8.12.
These data were obtained from a sample of 10 randomly selected production tran-
sistors of each type listed. The coefficients represent average values over the tem-

;;;;--::::::==~~2N~33~5~N~2N~3~36~______________
~

2N1273/ 2N337",2N338

I I I t I I I I I !
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Ie, ma

Fig. 8.1l. I1VBE/I1Tvs.10 •


132 D-C and Low-Frequency Designs

0.3

~
-...
ro
0.2 2N1237
::t
-
~I
""h 0.1
~<l
~~
~
2N337
2N335
2N338
=
o 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Ie, ma
Fig. 8.12. !1IiIE /!1Tvs. Ie.

perature ranges considered; however, as seen from Fig. 8.7 through 8.10, the
coefficients do not vary radically with temperature.
Figure 8.13 is a plot of the temperature, T CBO , at which !1lCBO/!1T is equal
to !1alE/ !1T, as a function of collector current. For a given collector current and
below the critical temperature T CBO , the temperature dependence of lCBO may be
neglected in predicting circuit performance. For temperatures near T CBO the tem-
perature coefficients of both lCBO and alE must be considered, while at tempera-
tures above T CBO it is necessary to consider only lCBO. Figure 8.13 also includes
a table which lists typical values of M CBO /!1T(lcBO)T and 8Tfor the 2N1273.

35
2N1273

30

25

20
~
8
E-i 15
Transistor
t:,Ieo oT
t:,T(Ieo)T
type
CC)-l CC)
10

2N1273 0.082 8.5


5

o 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Ie, ma
Fig. 8.13. Teo vs. Ie.
Direct-coupled Amplifiers 133

8.4. DIFFERENTIAL STAGE

The use of local degeneration in d-c amplifiers to stabilize the operating point
invariably reduces the stage gain and degrades the minimum detectable signal of
the amplifier. However, drift reduction by compensation does not materially af-
fect gain and, hence, offers a significant improvement in minimum detectable
signal. The emitter-coupled differential amplifier is a versatile input stage which
offers voltage-drift compensation between similar transistors.
Figure 8.14 is the equivalent circuit of a typical differential d-c amplifier stage.
For a pair of transistors which are matched at the operating point but have differ-
ent thermal coefficients, and for fc ~ Re + fe, Rb + fb, the equivalent input volt-
age drift is
Rb + fb + Re + fe (A T
LlVl - Llv2 = - (Ll VBEl - Ll VBE2) -
AI)
LlJ CBOl - L.1 CB02
a

This expression has the same form as Eq. (11), which is the equivalent input volt-
age drift for a single-ended stage. However, thermal effects are appreciably reduced
in the differential connection since changes in corresponding parameters of the two
transistors are subtractive.
The response of a differential amplifier to input signals may be analyzed from
the equivalent circuit of Fig. 8.14.

Rc Rc t::. iC2
'v---~-....q C 2

D.1CB02 i
- - +D."'2
-- E2
1- "'2 1- "'2

RB RB

E2

8"1 + RE

-
RB
RE +

f"'
Fig. 8.14. Differential-amplifier equivalent circuit for drift and low-frequency alternating cur-
rent (NPN).
134 D-C and Low-Frequency Designs

By properly arranging terms, it is possible to express Llim as



101
A
= GD (I.lVl - LlV2) + GA LlVl +2 LlV2 (18)

where GD and GA are respectively the transconductances for the differential and
average, or common-mode, input signals.
If (MOl - Llio2 ) is considered as the output in Fig. 8.14, the differential stage
transconductance is the same as that of the single-ended stage of Fig. 8.15a. This
single-ended stage may be used to predict the differential gain and drift perform-
ance of the differential stage. The current and voltage drift generators are the dif-
ference between the drift generators of the two transistors as indicated in Eq. (17).
The circuit of Fig. 8.15b has a transconductance equal to GA and may be used
for determining common-mode gain and drift. The drift generators in this case
are the average of the corresponding drift generators of the two transistors in the
differential stage.
An examination of the expressions for gain and drift of the differential amplifier
shows that many of the bias-stabilization techniques normally employed in Re-
coupled amplifiers may be used to stabilize the common-level operating point of
individual stages without affecting the differential performance.
The common-mode rejection factor of a differential amplifier is defined as

M = GGD (19)
A
It is possible to achieve perfect common-mode rejection in a circuit of this type
since GA [and therefore the denominator of Eq. (19)] vanishes when Rs is equal to
the critical value (Rs)K given by
(Rs)K = arc - Re - re (20)
2

RE

1(""'-"",)
+

1
+ 6Vl + 6V 2
2

- VEE
(a) (b) (c)
Fig. 8.15. (a) Equivalent differential amplifier; (b) equivalent single-ended amplifier; (c) con-
stant-current source for common-mode rejection.
Direct-coupled Amplifiers 135

When high values of Rs are necessary to provide adequate common-mode rejec-


tion, supply voltage requirements may be excessive. The transistor constant-
current source of Fig. 8.15c provides a high incremental resistance for these appli-
cations. When the base and emitter resistors of the constant-current source are
properly proportioned, an incremental resistance of (Rs)K may be realized.

8.5. INPUT STAGE DESIGN


In the design of low-drift input stages for direct-coupled amplifiers, some of the
variables which must be considered are source resistance, maximum operating
temperature, temperature range, and the desired drift performance.
Choice of Transistor. A knowledge of the maximum operating temperature
allows a choice to be made between germanium and silicon transistors. At tem-
peratures below their respective values of T OBO , drift performances of germanium
and silicon are quite comparable. As shown in Fig. 8.l2, the silicon transistors
tend to have lower input current drift than the germanium transistors. From Fig.
8.11 the input voltage drift is essentially the same for all types. Typical values of
T OBO for germanium alloy transistors are given in Fig. 8.13; for the silicon transis-
tors considered in this chapter, T OBO is in excess of lOO°C.
The choice of transistor type may also be influenced by the source impedance,
range of temperature, and desired performance. For low source resistance, low
values of input voltage drift may be obtained at temperatures above T OBO . With
high source resistance, the best drift performance occurs at temperatures where
lOBO may be neglected. For any given configuration, the drift may be significantly
reduced by placing the amplifier in a constant-temperature oven.
Choice of Circuit. In general, the input drift of a differential stage is at least as
good as an equivalent single-ended stage using standard transistors. F or low
source resistances, the differential stage offers an improvement of lO: 1 or better in
drift, owing to VBE• This improvement may be attributed to the inherent consist-
ency of the ~ VBE/ ~T coefficients, which for unmatched transistors of a given type
differ by 10% or less. For high-resistance applications in which the voltage drift
due to MB/ ~T is greater than ~ VBE / ~T, single-ended and differential stages have
comparable performance unless transistors with matched ~iB/ ~T coefficients are
used in the differential connection. For unmatched transistors of a given type,
SiiIE/~T coefficients may differ by 2: l. The ~IoBo/~T coefficients in germanium
transistors typically differ by 3: 1 or less; for matched lao at the operating tempera-
ture, MOBo/ ~T coefficients differ by less than 20%.
Choosing the Operating Point. Figure 8.12 shows that low values of input
current drift may be obtained by operating the input transistors at low values of
collector current. The input voltage drift is only slightly dependent on collector
current; the increase in ~ V BE/ ~T as collector current is reduced may usually be
neglected. In order to reduce the leakage component of lOBO, the collector-base
voltage should be held as low as possible.
Optimizing the low-frequency noise performance also calls for low values of col-
lector current and collector-base voltage. Optimum noise figure normally occurs
at source resistances in the order of a few kilohms. In general, the precautions
taken to reduce drift also tend to give low noise.
136 D-C and Low-Frequency Designs

Fig. 8.16. Input drift due to stages one and two.

As the collector current is reduced to minimize input current drift, the current
gain, LX, decreases and the internal emitter resistance, r e, increases. The gain re-
duction due to these two effects places a lower limit on the first-stage collec-
tor current.
In summary, a typical low drift input stage will be a differential amplifier with
collector current between 10 and 200 /La. The collector voltage should be 6 volts
or less to minimize leakage. At temperatures below T co, an equivalent input volt-
age drift of 400 /Lv or less per centigrade degree may be realized by using unmatched
2N336 or 2N338 transistors, provided the sum of resistances in the base and emitter
leads is less than 8 kilohms. For more critical applications, further drift reduction
may be realized by matching the transistors and/or placing the amplifier in a con-
stant-temperature oven.
In order for the differential amplifier to provide drift cancellation, the transistors
must be at the same temperature. Both transient and steady-state temperature
differentials may be minimized by securely mounting both transistors in a com-
mon heat sink of large thermal capacity.

8.6. SECOND-STAGE DRIFT

Figure 8.16 schematically shows the effect of drift in the second stage referred
to the input. For a single-ended amplifier, both the current drift and voltage drift
of stage 2 tend to cancel the equivalent input drift due to stage 1; for a differential
amplifier, the stage-2 drift may aid or oppose the drift of stage 1.

8.7. TWO DESIGN EXAMPLES

Figure 8.17 is the schematic of a d-c differential amplifier which makes use of
some of the design techniques outlined in this chapter. The amplifier performs
Direct-coupled Amplifiers 137
r - - - - -......- - - - - - - - - - r - O + Vee

Output
+

- VEE Output

Fig. 8.17. D-c differential amplifier.

best with low-resistance sources such as reference diodes, thermocouples, strain


gauges, accelerometers, etc.
Transistors QI and Q2 are operated at VOE = 6 volts, and 10 = 50 /La; Q3 and
Q4 collector currents are 200 /La. The input transistor pair have ~ VBE/ ~T coeffi-
cients matched to within 60 /Lv/eo. Since both ~a1E/ ~T and ~ VBE/ ~T are con-
stants, the residual input voltage drift is a linear function of temperature and may
be compensated by the sensistor* resistor S, and its associated transistor Q5. The
sensistor resistor has a positive temperature coefficient of 0.7% per Co. Potenti-
ometer Rl may be adjusted such that the sensistor resistor correction will cause
either output to increase with temperature. When Rl is in center position, no cor-
rection results.
The common-mode feedback transistor Q6 stabilizes the sum of the first-stage
collector currents, and hence gives almost perfect common-mode rejection.
If2N336 or 2N338 transistors are used in this circuit at temperatures below T OBO ,
adjustment of RI to give minimum drift as the temperature is cycled over the de-
sired range will give drifts of 6 /Lv or less per centigrade degree over a 15°C tem-
perature range.
A Four-stage Differential Amplifier. The circuit of Fig. 8.18 is designed for
maximum open-loop amplification of the differential signal. Series-shunt negative
feedback provides a high input impedance and low output impedance. The closed-
loop gain is determined by the differential feedback network and can be adjusted
by varying R I . Local shunt feedback in the third stage shapes the frequency re-
sponse and prevents oscillation under closed-loop conditions.
* Reg. U.S. Pat. Off.
0+ Vee
, +30v

"--..J\. " - " - - X


w
00

r
,
1---1----t--- VOl
VI • I

Constant
current
source
y

Constant
current
supply
Temperature 4.7 K 12 K
compensating
Sensistor©
resistor
Vz I I + Vee
+30v
--L______ Voz

Negative
All resistors ± 1 % feedback
All transistors TI2N338 amplifier

, 0 + Vee
+30v
Fig. S.18. Differential amplifier circuit.
Direct-coupled Amplifiers 139

Since all the transistors are NPN, the voltage level is increased at the collector
of each stage. Voltage-divider networks in the collector circuits of the second and
third stages drop the average output voltage to the desired level. Resistor R2 pro-
vides zero adjustment for the differential output, or a level control for either of the
single-ended terminals. No provision is made for adjusting the average output
voltage.
The amplifier of Fig. 8.18 responds to a differential signal of 25 fJ.V superimposed
on a common level which varies from zero to five volts. An input circuit similar
to that of Fig. 8.19, with a high value of R s , provides sufficient common-mode re-
jection to operate under these conditions. However, when series feedback is ap-
plied to the input, the feedback resistors shunt Rs and reduce the common-mode
rejection factor. The values of the feedback resistors determine the change of
collector current which results from a specified variation in the common level of
the source and, therefore, the minimum quiescent current at which the stage can
be operated.
Transistors Ql through Q5 maintain the quiescent emitter currents of the input
pair essentially constant at 50 fJ.a for the 5-volt change in the common input level.
This circuit acts as a negative feedback amplifier in which the common level of
the source is the input, and the potential of the emitters of Q3 and Q4 is the output.
Output is fed back to the emitters of Ql and Q2 by the feedback transistor Q5 in
such a direction as to oppose a change of input current. Amplified feedback pro-
vides adequate common-mode rejection by maintaining the closed-loop gain of
the common-level amplifier at much less than unity. Small common-level changes
which occur at the collectors of Ql and Q2 are further rejected by the common-
mode rejection of the second, third, and fourth stages.
Input Circuit. The d-c stability of an amplifier is determined primarily by the
input stage, since the equivalent input drift due to any subsequent stage is reduced
by the preceding gain. This stage is therefore operated at bias conditions which
produce minimum drift. Transistors with the best possible d-c characteristics

Fig. 8.19. Common-emiHer amplifier configuration.


140 D-C and Low-Frequency Designs

should be used for the input pair. For the circuit in Fig. 8.18, the optimum col-
lector current for the first stage was selected as 50 /La. Operation at lower levels
would deteriorate the gain because of a decrease in ex and an increase in the
emitter diode resistance re , thus increasing the drift of the second stage.
Because of the linearity of the VBE temperature characteristic, it is possible to
match VBE thermal coefficients for the input pair within 60 /LV IC o by measuring
VBE at two widely different temperatures. The magnitudes of VBE are also matched
to reduce the required range of zero adjustment.
Temperature coefficients for leBo and ex are not considered sufficiently uniform
to warrant matching. Effects of leBO are minimized by selecting units with low
leBO at the operating temperature.
Output Circuit. Output impedance for single-ended loads is determined by the
collector supply networks in the final stage. Since the collectors of Q6 and Qs
are effectively connected by the low differential output impedance, the output
impedance from either terminal to ground is approximately the parallel combina-
tion of R 3, R 4 , R 5, and R 6 •
When a single-ended output is used, drift in the average level of the output must
be eliminated as well as differential drifts. The average voltage of the output ter-
minals is made independent of the emitter potentials of Q6 and Q7 by Qs, which
acts as a constant-current supply.
Variations of the supply voltage present another source of drift in the single-
ended output circuit. An increase, i1Vce, in the positive supply voltage causes the
average output voltage to increase by i1Vo = i1Vcc/[R5/(R3 + R5)]' This drift is
compensated partially by the constant-current source, since an increase in the posi-
tive supply voltage produces an increase in the collector current of Qs.
Resistor R7 eliminates coupling of common-mode input voltage variations to the
output terminals through the differential feedback network. An increase in the
common level of the source causes the average potential at the emitters of the input
circuit to rise, thus increasing the current which flows through R s, R 9 , RIO, and
R l l , from the emitters of the input stage to the output collectors. The average
potential of the output terminals can remain constant only if the collector currents
of Q6 and Q7 increase such that the currents in the collector supply networks of
the final stage do not change.
The increase in the average emitter potential of the first stage causes the base of
Qs to increase because of the connection through R 7 • Since Qs determines the
average collector current of the final stage, collector currents of Q6 and Q7 are also
increased. Resistor R7 may be adjusted such that the average output level is not
affected by common-mode variations of the source ..
Thermal Compensator. The residual overall drift of the amplifier is compen-
sated by a special silicon resistor R12 which has a positive temperature coefficient.
This sensistor silicon resistor compensates for thermal variation resulting from
VBE, the primary cause of amplifier drift. Temperature characteristics of this ele-
ment are shown in Fig. 8~20. .
A variation of R12 with temperature changes the collector current of Q9 and the
current in potentiometer R 13 • The amount of this change is determined by the
bias current which is supplied to the silicon resistor through R 14 • ,When R 13 is
moved from its center position, a temperature-dependent potential is produced
Direct-coupled Amplifiers 141

2.0
~
u ~
~ o>
N ~U

.8 1.5 I~----~~~~~-r--~~~------~
VeE of silicon 0.8 ~
Wo
~
W
>
:;::; transistor ~ ~ .8
'" Sensistor© ~ g;
~
W resistor 1.0 2l ~
u 1.0 ~a;
c .8~
ro fJ)
tl '00
'00 c
W
0:: 1---b~-----+-------+-------+--------l1.2 e
0.5 I-

- 50 o 50 100 150
Temperature, °C
Fig. 8.20. Temperature characteristics of silicon resistor element.

between the emitters of Q1 and Q2; this potential may be adjusted for the desired
compensation.
A change in the collector current of Q9 with temperature does not affect the
quiescent condition of Q1 and Q2, because of the common-mode rejection provided
by Q5. Changes in the average level of the source do not affect the compensation
adjustment since, at a fixed temperature, Q9 is a constant-current source.
Test Results. The amplifier has a voltage gain for a single-ended output which
is continuously variable from 100 to 500, and a frequency response flat within one
per cent to 1,000 cps. When used with a low-impedance source such as a strain
gauge or thermocouple, it has drift characteristics superior to those of its electron-
tube counterpart.
The differential input impedance is in excess of 140,000 ohms. The output
impedance is less than 1,000 ohms to a single-ended signal, and less than 50 ohms
to a differential signal. The common-mode rejection factor is greater than
50,000: 1.
Drift was evaluated over a 12-hr period after an initial warmup of 45 min. The
equivalent input drift is less than 60 JW from 70 to SO°C. For critical drift appli-
cations, the amplifier should be operated under closely controlled temperature
conditions.
The input transistor pair and the silicon resistor should be mounted in a com-
mon heat sink of high thermal capacity. This procedure reduces transient drifts
due to different thermal time constants. Low drift characteristics are dependent
upon the stability of the transistor coefficients with time, the accuracy of adjusting
the temperature-compensation network, and the degree to which the temperature
characteristic of the compensation network matches the drift characteristic of the
amplifier.
Size, low power requirements; and low drift make the amplifier desirable for
military telemetering systems. Because of its versatility, many other applications
will be apparent for industrial and laboratory instrumentation.
The following sections illustrate methods of biasing and calculating the voltage
gain and input impedance of differential amplifiers.
A Two-stage Differential Amplifier. The circuit of Fig. S.21 shows a typical
design problem .. Q1, Q2, Q3, and Q4 comprise the actual differential amplifier, while
142 D-C and Low-Frequency Designs

- Vee - Vee

eo ----~

+ VEE
Figure 8.21

Q5 is used as a constant-current source. Q5 supplies bias current to Q2 and Q3,


appears as a high a-c or incremental impedance to the signal, and requires only a
fairly small d-c voltage drop. Two supplies are required for this amplifier so that
the input may be set at ground level.
Constant-current Generator. Rl and R2 form a voltage divider that sets the
emitter voltage of Q5. With the emitter voltage of Q5 set at a given level, R3 deter-
mines I E5 . From the data sheet, IE2 and I E3 were selected to equal 2 ma, so that
I E5 = 4 mao
v _ (Vee + VEE)R2 (21)
B5 - Rl + R2
VB5 - VE5 (22)

I E5 = VE5 (23)
R3

By using Eq s. (21) to (23), the actual values of R l , R 2, and R3 can be calculated.


Voltage Gain. Figure 8.22 shows the equivalent circuit used in calculating the
voltage gain of Fig. 8.21.
The current gain of the circuit is calculated first, and the voltage gain follows
from the relationship
RL
Av=A 1-R
(in)

In the calculations it is assumed that the voltage gains of the emitter followers, Ql
and Q4, are unity.
Direct-coupled Amplifiers 143

is

Figure 8.22

~ & &
AV(collector-collector) = e(in) = [(h{e + l)/hre](hib + R E) + Rg/h re = hib + RE (24)

Circuit values substituted into Eq. (24) give a calculated gain of 60:
2.7 kilohms = 60
20 ohms + 25 ohms
This agrees closely with the measured values of Table 8.1 (differential amplifier
performance).
Input Impedance. To find the input impedance, find Z4, then Z3, and work
progressively back to find Z(in) (refer to Fig. 8.21 for symbol meanings).

Z(in) = hie1 + (h re1 + 1)


R4 rie2 + 2R~hte2 + 1) + hib3(hte2 + 1) + G~::
(h
: Dz~
I)
R4 + hie2 + 2R~hfe2 + 1) + hib3(hre3 + 1) + h~::: 1 Z4

(25)

where Z4 = R5hib4 + R5 R g/(hre4 + 1)


R5 + hib4 + Rg/(hfe4 + 1)

Let hre }> 1, and let all respective parameters be equal:


Z. - h- hreR4(2hie + 2REhfe + Z4) (26)
(.n) - .e + R4 + 2hie + 2REhte + Z4
Z(in) can be reduced to an approximate form:
Z h R42hie + 2REhte + hib + Rg/hfe (27)
(in) - fe R4 + 2hie + 2REhte + hib + Rg/hte
Substituting circuit values into Eq. (27), Z(in) = 270 ohms. This is in reasonable
agreement with Table 8.1.
Differential Amplifier Performance. The following table shows experimental
results from the differential amplifier using 2N2188's. Five pairs of typical tran-
sistors were placed in the amplifier, and data were taken on each pair.
144 D-C and Low-Frequency Designs

Table 8.1. Typical Characteristics Measured at 25 ° C

D-c drift Output impedance


Transistor Input impedance Voltage gain referred to at 1 kc, collector
pair at 1 kc, kilohms (e o/ e(in» at 1 kc input 25-60°C, to collector,
/lv/CO kilohms
1 200 67 38 5.4
2 250 67 29.8 5.4
3 180 66 43.3 5.4
4 200 66 20.4 5.4
5 148 65 10.8 5.4

Operating conditions:
Maximum operating temperature: 60°C.
Output voltage swing before clipping: 16 volts peak to peak at 25°C.
RL RL
A V(collector-collector) =h 1 R = h- +R
fe + (h ib + RE ) + _g .b E
hfe h fe
where Rg = effective generator impedance for the differential stage (Q2, Q3).
Assumptions:
1. All transistors have equal parameters.
2. Output impedance of all transistors is much greater than that of their load
resistors.
9
Voltage Regulators

A voltage regulator provides a constant voltage to specified loads from a limited


range of input voltages. Since most applications require the series-type regulator,
only the series type will be discussed, although a shunt regulator may be used
where the load is relatively constant.
General design procedure may be divided into five elements as shown in the block
diagram of Fig. 9.1. Note that regulation is performed by comparing a sample of
the output voltage with a reference; any error present is amplified and used to
control a series element. The sampling element of the block diagram is usually a
simple voltage divider across the regulated output, as shown in Fig. 9.2 with its
Thevenin equivalent circuit. For this sampling element, the voltage to the com-
parison element is
ATVO = VO(R2 + R p2 ) (1)
Rl + R2 + Rp

where AT = voltage division of the resistive divider = R2 + R p2 (2)


Rl + R2 + Rp
and Vo = regulated output voltage

+ I Control I +
I I
I
I Amplifier
I
I
v:(in)
I Comparison l I
I
Sample I V(o ut)

I
I Reference
I
1
Fig. 9.1. Block diagram of a series or emitter-follower d-c voltage regulator.

145
146 D-C and Low-Frequency Designs

+ B
Il~ Rl
A(RI +Rpd

+
B Rpl
Rp V(out)
A V(out) '"
To Rp2
comparison

12~ R2

Fig. 9.2. Sampling element and its Thevenin equivalent circuit.

Equation (1) is valid when resistors R 1 , R 2 , and Rp are at the same temperature
and have the same temperature coefficient, i.e., are of the same type material.
Silicon breakdown diodes are generally used as voltage references in transistor
regulators because their breakdown voltage is relatively constant over a wide range
of reverse current. The effects of temperature, reverse current, and diode resist-
ance on breakdown voltage are characteristics that must be considered in the selec-
tion of a reference diode.
Silicon diodes with low breakdown voltages (on the order of 5 volts or lower)
usually have a negative temperature coefficient. As the breakdown voltage in-
creases, the temperature coefficient becomes increasingly positive. Figure 9.3 shows
how the temperature coefficient depends upon the nominal breakdown voltage and
the diode reverse current of typical breakdown diodes.
The doc resistance of breakdown diodes is also a function of reverse current and
breakdown voltage as shown in Fig. 9.4. The doc diode resistance of a breakdown
diode can be calculated, using

= Ra_c + ~Vz
Rd-c
.
~T V zv
fj
(3)

where R a_c = dynamic diode resistance, () = thermal resistance of the diode, and
Vz and ~Vz/~T are as shown in Fig. 9.3.
Because of the characteristics shown in Figs. 9.3 and 9.4, a series combination
of low-voltage diodes is usually preferred over one high-voltage diode if a high
reference voltage is needed. A series string of low-voltage breakdown diodes can
be made to have a lower net temperature coefficient and total diode resistance than
a single diode used to provide the same reference voltage. The combined tem-
perature coefficient can also be changed with very little change in reference voltage
by using forward-biased diodes (either general-purpose or breakdown diodes) in
series with breakdown diodes.
The combined temperature coefficient of a series string of diodes can be deter-
mined from the following equation:
~VT ~VZl ~VZn ~VFl ~VFn
~T = ~T + ~T + ~T + ~T (4)
Voltage Regulators 147
8

~
.......
> 6
E
+-'"
c
Q)
·0
i: 4
Q)
0
u
~
.a 2
~
Q)
0-
E
2 0

~~I~
<I <I
-2

2 4 6 8 10 12 14 16
VZ ' breakdown voltage, volts
Fig. 9.3. Temperature coefficient vs. breakdown voltage: 1N746 series.

where IJ.. VT/ IJ..T = combined voltage change per CO


IJ.. Vz / IJ..T = voltage change per CO for each breakdown diode
IJ.. Vp / IJ..T = voltage change per CO for the forward diodes
The temperature coefficient of each diode carries its own sign in Eq. (4). The
combined temperature coefficient computed from Eq. (4) is valid at only one cur-
rent value; therefore a constant diode current must be provided to obtain a stable
reference element. A constant diode current is also required to keep the break-
down voltage and the diode resistance constant.
80r------r-----,------~----~------~----~

en 60
E
..c
0
ai
u
c
.:g 40
en
"en
~
Q)

"
0
0 20

o~-- __ ~ ____ ~ ______ ~ ____ ~ ______ ~ ____ ~

2 4 6 8 10 12 14
Breakdown voltage, volts
Fig. 9.4. D-c diode resistance vs. breakdown voltage: 1 N746 series.
148 D-C and Low-Frequency Designs

o----.......- - - - - - - - - Q + 0-----1----------0+

t----oQ+ ~----o+

Fig. 9.5. A reference element and its equivalent circuit.

The importance of maintaining a nearly constant temperature coefficient is


apparent. The reference element and equivalent circuit in Fig. 9.5 are used to show
why it is also desirable to keep the resistance of the breakdown diode as low as
possible.
Assume AIl is small so that ARR ~ o.
Assume 11 ~ 12 •
l1 R 3 + VR = T(out) (5)
AI1R3 + AVR = AT(out) (6)
AVR ~ AI1RR (7)
AV~3
~+ AVR ~AV(out) (8)

AVR ~ RR
(9)
A T(out) = R3 + RR
Equation (9) shows that the change in reference voltage for a change in output
voltage can be made very small by selecting a breakdown diode with low resistance
and by holding the reverse current nearly constant. Ideally, the reference voltage
in a regulator should not change for any normal output voltage change.
The temperature characteristics needed in the reference and comparison elements
are usually determined simultaneously, because each element affects the tempera-
ture requirements of the other.

9.1. COMPARISON ELEMENT

The comparison element takes a sample of the output voltage, compares it with
the reference voltage, and produces a signal that is proportional to the difference.
A single common-emitter stage or an emitter-coupled differential amplifier may
be used for the comparison element. The choice depends on the degree of regu-
lation and temperature stability required. The common-emitter stage (Fig. 9.6) is
discussed first.
The potentiometers in Fig. 9.6 are used to adjust the output sample to match
the reference voltage at specified output voltages. The current from the potenti-
ometer wiper into the comparison element must be kept much smaller than that
through the divider so that the sample voltage remains an accurate portion of the
Voltage Regulators 149

output. Is in Fig. 9.6a or 14 in Fig. 9.6b must be considerably larger than the emitter
current of Ql or Q2 so that the diode reverse current can be kept nearly constant.
The sample voltage is applied to the base of Ql, and the reference voltage is
applied to the emitter in Fig. 9.6a. If the output voltage tends to increase, the
base-emitter voltage of Ql will increase and cause more collector current to flow.
A drop in output voltage causes the collector current of Ql to decrease. The
change in Ql collector current and the change in the input current to the control
element are out of phase. This means that if the output voltage begins to rise, the
amplified difference voltage will decrease the current into the control element and
the output voltage will be corrected.
The reference element may be used as shown in Fig. 9.6b for high output volt-
ages. This enables transistors in the comparison element to operate at low voltage
levels, regardless of the regulator output voltage.
The collector currents of Fig. 9.6a and 9.6b are of opposite phase because of the
different reference-element positions. If Fig. 9.6b is used, a d-c amplifier is required
between the comparison element and the series control element to provide the cor-
rect phase relationship.
Temperature compensation for the common-emitter comparison element: Since
the reference voltage plus the base-emitter voltage of the comparison transistor is
equal to the output sample, the following equation applies for Fig. 9.6a:

(10)

where V(out) = regulated output voltage


VR = reference voltage
VBE = base-emitter voltage of comparison element
If R 1 , R 2 , and Rp are of the same material,

~V(out) = RlR+2 R2 R
+ p2
+ Rp
(~VR + ~VBE) (11)

and any change in output voltage is the result of ~ V R and ~ V BE . Since ~ V BE / ~T

...---_---0+ ...---......--.q+

To
d·c amplifier

1-t--+---CR p V(out)

(a) (b)
Fig. 9.6. Common-emitter comparison element with sampling and reference elements: (a) low
output voltage; (b) high output voltage.
150 D-C and Low-Frequency Designs

is usually negative, the temperature problem can be solved by using a breakdown


diode which has a positive temperature coefficient that exactly cancels ~ VBE/ ~T
of Qi in Fig. 9.6a.
The same approach shows that Eq. (12) applies for Fig. 9.6b:
Ri + R2 + Rp
~V(out) = R R (~VR - ~VBE) (12)
1 + pi

If the sampling resistors are of the same material, the breakdown diode must be
chosen with a negative temperature coefficient equal to ~ VBE/ ~T of Q2 in Fig. 9.6b.
Temperature compensation can be provided with little difficulty for temperatures
below about lOOoe, using a single silicon common-emitter stage for the compari-
son element. The effects from leBo are usually not critical below this temperature
in silicon transistors; therefore, the problems of compensation are due primarily
to changes in the base-emitter voltage, VBE, with temperature.
An emitter-coupled differential amplifier is ideal as a comparison element if the
regulator is to perform over a wide temperature range or at very high temperatures
(Fig. 9.7).
The symmetrical arrangement of the differential amplifier tends to make it self-
compensating for temperature effects. Self-compensation can be improved by
selecting well-matched transistors and mounting them on a common heat sink.
The degree of matching needed is determined by the temperature compensation
required. The position of the reference diode, the associated phase shift, and a
slight gain variation are the only differences between the high- and low-output
stages in Fig. 9.7. The output of the differential amplifier is usually taken from
only one side unless cascaded amplifiers are used. The side chosen for the output
is determined by the number of phase shifts between the comparison element and
the control element.
The currents through the reference element and through the divider must again
be much larger than the base currents of the differential amplifier.
If the differential amplifier is perfectly temperature-compensated, the following
equations apply:
For Fig. 9.7a,
~v. - Ri + R2R+ Rp ~VR (l3)
(out) - R
2 + p2
and for Fig. 9.7b,
~v. - Ri + R2R+ Rp ~VR (14)
(out) - R
1 + pi

Equations (l3) and (14) show that an output voltage change with temperature
variation is due to a change in the reference voltage if the divider resistors are of
the same material. In both cases the breakdown diode should be chosen with a
temperature coefficient near zero. Equations (l3) and (14) were obtained assum-
ing that the base-emitter voltages of Qi and Q2 are equal and also that the base-
emitter voltage changes with temperature of Qi and Q2 are equal.
It should be noted that the performance of the voltage regulator with changing
Voltage Regulators 1 51

O-~~----~-'-------1-----O+ +

(a) (b)

Fig. 9.7. Differential amplifier comparison elements with sampling and reference elements:
(a) low output voltage; (b) high output voltage.

temperature is primarily determined in the design of the sampling, reference, and


comparison elements. The operation of the other elements is not critically depend-
ent on temperature.

9.2. D-C AMPLIFIER ELEMENT

The d-c amplifier must raise the difference signal from the comparison element
to a level sufficient to drive the control element. Because the amplifier is within
a strong feedback loop, very critical d-c amplifier design is not necessary. The
only requirement in most cases is that a gain be provided that is large enough to
supply the required current to the control element and small enough to retain
circuit stability.
In many cases, a single transistor or stage functions as both the comparison
element and d-c amplifier. Additional amplifier stages may be required for higher
loop gain to further improve the regulation and decrease the output resistance of
the regulator. The usual d-c amplifier element is similar to the common-emitter
comparison element in Fig. 9.7. A breakdown diode is used in the emitter circuit
to improve the voltage gain of the amplifier. Temperature compensation is not
critical in this portion of the regulator, but the breakdown diode should be chosen
with a temperature coefficient that will tend to cancel ~ VBE/ ~T of the amplifier
transistor.

9.3. CONTROL ELEMENT

The control element interprets the signal from the d-c amplifier and makes the
adjustment necessary to maintain a constant output voltage. The basic control
elements used in the three regulator types are shown in Fig. 9.8.
The control elements of series and emitter-follower regulators are basically the
same except for the base drive, which comes from the d-c amplifier in a series regu-
lator and from the reference element in an emitter-follower regulator. Series and
emitter-follower control elements must be capable of carrying the full load current
152 D-C and Low-Frequency Designs

of the regulator, but during normal operation the collector-emitter voltage can be
much less than the output voltage.
The shunt control element must be capable of withstanding the entire output
voltage; however, it does not have to carry the full load current unless required to
regulate from no load to full load. Since the series dropping resistor used with
the shunt regulator has high dissipation, total efficiency of the regulator is degraded.
The preceding observations indicate that a series regulator is preferable for high
voltage and medium current outputs with variable loads. The shunt regulator can
be used for medium to low voltages and high output currents with relatively con-
stant loads. Application of the emitter-follower regulator is usually limited to low
output voltages. It has poor ripple suppression and poor regulation with respect
to input variation, compared to the other regulator types.
Some of the quantities that must be considered when selecting a control element
are the maximum voltage, current, and power ratings of the transistor. The limi-
tations for a single transistor series or emitter-follower control element can be
determined from the following:
VCE(ma:c) > V(inma:c) - V(outmin) (15)
I C(ma:c) > I(out ma:c) (16)

P C(ma:c) > (V(in ma:c) - V(out min»I(out ma:c) (17)


where V(in ma:c) = maximum unregulated input voltage
I(out ma:c) = maximum load current
V(out min) = minimum output voltage
VCE(ma:c) = maximum allowable collector-emitter voltage
I C(ma:c) = maximum allowable collector current
P C(ma:c) = maximum allowable collector dissipation
The shunt control element must satisfy the following requirements: The series
dropping resistor, R s , should be chosen such that the current through the control
element can be held to a minimum.

R < V(in min) - V(out ma:c)


(18)
s-
- I(outmax)

V CE(max) > V(out ma:c) (19)

I > V(in ma:c) - V(out min)


C(ma:c) = V. V.(out ma:c)
(in min) -

I(out ma:c) - I(out min) < I C(max) (20)


P C(ma:c) > I C(ma:c) V(out max) (21)

The control element and regulator type can be chosen based upon the preceding
limitations if the performance requirements of the regulator are known. The
maximum power-dissipation ratings must be observed at all operating tempera-
tures. Power derating at elevated temperatures is given on the transistor data sheet.
The control-element drive current and the collector current of the d-c amplifier
are supplied from a common shunt current source.
Voltage Regulators 153

Fig. 9.8. Regulator control elements: (a) series regulator; (b) emitter-follower regulator;
(c) shunt regulator.

The series and shunt regulators should be designed so that the collector current
of the d-c amplifier is equal to or greater than the maximum current needed for
the base drive of the control element. This design consideration is needed to ensure
that the control element will have enough base drive current available to maintain
the required output current.
Because the current supplied to the base of the control element is usually small,
a compound connection is often used to provide the current gain necessary to
maintain a required load current. A compound connection, sometimes called a
beta multiplier, is shown in Fig. 9.9.
Assuming hpE ~ 1,
I(out) ~ (hpElhpE2hpE3 . . • hPEn)IBn (22)
Each transistor in the compound connection must withstand a voltage equal to the
maximum unregulated input voltage minus the sum of the output voltage and the
base-emitter voltage of each preceding transistor. The collector current require-
ments of each transistor are decreased by the corresponding hPE(n-l), going from
Ql to Qn. The power requirements for each transistor can be determined from
this information, and the best-suited transistors can be chosen for the compound
connection.

+ o-----..---~ --
[(out)

~----_o+

V (out)

. .
Fig. 9.9. Compound connection
~
• •
Qn
To d·c amplifier
and current
source
used as series control element.
1 54 D-C and Low-Frequency Designs

9.4. PREREGULATOR

The preregulator should be included as a functional element if the regulator is


to perform to its full capability. The preregulator provides a constant current to
the collector of the d-c amplifier and the base of the control element. If point A
in Fig. 9.10 is returned through a resistor directly to the positive terminal of the
unregulated supply, ripple current caused by the unregulated voltage variations
will be injected into the base of Q2. The ripple will be amplified by the series con-
trol element and appear in the output. A preregulated d-c supply obtained from
R 1 , R 2 , and Dl helps eliminate the ripple current. The breakdown diode tends to
keep a constant voltage across R2 and a constant current to Q2 and Q3. The
breakdown voltage of Dl can be any value less than V(in) - V(out) that will supply
sufficient current to Q2 and Q3. If possible, the breakdown voltage of Dl should
be approximately equal to four times the normal change in base-emitter voltage of
the control element. The values of this voltage may be calculated as follows:
V Z1 = V(inmin) - V(outmax) - flRl (23)
where It = lZl + 12 (24)
12 = IB2 + lC3 (25)
IB2 and 103 will have been previously determined by the selection of the control
element, the comparison element, and the d-c amplifier. Therefore, lz is a known
value.
R2 = V Z1 - V BE1 - V BE2 (26)
IB2 + 103
Knowing the nominal voltage of the breakdown diode, the current through R z,
the input and output voltages, and the maximum allowable current through the
diode, the resistance of Rl can be determined.
Vl(max) = V(inmax) - V(outmin) - V Z1 (27)
ll(max) = lZl(max) + 12 (28)

R > V(in max) - V(out min) - V Z1


so that 1- (29)
- lzl(max) + 1z
The maximum reverse diode current can be determined from the power-
dissipation ratings of the breakdown diode.
In addition to improving input regulation, the preregulator reduces the output
resistance of the regulator. If the current supply to Q2 and Q3 were shunted
through only a resistor, a load current increase would tend to cause the output
voltage to drop. The drop is caused by an increase in base-emitter voltage of the
control element and by a higher voltage drop through the internal resistance of the
unregulated supply. When this occurs, the comparison element is forced to com-
pensate for both changes, and the resistance of the unregulated supply as well as
the emitter resistance of the control element will contribute to the output resistance
of the regulator. Depending upon the source resistance, the output resistance can
be reduced by as much as one order of magnitude if the preregulator is used. If
the voltage across R2 is constant with small load changes, the output resistance is
independent of the internal resistance of the unregulated supply.
Voltage Regulators 1 SS

Dl

+Q---+-,<: ~+----~-~+

V Cout)

Fig. 9.10. The preregulator.

Improved performance for a preregulator can be obtained by using the circuit


of Fig. 9.11 in place of the two resistors (Rl and R 2 ) and the breakdown diode Dl
of Fig. 9.l0. In the circuit of Fig. 9.ll, the collector current of Q4 is independent
of changes in VBE of Q2 caused by temperature or load variation. In Fig. 9.10, the
current 12 is a function of the combined VBE of Q2 and Ql, due to either tempera-
ture or regulator load, or both.
From Fig. 9.l1,
104 = lE4 - IB4 = 182 + 103 (30)

RJE4 = VZ3 - VEB4 (31)

or R4 = VZ3 - VEB4 (32)


lE4
D3 is chosen to have a temperature coefficient sufficient to cancel ~ VEBI ~T of Q4.
A low breakdown voltage for D3 will fulilil two requirements: It will allow this type
of preregulator to operate with low unregulated input voltages, and will also pro-
vide the necessary negative temperature coefficient to cancel ~ VEBI ~T of Q4. If
the ~ VEBI ~T of Q4 is greater than the available negative temperature coefficient
of D 3, a small silicon diode may be added in series with D3 to provide additional
compensation.
+
Q1
Da B
R4

Iza~
Vein)

Is}

R5
-
IB4
Q4
---+-
IC3
~~----------- - -- - - To Qa
IC4

Fig. 9.11. Transistor preregulator.


156 D-C and Low-Frequency Designs

1B2 and 103 have been previously determined; now a transistor is selected which
will handle the sum of 1B2 and 103 . A low-voltage breakdown diode is selected for
D3 with lz3 determined from its power-dissipation rating. R5 can now be found
from
R5 = V(inmin) - V Z3 - lz3 R R (33)
I Z3 + IB4

9.5. FILLING IN THE BLOCKS

The elements just described can now be connected to show a complete regulator.
Figure 9.12 shows a regulator using a single common-emitter stage as comparison
element and doc amplifier element, and the resistor-breakdown diode-type
preregulator.
Figure 9.13 shows a typical regulator using a differential amplifier comparison
element, a single-stage doc amplifier, cmd the single transistor preregulator of Fig.
9.11. Note that this type of circuit uses both of the best methods of temperature
compensation: i.e., the differential amplifier and the temperature-compensated
transistor current source.

r----------..,
~--~I~ I
I I

i
L__
Rs
_ _ _ _ _ _ .J
:
Preregulator
r- - - - - - . . . . ,
r---l
+o-----I~~~ ~~.I--_+------------------~--~~~~--1_----_Q+
I I I
I I Current
I
I Q11 source Ra I
Phase shift
I I for Dl
capacitor Rl I
I I C1
IL I C2
_ _ _ _ _ _ ...II
I
Control r ------, I
I I I
I ~~I~~-+--~~ I
I I Rpi
IL ______
Q3 ...JI I
Comparison I
and amplifier I
I
1""'"-- - - - , I
I I I
I I I
I I R2 I
IL D l...JI
____ I
Reference I
I
___ J
Sample
Fig. 9.12. Typical series regulator using single common-emitter stage comparison: doc amplifier
element and resistor-breakdown diode preregulator.
r---------l r----'
, I I I I +
+0 • • f
I I I
I
I I I
I
R;~ fR; I
I
Rs R5
I I Rl
I
I
C1
I I I I
I I I
I I I I
*C2
I I II I
L _ _ _ _ _ _ _ ...J I I I I
I I I I
I Control I I
I I I I I
I I I I I
I I I I I V(out)
V(in)
I I I Rp I
I I I
I I I
* Current sources I I I
I
R; I
I
I
for Dlo D 2,
and Da ,--
I
--l I
I I
I I I
I I
I I
I I I I I I
I B
I B
I I I I
I I I <.R2
I
D2 I
I Dl I II I I
I I I I I I
I I I I I I
I I I I I I
- -
IL _ _ _ _ _ _ _ _ ..JI IL ____ J
I IL _ _ _ _ _ _ _ _ _ ...JI IL ____ ..J
t;; Preregulator Reference Comparison Sample
~

Fig. 9.13. Typical series regulator using differential amplifier comparison element, single-stage
d-c amplifier, and single transistor constant-current source.
158 D-C and Low-Frequency Designs

9.6. TYPICAL VOLTAGE-REGULATOR DESIGN

In this section a voltage regulator will be designed from a typical set of regulator
requirements. The regulator requirements must be specified before any attempt
is made to design the circuit. The problem is then reduced to determining a circuit
configuration adaptable to the application and solving for the component values.
The voltage-regulator specifications are as follows:
V(in) = 37.5 to 70 volts
Vo = 30.0 volts
< 0040 amp
10
T = -50 to + 125°C
and Ro < 0.5 ohm
A regulator which satisfactorily meets these specifications is shown later in
this chapter. Performance parameters for this circuit are described after these
parameters are first discussed in general.
The following steps are numbered to provide a logical design procedure:
1. The transistors needed in the control element are determined first:
VOE1(min) = ~inmin) - Vo = 37.5 - 30 = 7.5 volts
VOE1(max) = ~inmax) - Vo = 40.0 volts
IE1(max) = 10 = 0040 amp
P01(max) = (VOE1(max)(IEI) = (40 volts)(0.4O amp) = 16 watts
The data sheet for the TI 2Nl049 shows that with a proper heat sink, 16 watts
can be dissipated satisfactorily. At 500 rna and - 55 ° C, the 2N 1049 has a
minimum specified doc gain of 20. Therefore,

I B I>- lEI _ 0.40 ~ 20


- hFE1(min) + 1 - - 2+01= rna

2. Q2 is used in the compound connection with QI. It is selected as follows:


VOE2(max) = V OE1 - VBEI - V OE1 = 40 volts
IE2 ~ IBI = 20 rna
P 02(max) < (VOE2 (max)(IE2 ) = (40 volts)(0.02 amp) = 0.8 watt
The data sheet shows that a 2N497 or 2N656 will meet these requirements for
Q2. The 2N656 is selected because of its high current gain. Since hFEI > 20
and hFE2 > 25, then

IB2 < lEi 0040 080


(hFE1(min) + 1)(hFE2(min) + I) (20 + 1)(25 + 1) - . rna
103 > IB2 and 104 ~ 2 rna (two or more times I B2 )
3. In order to obtain the maximum range of temperature over which this regu-
lator will operate, a silicon PNP 2N1l31 is selected for Q4. It has an hFE(min)
of 15 and a V EB of 1.3 volts. Therefore, if 104 = 2 rna, lE4 = 104 + IB4 =
2 rna + ¥is rna = 2.133 rna. If we choose a V Z2 of 3.3 volts (lN746), from
Voltage Regulators 159

Fig. 9.4 we find that it has a resistance of about 50 ohms. Then from Eq. (32),

4. 3.3 - 1.3 0 935 kil h


(2.133)10- 3 = . 0 m

Use R4 = 1.0 kilohm.


5. From Eq. (33),

R 5= V(in min) - V Z2 37.5 - 3.3 48 kil hm


1z2 + 1B4 (7 + 0.135)10-3 =. 0 S

Use R5 = 5.1 kilohms.


6. The reference element, sampling element, and comparison element must be
specified after the control element and preregulator are designed. The break-
down voltage of Dl is not critical so long as it remains constant for normal
regulator operation. Dl must be chosen with a low resistance and a slightly
positive temperature coefficient for this application. A IN753 is chosen, hav-
ing a zener voltage of 6.2 volts. Current through the diode must be sufficient
to maintain breakdown; therefore, if 1Zl is chosen to be 4 ma, which is large
compared to 1B4 , then

7. R - Vo - V Z1 _ 30 - 6.2 ~ 6 kil h
3 - hl - (4)10-3 - 0 ms

Use R3 = 6.2 kilohms.


Note from the data sheet that using smaller current through the breakdown
diode produces a higher positive temperature coefficient. In this case, a 6.2-volt
zener carrying 5 ma has a temperature coefficient of 0.03% per Co, or about
+ 1.86 X 10-3 volt/CO. This is close to being the negative of the temperature
coefficient of VBE , i.e., about - 2.5 X 10-3 volt/CO. We can therefore expect
the IN753 at a current of about 3.5 ma to be even closer to canceling the change
of VBE of Q3 with temperature.
8. Collector current of Q3 will be about 3 ma, so a 2N338 is chosen for Q3.
9. A 500-ohm wire-wound potentiometer is used for R p , and 1Rl is chosen to be
Sma.

10. R > Vo - V BE - Vz = 30 - 0.8 - 6.2 = 4.6 kilohms


1 = 1Rl 5(10- 3)

Use Rl = 4.7 kilohms.


11. 7.0
5(10-3)
= 1.4 kil0 hms
R2 = 1.4 - 0.5 = 0.9 kilohm
Use R2 = 1.0 kilohm.
The O.OI-fLf capacitor from collector to base of Q3 has been added to prevent
high-frequency instability. Also, Rs has been added to provide a path for leakage
currents and to allow operation down to low load currents.
160 D-C and Low-Frequency Designs

+ +
Ql
D2 B 2N1049 Ra
1N746 6.2 K
0.01 JLf
Vo
30 volts
V(in)
0-400ma
37.5-70 volts
Q4
2N1131
1--1--"-+.....< Rp
5000
Rs R6
5.1 K 30K

Fig. 9.14. Typical series regulator using transistor-type pre regulator .

Figure 9.14 is a schematic of the completed design. Curves of Va vs. Vin ,


Va vs. la, and Va vs. temperature are shown in Figs. 9.15,9.16, and 9.17, respec-
tively. Data from these curves will be used later to determine performance
parameters for this circuit.
The regulation factor, F, for various output currents is shown in the curves of
Fig. 9.15. Output resistance, R o, for various input voltages is shown in the curves
of Fig. 9.16. The temperature coefficient, K T , is shown by the curves of Fig. 9.17.

30.76

30.74

30.72

.l!l
0
> 30.70
,;:>-0,

30.68

F= Ll.Vo
30.66 at tHo=O
Ll.V(in)

I I I I I I I I
40 45 50 55 60 65 70 75
V(in). volts
Fig. 9.15. Vo vs. E(in) for circuit of Fig. 9.14.
Voltage Regulators 161

30.76

30.74
:=:----.-x
~
'0
>
30.72

~ 30.70
~ x
xV(in) =
70 volts
x 60 volts

x50volts
30.68
T=25°C 40 volts
Ro= ~: at I:::" V(in) =0 x37.5volts
30.66

I I I I I I I I
50 100 150 200 250 300 350 400
10 , ma
Fig. 9.16. Vo vs. 10 for circuit of Fig. 9.14.

31.20

10=0 ma KT =0.0029 VI:>:;:;:


31.10

31.00 ;}~.
;::..0 30.90 f
30.80

30.70
10=1~Oma
x~
I~X:
~:_
K T =0.00294 VICo
••

~:..... /
~•• ~'
~~~~400m'
x:::::::::::........
I K T -O.00268 ViC"

10= 250 ma KT = 0.0028 VICo

01~____~____~____~____~____~____~____~____~1 ____ ~1 ____ ~1


-50 -25 o 25 50 75 100 125 150 175
Temperature, °C
Fig. 9.17. Vo vs. temperature for circuit in Fig. 9.14.
162 D-C and Low-Frequency Designs

The values for KT were found by KT = b.V/tlT, where b.Twas -25 to + 100°C,
or b.T = 125. Since KT is the slope of the curves plotted, the worst KT will be the
maximum slope of the curve; since this maximum slope constitutes only a very
limited portion of the curve, however, it does not yield a valid K T . The maximum
change in output voltage will then be, from Eq. (44),
tlVo = Fb.V(in) + RoMo + KTb.T
This completes the design of the typical series regulator. Note that there are a
number of combinations of elements that may be used to obtain the complete cir-
cuit. These elements are chosen on the basis of the regulation required over a given
temperature range.

9.7. PERFORMANCE PARAMETERS


Regulator performance can be expressed in terms of R o, F, and KT in the regu-
lation equation

where Output resistance = Ro = b. V(out) I (34)


b.I(out) aE(in) =0

Regulation factor = F = b. V(out) I (35)


b. V(in) LIl(out) =0

t) I t.I(out) =0
b. v,(o_u_
Temperature coefficient = KT = __ (36)
b.T aE(in)=o
This section discusses methods used to predict the performance of regulators.
A black-box approach shows the significance of each performance parameter
(Fig. 9.18).
The current and voltage relationships can be expressed in terms of g parameters
if the regulator is assumed to be linear.
b.I(in) = gll V(in) + g12 I(out) (37)
b. V(out) = g21 b. V(in) + g22 b.I(out) (38)

where gll=~
b.I(in) I (39)
(tn) LIl(out)=O

(40)

(41)

g21 =b.V(out)]
--- (42)
b. V(in) t.I(out)=O
Emphasis is placed on Eq. (38) because V(out) is the regulated output voltage.
The parameters g21 and g22 should be made as small as possible to minimize varia-
twns in V(out). Equation (41) shows that g22 has the dimensions of resistance;
Voltage Regulators 163

~ r-------, 1~
+ r i 01 2 O-it------O + '?
V(in)
iI Regulator
I
I
I
V(out)

-J-----.......;:~O 1
IL- _ _ 20 I
_ _ _ _ _ ....JI
b-
Fig. 9.18. The regulator as a black box.

specifically, it is the output resistance of Fig. 9.18 and is designated as Ro through-


out this chapter.
The forward transfer parameter, g21, is a dimensionless quantity that is used to
define the regulation factor, F. The per cent regulation with respect to input
variation is given by F X 100%. If the regulator input voltage has A % ripple, the
output voltage has AF% ripple.
The performance of the regulator with changing operating temperatures requires
the definition of another parameter, K T . Although the effects from changing tem-
perature are nonlinear, the value of KT obtained from Eq. (43) is usually adequate.

(43)

Regulator performance can be expressed in terms of R o, F, and KT in the regu-


lation equation:
il V(out) = F il Vein) + Ro 11I(out) + KT ilT (44)
The degree of regulation can be improved by reducing any or all of the three
parameters in Eq. (44).

9.8. PERFORMANCE ANALYSIS BY INSPECTION

I f the regulator circuit is simple, the approximate performance parameters can


often be determined by inspection (Fig. 9.19).
To permit this simplified analysis, many assumptions are usually made. The
validity of the assumptions can be determined by checking the regulator require-

1(out) 1(out)
~ ~
+ + + +
Ql Ql
Rl Rl

V(in) V(out) V(in) v(out)

J j V R

Fig. 9.19. An emiHer-foliower voltage regulator and its equivalent circuit.


t
164 D-C and Low-Frequency Designs

ments and the information on the transistor data sheet. The operating tempera-
ture is considered to be nearly constant for this example. The breakdown voltage
and diode resistance, RR, are assumed to be constant, and any change in reference
voltage is assumed to be caused by a change in reference current. The load varia-
tion is considered to be small enough so that hpE will not change appreciably, and
hpE is assumed to be much greater than 1.
AV(out) = AI~R + AVBE
M(out) = hpE AlB
Ro = M~R + AVBE
hpEAIB
II = V(in) - VR - I~R
Rl
Assuming V(in), VR, R l , and RR to be constant,

Ml = -AI~R
Rl

AlB = All - AIR = -AIR RR+Rl


Rl

RlRR AVBER I
Ro = hpE(RR + R l )
+ -:-::-:-----:,:::::--=--:=---:-
M~PE(RR + R ) l
+ Rl)
A T
.:..l..l(out) = AI~PE(RR
Rl

so that Ro = RlRR + AVBE


hpE(RR + R l) AI(out)
If the load is nearly constant, AVBEI AI(out) - 0, and
Ro- RlRR
- hpE(RR + R l )
The regulator can be analyzed as a voltage divider to determine F by inspection.

RB = RoRL
Ro +RL

A V(out)

Fig. 9.20. A voltage divider used to determine F.


Voltage Regulators 165

RB is the parallel combination of the output resistance and load resistance. If


the load resistance is much larger than Ro (which is usually the case), RB ~ R o.
The circuit can be divided along a line separating the input from the output by a
high-impedance path (dashed line, Fig. 9.19).
Using Fig. 9.20 and assuming hFE ~ 1,

RA = RIre
RI + hFEre

F = RR(RI + hFEre)
hFEre(RR + RI ) + RR(RI + hFEre)
Assume hFEre ~ RI ~ RR, so that
F~ RR
RI + RR
The preceding steps have been used to determine the approximate parameters
by inspection. KT must be determined experimentally if changing temperature is
an important factor.

9.9. PERFORMANCE TEST CIRCUITS

Verification of performance parameters is usually necessary after the regulator


has been designed.
Figure 9.21 is a test circuit used to measure R o , F, and K T •
The methods used to determine R o , F, and KT are not complicated. The main
concern is the choice of a voltmeter for measuring Ll V(out). The meter must be
accurate and capable of displaying a voltage to the required sensitivity.
Figure 9.22 is a test circuit used to determine ripple reduction.
The a-c voltage providing the input ripple can be obtained by using a filament
transformer, which can be connected to a variable-voltage transformer to obtain a
variable input ripple. The peak a-c input and output voltages can be measured
with a calibrated scope, or the ratio of the two can be obtained by applying the
output ripple to the horizontal deflection and the input ripple through an attenuator
to the vertical deflection circuit of the scope. The attenuator can then be adjusted
until the scope indicates equal ripple to each deflection. The attenuator will then
indicate the reduction in ripple caused by the regulator.

~----~--~I~
,-------, ~~I---.--~

I I
I Regulator I
I I
~----~--~I~ o~I----~--------~
IL- _ _ _ _ _ _ _ ....JI

Fig. 9.21. Ro, K T, and F test circuit.


166 D-C and Low-Frequency Designs

a·c signal

W r--------,
~~~~~---:~ ~I----.-----~
I
: Regulator
I
I
I I
~--------j

. . Input ripple
Ripple reduction = Output ripple

Fig. 9.22. Ripple reduction test circuit.

Figure 9.23 is a test circuit used to measure the output impedance, Zo, of the
regulator, where

IZol = 1~(out)1
1'(out)1
The output impedance can be obtained by superimposing a small a-c voltage
across the regulator output. The ratio of voltage to current measured with the
oscilloscope will determine the output impedance. The a-c voltage applied must
be small compared with the output voltage. If the a-c voltage is too large, the
transistor in the comparison circuit can be driven into saturation or cutoff. Per-
formance changes caused by changing temperatures can be measured by placing
the regulator in an oven and taking measurements at the desired temperature.
r---------,
~--~I~O ~I~~--~------__----~

1
V(in) !
Regulator
(fixed) T i l
!
~_--~I-o ~I~;-__+-J\
IL _ _ _ _ _ _ _ _ .J
I

fal
I"-=J I
I Scope I
I I
I 0-..:.1-+--,
I
L ____
I
J

Fig. 9.23. Zo test circuit.

BIBLIOGRAPHY

Baldinger, E., and W. Czaja: Designing Highly Stable Transistor Power Supplies, Electronics,
voL 32, pp. 70-73, September 25, 1959.
Baum, J. R.: Thermal Considerations in the Use of Power Transistors, Electronic Design,
pp. 56-59,June, 1959.
Voltage Regulators 167

Brenner, E.: Regulated Transistor Power Supplies, Electronic Design, vol. 7, pp. 178-179,
March 18, 1959.
Carter, J.: Transistor Regulated Power Supply, Electronic Equip. Eng., vol. 7, pp. 55-56,
July, 1959.
Chase, F. H.: Power Regulation by Semiconductor, Elec. Eng., vol. 75, pp. 818-822, Sep-
tember, 1959.
Collins, D. J., and J. E. Smith: Regulated Power Supplies, Electronic Eng., vol. 31, pp. 222-
226, April, 1959.
Ervin, H. D.: Transistor Power Supply Has Overload Protection, Electronics, vol. 31,
pp. 74-75, June 20, 1958.
Franklin, C. A., P. M. Thompson, and W. M. Caton: Precision High-voltage Transistor-
overload Power Regulators with Overload Protection, Proc. Inst. Elec. Engrs., vol. 106,
pp. 714-725, May, 1959.
Giuffrida, J., and W. O. Hamlin: Transistorized 25-volt Regulated Power Supply, Electronic
Design, vol. 5, pp. 28-29, January 15, 1957.
Hamm, T.: Equations for Designing Transistor Power Supplies, Electronics, vol. 32, pp. 74-75,
June 20, 1958.
Hunter, L. P.: "Handbook of Semiconductor Electronics," pp. 13.26-13.28, McGraw-Hill
Book Company, Inc., New York, 1956.
Hurley, R. B.: Designing Transistor Circuits: DC Regulators, Electronic Equip., vol. 5,
pp. 20-23, April, 1957.
Hurley, R. B.: "Junction Transistor Electronics," pp. 208-229, John Wiley & Sons, Inc.,
New York, 1958.
Keller, J. w.: Regulated Transistor Power Supply Design, Electronics, vol. 29, pp. 168-171,
November, 1956.
Lillienstein, M.: Transistorized Regulated Power Supply, Electronics, vol. 29, pp. 169-171,
December, 1956.
Lowry, H. R.: Transistorized Regulated Power Supplies, Electronic Design, parts 1 and 2,
vol. 4, pp. 38-41, February 15, 1956; pp. 32-35, March I, 1956.
Luft, W.: Taking the Heat off Semiconductor Devices, Electronics, pp. 53-56, June, 1959.
Mamon, M.: High-voltage Transistor-regulated DC Power Supply, Elec. Design News, vol. 2,
pp. 46-47, October, 1957.
Middlebrook, R. D.: Design of Transistor Regulated Power Supplies, Proc. IRE, vol. 45,
pp. 1502-1509, November, 1957.
Mitchell, W. B.: Design Silicon Diodes into Reference and Regulator Circuits, Electronic
Equip., vol. 4, pp. 18-21, September, 1956.
Sherr, S., and P. M. Levy: Design Considerations for Semiconductor-regulated Power
Supplies, Electronic Design, vol. 4, pp. 22-25, July 15, 1956.
Sherr, S., P. M. Levy, and T. Kwap: Semiconductor Diodes Are Important in Design
of Transistorized Regulated Power Supplies, Elec. Design News, pp. 50-51, October,
1956.
Sherr, S., P. M. Levy, and T. Kwap: Design Procedure for Semiconductor-regulated Power
Supplies, Electronic Design, pp. 22-25, April 15, 1957.
Spencer, R. H., and T. S. Gray: Transistorized Voltage Regulator, AlEE Trans., part 1,
pp. 15-17, March, 1956.
Unvala, B. A: DC Power Supply Circuits Using Silicon Rectifiers, TI Application Report,
revised July, 1959.
Silicon Transistor Voltage Regulator Overload Protection, TI Application Note, June, 1960.
DC Regulated Power Supply Design, TI Application Report, August, 1960.
10
Chopper Amplifiers

10.1. DESIGN OBJECTIVES

Amplifiers capable of responding to direct current or voltage present serious


problems to the designer. At first glance it would seem that response to direct
current could be obtained simply by eliminating elements which restrict low-
frequency response, i.e., capacitors and inductors. If several stages could be coupled
together using only resistors, there would then be no low-frequency response limita-
tion, and the resulting amplifier would respond to direct current as well as (or
better than) it did to alternating current.
Such circuits are easy to build, and they usually perform quite well with d-c signal
inputs-so well, in fact, that they are almost useless. Such an amplifier can make
no distinction between signals originating outside and signals originating internally.
A change in I aBO with temperature, for example, is just as readily amplified as is
an incoming signal. And any attempt to use bias stabilization or negative feedback
reduces the gain of the amplifier in the same proportion as it reduces the tempera-
ture drift.
An amplifier which responds only to a-c signals need not be subject to this
cumulative drift error. Consequently, many d-c amplifiers change the incoming
signal into an a-c signal to be amplified and then rectified to form a d-c output.
(Alternatively, the incoming signal may be caused to modulate the amplitude of
an a-c signal which is then amplified and demodulated to form an output. This
approach is used in magnetic and in dielectric amplifiers.)
Typical circuits used to change an incoming signal from direct to alternating
current are shown in Fig. 1O.la and b. Sl and S2 are switches so arranged that
when one is ON the other is OFF, and they are closed alternately at some con-
venient frequency, say 60 times a second. In Fig. 1O.la the incoming d-c signal is
connected between the center tap and first one side and then the other of the
transformer primary. The output of the transformer will then be a 60-cps signal
proportional in amplitude to the input signal. The phase of the output, that is,
whether the closing of Sl produces a positive or a negative pulse at a given terminal
of the secondary, depends on the input polarity. In Fig. lO.1b, capacitor C charges
through R when Sl is closed and discharges when S2 is closed. In either circuit,
the upper-frequency response of the overall amplifier is usually limited to no more
168
Chopper Amplifiers 169

81
0 0

Input
1 8: i
2
Gput
Input TI :
82
c
R Output

(a) (b)
Figure 10.1

than one-fourth of the switching frequency. By interchanging the input and output,
these circuits may be used as synchronous rectifiers to change the a-c output signal
from the amplifier back into d-c. Switches used in these applications are often
called choppers.
No semiconductor device acts as a perfect switch; that is, during the ON period
the resistance between terminals is not zero, and during the OFF period it is not
infinite. These resistances vary with temperature and with current flow through
the device. In addition, the back bias which turns the device OFF creates tem-
perature-dependent leakage currents, while the base current turning ON a transistor
or the light turning ON a photodiode or phototransistor produces more stray
offset voltages at the device terminals.
Offset voltage is the potential appearing across the semiconductor switch terminals
when the switch is turned ON and no current is allowed to flow through the switch.
For example, the offset voltage of a transistor chopper is the collector-emitter
saturation voltage when Ie = O. Offset current is the current that flows when the
semiconductor is reverse-biased. Leakagy current through a reverse-biased diode
is an example of this.
An idea of the minimum noise power the switch can be designed to inject into
the circuit is indicated by the product of the ON offset voltage and the OFF leakage
current. The optimum impedance to be seen by the switch for this minimum noise
power is approximately equal to the offset voltage divided by the leakage current.

10.2. RING MODULATORS

The circuit concept of Fig. 1O.la can be modified to use diode switches, as in the
so-called ring modulator shown in Fig. 10.2. When a square-wave switching voltage
is applied to the primary of T i , diodes Di and Dz conduct during one-half the cycle,
while D3 and D4 are back-biased. Then, as the switching voltage reverses, D3 and
D4 conduct while Di and Dz are turned OFF. Each set of diodes acts as a voltage
divider across the secondary of T i . If the diodes are balanced, and if the two halves
of the secondary of Ti are balanced, the voltages at points A, B, and C will be equal
when there is no signal input, and no current will flow through the primary of T z.
As soon as a d-c signal is applied to the input, this switching action will cause the
direct current to flow alternately through the two halves of the primary of T z. The
result will be an a-c signal at the output proportional to the d-c input and of a
frequency equal to the switching frequency. If the incoming d-c signal contains
an a-c component, the output will also contain frequencies equal to the switching
frequency plus and minus the incoming frequencies. This is true for all chopper
170 D-C and Low-Frequency Designs

Signal input Ealoutput

Switching drive input


Fig. 10.2. Ring modulator.

circuits. The a-c amplifier associated with a chopper must therefore be able to
pass a band of frequencies centered about the switching frequency. (The width of
this passband will be one of the limits imposed upon the high-frequency response
of the overall amplifier.)
Switching at high frequencies, even radio frequencies, is possible with this type
circuit. Linearity is good over the entire operating range, and switching frequency
is limited only by wiring capacitance, transformer characteristics, and diode
response time. Maximum signal current and voltage are set by the usual diode
limitations.
Figure 10.3 is an equivalent circuit of the resistances which determine a diode's
behavior. RSL is surface leakage resistance (ohmic), RB is bulk resistance (ohmic),
and RD is diode resistance (variable).

RD = VD (1)
Is(€qVnlkT A _ 1)

where VD = applied voltage RD (+ for forward conduction)


Is = diode saturation current (+ in sign)
q/k = 1.161 X lO4 (coulombs)CK)/joule
T = temperature, K0

/I.. = a factor which is approximately I for germanium at room temperature


and may vary from I to 2 for silicon
The familiar diode equation has been modified by a factor, /1.., which is a func-
tion of transistor temperature, current density, and semiconductor material. (A
good discussion of the variation of /I.. and its cause is given by Moll and Pritchard. 1, 2)
Since RSL and RB are constant, diodes may be matched for these quantities by
placing external resistors in shunt and in series with each diode. Is is temperature-
dependent, and for the reverse-biased case may be approximated by
Is = NeBT (2)

..
Chopper Amplifiers 171

where Nand B are constants peculiar to each


diode. 3 Actually, extreme methods for matching RD
and compensating are not always necessary if
ambient temperature and signal level can be re-
stricted. U sing selected Texas Instruments
type-601C diodes and driving from high-imped-
ance sources, Keonjian and Schmidt have de-
Figure 10.3
tected signal currents as low as 10- 10 amp at
room temperature. 4 In their circuit, a low-level constant-current switching
drive serves to balance the diode forward impedances.
Transistor Choppers-Equivalent Circuits. In order to use transistors, the
simple circuits of Fig. 1O.1a and b must be modified. If a single transistor replaces
each switch, the collector and emitter will become the switch terminals. Switch-
ing will be performed by a signal applied between the base and either the emitter
or the collector acting as an emitter.
Figure 10.4 is the equivalent circuit for the ON condition of an NPN transistor.
The circuit is correct for PNP transistors when the polarity of VCE(on) is reversed.
Positive current convention is assumed.
/ kT"A 1
VCE(on) = IBrE + - - In- (3)
q ai

kT"A( 1 - a.a n )
--"----:;---=-"...:.:"-. + rE + rb (4)
qanIB

where IB = base switching current


rE = ohmic emitter bulk resistance
rb = ohmic collector bulk resistance
an = common-base emitter-to-collector current transfer ratio, or normal
alpha
ai = common-base collector-to-emitter current transfer ratio, or inverted
alpha
q/k = 1.161 X 104 (coulombs)CK)/joule
T = temperature, OK
"A = hfe/hPE
An equally simple equivalent for the OFF condition is not always possible. The
expression for the OFF collector current is
IC(off) = I CBO [1 _ eqBelkTX _ ai(l _ eqBelkTX)] - ~ (5)
I-~~ R~
where I CBO ~ collector-base diode saturation current (+ in sign)
Be = voltage across the collector diode taken as + in the forward-biased
direction
Be = voltage across the emitter diode taken as + in the forward-biased
direction
RCB = collector-to-base ohmic leakage resistance
Fig. 10.4. ON condition Emitter~III-I+---OCollector
equivalent circuit. R(on) VCE(on)
172 D-C and Low-Frequency Designs

1 o~",""

Iq"m~,-- __ t_R_CE- - 0 Emitter Fig. 10.5. OFF condition


equivalent circuit.

If both the collector and the emitter diodes are back-biased greater than about
0.2 volt at room temperature, Eq. (5) may be simplified to

(6)

Figure 10.5 is an OFF equivalent circuit for an NPN transistor, based on Eq. (5)
or (6). ROE is the collector-to-emitter ohmic leakage resistance. The circuit is
correct for PNP transistors when the direction of the current source IC(of{) is reversed.
Inverted Operations. The quantities VOE(on) and IO(ofl) appearing at the switch
terminals form a source of noise signal. Notice, however, that the absolute mag-
nitudes of VOE(on) and of IO(of{) may be reduced by increasing ai. If an and ai are
measured while the two transistor diode junctions function in the circuit as marked
by the manufacturer, that is, if the diode terminal marked "collector" is actually
used in the circuit as the collector diode terminal, etc., then an will generally be
larger than ai. But if the diode marked collector is actually used for the emitter,
and vice versa, then the new ai will be larger than the new an. This inverted op-
eration substantially reduces the magnitudes of V OE(on) and of IO(ofl). The disad-

r:nal

Signal
input
L ut

(a)

Signal Signal
input output

(b)
Switching drive input
Fig. 10.6. Simple transistor-chopper circuits.
Chopper Amplifiers 173

vantages of this technique lie in the increase of rit and possible increase in I CBO.
(In normal operation these quantities were r; and lEBO, respectively, but inverted
operation exchanges the normal collector for the normal emitter. Note also that
the former BVEBO becomes BVCBO in inverted operation. Grown- and diffused-
junction transistors may not respond well to this technique because of a large in-
crease in the inverted rit .)

10.3. TRANSISTOR CHOPPERS-PRACTICAL CIRCUITS

Many chopper circuits use two transistors in such a way that the offset voltages
and/ or leakage currents appearing at the switch terminals either oppose each other
or add to produce a constant d-c signal into the amplifier. Figures 1O.6a and b
are simple transistorized examples of Fig. lO.la and b, respectively. The success
of this approach depends on the degree to which the quantities I C(off) and V CE(on)
can be matched over the operating temperature range. A mismatch of VCE(on)
may be compensated by placing selected resistors in each emitter lead. R(on) and
lB are stabilized by resistors in the base leads which maintain constant and equal
base-drive currents. Good temperature compensation may be had by making one
of the base resistors temperature-sensitive.
The effect of the OFF currents may be minimized by selected resistors shunting
the emitter-collector terminals. Germanium diodes shunting the emitter-base
diode can reduce the reverse bias VBE(off). (Silicon diodes would produce a some-
what higher voltage and therefore a larger lC(off).) However, perfect temperature
compensation requires that the transistors be matched for lCBO. Although the ON
and OFF resistances of the switch are degraded by these additions, this loss
is often outweighed by the decrease in noise level.

Signal ~nal
input 1-5M ~ut

Switching drive input


Fig. 10.7. Practical design for transistor chopper.
174 D-C and Low-Frequency Designs

Figure 10.7 shows a circuit which employs all these techniques. 5 Transistors
Ql and Q2 are turned ON and OFF in unison. A small tapped resistor in the
emitter leads permits balancing in the ON condition, while a large tapped resistor
across both collectors permits a balance in the OFF portion of the cycle. Base
currents are held constant by the base resistors R1 and R 2. Diodes D1 and D2 op-
erate with resistor R3 to reduce the base OFF voltage and thus help lower the OFF
noise current.
Switching Transients. During the actual instant of switching, the transistors are
not matched and may produce a noise spike. The obvious remedy would be to mini-
mize the duration of the mismatch by switching very quickly with a square-wave
base drive. Two considerations limit this technique. First, wideband transformers
having very low leakage inductances and very low interwinding capacitances are
expensive. Second,if the rise time of the square wave is short, a large noise pulse
may be coupled into the circuit by stray capacitances, including the transistor
capacitance. Careful attention to these points is extremely important.

10.4. PHOTODIODES AND PHOTOTRANSISTORS

Photodiodes or phototransistors may be substituted for Sl and S2 in Fig. 1O.1a


and b without modifications. Since these call for a modulated light beam to per-
form the switching operation, their use is limited. During the OFF period, these
devices act as simple diodes, and the same matching considerations will apply. If
enough light is available during the ON period, the devices act as an ohmic resistance
in series with a voltage source and a maximum current limiter. The amount of
light affects the photovoltage developed and the level of signal current at which
limiting takes place.

10.5. MODULATED CARRIER SYSTEM

A complete chopper d-c amplifier may be regarded as a modulated carrier sys-


tem. The chopper frequency would correspond to the carrier frequency, while the
slowly varying d-c level would represent the modulating signal. Figure 10.8 shows
a simple block diagram of a carrier system.
The oscillator ideally produces a square wave with fast rise and fall times. This
allows fast switching of the modulator and demodulator (choppers). In the case
of Fig. 10.8, the oscillator drives both the modulator and demodulator so as to

Input Output
signal signal
Demodulator

Figure 10.8
Chopper Amplifiers 175

keep the same phase relationship between the two; i.e., both are switched at the
same time. Thus, the demodulator is synchronized with the modulator and is
known as a synchronous demodulator. Phase information as well as amplitude
information may be transferred through the system of Fig. 10.8.
If the demodulator consists of only a rectifier and an integrator as is the case in
many common radio receivers, only amplitude information may be transmitted
through the system.
An advantage of the a-c amplifier is that any d-c drift occurring in any of its
single stages is not passed along as signal, as is the case with d-c amplifiers. The
amplifier should have enough gain to be useful for its intended application. The
mid-band gain of the amplifier should be centered about the chopping or carrier
frequency and should have an adequate bandwidth to take care of all sidebands
that are produced in any modulating system.

BIBLIOGRAPHY

1. Moll, J. L.: The Evaluation of the Theory for the Voltage-Current Characteristic of P-N
Junctions, Proc. IRE, vol. 46, pp. 1076-1082, June, 1958.
2. Pritchard, R. L.: Advances in the Understanding ofthe P-N Junction Triodes, Proc. IRE,
vol. 46, pp. 1130-1141, June, 1958.
3. Biard, J. R., and W. T. Matzen: Drift Considerations in Low-level Direct-coupled Tran-
sistor Circuits, 1959 IRE Conv. Record, part III, pp. 27-33.
4. Keonjian, E. J., and J. D. Schmidt: Ring-modulator Reads Low-level DC, Electronic
Ind. Tele-Tech, vol. 17, pp. 86-89, April, 1958.
5. Hurley, R. B.: "Junction Transistor Electronics," John Wiley & Sons, Inc., New York,
pp. 376-382, 1958.
General References
Bright, R. L., and A. P. Kruper: Transistor Choppers for Stable D-C Amplifiers, Electronics,
vol. 28, pp. 135-137, April, 1955.
Chaplin, G. B. B., and A. R. Owens: Some Transistor Input Stages for High-gain DC
Amplifiers, Proc. Inst. Elec. Engrs., vol. 105, part B, pp. 249-257, July, 1957.
Chaplin, G. B. B., and A. R. Owens: A Transistor High-gain Chopper-type D-C Amplifier,
Proc. Inst. Elec. Engrs., vol. 105, part B, pp. 258-266, November, 1957.
Ebers, J. J., and J. L. Moll: Large-signal Behavior of Junction Transistors, Proc. IRE, vol.
42, pp. 1761-1772, December, 1954.
Ettinger, G. M.: Transistor Modulator for Flight Trainers, Electronics, vol. 28, pp. 126-127,
September, 1955.
Grubbs, W. J.: Hall Effect Devices, Bell System Tech. J., voL 38, pp. 853-876, May, 1959.
Hurley, R. B.: Transistorized Low-level Chopper Circuits, Electronic Inds. Tele-Tech, vol. 15,
p. 42, December, 1956.
Kruper, A. P.: Switching Transistors Used as a Substitute for Mechanical Low-level Chop-
pers, Communs. and Electronics, no. 17, pp. 141-144, March, 1955.
Roy, R.: Transistorized High Frequency Chopper Design, Electronic Design, vol. 6, pp. 52-
55, August, 1958.
Williams, A. J., Jr., J. U. Egnon, and N. E. Polster: Some Advances in Transistor Modula-
tors for Precise Measurement, Proc. Natl. Electronics Conf, vol. 13, pp. 40-54, 1957.
11
AGC of Audio Circuits

Automatic Gain Control (AGC) of an audio amplifier consists of controlling the


amplifier's transfer characteristics with a d-c control voltage that is proportional
to the input signal. The purpose of this is to compress the dynamic range of sig-
nals being handled, and it should be accomplished without adding appreciable
distortion to the input signal.
Block Diagram. The block diagram of a typical AGC amplifier is shown in
Fig. 11.1. In many cases the low-level amplifier is not used, and the input signal
is fed directly into the control stage. A typical power rectifier can consist of
a half-wave rectifier and capacitance filter driving a d-c amplifier, as shown in Fig.
11.2. In many cases the base-emitter diode of the transistor is used for rectifica-
tion, which results in a saving of components at the expense of power gain.
Control Stage. The operation of the control stage can be resolved into two
main types:
1. Variation of the forward transfer characteristic of a transistor with the d-c
bias current.
2. Variation of the dynamic resistance of a diode or transistor used as a two-
terminal feedback or shunting element.
An example of the first type is shown in Fig. 11.3. The transistor is normally biased
in the active region and the AGC voltage tends to turn the transistor off, thus de-
creasing Yfe. Although it is simple, the disadvantage of this kind of AGC is that
large input signals will result in distorted output, since the bias point approaches
cutoff as the signal is increased. The AGC action obtainable in this mode of op-
eration, without introducing serious nonlinear distortion into the signal, is limited
to about 20 db/stage.
Examples of the second type are shown in Figs. 11.4 and 11.5. In l1Aa, the
input current divides between the diode resistance, R D , and the input resistance of
the amplifier. As the signal is increased, the AGC voltage increases, decreasing
RD (Fig. 11.4b), which limits the overall gain of the stage. For this AGC method
to perform satisfactorily, the signal source must have a high resistance, and the
input resistance to the amplifier must also be high. In Fig. 11.5a, a transistor is
176
AGC of Audio Circuits 177

Input Output

Figure 11.1

- Control

j
current

~f f
~

s;:"
Figure 11.2

Ic

VB - V AGC

I
VCE
VB
h FE · Rs

L
-
l'AGc---1 V BE
(a) (b) VB

Fig. 11.3. Typical YFE curve.

VD

V AGC

f--o RD

eo

V AGC ID

(a) (b)
Fig. 11.4. (a)AGC circuit; (b) diode characteristics.
178 D-C and Low-frequency Designs

r------.. . . .--o Vee

(b)
Figure 11.5

used as the two-terminal shunting element. Most of the AGe action is in the
region near saturation where the slope of the transistor output characteristic is
changing most rapidly.
The foregoing are three simple examples of the application of the two types of
control. The number of ways in which these types can be applied is limited only
by the imagination of the designer.
Design Example. Figure 11.6 is an example of an AGe circuit using a shunt-
ing diode (Dl). Ql and Q2 are the active elements in a low-noise low-level ampli-
fier, designed to operate with a source resistance of from 500 to 50 kilohms. Q3
controls the bias current to D 1 ; it obtains its base drive from the rectifier D2 and
associated low-pass filter. Q5 and Q6 form a high-level amplifier, while Q4 is an
emitter-follower whose function is to present a high resistance to the AGe net-
work. The specifications of this amplifier when driven from a 500-ohm source are
given below:
Temperature-compensated (open-loop) gain. . . . . . . . . . . . . 97 db
AGe range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 db
M~mum ?utput .signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 volt
Maxtmum mput SIgnal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mv
F (noise figure). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ~6 db
10/-lf ..J....+
35v d-C-J:-
47K

1N659
+ +I
-
+25v doc

l/-1 f
100 K 6_8K 15 v doc

1N659

0_1
RE 75v
22 K
disk

Q6
2N1309

disk
150 K
0_1
470K 0_0027
75v l/-1f 1+
disk
disk 6v doc

All resistors 1/2 watt 5% 0.1


4.7 K 10 K 75v
disk
~
1N659
Fig. 11.6. Low-noise low-level amplifier.
12
Low-frequency Harmonic Oscillators

The principle of oscillator circuits using vacuum tubes is well known, and a
number of the techniques which apply to vacuum-tube circuits are applicable to
transistor circuits. This chapter reviews some of the fundamentals of oscillator
circuit design and theory, and shows how these are applicable to designs using
transistors.
The term harmonic oscillators may be applied to those oscillators which are op-
erated in such a way as to produce a reasonably sinusoidal output voltage. In
these circuits, a resonator is usually employed to fix the frequency of operation.
The resonator acts to make the output sinusoidal, even though the current or
voltage applied to the circuits may be highly distorted.

12.1. CRITERIA FOR OSCILLATION

It will be helpful to examine some of the basic concepts of a sine-wave oscilla-


tor. Figure 12.1 shows that such an oscillator is composed of an amplifier to pro-
vide power gain, a resonator to fix the frequency of oscillation, and a feedback
network to provide oscillation. If this arrangement is to operate as a stable oscil-
lator, the gain around the closed loop should be unity. If a gain greater than this
exists, the output will increase until the loop gain is reduced to unity, because of
the limiting which will occur at high levels.
It can also be shown that the phase shift around the closed loop of Fig. 12.1
should be zero. If the phase shift is not zero, the frequency of oscillation will

Pi .1 Amplifier I GPi
~----~--~
1 Resonator 1~-.--~--~
Po
1 gain =Gil loss P~ 1 Power to
load

1Feedback network l Pi +pr


'--------------11 loss PL' 1

Fig. 12.1. Elements of an oscillator circuit.

180
Low-frequency Harmonic Oscillators 181

change in such a way as to make it zero. These two conditions of unity power
gain and zero phase shift around the loop are known as Barkhausen criteria for
oscillations.

12.2. FEEDBACK PATHS

The feedback path class of oscillators embraces those that require an external
path to couple the energy from the output to the input. Only a general discussion
of these circuits will be given here, to show some of the various configurations which
may be used to obtain oscillations.
Figure 12.2 shows several circuits which employ LC circuits as resonators to fix
the frequency of oscillation. These circuits are shown using PNP transistors; how-
ever, NPN transistors are equally suitable if the biasing potentials are reversed.
In Fig. 12.2a, the resonant circuit is in the collector, and the feedback is obtained
by transformer coupling from the collector to the base. In Fig. 12.2b, the resonant
circuit is placed again in the collector; however, this time the feedback is taken to
the emitter. In this case, it is necessary to use a somewhat larger turns ratio than
that in Fig. 12.2a, since the input impedance of the emitter is lower than that of
the base.
The circuit of Fig. 12.2c is the same as Fig. 12.2a except that the tank circuit is
a-c coupled to the collector with a coupling capacitor.
The circuit of Fig. 12.2d is similar to that of Fig. 12.2b except that the coupling
from the tank is accomplished by using the tank inductor as an autotransformer.
The capacitor is needed only to block the d-c potential which exists between the
collector and emitter.

Fig. 12.2. Some basic transistor oscillators using external feedback.


1 82 D-C and Low-Frequency Designs

-E

Fig. 12.3. Bridge-type oscillator.

The circuit of Fig. 12.2e is similar to those of 12.2a and 12.2d except that the
coupling in this case is obtained through tapped capacitors instead of a tapped
inductor. This technique results in a voltage and impedance transformation similar
to that resulting from a tapped coil.
The circuits shown here are only a representation of a few of the many circuits
which have evolved. Other types of external feedback oscillators, which produce
a sinusoidal output but do not employ an LC resonant circuit, are the bridge and
phase-shift oscillators.
A bridge oscillator in one of its simplest forms is shown in Fig. 12.3. Ql is
operated as a grounded-base amplifier with a very high collector load so as to give
a large voltage gain. Q2 is used as a grounded-collector amplifier (emitter-follower)
to couple this high-impedance collector to two feedback paths. One feedback path
to the emitter is broad-tuned and is regenerative, and the other path is to the base
and is made up of a bridged-T network. The feedback through this network is all
degenerative; however, the bridged-T has a sharp null at one frequency which
reduces the degenerative feedback and causes oscillation to occur at this frequency.

Fig. 12.4. Phase-shiff-type oscillator.


Low-frequency Harmonic Oscillators 183

The nonlinear element shown in the positive-feedback path provides a limiting


action, so that the transistor can operate in a class A condition.
A phase-shift oscillator can be built using a similar circuit. In Fig. 12.4, two
transistors are used again, one (Ql) to obtain high voltage gain and one (Q2) to
obtain an impedance match. In this circuit the feedback is applied to the base of
Ql. A phase shift of 180 is obtained in three RC networks, and the additional
0

180 required for oscillation is obtained through the grounded-emitter amplifier Ql.
0

12.3. DESIGN DATA

In order to illustrate the design of a transistor oscillator, a procedure for the design
of a typical circuit is given:
As stated before, the Barkhausen criteria require that the power gain around the
loop be unity and the phase shift around the loop be zero. These two factors are
easily separated in oscillators having only external feedback loops. A block
diagram of a feedback oscillator is given in Fig. 12.5. The amplifier has been
converted to an equivalent Th6venin voltage generator with a voltage e1Kmin series
with a resistance, r o, the output impedance of the amplifier which is considered to
be part of the feedback network. The input impedance of the amplifier is con-
sidered infinite, since any reactive component may be canceled at anyone frequency,
and the resistive component may be considered as a part of R. The phase angle,
B, is assumed to be a function of all external parameters, such as temperature and
voltage. The primary factors affecting the stability of the frequency of operation
now become cp(j), the resonator phase-shift characteristics as a function of fre-
quency and B(s), the variation of phase shift of the amplifier due to external effects.
For stable frequency operation, it is desirable to make dBjds as small as possible
and dcpj df as large as possible.
The factors influencing cp(f) are the geometry and element values of the frequency-
controlling network. The choice of the network geometry is limited only by
practical values of K and roo For most transistors, ro is too large unless a trans-
former is used, in which case the ratio K2 jro remains constant for any transformer.
This is true because the reflected impedance of a transformer varies as the square
of the voltage ratio. Thus, the amplifier and transformer may be characterized in
terms of Band K2jro = A.

r-------------l ,------------------,
I I I + I
I + I I ro II
I
: el : I R I
I I I I
~--~I~ ~----~I~I------~ :
I Amplifier I I Feedback network (k, cf» I
L ____________ ~ L ________________ ~

Fig. 12.5. Block diagram of feedback-type oscillator.


184 D-C and Low-Frequency Designs

r-------------l
I -jX 2 I
+ r----AVV~----~I-J I
I
I
IL _____________
Resonant element I
....l
R

. Fig. 12.6. Simplified schematic of feedback oscillator.

To illustrate this method for designing a practical oscillator, the network shown
in Fig. 12.6 is analyzed as follows: Let
jX =jX1 - jX2

Then R
el = e2 ------'----- (1)
R + Rl + jX + ro

or ~ = KI.Jl = Kltan-1 X (2)


e2 L R + ro + Rl
Here, series resonance, dcpjdj, increases as (R + ro) decreases. The minimum
value of (R + ro) that will permit oscillations is found as follows: For X = 0,

el = ro + Re2
Rl + R
Re1K
= --~----=-
ro + Rl + R
But K2jro =A
or K = ro1l2A1I2
Therefore, Rro1l2a1l2 = ro + Rl + R
or R = ro + Rl (3)
ro1l2A1I2 - 1
ro + Rl
from which R + ro = ro:rl.
112.4112 - 1 + ro

R + ro is minimum when d(R + ro) = 0, or when


dro
2ro3!2A1I2 - 3ro - Rl =0 (4)
By substituting Rl as determined from the resonant element chosen for the
oscillator and A as determined for the amplifier, ro can be determined from Eq. (4).
When ro is known, then the correct turns ratio of the transformer can be determined.
If ro and R could both be made zero and still maintain oscillations, the change
in frequency produced by a small change in amplifier phase shift, M, would be

tJ.j= M/o for M small (5)


2Q
Low-frequency Harmonic Oscillators 185

where

1
and for the resonant element
!o = yLC

For values of (ro + R) other than zero, Eq. (5) must be modified by making
Q= Xl
Rl + R + ro
13
Frequency Response and Stability
of Feedback Amplifiers

Feedback techniques are commonly used in transistor amplifiers to reduce the


effects of transistor parameter variations on gain and distortion, and to improve
the characteristics of the amplifier.
This chapter describes the importance of frequency response of a feedback
amplifier with respect to stability against oscillation, how to obtain the frequency
response of the amplifier from the transfer function, and how to shape the response
in order to ensure a stable amplifier.
General Stability Criterion. Consider the block diagram of a feedback ampli-
fier (Fig. 13.1), where
A = voltage gain of the amplifier without feedback
CPa = phase shift of amplifier
f3 = fraction of output voltage fed back to the input
cP = phase shift of feedback network
At the frequency of operation, the amplifier is assumed to have an inherent 180 0

phase shift, and generally the feedback network will have zero phase shift; hence
the gain can be computed as follows:
Input voltage to the amplifier = v = V(in) - f3v o
Output voltage = Vo = A(v) = A(V(in) - f3v o)
A
Gain = G=~
V(in) 1 +AB
(1)

Feedback network
(3 /tPb

Figure 13.1

186
Frequency Response and Stability of Feedback Amplifiers 187

Unfortunately, the amplitude and phase relationships of the amplifier and feed-
back network are functions of frequency, owing to the use of coupling and decou-
pIing capacitors, transformers, and to the frequency dependence of transistor
parameters, etc. Also, at some frequency it is possible for the loop phase shift (i.e.,
the phase shift of the amplifier plus the feedback network) to be 360 and if a signal
0
,

of this frequency is applied to the amplifier, the voltage fed back will be in phase
with the input voltage and will therefore add to it. The resulting gain will be
G = A/(l - Af3) and is effectively increased. This is called positive feedback.
If the loop gain (i.e., gain of the amplifier times the feedback fraction) is greater
than one at this frequency, and no signal is applied, any noise or transients in the
power supply appearing at the input with the same component of frequency will
be amplified, and the voltage fed back will be greater than the original signal. This
feedback voltage is amplified and fed back, etc., the output voltage getting progres-
sively larger until some component in the circuit saturates, whence the output
voltage will be stabilized. Thus we are getting an output voltage for no input signal,
and the amplifier is therefore oscillating.
For stability against oscillation, two conditions must be satisfied:
1. When the loop gain (Af3 product) is greater than one, the total loop phase
shift must be less than 360 0

2. When the loop phase shift is 360 0


, the loop gain must be less than one.
The amount by which the phase shift is less than 360 at the unity-gain frequency
0

is called the phase margin, and the amount of gain less than one at the 360 fre- 0

quency is called the gain margin. The magnitudes of these quantities give an
indication as to how stable an amplifier is and will depend on the application of
the amplifier. For example, a linear amplifier requiring good stability would
require a gain and phase margin of at least 10 db and 50 respectively, but a pulse
0
,

amplifier of limited bandwidth, in order to have a good transient response, would


require less than this.
Relationship between the Transfer Function and the Frequency Response.
Consider the network in Fig. 13.2. The transfer function of the circuit is as shown.
Vo R 1
(2)
V(in) - R + l/jwC - 1 + l/jwCR
The response of this circuit is shown in Fig. 13.3. It can be seen that the asymptote
of the frequency-response curve (the slope of which is 6 db/octave or 20 db/decade)
can be used as an approximation to the actual frequency response, with negligible
error.
The phase response can also be calculated from the transfer function, as is shown
in Fig. 13.4. It can be seen that the phase response can also be approximated to
a straight line, of slope equal to 45 /decade.
0

Table 13.1 shows the approximate amplitude and 0


phase response of common transfer functions. c
The use of this table may be illustrated by the V(in) R
following section of a transistor circuit (Fig. 13.5).
Assuming that the output impedance of the preceding
stage and the input resistance of the following stage Figure 13.2
188 D-C and Low-Frequency Designs

Table 13.1

Transfer function Amplitude response Phase response

db

Phase
6 db/octave,
lead
45°
G=K(1 +jwCR)

0 w =-.L logw 0 1
w=- W=-
10
CR CR CR

db
0

1 0
logw
G =K (1 + jwCR)
45° 45°/decade
Phase
6 db/octave lag
90°

db 1
0 w=CR

Phase
lag
45°
G=K(I+_l )
jwCR

20log lO K 90°

1 logw
w=CR

db 90°
20log lO K
0
1 log w
G=K_l_ W=-
1+_1_ CR
jwCR

6 db/octave

0 1
W=-
CR
Frequency Response and Stability of Feedback Amplifiers 189

10

..c
"0
20
~I
l5 ~
.~
Actual response
~~

b.O
.2
::: I
Errors between actual response
0
30
(\J and asym ptote are:
1
when w = 2CR error = 1 db
1
W=- error =3 db
40 CR
w=L error = 1 db
CR

50L---------____-L____________ ~ ______________ ~ ___

Figure 13.3

100
---- / Actual Jhase response
en 80 ...::.....
~
Q)
~
b.O
Q)
"0 60
-ci
ro
" Straight line approximation
~ 40 """'- Slope =45 0 jdecade

~"
Q)
en
ro Max. error=5r
..t:
c... 20

a I I
~ I
1 10 w
10CR CR CR
Figure 13.4

Figure 13.5
190 D-C and Low-Frequency Designs

are essentially resistive at the frequencies concerned and that these frequencies are
well below the hte cutoff frequency of the transistors, analysis of the circuit yields
the following transfer function.

G = Av I + l/jWC~Rl
1 + (hreRl + Ro + hie)/;wC1(Ro + hie)Rl
1 + jwC2R 2
(3)

where Av = mid-frequency voltage amplification. The frequency response is as


shown in Fig. 13.6.
The phase-angle diagram may be approximated in the same way.
Shaping the Frequency Response to Ensure Stability against Oscillation.
It will be noticed in the phase response of the RC network of Fig. 13.2 that at
some frequency the phase angle reached 90 and if there were two such networks
0
,

in a circuit, the phase angle would reach 180 the fall in amplitude response then
0
,

being 12 db/octave. This together with the 180 phase shift in the amplifier could
0

result in oscillation, if the loop gain were greater than one at this frequency. Con-
sequently, it is important that when the loop gain is greater than one, the response
should be controlled so that it does not rise or fall at a rate equal to or greater than
12 db/octave; and, in general, 9 or 10 db/octave is the maximum allowable for
good stability.
At the low-frequency end, the fall in response is generally due to coupling and
decoupling capacitors, together with any transformers in the circuit. One com-

Rising and
falling responses
at 6 db/octave cancel
and level response
20 log Au

I
I
I

w=_l_ log frequency


C1R1

(.oJ = hfeRl + Ro+ hie


C1(Ro+hie)R1

Figure 13.6
Frequency Response and Stability of Feedback Amplifiers 191

I
I
I
I
I
I
I
'- 12 db/octave
I
I
I
I
I
I
I
log frequency

Figure 13.7

monly used method of stabilizing is the dominant-lead technique. Using this


method for low-frequency shaping, one time constant is chosen to have its break
frequency just below the lowest used frequency in the amplifier, the response there-
after falling at 6 db/octave until the unity gain frequency has been passed. Mter
this point has been reached, the other time constants may cause the response to
fall at any rate, while still maintaining a stable amplification. In high-Ioop-gain
amplifiers, this technique is often difficult to apply, since it requires a very wide
frequency response, resulting in large decoupling capacitors, etc., and transformers
with high primary inductance. In these cases the time constants are chosen so that
the response falls at a maximum of9 db/octave as illustrated in Fig. 13.7.
Plotting the actual response curve, it can be seen that the response cannot
possibly be greater than 12 db/octave, and by careful choice of W1, W2, etc., the slope
can be controlled to 9 or 10 db/octave (Fig. 13.7).
At the high-frequency end of the frequency response, the chief causes of the fall
in response are high-frequency response of the transistors and transformers and
stray capacitances. Similar techniques to those used at the low-frequency end may
be used, but, in general, these require the use of additional shaping networks, as
illustrated in Fig. 13.8 (see next page).
192 D-C and Low-Frequency Designs

w = --=--c=-=1----=--c 1
0r-______C2~(_Rrl+_R_2~)_____w_=__-Cr2-R--~2--------IO-g~w~

Slope =6 db/octave
I
I
I
I
I
I
I
I
I
R2
201og-
R 1 +R 2
V(out)
(a) 20 loglo ---V:-' db
(in)

20 loglo. gain
____________ l'y--Response
I " without
: \ feedback
I "
\

3-db frequency of
rmp, without feedback

o logw
I w = C21R 2

hie + !:,hRL
(b)

Figure 13.8
14
Operational Amplifiers

By the use of feedback elements, certain amplifiers may be made to produce an


output which is proportional to the algebraic sum, the time derivative, the integral
with respect to time, or simply a multiple of the input signal voltage or other mathe-
matical operations. Such designs are widely used as building blocks for analog
computers. Because of their mathematical versatility they are called operational
amplifiers.
Operational amplifiers must meet these requirements:
1. The gain (without feedback) must be very large.
2. The passband must be wide, often extending from d-c (zero frequency) to
tens of kilocycles.
3. The phase-gain characteristics must allow for a strong negative-feedback
loop around the amplifier.
4. D-c drift must be minimized.
5. The amplifier must have either a very low output impedance and very high
input impedance, or vice versa. Low output impedance is the more popular,
but low input impedance has definite advantages for transistor amplifiers.
When operational amplifiers are used in analog computation, the system may be
represented as in Fig. 14.1.
The amplifier (represented by the triangle) has a gain of A (open loop without
external feedback). e(in) and eo represent the input and output signals, respectively.

Summing
point
~ if
~

e(in) e(out)

1 -
Figure 14.1
1
193
194 D-C and Low-Frequency Designs

e. represents an error signal that is applied directly between the amplifier and
ground.
The output signal is the product of the error signal and the gain of the amplifier.
If the gain of the amplifier is sufficiently large (A = 1()4 to 106), e. will be small
compared to e(in), and the summing point is assumed to be at zero or ground
potential. The eo connected through Z, tends to force the summing point to main-
tain a small potential close to ground.
An example will serve to illustrate the above point. Suppose the amplifier has
a gain of -106 , an output swing of -20 volts, and an input signal of 1 volt. The
gain ofthe system eo/ e(in) = - 20 volts/ 1 volt = - 20. The error signal = - eo/ - A =
20/106 = 20 MV. Thus, e. is 50,000 times smaller than e(in). ii =
(e(in) - e.)/Zi -
e(in/Zi, and (e. - eo)/Z, - -eo/Z,. If no current is assumed to flow into the
amplifier (ia = 0),
(1)

Since the summing point is at ground, the input impedance of the system equals
Zi. In our example, for a gain of - 20 we could assume values of 100 kilohms for
Zi and 2 megohms for Z,. Thus, the gain A = (2 X 106)/105 = -20, and the in-
put impedance Zi = 100 kilohms.
Note that, in Eq. (1), Z, and Zi may be complex impedances and are not limited
to pure resistance as in the example. Two examples will be given to show how
integration and differentiation are possible with this type of amplifier. If Z, is
represented by a capacitor C, and Zi by a resistor R, then from Eq. (1) (using the
Laplace operator S = (J +jw),
A =_ l/CS = __1_
R RCS
Noting that I/S corresponds to integration and A = eo/e(in»
1 (t
eo =- RC )0 e(in) dt

Thus we see that the output voltage is a constant (1/RC) times the integral of the
input voltage. Differentiation is performed in a similar manner. Assume that the
two impedances have been interchanged from the previous example; again, using
Eq. (1),
R
A =- I/CS =- RCS (2)

Noting that S corresponds to differentiation and A = eo/e(in),


_ RC de(in)
eo - - -;It (3)

Thus we see that the output voltage is a constant multiplied by the time derivative
of the input voltage.
The amplifier shown in Fig. 14.2 is a chopper-stabilized amplifier that can be
used as an operational amplifier. This amplifier is shown in block-diagram form in
Fig. 14.3.
e(in)
.
13K
26
" , 1/
47 K

r--I (
i l.: ~ ,~,
2N498

0- ..
Input
"" \... "'>', ( I I , \~I./ I ~nn <~--L..- « f v'\LI~/j:J
I Output

10K

Rl
l $ 4:l0 K $l.lMLj~ >11 J\/I >51OQ~ + I UU 1
180 K _
-48v

Chopper amplifier
r-------------------------------,
I
I 0.02 +48v I
I C2 AT" p.f.,... 150 K I d·c power requirements
1°.G24h-
I p.f -
100 v-d::-
-
I with 10 K load
I I Output +20v -20v
I I + Supply current 14 ma 6.4 ma
I I - Supply current 12 ma 8.7 ma
I I
I I
I I
I I
I I

~
I
I :G
: 400 cps 6.3v a·c
-= O.lp.f
I
II
'0
V. I ' I
I _________________________________
L Airpax 2300 I ~

Fig. 14.2. Chopper-stabilized d-c operational amplifier.


196 D-C and Low-Frequency Designs

C1
e(in)o----_-----ir---------I
doc blocking >-----<) e(out)
capacitor

Low-pass network

Figure 14.3

The input signal e(in) is composed of a d-c level with a-c information superim-
posed on it. The circuit shown in Fig. 14.3 consists of amplifier 1 which amplifies
the low-level d-c portion of e(in), and of amplifier 2 which amplifies both the a-c
portion of e(in) and the output from amplifier 1. Both I and 2 are d-c amplifiers.
Amplifier 1 is a mechanical chopper amplifier having excellent drift characteris-
tics and a high gain, but a limited bandwidth. Rb R 2 , and C2 form a low-pass
filter that blocks the a-c signal to this amplifier. The output from amplifier 1 is
large enough so that any drift in amplifier 2 will be small in comparison to the
signal. Gain of the d-c signal is A 1A 2 .
C1 prevents any direct current from reaching amplifier 2, allowing only alternat-
ing current to pass. Thus, the a-c gain of the circuit is A 2 • Amplifier 2 is a d-c
amplifier whose drift characteristics are not quite so good as those of amplifier 1,
but it has a larger bandwidth.
The circuit shown in Fig. 14.2 has both excellent d-c stability and a wide band-
width. The d-c gain of this circuit is greater than 120 db, while the gain at 10 kc
is 45 db. A curve of the typical frequency response of the amplifier is given in
Fig. 14.4.

140
fl
120

.0 100
~

"
"'0
c:
.~ 80
c.. ..............

'"
o
-'<:? 60
13)
c..

'"" ~ ~
o 40

20

a '"10.0
0.01 0.1 1.0 100.0 1 kc lOkc 100 kc 1,000 kc
Frequency
Figure 14.4
15
Low-level Audio Stage Analysis

One of the most-used circuits in transistor applications is the cascaded common-


emitter audio amplifier. This circuit performs a variety of functions, is fairly easy
to design, and gives good performance.
The function of a low-level amplifier is to raise a signal level from the millivolt
range to a workable level of several volts. For example, the input signal may be
derived from the output of a piezoelectric crystal, while the output may be required
to drive a power amplifier.
In the examples of the two- and three-stage amplifiers that follow, the transis-
tors are used in the common-emitter (CE) configuration. In a cascade of similar
stages, the CE connection is the only configuration that gives both voltage and
current gain. The common-base (CB) and common-collector (CC) configurations
offer only voltage gain and current gain, respectively. However, these configura-
tions are often useful for matching impedances where the CE stage would not
function properly.
Stages are capacitance-coupled for a-c operation and d-c stability. Class A
biasing is most often used, because it allows the output to follow the input, whether
the input excursion is plus or minus.
Bias currents and voltages are selected such that they are large compared with
the a-c signal. In small-signal operation, the transistor parameters are measured
at given bias levels and are assumed to remain constant as the signal causes the
operating point to make small excursions on either side of the bias point. With
correct biasing, class A operation allows for linear operation of the a-c signal; dis-
tortion is usually kept to a fairly low value.
A typical single-stage amplifier circuit is shown in Fig. 15.1. In the following
analysis, all power supplies and capacitors are considered to be short circuits to
a-c signals. Figure 15.2 shows the a-c portion of Fig. 15.1. Resistors Rl and R2
form a parallel combination of RA , while Rc and RL may be replaced by R B • RL
may be the input impedance of the next stage or an external load, but must never-
theless be taken into account. Rg and RA form a voltage-divider circuit that
attenuates the signal before it reaches the transistor. Thus, it can be seen that the
bias resistors and the generator affect the gain of the circuit.
The following analysis of a two-stage a-c coupled amplifier demonstrates how
197
198 D-C and Low-Frequency Designs

Figure 15.1

Figure 15.2

~------~--------~------~r-----------o+Vc
12v

Fig. 15.3. Twa-stage cascaded CE audio amplifier.

No.1 No.2
r-----------l . r-----------,
h. 1 Za
,e 1- hie
~----~~v I
I
I
2.86K I
I

-
Ri

L- _ _ _ _ _ _ _ _ _ _ _
I
I
I
I
1
...J1
4.4 K

~ _ _ _ _ _ _ _ _ _ _ _ .J

Fig. 15.4. The a-c equivalent circuit of a two-stage cascaded CE audio amplifier.
Low-level Audio Stage Analysis 199

the total amplifier gain may be calculated by the use of equivalent circuits. The
d-c biasing of each stage is also illustrated.

15.1. EQUIVALENT CIRCUITS

The first step in performing an analysis of the capacity-coupled CE amplifier of


Fig. 15.3 is to reduce the circuit to its equivalent circuit. This consists of remov-
ing the battery and replacing it with its internal impedance, if any, and eliminating
those resistors which are bypassed by capacitors. Also, the base bias resistors are
replaced by their Thevenin equivalent circuit, and the coupling capacitors are
shorted if their reactance is sufficiently small. The a-c equivalent circuit of Fig.
15.3 is given in Fig. 15.4.
The Thevenin equivalent (parallel combination) of Rl and R2 in Fig. 15.3 equals
2.86 kilohms, and of R5 and R6 equals 4.4 kilohms. These values and the load-
resistor values for R3 and R7 are inserted in Fig. 15.4.

15.2. DETERMINATION OF h PARAMETERS

The h parameter values for the 2N338 transistor are obtained from the manu-
facturer's data sheet and converted to the common-emitter values, corrected for
the operating conditions. The conversion formulas are obtained from the equiva-
lent circuit section.
The operating point for the second stage is set by the bias and load resistors at
VCE = 5 volts, IE = 6 rna. The operating point for the first stage is set at
VCE = 5 volts and IE = 1 rna.

15.3. OPERATING POINT AND PARAMETER CORRECTIONS

To determine the d-c operating points, the first and second-stage circuits are
drawn separately to illustrate the various direct currents and voltage drops across
the resistors (Fig. 15.5). The operating points and load lines for the two stages
have been plotted in Fig. 15.6 on the static-output characteristic curves for the

10.4v 8.6v

12v 12v

1.6 v 3.4v

(a) First stage (b) Second stage


Fig. 15.5. D-c voltages and currents of two-stage CE audio amplifier.
200 D-C and Low-Frequency Designs

2N338 transistor. Knowing the IE and VCR values for the two stages, the hybrid
parameter correction factors (shown in Table 15.1) are obtained from the transis-
tor data sheet. (Data sheets on the 2N338 transistor do not show these correction
factors, and so it is necessary to use those given for the 2N335, which has similar
characteristics.)
First-stage CE Hybrid Parameters

hie = 1 +hibhfb = 0.01


50
= 5,000 0 hms
h - hi~ob _ h = 50 X 0.2 X 10-6 _ 300 10-6 = 700 10-6
re - 1 + hfb rb 0.01 X X

h - -hfb _ -(-0.99) _ 0.99 - 99


fe - 1 + hfb - 1 - 0.99 - 0.01 -

h
oe = 1 +hobhfb 0.2 OX.011O-6 = 20 X 10-6 = 20 p.mhos
Second-stage CE Hybrid Parameters

h ib
ie = 1 +h hfb = 0.0086
11
= 1,280 ohms
h - hibhob h -
re - 1 + hfb - rb -
11 X 0.72 X 10-6 _ 600 X 10-6
0.0086
= 320 X 10-6

-hfb 0.9914
h,e = 1 + hfb = 0.0086 = 115
h hob 0.72 X 10-6
oe = 1 + hfb = 0.0086 = 84 X 10-6 = 84 p.mhos

15.4. GAIN AND OUTPUT POWER


From the above information, it is possible to calculate the power gain, power
output, and transducer gain for the CE circuit shown in Fig. 15.3. The power gain
for a CE amplifier is equal to the product of the current gain and the voltage gain.
In the analysis, it is necessary to start with the second or output stage and work
toward the first stage, because the input resistance of the second stage depends on
its load resistance. The load resistance of the first stage is dependent on the input
resistance of the second stage.
Second Stage. Referring to Fig. 15.4, the power gain of the second stage is
equal to

and

Therefore,
Low-level Audio Stage Analysis 201

Table 15.1. h-parameter Values and Correction Factors for 2N338 Transistor

Correction Correction
Corrected parameters
Parameter factor for factor for
Parameter value from second stage, first stage,
data sheet IE2 = 6 rna lEI = 1 rna Second First
Vcs = 4.4 volts VCB = 4.4 volts stage stage

hib 50 ohms 0.22 I II ohms 50


hrb 300 X 10- 6 2.0 1 600 X 10- 6 300 X 10-6
h{b -0.99 1.0015 1 -0.9914 -0.99
1 + h{b 0.01 0.86 1 0.0086 0.01
hob 0.2 X 10-6 3.6 1 0.72 X 10-6 0.2 X 10-6
mho

2N338 at 25°C
14
200 jJ.a
13

12

11
Vee ~
- - - = 10.25 ma-
RL +RE 10

9
'"
E
...,. 125 jJ.a
c 8
~:oJ
U
~ 7 /Stage No.2 operating
.8 100 J.l.a
~
u I point
0 6
u
I <0
......G 5
I C;>O'/,'
I
I : I / J .(9-s jJ.a
__________ _ 75

4 L~--------~------~~
I ~(9~
I q <?
I
3 I
I
: /Stage No. ~ operating
II pOint

o 2 3 4 5 6 7 8 9 10 11 12 13 14
VeE' collector· emitter voltage
Fig. 15.6. Static output characteristic curves for 2N338 transistor showing load lines and
operating points of two-stage CE audio amplifier.
202 D-C and Low-Frequency Designs

115
84 X 10-6 X 700 +1
= 108 = second-stage current gain
*Ri2 = hie + (hoehie - hrehre)R7
1 + hoeR7
Ri2 = 1,280 + (84 X 10-6 X 1,280 - 115 X 320 X 10-6)700
1 + 84 X 10-6 X 700
Therefore,

G2 = (108)2 X 17~~0
,
= 6,700 = power gain of second stage
Interstage. Not all the first-stage output current, h, flows into the second-
stage input, 14 (Fig. 15.4); therefore, the ratio of 14 to fa or the current attenuation
produced by the inter stage network must be known. The interstage network is
given in Fig. 15.7a.
The 6- and 4.4-ki10hm resistors in parallel give a combined value of approxi-
mately 2.5 kilohms, as shown in Fig. 15.7b. Also, 2.5 kilohms and 1,220 ohms in
parallel provide an equivalent resistance, Req ~ 820 ohms. Since the voltages
across both resistors are the same, then
1.2214 = 2.5(fa - 14) = 2.5fa - 2.514
and 3.7214 = 2.5fa
Therefore, the interstage current gain, which here represents an attenuation, is

14 = 2.50 = 0.670
13 3.72
First Stage. The equivalent resistance, R eq, from above, forms the a-c load re-
sistance of the first stage. The current gain is
99 99
= 20 X 10-6 + 820 + 1 = 1.016 = 98
• From standard h-parameter equations, input impedance = Zi = hie - h'ehreRd(l + hoeRL);
current gain = Ai = h'e/(l + hoeRL)'

-
is
-i4
-- is

-i4

R~ 16K 144K t R, K
.1.22 R eq -
is - i4 t
2.5K
Ri2
1.22 K

(a) Basic interstage network (b) Simplified network

Fig. 15.7. Interstage network of a two-stage cascaded CE audio amplifier.


Low-level Audio Stage Analysis 203

The input resistance is


Ril = hie + (hoehie - hrehre)Req
1 + hoeReq

R. = S,OOO + (20 X 10-6 X S,OOO - 99 X 700 X 10-6) 820 = 494 k'l hm


tl 1 + 20 X 10-6 X 820 . lOS

Pre-First Stage. It is also necessary to find the current amplification (attenua-


tion) and input resistance to the resistor preceding the first stage. This is the 2.86-
kilohm Thevenin (parallel) resistance of Rl and R2 forming the base bias voltage-
divider network for the first stage (see Figs. IS.3 and lS.4). The pre-first-stage
circuit, excluding the source voltage generator, is shown in Fig. IS.8.
The pre-first current gain is

(A ) 12 2.86 2.86 0 366


i prestage = 11 = 2.86 + 4.94 = 7.80 = .

The input resistance is


2.86 X 4.94
R
i = 2.86 + 4.94 = 1.8 k'llams
h

Total Power Gain of the Two-stage Amplifier. The total current gain of the
two-stage amplifier (Fig. IS.3) can be found by multiplying all the individual gains.
The total current gain is

(Ai) total = ~: = (0.366)(98)(0.670)(108) = 2,S60

The total power gain is

Ap = (2,S60)2 1~~gO = 2,S60,000


Ap = 2.S6 X 106 = 64 db
Therefore, the two-stage amplifier (Fig. IS.3) has a total power gain of 64 db.
Power Output. Continuing the analysis, the power output must be calculated.
By using the source values shown in Fig. IS.3, that is, a generator (source) imped-

A _i 1 _i2

R'~ 1286K Ri -
1.8 K

B B
Fig. 15.8. Pre-tirst-stage circuit. Fig. 15.9. Transducer input circuit.
204 D-C and Low-Frequency Designs

ance, R g, of 1,100 ohms, and a generator (source) voltage of 0.010 volt (10 mv),
the transducer input circuit will resemble the circuit shown in Fig. 15.9. From
this circuit, it can be seen that
v: 0.010 0.010
Ii = R g :' Ri 1,100 + 1,800 = 2,900 = 3.45 p,a
The input power supplied by the generator to the amplifier is

p(. )
on
= (11)2R· = (R V:+g2R·Ri)2
0
.
g

P(in) = (3.45)2 X 10-12 X 1,800 = 11.9 X 1,800 X 10-12


P(in) = 0.0214 p,w = input power
The input power multiplied by the power gain gives the amplifier output power,
that is,
p(out) = P(in0-p = 0.0214 X 10-6 X 2.56 X 106 = 0.055 watt
Therefore, p(out) = 55 mw
Transducer Gain. The transducer gain is defined as the ratio of actual power
supplied to the load, to the power generated by the signal source. When compared
with the total power gain of the amplifier, it is a measure of how efficiently the signal
source is being used.
If the input resistance of the amplifier exactly matched the signal source resist-
ance, maximum power transfer from the signal source to the amplifier would be
obtained, and Ri would equal R g • The power available at the transducer would
then be
E 2 (0.01)2 10-4
Pgen available = 4R(J =
g
---,---o.-----::-:-::-_=_
4 X 1,100 4.4 X 103 = 0.0226 mw
The transducer gain would then be

Transducer gain = 55 X 10-3


p(out)
P gen available 0.0226 X 10-6 = 2.43 X 106 = 63.8 db
The transducer gain is nearly equal to the power gain; therefore, the generator
is being used efficiently because the generator impedance nearly matches the ampli-
fier input impedance.
Voltage Gain. All the necessary information is known for the voltage gain:

Av = eo(across R 7) = Ai R7 = 2,560 X 700 = 998


e(in>Cacross R i ) Ri 1,800

1 5.5. A COMPLETED DESIGN

A complete amplifier design using the 2Nl565 is given in Fig. 15.10. Its per-
formance is given in Table 15.2.
Low-level Audio Stage Analysis 205

, . . . - - - -......- - - -.....- - -.....- - - - - - 1 1 ' - - - -.....- - - - - - 0 + Vee


25v

Component values: Operating conditions:


RL = 560 ohms Temperature range: -55 to + 125"C.
Rl = 16 kilohms Output voltage swing of stage: 2 volts peak to peak.
R2 = 6.2 kilohms
R3 = 1.6 kilohms
R4 = 1.0 kilohm
Ql, Q2, Q3 = 2NI565

Notes: Cl and C2 depend upon frequency response desired. Amplifiers were tested with
Cl = 10 Mf and C2 = 100 Mf.
Figure 15.10

Table 15.2. Performance Characteristics at 1 kc

Temperature, "C Typical current gain, db


-55 83
+25 88
+125 91
16
Class A Driver and Output Stages

The most common type of driver for a class B output stage is the transformer-
coupled class A amplifier. The design of such a driver stage is discussed in this
chapter.
Because of the many variables involved in the design of a class A amplifier, it
is difficult to arrive at a completely general design procedure. Consequently, the
design procedure presented here emphasizes circuit analysis rather than circuit
synthesis. The primary purpose of the design procedure and design example
presented is to emphasize the variety of factors to be considered in achieving a
reliable circuit design.

16.1. THE IDEAL AMPLIFIER

An understanding of the basic class A configuration is of fundamental importance,


but since many textbooks cover the subject, only a cursory explanation will be
presented. Figure 16.1a illustrates the basic circuit as it is encountered in most
textbooks.
The a-c and d-c load lines for the basic or ideal configuration are shown in Fig.

+ Vee
_ doc load line

Quiescent operating
point
,r-a-c load line; - Rl1,

VQ ; Vee 2VQ
(b) Collector-emitter voltage
Fig. 16.1. Basic configuration.

206
Class A Driver and Output Stages 207

l6.lb. R£ represents the load impedance reflected to the primary and, conse-
quently, determines the a-c load line. The intersection of the a-c and d-c load lines
is the quiescent operating point (IQ, VQ). Under quiescent conditions, lQ is the
collector current flowing through the transistor, and V Q is the voltage appearing
across its collector and emitter terminals. Thus, the power dissipated in the tran-
sistor under quiescent conditions is VQlQ:
(1)
When an a-c signal is applied, the a-c load line becomes the locus of the transistor's
operating point. In order to achieve maximum symmetrical swing of current and
voltage (neglecting transistor saturation resistance for the moment), the quiescent
point must be located midway between the a-c load-line intersections of the hori-
zontal and vertical axes, as shown in Fig. l6.lb. Since the transistor is assumed
to be ideal, i.e., R(sat) = 0 and 100 = 0, then the maximum power, P~, which can
be put into the transformer as a sine-wave signal is the rms voltage V Q / y'2 times
the rms current lQ/ y'2:

Po' = VQlQ ~ VoolQ (2)


2 - 2

Since the average power supplied to the class A stage is constant at any signal level,
it becomes apparent that the maximum collector efficiency is 50% and occurs only
at maximum signal output.

16.2. THE PRACTICABLE AMPLIFIER

The circuit shown in Fig. 16.2a represents a practical circuit. The obvious
differences between this circuit and the ideal one are the additional resistors and
the capacitor. In a detailed analysis of the circuit, however, many more compli-
cated differences appear. Examination of the load lines shown in Fig. 16.2b reveals
several important considerations which should be taken into account in the design
of a practical circuit.
Circuit Resistance Considerations. Resistors R y , RE!, and RE2 determine the
d-c load line, while R£, R y , and REI determine the a-c load line. The emitter
resistors are necessary to ensure bias-point stability as well as thermal stability.
All the emitter resistance could be bypassed, i.e., REI = 0, and it frequently is, but
since this is to be a general case, REI will be included in the analysis. REI provides
a-c negative feedback which increases the input and output impedances. It may
also extend the lower cutoff frequency of the bypass capacitor C1 . R£ represents
the reflected load resistance, and R y represents the d-c winding resistance of the
transformer primary plus the internal impedance of the power supply. Since R y
serves no useful function, it should be minimized for improved performance.
Another undesirable resistance affecting circuit operation unfavorably is plotted
in Fig. 16.2b as RIC. This is the resistance of the transistor at an arbitrary point
approaching saturation. As a general rule, Rx can be assumed to be two or three
times the saturation resistance specified on the data sheet, since saturation resist-
ance is usually measured with the transistor hard in saturation. The point worth
208 D-C and Low-Frequency Designs

+ Vee

,,- doc load line;


-1

1
1
1
1 Quiescent operating
1 /
point
-1-------
1
I . / a-c load line;
1 I' -1
1
I
I

Vx VQ Vee 2VQ - Vx
(a) (b) Collector-emitter voltage
Fig. 16.2. Practical configuration.

consideration is that, because of the rapid change of the transistor characteristics


when close to saturation, the area to the left of 1/Rx in Fig. 16.2b is unsuitable for
linear operation.
Bias-point Considerations. For maximum symmetrical swing of current and
voltage, the quiescent point must be located on the a-c load line at 1x12, where 1:c
is the current determined by the intersection of the a-c load line with II R x , as shown
in Fig. 16.2b. With such a bias point for a sine-wave signal, the maximum possible
a-c power out of the transistor is the rms voltage (VQ - V:c)/...j2 times the rms
current 1Q10:
(3)

where V Q = VQ - Vx (4)
and VQ = Vee - 1Q(Ry + REi + R E2 ) (5)
If the bias point should shift, the available peak current or voltage would decrease,
and less a-c power could be obtained from the transistor. Figure 16.3 illustrates
the shift in the a-c load line which occurs when 1Q increases to IQ or decreases to
lQ. A well-designed circuit would keep the bias point relatively stable and would
make allowances for shifts which may occur when using standard-tolerance com-
ponents. Allowance must be made for the increased power dissipation in the
transistor which will occur if I Q increases to I Q. Also, the desired a-c power output
of the transistor must be obtainable in spite of a bias-point shift to either l Q or £Q.
Calculations concerning bias-point shifting have been presented in Chap. 7.
Power Dissipation and Thermal Considerations. The instantaneous power
dissipated in any transistor under any circumstances is given by
(6)
If the transistor is not driven into saturation, the contribution of VBEiB to the
Class A Driver and Output Stages 209

Fig. 16.3. Bias-point shifting. Collector·emitter voltage

peak instantaneous power pJ(peak), and to the maximum average dissipation PJ(max)'
is quite small and can usually be neglected.
The maximum average dissipation of a class A stage occurs at quiescent
conditions:
(7)
The peak instantaneous power can be found by expressing power dissipation as
a function of a signal current, and differentiating to determine the value of ic
which causes pJ(peak).
Thus:
(8)

and at that instant


Vee + IQ(Ri - R E2 )
(9)
4(Ri + R y + R El )
Lp I
if and
Ri ?> !o
!o = signal frequency
The significance of PJ(max) and pJ(peak) have been explained in the chapter on
general biasing, Chap. 7. The peak power dissipation described by Eq. (8) will
only occur with unsymmetrical bias. Unfortunately, unsymmetrical biasing can
occur because of a-c load variations, which are common when the load is another
transistor stage. For symmetrical biasing as shown in the basic configuration of
Fig. 16.1, both the peak instantaneous power and maximum average power occur
at the quiescent point.
As explained previously in Chap. 7, a conservative thermal design results from
usmg
(10)
210 D-C and Low-Frequency Designs

Another important consideration which is explained in Chap. 7 concerns ther-


mal stability. A simplified version of Eq. (58) of Chap. 7 which must be satisfied
for thermal stability is

1-
(}T
> v:CC [it~ + RB) (006931
RE '\. CBO
- 1 dhFB\
Q dtJ) +
0.0025 ]
RE (11)

where I Q is the quiescent collector current.


This equation is subject to the restrictions and conditions originally imposed.
Recall that the equation is for silicon transistors (0.0693 becomes approximately
0.0459 for germanium transistors), and that the resistances RB and RE refer to the
equivalent circuit shown in Fig. 7.4 of Chap. 7.
Output Power Considerations. Another important consideration in the de-
sign of a class A driver stage is the a-c power requirement. For a load power of
PL , the power required at the primary of the transformer is

PI.. = PL (12)
'1/
where '1/ = transformer efficiency.
The a-c power output of the transistor has been expressed in terms of the qui-
escent current and voltage in Eq. (3). The portion of this power which will be
delivered to the reflected load impedance, RI.., is

(13)

or P' _ IQ2RI.. (14)


0- 2

Fig. 16.4. Design circuit.


Class A Driver and Output Stages 211

Ri
where 8 = --=-c,-------=-----::,---- (15)
Ri + R + REl
y
Actually, Po = Pi, but because of bias-point variations it is best during the de-
sign of a stage to make P;' larger by an amount PH to ensure that its minimum
value (which occurs during bias-point shifts) will still equal Pi . Thus:
(16)
Transistor and Transformer Considerations. The primary transistor consid-
erations are the current, voltage, and thermal ratings. The transistor should have
a useful hpE at 21Q and a voltage rating of
(17)

16.3. DESIGN PROCEDURE

The design procedure presented is based on the following factors being known:
Supply voltage Vee; its tolerance and internal resistance.
Frequency range.
Ambient temperature.
Load power, PL.
Load resistance, R L .
Configuration as shown in Fig. 16.4.
The following step-by-step procedure is intended to be a logical approach to
the design of a class A driver stage when reliability is of primary importance.
1. Determine the a-c power requirement of the transistor.
a. Estimate transformer efficiency, Tj.
h. Calculate power delivered to the transformer: Pi = PdTj.
c. Estimate PB , the extra power necessary because of expected bias-point
shifting.
d. Determine the a-c power output of the transistor: Po = Pi + PB •
2. Determine the average power-dissipation requirements of the transistor.
a. Estimate 8: 8 = RL/(Ri + REl + Ry).
h. Calculate the maximum average power dissipation: PJ(malI!) = VQIQ~
2P~/8.
3. Select a transistor or series of transistors from the available data sheet
information to meet power, temperature, and frequency requirements.
4. Select a quiescent current from examination of the transistor data sheet
information; the collector current versus hpE curve should indicate what
current range is appropriate.
5. Determine the quiescent voltage.
a. Vii can be determined from Eq. (13): P; = VilIQ8/2.
b. Estimate a value of VII! from the data sheet information.
c. Calculate the value of quiescent voltage:. VQ = Vii + VII!.
212 D-C and Low-Frequency Designs

d. Choose a different value of quiescent current if the quiescent voltage


appears unreasonable.
e. Determine the required minimum voltage rating of the transistor from
>
Eq. (17): BVCEO 2VQ•
6. Determine the required value of reflected load impedance.
a. Determine reflected load impedance from Eq. (14): Po = I Q2RL/2.
h. Determine the transformer turns ratio.
7. Choose values for the remaining a-c impedances.
a. Estimate a value for R y. It comprises the power supply and trans-
former primary resistances.
h. Decide upon a value for R El . At this time, the effect of a particular
value of REl can be evaluated by comparing it with R£ .
c. Calculate 8, since RL , REl , and Ry are now known. If it is noticeably
different from the estimated value, PJ(ma:c) may require recalculation.
8. Calculate the value of bypassed emitter resistance RE2 . The value of RE2
can be determined from Eq. (5): VQ = Vce - IQ(REl + RE2 + Ry).
9. Determine the maximum junction temperature.
a. For any given heat sink, the designer must ascertain that the junction
temperature TJ(Peak) obtained will be less than the manufacturer's
specified maximum.
h. If the transistor is assumed to have a thermal time constant of zero,
the peak instantaneous power pJ(peak) becomes an important considera-
tion. pJ(Peak) can be evaluated froni Eq. (8).
c. A maximum value of case-to-ambient thermal resistance can be de-
termined from Eq. (10).
10. Determine the maximum value of base resistance from thermal stability
considerations.
a. A simplified version of the thermal stability equation is given by Eq.
(11). Chapter 7 on biasing gives considerable detail on the derivation
of this equation.
h. Although solving for the base resistance from the thermal stability
equation gives an upper limit, a value of resistance approaching this
limit may be quite impractical in view of bias-point stability consid-
erations previously covered in the text. For a minimum limit, it is
desirable that the base resistance be large with respect to the input
impedance of the transistor.
c. The exact values of RBl and RB2 can be determined from base resist-
ance and bias voltage considerations.
11. Determine the bias-point stability. This procedure is covered in Chap. 7.
12. Determine the effects of possible bias-point shifts.
a. Determine whether the estimated extra power, PB , is sufficient.
h. Determine whether the transistor is capable of dissipating the addi-
tional power which could result from a possible quiescent point shift.
13. Determine the values of the coupling and bypass capacitors, and select a
transformer.
14. Breadboard and test the circuit.
Class A Driver and Output Stages 213

16.4. DESIGN EXAMPLE

Known:
Supply voltage = 40 volts; impedance = 1 ohm.
Frequency = 400 cps (single frequency).
Ambient temperature = -25 to + 100 e. D

Load power, PL = 400 mw.


Load resistance, RL = 15 ohms.
Configuration as shown in Fig. 16.4.
1. Determine the a-c requirements of the transistor. The transformer effi-
ciency 1/ is assumed to be 75%. Therefore,

Pi = PL = 400 = 534 mw
1/ 0.75
Adding a safety factor of 300 mw gives
Po = 534 + 300 = 834 mw
2. Determine the average power-dissipation requirements of the transistor.
8 is estimated to be 0.75. Thus, the average power dissipation is

PJ(max) =
-
2P; _ 2(834 X 10-3) _ 222 tt
8 - 0.75 - . wa s

3. Select a transistor or series of transistors to meet the power, temperature,


and frequency requirements. The 2N17l8 series is selected based on
these considerations. The selection is narrowed even further by deciding
upon the 2N 1720, to obtain the highest possible gain.
4. Select a quiescent current from examination of the transistor data sheet
information. hFE is a maximum at 200 rna, and remains high at 21Q or
400 rna. Therefore, a quiescent current of 200 rna is chosen.
5. Determine the quiescent voltage. The required peak a-c voltage swing,
VQ, can be determined from Eq. (13).

Vo ' = 2P; = (2)(0.834) = 11 1 It


Q MQ (0.75)(0.2) . vo s
This seems quite small with respect to the 40-volt supply, so that a smaller
quiescent current might be appropriate. A quiescent current of 100 rna
will be tried.

Vo ' 2P; (2)(0.834) 22 2 1


Q = MQ = (0.l)(0.75) = . vo ts

Vx is estimated to have a worst-case value of 4 volts at 21Q or 200 rna.


Thus, the quiescent voltage is
VQ = VQ + Vx = 26.2 volts
The transistor will require a BVCEO > 2VQ or 52.4 volts. It appears that
214 D-C and Low-Frequency Designs

the 2Nl720, which has a 60-volt BVOEO , can be used if the bias point
does not shift excessively.
6. Determine the required value of reflected load impedance. The reflected
load impedance can be determined from Eq. (14).

R'
L
= 2P;
IQ2
= 2(0.834)
(0.1)2
= 1668. 0 hms
The turns ratio of the transformer is, therefore,

a = jR£ = j66.7 = 3.33


RL 15
7. Choose values for the remaining a-c impedances. The total value of R y
is assumed to be 20 ohms. REi is chosen as 5 ohms. This will help to
increase the input impedance and lower the emitter bypass capacitance
cutoff frequency, yet will not appreciably affect the gain, since R£ >
35REl . l) is calculated:

l) = R£ 166.8
R£ + Ry + REl 166.8 + 20 + 5 = 0.87
The estimated value 0.75 appears to be close enough to the calculated
value 0.87 so that PJ(marc) need not be recalculated.
8. Calculate the value of unbypassed emitter resistance R E2 • RE2 can be
determined from Eq. (5).
40 - 26.2 - (0.1)(5 + 20)
0.1
= 113 - 110 ohms
9. Determine the maximum junction temperature and required value of heat
sink thermal resistance. Since thermal-time-constant information is not
available on the data sheet of the transistor, and since the operating fre-
quency is fairly low, a conservative design will be achieved by assuming
the thermal time constant to be zero. The pJ(peak) for a class A stage can
be determined from Eq. (8).
[Voo + IQ(R£ - R E2 ))2 _ [40 + (0.1)(166.8 - 110)]2
pJ(peak) = 4(R£ + R y + R El ) 4(166.8 + 20 + 5)
= 2.72 watts
The maximum value of case-to-ambient thermal resistance can be deter-
mined from Eq. (10).
llTJ_A = (hOpJ(Peak) + ()OAPJ(marc)
Since the ambient is 100°C, llTJ-A could be 75 CO, but 70 CO will be used
to introduce a safety factor.
70 CO = (7.5)(2.72) + ()OA 2.22 ()OA < 22.4 - 22 CO /watt
Class A Driver and Output Stages 21 5

Thus, the heat sink, mica washer, and interface-contact thermal resist-
ance must all be less than 22 CO /watt.
10. Determine the maximum value of base resistance from thermal stability
considerations. The simplified stability expression is used. Since the
power-supply resistance of the circuit is small, the resistances of Eq. (11)
will be applicable to the circuit shown in Fig. 16.4. Equation (11) is:

->
1 Vee [~RB)
1 + - ~ .06931eBo-IQ--
dhFB) +---
0.0025 ]
OT RE dtJ RE
OT = 7.5 + 22 = 29.5 CO/watt
Vee = 40 volts
RE = 110 + 5 = 115 ohms
leBo = 500 p,a (from data sheet)
0.06931eBo = 34.6 X 10-6 amp
In most instances, it will be necessary to calculate leBo from the follow-
ing equation:
leBO ~ lOBO + 2n l cBO (18)
where lOBO = the voltage-dependent portion of leBo
leBo = the temperature-dependent portion of leBo
n = the number of 10 Co increments (for silicon transistors, or
14 Co increments for germanium transistors) between the
junction temperature at which leBo is known and the junc-
tion temperature for which leBo is being determined. This
rule of thumb is applicable for high temperatures over
relatively small temperature ranges.
lQ = 100 rna
dhFB ~ 6.h pB ~ hpEt/(1 + hpEl) - hpE2 /(1 + hpE2)
dtJ = MJ = tJ2 - tJl
Table 16.1 lists information obtained from the 2N 1720 data sheet con-
cerning the variation of hpE with temperature. The temperature range of

Table 16.1. hFE Characteristics of 2N1720 at 100 ma

Guaranteed Typical
TJ, °C Estimated minimum hpE
minimumhFE hpE
38
150 ... 125 82· 125 = 57.9 ~ 58
38
75 ... 97 82 . 97 = 44.9 ~ 45
25 38 82 38. 82 = 38
82
216 D-C and Low-Frequency Designs

+ 75 to 150°C was chosen for the evaluation of dh;B/dtJ since hFE infor-
mation at these temperatures is available on the data sheet and because
the choice results in a conservative design. Ideally, the variation of M'B
with temperature would be evaluated at the maximum anticipated junc-
tion temperature, which in this instance is 170°C. However, since h;B
decreases at lower temperatures, a safety factor is achieved by calculating
MiFB/ dtJ over a temperature range below the maximum anticipated junc-
tion temperature.
dh;B ~ hFEd(1 + hFE1 ) - hFFJ2/(l + hFE2 ) _ 4%6 - 5~9
dtJ = tJ2 - tJl 150 - 75
= -63.9 X 1O-6 /C

-IQ d;t
B < -(0.1)(-63.9 X 10-6) = 6.39 X 10-6 amp/CO
R < RE/OTV CC - 0.0025 - RE(0.0693IcBo - IQdh;B/dtJ) ohms
B 0.0693IcBo - IQdh;B/dtJ
R < 115/(29.5)(40) - 0.0025 - 115(34.6 X 10-6 + 6.39 X 10-6) ohms
B 34.6 X 10-6 + 6.39 X 10-6
RB < 2.2 kilohms
Although this is the maximum limit for thermal stability, it will not nec-
essarily ensure the desired bias-point stability. A rule of thumb sometimes
useful in obtaining a stable bias point is to limit the ratio of the base
resistance to the emitter resistance to 5 or less. A base resistance of
approximately five times the emitter resistance, or 575 ohms, will be tried.
A value of RBl = 2 kilohms and RB = I kilohm closely satisfies this
requirement as well as the necessary bias requirement, i.e., an emitter
voltage of IEQ(REl + R E2 ) or 11.5 volts. This parallel combination of RBl
and RB2 is actually 667 ohms instead of 575 ohms.
11. Determine the bias-point stability. From Chap. 7 the expression for mini-
mum quiescent current can be expressed as
I > bFE(!(B - VBE)
-Q = RB + RE(I + hFE)
and maximum quiescent current can be expressed as
I < VB - YBE + fcBoeRB + BE)
Q= R
_E

Because the power-supply resistance is small with respect to other circuit


resistances, it is not necessary to convert the circuit of Fig. 16.4 to an
equivalent circuit to obtain the correct resistance values for these equa-
tions. In this analysis, 1% resistor tolerances are used, and no allowance
is made for the change of this tolerance with temperature, aging, etc.
Class A Driver and Output Stages 217

The following characteristics are estimated data sheet information at


worst-case temperatures.
l1FE ~ 25 hFE~ 00

Y"BE ~ 0.4 volt VBE ~ 1.2 volts


leBO = 500 !La
The possible resistor and bias voltage limits are:
RE = 115 + 1.15= 116.15 ohms BE = 115 - 1.15 = 1l3.85 ohms
RBl = 2 K + 20 = 2.02 kilohms EBl = 2 K - 20 = 1.98 kilohms
RB2 = 1 K + 10 = 1.01 kilohms BB2 = 1 K - 10 = 0.99 kilohm

RB = RBlRB2 = 680 ohms


RBl + RB2
Vae = 40.5 volts [ea = 39.5 volts
-
VB =
-
Vee--~~~
RB2 ---,-:-(,-:40.,....5..,.:-)-,-0_.0_I_kil_·o_h:-m:-s-'--,)_ = l3. 7 volts
BBl + RB2 1.98 kilohms + 1.01 kilohms
__(-,-3_9.--,5)-,-(0_.9_9_kil_·_oh_m..,.:-)_ _ = l3.0 volts
2.02 kilohms + 0.99 kilohm
Solving for I Q,
I > (25)(l3.0 - 1.2) = 79.5 rna
Q- 680 + 116.l50 + 25)
I < l3.7 - 0.4(0.5 X 10-3 )(680 + 1l3.85) = 114 rna
Q= 113.85
12. Determine the effects of possible bias-point shifts. Since I Q is capable of
varying 20.5 rna, the peak alternating current can also be decreased by this
amount. Under such conditions, the a-c power supplied to the transformer
would be
Pi = (0.1 - 0.0205)2Ri = (0.0795)2066.8) = 526 mw
2 2
This is within several per cent of the required value of 534 mw. In view
of the conservative estimates made in determining these results, it is
reasonable to assume that the required output power can be achieved
despite possible shifts in the bias point.
l3. Determine the values of the coupling and emitter bypass capacitors and
select a transformer. The value of the coupling capacitor C1 can be
determined if the signal source impedance is known. When the source
resistance, R s , equals 1 kilohm, the coupling capacitor will affect the gain
less than 3 db if
218 D-C and Low-Frequency Designs

C1 > w(Rs +1 R(in))


. __ RaRE(1 + hFE) -- hm
R(.n) = (l h ) = 110 0 S
RB + RE + FE
W = 2'77f = 2'77(400) = 800'77 radians/sec
1
C1 > 800'77(1.110 kilohms) = 0.359 pi
A value greater than ten times this, or 5 pI, will be used.
The emitter bypass capacitor CE can also be determined from gain
considerations. The emitter capacitor and resistors will lower the gain less
than 3 db if

eM> [ ~
w RE211 REl h: 1
I R IIR )
+ 1~ E

CE > RBRS + (RE2 + REl)(RB + Rs)(l + hFE)


WRE2[RaRs + RE1(RB + Rs)(1 + hFE)]
A conservative simplification gives
1
CE > -w REl
= 79.5 pI
Transformer efficiency and output power considerations require that the
open-circuit primary inductive reactance be much greater than the reflected
load impedance. The open-circuit primary inductance must exist with a
direct current of IQ flowing through the primary. Good low-frequency
response, however, dictates a more stringent requirement. The inductive
reactance must be less than the parallel combination of reflected load
impedance and the output impedance of the transistor. Because the size
of the transformer is also an important consideration, the low-frequency
gain is often sacrificed, and only the requirement that the inductive
reactance be much larger than the reflected load impedance is satisfied.
In this particular example a square stack of 56EI laminations with 442
turns of no. 30 wire was chosen as the transformer. A secondary was not
actually wound on the core, but slightly more than half the window area
is available for this purpose.
14. Breadboard and test the circuit. The completely designed circuit is shown
in Fig. 16.5 with performance data obtained for high- and low-limit hFE
transistors over the specified temperature range.
Class A Driver and Output Stages 219

C1

400~+
input

Component list Transformer data Circuit characteristics


R£ = 166.7 ohms, \6 watt NI = 442 turns no. 30 AWG at 400-mw power output
Rl = 2 kilohms, I watt Core-Allegheny 56EI SL-14 and 400 cps
R2 = I kilohm, V2 watt 1 X 1 interleaved Power gain 2 24 db
R3 = 5 kilohms, \6 watt \6 window area available for Voltage amplification 2 22 db
R4 = 110 kilohms, 2 watts secondary Input resistance;;:,; 260 ohms
C1 = 5 p.f, 50 volts D-c resistance of primary = Ambient temperature range =
C2 = 100 p.f, 50 volts 9 ohms -25 to + l00"C
Ql = 2NI720 Total harmonic distortion
<5%
Notes:
1. All resistance values in ohms-1% tolerance.
2. Resistance wattage ratings and capacitance voltage ratings at 100"C.
3. Ql on heat sink allowing thermal resistance from case to ambient < 22"C/watt.
4. Signal source impedance of 1 kilohm used during performance measurements.
Fig. 16.5. 400-mw class A amplifier.
17
Low-frequency Transformer-coupled
Class B Output Stages

A class B stage may be defined as one biased close to cutoff, so that any upward
signal fluctuations turn the active device ON, while for downward fluctuations it
remains OFF. If the incoming signal were a sinusoid, for example, the active
device (in our case, the transistor) would be turned ON during 180 of the signal.
0

A second active device is necessary to handle the remaining 180 of the signal cycle.
0

The most popular means of driving the two amplifying devices and combining their
individual outputs is the center-tapped transformer. A typical circuit is shown in
Figure 17.5.
Class B stages are often used for the output stages of transistor power amplifiers
for the following reasons:
1. Even harmonic distortion can be reduced to a minimum.
2. Theoretical maximum efficiency is 78% for a class B vs. 50% for a class A
stage.
3. Quiescent power drain is very small, whereas a class A stage draws a con-
stant power from the supply at all times.
4. Power dissipation is shared between two transistors.
5. Because no net direct current flows through the output transformer, the net
d-c magnetizing flux is zero and transformer weight is low.

17.1. DISTORTION

We will now discuss a few of the causes of distortion in a class B stage. Some
will be quite common; some are rather obscure.
A waveform which is symmetrical in amplitude about an axis drawn through
its average value and symmetrical in time about the wt = 7T/2 axis contains no even
harmonics. A push-pull type of circuit uses this fact to reduce the even-harmonic
distortion in the output signal. We have said that in a strict class B push-pull
amplifier, the positive portion of an input signal is amplified by one transistor and
the negative portion by another. If the transistors have identical characteristics,
220
Low-frequency Transformer-coupled Class B Output Stages 221

when the two amplified portions of the signal are recombined, the output will be
symmetrical, and no even harmonics will be present. This type of operation is
illustrated in Fig. 17.1.
Bias. Figure 17.1 reveals a potential source of trouble. If both transistors are
allowed to turn OFF at zero instantaneous signal, then the composite transfer
characteristic obtained by combining the VBE vs. Ie curves for both transistors can
be far from linear. The large change in die/ dVBE as the instantaneous signal voltage
crosses the zero axis will cause crossover distortion. Similar effects result from the
combined IB vs. Ie curves.
There is an instant while the input signal reverses polarity that both transistors
of Fig. 17.1 are OFF. The collector current through the output transformer is
changing very rapidly at this moment, and the collector impedance is very high.
The interaction of these effects with the transformer leakage inductance will produce
a notch in the output waveform each time it crosses the zero axis. This effect is
commonly known as a switching transient and is another design problem attendant
upon truly class B operation. Some decrease in switching transients may be realized
by the use ofbifilar windings in the output transformer to achieve better symmetry
and tighter coupling. Unless this is done carefully, however, it may result in high-
frequency response deterioration.
Switching transients can be reduced and the composite transfer characteristic
made almost linear by biasing the transistors to conduct a few milliamperes with
no applied signal. A composite for this type of operation is shown in Fig. 17.2.

First transistor

Second transistor

Fig. 17.1. Composite transfer characteristic for unbiased stage.


222 D-C and Low-Frequency Designs

First transistor
Input
signal voltage

Base bias
voltage
Composite output
current

Second tra nsistor


Fig. 17.2. Composite transfer characteristic for biased stage.

The amount of bias required is fairly critical: too little will fail to eliminate cross-
over distortion, while too much will cause distortion at high power levels. The
correct bias voltage for a particular transistor type must be found by experiment.
Thus, practicable class B amplifiers usually do not operate, strictly speaking,
class B. Each transistor is usually biased into slight conduction rather than at the
edge of cutoff.
Source Impedance. For certain transistors the VBE vs. IcCYFE) characteristic
has a curvature of opposite sign to that of the IB vs. I c( hFE ) characteristic. At
low signal source impedance (constant-voltage drive), the stage operates on the YFE
characteristic; at high source impedances, on the hFE. For some optimum a-c
source impedance, r g, defined by Fig. 17.3, the effects of these two curvatures will
almost cancel, and the distortion of the stage will minimize. In terms of transistor
small-signal parameters,
_ (h(e/Y(e)2dYre/d1c _ R _ hre dhie/d1c _ h· _ R
rg - _ dhre/dlc E - dhre/dlc .e E

but this is of little practical help. For large-signal operation, rg must be determined
by experiment, especially if diodes are used in the base bias circuit.
Another source impedance consideration is given under Transformers.
High-current hFE Fall-off. Another form of distortion occurs for large signals
if the current gain of the transistors falls off at high current levels. This appears
as a gentle clipping or compression of the instantaneous signal peaks. The effect
is shown in Fig. 17.4.
If the clipping is sharp and sudden, the transistor is probably driven into satura-
tion and the peak current is being limited as in Eq. (9).

- ic

Figure 17.3
Low-frequency Transformer-coupled Class B Output Stages 223

,, ,
,-, y--Ideal sine wave
\
" \,..-...-- Distorted output
/ " s i n e wave

Fig. 17.4. Distortion from


hFE fall-off.

Transformers. No attempt is made to match the output transformer primary


impedance to the transistor output impedance; the transformer turns ratio is set
by other considerations. In fact, the disparity is usually so great that the trans-
former sees the transistors as a constant-current source. Low-frequency response
is determined only by the transformer inductances and the load resistance. Distor-
tion from magnetizing current is calculated accordingly.
Since the input impedance of the transistors varies with the current gain and the
instantaneous collector current, the load on the driver transformer secondary is
constantly fluctuating. To guarantee a particular low-frequency response, the
primary inductance must be determined by the driver source impedance alone with
the secondary open-circuited.
Description of ICBO and lEBO. At high reverse-bias voltages and high junction
temperatures, the ICBo and lEBO of many power transistors becomes strongly
voltage-dependent. If the class B circuit forces the OFF transistor into this voltage
range, considerable leakage current will flow on signal peaks. Besides adding to
the transistor dissipation, these currents may cause substantial distortion.

17.2. PRIMARY DESIGN CONSIDERATIONS

Usually, a particular power output is the first design requirement. An under-


standing of output power limitations can be developed from the typical circuit in
Fig. 17.5. The maximum average undistorted sine-wave power into Z, Pc:, is
given by
(1)

Figure 17.5
224 D-C and Low-Frequency Designs

Not all this power will be delivered to the load; some will be lost in the output
transformer. The efficiency of this transformer may range from 95% for a design
without space or weight restrictions to 50% for a subminiature design. The require-
ment for P; must be increased accordingly.
The quantities comprising Eq. (1) are subject to many restrictions and complex
interactions. We will now discuss these in some detail.
Description of Vec. A transistor stage achieves power gain through two mecha-
nisms: the current amplification of the transistor, and the difference in impedance
between the load on the transistor and the input presented by the transistor. The
current gain is fixed by the transistor alone, but the impedance gain is circuit-
dependent. To take maximum advantage of impedance gain, a class B stage should
operate with the largest possible load voltage swing, which, in turn, implies the
largest possible supply voltage.
Except for abnormal voltage spikes, such as might be caused by removing the
amplifier load during an applied signal, the maximum supply voltage for a class B
stage is limited by one of two requirements:

Wcc! < IBVCBXI


2
where the emitter diode is reverse-biased (2)

or IVcci < IBVCERI where R is the base-to-emitter circuit im-


(3)
pedance seen by the transistor
Of course, operating at high supply voltages makes the stage more sensitive to
transient voltage spikes and may also influence the reliability of some transistor
types. Voltage spikes generated in the output transformer may be reduced by
bifilar-winding the transformer primary, and completely eliminated by protective
breakdown diodes (not shown in Fig. 17.5) between each collector and circuit ground.
Heat Dissipation and (RE + Z). The ease with which heat energy can be
dissipated from the junction into the ambient limits the number of independent
variables in Eq. (1). The nature of thermal resistance is discussed in Sec. 4.4. The
transistor data sheet will give sufficient information to calculate junction-to-case
thermal resistance, OJ_C, and for transistors designed to operate without a heat sink,
junction-to-ambient thermal resistance, OJ-A, also. The thermal resistance from
the transistor case through a particular heat sink into the ambient, BC_A' must be
determined by the transistor user, not the manufacturer. The design and analysis
of heat sinks is a complex study; references are given at the end of Chap. 4.
From Eq. (21) of Sec. 7.2,
(4)
where Bl = portion of total BJ-A which may be considered unbypassed by any
thermal capacitance at the lowest signal frequency (see Sec. 4.4)
O2 = portion of total BJ-A for which the pulsations of pJ have been smoothed
out by thermal capacitances
For class B power amplifiers carrying signals of very low audio frequencies, Bl may
>
be assumed to be BJ_c, and B2 may be taken to be BC_A • If BJ_c 2CO /watt, or if
only upper audio frequencies and higher are considered, then this value for Bl may
be too large.
Low-frequency Transformer-coupled Class B Output Stages 225

In terms of power dissipation, the worst signal waveshape which a class B stage
might be required to amplify is a square wave of an output peak amplitude about
one-half the available peak instantaneous output voltage. For that waveform, if
I CBO and lEBO do not cause significant dissipation in the OFF transistor,
pJ(peak) ~ 2PJ(maxavu) (5)
Therefore, from Eqs. (4) and (5) an upper limit for junction temperature can be
assured if
< 2ATJ-A
pJ(peak) = 281 + 82 (6)

It can be seen by inspection of Fig. 17.5 that

pJ(peak) ~ 4(RE + Z) (7)

RE and Z must be chosen so that this peak junction power is held within the
restrictions of Eq. (6).

RE + Z >-- Vc~(281 +( 2)
-----='-=-::''-:-:::::------:------=~ (8)
8ATJ-A
In practice, the peak signal current on which the designer can rely is limited by
the maximum saturation voltage of the transistor over the whole operating tem-
perature range.
I = Vcc - VCE(sat) (9)
C(peak) - RE +Z
If the stage must be designed for the maximum possible output power, (RE + Z)
must obviously be minimized. Using the minimum value from Eq. (8),
I < 8ATJ-A(1 - VCE(sat)/VCC) (10)
C(peak) = V cc (28 1 + ( 2 )

Here, then, is an upper limit, imposed by heat-dissipation considerations, upon the


peak collector current for which the stage may be designed.
Substituting Eq. (10) into Eq. (1),

P; = 4 ATJ-A ~ _ VCE(sat)\2 (1 _ 8RE ATJ-A) (11)


281 + 82 '\ Vcc -; '\ Vc~ 281 + 82

IfEq. (11) does not yield a sufficient P~, one solution is to parallel output transis-
tors. Note that even if the transistor and circuit were perfect (i.e., RE = 0 and
VCE(sat) = 0), P; could not exceed 4ATJ-A/(281 + ( 2).
Description of R E. The resistor RE reduces the current gain, the available out-
put power and, sometimes, the high-frequency response of a class B stage. Why,
then, have any RE at all? Because RE serves two very important functions: it
helps stabilize the transistor against thermal runaway, and it helps establish the
quiescent operating point necessary to prevent crossover distortion. (It may also
stabilize gain and reduce distortion by providing negative feedback for the signal,
226 D-C and Low-Frequency Designs

but this is a dubious incidental benefit. There are other ways to accomplish this
end without sacrificing output power.) The value of RE is dependent upon the
nature of the base bias network, and the quiescent-operating-point stability is
closely related to the thermal stability. For clarity in our discussion we shall
treat each of these considerations separately, but an actual design must satisfy all
simultaneously.
Figure 17.6 shows a very general representation of the elements of class B bias.
RB2 is the d-c resistance of the driver transformer secondary seen by each transis-
tor. VBB and RBl are the Thevenin equivalent of the bias voltage source.
To ensure quiescent (no signal) thermal stability, a simplification of Eq. (59),
Sec. 7.3, will probably suffice. Only the result is given here; Sec. 7.3 should be
consulted for a complete explanation.
R > OJ-AVcc[ (RBl + RB2 + yB)(0.0693IcBo - IOQ dh;B/dtJ) + 0.0025] (12)
E 1 - OJ-AVco(0.0693IcBO - ICQ dhFB/dtJ)
This assumes silicon transistors [Sec. 7.3, Eq. (48)] having no common heat sink.
If the two transistors were tightly coupled thermally, then it would be necessary
to double the values of lOBO and IOQ in Eq. (12).
Thus, the smaller (RBl + R B2 ), the smaller R E.
It is advisable to use a separate emitter resistor for each transistor. This serves to
1. Equalize IO(peak) and IO(quiescent) through each transistor.
2. Reduce the peak inverse base-emitter voltage at the OFF transistor.
3. Simplify the thermal stability analysis so that Eq. (12) is valid.
Another restriction upon RE is set by the breakdown voltage of the emitter
diodes. For a minimum of safety,

IBVEBXI > IIC(Peak) I (l~E + 2RBl +hRB2


pE
+ RE) + IVBE(on peak) I -2 WBB(min)
' I (13)

Equation (13) can be put in the form

(14)

where N = BVEBX + 2VBB(min) - VBE(onpeak) (15)

Figure 17.6
Low-frequency Transformer-coupled Class B Output Stages 227

Also, a solution of Eq. (12) in terms of RE and (RB1 + RB2 + rB )will take the
form
RE > A + B(RBl + RB2 + rB ) (16)
Substituting Eq. (16) into Eq. (14),
RE < NhpE/lc(Peak) + A/B + rB - RBl (17)
1 + hpE + liB
If ~ + rB > RBl + -c(peak)
N1 iJ +
\
Bl_\
)
(18)

then the worst restriction on RE occurs for high hpE. Letting hpE ----'> 00,

RE<~ (19)
Ic(Peak)
This result is also obtained if Eq. (18) is an equality. If the inequality sign in
Eq. (18) must be reversed, then the minimum hpE is used in Eq. (17). In these
equations V~B' hpE, and RBl must be evaluated for the exact circuit conditions
existing where Ic(peak) occurs.
Thought must be given to the conditions for measurement of BVEBX. The
amount of base current (i.e., I EBx + I CBX) which flows in the OFF transistor dur-
ing signal voltage peaks must be kept small, not only to prevent excessive power
dissipation, but also because this current may act as a distortion component in
the signal. Since some emitter diodes tend to relatively high leakage and gradual
breakdown knees, it is a good practice to check the diode reverse characteristic at
the expected maximum temperature. Reasonable rules of thumb might be that
at TJ(ma:c)'
2VcclcBXI(VoB",,2vOc) < O.IpJ(Peak) (20)
and IIcBxl (VoB",,2Voc) + IIEBXI (VEB""BV EBX ) < O.lIIB(Peak on) I (21)
Equation (20) places a limit upon I cBx, and Eq. (21) sets a limit for I EBx at
VEB ~ BVEBX. If the manufacturer does not guarantee I EBx and I cBx, lEBO and
I cBo may be used.

17.3. BASE BIAS CIRCUITS

Equation (11) of Sec. 7.1 enumerates the factors affecting the quiescent operat-
ing point of any isolated transistor stage. Particularly important in class B design
is the variation of V BE with temperature. Unless compensated, VBE may change
the circuit operation from class C at low temperatures to class A at high. An ob-
vious solution is to vary V ~B accordingly so that (V~B - VBE ) remains constant
over the temperature range. The effects of I CBO and hpE variation can be reduced
by minimizing (RBl + RB2)'
The goals of our bias design are clear: RBl should be as small as possible, V~B
should vary with temperature at the same rate as dVBE/dtJ (approximately -0.002
volt/CO), and vim should be no larger than is needed to eliminate crossover dis-
228 D-C and Low-Frequency Designs

+ Vee + Vee + Vee + Vee


Rl Rl Rl

R2 R2 Dl

(a) (b) (c) (d)

+ Vee
Rl Rl

D2 C

(e) (f) (g)


Fig. 17.7. Bias circuits.

tortion. Many circuits are used to these ends, with varying degrees of success.
Figure 17.7 gives examples.
Example a is a simple voltage divider. It does not provide temperature com-
pensation for VBB and cannot be used for a wide junction temperature range.
The design equations are
Rl = RBlVBB: ce (22)

R _ RBl (23)
and
2 - 1 - VBB/Vee
Examples band c are similar in design, except that each uses a temperature-
sensitive resistor to compensate VBB . In example b, Rl must have a temperature
coefficient
TC = + 0.OO25(Rl
V. RR
+ R2)2 X 1000110 per Co (24)
ee 1 2

In example c, R2 must have


TC 0.OO25(Rl + R2)2 100O/C CO (25)
=- VecR2(R 1 + R2 _ 1) X 0 per

The linear positive temperature coefficient for Rl is easily and accurately obtained
with sensistor* resistors, alone or combined with fixed resistors. The negative
temperature coefficient for R2 is usually approximated by a thermistor in parallel
with a fixed resistor.
The success of example d depends on the fact that the diode Dl can exhibit the

* Trademark of Texas Instruments Incorporated.


Low-frequency Transformer-coupled Class B Output Stages 229

same temperature coefficient for its forward voltage drop as do the emitter diodes
of the transistors. Ri is adjusted to pass a current just slightly greater than the
peak signal current into the transistor bases, so that Di remains forward-biased
at all times. RBi and V~B are fixed by the forward characteristics of Di and the
current through it.
Let us examine the behavior of a forward-biased diode in some detail. The
voltage across a diode is related to the current through it by the expression

Vn = InriJ + k~A In 0- ~:) (26)

where Vn = voltage across the diode (positive in sign for a forward-biased diode)
= current through the diode (positive in the forward-biased direction)
In
k/q = 8.616 X 10-5 volt/Ko
riJ = bulk (ohmic) resistance of the diode
A = a correction factor (usually one to two)
T = absolute temperature, OK
Is = saturation current of diode (negative in sign)
This characteristic is illustrated in Fig. 17.8. Operation of the diode at some cur-
rent h produces a voltage V1. If a line is drawn through point (V1,!1) tangent to
the diode characteristic curve, it will intersect the voltage axis at some point
(V~,O). The slope of the line will be

_dVn kTA
rn = - -
dIn
= rn, + ---:--:;---=-:-
q(1n - Is)
(27)

ViJ = kTA r1n it - In) - In J (28)


q L '\ Is In - Is
If In ~ - Is, then
(29)

and (30)

Thus, at any instantaneous forward-biased operating current In, the diode may
be represented by an equivalent Thevenin circuit as shown in Fig. 17.9. At

Fig. 17.8. Diode forward characteristic. Fig. 17.9. Diode equivalent circuit.
230 D-C and Low-Frequency Designs

TJ = + 150°C and A. = I, kTA/q = 0.03646 volt. If this substitution is made into


Eq. (27), it is easy to see that rn may dominate rD at diode currents larger than
36 rna. It is not always easy to determine rn. However, a line through points
(hV1 ) and (0,0) will always have a greater slope than a line through (hV1) and
(VD'O). Therefore, the d-c resistance of the diode, Vdh will always be greater
than its instantaneous a-c resistance, rD.
VD
rD<- (31)
ID
This is a helpful limitation to remember in the initial stages of a design.
Relating example d to Fig. 17.6,

RBl = rnRl (32)


rD + Rl

and ,
vBB= V:' (Vee - Vn)rD (33)
D+ rD +R1
Three disadvantages result from the high diode current required in example d:
1. Considerable power may be thrown away in R 1 .
2. The magnitude of V~B cannot be adjusted readily.
3. In Eq. (26) the temperature coefficient of (kTA./q) In (1 - In/Is) is nega-
tive because Is increases almost exponentially with temperature. But the
coefficient of rn is positive, so that the coefficient of VD goes from negative
to positive as IDrn increases. Thus the whole purpose of example d may
be nullified.
Examples e and f attempt to reduce the diode current required. In example e,
Rl and Dl must pass only sufficient bias current to give the desired RBl and VBB
as defined by Eqs. (29), (30), (32), and (33). When the instantaneous base signal
current exceeds this amount, Dl becomes back-biased but D2 takes over to pro-
vide a low-impedance return path for the base drive. D2 must be large enough
to carry the peak base current. Some distortion is introduced into the driver-
signal-voltage-vs.-collector-current transfer function of the stage, but the driver-
signal-current-vs.-collector-current transfer function is unchanged, and if the
driver signal generator impedance is reasonably high, the increase in total distor-
tion will be low.
In example f, the capacitor bypasses the a-c component of the signal current
flow through Dl so that Rl need carry only one-half the peak base current. This
circuit is most convenient at high frequencies where C can be small. The shift in
d-c voltage across C with signal level may cause annoying transient changes in
stage gain if C is too large or if the driver signal generator impedance is too low.
Example g is similar to example a except that the driver transformer secondary
resistance (RB2 of Fig. 17.6) has become a part of R 2. For the same V~BRBl and
R B2 , example g will always require more drive power. However, if in example a,
<
R2 RB2 (1 + R2/R 1), then example g will require less bias current.
Low-frequency Transformer-coupled Class B Output Stages 231

17.4. OUTPUT TRANSFORMER DESIGN

The output transformer does not attempt to match the load impedance to the
transistor output impedance. Instead, it must present a load, Z, to the ON tran-
sistor such that
Z > Vcc2(20l + O2 ) - RE (34)
- Bf:..TJ-A
the smallest Z giving the greatest output power. Since the OFF transistor is in-
active, that half of the center-tapped primary does not enter into the picture.
Therefore, the ratio of total primary turns, N l , to secondary turns, N 2 , is

Nl = 2 fZ (35)
N2 YIf;;
The inductance of the transformer is computed from RL only, the output im-
pedances of the transistors being high enough to act as a virtual open circuit for
the primary. If the load varies, it may not be practical to design for an inductance
to suit the largest value of R L. Then the inductances are set for the value of RL
corresponding to maximum output power, and overall feedback is added to re-
duce the distortion resulting from nonlinear magnetizing currents. Alternatively,
the transistor output impedance might be lowered with collector-to-base feedback.
Bifilar winding reduces distortion. The peak-to-peak voltage across Nl used
for computing maximum flux density is approximately 4Vco .

17.5. DRIVER TRANSFORMER DESIGN

The design problems of the driver transformer are similar to those of the out-
put, with one exception. The transistor input impedance loading the secondary
varies widely both with instantaneous operating point and from unit to unit, so
that the secondary load cannot be used to set the inductance for low-frequency
response unless maximum hie and hte are guaranteed. Instead, these inductances
are usually determined by the driver source impedance. If the driver source is a
class A transistor stage, it may be necessary to establish a maximum for this by
shunting the transformer primary with a resistor or reducing the transistor output
impedance with feedback. These niceties are often overlooked through careless-
ness or for economic reasons, but their effect upon phase-gain stability margins
in an amplifier with overall feedback is considerable.
The peak current, ITS, which must be supplied by one-half the driver secondary is

I
TS(peak) = I Bl(on peak) + I B2(ot! peak) = hIO(Peak)
FE(min)
+ 1OBX(max) + I EBX(max) (36)

The peak voltage to be supplied at the ON base is

VB1(peak) = VBE1(onpeak) + RE(max/O(Peak) \~ + hI)


FE(min)
(37)
232 D-C and Low-Frequency Designs

The worst cases for these requirements generally appear simultaneously with
minimum hpE transistors at the lowest junction temperature. How much voltage
must be supplied by the secondary to meet VB1(Peak) at I B1 (on peak) depends upon
which circuit of Fig. 17.7 is chosen.

17.6. A TYPICAL CLASS B DESIGN

A typical problem might be to design a class B stage to provide some sinusoidal


audio output power, Po. Usually other factors in the design may dictate the range
of ambient temperature, TA , and the worst thermal impedance from transistor to
case to ambient, OC_A. Sometimes the supply voltage, Vcc, may be fixed, some-
times not. Let us assume that
j= 400 cps
Po = 5 watts
OC_A < 15 Co /watt for each transistor
TA = -55 to + 125°C
Vcc = as required
We may further assume that the output transformer efficiency is at least 85%, so
that the true output power expected of the transistors, P;, is 5.9 watts.
At this point, there is nothing to do but peruse data sheets for a likely candidate.
But the search may be narrowed somewhat by the following reasoning.
A maximum ambient temperature over about 80°C will restrict the device
material to silicon. For good reliability, present silicon transistors are seldom
operated at junction temperatures higher than + 175 to +200°C.
For perfect transistors, Eq. (11) reduces to
P' < 4LlTJ_A (38)
o = 20 1 + O2
Substituting the known information into Eq. (38),

5 .9 watt s <
_ 4(175°C - 125°C) . '. 0J-C < 9.45 Co /watt
- 201 + 15 CO /watt
<
This should be quite conservative, since at these values of 0J_C, 01 OJ-C.
If the maximum collector voltage may be used to aid stage gain, then from Eqs. (1)
through (3),
and

We now know we must have a silicon transistor with OJ_C < 9.45 Co /watt, and we
know what collector currents to expect based upon the breakdown voltage of the
transistor. With these limits as guides, the search may begin.
Among the contending types, the 2N1719 seems an excellent possibility. A
maximum ICES is specified for VCE = 150 volts, which indicates that BVCEX 150 >
volts. This would allow a safe Vcc of 70 volts. Support for this choice comes
>
from an I CEO specified at 90 volts, indicating that BVCEO 90 volts. At Vcc = 70
Low-frequency Transformer-coupled Class B Output Stages 233

volts,Ie(peak) will be about 0.17 amp-well within the transistor capability. Also,
fr > 16 mc, so that the problems of closing a feedback loop around this stage are
minimized. A (}J-C < 7.5 CO/watt betters the estimated requirement.
A minimum limit for Z in terms of RE can be found from Eq. (8).
R Z> (70 volts)2[2(7.S CO/watt) + IS CO /watt]
E + = 8(17SoC _ 12S0C)
Z> 367.5 - RE

If RE has a -+- S% tolerance, this becomes


Z > 36S.5 - (0.9S)RE

The boundary values for this inequality are graphed as the lower line of Fig. 17.10.
The voltage drops around the collector circuit at Ie(Peak) are:
1 + hFE
Voo = ZIc(peak) + VOE(sat) + h
FE
REle(Peak)

A minimum value for hFE at -SSoC at Ie = 0.2 amp is guaranteed by the data
sheet:
hFE(min) > 10
Extrapolated from the guaranteed VOE(sat) at Ie = 0.2 amp, IB = 20 rna, and TA =
2SoC, the typical VOE(sat) vs. TA data sheet curves indicate that
VOE(sat) < 3.3 volts
TA=175°C
Ie=O.2amp
IB=20ma

A minimum value for Ie(peak) can be found in terms of Z from


I >
e(peak) =
j 11.8 watts
Z

Allowing a -+-S% tolerance for RE and substituting into the equation for collector
voltage drops,

70.0 volts > YZ(I1.8 watts) + 3.3 volts + 1 toW (1.0S)R E jl1.8 ;atts
This inequality can be solved for a maximum value of Z in terms of R E • The solu-
tion is graphed as the top line of Fig. 17.10. Thus, Fig. 17.10 indicates a permis-
sible area of solution for Z in terms of RE when RE has a -+-S% tolerance.
In order to decide what type of bias circuit to use, we must have a feel for the
dependence of (RBl + R B2 ) on RE • Equation (12) will provide this.
The data sheet gives I oEs = SOO p,a at + 170°C. If los doubles for each 10 CO
rise, then at + l7SoC, lOBo = 7.1 X 10-4 amp.
Equation (69) of Sec. 7.3 suggests a method of evaluating dhpB/dtJ. As a rule
of thumb, the quiescent collector current will not be greater than 0.2 nor less than
about 0.1 of the peak current expected. From Eq. (10), as an approximation,
234 D-C and Low-Frequency Designs

I < 8(175°C - 125°C)(1 - 3.3 volts/70 volts)


c(peak) = (70 volts)[2(7.5 CO/watt) + 15 CO/watt]

Ic(peak) < 0.1815 amp


Considerations of the data sheet typical curves and guaranteed minimums indi-
cate that at IEQ = -20 rna,
hFE> 17
and hFE> 55
Over this range,
MFB -1/(17 + 1) + 1/(55 + 1) = -00005026/CO
!::.tJ = + 150°C - 75°C .

378

376 \
374 \
372
\
370 \
\
<f)

E
.s:::
o
~-
368

366
~ \
""
\
364

362
"" ~ ~

360
o 2 4

"
6
R E , ohms ± 5%
Figure 17.10
8 10
Low-frequency Transformer-coupled Class B Output Stages 235

This is likely to be larger in absolute magnitude than dhh/dtJ at + 175°C or at


moderately high currents.
Substituting these worst-case conditions into Eq. (12),

4.5~ + 15~)
\ watt watt
(70 volts) {(RBl + RB2 + rB) [0.OC693 (7.1
°
X 10-4 amp)

+ (0.2)( -0.1815 amp) -0.0~?5026 ] + O.OO~o volt }


RE> -------------------------------------------------------
1 - (7.5 ~ + 15 CO)
(70 volts) [0.OC693 (7.1 X 10-4 amp)
watt watt _ °

+ (0.2)( -0.1815 amp) -0'0g!5026 ]

RE > 4.405 ohms + 0.1189(RBl + RB2 + rs )


The peak base current required at Ic(peak) and hPE(min) is 0.01815 amp. This
modest requirement makes the bias circuit d of Fig. 17.7 feasible. The complete
circuit is shown in Fig. 17.11.
The current through Rl must be slightly greater than IB(Peak); 20 to 25 rna should
be satisfactory. The diode voltage drop at -55°C at 25 rna will surely be no
greater than about 0.7 volt.

Rl ~ 70.0 volts - 0.7 volt = 3,465 ohms


0.02 amp
The TI 1N538 would be a good choice for the diode. The dynamic resistance
of this type can be extrapolated from the data sheet to about 6 ohms at 20 rna at
+ 175°C, and it should decrease at higher current and at lower temperatures.
RBl < 6 ohms
The solution of Eq. (12) indicates that we had better choose the largest possible
value for RE in order to permit a reasonable RB2 and an inexpensive driver trans-
former. The largest 5% MIL standard resistance value which falls within the

.....----------...----0 + vee

c
Figure 17.11
236 D-C and Low-Frequency Designs

restrictions of Fig. 17.10 is 6.81 ohms. If the resistor has a low temperature coeffi-
cient, this will be satisfactory. Substituting into the solution of Eq. (12),
(0.95)(6.81 ohms) > 4.405 ohms + (0.1189)(6 ohms + RB2 + riJ)
RB2 + riJ < 11.37 ohms
For an exact solution of RB2 , riJ may be evaluated with the technique suggested
at the end of Sec. 7.3. But for a transistor with this current capability, rfJ should
not be very large, and if RB2 is held less than about 7 ohms when the driver trans-
former is at + 125°e, all should be well.
To verify that this value for RE(malt) will not cause excessive voltage across the
OFF emitter diode, we must examine Eq. (18). From the solution of Eq. (12),
A = 4.405 ohms B = 0.1189
From the data sheet,
BVEBX > BVEBO = 6 volts
Extrapolating from the guaranteed VBE at Ie = 0.2 amp at 25 ° e on the typical
VBE vs. TA curves in the data sheet,
VBE(on peak) = 1.7 volts
For any of the bias circuits in Fig. 17.7, the worst that can happen is
VBB= 0
N = 6 + (2)(0) - 1.7 = 4.3 volts
Substituting into Eq. (18),
4.405 ohms + rfJ > RBl + 4.3 volts II + _1_)
0.1189 0.1815 amp \: 0.1189
37.07 ohms + rfJ > RBl + 223.0 ohms
Since Eq. (12) will obviously be false (riJ will not be so high), Eq. (17) will be
required. A minimum hFE of 10 is guaranteed at Ie = 0.2 amp at - 55°C.
Therefore,
R < (4.3 volts)(I0)/0.1815 amp + 4.405 ohms/0.1189 + rfJ - RBl
E 1 + 10 + 1/0.1189

RE < 14.11 ohms + rfJ 19.41


- RBl

The chosen value of RE will obviously be safe.


To summarize,
vcc = 70 volts
RE = 6.81 ohms -+ 5%
Rl = 3.16 kilohms -+ 5%
Z = 361.1 ohms
RB2 < 7 ohms at 125°e
Low-frequency Transformer-coupled Class B Output Stages 237

The final step is to calculate the peak current and voltage which the driver
transformer must supply.

I
B(peak)
Ic(Peak)
= hFE(min) 11.8 watts = 18.1 rna
10 -=-3--=-6-=-1.-=-1-0C:-hm
- s

At -55°C the driver transformer must supply a peak voltage of


VT(peak) = IIE(Peak)IRE + jVBE(Peak) I - jVdiodel

The minimum diode voltage at this time will surely not be less than 0.5 volt.
Substituting,
VT(Peak) = (0.1989 amp)(l.05)(6.81 ohms) + 1.7 volts - 0.5 volt
V T(peak) = 2.62 volts
The peak driver power which could ever be required is
PD(Peak) = (2.62 volts)(0.0l81 amp) = 0.0474 watt
18
Servo Amplifiers

This chapter presents seven recommended class B servo amplifier circuits using
silicon power and medium-power transistors. These amplifiers are designed to
include entire parameter spreads and provide average power outputs of 1.5 to 35
watts. Their common characteristics are:
Frequency: 400 cps.
Ambient temperature: -55 to + 125°C.
Total harmonic distortion: 5% maximum at rated output.
Output Stages. The output stages follow conventional class B design except
for special techniques used to ensure thermal stability. Good thermal stability
generally requires that the ratio RBIRE be kept low, where RB and RE are defined
as in Fig. 18.1 for an ideal transistor. This ratio is usually less than four, and RE
is as large as the desired efficiency will permit.
For this reason, if a balance control is needed, it should be used in the emitter
circuit. Some resistance must be included on both sides of the balance control
(as shown in the 7.5-watt circuit, Fig. 18.4) so that RE is never too small for good
thermal stability. Disadvantages of using a balance control are that it decreases
the stage efficiency and increases the required drive voltage. This can cause the
negative signal swing to exceed BVEBO , making blocking diodes necessary.
Any bias network used in the base to decrease crossover distortion will increase
R B . Silicon diodes are used in these circuits because they minimize this increase.
The diodes also help to temperature-compensate the quiescent bias point of the
output transistors, thus preventing the transistors from moving into an unstable

Rc

Figure 18.1

238
Servo Amplifiers 239

condition as the base-emitter threshold voltage decreases with increasing tempera-


ture. This compensation is not complete, however, since the transistor and diode
junction temperatures do not conform precisely.
Since the d-c resistance of the driver transformer's secondary usually constitutes
the greatest part of R B , it is a major consideration in the transformer specifica-
tions. The 35-watt amplifier uses emitter-followers; with a negative supply, they
provide an extremely low RB for the output transistors. The + 12-volt supply can
be eliminated by connecting the collectors of Q2 and Q3 to Q4 and Q5, respec-
tively. This will reduce the output voltage, because VCE(sat) of Q4 and Q5 is
effectively increased. TI 2Nl72I's must then be used rather than 2NI720's be-
cause a higher BVCEO will be required.
The Driver Stage. The first three circuits use straightforward class A drivers.
The 10- and 35-watt circuits are modified to decrease the phase shift caused by
low primary inductance of the driver transformer. The practicable inductance
may be limited by the turns ratio, the d-c resistance of either winding, physical
size, and/or direct current present in the primary.
The lO-watt amplifier uses collector-to-base shunt feedback to lower the output
impedance of the transistor. Since this feedback also lowers the input impedance
and the gain, another stage is added. This is probably the best method for cor-
recting phase shift caused by low transformer inductance, since little driver power
is lost and since the driver would usually be preceded by a preamplifier in any case.
The 35-watt amplifier uses a constant collector load on the driver to minimize
the phase shift. Although this causes considerable power loss, the decrease in
gain is small. An alternative method involves shunt-feeding the transformer
through a capacitor; the advantage is the absence of direct current in the primary.
This technique is not used here because of the more serious power loss involved.
240 D-C and Low-Frequency Designs

18.1. 1.S-WATT CLASS B DESIGN

r-----~--------~~--------------~~----~+28v
Q2
2N696
5.11 K

Q3
2N696

1.96K

2.15 K

Circuit characteristics Transformer data


Actual power gain: 38 db min. TI-Nl = 2050 turns No. 35 A WG. N2 =
Voltage amplification: 40.5 ± 1.5 db. Na = 466 turns No. 29 AWG, bifilar
Input resistance: 1.2 kilohms min. wound. Core: Magnetic Metals 75 EI,
SL-14, or equivalent, butt-jointed.
T 2-N1 = N4 = 90 turns No. 29 AWG.
N2 = Na =433 turns No. 29 AWG,
bifilar wound. N5 = 303 turns No. 38
A WG. Core: Magnetic Metals Car-
penter 49, 0.006-in. 375 El or equiva-
lent, 8 X 8 interleaved.
Notes:
1. Q2 and Q3 on heat sinks with thermal resistance from case to ambient ~15 CO /watt each.
Two 3- by 3- by 1-8-in. copper plates with appropriate holders meet this requirement.
2. Q2 and Qa: hpE's matched 10%.
3. All resistance values are ±5% tolerance.
Fig. 18.2. loS-watt 2N696 servo amplifier (400 cycles).
Servo Amplifiers 241

18.2. 4.0-WATT CLASS B DESIGN

~-----1----------1------------------1----~~+40v
Q2
2N1718
3.32 K
0.1 Itf
100v

C1
47 Itf
23v

r Qs
2N1718
1.47 K
3.32 K

Circuit characteristics Transformer data


Actual power gain: 42 db min. T1-N1 = 1630 turns No. 35 A WG; N2 =
Voltage amplification: 42.5 ± 2.5 db. Na = 510 turns No. 29 AWG, biffiar
Input resistance: 820 ohms min. wound. Core: Magnetic Metals 75 EI,
SL-14, or equivalent, 5 X 5 interleaved.
T2-Nl = N2 = 460 turns No. 27 A WG,
biffiar wound. Na = 304 turns No. 35
AWG. Core: Magnetic Metals 75 EI,
SL-14, or equivalent, butt-jointed.
Notes:
1. Q2 and Qa on heat sinks with thermal resistance from case to ambient ~20 Co /watt each.
Two 3- by 3- by Ys-in. copper plates will meet this requirement.
2. Q2 and Q3: hFE's matched 10%.
3. All resistance values are ±5% tolerance.
Fig. 18.3. 4.0-waH 2N1718 servo amplifier (400 cycles).
242 D-C and Low-Frequency Designs

18.3. 7.S-WATT CLASS B DESIGN

~--------~~--------------~----------------------------------~----~+70v
Q2
2Nl719

6.19 K

500J.,tf
50v

3.32 K

Circuit characteristics Transformer data


Actual power gain: 45 db min. Tl-Nl = 1630 turns No. 35 A WG. N2 =
Voltage amplification: 44 ± 2 db. Na = 510 turns No. 29 AWG, bifilar
Input resistance: 1.9 kilohms min. wound. Core: Magnetic Metals 75 El,
SL-14, or equivalent, 5 X 5 interleaved.
T2-Nl = N2 = 460 turns No. 27 A WG,
bifilar wound. Na = 304 turns No. 35
AWG. Core: Magnetic Metals 75 El,
SL-14, or equivalent, butt-jointed.
Notes:
1. Q2 and Qa on heat sinks with thermal resistance from case to ambient ~12 CO /watt each.
Two 3- by 3- by 18-in. copper plates will meet this requirement.
2. All resistance values are ±5% tolerance.
Fig. 18.4. 7.S-watt 2N1719 servo amplifier (400 cycles).
Servo Amplifiers 243

18.4. 10-WATT CLASS B DESIGN

~--------~r-------~r---------------~------~+55v
QJ
2N1050

47 ).tf
23v

f •

Q4
1.96 K
2N1050
6.19 K lK

Circuit characteristics Transformer data


Actual power gain: 39 db min. Tl~Nl = 755
turns No. 32 A WG. N2 =
Voltage amplification: 32.5 ± I db. N3 = 510
turns No. 29 A WG, bifilar
Input resistance: 1.3 kilohms min. wound. Core: Magnetic Metals 75 El,
SL-14, or equivalent, 5 X 5 interleaved.
72~Nl = N2 = 450 turns No. 26 A WG,
bifilar wound. N3 = 300 turns No. 36
A WG. Core: Magnetic Metals 75 El,
SL-14, or equivalent, I X I interleaved.

Notes:
1. Q3 and Q4 on heat sinks with thermal resistance from case to ambient ~5 Co /watt each.
Two 4- by 4- by Yl6-in. aluminum plates suffice.
2. Q2 on heat sink with thermal resistance from case to ambient ~ 15 CO/watt. A 2- by 2- by
Yl6-in. aluminum heat sink suffices.
3. Q2 and Q3: hpE's matched 10%.
4. All resistance values are ±5% tolerance.

Fig. 18.5. 10-watt 2Nl050 servo amplifier (400 cycles).


244 D-C and Low-Frequency Designs

18.5. 35-WATT CLASS B DESIGN

+ 12v -40v

~-------------------r-+--------------~~+40v

Q2
2NI720 Q4
2NI722

4.32 K
TI
IN538
TI
IN538

1,000 p.f
or
25v
2NI724
lK

Circuit characteristics Transformer data


Actual power gain: 45 db min. TI-Nl = 755 turns No. 30 A WG. N2 =
Voltage amplification: 36.5 ± 1.5 db. N3 = 330 turns No. 28 A WG, bifilar
Input resistance: 700 ohms min. wound. Core: Magnetic Metals 75 El,
SL-14, or equivalent, 1 X 1 interleaved.
T2-Nl = N2 = 100 turns No. 20 A WG,
bifilar wound. N3 = 67 turns No. 28
A WG. Core: Magnetic Metals 100 El,
SL-14, or equivalent, butt-jointed.
Notes:
1. Ql on heat sink with thermal resistance from case to ambient 240 CO /watt. A 1.5- by 2- by
YJ6-in. copper plate suffices.
2. Q2 and Q3 on the same heat sink with thermal resistance from case to ambient 240 CO /watt
each. A 3- by 3- by YJ6-in. copper plate will meet this requirement.
3. Q4 and Q5 on heat sinks with thermal resistance from case to ambient 21.5 CO /watt each.
Refer to TI data sheet on these transistors, bulletin DL-S 61431, March, 1961.
4. Q4 and Q5: hpE's matched 10%.
5. All resistance values are ±5% tolerance.

Fig. 18.6. 35-watt 2N1722 servo amplifier (400 cycles).


Servo Amplifiers 245

18.6. 2-WATT DESIGN WITH HIGH EFFICIENCY

I t can be shown that a transistorized servo amplifier using unfiltered rectified


alternating current for the collector supply voltage has higher collector efficiency
than a conventional class B push-pull amplifier. * This section describes such an
amplifier, designed to deliver 2 watts into the control winding of a servo motor.
No output coupling transformer is employed, and no center tap is required on the
control winding of the motor. Negative feedback is employed to provide tem-
perature stability and interchangeability of components.
This amplifier represents a substantial improvement in transistorized servo
amplifiers. The use of this technique reduces size, weight, and power-supply re-
quirements. The higher efficiency results in greater transistor reliability, smaller
heat-sink requirements, and/or higher allowable ambient temperatures. An addi-
tional advantage is the lack of distortion caused by overdriving the amplifier.
The type of clipping that occurs in conventional push-pull amplifiers when over-
driven will not occur in this amplifier. Its output remains sinusoidal even if the
driver output is many times that required to produce full output.
Output Stage. Since the output stage is somewhat unconventional, its opera-
tion should be explained. (See the simplified circuit in Fig. 18.7.) Assume that
an input signal, V(inJ, is present which is in phase with the supply voltage, Vs.
During the first half-cycle, transistor Q4 is turned ON and Q5 is OFF. A half-
cycle of current, II, will flow from terminal A of transformer Tl through D 1, Q4,

* Bruce M. Benton, Servo Amplifiers Use Power Transistors, Electronics, pp. 153-155,
September, 1956.

1 1
1 0. 0. •
0.
V

':]
V(in)
C
B

Figure 18.7
246 D-C and Low-Frequency Designs

V(in)
C\V l'<in)~
C\
V1~

V2
CAJ V2 Cl\J
11 C\ C\
12 C\
1L
~Time_ Time-.

(a) (b)
Figure 18.8

and RL back into the transformer center tap C. During the next half-cycle, tran-
sistor Q4 is turned OFF and Q5 is turned ON. A half-cycle of current 12 will flow
out of the transformer center tap C, through R L, Q5, and D 3, then back into trans-
former terminal A.
For the condition just described, Fig. 18.8a shows the voltage and current wave-
forms vs. time when V(in) is in phase with Vs. Figure 18.8b shows the voltage
and current waveforms vs. time when V(in) is 180 out of phase with respect to Vs.
0

Note that in both cases the load current is in phase with V(in), which should be
either in phase or 180 out of phase with Vs.
0

Complete Servo Amplifier. The complete servo amplifier including preampli-


fier and driver stages is shown in Fig. 18.9.
This circuit provides the required 2-watt power output for ambient tempera-
tures between - 55 and + 125 C. Silicon transistors, solid-tantalum electrolytic
0

capacitors, and carbon film resistors were used to ensure reliable operation over
this temperature range. The output-stage operation is essentially the same as that
described above for Fig. 18.7. R 17 , R 18 , C13 , and D5 comprise a filter and divider
network to provide a d-c base bias for transistor Q4. R 19 , R20, C14 , and D6 pro-
vide a similar bias for Q5. This bias is necessary to minimize crossover distortion.
The temperature coefficient of D5 and D6 matches that of Q4 and Q5 so that the
correct bias is provided over the entire temperature range. R 16 and R21 serve the
usual emitter-resistor functions of temperature stabilization and distortion reduc-
tion. T2 is the driver transformer, and it couples signal power from the driver Q3
to the base-emitter circuits of Q4 and Q5.
The preamplifier and driver stages are direct-coupled and have considerable d-c
feedback to ensure stability of bias conditions. Positive and negative voltages are
Rs
L<L
115v rms
400 cps
1
--<
1
1
Input 1
&:. 1
or 1
/180° I
1
&:. 1
or I
/180° 1
I

5~~n~:
LI
If ~®
R22 R 23 -=-1
1
I

R12 R 13
'V\f\v VV
Parts List
Transistors Transformers
Resistors Ohms Watts Resistors Ohms Watts Ql, Q2 2N337 Tl 400-cps 4-watt power transformer.
Rl 68 K y., R lO , R l5 , R 23 l.5K 'h Q3 2N656 Step-down 115-76-volt center-tapped.
R 2, R3 22K y., Rll 680 ':4 Q4, Q5 2N1048 T2 400-cps 50-mw driver transformer:
R4 39 ':4 Rl3 4.7 K y., Turns ratio: N 1 : N 2 : N3 = 3.7: 1: 1.
'"
.j>..
'-I R5 2.2 K y., R l4, R22 390 y., Primary current = 5 rna d-c. Primary
Rs, R12 15 K y., R 16, R21 15 y., Capacitors fLf Volts
inductance ~ 1.5 henrys.
Cl 6.8 20
R7 10K y., R l7 , R l9 3.3 K 2
C2, C 3, C4, Cs 47 20 Diodes
Rs 5.1 K 1,4 R lS , R 20 470 y.,
C5* 0.1 D 1, D2, D 3, D4 1N645
Rg 100 y.,
C 7, Cs , Cll, C12 47 35 D 5 , Ds 1N482
Cg, C10 0.001
* Value depends on primary inductance of T2. Cl3 , Cl4 39 10

Fig. 18.9. 2-watt servo amplifier.


248 D-C and Low-Frequency Designs
3.0,.-----------,----------r-----------,

2.0 ------.-.

VI
:t:: 1.0
III
3: 1.5K
...s

- I
"I , Power meter

"
:l
c. Servo
Daven OP-961
:l amplifier
0
OJ I
/ , load =50012
3:
0
a..
I
II , Eg in phase with
400 cps source
/
10 100 1,000
Input (Eg), mv rms
Figure 18.10

obtained from the full-wave rectifier circuits consisting of D 1 , D 2 , and D 3 , D 4 ,


respectively. These voltages are filtered and reduced to +20 volts and -20 volts
doc by C7 , C8 , R 14 , R 15 , and Cl l, C12 , R 22 , R23 , respectively.
Negative feedback is applied to the emitter of Q3 from the amplifier output
through R13 and to the emitter of Ql from the emitter of Q3 through R 12 • Voltage
gain of the amplifier with the feedback loop closed is approximately 10,000. In-
put impedance is 10,000 ohms, and output impedance is on the order of 150 ohms.
Power output vs. input voltage characteristics at ambient temperatures of - 55,
+25, and + 125°e are shown in Fig. 18.10. At an output level of 2 watts, the
change in gain due to temperature variations is less than 3 db. The maximum
power output decreases slightly with increasing temperature, owing to the positive
temperature coefficient of the saturation resistance of the output transistors_ As
mentioned above, the type of clipping that occurs in conventional class B push-
pull amplifiers when overdriven does not occur in this amplifier. The output re-
mains essentially sinusoidal even if the input signal is many times that required
to produce full output. The output distortion is only 7% when the input voltage
is 30 db greater than that required to produce full power output.
At rated power output, the efficiency of the complete amplifier is greater than
50%. Under the most adverse signal conditions, the total dissipation of the ampli-
fier is approximately 2 watts.

18.7. 6-WATT DESIGN WITH HIGH EFFICIENCY


Figure 18.11 shows a 6-watt circuit employing the same general circuit concept.
Overall efficiency is 55%.
Design Information. The following design information is presented for those
who wish to design similar amplifiers for a specified power output.
Servo Amplifiers 249

It can be shown that the maximum power output of this circuit is given by the
formula
PO(ma:c) = (R
O.5Vs
R R
)2 RL (1)
L + es + E

where RL = load resistance (control winding of servo motor)


Vs = rms value of full secondary voltage from Tl
Res = collector-emitter saturation resistance of Q4 and Q5
RE = emitter circuit resistance for Q4 and Q5
In Eq. (1) the voltage drop across the rectifiers is neglected. The peak value of
the supply voltage, yl2vs , should not exceed the maximum collector-emitter volt-
age rating of the transistors. The peak collector current of each transistor is given
by Eq. (2).
I _ O.707Vs (2)
e(ma:c) - RL + Res + RE
The value of Res used in Eqs. (1) and (2) should be the maximum value which
may be encountered in a production spread of the transistor type used and over
the temperature range for which the amplifier is designed to operate.

+ 47 J.Lf lK TI
=!=- 35v lw IN538's

~
115v rms
400 cps

Phase

12 K

TI
IN482's
7.5 K
:r47 J.Lf
~ 15v

Transformers: Tl 400cps 12·watt power transformer step· down 115 volt to 68 volt c.t.
T2 400 cps 65·mw driver transformer. Turns ratio Nl : N2 : N3 = 2: 1 : 1
Primary current = 10 ma d·c. Primary inductance = 1.5 hy.
Fig. 18.11. 6-watt servo amplifier.
250 D-C and Low-Frequency Designs

The peak base current which must be supplied by the driver transformer is
given by Eq. (3).
I _ IO(max)
B(max) - -h-- (3)
FE

The driver transformer must provide the peak base voltage necessary to pro-
duce the peak collector current given by Eq. (2). The collector current vs. base
voltage characteristic is usually given on the transistor data sheet. The peak
driver-transformer output voltage required is given by Eq. (4),
(4)
where VB is the zero-signal bias voltage developed across diode D 5 . Since the
signal current through D5 is in the opposite direction to the bias current supplied
through D 5 , the bias must be at least equal to the IB(max) given by Eq. (3). The
same is true for D 6 .
Part 3

High-frequency Designs
19
Wideband or Video Amplifiers

This chapter discusses basic design theory for wide band transistorized ampli-
fiers, considers effects of negative feedback, offers a step-by-step design procedure,
and presents several design examples.

19.1. NEGATIVE FEEDBACK

By using negative feedback, the operating characteristics of an amplifier can be


considerably modified. In general, negative feedback stabilizes amplifier operation
and increases the bandwidth at the expense of reduced Ai andA v • This results in a
smaller change in closed-loop gain for a given change in open-loop gain brought
about by changes in transistor parameters at different frequencies. Feedback
in general can be classified as series feedback and shunt feedback.
With Negative Series Feedback. If negative feedback is accomplished
through a series resistance, Rp , as shown in the simplified circuit of Fig. 19.1, the
characteristics of the amplifier are modified as follows:
1. Input impedance, Zi, and output impedance, Zo, are increased.
2. Voltage amplification, Av = V2/Vl, is reduced, but it also becomes less
dependent on individual transistor parameters.
3. Current amplification, Ai = i2lh, is slightly reduced, but not nearly to the
extent of the Av reduction.
These characteristics are particularly useful in high-input-impedance amplifiers.

Fig. 19.1. Simplified series


feedback circuit.

253
254 High-frequency Designs

Fig. 19.2. Simplified shunt


feedback circuit.

With Negative Shunt Feedback. If a shunt feedback resistance, R F , is used


as shown in the simplified circuit of Fig. 19.2, the characteristics of the amplifier
are modified as follows:
1. Zi and Zo are reduced.
2. Ai is reduced, but it also becomes less dependent on individual transistor
parameters.
3. Av is slightly reduced, but not nearly so much as Ai.
The characteristics of shunt feedback amplifiers immediately suggest possible
application in low-input- and low-output-impedance amplifiers.
The design analysis in this section gives a step-by-step approach to design for
negative shunt feedback only, but series feedback can be analyzed in the same
manner. A circuit using a combination of series and shunt feedback is shown in
an example at the end of this chapter.
Iflow impedances are desired at the input and output of the amplifier, as is usually
the case when 50-ohm coaxial cable is used, shunt feedback networks are employed
in each stage. Since the input and output impedances are usually the same, the
amplifier will have identical voltage and current amplification.

(1)

where Ai = current amplification


Av = voltage amplification
Zi = input impedance
ZL = output load impedance
Therefore, under the condition of equal input and output impedances, the feed-
back stabilizes both Ai and Av.
Neglecting the doc bias networks, a simplified circuit of a common-emitter shunt
feedback amplifier is shown in Fig. 19.3.

Fig. 19.3. Shunt feedback


equivalent circuit.
Wideband or Video Amplifiers 255

Fig. 19.4. A-c equivalent circuit. Fig. 19.5. Simplified a-c equivalent circuit.

For the purpose of circuit analysis, this amplifier may be represented by the a-c
equivalent circuit of Fig. 19.4.
This circuit employs small-signal parameters, Yie and Yoe, and two constant-
current generators,Yrev2 and YfeV1. The current generator in the input circuit,Yrev2,
represents the component of input current, h, produced by output voltage, V2. The
Yre therefore represents an internal feedback, or reverse transfer function. The
current generator in the input circuit of this amplifier may generally be neglected
because the external feedback is much larger than the internal feedback. The
output admittance, Yoe, when multiplied by the output voltage, V2, represents the
contribution of V2 to the output current, i2. The load admittance, YL , is usually
much larger thanYoe so that the current throughYoe may be neglected. Therefore,
the equivalent circuit of Fig. 19.4 may be considerably simplified, as shown in
Fig. 19.5.
The important transistor parameters for the analysis of a low-impedance shunt
feedback amplifier are therefore Yie and Yfe.

19.2. FREQUENCY CHARACTERISTICS OF Yie, h re , AND Yte

The input circuit of a transistor, with the output short-circuited, may be repre-
sented as in Fig. 19.6: 1

where /r = frequency at which Ih,el = 1, and h'eo = low-frequency value of h,e.


When the resistance rb is small and the frequency is less than /r, rb may be neg-
lected and Yie may be approximated by

Yie = Yieo (1 + j Le) (2)

- i1

t
l
----~\tV\---i.-----~
r;'
g1
Fig. 19.6. Input equivalent Vl_ _ _ -6----'c,
circuit.
256 High-frequency Designs

where Yiea = low-frequency value ofYie


j = operating frequency
jyie = frequency at which IYiel = Vi Yiea
When the log magnitude ofYie is plotted as a function of the log frequency, a curve
of the type shown in Fig. 19.7 is obtained. Note that the curve representingYie is
asymptotic both to the low-frequency value ofYie or Yiea, and to a line crossing
Yiea at the corner frequency,fyie, and at an angle of +45 with the horizontal. The
0

45 angle on a log-log plot represents a slope of6 db/octave. Therefore, the values
0

ofYiea and jyie of Eq. (2) may be determined from a log magnitude vs. log frequency
plot ofYie measurements. This procedure provides both the magnitude and phase
angle ofYie, as defined by Eq. (2) from simple magnitude measurements.
For frequencies below Jr, hfe may be approximated by

hfe = hfeo (3)


1 + ijljhfe
where hfea = low-frequency value of hfe , and jhfe = frequency at which hfe =
(1 I V2)h feo ' When the log magnitude of hfe is plotted as a function of the log fre-
quency, a curve of the type shown in Fig. 19.8 is obtained. Note that the curve
representing Ihfel is asymptotic both to hfea and to a line that crosses the value of
hfeo at the corner frequency,fhfe, and at an angle of - 45 with the horizontal. The
0

values of hfea and jhfe of Eq. (3) may be determined from a log magnitude vs. log
frequency plot of hfe measurements. Thus, both the magnitude and phase angle
of hIe may be defined. The measurements required to evaluate Yie and hfe are
given in Chap. 5.
After equations for Yie and hIe have been obtained, a general expression for Yfe
may be derived from Eq. (4).
h 1 + i jljyie (4)
Yfe = Yie Ie = Yfeo 1 + ijljhfe

where Yfea = low-frequency value of Yfe, and is equal to Yieohfeo' Once the tran-
sistor parameters have been evaluated at the desired doc operating points, amplifier
performance may be predicted by using the equivalent circuit of Fig. 19.5 and
conventional circuit analysis.
One approach to the design of a wideband amplifier using only these measured

loglh{el

h{ea 1----_;;;;:

yieol----~

f yie log f fhre log f


Fig. 19.7. IYiel vs. frequency. Fig. 19.8. Ih'el vs. frequency.
Wideband or Video Amplifiers 257

Fig. 19.9. Redrawn a-c


equivalent circuit.

parameters follows. This approach is used in the first example at the end of this
chapter.

19.3. DESIGN EQUATIONS

The simplified a-c equivalent circuit (Fig. 19.5) may be redrawn as in Fig. 19.9.
Equations (5) and (6) are obtained by summing currents at nodes a and b.
(Yie + YF)Vl - YFV2 = i l (5)
(Yre - YF)Vl + (YL + YF)V2 =0 (6)
where the voltage amplification, A", is defined as the ratio of the output to input
voltage, V2/Vl. This ratio may be obtained from Eq. (6).

(7)

In general,Yre, Y L , and Y F will be complex or vector quantities and must be com-


bined in accordance with the rules of a-c circuit analysis. The negative sign
indicates the phase reversal obtained in the output voltage with respect to the input
voltage for a common-emitter amplifier.
If the input admittance, Yi , is defined as the ratio of input current to input voltage,
idvl' this quantity may be obtained from Eqs. (5) and (6) as follows:

Yi =Yie + YF ( 1 + Yre - YF)


YL + YF (8)

Av may be substituted in Eq. (8) to produce

Yi = Yie + YF(l - A,,) (9)


Remembering that Av is a negative quantity, Eq. (9) shows that the driving source
CiG, YG) effectively sees an admittance equal to the transistor input admittance in
parallel with the feedback admittance, YF , multiplied by one minus the voltage
amplification. If the feedback impedance is a pure resistance, the effective input
circuit of the amplifier is shown in Fig. 19.10.

Fig. 19.10. Effective input circuit:


resistive feedback.
258 High-frequency Designs

Fig. 19.11. Effective input


circuit: inductive feedback.

A shunt feedback resistor increases the amplifier input admittance, or in other


words, it reduces the amplifier input impedance. Circuit values may be chosen so
that Y i is determined mainly by the feedback term, Yp(l - A v ), while Yie has only
a negligible effect. As the voltage amplification drops at higher frequencies, the
magnitude of the feedback term becomes smaller. The effective Yi will therefore
tend to drop as Av falls off, or the input impedance will tend to rise as Av
decreases.
The effect of an inductive feedback admittance on Yi of the amplifier may be
seen from the equivalent circuit of Fig. 19.11. Since the inductive component,
-jBp(1 - A v), tends to cancel the capacitive component OfYie, circuit compo-
nents can be selected to produce a resonant effect on Yi . In other words, the input
impedance will peak at the frequency where WCie is exactly canceled by Bp( 1 - Av).
Shaping Yi , or the input impedance, of a multistage amplifier is important
because the input impedance of one stage is the output load impedance of the
driving stage and therefore affects the voltage amplification of the driving stage.
If a particular Yi is desired, Eq. (8) may be rearranged to yield the proper value
of Yp , as follows:
Yp = YL ( Y i - Yie) (10)
Yie(l + h'e) + YL - Yi
The current amplification, Ai, of the amplifier, when defined as the ratio of output
to input current, i2/i1, is given by
Ai = -AvYrZi (11)
Since Av is negative, Ai becomes positive, indicating no fundamental phase shift
in the output current with respect to the input current for a common-emitter
amplifier. If a particular Ai is desired, the required feedback admittance may be
calculated by combining Eqs. (9) and (11), as follows:
Yp = Yie(h,e - Ai) (12)
1 + Adl + ZLYie(1 + hIe)]
The effective output impedance of the amplifier may be determined by reducing
the generator current, i G, to zero and removing the load admittance, YL, for the

Fig. 19.12. Effective output circuit.


Wideband or Video Amplifiers 259

Fig. 19.13. Feedback network. L

circuit shown in Fig. 19.9. This results in the circuit of Fig. 19.12. Equations (13)
and (14) are obtained by summing currents at nodes a and b.
(Yre - YF )V1 + Y F V2 = i2 (13)
(Yie + YG + YF)V1 - YFV2 =0 (14)
The effective output impedance, Zo, of the amplifier may be defined as the ratio of
output voltage to output current, vdi 2 , with the input generator (voltage or current)
reduced to zero and the output load impedance removed, as shown in Fig. 19.12.
Using Eqs. (13) and (14), Zo may be expressed as
Zo = ZF(Yie + YG) + 1 (15)
Yle + Yie + YG
By rearranging Eq. (15), the shunt feedback impedance, ZF, may be calculated for
a particular value of Zo; that is:
ZoYfe - 1
Z F -- Z 0 + --""-'-=---=::- (16)
Yie + Y G
The circuit shown in Fig. 19.13 is the type of circuit usually used in the feedback
loop of an amplifier of this type. The admittance of this circuit is

YF = G1 1 + JwLG 2 (17)
1 + JwL(G 1 + G2 )
Equation (17) also may be written in the following form:
Y _ G 1 + Jflfb (18)
F - 11 + Jf/fa

where 1
jb = 2'lTLG2
Plotting YF as a function of frequency yields a curve of the type shown in Fig. 19.14.

">--
I
I YF =_1_
I Rl+R2
I

Fig. 19.14. Yp vs. frequency. fa h log f


260 High-frequency Designs

Thus the feedback network, shown in Fig. 19.13, will produce constant feedback
at frequencies well below the corner frequency, fa, and well above the corner fre-
quency,jb, but will produce a changing feedback characteristic between the two
corner frequencies. The desired low-frequency operation of the amplifier will
determine the resistance of R 1 • The desired high-frequency operation will deter-
mine the choice of fa and jb in the feedback circuit. The values of R2 and L may
be calculated from these corner frequencies by use of Eqs. (19) and (20).

R2 = Rl(i- 1) (19)

L = Rl(J _~) (20)


2'lT Va jb
Equations (5) through (20) may be used to predict the operation of a shunt feed-
back amplifier and as a basis for selecting the circuit values for both low- and
high-frequency operation.

19.4. SINGLE-STAGE VS. MULTISTAGE OPERATION

The voltage amplification of a single-stage amplifier may be calculated from Eqs.


(4) and (7). For a pure resistance load (i.e., YL = GL ) and no feedback, the
normalized voltage amplification becomes
Av _ 1 + jfffYie
(21)
Avo 1 + j fffhfe

where A - _ Yfeo
vo - GL

A typical plot ofEq. (21) is shown by curve a of Fig. 19.15. Ifresistive shunt feed-
back is used, the normalized voltage amplification is

1 + j!lh (22)
1 + jfffhfe

(c) R-L feedback

Fig. 19.15. Normolized


log f voltage amplification.
Wideband or Video Amplifiers 261

where

I: _ 1'. Yfeo - GF
I' /il'.
j3 - jy.e
Yfeo + GF jyie jhfe

Resistive shunt feedback reduces voltage amplification. Since j3 is a higher fre-


quency than jYie, the relative high-frequency Av with feedback is poorer than the
relative high-frequency Av without feedback. This condition is represented by
curve b in Fig. 19.15. The high-frequency Av can be improved by using RL shunt
feedback, as shown by curve c in Fig. 19.15.
Amplifiers are not fed from constant-voltage sources with negligible internal
impedances. Therefore, the frequency response of an amplifier is also dependent
upon its input impedance, Zi. Typical curves of input impedance vs. frequency,
with and without feedback, are shown in Fig. 19.16.
Curve a shows the drop in Zi as frequency is increased, for a single stage without
feedback. If this amplifier is driven from a voltage source with a constant internal
impedance, the output voltage will drop faster, with increasing frequency, than the
voltage amplification curve of Fig. 19.15 would indicate, because of the drooping
Zi characteristic.
The effect of resistive shunt feedback on Zi is shown in curve b of Fig. 19.16.
Though at high frequencies the voltage amplification is not helped by the addition
of resistive shunt feedback, as seen from Fig. 19.15, the amplifier operation is con-
siderably improved because of the fiat input-impedance characteristic, shown in
Fig. 19.16. The output-voltage characteristic, when driven from a voltage source
with a constant internal impedance, will follow the shape of the voltage amplifica-
tion curve of Fig. 19.15, over the fiat section of the input-impedance curve. At
high frequencies, the output voltage will drop faster than curve b of Fig. 19.15
indicates because of reducing input impedances.
Introduction of RL shunt feedback improves the voltage amplification charac-
teristic slightly and provides a rising input-impedance characteristic, as shown in
curve c of Fig. 19.16. If the RL feedback network is properly chosen, the effect
of the rising input-impedance characteristic will offset the drooping voltage ampli-
fication characteristic and provide almost a constant output voltage over a wide

/(c) R·L shunt


, feedback

Fig. 19.16. Input impedance


vs. frequency. log f
262 High-frequency Designs

frequency range (again this assumes that the amplifier is fed from a voltage source
with a constant internal impedance).
An amplifier fed from a coaxial cable should have a flat input-impedance char-
acteristic, with frequency, equal to the characteristic impedance of the cable, for
maximum input power to the amplifier and minimum reflection at the input
terminals. Recalling the previous discussion, a single shunt feedback stage cannot
meet this condition and still obtain a good high-frequency output-voltage charac-
teristic. Therefore, a video amplifier of this type should contain two or more stages.
The first stage should have resistive feedback to provide a flat input-impedance char-
acteristic. The other stages should have RL feedback to produce rising input-
impedance characteristics for good overall high-frequency response. The major
problem in designing the amplifier is to select the feedback networks.

19.5. SELECTING THE DIRECT CURRENT AND VOLTAGE

The optimum d-c operating point for each transistor stage is determined by the
expected performance of the circuit, the optimum transistor parameters, and the
ratings of the transistors. From a circuit standpoint, the d-c collector voltage
must be at least as large as the expected peak a-c voltage swing across the load
impedance, to prevent clipping the negative half-cycles of the output voltage. A
d-c collector voltage of twice this value is desirable, particularly for amplifiers
feeding high-impedance loads. For similar reasons, the d-c collector current must
be at least as large, preferably twice as large, as the expected peak alternating
current delivered to the load impedance. A low-impedance amplifier will require
relatively large current swings. For example, a peak sinusoidal current of 28.28
rna will be required to produce 1 volt rms across a 50-ohm load. Therefore, the
maximum output voltage of a low-impedance amplifier will usually be limited by
the collector current and power-dissipation ratings of the transistor. Consequently,
a large d-c collector current, at least in the last stage, is desirable.
The h fe is not very dependent on d-c collector current and voltage. Very small
or very large collector currents and voltages result in reduced values of h fe • For
example, a 3N35 has a peak value for h{e at about 1.5 rna and 20 volts. However,
a very little change in h{e is obtained with a 2: 1 or 3: 1 change in d-c collector
voltage or current. The d-c operating point that will produce the most favorable
hfe characteristic can usually be determined from the transistor data sheet. If this
information is not available, it can be determined from curves plotted from ex-
perimental measurements. In general, d-c collector currents larger than those
recommended by the data sheets will produce smaller low-frequency h{e values
and poorer high-frequency hfe characteristics.
The value of Yie is quite dependent on collector current. The approximate rela-
tionship betweenYie and emitter current is given in Eqs. (23) and (24).2
IE (23)
gie:::: 26h feo

IE (24)
Cie = 52'TTfT
Wideband or Video Amplifiers 263

where IE = d-c emitter current, ma, and


Yie = gie + jweie
These equations show that Yie varies directly with collector current. Since the
voltage gain of the amplifier varies almost directly with Yte, which is the product
of Yie and hte , it would immediately appear that a large collector current is desira-
ble in the amplifier. It is true that when the collector current is increased in a
particular amplifier while the d-c collector voltage is held unchanged, the overall
voltage amplification does increase. At the same time, however, the input imped-
ance of the amplifier is reduced by approximately the same amount. If the feed-
back network in the first stage is readjusted to provide the original input imped-
ance, essentially no change will be observed in the overall voltage amplification
for increased collector currents. Thus, no advantage in overall voltage gain can
be obtained by raising the d-c collector currents above the optimum h te value,
because the overall voltage gain must equal the overall current gain in an amplifier
having the same input and load impedances. On the other hand, the d-c collector
current in the first stage should be relatively low so that the input admittance will
be large compared with Yie. In other words, the input impedance will be fixed by
the feedback circuit rather than by Yie'
To summarize, the collector current in the last stage should be high in order to
provide a high output voltage, but the collector current in the first stage should be
low in order to stabilize the input impedance.

19.6. DESIGN PROCEDURE

In example 1 (Sec. 19.7) the steps detailed below were performed in the order
shown.
Design of D-C Circuit. The combination of biasing resistors that determines
the transistor and circuit direct voltages and currents is the d-c circuit. This cir-
cuit is designed as follows:
1. Select bias circuits.
2. Select transistor direct voltages and currents.
3. Select d-c supply voltage and its distribution across the transistors and
bias resistors.
4. Calculate bias resistors from the circuit of step 1 and the voltages and cur-
rents of steps 2 and 3.
Determination of Applicable Parameters. As shown in the design section
(Sec. 19.3), the only transistor parameters of importance in the analysis of a low-
impedance shunt feedback amplifier are the admittance parameters, Yie and Yte, or
the hybrid parameters, hie and h te . It is slightly more convenient to evaluate hte
andYie. ThenYte is obtained from the product OfYie and hte . They may be evalu-
ated by either of two methods. The first method is graphical determination:
1. Measure a-c input voltage, input current, and output voltage, for a 50-ohm
collector load resistance at desired d-c operating point of each transistor,
and over desired range of operating frequency.
264 High-frequency Designs

2. Calculate Ih{el and IYiel values from the measurements of step 1 at each
frequency.
3. Plot Ih{el and IYiel on log-log graph paper as functions of frequency.
4. Determine magnitudes of low-frequency values of h(e and Yie and their
corner frequencies from curves obtained in step 3.
The second method is determination of hfe and Yie from a set of high-frequency
measurements:
1. Measure magnitudes of hfe and Yie at any convenient low frequency.
(These are the values of hfeo and Yieo.)
2. Measure magnitudes of h{e andYie at any convenient high frequency,j3,
well above their corner frequencies.
3. Calculate corner frequencies from these measurements and the equations:

!yie = !3 (25)
V (Yie3/Yieo)2 - 1
where !yie = corner frequency ofYie, and Yie3 = value ofYie at frequency j3.

!hfe = !3 (26)
V(hfeo/hfe3)2 - 1
where !hfe = corner frequency of hfe , and hfe3 = value of hfe at frequencY!3.

Design of Low-frequency A-C Circuit. The low-frequency current amplifi-


cation, voltage amplification, and input impedance of each stage are determined
by the transistor parameters, the low-frequency feedback resistor between collec-
tor and base, and the effective collector load impedance. The major factor in de-
signing the low-frequency circuit is selecting feedback resistors that will provide
the desired overall Ai and A v , the desired division of Ai between stages, and the
desired input impedance. In general, a compromise must be made between Ai
and A v , and frequency coverage. For a given amplifier, an increase in operating
frequency entails a reduction of Ai and Av. The maximum useful frequency may
be estimated from hfe and A io . Av will be down 3 db at the frequency where hfe
equals A io .
The low-frequency a-c circuit may be designed in the following steps:
1. Select Ai, with feedback, for each stage. Allow 4 or 5 db for loss in bias
networks and for input-impedance correction in the first stage, so that
the total indicated Ai will be slightly higher than the desired overall Ai
for the amplifier.
2. From Eq. (12), calculate feedback resistor, R 1 , for the last stage to pro-
vide the desired low-frequency Ai. Note that ZL is the effective load im-
pedance, and includes the parallel combination of the a-c load and the
d-c collector bias resistor.
3. Calculate Av and input admittance, Yi , of the last stage from Eqs. (7) and
(9). Note that Y i , as calculated from Eq. (9), must be corrected because
the bias circuit shunts the transistor input circuit.
Wideband or Video Amplifiers 265

4. Calculate feedback resistor, R 1 , for the second stage, using the procedure
explained in step 2. Remember that the a-c load impedance of the
second stage is the input impedance of the last stage after correcting for
the effects of the d-c collector bias resistor.
5. Calculate Av and Y i for the second stage, using the procedure described
in step 3.
6. From Eq. (10), calculate feedback resistor, Rl, for the first stage to pro-
vide the desired value of input impedance, Zi.
7. Calculate Av of the first stage, using the method described in step 3.
8. Calculate capacitances of the coupling capacitors, from calculated input
impedances and the lowest desired operating frequency.
9. Connect the low-frequency circuit, and compare measured Av and Zi with
calculated values.
10. Any correction in input impedance may be made by adjusting the first-
stage feedback resistance. Overall voltage amplification may be corrected
by adjusting d-c supply voltage or the currents of individual stages.
Design of High-frequency A-C Circuit. A typical voltage amplification vs.
frequency plot for an amplifier with resistive feedback only is shown by the solid
line of Fig. 19.17. One effect of shunt feedback is to reduce Zi for that stage. If
the feedback network for one stage is designed to decrease feedback as frequency
is increased, Zi of that stage will have a rising impedance vs. frequency character-
istic. Therefore the preceding or driving stage will have a rising voltage amplifi-
cation vs. frequency characteristic. A feedback circuit that has this property was
shown in Fig. 19.13. By using RL feedback networks in the last two stages and
selecting proper corner frequencies for these networks, the three-stage voltage
amplification vs. frequency characteristic can be changed from the solid line to
the dotted line, as shown in Fig. 19.17. Since the value of Rl is determined by
the low-frequency circuit after the corner frequencies for the feedback network
are selected, the values of R2 and L in Fig. 19.13 may be calculated from Eqs. (19)
and (20).
The following procedure may be used to design the high-frequency circuit:
1. Measure and plot the Av vs. frequency characteristic of amplifier with re-
sistive feedback only, using db an,d log frequency scales. It will be noted

R.LShunt
(
feedback
--------- ........ "
\
,,
\

Resistive shunt
,,
feedback
Fig. 19.17. Av vs. frequency:
resistive feedback. log f
266 High-frequency Designs

that Av starts dropping at or near the h(e corner frequency of the last
transistor.
2. In the last stage, add a high-frequency feedback network having values of
fa equal to the h(e corner frequency of the last transistor and fi equal to or
greater than the highest expected operating frequency as determined by
intersection of the low-frequency Ai with the hie vs. frequency curve of the
last transistor. R2 and L may be calculated from Eqs. (19) and (20).
3. Measure and plot the Av vs. frequency characteristic of the amplifier after
completing step 2. Considerable improvement will be observed at the
high-frequency end of the curve.
4. Select values of fa and fi for second-stage feedback network from the curve
obtained in step 3. A value of fa should be selected at or near the
frequency at which Av begins to drop. A value of fb may be selected at a
frequency above fa.
5. Measure and plot the Av vs. frequency characteristic of the amplifier after
step 4 has been completed. If the selected value offi was too large, a pro-
nounced peak will be obtained at the high-frequency end of the character-
istic. If fb was too small, the high-frequency operating range of the
amplifier will be too small. Two or three trials should be sufficient to de-
termine optimum values for the corner frequencies of the second-stage
feedback network.
6. Measure and plot the Zi vs. frequency characteristic.

19.7. CIRCUIT EXAMPLES

The following three circuits show the results obtained by using feedback to ex-
tend the frequency response of a transistor for use in wideband applications.
Circuit Example 1. The three-stage silicon wideband amplifier shown in Fig.
19.18 applies the design procedure described in Sec. 19.6. It employs feedback
around each of its three stages.
Design objectives for this amplifier were:
1. Voltage and current amplification of 20 db.
2. Flat frequency response to as high a frequency as possible.
3. Input impedance of 50 ohms when feeding a 50-ohm load.
4. Output impedance of 50 ohms when driven from a 50-ohm voltage source.
It will be noticed that a zener diode has been added to each stage of the ampli-
fier. This is done to stabilize VCE. Since Yie is very dependent on I c, the amplifier
should be operated from a well-regulated d-c voltage or from a constant current
d-c source to stabilize Av.
Frequency response of the circuit is shown in Fig. 19.19.
Circuit Example 2. The three-stage 50-mc wide band-amplifier circuit shown
in Fig. 19.20 is a very good example of the maximum bandwidth which can be
achieved with a given transistor using standard stability criteria for wideband
amplifiers in the design. Because of the difficulties involved with instability at
high frequencies, it is difficult to apply feedback over more than two stages at a
Wideband or Video Amplifiers 267

~--------------~~----------------.----o+30v

+11-.
0.01 ~
RL
'--+-+-+--+----1---, 50 12
I
82K I
I
I
I
Input I
I
I
I
I

-=-
~ r;,: ,'," ---L- s,,,:, "," -L l,"~""
Fig. 19.18. Video amplifier.

time. It will be noted here that the feedback is over three stages in this example,
but the design includes stability considerations to provide for this.
The delay characteristics of a transistor can be approximated by the equation
e-jmflfa

a = aD 1 + Jf/fa
24

20 ~:-"_ ... _)(-"_)(O _~)(


r ....
..Cl
""0
c:: 16
L
(~
I
"
Useful frequency range
"
I \
:;:;
co
u
o
I "'--3.2kc 32mc/\
~
Ci 12 ".

.&
E
co
Ql

8
\
"0
>
" = measured response
\
4

o I
0.001 0.01 0.1 10 100
Frequency, mc
Fig. 19.19. Video amplifier frequency response.
268 High-frequency Designs

O.5pf

2.5 J.!h 150 n 100 pf

250J.!h
4.3 K

300
pf

5.1 K

6.8K 3.5K 3.4 K 1.8 K

~----------------r-----~----------------~r------+----~-45

~--------~------------------------+---------------~--------o+45
Bias
Ve=-5v
Ie =10 ma
Fig. 19.20. Diffused-base feedback amplifier.

which shows the excess phase that the transistor has in addition to the phase shift
exhibited by the simple minimum phase network which approximates its ampli-
tude response.
The design objectives for this amplifier were:
1. An external current gain of 34 db, flat to within 0.01 db up to 5 me, and
flat to 0.1 db up to 10 me.
2. A negative feedback of 34 db to be maintained from 50 kc to 5 me.
3. A match between a 3,OOO-ohm source to a 75-ohm load to within 5% over
a frequency range of 50 kc to 5 me.
The transistor used should be similar to the 2N2415, a diffused-base germanium
mesa. It should have a low-frequency common-base current gain, ao near 0.97,/t
near 600 me, low collector capacity Cc less than 1 pf, low collector body resistance
r~ less than 20 ohms, and emitter body (point) resistance re less than 5 ohms.
The d-c biasing uses both series and shunt feedback to each stage. This pro-
vides an extremely stable d-c circuit, enabling the circuit bandwidth to be extended
to d -c if necessary.
Wideband or Video Amplifiers 269
40

..c
""0
C 30 ~
ro
tl.O
C
\
~ 20
::l
(,)

10 I I
100 ke 1 me lOme 100me
Frequency

Fig. 19.21. Current gain, db vs. frequency.

The f3 network is a bridged T network which appears resistive at mid-band.


The shunt arm of the T contains a series capacitor which provides a rising asymp-
tote for the Af3 gain characteristic at low frequencies, and the capacitor which
bridges the T provides a high-frequency rising asymptote. A compensating net-
work is placed in series with the bridged T in order to keep the f3loss flat to 10 me.
The Af3 characteristic, without interstage shaping, is flat at 34 db up to 25 me,
where, because of the transistor's current-gain cutoff, it falls at a rate of 18
db/octave to 50 me, where the rising asymptote of the f3 network reduces this to
12 db/octave. Since the rising asymptote occurs outside the usable band, the
inband characteristics are not appreciably affected.
To approximate an ideal Bode cutoff, the gain between 5 and 100 me is shaped
with the series interstage networks. The Bode fillet is added at 7 me by the first-
stage feedback so that Af3 is down 3 db at 7 me.

Vee = -30volts±25%

12 K 1K 0.001 J.lf

2N2188 180 J.lf

180 0.001
Re
82!2 J.lf J.lf

Fig. 19.22. Wideband amplifier.


270 High-frequency Designs

60 ,

Open loop gain


50
V -......
.c
': 40 ~
~
c:
o
:;::;
co
u

c.
30

1\
E V(out)
co
Voltage gain = 20 log - -
~ V(in)
~ 20
~
10
Vee = -30v
TA=25°C
\'rin)= 10 mv _\
o
10
,..- \
Frequency, cps

Fig. 19.23. Typical frequency response of wideband amplifier in Fig. 19.22.

The emitter bypass capacitors control the low-frequency response with the first-
stage bypass providing a roll-off frequency of approximately 50 kc. The other two
stages extend to under 0.5 kc to provide stability.
The frequency response of the circuit is shown in Fig. 19.21.
Circuit Example 3. A two-stage amplifier is shown in Fig. 19.22. D-c feed-
back provides stable doc operation with parameter variations encountered in the
normal production spread, as well as those caused by changing temperature.
Supply-voltage variations of +25% have a negligible effect on the performance of
the amplifier.
The a-c feedback is a combination of the two types discussed earlier: shunt and
series. A portion of the output is fed back in series with the input. This extends
the bandwidth and stabilizes the amplification. It also reduces the output imped-
ance and increases the input impedance.
Typical open-loop amplification is 48 to 50 db. R f controls the closed-loop
amplification, A Cl . ACl can be approximated by

ACl = AlA2
I - AlA2 Re/Rf
where AlA2 = open-loop amplification, which is the product of the amplification
of stages 1 and 2
Re = unbypassed emitter resistance of the first stage
R f = value of the feedback resistor
Wideband or Video Amplifiers 271

The open-loop bandwidth is 1 mc, and the bandwidth at 30-db closed-loop


amplification is 17 mc. Figure 19.23 shows the typical frequency response of this
amplifier.

BIBLIOGRAPHY

l. Pritchard, R. L.: Electric Network Representation of Transistors, IRE Trans., vol. CT-3,
p. 14, March, 1956.
2. Hunter, L. P.: "Handbook of Semiconductor Electronics," p. 4.12, McGraw-Hill Book
Company, Inc., New York, 1956.
20
Low-level RF Stage Stability

20.1. UNILATERALIZATION
A serious problem in RF and IF amplifiers is the internal feedback of the device.
Because of internal feedback, a general range of frequencies exists for which a tran-
sistor can be made to oscillate by properly choosing passive terminations. In
addition, internal feedback causes the transistor input impedance to be a function
of load impedance. This makes multistage IF amplifier alignment difficult.
In general, two design methods are available to overcome internal feedback
effects. One technique is to neutralize the effect of the reverse feedback ratio or
unilateralize the transistors in the amplifier. The second technique involves mis-
matching the transistors. (Mismatching is considered in the next section.)
Neutralization is the process of balancing out an undesirable effect. Unilateraliza-
lion may be defined as a method for converting a bilateral four-terminal network to
a unilateral network. Comparing the definitions, it is clear that unilateralization
is a special type of neutralization. However, the reverse is not necessarily true.
For example, hum-neutralized circuits are not unilateralized.
Unilateralization vs. Mismatching. Unilateralization offers three advantages:
First, if the transistor is exactly unilateralized, the stability of the amplifier stage
is completely independent of passive networks connected at the input and output
of the stage. Second, the input and output circuits are completely isolated from
each other. The input and output impedances of the transistor are independent
of the load and generator impedances, respectively. Third, by conjugate-matching
the generator and load impedance to the transistor, power gains may be obtained
very nearly equal to MAG.
Unilateralization has three serious disadvantages. First, for the design method
to be useful, the unilateralization network must very nearly eliminate the internal
feedback of the transistor. In practice, the passive network may have to be tailored
for each transistor individually. Second, unilateralization circuits often employ a
transformer for phase inversion; these transformers limit the unilateralized band-
width. Furthermore, if a transformer is avoided, the passive network can only
roughly unilateralize the transistor over a broad band. For this reason, unilaterali-
272
Low-level RF Stage Stability 273

zation techniques are usually limited to narrow-band, high-gain applications. A


third disadvantage is that the amplifier may become unstable if the transistor
parameters vary.
The mismatching design technique, on the other hand, has three important
advantages: First, stability may be ensured for all transistors of a particular type.
Second, the input impedance of a stage can be made essentially independent of the
load impedance, permitting practical multistage amplifier alignment. Third, the
design technique is particularly useful in broad-band applications.
Unilateralized Gain. I The derivation of the high-frequency unilateralized gain,
G u, starts with two basic relations using the transistor's four-terminal admittance
parameters.

I~~I = I;~~ ;~~II~~I (1)

For admittance unilateralization, a second two-port network is added in parallel


to the transistor,
Y = I Yn (2)
-Yn
such that IYnl = Y12 (3)

The combined matrix of transistor plus unilateralizing network is

I ~I[ =
12
[(Yll + Y12)
(Y21 - Y12) (Y22
0
+ Y12)
[IVII
V2
(4)

For conjugate-matched input and output,

=
lill2
P(in) ---:=--:-'--'----,-- (5)
4Re (Yll + Y12)
where the Re represents the real part of the complex expression.

p(ont)
1(Y2I - Y12)V112
= -'-:-'::"--,---"---'-----'-:- (6)
4Re (YZ2 + Y12)
G u = 41 (Y21 - Y12)Vl 12 Re (Yll + Y12) (7)
4Re (Y22 + Y12)1ill2
Since

Vll2
Ii; =
l I
2Re (Yll + yd
]2 (8)

Gu = IY2I - Y121 2 (9)


4Re (Yll + Y12) Re (Y22 + Y12)
Equation (9) is the G u of the composite network. Ordinarily, this equation is used
in a simplified form.
274 High-frequency Designs

Defining
h'
21 = Y21 - Y12
Yll + Y12
(10)

1 (11)
M1=
+ Y12
Yll
and Re yb = Re (Y22 + Y12) (12)

then Gu = Ihhl 2 (13)


4Re Y22 Re hll
If Y12 ~Yll (14)

then Gu = Ih21 + h1212 (15)


4Re hll Re Y22
where h21 and h12 are the unneutralized network parameters.
If two other approximations can be made,
h21 ~ h12 (16)
and Re Y12 ~ Re Y22 (17)
the power gain then reduces to
Gu = Ih2112 (18)
- 4Reh ll ReY22

This expression is also referred to as maximum available gain, MAG.


Methods of Unilateralization. 2 Three methods* for unilatera1izing common-
emitter circuits are shown in Fig. 20.1. In the bridge circuit, the combination L
and CFprovide the necessary phase shift in the output signal (approximately 180°).
Land CF should resonate at a factor of 5 or more below the center frequency of
the amplifier passband.
If E1 is the voltage across the parallel resonant circuit, E2 is the voltage across
CF , and I is the signal current through Land CF , the following equations obtain:

I = ~ for X CF ~ XL (19)
jWoL
E1 1
E2 = IXcF = -.-- -.--
jWoL jWoCF
(20)

since woL=_l- (21)


woC1

and (22)

* See Ref. 2 for other practical circuits.


Low-level RF Stage Stability 275

The bridge is completed by feeding back E2 to the input across a capacitance:

CN =Cp
C1 Cc (23)

This provides a feedback current equal to, but 180 out of phase with, the internal
0

current feed-through Ce .
The capacity tap circuit is similarly designed. The transformer provides the 180 0

phase reversal, and CN should be chosen so that

(24)

1
fo» 27r..jLCF

(b)
I

(c)
I
Fig. 20.1. Methods of unilateralization: (a) capacitance bridge circuit; (b) capacitance tap
circuit; Ie) inductive feedback circuit.
'"
~

10 pf 10 pf 10 pf 0.5-3
pf 8.0 pf

0.02 }.If 0.02 }.If 0.02 }.If 0.02 }.If 0.02 }.If

6.2K 6.2K
6.2 K 6.2K
L12 L 13 L14
'-----~uwu UWU' UWU 0-12 v

L10 L8 ·3.5}.1h 23 turns #36 heavy Formvar closewound on Cambion LS·9 form
L 2 , L 4 , L6 -0.53 }.Ih 9 turns #36 heavy Formvar space 1M.' apart on Cambion LS-9 form
L 3 , L 5 , L7 -5.3 }.Ih 29 turns #36 heavy Formvar closewound on Cambion LS-9 form
L9-L14 -15 }.Ih rfc

Fig. 20.2. 30-mc IF amplifier: 3-mc BW, 65- to 75-db gain, all transistors 2N1405.
Low-level RF Stage Stability 277

The inductive feedback circuit should satisfy the approximate condition

LN=_l- (25)
wo2Cc
The circuit shown in Fig. 20.2 employs the unilateralization shown in Fig. 20.la.
Design Example. To design the unilateralization circuit, a scheme for inter-
stage coupling must be chosen. The capacitive coupling network shown in Fig.
20.3 was used.
In this design:
Ql = loaded uncoupled Q of the primary
Q2 = loaded uncoupled Q of the secondary
k = coefficient of coupling
The following assumptions are made:
1. Ql = Q2
2. k < kc; k is larger than the value for critical coupling or flat response. This
condition yields a double-peaked response. The ratio of output voltage at
either peak to that at the valley (center frequency) is given by

E(valley) 2k/kc
(26)
E(peak)

where (27)

E(valley)
Therefore, (28)
E(peak)

Cl
Rt[~~! -lJ21T f o

Rio L l • C l are total Ql = Primary loaded Q Ll = 1


parallel RLC of primary (21Tfo)2C l
=QL
R 2 • L 2 • C 2 are total Q2 = Secondary loaded Q -
C2- Qu
parallel RLC of secondary
=QL
R2[~~ -l}1rfo
For 1 db peaks to valley gain ratio
kQ L = 1.63 L2= 1
(21Tfo)2C2
QL=B.,)o
PK·PK
-VCk QL)2-1 k= 1.63
Qu = Unloaded Q of coils QL
to = Center frequency CM =k,JC l C 2

Fig. 20.3. Design equations for capacitive coupling.


278 High-frequency Designs

If 1 db is specified as the allowable ripple, it follows that


kQL = 1.63 (29)
The other important relationship is

QL = BW(pk_pk)
/0 y(kQL)2 - 1 (30)

The design of Fig. 20.2 is now given:


B W(Pk-pk) = 3 mc Qu = 50 /0 = 30 mc
For the 2N1405,
= 18 kilohms and Coep = 2 pf
roep
From Eq. (29), kQL = 1.63, (kQL)2 = 2.65, and from Eq. (30),

QL = 330 ; 1~6 Y2.65 - 1 = 12.9

50
18,000(50/12.9 - 1)6.28 X 30 X 166 = 5.2 pf
Allowing for transistor capacitance variations and circuit strays, let
C1 = 1 to 6 pfvariable capacitor Ll = 5.3 ph
For the secondary:
riep = 1.8 kilohms Ciep = 13 pf
50
C tot 1,800(50/12.9 _ 1)6.28 X 30 X 106 = 52 pf
Again allowing for circuit conditions and transistor variations, set
C2 = 8 to 50 pf variable capacitor L2 = 0.53 p.h
Since kQL = 1.63 and QL = 12.9 k = 0.126
C M = kyCtotPriCtotsec = 0.126Y52 X 5.2 = 2 pf

To allow for alignment adjustment, use a variable capacitor.


CM = 0.5 to 3 pf
The unilateralization network may now be designed. For
CF = 100pf Cc = 0.5pf CN = 10%(0.5) = 10 pf

20.2. MISMATCHING

General Theory. A second method of achieving stability is by the mismatch


technique. If the device is mismatched at its input and output terminals, useful
stable gains can be obtained up to very high frequencies and over broad bandwidths.
Low-level RF Stage Stability 279

Fig. 20.4. Single-stage two-port driven and terminated.

Two-port theory using admittance parameters provides a convenient approach


to the problem. Figure 20.4 shows the single-stage equivalent circuit. The general
transducer power gain is
GT = 41 Y 21 12GgGL (31)
[(Yn + Yg)(Y22 + YL ) - Y12 Y21 12
Equation (31) is not a stable gain in many cases. Note that for a conjugate match
of Yll and Y22 , if the Y12 Y 21 product is real, the denominator may approach zero.
However, these very high gains can be realized only at the expense of stability.
Oscillation is interpreted as the case where GT equals infinity.
The power gain of a unilateralized network is given by Eq. (18) as
Gu~ Ih2112
4Re hll Re Y22
The typical unilateralized power gain is plotted in Figs. 20.5 to 20.8 for the TI
type 2N1141 series germanium mesa transistor, at two bias points for the frequency
range of 60 to 400 mc.

28

24
VCB = -10v
Ic= -10 ma
20

2N1141
I I
I'-
.0 16
2NP4.2 r--. "'"
"~~
-0

2N1143 r--.
ro
12 ~

,"'
Cl
"-
8 ~ 1\
~
4

o
10 100 1,000
Frequency, mc
Fig. 20.5. Common-base unilateralized RF power gain.
280 High-frequency Designs

28

24
VeE = -lOv
Ie= -5 ma
20

.0 16 2N1l41
v I I

'" "
c- 2N1l42~
I I
"
('(l
(9 12 2N11431'

8 ~ i'.. r\.
4
"
~~
a
10 100
Frequency, mc
'" 1,000

Fig. 20.6. Common-base unilateralized RF power gain.

The optimum conditions of mismatch, i.e., highest gain for a given degree of
stability, have been determined by several authors.3, 4 These are:

Gg = mGl l (32)

That is, the parallel input and output conductances measured with the other port
short-circuited must be mismatched by the same factor, m.
28

2NIllL
24 I\.
VeE=-lOv
2Jl1i2~ Ie= -10 ma
20

~
2N11d-3
~
.0 16
v

('(l
(9 12
\\ ~
8
\ ~~
\.

4
\ ~
a
10 100
\ 1,000
Frequency, mc
Fig. 20.7. Common-emitter unilateralized RF power gain.
Low-level RF Stage Stability 281

28

24
VCE = -lOv
2Nrr' Ic= -5ma
20
llY,
..0
"0
e-
16
2N1
2N1l43,
",
"\."
"
m
(!l 12

a
10
""\.'
100
'\

1\
~
~

1,000
Frequency, mc
Fig. 20.8. Common-emitter unilateralized RF power gain.

The RF gain stability factor, p, is defined by the equation4


2(Gl l
p=~~~~-=~--~~~
+ G )(G22 + GL )
g
(33)
IY21Y121 (1 + cos L Y21Y12)
If p> 1, the stage will be stable; however, well-designed stages will provide a
stability margin of p = 5 or more. The advantage of an amplifier having a high
stability factor is its gain stability with variations in temperature and bias, and with
interchange of transistors. It can be shown that p at a given frequency will be a
function of m alone and will have the following form:
p = p'(1 + m)2 (34)
The coefficient p' is plotted against frequency for the 2Nl141 series in Figs. 20.9
through 20.12. Based on these figures, it appears desirable from the standpoint of
stability to design amplifiers in the common-base configuration at frequencies
above 100 mc. The tendency of the common-emitter configuration to be unstable
at higher frequencies is believed to be due to the feedback introduced through the
header-to-collector connection.
The transducer power gain of a stage which is stabilized by mismatch will now
be calculated. This will be done by computing a loss factor, which, multiplied by
Gu, will yield the mismatched transducer gain, GTM ; L is the product L 1 L 2, which
is defined as

Ll = P OM (35)
PIMG u

and L2 = PPIM (36)


A
282 High-frequency Designs

7 ,
6
"
"
5 " ,
4
-
<:\.

Common base
~---+'~--+--+---l---+- V CB = - 10 v
Ic= -lOma

o 100 200 300 400


Frequency, mc
Figure 20.9

where P OM = output power for a mismatched condition


P IM = input power for a mismatched condition
PA = available power from the generator
In logarithmic form,
GTM (db) = 10 log Gu + 10 log L (37)
L will be shown to be a function of m only, as in the case of p (see Fig. 20.13).
7

6
Common base
Typical curve
5 V CE = -lOv
Ic=-5ma
4
-
<:\.

o 100 200 300 400


Frequency, mc
Figure 20.10
Low-level RF Stage Stability 283

6
Common emitter
Typical curve
5
VcE=-lOv
Ic=-lOma
4
2N1l4;............

3
2N1l1 2............
~
2
2N1l43..........
,\ \.
"- ~ V
""'"
J'

~ ~
o 100 200 300 400
Frequency, mc
Figure 20.11

To calculate GTM, take the difference of the unilateralized transducer gain read from
Figs. 20.5 to 20.8 and the loss factor read from Fig. 20.13. The stability factor may
then be evaluated, using Eq. (34) and the data from Figs. 20.9 to 20.12.
L will now be calculated. If the input and output susceptances are canceled by
tuning, the output power is given by

(38)

6
2Nllf\ Common emitter
Typical curve
5
V CE = -lOv
2N1l12 Ic= -5 ma
4 2N1l43

3 \
2 \ '\~
~~ "'- ~
~
..............
--- /"
-'"
o 100 200 300 400
Frequency, me
Figure 20.1 2
284 High-frequency Designs

4
....
.s v V
~ 3
..<:: ~
B
'"EII) 2 "". V
V'
~
~
V
---
a 2 4 6 8 10
Loss factor, db
Fig. 20.13. Loss factor vs. mismatch factor.

Furthermore, if the stage is mismatched at input and output by the factor m,

POM = IY2112112GL (39)


I(m + 1)2Gl lG22 - Y12Y2112
In most cases Gl l G22(m + 1)2 ~ Y12Y21, and
POM = IY2112112GL (40)
I(m + 1)2Gl l G2212
The input power available for amplification by the transistor when mismatched
can be seen from Fig. 20.14 to be
P _ 112
-o(m-+-==-l):-::2--=G:- (41)
1M - g (m + 1)2Gl l
The power gain under mismatch is then
GTM = IY2112GllGdm + 1)2
(42)
I(m + 1)2Gl l G2212
and, because GL = mG22 ,
m IY21 1
2
(43)
GTM = (m + 1)2 Gl l G22
If this expression is normalized with respect to G u, the ratio is the first loss factor:
4m
(44)
L1 = (m + 1)2
The second loss factor is simply the ratio ofEq. (41) to the power available from
the generator, PA = 112/4Gg :
4m
(45)
L2 = (m + 1)2
Low-level RF Stage Stability 285

(m-l)G l l
Resistive
loading

(1) Net input and output susceptances have been tuned out
(2) I1 and its internal impedance have been transformed so
that Re Yg =Re Yil= G ll
(3) Mismatch has made Yll negligible

Fig. 20.14. Equivalent circuit for calculating mismatched gain.

The composite loss factor, L = L 1 L 2 , is given by


L = 16m (46)
(m + 1)4
In logarithmic form,

L (db) = 10 log 16m (47)


(m + 1)4
and the mismatched transducer gain is, therefore,

GT (db) = 10 log G u + 10 log 16m (48)


(m + 1)4
Measurement of Characteristics. The design data presented in Figs. 20.15 to
20.20 were taken on a General Radio 1607A transfer function and immittance

140

120
V CB = -lOv
Ic=-lOma
100

en
0
.s:: 80
E
-
"" 60
>-<'"

40

20

0 100 200 300 400


Frequency, mc
Fig. 20.1 S. Magnitude of forward transadmittance common base vs. frequency.
286 High-frequency Designs

1,000

900 \ ~ V CB = -lOy

800 ~ Ic= -lOrna

<II
E
..c: 700
2Nll4l" I"--
-
..........

~
0

~I~ 600
0 ~1142
~
500

400
"'
2Nl~ - ....
-~
.........

o 100 200 300


"--~ 400
Frequency, mc

Fig. 20.16. Parallel output resistance common base vs. frequency.

bridge. These are the typical characteristics of several tested samples. The accu-
racy of the measurements is + 10%.
The 1607A bridge is a coaxial instrument which is capable of measuring two-
port admittance and hybrid parameters in the frequency range of 25 to 1,500 mc.
The range of the measurements in this report was restricted to 60 to 400 mc be-
cause this range covers most of the applications of the 2N1141 series.
The test-equipment block diagram is given in Fig. 20.21. The signal source is a
175
2~1143

-
150 - 2N1142-

~
VCE = -lOy

125
Ic= -lOrna
/
<II
E
..c:
0
100

~/
/ ~ ~
./
- 2N114l

~
IJ. 75 /
~V
Rj

50 ~
~/ , /
25
~

0 100 200 300 400


Frequency, mc
Fig. 20.17. Parallel input resistance common base vs. frequency.
Low-level RF Stage Stability 287
140
~N1141
120

100 1\\ VCE = -lOv


Ic= -10 ma

Ul
0
..c:
2N114~ i\
80 "

~'"
-
E
. \ I\.
~. 60

40
2Nl1~ "
" r-- -
~

~ r--.....
.........
~
~

20

0 100 200 300 400


Frequency, mc

Fig. 20.18. Magnitude of forward transadmittance common emiHer V5. frequency.

Hewlett-Packard 608C VHF generator which is set to 50 to 100 mv, depending on


the measurement being taken. The null detector employed is a Nems-Clarke
1502A receiver with a Nems-Clarke REV 300B frequency-range extension unit.
Nulls of about 1 /LV were obtained.
No input susceptance data are given in the graphs because they are immaterial
in the power-gain calculations. Table 20.1 gives data representative of these
characteristics over the 60- to 400-mc frequency range.
1,400

1,200

1,000
Ul
E 800
..c:
0
-
""I~ 600

400

200

0 100 200 300 400


Frequency, mc
Fig. 20.19. Parallel output resistance common emitter vs. frequency.
288 High-frequency Designs

Table 20.1

Parameter
Characteristic
Common-base Common -emitter
Parallel input inductance ......................... . 0.02-0.05 JLh 6-20 pf
Parallel output capacitance ....................... . 2-5 pf 5-15 pf

l00-mc Design Example. The example chosen to illustrate the mismatch de-
sign is a three-stage common-base 100-mc amplifier (Fig. 20.24). The input and
output circuits to be matched are shown in Fig. 20.22. Because the common-base
input is inductive with a Q equal to approximately 2, the self-inductance ratio
transformer shown in Fig. 20.23 is used. The value of L needed is obtained from
the R(in)' Ri relationship. Substituting the values R(out) = 850 ohms for R(in)'
R(in) = 37 ohms for R i , and L(in) = 0.02 /Lh for Li yields L = 0.08 /Lh. The total
parallel inductance of the interstage is
LT = 0.02 + 0.08 /Lh = 0.1 /Lh
160

140
VCB = -lOv
Ic= -1Oma
120
til
E
2Nli~ r--.....
.<:: 100
0
-
.....
I~. 80
2Nlt~ r--
~

60
2N1141 --
r--. to-.

40

o 100 200 300 400


Frequency, mc
Fig. 20.20. Parallel input resistance common base vs. frequency.

General Radio
Hewlett·Packard Nems·Clarke
1607A coaxial
608C VHF bridge and 1502A receiver
generator transistor mounts and REU 300B

I
Bias supplies

Fig. 20.21. Test-equipment block diagram.


Low-level RF Stage Stability 289

R<.fT r~~)-~:'~rn~--:J
Collector
R(out) = 850 n
C(out)= 2-5 pf
L(in) = 0.02 JLh
I I
R(in) = 37 n
I o-~I----~~
Base L ___________ J Base
Fig_ 20.22. Input-output circuit to be matched for design of lOO-mc RF amplifier.

The parallel capacitance is 25 pf for resonance at 100 mc. A 4- to 30-pf trimmer


capacitor is used in the circuit to facilitate tuning. For m = 2, an 850-ohm resis-
tor must be added in parallel with the 100-mc tank circuit. This determines the
loaded Q of the interstage,
QL = R tot parallel or
XL tot parallel
Since the single-stage bandwidth is related to the loaded Q by the expression

BW=~
QL

where /0 is the mid-band frequency, the single-stage bandwidth will be

BW = 100 mc = 21 mc
4.7
For three cascaded stages of this same interstage Q, the bandwidth will be
BW = 21 mc X 0.43 = 9.0 mc
The output-matching network was chosen to be an autotransformer to match
R(out) = 850 ohms to the 50-ohm output load. The same total parallel inductance
and capacitance are used to set QL = 4.7. The tap position for the 50-ohm load
is experimentally determined.
The input network is required to match the 50-ohm impedance of the source to
19 ohms, which is approximately one-half the parallel input resistance of the input
stage. The necessary inductance is calculated as before:
L + 0.02 p.h 50
L = 0.01 p.h
0.02 p.h 19
With this required L, the necessary input capacitance is approximately 80 pf.

L.+L)2
R(in)=
(
~ Ri

~(L.L ) 1]2 « 1
Conditions: W2~ Li'+L Rd
w
r + 1>> 1
L
\-'zi-J L 2

Fig. 20.23. Self.-induclance ratio transformer.


290 High-frequency Designs

0.08 and 0.1 J.lh coils are 3 and 4 turns respectively of No. 18
tinned bus wire, 1/4" diameter
0.01 J.lh coil is 1 turn of NO. 00 enameled wire, 3Js" diameter.
All loading resistors are TI MIL·LlNE 1%.

Fig. 20.24. lOO-mc RF amplifier.

Next, the expected gain is calculated. The loss factor for m = 2 is read from
the graph as 4 db. Subtracting this from Gu for the common-base stage at 100
mc, the result is 16.5 - 4.0 db. This means that the gain per stage should be ap-
proximately 12.5 db, or the overall gain should be 37.5 db.
The stability data can be determined from the appropriate graph as p' = 1.6.
For m = 2, this means that p = 14.4.
Data were taken on the amplifier for three values of m which provide adequate
stability. The center frequency gain calculated and measured along with the
amplifier response is shown in Fig. 20.25 for the three values of m and p. Gain
stabilities of -+-1 db for interchange of transistors were noted for the p = 25.6
condition.
The following are other design examples using the mismatch technique.
60-mc Design Example. Figure 20.26 shows a single stage of an eight-stage
60-mc IF amplifier using TI type 3N35 silicon tetrode transistors. All eight stages
are identical except for the input and output stages, whose transformers are de-
signed for the appropriate driving and load resistances, respectively. Transitionally
coupled, double-tuned interstages are used. The design of these networks is
treated extensively in a report by Lawson and Stone. 5 A 5: 1 mismatch provides
stability and ease of alignment while allowing a stage gain of about 12.5 db.
The interstage description and calculation of the necessary constants are:
1 ( 0:1 2 1 ( 2
30: 22 )
= Wo4 C11 C2
0:2 30: ) 12
A1 = wo2C1 1 + 8 + -8- A2 = wo2C2 1 + 8 + -8- A3
Low-level RF Stage Stability 291

40.-----,-----,-----,-----,-----,-----,

..0
""0
c
ro
o 25r-----r---~~----r---~Hr4r--T---~

l5L-__ ~LL~ _ _L -____L -_ _ _ _L-~WL~_ _~


85 90 95 100 105 110 115
Frequency, mc

Single G TM3
3 stage G TM3
stage calculated
L3(db) measured
M p L(db) G u3 (db) - L3(db)
2 14.4 4 db 12 db 37,5 db 36db
2,5 19,5 5,6db 16,8 db 32,7 db 32 db
3 25,6 7 db 21.0 db 28.5 db 28db

Gu =16.5 db for this example Gain stability of ± 1 db for interchange in transistors


G U3 = 49.5 db for 3 stage was noted for the p =25,6 condition
Fig, 20.25. 100-me RF amplifier data.

where Wo = 27Tfo
/0 = design center frequency
Al = primary inductance
A2 = secondary inductance
M = mutual inductance
k = coefficient of coupling
(Xl = primary dissipation factor
(X2 = secondary dissipation factor
R1 = common-emitter parallel output resistance
C1 = total parallel primary circuit capacitance
R2 = common-emitter parallel input resistance
C2 = total parallel secondary circuit capacitance
Each stage is designed with a 32-mc bandwidth. Thus,

b = !if = 37160 = 0.533 where b = fractional bandwidth


/0
292 High-frequency Designs

t[
-20v +20v
Fig. 20.26. One stage of the amplifier.

However,
I
b = V2 (0'1 + 0'2)

so that the relationship 0'1 + 0'2 = V2 (0.533) = 0.754 is obtained. It was de-
cided to design the transformer using a typical value of 5,000 ohms for R1 and
6 pffor C1 .
I
(2'17)(60 X 10-6)(5,000)(6 X 10-12) = 0.0885
Thus, 0'2 = 0.754 - 0.0885 = 0.6655
Values of R2 = 133 ohms and C2 = 30 pf were chosen.
I
0'2 = --=---=-
WoR2 C2

The transformer constants then were calculated as follows:


A -
1-
I
(377)2(1012)(6 X 10-12)
[I + (0.0885)2
8 +
3(0.6655)2J - I 365
8 -. X
10-6 h
enry

A - I [(0.6655)2 3(0.0885)2J _ -6
2 - (377)2(1012)(30 X 10-12) 1 + 8 + 8 - 0.2475 X 10 henry

I
A3 = (377)4(1024)(6 X 10-12)(30 X 10-12) = 0.275 X 10-12 henry

k = j I- 0.275 X 10 12
1.365 X 10-6 X 0.2475 X 10-6 = 0.43
The proper biasing of the stage is important to ensure optimum gain and inter-
changeability of units. Measurements made on large quantities of 3N35 units
show that this device has optimum gain characteristics at an operating point of
VeE = 20 volts, IE = -1.3 ma, and IB2 = -0.1 mao To ensure adequate bias
circuit performance from unit to unit under conditions of large ambient tempera-
ture variations, a two-battery circuit was employed. The negative supply was
made 20 volts, thereby providing a symmetrical arrangement. Each transistor is
biased common base even though the RF circuitry is common emitter. The large
Low-level RF Stage Stability 293

Fig. 20.27. Demodulator probe.

resistors in the emitter and base-2 leads assure that the circuits in these elements
will remain constant. These resistors are bypassed for signal frequencies by ap-
propriate capacitors. An additional 0.2-pJ capacitor helps ensure that the bias
point will remain constant with a pulsed input signal.
The RF circuitry is straightforward. Trimmer capacitances tune both sides of
the transformer: a 4- to 30-pf unit at the input to the transistor and a 1.5- to 7-pf
unit in the collector circuit.
Figure 20.27 shows the demodulator probe which is used to simplify alignment.
It consists of a resistor and a capacitor which simulate the input to the stage fol-
lowing the one to be tuned, plus a diode for demodulating the signal. The de-
modulated signal may be viewed on a high-gain, low-frequency oscilloscope. The
probe has low stray capacitances and a flat frequency response so that the circuit
under alignment will not be detuned by the probe. All measurements were made
on the low-impedance side of the transformers.
The testing was done using a sweep generator. This method permits the effect
of minor adjustments to be evaluated rapidly, and is recommended for any wide-
band amplifier work. The effects of regeneration show up on this test as spikes
or otherwise unexplainable lobes in the passband. In aligning the entire amplifier,
the stages can be tuned by moving the probe one stage at a time.
5.5-me Design Example. Figure 20.28 shows a three-stage 5.5-mc amplifier
using TI type 2N2189 germanium transistors. This amplifier has a 3-db bandwidth
and mid-band gain equal to 200 kc and 60 db, respectively.
The interstage networks consist of single-tuned transformers with the collectors
tapped down on the primary (Fig. 20.29). This tap-down method ofIF transformer
design has been described by Webster6 and Cooke. 7
The interstage calculations using their notation are

(49)

where BWA = 200 kc


!o = 5.5 mc
QL = single-stage loaded Q
n =3
Substituting these values into Eq. (49) gives

QL = (o~i~m~c) (0.51)
QL = 14
294 High-frequency Designs

-r
0.02 30 0.02 30 0.02 30

-f t
-IOv

0.02

Fig. 20.28. 5.5-me amplifier.

At this point we must decide on the tota110ss allowable for interstage. This
loss is divided into a mismatch loss, ML, and a coil loss, n. ML is defined in this
design procedure as the efficiency of match.

ML (db) = 10 log (1 !a a)2 (50)

where a = Ri/R; (called the mismatch factor).


R£ = load impedance (transistor's input impedance) referred to unit turns
ratio
R; = generator impedance (transistor's output impedance) referred to unit
turns ratio
The coil loss is defined as the efficiency of the transformer,

1/ (db) = 10 log (1 - g~y (51)

where Qu = unloaded Q of the primary. Using an a = 0.5 results in a mismatch


loss:
4(0.5)
ML (db) = 10 log (1 + 0.5)2 ML (db) = -0.5 db

Figure 20.29
Low-level RF Stage Stability 295

Figure 20.30

For this amplifier, a total loss equal to 10 db/transformer provides stable opera-
tion and minimizes interaction between the tuned circuits.
Therefore,
n (db) = -10 + 0.5 db = -9.5 db = 0.112 (numeric)
Solving for the Qu from Eq. (51) gives

Q QL
(52)
u=l_vn

Substituting values for QL and n,


1
Qu = 1 _ y'OTI2 = 18.7
Figure 20.30 shows the transformer with all impedances referred to the total
primary. Assuming a value of C = 30 pf gives, for the antiresonant unloaded coil
impedance,

(53)

Rc = 1.0381~71O-3 = 18.3 kilohms


The total shunting impedance across C required to give the correct QL is
QL 14
RT = woC = 1.038 X 10-3 = 13.5 kilohms (54)

RT is equal to the parallel combination of R c, R6, and Ri; therefore, we must de-
termine the value of resistance, Ra:, which parallels Rc to give R T.

RT = Ra:Rc (55)
Ra:+ Rc
Ra: = RcRT (56)
Rc - RT
Substituting values for Rc and RT gives

R _ (18.3)(13.5)
a: - 4.8 Ra: = 51.5 kilohms
Ra: represents the loading referred to total primary caused by R; and R£ .
296 High-frequency Designs

We have
R~R£
(57)
Rx = R~ + R£
R~aR~
(58)
R~ + aR~
-R' _a_ (59)
- g 1+ a

or R'-R
g - x
1+a
a (60)

Also R~ = (Z~yRg (61)

Therefore Nl = jRi1 + a)/a (62)


N2 Rg
Using Rg = 6 kilohms and substituting the above values for Rx and a gives

The ratio NdN3 is determined from the equations

R£ = aR~ = aRg(Z~) 2 (63)

and R£ = (Z:y RL (64)

Therefore (65)

Using RL = 400 ohms,


Nl 0.5(6)(25.7) = V192 = 13.88
N3 4
Transformer data

Nl =
30 turns of No. 40 Gripeze* wire.
N2 =
6 turns of No. 40 Gripeze wire.
N3 = 2 turns of No. 40 Gripeze wire.

The windings are bifilar-universal wound using EI Rad* IF assemblies with ferrite
cup and core.

* Registered trademarks.
Low-level RF Stage Stability 297

BIBLIOGRAPHY

1. Cote, A. J., and J. B. Oakes: "Linear Vacuum Tube and Transistor Circuits," McGraw-
Hill Book Company, Inc., New York, 1961.
2. Sands, H. F., and H. K. Schlegelmilch: Design Considerations of Transistor I-F Ampli-
fiers for TV Receivers, Proc. NEe, vol. l3, p. 433, 1957.
3. Bahrs, G. S.: Amplifiers Employing Potentially Unstable Elements, doctoral thesis,
Stanford University, 1956.
4. Frazier, R. M.: Methods of Designing and Cascading Unneutralized Tuned Transistor
Amplifiers, address presented at Solid State Circuits Conference, Philadelphia, 1960.
5. Lawson, J. L., and A. M. Stone: Double Tuned Circuit with Transitional Coupling, MIT
Rad. Lab. Rept. 784, Cambridge, Mass., October 8, 1945.
6. Webster, R. R.: How to Design I-F Transistor Transformers, Electronics, pp. 156ff, August,
1955.
7. Cooke, H. F.: Tap-down Method ofI-F Transformer Design, unpublished paper.
21
Noise

21.1. TRANSISTOR NOISE FIGURE

Noise figure 1 and gain determine receiver or amplifier sensitivity in the VHF
range, and are therefore important quantities in the application of VHF small-
signal amplifying devices.
Noise figure is defined by the equation
NF = input signal-to-noise power ratio (1)
output signal-to-noise power ratio
An ideal amplifier would amplify the incoming signal and incoming noise equally
and would introduce no additional noise. From Eq. (1) such an amplifier would
have a noise figure equal to unity (0 db).
The noise figure of several cascaded amplifier stages is

(2)

where NF = total noise figure


NFn = noise figure of the nth stage
Gn = available gain of the nth stage
From Eq. (2), the gain and noise figure of the first stage of a cascaded chain will
largely determine the total noise figure.
Transistor noise figure is defined as the noise figure the device can yield under
the specified conditions of source resistance, frequency, and bias levels. It is
important to note the effect of input circuitry losses (POL) on noise figure. Any
input losses (expressed in decibels) add directly to the noise figure (in decibels)
because the input signal is effectively attenuated while the available input noise
power remains the same. Any noise test circuit should have input losses negligible
compared to device noise figure.
In tuned networks the losses are given by

POL = 20 log (1 - ~~) (3)

298
Noise 299

Example. If QL = 10 (loaded Q) and Qu = 50 (unloaded Q), then


PeL = 20 log (1 - 1%0) = -2 db
In some designs a compromise of input selectivity may be necessary to keep the
input losses low.
Neilson 2 has shown that transistor noise figure is dependent on several physical
device characteristics. His treatment of the subject, based on the noise equivalent
circuit of Fig. 21.1, attributes noise in transistors to three noise generators:
(1) emitter and (2) collector noise current generators representing fluctuations due
to diffusion and recombination in the base region, and (3) a base noise voltage
generator representing the effect of thermal noise in rb .
On the basis of this equivalent circuit, Neilson's expression for common-base
and common-emitter noise figure is

where h{eo is the low-frequency common-emitter short-circuit forward current


transfer ratio.
The good agreement of Eq. (4) with measurements for two 2N1405 series tran-
sistors having somewhat different parameters is shown in Figs. 21.2 and 21.3. For
these two transistors,lhfb = 500 mc and hfbo may be computed from h{eo by the
well-known relationship
h - -hfeo
fbo - (5)
1 + h feo
Neilson's treatment does not account for low-frequency transistor noise. Experi-
mentally it is found that noise figure has a low-frequency corner of about 2 mc
(with Rg = 50 ohms, Ie = -2 rna, VeE = -6 volts) for 2N1405 series types. This
low-frequency corner can be made to extend below 2 mc for higher source-imped-
ance levels.

r = 26mv 12
,2 e IIElma
~c
ri,=ohmic base resistance
£e 2=2qIE df
~2=2qlc(1_1:~2)df
eb2 =4k Tri,df
where k = Boltzmann's constant
T= absolute temperature
df= noise bandwidth
Z _ Rc
c- p R c Cc+ 1
where Rc= Early·effect
resistance
Fig. 21.1. Noise equivalent circuit of transistor, and definitions.
300 High-frequency Designs

14

12
Parameters of Pa ra mete rs of Conditions:
measured device computed device R g =50n
ri,=38n r/,=40n V CB = -6v
10 r--- h FEO =30 h FEO =32 IE =2 ma

..0
""C
8 J
~
::s
OIl
<;::
Q)

'"
'0 6
r, (/
!
/
/'
z

4
"'........ ........
-
'- V
1------ -- -- -I-' _c-I-'
o Measured
It Computed
2

o
1 2 4 7 10 30 70 100 200 400 1,000
Frequency, mc
Figure 21.2

Two important conclusions may be drawn from Eq. (4):


1. Low r;' and high h(eo are necessary for low noise-figure mid-frequency
(30-mc) range.
2. NF is also a function of the source resistance, R g, and bias conditions.
Normally, however, the noise figure is not seriously degraded by designing
the input circuitry for a maximum power-transfer match (i.e., Rg equal to
input resistance).

21.2. TRANSISTOR UPPER NOISE-CORNER FREQUENCY

The expression usually quoted3 for the upper noise-corner frequency,fA, shown
in Fig. 21.4 is
fA = fMb \11 - hfbo (6)
This expression is calculated from the formula given by Neilson [Eq. (4)], con-
sidering only the collector noise term (fourth term on the right-hand side).
In many practical cases, the first terms in Eq. (4) may be significant, so the fA
derived will, in general, be too low. Also, the upper noise-comer frequency is
determined by fhfb rather than by the transition frequency, fr, which is defined as
the frequency for which the magnitude of the common-emitter forward current
transfer ratio, Ih(el, can be extrapolated to one (assuming that Ih(el is decreasing at
the rate of 6 db/octave).
Noise 301
14

12
Parameters of Parameters of Conditions:
measured device computed device R g =50n
rz,=67 n rz,=60n VCB = -6v
i
r
10 I - - - h FEO =23.4 f- hFEO=20 IE =2 ma

.0
-0 8 ~ h
'" '(I
OJ-
~

~
bD

~ ........ t-.
;;:::
OJ
'6 6
z
__ k·1-' l/
4
~---- -- ~- 1-- I-.~-

o Measured

x Computed
2

o
1 2 4 7 10 30 70 100 200 400 1,000
Frequency, mc
Figure 21.3

A more ex~ct form forjA is obtained by equating the frequency-dependent term


in Eq. (4) to the sum of the fOUf non-frequency-dependent terms and solving
forjA'

JA =jhfb- h 2R g + 2r/; + re (1 h) (7)


fbore (R g + re + rb)2 + + (bo
Of, if hfbo =- 1,
(8)

~
::s
bD
;;:::
OJ
Ul
'0
Z
/ __ 1
II 3 db
------~---r---T
I
I

fA log frequency
Figure 21.4
302 High-frequency Designs

Table 21.1

Upper noise-comer frequency


fA, in me, when Rg = 50 ohms
Transistor fr, fhfb,
h{bo
rb, Te ,
type me me ohms ohms Computed, Computed,
Computed,
Measured Eq. (7) Eq. (7)
Eq. (6)
withfh{b withfr
2N544
28 40 -0.991 22 16.6 24 3.8 23.5 16.5
(drift)
OC170
88 110 -0.992 34 16.6 62 9.8 64.0 49
(PADT®)
T1832
275 470 -0.9615 38 16.6 280 91.7 268 155
(MADT®)
2N1405
460 620 -0.984 46 16.6 320 78.4 330 245
(Mesa)

21.3. EXPERIMENTAL RESULTS

Transistor parameters are presented in Table 21.1 for four types of transistor
structures, together with calculated values for /A (for Rg = 50 ohms), using the
classic equation and the more exact expression [Eq. (7)]. Also shown is the calcu-
lated /A, using the more exact expression but substituting the frequency /r in place

14
IJN544
~ DRIFT
12

J fe170
PADT II
10
If
..c
"0 8
/ I I
I

,- .l
~
~-
:J
l T1832
bO
<+=
Q)
J ~~. MAD~ I
It

,---~:
.!!! 6
o
z t..... ~ .'
~ 6 db/octave
4
0-
~1405
./ MESA
~ ......
2
....I- f-"~

a
1 10 100 1,000
Frequency, mc
Fig. 21.5. Experimental values for transistor noise figure vs. frequency for four types of
germanium high-frequency transistors. Rg 50 ohms, IE =
1.5 ma, VOB -9.0 volts. = =
Noise 303
10

9
/=30 mc R g=860,
Vee=10v
8
Average of 10 transistors
~
/
......... ~ V R g=400n

5l 6
-r- r-
- ./
L R g=5on111
/ R g =105n

~ V
-- ~g=12d06
'0
z
~ -~ ~
~ .L ~
5

4
~ i"'--.. ... ~J::::::::::V
~

0.1 0.2 0.5


I I II II 1.0 2.0
I I III r
5.0
Collector current, ma

Fig. 21.6. NFvs. Ia. transistor 2N743.

10
/=60mc
Vee = lOv
9 Average of 10 transistors
R g =760n
i"-.... r---
r-- ~ t...
8 I-R g =50n
~ t'-.... V
..Cl
'0
~-
::l
7
R g =420n

R g=94n
i"-.... r-.... i""o-
r-- t--r- l"- i'-..

--... ...
r- ....
-
L V
1-'

----
~
b.O I"'"
R g = 154n
""
CIJ
(/) 6 i"---.. -I"'-
~ ~
'0
z

"
o~(--~~~I~I~I~II~I__~~~~I~I~II~lr
0.1 0.2 0.5 1.0 2.0 5.0
Collector current, rna
Fig. 21.7. NF VS. Ia. transistor 2N743.
304 High-frequency Designs

18
I
16 L L
R~=75b
14 1 V
12 lL L
..c 10
VCB=lj
L L
""C
",,-
~ 8 ~ r-....
~
./
V
~
r-
/
~ ~
..........:: < 10v
..",;

0 2 3 4 5 6 7 8 9 10 11
lEI rna
Fig. 21.8. 200-mc noise figure.

ofjhfb. The measured values foriA were obtained from Fig. 21.5 by locating the
frequency at which the noise figure had risen 3 db above the low-frequency (I-me)
value. Note the very good agreement between measured values and the noise
corner calculated according to Eq. (7), employingjhfb rather than /T. This is true
for a wide variety of transistors with cutoff frequencies ranging from 40 to over
600 me.
-30v
Calibrate 0.2 J.l.f

O.2'fl~---""""-!~
50K

Test To H·P
400H
VTVM

- 100
10 K
+ p.f

+
Calibrate for 1 rnv
Place transistor in socket
apply bias
24K 24K hfeo = V (in rnv)
L Burnell AF 87 10 h choke
Fig. 21.9. h reo at l-kc test circuit.
Noise 305

RX
meter

Hi

lK

+
Measure riep and Emitter and collector terminals of
ciep; convert to transistor socket are fitted into
Erie type 2405·102 feed-through capacitors.
ries; ries =rb
Shield terminal is wired to ground
usef=250mc

Fig. 21.10. r;' test circuit.

2.4pf

100 mc oscillator

lK

2K 2K

Ql 2N1407 or 2N1143 Procedure for Ihfe I at 100 mc


Q2 Test transistor or f t measurement:
Ll 5 turns #18 tinned buss 1/4" (1) With calibrating capacitor in position
dia 7/16 " length no core read El = [(in) X 20 rl
L2 3.3 Mh rfc (2) Remove capacitor, place transistor in
socket, apply bias
read E2 = [(out) x 20 rl
Ih fe [_- I(out) _ E2
I(in) -"Ii:;

Ihfeldb=20 IOg10 ~:]


Since Ihfe I decreases 6 db/octave
at high frequency

it = ~:] x 100 mc
Fig. 21.11. [h re [at 100 mc or /T test circuit.
306 High-frequency Designs

Experimental values for noise figure as a function of frequency are shown in Fig.
21.5. These values are in good agreement with values calculated from Neilson's
equation, using the appropriate transistor parameter data. Emitter current bias
for optimum noise figure is about 2 rna for the 2Nl405 series.
It is found experimentally that noise figure increases at low emitter currents.
This effect is caused by the degradation of h{eo and the noise contribution of reverse
saturation currents (I CBO) in the low-current range. Illustrations of this effect are
shown in Figs. 21.6 to 21.8. Figures 21.6 and 21.7 also illustrate the NF depend-
ence on Rg for the 2N743, a silicon epitaxial mesa device. Figure 21.8 contains
NF information for a VHF germanium mesa transistor. For this device, MAG is
greatly reduced in the 5-ma emitter range by decreasing V CB below about 3 volts,
thus causing an increase in NF.
The parameters having greatest effect on noise figure can be measured by the
following methods:
1. h'eo-use test set in Fig. 21.9
2. rb-use RX meter in conjunction with jig of Fig. 21.10.*
3. 1Mb-measure iT, using test set of Fig. 21.11, and convert to hhfb by extrapo-
lation or Ihfb = 1.4/'T. t

BIBLIOGRAPHY

1. Kronlage, J. w.: Characteristics and Applications of 2N1405, 2N1406, and 2N1407


Diffused Base Mesa Transistors, TI Application Report, January, 1961.
2. Neilson: Behavior of Noise Figure in Junction Transistors, Proc. IRE, vol. 45, p. 957,
July, 1957.
3. Cooke, H. F.: Transistor Upper Noise Corner Frequency, Proc. IRE, vol. 49, p. 648,
March, 1961.
4. Transistor Internal Parameters for Small Signal Representation, Proc. IRE, vol. 49, no. 4,
April, 1961.

* This measurement is not valid for 2N743 (Ref. 4).


tThis approximation is valid for the 2N1405 series only.
22
RF Harmonic Oscillators

This chapter discusses some of the fundamentals of RF harmonic oscillator


design. The characteristic equation for the various oscillator configurations is used
to develop expressions for the natural frequency of oscillation and the necessary
conditions for buildup of oscillation. Causes of frequency instability and methods
of improving stability are discussed. The effects of changing load, changing passive
parameters, and changing active parameters are analyzed. A brief treatment of
crystal oscillators is presented along with a discussion of the crystal itself. Finally,
a design procedure is proposed, and circuit examples are presented.
The general treatment of oscillators in this chapter is on a linear basis. However,
the conditions of self-sustained oscillation must necessarily be nonlinear. Because
of this linear analysis restriction, certain interesting topics such as limiting output
voltage and current amplitude will be treated on a very approximate basis. To
analyze these aspects more accurately would require limit-case solutions of the
nonlinear differential equation describing the oscillator current or voltage in the
phase plane, which are beyond the scope of this treatment.

22.1. OSCILLATOR CONFIGURATIONS

Necessary Conditions for Oscillation. The first necessary condition for self-
sustained oscillation in a circuit is that the active device permit power gain at the
frequency of oscillation. Furthermore, the device must have sufficient gain to
overcome circuit losses and establish exactly unity gain around the feedback loop.
The second necessary condition is that the phase shifts introduced by the active
device and the feedback network result in exactly zero phase shift around the
overall circuit.
These conditions will permit sustained oscillations, but they do not guarantee
that oscillations will occur. In other words, it is not enough that unity loop gain
can exist. There must be more than unity loop gain at first to cause buildup of
oscillations. These, then, are the necessary and sufficient conditions for the buildup
and maintenance of self-sustained oscillation in a circuit.
307
308 High-frequency Designs

Vi
- Amplifier
- V2

Vi
- Ii
Feedback
network
-12

Vi!

Fig .. 22.1. Feedback oscillator configuration. Fig. 22.2. '1T-type feedback oscillator.

Basic Configurations. Most oscillator circuits can be regarded as having two


basic components: the amplifier and the frequency-selective feedback circuit. This
arrangement is known as a feedback oscillator, and is shown in Fig. 22.1. The
frequency-selective circuit can be further reduced to the network arrangement shown
in Fig. 22.2. This configuration allows a clear visualization of each of the basic
oscillator types. If K2 and Kl are capacitors and K3 is an inductor, the circuit is a
Colpitts type. Figure 22.3 shows this configuration. If Kl and K2 are inductors
and K3 is a capacitor, the configuration is called a Hartley oscillator and is shown
in Fig. 22.4. Figure 22.5 shows the Hartley configuration realized with a two-
winding transformer. The choice between a two-winding transformer and a tapped
coil depends partly on the frequency of operation, since the expressions for the
natural frequency of oscillation are slightly different. Also, the tapped coil requires
an extra d-c isolation capacitor, which is not necessary with the two-winding trans-
former. Because of the possibility of obtaining phase reversal with the two-winding
transformer, the transistor can be changed from common base to common emitter.
A modification to the Colpitts circuit results in the Clapp oscillator. In this
circuit, the resonant frequency is determined primarily by the series combination
of Land C. Figure 22.6 shows the arrangement. Where there is a requirement
for high stability, crystals may be used for the frequency-determining element. A
configuration using a crystal is shown in Fig. 22.7.
Some of the many possible modifications to the above basic configurations are
shown in the circuit performance section. These arrangements of the active device
and passive structure have been made so that it will be easy to combine the two-

Fig. 22.3. The Colpitts type circuit. Fig. 22.4. The tapped Hartley circuit.
RF Harmonic Oscillators 309

Fig. 22.5. Two-winding Hartley oscillator. Fig. 22.6. The Clapp oscillator.

terminal pair parameters of each black box into one equation characterizing the
composite network. The set of equations characterizing the active device in
h parameters is shown in Eqs. (1) and (2).
Vl = hib/l + hrb V2 (1)
12 = hfb/l + hob V2 (2)
Equations (3) and (4) characterize the passive structure.
Vl = hull + hl2 Vz (3)
Iz = h2l/l + h22 Vz (4)
The combination of these black boxes results in a set of equations which completely
characterize the composite network. For the networks of the type shown in Fig.
22.2, the combination must be accomplished as indicated in Eqs. (5) and (6).*
Vl' = (h ib + hl l )I1' + (hrb - hl2) Vf' (5)
(6)
Oscillator connections are special cases, however, since Vl' = 0 and 12 = O. These
restrictions create the set of simultaneous homogeneous linear equations shown in
Eqs. (7) and (8).
o = (h ib + hu)I'{ + (h rb - h12 ) V2' (7)
o = (hfb - h21 )I1' + (hob + h22) V2' (8)
This set is, by definition, the characteristic equation of the combined network; and

* See Ref. 3, p. 553, for further discussion.

Fig. 22.7. Crystal oscil-


lator.
310 High-frequency Designs

its solution for the imaginary part will yield the natural frequency of the system.
This may be done by inserting actual circuit values into Eq. (9) and solving for the
imaginary part equated to zero.
(hib + hu)(hob + h22) - (hrb - h12)(hfb - h21) = 0 (9)
Evaluation of the real part of the expression is done in a similar way to yield
the unity gain and, hence, starting conditions. Table 22.1 lists the natural frequen-
cies and starting conditions for various configurations.

22.2. TANK CIRCUIT

Considerations for the Tank Circuit. Tuned LC circuits can be made to store
energy. Used for this purpose, they have acquired the nickname of "tank" circuits.
The frequency-determining LC circuit of an oscillator is such an example. The
three essential parameters of the oscillator tank circuit are natural frequency of
oscillation, selectivity, and characteristic impedance. The tank performs the
following functions:
1. It determines the frequency of oscillation.
2. It is the feedback network.
3. It determines the stability of the oscillator.
4. It is a part of the coupling network to the load.
5. It affects the noise energy output of the oscillator.
6. It is a principal factor determining the circuit efficiency.
For a well-designed oscillator, the reactive components surrounding the tank
are negligible in their effect on the resonant frequency set by the Land C of the
tank.
It is easily seen in Figs. 22.1 to 22.3 that the tank can be treated as a feedback
network connected across the active device. Even in the Clapp connection of Fig.
22.6 this is still true, but now the feedback is primarily determined by divider
action of C1 and C2 , and the frequency is determined by Land C in series.
Frequency stability is primarily determined by the QL of the tank. The reason
for this is that the frequency deviation required to develop a given phase correction
to establish exactly 360 phase shift around the feedback loop is inversely propor-
0

tional to the loaded Q. Frequency stability is usually the most difficult specification
to meet, and meeting it will usually more than satisfy the other requirements of
constant Q and constant characteristic impedance. In other words, the environ-
ment of the tank tends to change not only /0, but also Q and Zo: * By satisfying
the requirement for stability of fo, one usually satisfies the requirements of stability
of Q and Zo also.
The load on a transistor oscillator is usually magnetically or capacitively coupled
into the tank circuit. The load determines both the power drawn from the oscillator
and the loaded Q of the tank circuit. The ratio of loaded Q to unloaded Q for the
tank circuit should be low for good circuit efficiency.

* 20 is the antiresonant tank resistance.


RF Harmonic Oscillators 311

Components of the Tank. Capacitors. One of the most desirable types of


capacitors for use in RF oscillators is the silvered-mica type. Since the silver plates
are applied on the mica by vacuum evaporation, the silvered-mica capacitor is much
more stable than ordinary mica capacitors with plates of foil pressed against the
mica insulation. Mica has high secular* stability, a low temperature coefficient of
capacity, and a low power factor. Typical values are +20 ppm;oC temperature
coefficient and 0.015% power factor at 1 me, over a range of -60°C to +80°C.
Dielectric constants of 6 are typical. Very low parasitic inductance and d-c leakage
(the leakage is principally over the surface of the plastic jacket) are features of the
silvered-mica capacitor.
Ceramic capacitors offer two interesting advantages. Ceramic has, when mixed
with titanium, negative temperature coefficients as high as 750 ppm;oC and about
10 times greater dielectric constant than mica. These advantages lead to the
following possibilities: First, owing to the negative temperature coefficient, some
compensation can be made for the positive coefficient of most inductance coils.
Second, since such high dielectrics are available, it is possible to obtain large
capacitance in small noninductive structures. Secular stability is very good, and
power factors range from 0.02 to 0.05% at 1 mc to 0.04 to 0.1 % at 100 me. The
temperature coefficient with frequency is about constant between 1 and 100 mc.
Inductance. Normally, the capacitors used in LC tank circuits of RF oscillators
have very low losses compared to the losses in the coil. F or this reason, the
unloaded Q of a resonator depends almost entirely on the Q of the coil. The exact
design of a coil is quite complicated because of the many factors which must be
considered. The coil must have the correct inductance and be stable with time
and temperature. It must have low parasitic capacitance and a high, reasonably
stable unloaded Q.
The form of inductance coil most frequently used in RF circuitry is the single-
layer solenoid, although powdered iron cores are sometimes used for better Q or
for a variable inductance. The inductance is determined by the number of turns
and the geometry of the coil. The self-inductance and the resistivity will vary with
the frequency because of proximity and skin effects. Since the resistivity of a con-
ductor varies rapidly with temperature changes, the inductance of a coil may be
very sensitive to temperature changes, even though no appreciable change occurs
in its dimensions. The problem, therefore, is to design the coil so that its dimen-
sions are independent of time, temperature, and atmospheric conditions. The
current distribution through the wire cross section must also be independent of
temperature over the range specified.
If severe vibration is not expected, a coil may be self-supported at one end and
connected at the other end by flexible braid. This results in reasonably stable coils
having low losses. If both ends are rigidly attached, temperature-expansion coeffi-
cients may become a problem.
As stated before, the self-inductance of a coil is a function of skin effect. Skin
effect is, in tum, a function of conductivity. At high frequencies the penetration

* Secular stability is the property of a material to retrace its path when one of its parameters
is cycled with respect to temperature.
312 High-frequency Designs

of current into the conductor is very shallow, while at low frequencies it may cover
the entire cross section. The inductance is a function of both frequency and
resistivity. Since this resistivity increases rapidly with temperature, the inductance
also increases. The temperature coefficient of copper is about 4,000 ppm;oC, and
the inductance coefficient due to this effect alone may be as high as 100 ppm;oC.
At higher frequencies, where small inductance values are needed, sheet-copper strap
is used to form the coil. This provides a large surface area and reduces skin effect
for a given inductance.
Because it is expensive as well as difficult to build coils with low positive tem-
perature coefficients of inductance, negative-temperature-coefficient capacitors are
often used for compensation. This method is sometimes impractical, however,
since the elements must track each other and must be reproducible in large-scale
production.
Typically, a poorly built LC resonator may be affected by temperature so that its
self-resonant frequency drifts by about 40 ppm;oC. The drift of a GT cut crystal
will usually be 1/10,000 as great.
Crystal Discussion. When extreme frequency stability is required of an oscil-
lator, a crystal is usually used as a substitute for the tank circuit or in the feedback
loop to stabilize the frequency. The tolerance on most commercial crystals is about
0.002% from -55 to +90°C. An example of a Colpitts-Pierce crystal-oscillator
configuration is shown in Fig. 22.7. Here the crystal is operated at a frequency
just slightly below its parallel resonant frequency so that it will appear as an
inductance.
The equivalent circuit for a crystal is shown in Fig. 22.8.
The L is analogous to the mass of the crystal structure, C is analogous to the crys-
tal elasticity, and R is analogous to mechanical friction, accounting for energy lost as
heat in the crystal. Co is the total effective shunt capacitance contributed by the
distributed capacitance of the leads and terminals of the mounting structure, the
nonvibrating electrostatic capacitance across the quartz-crystal faces with the
quartz serving as the dielectric, and any capacitance added by the crystal holder.
Crystals may also be operated at certain overtones of the fundamental, but even
though the overtone Q is approximately the same as the fundamental Q, the ac-
tivity or piezoelectric effect will be progressively smaller, the higher the overtone.
Also, since in the parallel mode the activity is inversely proportional to the square
of the terminal capacitance, care should be taken to minimize external capacitance
so as to preserve crystal activity.

Fig. 22.8. Equivalent circuit of a quartz


crystal.
RF Harmonic Oscillators 313

In RF circuits, the dissipation must often be held to a few milliwatts. Tem-


perature coefficients are normally specified in the form of Eq. (10):

D 'ft = b.f//o
n b.T (10)
In other words, the specification is in parts per million per degree or in per cent
per degree. This coefficient can be positive, negative, or zero over small tempera-
ture ranges, depending on the crystal cut. Crystal-oscillator design will not be
elaborated here, in view of the wide range of crystal types and possible circuits.

22.3. ACTIVE DEVICE

Requirements. The primary function of the active device is to develop enough


output power at the frequency of operation to supply the required load power, the
tank losses, and the drive power for itself. It should also generate as little noise
voltage as possible. The active device should have a maximum frequency of
oscillation well above the design frequency. Because these requirements are rather
loose, many transistor types will function properly as oscillators. However, cer-
tain types of manufacturing processes result in device parameters which yield bet-
ter oscillator performance. Paramount among these is the epitaxial mesa technique
which allows a relatively lower value of effective collector bulk resistance, permitting
higher operating efficiency.
Parameter Variation. At low frequencies the transistor parameters in the
characteristic equation do not have large imaginary components, but at RF fre-
quencies these parameters must be inserted in the characteristic equation in com-
plex form. Solution of the real and imaginary parts, therefore, will include the
effects of input, output, and transfer immittances. The sensitivity of frequency
and starting conditions to changes in any of these immittances with the tempera-
ture, age, or bias point can be evaluated. Examination of Table 22.1 and the
design example shows the form of these equations and the specific parameters
involved.

22.4. FREQUENCY STABILITY

Causes of Frequency Instability. Oscillator frequency stability is a measure


of the amount of drift in frequency away from the design center value. There are
two causes of drift. First, the active parameters may change. The equations for
w 2 in Table 22.1 indicate the particular active parameters involved. Inserting
actual values gives an indication of their influence. Second, the passive parameters
may change. Both active and passive parameters generally change for two rea-
sons: temperature and age.
Specification of Frequency Stability. An explicit expression for frequency
variation with temperature is given in Eq. (11).

D ift = b.fI/0 (11)


r b.T/To
Table 22.1

Circuit Natural frequency (wZ) Starting condition

W
Colpitts. =-+-
I r
- - + C-hie
- +---
I !1he* hoe h
fe
> r( C 1 +
L
CZ)hie
+
Cz
C1 +
C 1 /1h
C2 e
=-
-
C2
C1
LC L C hie C CZhie 1 1 1
.I>.

=- _1_ fr + LCh oe )
- LC \ C 1 C zh ie

C1 C2
where C =
C1 + C2
and r = a-c series resistance of coil L
I hob I -C 2
Colpitts. =-+--~-
LC h;bCl C2 LC h fb >C 1 + C2

+ L 2r l) T
/1h*
rLChie + (M + Ll)2 + (L 1 r2
hie
H artley (tapped) ..
C(Lhie) + (Llr2 + L2rl)hfe + (LIL2 - M2)hoe h fe > (Ll + M) U

hoe =- Ll + M =- 1 + KN
LC + (LIL2 - M2) hie - L2 +M - 1/N2 + KN

where L = Ll + L2 + 2M M
rl = a-c series resistance of coil Ll where K = V LIL2
r2 = a-c series resistance of coil Lz
N= ~
,.JY;
Hartley (tapped) . _ _ _ _-------''--_ _ _ _ =- _1_ h fb> Ll + M Nl
~
LC + (hob/hib) (L2Ll - M2) - LC Ll + L2 + 2M N2

where L = Ll + L2 + 2M where Nl = number of turns of Ll


N2 = number of turns of L2

C1 + C2 C2 C2
Clapp. ~ - I + -I ---=----::-- h fb >- C1 + C2 h fe > C1
LC L C 1 C2

where C = series capacity with L


* !1he = common-emitter determinant = hiehoe - hrehfe .
RF Harmonic Oscillators 315

This expression gives the sensitivity of center frequency,/o, to temperature change


at a particular center frequency and operating temperature. Another expression
that can be used is given in Eq. (12),

Drift = 1::./1/0 (12)


I::.T
usually expressed as parts per million per centigrade degree.
Techniques for Improving Frequency Stability. As mentioned earlier, mini-
mization of active device influence will improve stability. For the Colpitts con-
nection, this is satisfied by the following inequality:
hob <{ C1 + C2 (13)
hibC1C2 LC1C2
Similar inequalities for other oscillator connections may be found from Table 22.1.
Selection of an active device which satisfies this inequality is therefore the first
technique.
The second technique is to swamp out part of the particular active parameter
which enters the frequency expression by putting appropriately sized resistances
in series with hib and in parallel with hob. The characteristic equation below shows
the effect of this approach.

(hib + Rl + hllp)(hob + R2I + h22p) - (hrb - h12p)(hfb - h21p) =0 (14)

Now if hib <{ Rl and hob <{ 1/R 2, the equation becomes
(Rl + hllp )(G2 + h22P) - (hrb - h12P)(hfb - h21p) = 0 (15)
The resonant frequency is solved for in the same way, except that now Rl and G2
are the terms in the expression instead of hob and hib .
The effect of load change on frequency may be shown by inserting YL into the
characteristic equation. This is shown in Eq. (16).
(hib + hllp)(hob + h22p + YL ) - (hrb - h12P )(hfb - h21p) = 0 (16)
If Y L <{ (hob + h22p), its change will be minimized in the expression for fre-
quency. This condition is generally established by a buffer stage. On the other
hand, the solution of Eq. (16) for YL will yield the maximum load conductance
which will still satisfy the conditions for oscillation. This load is important if the
oscillator is intended as a power source rather than as a frequency source.

22.5. OSCILLATOR DESIGN PROCEDURE

Discussion. The design procedure for transistor oscillators is usually treated on


a linear basis even though self-sustained oscillation indicates nonlinear operation.
Therefore, the preliminary design calculations provide only approximate values for
components, and these components must be adjusted experimentally in the final
design.
316 High-frequency Designs

Since a design procedure must be tailored to the individual oscillator specifica-


tion no exact procedure can be given other than the general steps involved. The
following is a listing of these design steps:

Design Steps

1. Select a transistor capable of providing sufficient gain and desired power


output at the operating frequency, based on data sheet specifications.
2. Select the oscillator configuration to be used, based on the application.
For example, the oscillator will probably be used either as a frequency-
determining element or as a source of power at a given frequency.
3. Design the d-c bias network to establish the bias point and provide the
necessary stability.
4. Design the tank or frequency-determining network using the formulas for
operating frequency and starting conditions given in Sec. 22.1 (Oscillator
Configurations) and in Table 22.1. The table gives natural frequency (w 2 )
and starting conditions in terms of h parameters.
S. Make necessary adjustments in the feedback and bias networks to optimize
efficiency. Be sure not to sacrifice ease of starting when adjusting the bias
network for possible class B or C operation.
6. Use a trimming capacitor to make final adjustments, if necessary, to oscil-
lator frequency.

22.6. DESIGN EXAMPLE

Specifications for the low-power oscillator design example are as follows:


!o = 90 mc
Vo = 2 V(rms) across a I,OOO-ohm load
Vee = 10 volts
The design procedure is as follows:
1. Select the 2N743 to provide this specified output power and voltage. It
has an It which is, at the normal bias point of S volts and S rna, about three
times!o.
2. The Colpitts connection is selected for this frequency range because it
yields values of tank inductance and capacitance which should be fairly
insensitive to transistor parameter variation. The circuit configuration is
shown in Fig. 22.9.
3. The d-c values for the network are as follows:
Let the drop across R3 be 2.S volts.

R3 = 2.5 volts = SOO ohms


Sma
Let the current through Rl and R2 be S rna, so that the value of R2 will be

R2 = 3.1 volts = 620 ohms


Sma
RF Harmonic Oscillators 317

This leaves VRl = lO - 3.1 = 6.9 volts; if IB is about 0.4 rna,

Rl = 6.9 volts = l.3 kilohms


5.4 rna
R4 will have about 2.5 volts across it; therefore,

R4 = 2.5 volts = 550 ohms


4.5 rna
4. The a-c circuit design is carried out as follows. Since R2 is 620 ohms, ade-
quate bypass is about 5 ohms. This gives C1 = 300 pf; to avoid a self-
resonant frequency at or around 90 mc, C1 must have a total lead length
less than 0.4 in. C4 and C5 are 500-pf feed-through capacitors.
At 5 volts, 5 rna, and about 90 mc, the hb parameters for the 2N743 are:
hib = 2l.3 L45.6° = (15.2 + j15) ohms (17)
hrb = 0.069 L 77° = 0.0672 + jO.0154 (18)
hfb = 0.97 L 182.3° = -0.969 - jO.039 (19)
hob = 2.76 X lO-3 L 15.3° = (2.66 + JD.73) X lO-3 mho (20)
The expression for w 2 is

w2 = (hLib + hob ) C1 + C2 1
+ C2
C1 C1 C2 hib
1 C1 + C2 + hob
L C1 C2 hib(C 1 C2 )
1 1
= + -:----:-::-....,--,:---",--:- (21)
L C1 C2 /C1 + C2 hibr/hobr (C1 C2)
By experimentally adjusting the capacitance ratio of the tank, we found that the
following ratio gave the desired signal across the I-kilohm load:

C2 = 43 = 0.47
C3 91
The inductance is 0.11 fLh (~ 2 turns no. 18 wire on V2 in. diameter). Vo = 2 volts
across the I-kilohm load.
In order to determine the effect of the transistor parameters on the frequency of
oscillation, we will compare the values obtained from the following expressions.
Frequency determined by considering only the tank:

w2 = 1
L[C1 C2 /(C 1 + C2)]
w2 - 1
o - (0.11 X lO-6)(29 X lO-12)
1 1
.fo = (6.28)(3.2 X lO-18)1I2 (6.28)(1.79)lO-9 = 90 me
318 High-frequency Designs

CJ
~------------~------------~~-----oVcc=10v

Fig. 22.9. 95-mc oscillator. Circuit uses a silicon epitaxial mesa to deliver about 2 volts (rms)
across a 1-kilohm load at 95 mc. Typical circuit efficiency ~ 3%.

Using hibr and h obr equal to 15.2 ohms and 2.66 X 10-3 mho, respectively,

w2 - 1 + 1
o - L[C1C2/(C1 + C2)] (hibr/hobr)(C1C2)
1 1
(0.11 X 10-6 )(29 X 10-12) + (15.2/2.66) 3.94 X 10- 18
= 0.313 X 1018 + 0.044 X 1018
W o2 = 0.359 X 1018 /0 = 95.4 mc

100·500 pf
50n
3.6K
load

0.001 J.Lf

-lOv
N5
170·780 170·780
pf pf

Tl
3.6 K Air Dux·508
N 1 ·3 turns
N 2·1 turn
N a·1 turn
N 4 ·3 turns
N 5·5 turns
Coefficient of
coupling ~ 0.5
Fig. 22.10. 23-mc push-pull oscillator.
RF Harmonic Oscillators 319

50n
load
220 pf

500 pf

T l -6 turns Air Dux-40B


Fig. 22.11. 24-mc oscillator.

Evaluation of the operating frequency, using the full set of complex values for the
h parameters, indicates that the frequency is still almost completely determined by
the tank components. Experimental measurements of frequency agreed very well
with the predicted value. Figure 22.9 shows the circuit and performance.

22.7. ADDITIONAL CIRCUITS AND PERFORMANCE

23-mc Oscillator. The 23-mc push-pull oscillator of Fig. 22.lO was designed
to deliver 75 mw to a 50-ohm load. A 'IT-matching network is used to optimize
the output to a 50-ohm load with a noncritical design for the output transformer.
Transistor type used is the Dalmesa 2N2188.
24-mc Oscillator. Figure 22.l1 shows a 24-mc Clapp oscillator designed to de-
liver 300 mw into a 50-ohm load. Typical collector efficiency is 35%. The tran-
sistor type used is the 2N696.
30-mc Oscillator. Figure 22.12 shows a 30-mc oscillator designed to operate
over a temperature range of -40 to +60°C. Typical power out is 23 mw at

I
I Shield
I
~r-----------~~-----1----~~----~)

-10v

Tl
11 turns Air Dux-516
N l -4 turns
N 2 -7 turns
Fig. 22.12. 30-mc oscillator.
320 High-frequency Designs

-lOv

820 pf
Tl
-lOvo---+ 8 turns Air Dux·432
N 1 ·4 turns
N 2·4 turns

Fig. 22.13. 6O-mc oscillator.

_40°C and 20 mw at +60°C. Typical collector efficiency is 30%. Transistor


type used is the Dalmesa 2N2188.
60-mc Oscillator. The common-base circuit in Fig. 22.13 is a 60-mc oscillator
designed to deliver approximately 10 mw to a 50-ohm load at 25°C. Collector
efficiency is typically 8 to 10%. Transistor type used is the Dalmesa 2N2188.

BIBLIOGRAPHY

1. Linvill, J. C., and J. F. Gibbons: "Transistors and Active Circuits," McGraw-Hill Book
Company, Inc., New York, 1961.
2. Cote, A. J., Jr., and J. B. Oakes: "Linear Vacuum Tube and Transistor Circuits,"
McGraw-Hill Book Company, Inc., New York, 1961.
3. Gartner, W. W.: "Transistors: Principles, Design, and Applications," D. Van Nostrand
Company, Inc., Princeton, N.J., 1960.
4. Reich, H. J.: "Functional Circuits and Oscillators," D. Van Nostrand Company, Inc.,
Princeton, N.J., 1961.
5. Pullen, K. A.: "Handbook of Transistor Circuit Design," Prentice-Hall, Inc., Englewood
Cliffs, N.J., 1961.
6. Edson, W. A.: "Vacuum Tube Oscillators," John Wiley & Sons, Inc., New York, 1953.
7. Guillemin, E. A.: "Communication Networks," 2 vols., John Wiley & Sons, Inc., New
York, 1931, 1935.
8. Buchanan, J. P.: Handbook of Piezoelectric Crystals for Radio Equipment Designers,
WADe Tech. Rep. 56-156, ASTIA Document AD 110448, October, 1956.
23
Frequency Heterodyning and
Multiplication

23.1. VHF MIXERS

A transistor frequency mixer is equivalent to a diode converter followed by a


transistor amplifier. Frequency conversion is possible at any frequency as long as
the emitter-base diode shows diode characteristics. Conversion does not depend
on the ability to amplify at the signal frequency. For this reason, a transistor will
often be useful as a converter at a higher frequency than it will amplify. The dif-
ference frequency (IF frequency), however, must be such that the transistor will
function as an amplifier.
Transistors used as mixers must meet the following requirements:
l. Efficient emitter-base diode characteristics.
2. Low emitter input capacitance.
3. Good power gain (MAG) at the IF frequency.
The TI 2N 1406 has these properties and is recommended for VHF jUHF mixing
applications.
The local-oscillator transistor must supply about 100 to 300 mvat the oscillator
frequency for optimum conversion gain. The 2N1406 will more than meet this
requirement to about 600 mc.
Mixing action in transistors can be described as follows:
l. The local-oscillator signal modulates the nonlinear impedance of the
emitter-base diode of the mixer transistor. The RF signal which is also
present across this nonlinear impedance produces sum and difference fre-
quencies, one of which is the converted IF signal. Below about 100 mc,
this conversion process is carried out with almost negligible loss, using the
2N1406. At higher frequencies, these losses become significant.
2. The mixer transistor then amplifies the difference frequency (IF) up to an
amount approaching MAG, the maximum available gain at the IF frequency.
Conversion gain is defined as
CG = IF power available at mixer output
(1)
RF power available to mixer input
321
322 High-frequency Designs
28

26
--...... .........
24 "-
22
MAG
1\
20
'\,
~
18
~
.0
"0
.<, 16

",
....'"
5 14 I
<.!J
<C 12
\
:2:
10
i\. I)
8
1I
6
~
~/ 1\
4
V r\
o
2

1.0 10
Peb

100
, 1,000
Frequency, mc
Fig. 23.1. Typical maximum available gain MAG and emitter-base diode conversion loss Peb
vs. frequency, 2N1406.

From the two steps of the mixing process outlined above,


CG = MAG (db at IF) - Peb (db at RF) (2)
where P eb is the power loss (expressed in decibels) suffered by the input signal in
the emitter-base diode conversion process.
Figure 23.1 provides a method of calculating conversion gain for a 2N1406
mixer as a function of the signal and intermediate frequencies.
Example. For a 300-mc signal frequency and a 30-mc intermediate frequency,
using Eq. (1) and Fig. 23.1:
CG = 24.8 db - 6.4 db = 18.4 db
Several possible mixer connections are given in Fig. 23.3.
An IF trap should be used at the signal input terminals. This prevents the loss
of generated IF power to the input terminations of the mixer. The Q of the trap
should be low enough so that it will not determine the IF passband.

Fig. 23.2. Input equiva-


lent circuit.
Frequency Heterodyning and Multiplication 323

A design example will now be presented for a mixer having a signal input fre-
quency of 225 mc. The intermediate frequency is 30 mc, and the desired circuit
bandwidth is 3 mc. The local oscillator will be designed for 255-mc operation.
Figure 23.2 gives the circuit configuration to be used. The circuit parameters
are calculated as follows:
For the 2N1406 at 225 mc with VCE = -6 volts, IE = 2 rna:
riep = 50 ohms Ciep = 4 pf

Input Circuit. No input transformer is necessary because ries is sufficiently close


to 50 ohms.
Let

Ll = 0.04 p.h and C' = 4'lT2f2L


1 = 13 pf for series resonance at 225 mc
1

where C' = ClC'


feS; therefore C l =17 pf.
Cl + Cies
Output Circuit. For the 2N1406 at 30 mc with VCE = -6 volts and IE = 2 rna,
roep = 10 kilohms Coep = 2 pf

r·f ~t--__--.c i·f r-f o----)t-------.--7C i·f


signal signal signal signal
input output input output

Local Local
oscillator oscillator
input input
Low impedance High impedance
(1) Signal in emitter, oscillator in base (2) Signal and oscillator in emitter
(a) Common base

...-:->t---oj·f r.A~---o i·f


r.fo---1l---1.....--H signal r-f o----)I---~...-t--f sign aI
signal output signal output
input input

Local Local
oscillator oscillator
input input
Low impedance High impedance
(1) Signal in base, oscillator in emitter (2) Signal and oscillator in base
(b) Common emitter

Fig. 23.3. Possible mixer configurations.


324 High-frequency Designs

C4 will serve to match the 50-ohm load to 10 kilohms, the output resistance of
the transistor. Since
R _ roep'
.L-l+QM2~

where RL = load resistance, and QM = Q of the matching network,


1 + QM2
.= 10 kilohms
50
= 200 or Q = 14
r' ~
and c = 1 = 0.159 = 7.6 f
4 2'TfjRLQM 30 X 106 X 50 X 14 P

The equivalent of the matching circuit is a parallel resistance of 10 kilohms and


a parallel capacitance of 7.6 pf.
The total parallel resistance from collector to ground is 5 kilohms. To obtain a
3-mc bandwidth, QL, the loaded Q of the output circuit must-be

QL = 10
Therefore, the parallel inductive reactance is

X L2 = 5 kilohms
10
= 500 ohms. or L2 = 2.65 p.h

Mixer

Fig. 23.4. Circuit configuration of mixer design example.


Frequency Heterodyning and Multiplication 325

The required total parallel capacitance must be


1
47T2(30 X 106)2 2.65 X 10-6 = 10 pf
Let C2 = 1- to 6-pf tuning capacitor.
IF Trap. R3 is a biasing resistor; C5 and R5 combine with L3 to series-tune at
30 mc. R5 is included to reduce the Q of the trap. C3 is used to tune with the
parallel reactance of L3 at the radio frequency.
Let L3 = 0.2 fLh and C3 = 1- to ll-pf tuning capacitor.
Let C5 = 150 pf and the Q of the trap Qs = 3. Then

R5 = 1 1 = 12 ohms
27TjC5 Qs 6.28 X 30 X 106 X 150 X 10- 12 X 3
Bias Circuit. To set the transistor bias at VCE = -6 volts and IE = 2 rna, let
R1 and R3 divide the supply vo~tage to - 2 volts at the base of the mixer. With
R4 = 1 kilohm, 2 rna of emitter current will flow. To bias VCE at -6 volts the
collector-ground voltage must be - 8 volts. This requires a 4-volt drop across R 2 .
Since 2 rna of collector current bias is used, R2 should be 2 kilohms.
Oscillator Circuit. The common-base circuit is a convenient high-frequency
oscillator configuration. The emitter and collector signals are almost in phase, and
so a small capacitor between emitter and collector will provide an adequate feed-
back path.
The 255-mc local oscillator must drive the emitter of the mixer at a low impedance
level. A 7T-matching network will suffice to feed this low impedance.
The oscillator load is nonlinear and complex; hence the 7T network elements must
be adjusted experimentally in the final design. A preliminary calculation will now
be made to arrive at approximate values.
Assuming that the impedance seen at the emitter of the mixer is approximately
10 ohms, design the 7T network for an impedance of 500 ohms at the collector of
the oscillator. Then
X L5 = yRlORll = Y500· 10 = 70 ohms
L5 = 0.04 fLh X Cll = X L5 = 70 ohms Cl l = 9 pf
CIO should be about I to 6 pf in order to tune the oscillator to the correct
frequency.
For the feedback capacitance Cs , a value of 1 pfwas found sufficient for all tran-
sistors used. A 1,000-pf feed-through-type capacitor was used for base bypass C9 •
R 6 , R 7 , and Rs bias the oscillator to VCE = -6 volts, and IE = 2 rna.
Figure 23.5 gives the final mixer-oscillator circuit. Typical conversion gains of
20 db were realized.
Figure 23.6 gives a common-base mixer designed for 420-mc operation. The
mixer input circuit uses a hairpin-shaped inductor which was trimmed to resonance
using a Measurements Corporation model 59 grid dip meter. The oscillator-tuned
circuit uses a section of copper tubing cut for 480-mc resonance. Oscillators of
this type have been made to operate above 900 mc.
326 High-frequency Designs

-12v
10 K

Mixer
2N1406

2·30
pf

6.2K 6.2K
L l • L 2 ' 4 turns #18 tinned buss on 3/8 " dia Teflon® rod
Length 9h6'
L3 25 turns #36 copper enamel on eTe LS 9
L4 0.68 J.lh RFC
L5 1 turn #18 tinned buss on 3/8" dia Teflon® rod
Length 112"
Fig. 23.5. 225-mc mixer: 30-mc IF, 20-db average conversion gain.

23.2. FREQUENCY DOUBLERS

Frequency multiplication is usually accomplished by feeding a fundamental


frequency signal into a nonlinear network; from the harmonics thus produced, one
multiple of the fundamental frequency is isolated and amplified. The transistor's
emitter-base diode characteristic, as indicated in Fig. 23.7, is often used as the
nonlinear network required.
The type of frequency doubling discussed here is the tuned-input, tuned-output
type, in which the input is tuned to the fundamental and the output to the second
harmonic.
The curve of Fig. 23.7 indicates that the transistor should be biased at low current
levels to maximize doubling action.
TYpical design steps are:
1. Match the input of the transistor to the source at the fundamental frequency,
using conventional matching techniques.
2. Present a load to the output that corresponds to the correct load for the
Frequency Heterodyning and Multiplicatian 327

60 mc i·f
Mixer out
420mc 0.5·3 pf 2N1406 1·12 pf to 50 n
in
50n

L1 Rectangular rod bent to U·shape; AI", B 2 1/8"


Rod cross section 1/8" X 1/2 "
L2 1 3 14 turns #14 buss on Teflon®rod 3/8 " dia 1/2 " length
L3 8 1/2 turns #36 Formvar wire 1/64 " apart on CTC LS 9
L4 Copper tube 1" depth 1/8" thickness 3/4 " ID

Fig. 23.6. 420-mc mixer: 6O-mc IF, lO-db average conversion gain.

predicted power output at the harmonic desired, using the same techniques;
'IT-matching networks are shown in Figs. 23.8 and 23.9. Since a 'IT-matching
network is a low-pass filter, a trap is needed in the collector circuit to reject
the fundamentaL The trap is made up of a parallel and a series circuit as
shown in Fig. 23.10. The combination ofC1 and Ll offers a high impedance
in the form of a parallel resonance circuit to the second harmonic. C1 , C2 ,
and Ll offer a low impedance in the form of a series circuit to the funda-

Fig. 23.7. Input diode


characteristic curve.
328 High-frequency Designs

8-50 pf 68 pf
I o
50n
load

-12v
Fig. 23.8. 121.5- to 243-mc doubler.

\ Shield
\ L2
\ 0.0861-'h O.OOll-'f
~-----.---;~n
\

load

170-780
of

Ll 3 turns #516 (Air Dux)


+ 12v
L2 4 turns #416 (Air Dux)
La 7 turns #416 (Air Dux)
Fig. 23.9. 21- to 42-mc doubler.

mental. This type of circuit is constructed for the purpose of trapping the
fundamental so that it will not appear at the output. The fundamental
rejection for the circuits in Figs. 23.8 and 23.9 was - 45 to - 55 db. Fig.
23.8 illustrates the common-base configuration, Fig. 23.9 the common-
emitter configuration. The configuration is chosen on the basis of transistor
performance at the frequencies involved.

Fig. 23.10. Funda-


mental trap circuit.
24
AGC of RF Circuits

In addition to gain and passband requirements, amplifiers must be able to handle


input signals having varying dynamic ranges. This requirement is met by controlling
transistor gain as a function of input signal strength. Naturally, AGC performance
varies with transistor type; the example used to demonstrate gain-control charac-
teristics in this chapter is the TI 2N1405 germanium mesa transistor. Regardless
of transistor type, however, the same information must be known.
The following sections illustrate a variety of techniques for controlling a tran-
sistor's gain by varying its d-c operating point.

24.1. REVERSE AGe

Reverse A GC is a term generally applied to a transistor amplifier which is gain-


controlled by holding the collector voltage relatively constant and changing the
current through the device. The expression forward A GC indicates a method
wherein the collector-base (or collector-emitter) voltage is made to vary in accord-
ance with collector current, the gain being directly dependent upon voltage across,
and current through, the transistor. In choosing between the two methods, the
desired end result of the AGC amplifier must be kept in mind and a comparison
made as to the most practical and efficient method by which that result can be
attained. Comparisons can be made in the areas of available power gain, gain
variation, noise figure, overload characteristics, and d-c operating point.
Figure 24.1 illustrates 100-mc dynamic transconductance characteristics super-
imposed upon the d-c transconductance curve. It will be used to demonstrate the
transistor's signal-handling capabilities and attenuation characteristics.
Considering the case of the reverse AGC conditions, a collector-emitter potential
of - 10 volts, a starting current of - 2 ma, and a stopping current of - 0.25 ma were
assumed for purposes of illustration. At the starting point A of - 2 ma, 100-mc
small-signal eSl is shown to produce a collector current of i Cl . If a smaller d-c
voltage is applied between the base and emitter, the operating point will be shifted
to the stop reverse A GC condition at point B. At this point, considerable reduction
in gain has been realized, as illustrated by eS2 and icz . Under these conditions, the
maximum signal which can be handled at the base without excessive distortion is
329
330 High-frequency Designs

-12
I /
V CE = eonstant .1
d-eIYFEI /
--
--
-10

-8
- ----===
:
t== If
I
I
..:---- j.---
---- II
I
/\
iC4
V
til I
E -6
..u
.

-4
100 me
IYrel
e
I
I
top fwd AGC
?tart fwd AGC
'/
~
Cj

tIt{
i I" \
!\/
ica
--
I

-2 -100 me
I !
CI tart rev AGC ;11 !/\ iC2
IYrel Stop rev AGC
r:- f--
I

B~
D{[A: I
~ ~

IJ{!
1 1
I i I foJf:'"
l.....do ~
I I
o -0.5 -0.6 -0.7 -0.8
-0.1 I
I
-or I I I
VBE • volts I
I
I

! 1 : : eS1 I
Start rev AGC:h I I I
Stop rev AGC I I 1
I ~II I
I r-I--"'" I I I
Input I ~ IIeS2 I
I ~ II I
signal
swing I I I
I I 1
I I eS3 1
Start fwd AGC ~( I
Stop fwd AGC
I I 1\ -
I k:: :1 eS4

Fig. 24.1. Mesa transconductance characteristics (direct current and 100-mc alternating current).

approximately 60 mv (rms) as shown by eS2- A voltage swing exceeding this amount


would drive the instantaneous collector current past the zero axis, and distortion
would occur_ This demonstrates the gain-control and signal-handling capacity of
the germanium mesa transistor in the reverse AGC condition, and shows that
amplifiers receiving maximum signal levels of 60 mv (rms) or less can be designed
safely by using this type of gain control.

24.2. FORWARD AGe

Consider now the forward AGC characteristics of the mesa transistor. For pur-
poses of illustration, a supply voltage of -12 volts and a total d-c circuit resistance
of 1,200 ohms have been assumed. Reasons for, and methods of, selecting the
AGC of RF Circuits 331

proper value of total circuit resistance will be discussed later, using more appro-
priate diagrams. The starting conditions using the 1,200-ohm d-c load line will
result in a collector-emitter voltage of - 6 volts at a collector current of - 5 rna.
At this point C of Fig. 24.1, a small signal eS3 is shown to produce a collector cur-
rent of iC3 • If the d-c collector current is now increased in the transistor to point
D by increasing the base-emitter voltage, the stop forward A GC conditions will
result in a collector-emitter voltage of 1.25 volts at a collector current of -9.0 rna.
Again, a considerable reduction in gain has been realized, as shown by eS4 and
i C4 . The signal voltage eS4 is now limited by the minimum instantaneous base-
emitter voltage swinging past the zero axis. Another limiting factor is also imposed
upon the circuit, that of the instantaneous collector voltage swinging below the
instantaneous base voltage.
An a-c load line of 500 ohms was assumed in illustrating eS4 in Fig. 24.1. At
point D, a signal-handling capability of approximately 200 mv (rms) can be real-
ized with negligible distortion. Since the input resistance of the mesa transistor
is approximately 45 ohms at this operating point, this signal level is equivalent to
520 mv (rms) across a 300-ohm input. A further increase in signal-handling capa-
bility can be realized by lowering the d-c load resistance, by lowering the a-c load
resistance, or by introducing degeneration in the emitter circuit (thereby reducing
Yfe) by means of a small unbypassed resistor. However, if the latter method is
used, the maximum available gain will be reduced, and will be accompanied by
a deterioration in noise figure.

24.3. MESA CHARACTERISTICS

The 100-mc h{e characteristics as a function of collector voltage and emitter cur-
rent are shown in Fig. 24.2. The region where V CB = -10 volts reveals the de-
sirable reverse AGC characteristics of this transistor, that is, a strong influence of
emitter current on h fe in the region below 5 rna. It is particularly interesting to
note the relative independence of h{e over a wide range of operating voltage if the
current through the device is maintained at or below 3 rna. This is a very desira-
ble characteristic where ability of the device to handle a large collector voltage
swing is required, as in a power amplifier, a transmitter final, or a similar applica-
tion requiring the delivery of large amounts of power into a load.
Further examination of Fig. 24.2 shows a strong dependence of h{e on operating
voltage if the current through the device is 5 rna or more. It is this particular
characteristic which enables this transistor to be used so effectively as a forward
AGC amplifier. The line AB is a plot of hfe using a 12-volt supply voltage and a
I,200-ohm d-c load. Line A'B' is a similar plot, using a d-c load resistance of 845
ohms. Note the increased attenuation of h fe in the lower collector voltage region
when the transistor is driven to higher currents. Line AB' shows the variation in
hfe , using a supply voltage of 9 volts and a 600-ohm d-c load.
Figure 24.3 is a plot of the same data displayed in Fig. 24.2, except that emitter
current becomes the independent variable and collector voltage is held constant.
This figure more clearly shows the variation in hfe as a function of current through
the transistor, the lower-current region exhibiting relative independence of h{e
332 High-frequency Designs

12

10
I A' V ~ .....
12 v SUPPIY}-..

6
{=100 mc
IE =constant
1,200n . /

~ £. ./
~ 7 A 'l V
- ~V
~ ~ / ........ F-- l-I- .....
.....

..0
""0
-4 ./
~ V ~
'l /
V/li '~ I E ",1.0ma

-
2.0m~
~ l- f-
~j/ W,1-9v
~
..\:!
__ ~~11 ~
supply
600 n load
2
V V . . . 1-84512 nv supply
/I~
V V load 0.5ma
0
/ /3.0ma V
~ B~B,/12.5ma
~
-2

-4
-0.3
/ I
Zma
I

-0.5
{o.~mV
-1.0
VI -2.0 -3.0 -5.0 -10.0
VCB' volts
Fig. 24.2. h'e vs. V CB (at! = 100 mc).

Fig. 24.3. h'e vs. IE (at! = 100 mc).


AGC of RF Circuits 333

200

180
t
160
f= 100 mc
V CB =constant
140

(J)
120
E
.I:
c: 100

.
.~
80 ~ /riep
20

~~ ~~-L' '(-i
10v
1 v
60 15
~VCB :::-rv=::::,~
~ 3v -2v/
J_

--
40 -...-. 10

~~
ciep./
0.

20 =::".... --1 5v - I - - 5 &


Jf"'"
V CB ?v--- 10v <o~

o
'" ~
2V~
-3v
i'-...
r-- r--

~ .....
--- 0

-5

-10
o 2 3 4 5 6 7 8 9 10 11 12

Fig. 24.4. Parallel component of input resistance and capacitance vs. emitter current (at f =
100 mc).

from collector voltage. If reverse AGC is desired, the higher-voltage region (10
to 15 volts) is more attractive because of the greater gain and larger change in hte .
The lines shown are the same as those plotted in Fig. 24.2 for forward gain control,
and show the amount of current change required for any given change in hte•
The results of input-impedance measurements, using the neutralized common-
emitter configuration, are self-explanatory in Fig. 24.4. It should be noted, how-
ever, that the real component of the input impedance, riep, remains reasonably
constant in the forward AGC region. The reactive component becomes inductive
at higher currents and low voltages. However, the resistive component predomi-
nates in this region and the effect is not of major consequence in circuit design.
Figure 24.5 shows the real and reactive components of output impedance in the
neutralized common-emitter configuration. Here, also, the reactive component
becomes inductive, but, again, the effect is minimized because of the predominance
of the resistive component.
334 High-frequency Designs

12 K 6
'vJ=-lOIV
CB
10K 5

8K \\ -Iv
--..... r--...~
f=IOOmc
VCB = constant
4
,~
en I--C oep
E -2v
..c:
0 6K 3v , 3
,,i ......
. §<
c
~
\.I'\.

"-
4K
"" 2 b..

~ ~i1-- -
-lOv
-5v -3v "-
~

":.5i1
-IOv r--....
&
c
2K
~
Iv
-::t '\.. '"
0 '1 o
-2,,/

'" "
roep/

-1

-2
'\ -3
o 1 2 3 4 6 7 8 9 10

Fig. 24.5. Parallel component of output resistance and capacitance (common emitter) vs.
emitter current.

24.4. MAXIMUM AVAILABLE POWER GAINS

Maximum available power gains (neutralized common emitter) at 100 mc are


determined by the following formula (see also Fig. 24.6):

MAG (db) = hIe (db) + 10 10gf(Ciep)2rieproep + roepJ (1)


L 4riep

where Ciep is in picofarads and riep, roep are in kilohms.


This formula is used in conjunction with the current gains and impedances shown
in Figs. 24.3 to 24.5 and, because of the coefficient (0.1) involved, should be used
only at 100 mc. The formula shown was derived from the expression

MAG (ratio) = (h(e)2 4roep


ries
(2)

Examination of the low-current region at first glance seems to indicate an


attractive area for operation of an amplifier, owing to the small current consump-
tion. However, the output-impedance components, roep and Coep (as seen in Fig.
24.5), yield a rather narrow matched bandwidth. Also, the extreme dependence of
impedances on operating conditions eliminates the practicality of attempting to
match in this region. Most amplifier designs would necessarily load the transistor
very heavily in this region, and as a result the power gain would be due mainly to
h(e, which is very small. Figure 24.7 is a sinlilar display of power gain, using
emitter current as the independent variable.
AGC of RF Circuits 335

IE' rna
Fig. 24.6. Maximum available power gain vs. IE.

Figure 24.8 is a combination of Figs. 24.6 and 24.7, and shows constant maxi-
mum available gain curves plotted against voltage and current. The d-c load lines
correspond to those shown on the h(e curves of Figs. 24.2 and 24.3. Although the
actual power gain of any given design will not follow precisely the maximum
available gain, this type of display is very useful as a guide in determining what
to expect from an amplifier (using the 2N1405) in the way of gain control.
Examination of the load lines shows available gain control on the order of 23 db,

20

15

10

..c
-0
ci 5
«
::;;:

0
f=100rnc
I E= constant
-5

-100~----~1----~----~----~4~----~5-----~6~---~7~----~8------9~---~10

Fig. 24.7. Maximum available power gain vs. VOB.


336 High-frequency Designs

f=100 me
12

10

ro
E 8
.....~
6

o -1 -2 -3 -4 -5 -6 -7
VCB • volts
Fig. 24.8. 1CO-mc MAG curves for variation in operating point.

while changing the collector voltage and emitter current by approximately 5 volts
and 5 rna, respectively.
The dynamic transfer characteristics at 45 mc in Fig. 24.9 are used in precisely
the same manner as the corresponding 100-mc curves shown in Fig. 24.1. Again,
for purposes of illustration, a 12-volt supply and a 1,200-ohm d-c load have been
assumed. The input-signal limitations are seen to be approximately 63.5 mv (rms)
in the stop reverse AGC conditions at point B, and 177 mv in the stop forward
AGC conditions at point D. Here again, the signal-handling capability can be
improved by reducing the a-c or d-c load resistance, or by introducing degenera-
tion in the emitter circuit. The latter method will reduce the maximum available
gain, but the accompanying deterioration in noise figure should not be of major
concern in an IF amplifier.
Figure 24.10 illustrates the 45-mc h'e characteristics as a function of operating
point, and shows clearly the influence of current on h'e in the region below 5 rna
at the higher collector voltages. Here again, the flat h'e characteristics over a wide
range of operating voltages should be noted. This characteristic is very desirable
in the output stage of a video IF amplifier where considerable power must be
handled in the collector circuit.
The higher-current region shows the strong influence of collector voltage on h'e.
Note that somewhat higher currents are required at 45 than at 100 me to attain
similar attenuation characteristics. The d-c load lines AB, AB', and A'B' are the
same as those shown at 100 mc, and need no further explanation.
The line A"B" represents a 12-volt supply with a nO-ohm load, and has been
added to this diagram to show the more linear change in h{e at higher operating
AGC of RF Circuits 337

currents. The start forward AGC point A results in a 6-volt, 8.3-ma operating
point with the stop forward AGC point at 1.5 volts, 14.6 mao In applications
where this higher-current drain is undesirable, such as battery-operated portable
equipment, the possibility of using a lower supply voltage to reduce power con-
sumption should be considered. Another method of reducing battery current
consumption is a d-c circuit arrangement whereby two or more amplifiers are
cascaded in series with a 12- to 18-volt supply.

12r-----,------.-----,-----,---.--.------.-----r~~_,

10~----4_----_+----_+----_+--~--4-~~~-----#--r__;

8~·-----4------~----~~--+_~--~------~----r_~~

--------I--~
'"
E 6~----4_----_+----_+~.--_+~-n~H-----~----~----_;
....c.,

4~----4_----_+----_+----~~----~-r--~----~----_;

o - 0.1 - 0.2 -0.3 -0.5 -0.6 -0.7 -0.8


VBE • volts

I
1yD
Start rev AGC
Stop rev AGC C\ "

j'""'I-. ........

~--­
Input
signal
swing I---

Start fwd AGC~---/~


Stop fwd AGC "-
eS3

r----t---i---l

Fig. 24.9. Mesa transconductance characteristics (direct current and 45-mc alternating current).
338 High-frequency Designs

20

18 - Il45L I
~A~ I-~
:.4,- ~ f-
16
IE=constant
f , ......-:: P"'"A V /'
12 v supply
1,200n~~ / ' 'f'"/ / /
//
14

12 -. ",.. ~
I-
~X jJ VI
~~v ~ //' /
/1, H I II
10
~~ I
V
II If 77 r-~9 v supply
600 n load
8 _~'tr
/ / !J If
.0
"0 C)

2 IE 0.5ma £
4 7 if f / It f!-~ 845
12 v supply
n load
q
2
/ "".
0 L p2~
/ ~t I t 720 n load
supply

o I I I~' I II
-2
I Jf J flot
-4 / r B'jf!!;'
Bj
-6
-0.3
/
-0.5 -1.0 -2.0 -3.0 -5.0 -10
VCB, volts

Fig. 24.10. hre vs. VCB (at f = 45 mc).

22

20 )-Lo.ov

-
A A' I 45mc
15 .0V
1 5.0v VCB constant
16 ...... ~ ...........

~
.........

"'- ~ ~
I
N 112 v supply
1,200 n load
12
~ V ~\ -\\" ........... 19v600nsupplyload
'" '"
......

, \\
..c
"0
...:: 8
~
~ ~
N ~ov
4

0
~0.5V
'\
1\ eI~ j12 v supply
f(45n loaf

~~12 v supply
~ ........
~ !'~ ~,
...........
720n load ........
l.Ov
-4

-8
\ '{ B" ~1-2.01
o 2 4 6 8 10 12 14 16 18 20 22 24
IE' rna
Fig.24.11. hre vs. IE (atf= 45 mc).
AGC of RF Circuits 339

The excellent power gains available in the neighborhood of 5 volts make either
of the aforementioned arrangements practical. Pursuing the same line of thought,
consideration should be given to the use of a combination of forward and reverse
AGC control, wherein one or more of the stages is forward-controlled and the
remainder are reverse-controlled. The regions applicable to both forward and
reverse AGC control can be seen in Fig. 24.11 (same data as in Fig. 24.10, with
current as the independent variable).
The resistive and reactive components of the neutralized common-emitter input
impedance under various operating conditions are shown in Fig. 24.12. Figure
24.13 displays the output-impedance components at various voltage and current
levels. The power gains shown in Fig. 24.14 were determined, using the values of
h'e and impedances obtained from Figs. 24.11 to 24.13 in conjunction with the
formula
MAG (db) = h'e (db) + 10 10g[O.02(Ciep)2rieproep + 4roep
r lep
(3) J
(Here, again, it should be pointed out that the formula is valid only at 45 me.)

600

550

500
f=45 me
V CB = constant
450
1
400

350

l\
If)

E
.<::
0
300 30
§< ~,
,.:- VcB::.l v Ciep
\ ~ ,. -,(
250
~ ......-: ...... 25

-
'

~ ~ lOv ~ lY'\ ,~
3~_
200 5v 20
~
~~ ~
150

100

50
r.
lep
~,

~~
'""'-
~ '-- "
~lOv

~ r--
~~
-5v ~,
2v
I

-,
3v\
~

"
15

10

5
1i
.~
"

VCB=-lv

0 2 3
IE' ma
4 5 6
I
7 8

Fig. 24.12. Parallel component of input resistance and capacitance vs. emitter current (at f
45 me).
'" 9 10
o

=
340 High-frequency Designs
16K
\
14K
[=45 me

12K ~\ Vc = -1 v
V CB = constant
6

~\/
V ...............
10K ............ 5
2v
'" '(\ V ~
r-- . . R c oep

"" '"
E
.s::
0 8K 3v 4
~
~
I V~
~
~ V .....

-
I
...c 5v c.
r- r-..,.,
6K 3 §<
r\.
~~
~,
c
-lOv
4K 1'... ........
V c =-10v
~ 2
'"
" ~ ~ ~ --::- ~v )?,ep
2K
,,~ .::::::: ±::f,
3v /2v-

0 2 3
Iv
-
4 5 6 7 8 9 10
o
IE' ma
Fig. 24.13. Parallel component of output resistance and capacitance (common emitter) vs.
emitter current (at f 45 mc). =
The maximum available gain plotted as a function of collector voltage in Fig.
24.15 contains the same information as Fig. 24.14. Combining Figs. 24.13 and
24.14, Fig. 24.16 illustrates constant maximum available gain curves as a function
of operating point. The load lines AB, AB', and A'B' are the same as those shown
for IOO-mc operation. Line A"B" corresponds to the additional load line shown in

30

- V CB 10v

---r--.r--.. - 5v

, --
25

20
-'-
-............... 3v
-r--- -
15
[=45 mc
v CB = constant ...........
~
...............
r-......-2v 1 ro-
......
..c
~
'"
"0
ci 10
~
« ...............
:2
5
......

"
( ciepinpf )
o riep. roep in K ~ -Iv
I I I

I I
-5 r-MAG (db) = hfeCdb) + 10 log 0.02 (Ciep) 2 riep Toep + - -
Toep ~ 4 r iep
J ""- ~~
-10 I I I I I I I I
o 2 3 4 5 6 7 8 9 10 11 12 12.5
IE' ma
Fig. 24.14. Maximum available power gain vs. IE (atf = 45 mc).
AGC of RF Circuits 341

30

I
IE2~:'~ ~
::::::
25
~

20
3ma 0
II /; /
/
.0 15
"0 1/
5ma
c3
<x: ,/
::2: 10
/
5 / I
f=45 mc
= constant

o II
10 ma / h2.5ma
-5
a -1 -2 -3 -4 -5 -6 -7 -8 -9 -10
VeE' volts

Fig. 24.15. Maximum available power gain vs. VeE (at f = 45 me).
Fig. 24.10. It can be seen from this graph that available gain control on the order
of 30 db can be realized by changing the collector voltage and emitter current by
5 volts and 5 ma, respectively.

24.5. D-C CHARACTERISTICS

Figure 24.17 shows the variation in typical d-c forward current gain (hFE) over
a wide range of operating conditions and is used, in the following section, to de-
termine AGe power required. The variation in d-c circuit transconductance as a
function of emitter circuit resistance in Fig. 24.18 is referred to in conjunction with
the offset emitter-ground voltage scale VE to calculate the portion of total d-c load
resistance which should be inserted in the emitter circuit.

24.6. DESIGN PROCEDURE

The following design procedure is useful as a guide to determining proper values


of d-c load resistance, AGe power required, and transformer-turns ratio for for-
ward AGe operation:
1. Using Fig. 24.8 (lOa mc) or Fig. 24.16 (45 mc), draw a d-c load line start-
ing at Vc = supply voltage, and sloping through the desired MAG varia-
tion. Total circuit d-c resistance (RE + R c), as shown in Fig. 24.19, is
represented by reciprocal of slope of the line.
2. Assume a maximum VB available from the AGe supply. Locate the inter-
section of the coordinates of maximum VB available and maximum IE
342 High-frequency Designs

17
~
16

15

14
",
~,
I'-B"
.~
\ [=45 me

13
"~ B] ~ \
\
12 .0 '( II'"
J~ ~ 1\
"0
trl
11 r - I

10
'lf5/ ~ t)( ,,\
co 9 f--'B °l / ~' hJ'~
i'-- L V
III '\V"'- V

" " L
E
A"
......"1 8
.0 / IIl' ~ )X /
7

6
t-~/ V'" .""
~'1
I\. / " ~~o
5 1// / ~ ~V~ ,,~
~o
tnWd'
t":S/SSiPat,
10'2..-::7"
t--~I / A~ ~ <5'~s \o..-~
/ / ..........-::P"""-
/ v , 1\~I/Q ~K("
4

Iln;:;1
f5 V ~r,
' ..... ~".,
3

2 .0/ ,0/
'0/ .0 1
V ~'& ~
~I ~I ~ r--~
.........
ifJ ~o
S ~~
o -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12
V CB • volts
Fig. 24.16. 45-mc MAG curves for variation in operating point.

(from Fig. 24.8 or 24.16) desired in Fig. 24.18. From this point, construct
a line through point A. This line is the slope of R E .
3. Determine AGC power required from the formula
b.IE
PAGe - b.VB - (hFE can be obtained from Fig. 24.17)
hFE
4. Find MAG at starting point from Fig. 24.8 or 24.16.
5. Determine required interstage loss (IL).

IL (db) = MAG (db) - desired power gain (db)

6. Convert IL (db) to IL (ratio) by

IL (ratio) = log-l IL (db)


10
AGC of RF Circuits 343

50

vc~ = const~nt
40

V~:!y
o 30 - -5v
."
L': j.--- ~t-"
~
.1
-Iv
.,...,... ~ r-
I""'"
V
10

o 2 3 4 6 7 8 9 10

Fig. 24.17. D-c forward current transfer ratio (hFEl vs. IE.

VB' volts
100~__~_____
-~1~.0____y -____
-,2._0_________-~3~.0__________
-_4r.0__~~___
-,5.0

c:
o
II

"
i:G
<Il

E 5~~~--~------~~--~~~------~~
......[4

0~1~0~~=-A--------IL.0----------~2.-0----------3~.0~--------~4~.0~--~

-l V BE f.- V E ' volts

Fig. 24.18. D-c transconductance linearization.

Figure 24.19
344 High-frequency Designs

7. Determine NdN2 by

N1 = ~
N2 V "-':;;
where a (generator mismatch factor) = riep/roep, and riep = riep reflected to
primary. The value of a is given by
a = 2IL -1 - y4IL(IL - 1) IL (ratio)
It can be shown that

IL (ratio) = Q) (roep + ri~p)/(9u - QL) F


4roepriep

IL (ratio) = (1 + a)2
4a
Solving for a,
a = 2IL - 1 -I- y4IL(IL - 1)
For a < 1,
a = 2IL - 1 - y4IL(IL - 1)
25
VHF Power Amplifiers

25.1. SELECTING THE OPTIMUM CONFIGURATION

The most important of the transistor parameters which limit the maximum RF
power output are:
Breakdown voltage.
PG vs. bias-power-gain variation with bias.
PD('II!a3»-allowable power dissipated at the collector junction.
These parameters and how they influence the choice of configuration are dis-
cussed here.
Breakdown Voltage. If ideal class B operation is assumed, the static operat-
ing point would exist as shown in Fig. 25.1. An arbitrary load line has been
constructed on a typical set of collector characteristics (either common base or
common emitter). The collector voltage for class B operation will have a minimum
of E(min) (see Fig. 25.1) and a maximum of (2 Vee - E(min»). Figures 25.2 and 25.3
illustrate the voltage and current waveforms for idealized class B operation.
Because it is necessary to stay within the normal operating region of the tran-
sistor, the breakdown voltage (common base or common emitter) limits the peak
voltage, E p ,

E p -- v:ee - E.
(mtn)
< BVe -
= 2
E(min)
(1)

where BVe is the collector breakdown voltage.


The power output can be written as
P _ Ep'2
(2)
0- 2RL

Thus, for a given RL and E(min) fixed by other considerations, the breakdown volt-
age limits the available output power. The maximum output power can be found
by combining Eqs. (1) and (2):
p _ (BVe - E(min»)2
O(mall!) - 8RL (3)

345
346 High-frequency Designs

Slope = _1_
RL

=-..2-------~--::::=--Static operating point

Vee
V e , collector voltage, volts
Figure 25.1

Power Dissipation from Thermal-stability Considerations. The maximum


allowable junction temperature Tj(max) limits the power that can be dissipated in a
transistor. However, in circuit configurations which have high thermal-stability
factors, thermal runaway may occur before Tj(max) is reached. Thermal runaway
occurs when the increase in leakage current due to increasing temperature causes
power dissipation to increase, causing a further increase in temperature and leak-
age current. If this series of events becomes self-sustained, thermal runaway occurs.
In the common-base circuit, the thermal-stability factor is unity. The cornmon-
emitter circuit may have a thermal-stability factor as great as the common-emitter
forward current gain hpE• A large thermal-stability factor may cause thermal
runaway to occur before the junction temperature reaches its maximum rated value
1j(max). When this condition occurs, the power-dissipation rating of the cornmon-
emitter circuit is decreased. .
Additional information on thermal parameters appears in Sec. 4.4 and Chap. 7.
Power Gain vs. Bias. At relatively low frequencies (low compared to the cutoff
frequency of the device under consideration), current and voltage swings are usu-
ally limited by such factors as breakdown voltage, saturation voltage, and maximum
power dissipation. As the operating frequency is increased, the variation in power

I I
--1------1------- BV
l i e
I I
1 1
I
------- Vee
1
1
I
- - 1 - - - - - - - E(min)

Time
Figure 25.2
VHF Power Amplifiers 347

I
--i-------Ip
I
I
I
I
I
I
I

Time
Figure 25.3

gain becomes more important, and in some cases it is the dominant limitation.
Figure 25.4 illustrates the variation of power gain for the 2Nl142 at 108 mc; this
graph shows the changes in power gain for various bias conditions. Small-signal
measurements were used to calculate the power gain shown in Fig. 25.4, with the
assumption that the transistor is unilateralized and conjugately matched at each

100
90
80
70 V eB
60 ( -30v)
VeB

c: 30
'ro
bII
50
40

.~
=::::::::::
-:
(- 25 v)
VeB
(- 20v)

Q;
:s:
0
20
Q.

co
(/)

'"
..0
c:
0
E 109
E 8
0
u
7
"
co 6

""
.~
5
'"Q;
..... VeB
..!!! 4
c: (-1 v)
::J V eB
3
(- 5v)

1~----~------~----~L------L----~
o 10 20 30 40 50
Ie' collector current, ma
Fig. 25.4. Unilateralized power gain vs. bias of the 2Nl142 at 108 mc in common-base
configuration.
348 High-frequency Designs

measurement point. If the short-circuit admittance parameters are used, then


power gain is given by
PG = iY21i 2 (4)
4Gll G22

The rapid decrease of power gain at low voltages and high currents (shown in Fig.
25.4) severely limits the maximum power output obtainable from the 2N1142.
A more graphic method of displaying this limitation is to construct curves of
constant power gain, using the collector voltage and collector current as coordinates.
Figure 25.5 shows these constructions for the 2N1l42 at 108 mc with resistive load
line included. When power output is of prime importance, the instantaneous bias
point should be restricted to a point which has a power gain equal to or greater
than unity, because operation beyond this point requires a greater increase in input
signal than is obtained in the output. This causes a large decrease in efficiency
and an increase in harmonic distortion.
If the limit of unity power gain is accepted, then an optimum load line can be
established. The determination of the best load line may be accomplished by noting
that the locus of the minimum voltage, E(min)' and the maximum current, I p , is the
unity-power-gain curve. This curve establishes a relationship between E(min)
and I p :
(5)

80

70

'"
E 60
....c:-
~ 50
::l
U
...
~ 40
!!!
"0
u
.....Q 30

20

10

0
VCB' collector-base voltage, volts

Fig. 25.5. Curves of constant unilateralized power gain of the 2Nl142 at 108 me in common-
base configuration.
VHF Power Amplifiers 349

The peak voltage is


E < BVe - E(min) [Same as Eq. (1)]
p= 2

The output power may be expressed in terms of BVe and E(min):

Po = Eplp = BVe - E(min)/(E . ) (6)


2 4 ~~

By differentiating expression (6) with respect to E(min), the conditions for the maxi-
mum output power are obtained:

(7)

E
or (min) = BV:e - /(E(min»)
/'(E(mm)
. ) (8)

This value of E(min) is optimum, provided the power-dissipation rating is not


exceeded.
Power Dissipation. The value of E(min) given by Eq. (8) may result in power
dissipation in excess of the transistor rating. In this case E(min) is selected by
writing power dissipation in terms of E(min). Power dissipation P D < PD(ma:c),
where PD(marc) is the maximum allowable dissipation of the transistor for the par-
ticular ambient temperature and heat-sink configuration. Power dissipation (see
Figs. 25.2 and 25.3) is given by

(9)

P D = IpEp
'iT
+ IpE(min)
'iT
IpEp < P
- -4- = D(marc) (10)

Substituting Eqs. (1) and (5) into (10),

PD = /(i,:in») [BVo(4 - 'iT) + E(min)(4 + 'iT)] < PD(marc) (11)

This equation gives the largest value of E(min) which may be used.
Optimum Load Line. The load resistance, R L , may be written as

( (12)
- j

The optimum value of RL is obtained by substituting the smallest value of E(min)


given by Eq. (8) or (11) into Eq. (12).
As stated previously, the above values of E(min), R L , etc., are calculated to deliver
the maximum power output. If more gain is needed, instantaneous bias points
must be restricted to constant power-gain curves significantly greater than unity
(3- or 4-db gain curves). This decreases the variation in power gain, thus increasing
overall gain and decreasing harmonic distortion. The new power-gain curves are
350 High-frequency Designs

used to obtain values of E(min) and RL in exactly the same manner as previously
described.

25.2. MATCHING NETWORKS

Output Matching Networks. VHF transistor power amplifiers are usually


required to drive a load of approximately 50 ohms. A matching network must be
used to transform the 50-ohm load to the value given by Eq. (12) at the output of
the transistor. The matching network shown in Fig. 25.6 is one of the more useful
of those commonly used. L, C1 , and C2 are given by the following equations:

C1 =~
waRp
(13)

C2 =_1_ ~ (14)
waRoV R.-=t
L = LpRp2 + _1_ (15)
Ri + (w oLp)2 wo2Cs

where QL is the desired loaded Q of the circuit and

R p_- R~(out)
(16)
RL + R(out)
R(out) is the output resistance of the transistor at the operating conditions
R _ Rp(woLp) 2 (17)
s - Ri + (w oLp)2

j
Cs =wo2Rs(Ro - Rs)
1
(18)

L-~
p - WoQL (19)
It may be impractical to transform Ro to RL for the desired value of QL. In this
case, a second network can be used to transform Ro to a lower value at the output
of the first network. This network is calculated exactly like the first, but with the
ends reversed.
Another useful matching network is shown in Fig. 25.7. This network eliminates

pi-matching network
Figure 25.6
VHF Power Amplifiers 351

Figure 25.7

a coupling capacitor; loaded Q's of ten or above are easily obtained. The equa-
tions for the circuit elements are:

(20)

(21)

R _ (Ep)2
L - 2Po (22)

L=~ (23)
WoQL

C2 = 1 (24)
woRo v'Rp/Ro - 1
Input Matching Section. Either of the above circuits may be used to match
the input. The circuit of Fig. 25.7 is recommended because a low input impedance
makes a high loaded Q difficult to obtain.

25.3. DESIGN EXAMPLE

As an illustration of the design technique, a 108-mc power amplifier has been


built, using a Texas Instruments 2Nl142. The goal is maximum power output with
a gain greater than 6 db.
Selecting the Optimum Configuration. Figure 25.8 shows the O-db power-
gain curve for the common-base configuration of a typical 2Nl142, and Fig. 25.9
shows Ih(el vs. collector current at 100 mc. Power-gain variation is approximately
the same in both configurations. Since the breakdown voltage is - 35 volts in the
common-base configuration compared to -20 volts in the common-emitter con-
figuration, and since the thermal-stability factor is unity in the common base
compared to a possible value equal to the common-emitter forward current gain
in the common emitter, common base is selected as the optimum configuration.
Selecting the Optimum Load. The O-db power-gain curve of Fig. 25.8 is
closely approximated by
Ip = 55 rna [1 - exp (-aE(min»)] a = 0.33 volt- 1 (25)
where a is determined experimentally to make Eq. (25) fit the curve of Fig. 25.8.
352 High-frequency Designs

60

50
~
-- -
'"
E 40 V
I
I Curve of 0 db unilateralized
Power gain of the 2N 1142

I
10
/ i=108mc

o -2v -4v -6v -8v -lOv -12v -14v


E(min) , minimum collector-base voltage, volts

Figure 25.8

From Eq. (6), the output power is

Po = -554rna- (BVOBO - E(min»[l - exp (-aE(min»] (26)

When power output is maximized with respect to E(min)' the above equation
becomes

aE (min) = 0 = aBVOBO exp (-aE(min» + exp (-aE(min»-l


OPo - aE(min) exp (-aE(min»
(27)
and exp ( - aE(min» + aB V OBO exp ( - aE(min» - aE(min) exp ( - aE(min» =1 (28)
Dividing both sides by exp ( - aE(min» and taking the natural logarithm gives

E
(min) = In (aBVOBO -aE(min) + 1) (29)
a
Using 35 volts for BVOBO gives
E _ _ In (11.55 - 0.33E(min»
(m~n) - 0.33 (30)

A graphic solution for E(min) is shown in Fig. 25.10, and yields the value
E(min) = -7.0 volts
The O-db gain curve shows the value of current that corresponds to an E(min) of
- 7.0 volts (Fig. 25.8). This current Jp is
Jp = 48 rna
VHF Power Amplifiers 353

16
....s::::
~ 14
::l
<.) Ihfe I vs Ic at 100 mc
"0 12
ro .......
~ .n 1\
.g "0 10

~
"E
~ ci
:;::;
~ 8
\
Ql
C
0
~

.2:'
III
s:::: 6
1,\, Vee = - 7 volts

E ~
E
0 4 1\
\
<.)

-
~ 2
~

0 5 10 15 20 25 30 35
I\.
40 45 50 55
I c ' collector current, rna
Figure 25.9

The collector voltage supply, Vee, is given by


V; BVe + E(min)
ee = 2 -21 volts

From Eq. (1),


Ep = BVeBo - E(min) 35 - 7 volts
14 volts
2 2
and from Eq. (12),

25
Not~: point A liS thel SOlutlion Ofl eqUa~iOn 3 0 1

II
20
III
III .....~
Ql
15 ~-f_
C <l'
0
"in
s::::
Ql
E 10
Y=11.55-~E
(min) A/~~
'5
?; /
V
--
5
,.....,..V Note: 0;=0.33

o
--1 -2 -3 -4 -5 -6
I
-7
I
-8
I
-9 -10
E(min) , minimum collector"base voltage, volts
Figure 25.10
354 High-frequency Designs

80

70
1 l'
Slope=-=--
RL 30012
E 60 .
+'
<: 50 V cc ( - 21 v) BVC<-35v)
~
:::J Ip(48 ma)1 I
u 40 I I
~ I I
-§ I I
I
~ 30 I
"0 I I
U I I
.....~ 20 I I
I I
I I
10 I E(min)( - 7 v) I
I I

o -5v -lOv -15v -20v -25v -30v -35v


V c, col/ector voltage, volts
Figure 25.11

Figures 25.11 to 25.13 show the predicted collector current and voltage waveforms
of the 2N1142 at 108 mc. Using Eq. (2), the power output is given by

Po = Ep2 = 196 volts2 = 325 mw


2RL 600 ohms
Power dissipated in the transistor is

PD __ Eplp
7T
+ IpE(min)
7T -
IpEp - 153
-4- - mw =
< P
D(mail!)

Power-dissipation rating of the 2N1l42 in free air at 25°C ambient is 300 mw.
The derating of maximum power dissipation as ambient temperature increase is
4 mw;oC; therefore the 2N1142 is capable of dissipating 153 mw up to 62°C
ambient. The collector efficiency is given by

Collector efficiency = lower ou~put = P POp = 68%


-c power lllput 0 + D

.l1
"0
>
~ 40
= -35v
~
g 30

o 10
Time, m}Lsec
Figure 25.12
VHF Power Amplifiers 355

1 1
III
50 _ _1_ _ _ _ _ _ 1__ __ i______ Ip =48 ma
E I I I
....- 40 I I. I
c I I I
~ I I I
B 30 I I I
I I I
I I I
I I I
I I I

o 10 20
Time, mJ,lsec
Figure 25.13

To calculate the input drive, the overall power gain, Pa, must be determined, since
RF power input is given by
P Po
(in) = Pa
A good approximation of overall power gain in the common base is given by
PG = (RL)Re Yib
where RL = load resistance = 300 ohms, and Re Yib = real part of the input
admittance. The plots of l/ReYib given in Figs. 25.14 and 25.15 show that the
average value is approximately 40 ohms. Thus,

Power gain PG = 34~ = 7.5


.
and RF power mput P
(in) = -PPoa = 3257.5mw = 43 mw

....
':;i fJJ
140

~ E 120
'(3..c
IC=-lOma
-e~
~ ~ 100
I I
Vl C 1
.... 1Il vs V CB of the 2N1142 at lO8mc
~:gj 80
ReYib

> Q)
III
...
'g."5
Q)e.
60
~ -.!::
i-,"iii 40
.-/
..,=
>t~
., III 20
~e.

o -5 -10 -15 -20 -25 -30 -35 -40


V CB' collector· base voltage, volts
Figure 25.14
356 High-frequency Designs

140

'§ Vl 120
~E Ve =1_lOv
·u ..c:
t: ~ 100 I
0(1)
..c:: U 1
Vl c: R y, vs Ie of the 2Nl142 at 108 mc
.....
c: Vl
.lS 80
e ,b
.!!? "ti)
~ ~
'::;..... 60
g~
r ...-=
......,~ 40
.0-

~~
,,0.
20
~

0 5 10 15 20 25 30 35 40 45
Ie' collector current, ma
Figure 25.15

The power gain may be obtained by averaging the values associated with the constant
power-gain curves. This method is probably more accurate but requires plotting
a large number of curves.
Matching Networks. Output Matching. The circuit of Fig. 25.7 is selected as
the output matching network. From Eq. (24),

C2 = 1
waRoY Rp/Ro - 1
where w = 2'1Tf = 2'1T X 1.08 X 108 cps
Ro = 50 ohms
Rp = RL = 300 ohms
Thus, C2 = 13.2 pf
From Eq. (23),
R 300
L = wJ:!£ = (2'1T)(1.08 X 108)(10) = 0.44 ph
and from Eq. (20),

C1 =w:;'p - C2~ - ~: )= (2'1T)(1.08l~ 10 )300 - 13.2~ - :~o) 8

C1 = 38.2 pf
Input Matchirtg. The curves of Figs. 25.14 and 25.15 show ReYib vs. bias at 108
mc. Figure 25.16 shows the equivalent input circuit. Figure 25.17 shows the in-
put matching network circuit. Since Xeq is inductive and Req is 40 ohms, it was
decided to resonate Leq with C3 and allow slight mismatch between Rg and Req.
Leq for the 2N1l42 in the common-base configuration is 0.02 to 0.5 /Lh. Therefore,
C3 is chosen to vary from 9 to 180 pf.
VHF Power Amplifiers 357

Req
400

Fig. 25.16. Input equiva-


lent circuit. Fig. 25.17. Input matching network.

Construction and Testing. The networks were constructed of high-Q coils and
capacitors. Each component was tested on the Boonton RX meter to be sure it
exhibited the proper impedance at lOS mc. The complete amplifier schematic
diagram is shown in Fig. 25.1S.
The amplifier was built in a brass chassis. All components were measured and
fitted so as to assure minimum lead length. The input was driven by a General
Radio l2l5-B unit oscillator. Power output was measured with an H.P. 430C
power meter using a bolometer mount, with a General Radio lS5.0-mc low-pass
ffiter inserted between the output matching network and bolometer.
Comparison of Predicted and Experimental Results. The predicted results
were based on an idealized situation in which the following effects were neglected:
1. Power loss due to r~ (collector body resistance).
2. Matching network losses.
3. Harmonic generation.
The collector body resistance losses amount to approximately 20 mw. A conserva-
tive estimate of the a-c collector body resistance can be made by measuring the
saturation voltage at a large value of collector current. For the 2Nl142,

r ~ = VCE(sat) ~ 30 ohms
Ic
Thus the losses for the design example are
h,2r~
Pir,c = -4- ~ 20 mw

The loss in the intrinsic base resistance, rb, was found to be negligible.

Fig. 25.18. 108-mc amplifier.


358 High-frequency Designs

The matching network losses can be computed as

P 1m = 20 10glO 0- g:J db

where QI is the loaded Q of the matching network and QuI is the unloaded Q.
For the design example,
P 1m = 20 10glO (1 - !(~oo) = 0.25 db - 20 mw
The output of the amplifier circuit was measured on an H.P. model 430C power
meter with bolometer mount and found to be 285 mw. When a low-pass coaxial
filter was inserted between the matching network and the bolometer, the output
decreased to 270 mw. Thus, the harmonic content was 15 mw.
Table 25.1 lists the experimental results along with the necessary adjustment.
The predicted result, shown in line 5, is based on an idealized situation in which
the losses in the collector body resistance and matching network are neglected.
When the measured power output is adjusted by adding lines 1,2, and 3, line 4 is
obtained. A comparison of line 4 and line 5 shows that when the measured result
is adjusted to conform with the idealized situation, good agreement is obtained
between measured and predicted values of RF power output.
The measured doc power input of the amplifier circuit was 512 mw compared to
a predicted value of 478 mw. Thus, the intrinsic collector efficiency N ic =
310 mw/512 mw = 61%. Intrinsic collector efficiency is defined as the fundamental
output power divided by the doc input power if the collector body resistance is
zero. The measured collector efficiency is Nc = 270 mw/512 mw = 53%, com-
pared to a predicted value of 68%. A major portion of the difference between the
measured and predicted values of efficiency is due to the losses cited above, which
are included in the calculation of intrinsic efficiency. The remaining difference is
probably due to harmonics and losses in the auxiliary network such as power sup-
plies, etc.
The total device dissipation is the doc input power plus the a-c input power
minus the a-c output power. For the design example,
A-c input power = 43 mw
D-c input power = 512 mw
Total input power = 555 mw
The a-c output power at the transistor terminals is equal to
Fundamental power = 270 mw
Harmonic generator loss = 15 mw
Loss in matching network = 20 mw
A-c output power = 305 mw
Total input power = 555 mw
A-c output power = 305 mw
Total device dissipation = 250mw
The total device dissipation can be used to find the maximum allowable ambient
VHF Power Amplifiers 359

Table 25.1
I. Measured value, mw .......................... , .............. . 270
2. Collector body resistance loss, mw ..................................... . 20
3. Matching network loss, mw ........ , .................. . 20
4. Fundamental power generated in the intrinsic transistor, mw. 310
5. Predicted power output, mw. . . . . . . . , ....... . 325
6. Harmonic generator loss, mw. . . . .......... . 15

temperature. The thermal resistance for the 2N1l42 is 0.1 °C/mw with an infinite
heat sink, and 0.25° /mw in free air. Under the operating conditions of the ex-
ample, the maximum ambient in free air (with no heat sink) is 37"C, and 75°C
with an infinite heat sink.
26
Remote-control System

This chapter describes a remote-control system that demonstrates the high-


frequency capabilities of TI alloy mesa germanium transistors. Good remote-
control performance may be achieved over a range of one mile; under ideal condi-
tions with no obstruction or interference, range may be extended to over two miles.
The system components, a transmitter and a receiver, are described separately,
and suggestions for adjusting the system for optimum performance are presented.

26.1. TRANSMInER

Figure 26.1 is a block diagram of the transmitter which consists of an RF and


an audio section. The RF section includes a crystal oscillator and a keyed power
amplifier. A free-running multivibrator turns the power amplifier on and off at
an audio-frequency rate.
Figure 26.2 is the transmitter schematic. The crystal oscillator, Q3, is a common-
base oscillator at the resonant frequency of Y 1 . Feedback is from the collector to
the emitter through the collector-emitter capacitance of Q3. C5 forms a voltage
divider with this capacitance to provide the proper feedback level to sustain
oscillation. R 6 , R 7 , and R9 are bias resistors; Rg is a decoupling resistor; C4 is an
RF bypass capacitor, while C6 tunes the collector circuit to the 27.255-mc crystal
frequency. Output is taken through a two-turn link at the cold end of L 1 .
The power amplifier, Q4, is operated as a driven common-emitter stage. RlO
and Rll are bias resistors. The bias voltage on the base of Q4 is varied at

Crystal
oscillator

Multivibrator Fig. 26.1. Transmitter


block diagram.

360
Remote-control System 361

12v 50 n load
50mw
+
output

R2
Y1t:::l

~
Parts List
Resistors Kilohms Watt Capacitors Transistors
Rl 6.8 \2 Cl, C2 O.OI-.uf disk Ql, Q2 2NI274
R2 20 \2 Ca O.I-.uf disk Qa, Q4 TI 395
Ra, R4 100 \2 C4, C r, Cg, C9 0.05-.uf disk
R5 6.8 \2 C5 56-pf disk
Rs 47 \2 Cs, CIO 33-pf disk
Rr 4.7 \2
R g, R9 150 ohms 1;' Inductors
RIO I \2 L 1, L2 Adjustable RF coil (1. W. Miller
Rn 47 ohms \2 4403 or equivalent). Add 2
turns of No. 24 enameled wire
Miscellaneous on cold end.
Sl Push-button switch (normally open) La RF coil, 15 .uh (Delevan 1537-40
Y1 27.255-mc crystal or equivalent).
Fig. 26.2. 27-mc transmitter.

an audio rate which keys the output stage. Cg and Cg are RF bypasses; ClO is the
collector-tuning capacitor. Output is taken from a two-turn link wound on the
cold end of Lz, to a 50-ohm antenna.

26.2. RECEIVER

As shown in the block diagram (Fig. 26.3), the receiver consists of a super-
regenerative detector, quench filter, audio amplifier, audio filter, power detector,
and relay. The receiver was designed for maximum performance consistent with
simple circuitry.
Receiver operation is as follows: The incoming signal, a carrier in the 27-mc
region modulated with an audio tone, is coupled into the collector circuit of Ql
which acts as a superregenerative detector.
The detector operates as a self-quenched oscillator with audio taken across the
collector load resistance. This stage is desirable for remote-control equipment
362 High-frequency Designs

Fig. 26.3. Receiver block diagram.

because of its high sensitivity. The lack of selectivity can be tolerated since audio
filtering is used.
Output from the detector consists of a supersonic (about 200-kc) quench signal
and the modulation from the incoming signal. This signal is applied to the quench
filter which passes only the audio signal to the amplifier. Without this filter, the
quench signal would overload the audio stages, preventing their proper operation.
The audio signal from the quench filter is amplified in a two-stage tuned ampli-
fier. By requiring a particular audio tone as well as the proper RF signal, the
amplifier discriminates against undesired signals. How this selectivity is obtained
will be discussed later in detail.
The amplified audio is detected and the resulting direct current used to operate
the relay. The relay contacts can be used to control other circuits as desired.
The receiver schematic diagram is shown in Fig. 26.4. The incoming signal is
coupled into the collector circuit of Q1, through a two-turn link on the cold end
of L 1 .
L 1 and C3 provide a tuned circuit for the superregenerative detector, Q1, which
is operated as a common-base self-quenched oscillator with R4 and C5 in an RC
quench-determining network. L4 isolates the emitter from RF ground; C1 and C2
are RF bypasses. R4 is the d-c emitter resistance. C2 , L 2 , and C7 form a quench
filter, while R5 is a volume or sensitivity control.
Q2 and Q3 comprise a two-stage tuned audio amplifier. L3 and C12 form a
resonant tank circuit at 1,000 cps. At all frequencies other than this resonant
frequency, the collector of Q3 is placed very near the a-c ground, thus reducing the
gain of Q3. The stages are direct-coupled, with R7 and R9 providing a feedback
d-c bias arrangement. Cl l is an audio bypass while C6 , C9 , and C 13 are coupling
capacitors.
Coupled to Q4 through T 1 , the audio signal is rectified by the emitter-base diode
and the amplified current is used to operate relay K 1 . C14 bypasses the relay and
smooths the pulsating direct current. Contacts of K1 may be used to actuate the
necessary control equipment.

26.3. ADJUSTMENT SUGGESTIONS

Observe the normal precautions for building high-frequency equipment. Short


leads and isolation of stages help eliminate unwanted feedback. The receiver
should be aligned in the order suggested below.
I. Transmitter adjustment:
A. Connect a 0- to 1.5-volt voltmeter across R lO .
B. Adjust L1 until maximum meter reading is obtained. (Disconnect
either end of L3 to perform this adjustment.)
Remote-control System 363

12v
-\1\++

- -
Parts List
Resistors Kilohms Watt Transformer
Rl 22 Y2 Tl 10-2 kilohms (Thordorson TR7
R2 2.2 Y2 or equivalent)
Ra, R4 1 1/2

R5 10 Potentiometer Inductors
R6 2.7 'h
Ll Adjustable RF coil (J. W. Miller
R7 10 'h
4403 or equivalent). Add 2
Rs 270 ohms Y2
turns of No. 24 enameled wire
R9 150 ohms Y2
on cold end.
Transistors L2 30-mh choke (Bud CH 1227 or
Ql 2N2188 equivalent).
Q2, Qa, Q4 2Nl274 La 8.S henrys (Stancor CI279 or
Capacitors equivalent).
C1 O.OOI-fJf disk
L4 RF coil, 15 /.Ih (Delevan 1537-44
or equivalent).
C 2, C 7, C10 0.05-pf disk
Ca IS-pf disk
C4 18-pf disk Miscellaneous
C 5 , C12 0.002-pf disk Kl Typical: Sigma IIF-2300-G/SIL
C6, C9, C1a 5-fJf electrolytic or equivalent
Cs, C14 100-/.If electrolytic
Cl l 40-/.If electrolytic
Fig. 26.4. 27-mc receiver.

C. If a dummy load or RF power meter is available, connect to the out-


put jack of transmitter. If a dummy load or RF power meter is not
available, connect suitable antenna to the transmitter.
D. Connect a 0-1 volt voltmeter across R l l . Adjust L2 for minimum
meter reading. Readjust Ll for maximum reading across R l l . A
364 High-frequency Designs

reading of 0.376 volt across Rll represents an input of approximately


92mw.
E. Reconnect L 3 •
Note: Steps A through D must be performed with switch, Sl, closed.
II. RF section alignment:
A. Connect suitable antenna to receiver.
B. Set L1 at mid-range.
C. Set R5 for maximum output.
D. Connect an a-c VTVM (or oscilloscope) between collector of Q3 and
ground. (Note: If L 3 C 12 circuit has not been tuned to transmitter
modulation frequency, disable it by disconnecting either end of C 13 .)
E. Turn on transmitter.
F. Adjust L1 for maximum VTVM reading. (Use the transmitter with-
out an antenna or bottom cover as a signal source.)
III. Tuning L 3 C12 audio filter:
To produce audio selectivity, a filter composed of L3 and C 12 provides a
low-impedance path to ground for Q3 at all frequencies other than 1,000
cps. For best gain and selectivity, L3 and C12 must be tuned to match
the modulation frequency of the transmitter. This is accomplished as
follows:
A. Complete RF alignment of receiver.
B. Set R5 at mid-range.
C. Connect an a-c VTVM between collector of Q3 and ground.
D. Tum on transmitter.
E. While observing VTVM reading, change value of C12 until a maxi-
mum reading is obtained.
IV. Audio gain adjustment:
Maximum setting of R7 is dictated by noise output of the detector in a
no-signal condition. Too high a setting will prevent the relay from drop-
ping out.
A. Current method:
1. Complete RF alignment of receiver.
2. Obtain value of dropout current for relay to be used.
3. Insert a 0- to 5-ma milliammeter between relay and 12-volt battery.
4. Increase audio gain control, R 5 , until relay current is 0.5 ma less
than dropout current.
5. Lock R5 in this position.
B. Voltage method:
l. Complete RF alignment of receiver.
2. Connect a d-c voltmeter from collector of Q4 to ground. (Note:
Use voltmeter with at least 20,000 ohms/volt.)
3. Adjust R5 until the drop across the relay coil is equal to resistance
of relay coil times dropout current minus 0.5 mao
4. Lock R5 in this position.
Note: The current method is preferred to the voltage method.
If only a short range is desired, greater protection against accidental operation
may be achieved as follows:
Remote-control System 365

1. Complete RF alignment of receiver.


2. Complete tuning of L 3 C12 audio filter.
3. Mount receiver's antenna in its permanent location.
4. Connect antenna to receiver.
5. Place transmitter at maximum range where operation is desired.
6. Tum on transmitter.
7. Adjust R5 until relay just pulls in.
8. Lock R5 in this position.
This setting may be considerably lower than if adjusted for maximum sensitivity;
hence the greater protection.

26.4. PERFORMANCE

This circuit provides enough gain to operate many small-signal relays. The re-
quirements for the relay are: (1) The value of pull-in current must not exceed 150
rna, and (2) the product of the pull-in current and the coil resistance must not exceed
12 volts. A typical relay is Sigma llF-2300-G/SIL with a coil resistance of 2,300
ohms and a current of 4.6 rna.

1,000
Signal level at which
receiver completely
I- blocks
vs
Transmitter
modulation
freqUency~

Jl
0 100
>
~
cn-
(ij
c
.§ r-
.l!!
'"cc
.l!!
c
....'"
'"
(ij
10
c
DO
en Minimum signal
r-
level required ,
to pull in relay
vs

j
Transmitter Note: This graph
modulation compiled using a
freqUency~\ 50% modulated
signal
I I
1
100 1,000 10,000
Modulation frequency, cps

Figure 26.5
366 High-frequency Designs

As shown in Fig. 26.5, the receiver sensitivity to the desired signal is 1.2 IW at
the antenna terminals to energize the relay. At 750 cps, a signal level of 3.7 /Lv is
required, and at 1,400 cps, 10 /Lv. Unmodulated carriers have no effect, regardless
of strength. Because the level at which the receiver will block varies inversely
with the modulation frequency deviation from 1,000 cps, further selectivity is ob-
tained. In order for an unwanted RF signal to energize the relay, it must be
amplitude-modulated between 750 and 1,400 cps, and produce a voltage on the
antenna within the limits shown on the graph.
The total receiver current drain with a 12-volt battery is 9 rna with no signal
input, and 14.5 rna when saturated. With the receiver properly aligned and no
signal input, the following d-c voltages were measured at the transistor terminals.
(All voltages are referred to ground and were measured with a VTVM.)

Transistor VB Vo VE

Ql -0.94 -9.4 -1.38


Q2 -0.3 -0.69 0
Q3 -0.69 -11.8 -0.51
Q4 -0 -12 0
Part 4
Switching-mode Designs
27
Switching Design Considerations

The basic concept in switching circuitry is that of a discrete change of state. The
change of state may take the form of a voltage change, a current change, or both.
It may be used to perform logical operations as in a computer, or to transfer energy
as in relay drivers and switching regulators.
Two static states are considered in transistor switching circuitry, the ON state
and the OFF state. In saturated switching circuits, the ON state is marked by a
very low collector voltage and relatively large collector current, and the OFF state
is marked by a relatively high collector voltage and a very small collector current.
The selection of components and supply voltages which allow this change of state
will be called the d-c design procedure.
A transistor cannot change states in zero time. The time interval between ini-
tiation and completion of the switching action is a measure of switching speed.
The rate at which a computer can do work is determined largely by the switching
speed of its circuitry, and the efficiency of a power-switching circuit can be affected
by switching speed. In some applications, a slow transistor with a high power
rating can be replaced by a faster transistor with a lower power rating.
Efficiency of a computer circuit is difficult to define because information, power,
and cost are measured in different units. The basic question is where to compromise
between a fast, complex, high-power circuit and a relatively slow, simple, inexpen-
sive low-power circuit.

27.1. WORST-CASE D-C DESIGN

One of the first steps in switching circuit design is the selection of circuit values
to ensure turn-on and turn-off in the circuit. Separate equations relating circuit
and transistor parameters can be written for the ON and OFF states, and two cir-
cuit parameters, such as the values of RB and RK in Fig. 27.1, can be selected as
the dependent and independent variables, respectively.
A worst-case design may be accomplished by assuming that all transistor and
component tolerances go to their worst-case extremes at one time. F or example,
in the flip-flop circuit of Fig. 27.1 the ON and OFF equations for Q2 are:
369
370 Switching-mode Designs

Fig. 27.1. Basic flip-flop.

VBB + VBE(on)2
ON: BB = -=---;;;---;;---=-----:-----:c~-_::_=__--_::_=__--__:::_-__:_ (1)
Yom - RLIloBOl - V BE(On)2 _ _ 1_[VoC2 - YOE(Sat)2 _ VBE(O{f)l + YOE(Sat)2)
RK2 + RLl hFE2 \. &2 RKl

OFF: RB = YBB - V BE(o{f)2 (2)


VBE(off)2 + VOE(sat)l -
RK2 + I oBo2

where the underlines indicate the minimum, and the overlines the maximum,
specified values. Voltage and current magnitudes are used for simplicity in
applying the equations to either NPN or PNP transistors. VBE(otn is normally a
reverse-bias voltage. If a slight forward bias is used in the OFF state, the following
substitution must be made in the OFF equation [Eq. (2)]:
VBE(off)2 ~ - VBE(otn2

Note that two distinct Voo terms are contained in the ON equations. In most
switching circuits with a single Voo supply, the worst-case condition for turn-on is
YOCl = VcC2 = Yoo
In circuits with external d-c loads, YOCl and VCC2 can be represented by Thevenin
equivalent generators. In this case, both YOOl and V002 should be used to ensure
absolute worst-case conditions.
The transistor maximum and minimum parameter values are obtained from the
data sheet. The resistor and power-supply maximum and minimum values are
determined from the following relations:
x= X(nominal) (1 + A) (3)
and X = X(nominal) (1 - A) (4)

where A is the tolerance of X expressed as a decimal fraction. Temperature effects


on resistors are sometimes ignored, assuming that the temperature change is com-
pensated by a uniform drift of all resistors in the same direction. Temperature
Switching Design Considerations 371

effects on transistors, however, must be considered. The following conditions


usually exist at temperature extremes:
Low Temperature High Temperature
Maximum lCBO Maximum
Minimum VCE(.a') Maximum
VCE(sa') Minimum

Thus, turn-on worst case occurs at low temperature, and turn-off worst case occurs
at high temperatures.
Equation (1) gives the minimum allowable value of RB for turn-on, and Eq. (2)
the maximum allowable value of RB for turn-off. If several trial values of RK are
substituted in (1) and (2), the resulting values can be plotted as in Fig. 27.2. Com-
binations of RB and RK above the ON curve ensure that Q2 will turn ON; combina-
tions below the OFF curve ensure that Q2 will turn OFF. Combinations above
the ON curve and below the OFF curve ensure d-c stability in both the ON and
OFF states.
The worst-case design procedure yields the most reliable individual circuit, but
it greatly limits maximum fan-in and fan-out of logic stages. Since the probability
of all components having worst-case values simultaneously is small, a statistical
approach to d-c design may be used to increase fan-in and fan-out of logic stages.

120

100

80
ON equation
Vl
E
..c
..Q 60
:.;;:
~
i:q

OFF equation
40

20

a 8 10
R K • kilohms
Fig. 27.2. Sample plot of worst-case ON and OFF equations.
372 Switching-mode Designs

The resulting reduction in the number of stages may increase the overall reliability
of a computer. A special case of statistical design techniques is satisfactory for
many applications-nominal values of resistance and supply voltage are used with
worst-case values of transistor current gain and leakage currents. The yield of
usable circuits is usually very high for this type of design. Statistical design is not
discussed in detail here because of its complexity.

27.2. DESIGN EXAMPLE

Consider the circuit of Fig. 27.1. Assume the following circuit values and
specifications:
Temperature range ...................................... -55 to +55°C
Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10 volts ±5%
VBB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . + 10 volts ±S%
VBE(om . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2 volt
R L1 , RL2 .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. I kilohm ±5%
Transistor .............................................. PNP, germanium alloy
hpE (at _55°C, VCE = -I volt, Ic = -10 rna) .... , ......... 10 min
VBE(on) (at _55°C, IB = -I ma,Ic = -10 rna) ............. -0.6 volt max
VCE(sat) (at + 55°C, IB = -I rna, Ic = -10 rna) ............. -0.5 volt max
I CBO (at +S5°C, VCE = -10 volts) ......................... -100 Ita max

The magnitudes of these worst-case values were substituted in Eqs. (1) and (2).
Equations (3) and (4) were applied to the resulting values of RB and BB to obtain
nominal values, which are plotted in Fig. 27.2. Any point within the shaded area
would be a valid solution to the problem. The point RB = 20 kilohms, RK = 3
kilohms was chosen for maximum d-c stability. A point on the ON curve would
result in minimum ON current, lB!. A point on the OFF curve would result in
minimum OFF bias.
D-c design equations for logic circuits become more complex than the simple
equations shown here, but the same principles apply.
28
Digital Circuits

A multivibrator circuit uses two active devices with positive feedback in such a
way that the two devices tend toward opposite states, one OFF, one ON. The
bistable, astable, and monostable multivibrators are discussed below. The Schmitt
trigger is also discussed here because of its similarity to multivibrators.

28.1. BISTABLE (FLIP-FLOP) MULTIVIBRATOR

The bistable multivibrator is characterized by its ability to maintain either of


two possible states. It is widely used in counting circuits, shift registers, and
memory circuits. The basic circuit is shown in Fig. 28.1.
To analyze the flip-flop operation, assume that Ql is ON and Q2 is OFF. With
Q2 OFF, enough current flows from Vee through RL2 and RKl to forward-bias the
base of Ql and saturate Ql. The collector voltage of Ql is then VeE(sat). The R K2 ,
RB2 divider network holds the base of Q2 reverse-biased, thus keeping Q2 OFF.
If a disturbance is introduced to start the turn-on of Q2 or the turn-off of Ql, regen-
eration can occur, and the opposite state (Q2 ON, Ql OFF) will follow.
Design Procedure. The d-c design procedure is one of the first steps in the
design. The philosophy of d-c design is explained in Chap. 27.
Before applying the ON-OFF design equations, certain other design decisions
must be made. Because many of the design considerations are interrelated, there
are very few concrete rules. The final design will be a compromise of the considera-
tions presented below.
The collector saturation current,
Vee
Ie(sat) ~ RL (1)

should be chosen considering the following factors:


1. The supply voltages Vee and V BB should be much larger than the transistor
saturation voltages VeE(sat) and VBE(on)' to minimize effects of variations in
these voltages.
373
374 Switching-mode Designs

Note: RE and C E
are used
when VBB=O

Fig. 28.1. Basic flip-flop with emitter bias.

2. Vee and RL should be such that the load line does not cross any breakdown
region on the collector characteristics.
3. Total circuit dissipation and transistor dissipation should be kept within
limits.
4. The current gain, hFE' varies with collector current in many transistors.
Ie(sat) should be such that hFE is a reasonable value.

For maximum speed, the product RLCOB should be much less than 1/27T/r, and
RL should be much greater than hie. These two conflicting requirements are diffi-
cult to optimize analytically. A propagation time test is described in Sec. 5.5.
Propagation time can be measured on several trial circuits to determine the circuit
for maximum speed.
Mter Vee, VBB , and RL are chosen, values of RK and RB can be calculated. The
flip-flop d-c design equations are identical with Eqs. (1) and (2) of Chap. 27.
If the flip-flop drives external d-c loads to ground, substitution should be made
for Vee and RL in Eq. (1) of Chap. 27:
YeeRn (2)
Yeel should be replaced by
RLl + EXI

RLI should be replaced by EnRLI (3)


RLI + Bn

Vee2 should be replaced by YeeRX2 (4)


RX2 + EL2

should be replaced by RX2BL2 (5)


BL2
RX2 + EL2
where Rn and RX2 are the external loads on QI and Q2, respectively.
Digital Circuits 375

Self-bias. A single-supply flip-flop may be made by returning RBl and RB2 to


ground and using an external emitter impedance, RE and CEo A nominal value of
emitter voltage (VE ) between 0.5 and 1.5 volts is commonly used. The approximate
value of RE is
RE~ VER L (6)
Voo - VE
In this case, 1::'001, V002 , and VBB in the worst-case ON equation should be
modified:
YOO1 should be replaced by Yoo - VE2 (7)
17OG2 should be replaced by .Yoo - 17E2 (8)
17BB should be replaced by VE2 (9)

V - fOE(sat)2)(b.FE2 + l)RE
where E2 = (!:::'oo
l1FE2RL2 + (bFE2 + I)RE
(10)

and VE2 is the emitter voltage when Q2 is ON.


Flip-flops are usually constructed symmetrically; this makes it necessary to
analyze only one of the two transistors. The equations shown are written for Q2.
If an asymmetrical flip-flop is designed, it will be necessary to interchange the
subscript numbers in the equations and analyze Ql separately.
If the first value of RE substituted into the equations does not give a good d-c
solution, a different value should be tried. The time constant RECE should be much
greater than the transition period of the flip-flop. If I 01 (sat)"* I 02(sat) in a single-
supply flip-flop, RE should be replaced by a zener diode to eliminate changes in
VE as the flip-flop changes states.
The counting flip-flop shown in Fig. 28.2 is formed by adding a steering net-
work to the basic flip-flop. The trigger capacitors CT charge and discharge in such

Input
Fig. 28.2. Counting flip-flop.
376 Switching-mode Designs

a manner that the steering points Al and A2 follow the collectors of QI and Q2,
respectively. This action is such that the circuit is triggered with each negative
excursion of the input signal. Assuming that the circuit has been in the state shown
long enough for the steering network to be stabilized with QI ON and Q2 OFF,
then the voltage at A I will be VeE(sat)' and the voltage atA2 will be [RK/ (RL + RK)] Vee.
Then diode DT2 has a large reverse bias, while DTl has a small reverse bias. An
incoming negative pulse will forward-bias DTl and turn OFF QI, thereby turning
ON Q2. This process is repeated for opposite conditions when the next triggering
pulse occurs.
Selection of Steering Network. All capacitances should be small to mini-
mize RC time constants, but they should also be large enough to provide sufficient
triggering and overdrive. CK is chosen to provide overdrive during the turn-on
period.
The speedup capacitor CK reduces the transition time of the circuit by providing
overdrive to the transistor being turned ON. CT couples the trigger to the tran-
sistor being turned OFF. First-approximation values of C T and CK are given by

CK = K Qs (11)
Vee

and CT =K QB (12)
Vee
where Qs is the stored base charge necessary for collector saturation, and QB is
the total stored base charge. The constant, K, is an empirical safety factor; values
of 1.5 to 2.0 are commonly used.
Equation (12) is a good approximation for the value of C T when the rise time of
the triggering pulse is short. However, if the triggering rise time is long, the value
of C T must satisfy the following inequality:
0.8CT Vp > K(1Bltr + QB) (l3)
where Vp is the trigger-pulse amplitude, 1Bl is the base current supplied to the ON
transistor, and tr is the voltage rise time of the trigger pulse.
It may be necessary to optimize C T and CK experimentally for maximum speed.
CK may be optimized with the propagation time test of Sec. 5.5, and C T can then
be optimized in the actual flip-flop circuit. Storage time increases with tempera-
ture, making high temperature the worst case for triggering.
The time constant RKCK should be such that
(14)
where T is the period of the triggering signal.
RT should be large to minimize loading, but RTCT should be small enough to
permit recovery of the steering circuit within a cycle. If a speedup diode is not
used,
3R~T< ; (15)
Digital Circuits 377

10v

10K

270 pf 270 pf
~------;-------~---o-lOv
All diodes 1 N914
Qv Q2 2N1304
Resistor and power supply
tolerances ± 5% In p ut <>--::J..-
Fig. 28.3. 2S0-kc flip-flop.

If a speedup diode is used, RTCT should be such that

0.7R T C T <; (16)

The diodes should have a recovery time in the same order of magnitude as the
flip-flop transition time, and the diode capacitance should be much lower than the
circuit capacitances.
Typical Design. The flip-flop circuit shown in Fig. 28.3 was designed to operate \
in the temperature range -55°C TA< <
+55°C with an input frequency of 250
kc. Circuits from a typical production run of this circuit could be expected
to operate at speeds considerably greater than 250 kc.

28.2. ASTABLE (FREE-RUNNING) MULTIVIBRATOR

The astable or free-running multi vibrator has no stable state. It is commonly


used as a square-wave generator. The basic astable multivibrator circuit is shown
in Fig. 28.4. To analyze its operation assume that Dl and D2 are not connected
into the circuit; i.e., the emitters of Ql and Q2 are connected to ground. Also as-
sume that Ql has just turned ON, and Q2 has just turned OFF at t = O. The volt-
age across C2 is approximately Vee, which makes VBE2 = - Vee. The initial voltage
across C1 is approximately zero. The base end of C1 is clamped to VBE(on) of Ql.
C1 charges rapidly through RL2 to Vee. The R L2 C 1 time constant causes the lead-
ing edge of the output wave to be rounded (see Fig. 28.5). Ql is held ON by the
current from V BB through RBI. The collector end of C2 is clamped to VeE(sat) of
Ql. C2 begins to charge in such a way that V BE2 rises toward V BB . When VBE2
reaches VBE(on)2, Q2 begins to turn ON; the resulting negative voltage excursion at
the collector of Q2 is coupled through C1 to the base of Ql, turning Ql OFF. The
circuit at t = T/2 is now in the opposite state from that at t = O. The reverse
378 Switching-mode Designs

Note: Dl and D2 are used to


prevent base·emitter
breakdown of Ql and
Q2 if BVEBO < V cc

Fig. 28.4. Basic astable multivibrator.

VCE(off) /' r r
V Cl
VCE(sat)
o ! !
!
!

Collector voltage of Ql

VCE(sa3_~1.:-:-:-:-:-~~!~_ _+===+!_ _ _~===~_ __


Collector voltage of Q2 : :
! J

VBE(~)~: ~: 1/
V
BEI
- Vce
V V
!
V
!
Base voltage of Ql !
!
J
V BE(on)! .JI'

V BE2 O~V-;----!-t----7""-v~t7
- Vce I

Base voltage of Q2 I I I
T
t=O T
2

Fig. 28.5. Astable multivibrator waveforms.


Digital Circuits 379

process is repeated from t = 7'/2 to t = 7'; at t = 7', the circuit has returned to its
original state.
Design Procedure. The load resistors and the transistors are chosen, based on
the same considerations as in the bistable multivibrator. RB is chosen to ensure
saturation of the transistor.
R < h (EBB - VBE(on»BL1 (l7)
B1= _FE1
Vee - EeE(sat)
If BVEBO < Vee, diodes should be used in the emitter leads as shown in Fig. 28.4.
The reverse breakdown of the diode should be greater than (Vee - BVEBO ).
The OFF time of each transistor is controlled by the time constant RBC. The
time constant and the OFF time are related by

C1 tOFF(l)
R
B1 = In[(VBB + Vee - VBE(on»/(VBB - VBE(on»]
(18)

If VBB = Vee, and Vee ~ VBE(on), then


tOFF
RBC ~ In2 = l. 44tOFF (19)

A variable VBB can be used to control the frequency of the multivibrator, but in
cases where a constant frequency is desired, a single supply is usually used for con-
venience and for better frequency stability with voltage changes. Equation (18) is
reasonably correct at low frequencies if
VBB
leBO + lEBO ~ RB

A higher frequency is affected by input capacitance and stored base charge. It is


impractical to build a frequency-stable multivibrator if CVee ~ QSB.
If the multivibrator is constructed symmetrically, the duty cycle of the output
will be 50%; lower duty cycles can be achieved by using different values of C. The
multivibrator must not be made so nonsymmetrical that the waveform of the tran-
sistor with the short OFF time is limited by the RLC time constant. For example,

Fig. 28.6. Sure-starting


astable multivibrator.
380 Switching-mode Designs

lK lK

2N1304 2N1304

Fig. 28.7. 50-kc free-running multivibrator.

if Q1 is to have a short OFF time, 3RL1 C2 < tOFF1. If the supply voltages are ap-
plied slowly to the circuit of Fig. 28.4, both Ql and Q2 may go into saturation and
stay. This locked-up condition is less likely to occur when the supplies are switched
ON sharply. The circuit shown in Fig. 28.6, however, will always start, regardless
of how slowly Vee is applied.
Typical Design. The circuit of Fig. 28.7 was designed using the transistor and
load resistor of the bistable flip-flop of Fig. 28.3. The 2N1304 has a base-emitter
breakdown voltage of -25 volts, making the emitter diodes unnecessary. This
circuit oscillates at approximately 50 kc.

28.3. MONOSTABLE (ONE-SHOT) MULTIVIBRATOR

The monostable or one-shot multi vibrator has one stable state. It is a hybrid
between the bistable and astable multivibrators. Consider the circuit of Fig. 28.8.
Q2 is held ON by the base current through R B2 • Q1 is held OFF by R Kl , R Bl , and
- VBB• If either transistor is triggered out of its stable state, regeneration can oc-
cur, and the astable state (Ql ON, Q2 OFF) will exist for a time determined by
R B2 C. Q2 is held OFF as in the free-running multivibrator, and Ql is held ON as
in the bistable multivibrator. After C has charged such that Q2 begins to turn ON,
Ql turns OFF and the cycle is complete.

Trigger 0---+-+--1
input

V BB Note: Dl used if IBVEBO(2)1<lVcci


Fig. 28.8. Basic monostable multivibrator.
Digital Circuits 381

IK

2Nl304

Fig. 28.9. 10-.usec monostable multivibrator.

Design Procedure. R Ll , R L2 , R Kl , R Bl , Vee, VBB , and Ql are selected as out-


lined for the bistable multi vibrator. R B2 , C, and Q2 are selected as outlined for
the astable multivibrator. The diode is used only if BVEBO (2) <
Vee. The OFF
time of Q2 is given by
tOFF - R B2 C 2 In 2 = O.7R B2 C 2

Triggering is usually accomplished at the base of Ql.


Typical Design. Figure 28.9 shows a typical one-shot design. Values are taken
from the circuits of Figs. 28.3 and 28.4 to form this circuit. Its output pulse width
is approximately 10 }.Lsec.

28.4. SCHMITT TRIGGER

The Schmitt trigger is a regenerative circuit which changes states abruptly when
the input signal crosses specific d-c triggering levels. The use of the Schmitt trig-
ger to produce a square wave from a sinusoidal input is a common application.
Consider the circuit of Fig. 28.10. Ifv(in) is zero, then Ql is OFF and Q2 is ON.

Fig. 28.10. Basic Schmitt trigger.


382 Switching-mode Designs

With Q2 ON, V E > O. If V(in) is allowed to rise to (VE + V BEI ), QI begins to con-
duct, lowering the collector voltage of QI and raising VE. These excursions will
reduce the base current in Q2 to the point that Q2 comes out of saturation. The
decrease in le2 causes VE to fall, which increases IBI. Both transistors are active
and the circuit is regenerative. The regeneration continues until QI is ON and Q2
is OFF. Note that V E is now less than it was initially because RLI > R L2 . Con-
sequently, the trip point is also lowered. The two trip points are called the upper
trip point, UTP, and the lower trip point, LTP.
This difference in trip points makes possible the snap action which reduces the
effect of noise. When V(in) falls to the LTP, the reverse operation occurs, and the
circuit returns to its initial state.
Design Procedure. The transistor type, the Vee, and RL2 are selected consid-
ering the same factors outlined for the bistable flip-flop. VE2 , the emitter voltage
when Q2 is ON, should be much greater than the normal variations in VBE(on).
VEl, the emitter voltage when QI is ON, should be greater than V E2 by the desired
difference in trip points. Neglecting the current in R Bl , the upper and lower trip
points are:
UTP = V E2 + V BEI and LTP = VEl + V BEI
Large differences in trip points tend to increase the regenerative action of the circuit.
Values of VEl greater than 1 volt and differences in trip points of 0.5 volt are
common. Mter selecting desired values of UTP and LTP, and hence VEl and V E2,
RE and RLl are calculated by

and

RK2and RB2 are selected as outlined for the self-biased flip-flop, using Eqs. (1) of
Chap. 27 and (11) through (15) of this chapter for the ON case, and Eqs. (2) of
Chap. 27 and (14) and (15) of this chapter for the OFF case.
The external base resistor RBl is used to limit base current in QI. RBl should be

lOv

1.0 K

2N1304

Fig. 28.11. Typical Schmitt trigger.


Digital Circuits 383

small and hFEl large to minimize the voltage drop across RBI, but RBI should be
much greater than RE to minimize changes in VEl when V(in) goes highly positive.
The output is usually taken from Q2 because VEl rises after V(in) becomes greater
than the UTP, and this change shows up in the collector. VE2 does not change in
this manner since V(in) is isolated by the OFF transistor, Q1.
Typical Design. The circuit of Fig. 28.11 is a typical Schmitt trigger. The
UTP = 2.2 volts and the LTP = 1.8 volts. It will perform well at frequencies of
100 kc or less. The 2N1304, with a minimum h pE of 40, was selected to reduce
the separation between V(in) and the trip points. The capacitor may be removed
for low-frequency operation.
29
Logic Circuits

29.1. SATURATED TRANSISTOR LOGIC CIRCUITS

The transistor switch is widely used as the basic logic element in many control
operations as well as in the arithmetic section of most digital computers. Six types
of circuit configurations using the transistor as a switch are:
1. Transistor-resistor OR circuit.
2. Transistor-resistor AND circuit.
3. Transistor-resistor NOT (inverter) circuit.
4. Transistor-resistor NOR circuit.
5. Transistor-diode NOR circuit.
6. Transistor-diode NAND circuit.
The operation of each of the above circuits is discussed here, and design techniques
for the NOR and NAND circuits are described. In order to describe operation of
the individual circuits, a brief discussion will first be given of the binary number
system, and of Boolean algebra and the manner in which it is applied to analysis
and synthesis of control and computer systems.
The Binary Number System and Boolean Algebra. Generally, switching cir-
cuits have two stable states: ON or OFF, low voltage or high voltage, low current
or high current. The decimal number system is incompatible with such circuits.
It is desirable therefore to convert decimal numbers to binary numbers for ma-
nipulation within a computer or control circuit. Numbers are written in the deci-
mal and binary systems in an identical manner. The decimal number system is
easily understood because it is familiar, whereas a binary number system appears
strange and complex.
To show the similarity of these number systems, consider first the manner in
which the decimal number "one hundred and sixty-seven" is represented in the
decimal system. It is written "167" and represents (1 X 102) + (6 X 101 ) +
(7 X 100), which is equal to 100 + 60 + 7, or 167. Each digit is multiplied by ten
raised to a certain power. The value of the power of ten by which a digit is multi-
plied is determined by the position of the digit in the number. Thus, a digit in
the first column (reading from right to left) is multiplied by 1, a digit in the second
384
Logic Circuits 385

column is multiplied by 10, and a digit in the third column is multiplied by 100.
This process is extended for higher-order digits.
The base of a number system is called its radix. The base or radix of the decimal
system is 10, and of the binary system 2. The binary system uses only the digits 0
and 1 and is ideally suited to switching circuits. A binary number written as
101011, with the most significant bit to the extreme left, is interpreted as (l X 25 )
+ (0 X 24) + (1 X 23 ) + (0 X 22) + (1 X 21) + (1 X 2°), which is equal to 32 +
o + 8 + 0 + 2 + 1, or the decimal number 43. Rules for binary and decimal ad-
dition, subtraction, division, and multiplication are identical. Although more
digits are required to express numerical values in the binary system than in the
decimal system, the ease with which binary representations can be manipulated by
electronic circuitry has led to almost exclusive use of some form of the binary system.
Boolean algebra is a type of mathematics used in conjunction with the binary
number system. This algebra may be used to express the relationships between
inputs and outputs of various circuits or systems. For example, consider the sym-
bolic diagram of Fig. 29.1. Inputs A, B, and C are combined in such a manner
that an output signal is present only if A and Band C are present; otherwise, there
is no output.
Throughout this section, the following nomenclature is used in Boolean expres-
sions: The word AND is understood when there is no symbol between letters; a
plus symbol is defined as OR; the prefix NOT is added to a letter having a bar
over it. An expression for the diagram of Fig. 29.1 can be written:
Output = ABC (1)
and is read "Output equals A and B and c." As in ordinary algebra, there are
certain rules which govern manipulation of Boolean algebra expressions. If the
above equation is expanded in accordance with the rules, many equivalent expres-
sions can be written for the diagram of Fig. 29.1.
A relationship between inputs and outputs for the symbolic diagram of Fig. 29.2 is
Output =A + B + C (2)
and is read "Output equals A or B or c."
Figure 29.3 is a symbolic diagram having as a Boolean expression
Output =A (3)
which is read "Output equals not A."
The equations which express relationships between inputs and outputs of the
three symbolic diagrams are referred to as logical expressions. Circuits employed
to realize these logical expressions are known as logic circuits. Logic circuits used
to realize the symbolic diagrams of Figs. 29.1 through 29.3 are the AND, OR, and

~
A
:D O",P"~-ABC E[>E
A
B
C
+
Output=
A+B+C

Fig. 29.1. AND gate. Fig. 29.2. OR gate. Fig. 29.3. Inverter.
386 Switching-mode Designs

b\~ ·1
Output=

f.::lJ L--_-+\ I 1°",,"'·-ABc ..


A+B+C

Fig. 29.4. NAND gate. Fig. 29.5. NOR gate.

NOT (inverter) circuits, respectively. These three logic circuits are the basic build-
ing blocks from which control and arithmetic operations are synthesized. When
the symbolic diagrams of Figs. 29.1 and 29.3 are combined as shown in Fig. 29.4,
the relationship between inputs and outputs is
Output = ABC (4)
and is read "Output equals not the expression 'A and B and C."
When the symbolic diagrams of Figs. 29.2 and 29.3 are combined as shown in
Fig. 29.5, the relation between inputs and outputs is
Output =A + B + C (5)
and is read "Output equals not the expression 'A or B or C." If De Morgan's
theorem is applied to expression (4), the result is
Output = A + B+ C (6)
When both sides of expression (5) are negated, the result is
Output =A + B + C (7)
If the reference is inverted in either expression (6) or (7) (A substituted for A, B

x y
x y S C

0 0 0 0

1 0 1 0

0 1 1 0

1 1 0 1

x = Input number one


Y = Input number two
S=Sum
C=Carry
1 =Signal present
0= Signal not present

Xy+x+ Y=Xy+ YX
Fig. 29.6. Half-adder.
Logic Circuits 387

~~~
=I NOR H~
. ~ = Output=A+B+C+D

A
B

Output=A +B+ C+D

C
D

Fig. 29.7. Four-input, four-output NOR logic.

substituted for Ji, etc), the expressions are identical. Therefore, a circuit which
will perform either the NAND (negative AND) or the NOR (negative OR) func-
tion can be made to perform the other by reversing the reference levels of the sig-
nal voltages; hence these circuits are interchangeable. A NOR or a NAND cir-
cuit can serve to formulate any and all combinational logic functions. As an
example, Fig. 29.6 shows how five NOR functions are combined to form a half-adder.
It would be ideal if logic circuits were not limited in their number of inputs and
outputs. The importance of maximizing the number of inputs and outputs is il-
lustrated in Fig. 29.7. Suppose that at some point in the system it is desired to
take four separate inputs, perform a NOR function with them, and feed the output
to four separate identical stages. The logic function is performed with one logic
block, and hence one transistor which has a fan-in of four and a fan-out of four.
In order to perform the same operation with a fan-in and fan-out of two, however,
six logic blocks or six transistors are needed.
The discussion now proceeds to transistor logic circuits showing how the AND,
OR, NOT, NOR, and NAND functions can be accomplished with the transistor
switch.
Series and Parallel Transistor Logic. Figure 29.8 shows how logic functions
may be realized using transistors in series. Figure 29.9 shows how the same logic
functions can be accomplished using transistors in parallel. These methods of ob-
taining logic functions require one transistor for each input. Logic circuits
accepting more than one input and supplying more than one output are often
preferable.
Transistor-Resistor Logic NOR Circuit. Figure 29.10 shows a TRL circuit with
M inputs and N outputs. A negative signal to any of the input resistors will cause
the transistor to be in saturation, and the collector voltage will be near ground
potential (binary 0). The collector voltage will be negative (binary 1) only when
neither input A nor B nor C is negative. Because the OR and NOT functions are
performed by the input resistor network and the transistor, respectively, the overall
circuit is considered to be a NOR circuit. A logic expression for this circuit is
388 Switching-mode Designs

(a) (b)
Gates using NPN and PNP transistors
and gate for normally open switches
or gate for normally closed switches
Note: Phase inversion of input
Fig. 29.8. Basic logic circuits using series transistors.

Output =A + B + C (8)
The above equation can be rearranged to the form
Output = ABC (9)
This latter expression for the TRL output shows that the circuit performs the AND
operation on the inverse of each of the inputs.

+ lOv

Output Output

Gates using NPN and PNP transistors


or gate for normally open switches
and gate for normally closed switches
Note: Phase inversion of input
Fig. 29.9. Basic logic circuits using parallel transistors.
Logic Circuits 389

(M) RK

~ I
I
I
RK [2] Outputs
Inputs (2)
[1]
(1)

Note:
For PNP transistors For NPN transistors M = Number of inputs
VBB is positive and V EB is negative and N = Number of outputs
Vee is negative Vee is positive

Fig. 29.10. Basic NOR TRL circuit.

A TRL logic block is assumed to be driven by other identical TRL elements, and
its outputs are to be used to drive additional TRL circuits having the same values
of M, N, resistors, and voltages. Figure 29.11 shows a connection ofTRL circuits.
Arbitrary selection of all voltage and resistance values for a TRL circuit will
usually not give satisfactory operation. The worst-case method of designing a
reliable circuit is described here. Figure 29.12 shows the conditions for minimum
base drive to a TRL transistor. All input transistors but one are in saturation, and
all resistances, voltages, and transistor parameters have simultaneously gone to their
extreme values in the direction which would tend to prevent Ql from saturating .
.The equation shown with this figure is an expression for a minimum value of RB
in terms of all other circuit variables. A line over a variable indicates a maximum
value and a line under a variable indicates a minimum value. M = inputs, and
N = outputs. Any value of RB greater than the value calculated from this equation
will allow Ql to be in saturation when at least one input transistor is at cutoff.

Fan OUT

Input

Fig. 29.11. Connection of TRL circuits.


390 Switching-mode Designs

Figure 29.13 shows a worst-case condition for maintaining Ql at cutoff. The


equation presented with this figure determines the maximum value which RB can
have for reliable operation of the circuit.
All values on the right sides of the two worst-case equations (except for BK and
RK ) are selected from collector current requirements, the expected range of satura-
tion voltages, the resistance and voltage tolerances, the desired values of M and N,
the maximum leakage currents, the reverse base-emitter voltage, and the anticipated
minimum value of current gain. The minimum value of RB is calculated for various
nominal values of RK by using the ON equation of Fig. 29.12. The maximum
value of RB is calculated in a similar manner by using the OFF equation shown
with Fig. 29.13. Nominal values of RB may be plotted for both cases by using the
following relationships:
RB = RB(nominal) (1 + M) (10)
and BB = RB(nominal) (1 - flR) (11)
where fl equals the tolerance expressed as a decimal fraction.

RK [1]

y
CE(sat) 11K [2]
t---'-~~
VBE(on) 1
1
1
1

~
[2]

[N]
'----'VV'v
11K XBE<_'(Q
TRL ON equation (use magnitudes only):
j7BB + VBE(on)
BB (M l)(VOE(,at) VBE(on) + (Vee - ICBoRL - VBE(m»& + (N - I)RL(VBE(vn) - VBE«(I7I.) ~(Voo - J::OE(lIat) + VBE(on) - KOE(Satl)
EK RLEK + RKRL(N - I) + EKRK l1FE \ - EL EK/N

Fig. 29.12. TRL NOR circuit, ON condition.


Logic Circuits 391

V BE (off)

TRL OFF equation (use magnitudes only):

RB = _----'-=V'-BB"---=-V-'Bc::;:E=(o.:..cff)'--_
VBE(off) + VCE(sat) + I
BK/M BX

Fig. 29.13. TRL NOR circuit, OFF condition.

There are general rules of thumb to be applied when choosing which valid solution
to use. The theory behind this design procedure will permit the choice of any
point lying on or between the two curves. However, by moving away from the
boundaries, a safety factor is incorporated in the design; hence, reliability increases
as the point chosen moves farther away from the boundaries of the area of solution.
If speed is a prime consideration, it is best to choose a point where the values of
the resistors are the smallest possible; the speed of the circuit increases as the point
chosen moves toward the origin of the graph. If power dissipation is of prime
importance, then a point is chosen where the values of the resistors are the largest
possible; power dissipation decreases as the point chosen moves away from the
origin of the graph.
All circuit parameters, in addition to transistor parameters, affect the area of
solution. In general, large values of VBB and Vce increase the area of solution, but
this means using high-impedance circuits (large values of RL , R B , and RK)' Thus,
the operating speed may be reduced appreciably as supply voltages are increased.
The area of solution becomes smaller as supply voltages decrease, and as N, M, or
VBE(off) increases. In certain cases, the ON and OFF curves may not intersect.
This means that no combination of RB and RK will allow the circuit to operate
reliably under adverse conditions.
Transistor-Diode Logic NOR Circuit. Diodes may be used in conjunction with
transistors, as in Fig. 29.14, to perform the NOR function. This type oflogic block
is usually referred to as a TDL (transistor-diode logic) NOR circuit. Figures 29.15
and 29.16 show worst-case circuit conditions and equations for the ON and OFF
states, respectively, of this type of logic block.
392 Switching-mode Designs

[N]
(M) ~ 0
0 I.
[2] Outputs
Inputs (2)
[1]
(1)

M = Number of inputs
N = Number of outputs

Fig. 29.14. Basic NOR TDL circuit.

Transistor-Diode Logic NAND Circuit. A second type of transistor-diode logic


block, the TDL NAND circuit, is shown in Fig. 29.17. Resistor RL is a load
resistor for the input transistors and, in conjunction with the input diodes, performs
the AND operation on input signals. The transistor inverts the output of the AND

I
(M)~ ..?:-
~ON) ! [N] 1__

(1)

(OFF)

I M
:P::JDO
1__ [N] 1 Vv-.,BK YRE(MlE!'2.

NOR TDL ON equation (use magnitudes only):

Fig. 29.15. TDL NOR circuit, ON condition.


Logic Circuits 393

NOR TDL OFF equation (use magnitudes only):


-
R YBB - VBE(off)
B=
(VBE(off) + VOE(sat) - Yn) +I
R
_K
BX

VBE(off) is assumed to reverse-bias the transistor.


Fig. 29.16. TOL NOR circuit, OFF condition.

circuit and the complete circuit performs the NOT-AND (NAND) operation. A
logical expression for the output of this circuit is
Output = ABC (12)
where A, B, and C are input levels to the diodes. Figures 29.18 and 29.19 show
worst-case circuit conditions and equations for the ON and OFF states respectively,
of this type of logic block.
Table 29.1 shows design parameters and circuit values for TRL NOR logic, TDL
NOR logic, and TDL NAND logic. The circuits using silicon transistors were
designed to operate over the range -55 to 125°C, The circuits using germanium
transistors were designed to operate over the range -10 to +55°C, For additional
circuits see the "Texas Instruments Incorporated Computer Manual."
Speedup Capacitors. In saturated transistor logic circuits, storage time is
generally the most significant component of propagation time (see Propagation

~ [N] 0
o (M) ~

t---I*-....;[;",,2,;;,,]- 0 Outputs
Inputs (2)

~~1_
0_(;"",;1)'--... ----'V\ Iv-+--+--I
[1]

M = Number of inputs
N=Number of outputs

Fig. 29.17. Basic NAND TOL circuit.


_ N
I cBo + EIDO
_ ~I [1] -! (1) VCC

~
(,.) '-::!-(OFF) J -I DO
~I [2 ] TV ~~5:at) + YD
I !1L
1

Yc".., + y" fCCC


RL
N .r
1
I CBO+ "'-
~IDO (1) •

--
[1] ~ (2)

(OFF)
f""--
I I [2] 1!::CE(sat)+
Do
~ --- YD 17- I~ ICBo+(N -l)IDo

>, f,;:I
I 1 1
V 1 I
1 -
I 1
[N] !::CE(sat) + -D :
I........ 1 --- 1
lIDO (2)
~I ~
M
Do
1 N 1 I DO 1
-
II cBo + " '-
~IDo 1
V BB (OFF) ---=- :
[1] ~ (M)
I

~
M)
~
JE.O
~
I [2] ,---!::CE(sat) + !::D I DO

• (OFF) -=
1£0
,
.1 [N] • !::CE(sat)
--- + YD
TDL ON equation (use magnitudes only):
RB = VBB + VBE(on)
- Yee - RrN[IeBo + (N - l)IDo] - VBE(on) _ N [Vee - (I:eE(sat) + VD) + (M _ l)IDo _ (VeE(sat) + VD + VBE(Om)]
RL + RK .b.FE BL RK
Fig. 29.18. TDL NAND circuit, ON condition.
Table 29.1

Logic constants Transistor constants Diode constants Circuit designs

Transistor
Logic VBE(on) V UE(,,"') VD RK for RBfor
type Ic. R L, h pE lCBO IDa Max maxM maxM Tp,*
Vee VBB %V %R VBE(otn min at max at Tma.r,
ma kilohms max f----- and N, andN, msec
-55°C mill max mill max (la mill at _55°C (la
1\1 N kilohms kilohms

2N744 TRL
NOR 10 10 10 I 2 5 0 20 0.87 l.l 0.15 0.33 10 2 3 2.7 30 33
TDL
NOR 10 10 10 I 2 5 0 20 0.87 l.l 0.15 0.33 10 0.15 0.9 10 10 6 1.2 47 23
TDL
NAND 10 10 10 I 2 5 0 20 0.87 l.l 0.15 0.33 10 0.15 0.9 10 4 5 3.0 27 14t
2N2412 TRL
NOR 10 10 10 I 2 5 0 20 0.85 l.l 0.08 0.26 5 2 4 2.7 33 77
TDL
NOR 10 10 10 I 2 5 0 20 0.85 l.l 0.08 0.26 5 0.15 0.9 10 10 6 1.8 6.8 75
TDL
NAND 10 10 10 I 2 5 0 20 0.85 l.l 0.08 0.26 5 0.15 0.9 10 10 6 3.0 30 21t
2N964 TRL
NOR 5 5 10 0.5 2 5 0.1 27 0.36 0.56 0.08 0.2 15 2 3 2.0 15 37
TDL
NOR 5 5 10 0.5 2 5 0.1 27 0.36 0.56 0.08 0.2 15 0.28 0.8 I 10 8 1.2 47 26
TDL
NAND 5 5 10 0.5 2 5 0.1 27 0.36 0.56 0.08 0.2 IS 0.28 0.8 I 5 3 2.0 7.5 II §
2N797 TRL
NOR 5 5 10 0.5 2 5 0.1 32 0.36 0.51 0.07 0.15 10 2 4 2.0 16 43
TDL
NOR 5 5 10 0.5 2 5 0.1 32 0.36 0.51 0.07 0.15 10 0.28 0.8 1 10 9 1.0 43 35
w TDL
'0 NAND 5 5 10 0.5 2 5 0.1 32 0.36 0.51 0.07 0.15 10 0.28 0.8 I 10 5 2.7 12 1St
'"
* Measured for M = N = 3 if obtainable. Germanium transistor temperature design range: -10 to + 55°C.
t 33-pf speedup capacitor used. Silicon transistor temperature design range: - 55 to + 125 ° C.
t47-pf speedup capacitor used. Silicon TRL temperature design range: 0 to + 125°C.
§ 20·pf speedup capacitor used.
396 Switching-mode Designs

~I 0

TDL OFF equation (use magnitudes only):

R- B-
_ V BB - VBE(off)

(VD + VCE(sat)
~=-~~~~----~~+IBx
+ VBE(off)) -

BK
VBE(off) is assumed to reverse-bias the transistor.
Fig. 29.19. TDL NAND circuit, OFF condition.

Time, Sec. 5.5). In the NAND circuit, speed can be greatly improved by shunting
resistor RK with a capacitor as shown in Fig. 29.20. The circuit applies constant-
current drive to the transistor during the steady-state operation, but during the
switching transient, the capacitor is essentially a low impedance and the drive
approaches a voltage drive. The stored charge on the capacitor during saturation
of the transistor should be only large enough to equal QSB, the stored base charge
of the transistor. The capacitor should have a time constant which will permit it
to recover sufficiently between incoming pulses. Making CK too large defeats its
purpose since this adds a time constant that may limit the maximum clock rate.
The equivalent circuit and circuit time constant obtained the instant after the drive

O---I~w.l---,

Fig. 29.20. NAND logic with speedup capacitor.


Logic Circuits 397

T VCE(sat) + Vn

(b)
Fig. 29.21. Time constants added.

transistor is switched ON are shown in Fig. 29.21a, OFF in Fig. 29.21b. Again,
care should be taken in selecting CK to assure that both time constants are small
enough to allow the capacitor to recover sufficiently during the ON and OFF
intervals of the clock pulse.
Comparison of Logic Types. The designer of computer logic circuitry continu-
ally strives to handle more bits of information per second per dollar. The emphasis
in a particular system will be on either or both of the above requirements. Com-
ponent count in a circuit, component reliability, ease of manufacture, power
dissipation, and maximum fan-in and/or fan-out are other factors affecting the
choice of design.
Although each system must be evaluated after the basic objectives have been
decided, some general statements can be made. These general comparisons apply
to the circuits without speedup capacitors. When capacitors are used the speed is
increased significantly, but in the TRL circuit severe cross talk or noise problems
arise that present significant disadvantages outweighing the speed advantage.
TRL vs. TDL. When speed and maximum fan-in and fan-out are not of prime
importance, TRL circuitry is commonly used in place of TDL circuitry because of
its simplicity, low cost, and component reliability. The speed ofTRL logic circuits
is device-dependent up to the point where time constants of load resistors and
capacitors limit the speed. Generally, a faster transistor gives faster logic circuits.
TDL NOR vs. TDL NAND. The main differences between TDL NOR and TDL
NAND circuitry are in speed and maximum fan-in and fan-out capabilities.
NAND circuitry is faster, whereas NOR circuitry is capable of higher fan-in and
fan-out. Both these differences can be attributed to the way in which the diodes
are used in the circuits. TDL NAND circuitry may be a bit more difficult to design,
but its excellent speed performance outweighs this disadvantage. In some systems,
the higher fan-in and/or fan-out of TDL NOR circuitry may be used to decrease
the number oflogic stages required. Therefore, if speed is not the primary concern,
TDL NOR is more economical.
Circuitry Speed. The speed of logic circuits in general depends a great deal on
the external circuitry. As with high-frequency techniques, low impedance (low
resistance as well as low stray capacitance) is important. Thus, high-speed operation
involves lower resistance, lower capacitance, and higher currents.
398 Switching-mode Designs

A significant advantage of the mesa transistor in logic circuits is that the impor-
tant design-limiting parameter (transistor current gain) increases as current in-
creases. Therefore, much faster propagation times can be obtained by operating
at an increased current level. Although this carries a penalty of increased power
dissipation, epitaxial devices with their lower internal voltage drops help reduce
this problem. The epitaxial technique also provides higher current-carrying capa-
bility and lower device capacitance with the same mesa geometry.

29.2. COMPLEMENTARY LOGIC CIRCUITS

A PNP current mode switch is shown in Fig. 29.22a. Current generators at the
emitter and collector supply constant currents of 12 and 11 as shown. With the
base of Q1 grounded, the current 12 divides between Q1 and Q2. The base-to-
emitter voltage drop of Q1 and also Q2 is approximately 0.2 volt. This causes the
common-emitter point to be 0.2 volt positive with respect to ground. If a positive
voltage greater than 0.2 volt is applied to the base of Q1, the base-to-emitter diode
of this transistor becomes reverse-biased, and the collector current drops to the
value of the collector reverse current. h then flows almost entirely through Q2.

(a) A PNP current


mode switch

n
vee+ v Il Vee
(b) Relative pol a rities of
input, collector and
emitter voltages

Vee - VI

(c) An NPN current


mode switch

Fig. 29.22. Current mode switches.


Logic Circuits 399

When a negative voltage greater than 0.2 volt is applied to the base of Q1, this
transistor conducts, and consequently Q2 will turn OFF. 12 then flows into the
emitter of Q1.
When Q1 is OFF, the voltage at the collector is
(13)
When conducting, the collector current of Q1 is aI2 where a = lei IE. A portion
of 12 supplies 11 , and what is left of 12 flows through R L . The collector voltage of
Q1 then becomes
VOl =- Vee + (aI2 - I 1 )RL (14)
If 11 is chosen to be 1212, then Eqs. (13) and (14) can be written as
VOl ~ - Vee - I1RL (15)
and (16)
The total voltage change at the collector of Q1 is
Ve = 2(11RL) (17)

The quantity 12 may be relatively large. It is for this reason that the circuit of Fig.
29.22a is considered to be a current switch. Relative polarities of input voltage,
emitter voltage, and collector voltages are shown in Fig. 29.22b.
Since nonsaturated switches operate at higher speeds than saturated switches, it
is necessary to keep the current mode switch out of saturation. The emitters of
Q1 and Q2 are near ground potential while the collector potentials vary by about
(- V ee -+ 11RL). By choosing - Vee sufficiently large, saturation may be avoided.
It should be noted that two outputs are available, one at each collector; the com-
puter designer derives added flexibility from this complementary output. The
input signal at the base of Q1 is given as plus and minus with respect to ground,
whereas the output varies plus and minus about Vee (see Fig. 29.22b).
A second current mode switch using NPN transistors is shown in Fig. 29.22c.
This circuit requires an input signal which goes plus and minus with respect to Vee,
and gives an output which varies plus and minus with respect to ground, i.e., the
exact complement of the circuit of Fig. 29.22a. Thus, a logic chain would use
alternating types of current mode switches. It should be noted that current mode
switching can be accomplished using only one polarity of transistor if some means
is available to reestablish the proper d-c level between each successive stage oflogic.
In general, nonsaturating switches operate at a higher dissipation level than
saturating switches because of the higher collector-to-emitter voltage when the
switch is in the ON condition; thus, when choosing a transistor for a current-mode
switch, the maximum power dissipation becomes an important factor.
D-C Analysis. Figure 29.22a indicates that three constant-current generators
are required. To obtain such a generator, a large resistance can be placed in series
with a d-c voltage as shown in Fig. 29.23. If the external resistance Rx connected
between points A and B of Fig. 29.23 is much smaller than the resistor, R s , the
current from V will be essentially independent of the value of Rx. The circuit of
Fig. 29.22 can be closely approximated by the circuit shown in Fig. 29.24. From
400 Switching-mode Designs

Rs
r-----~~VV--------OA

v
Fig. 29.23. Constant current is achieved
by use of relatively large Rs compared
~----------------_OB to load Rx.

Fig. 29.24, with the transistor removed, the collector circuit current generators are

Ii =- Vee + Vi if Rl ~ RL (18)
Rl
Also, since either Ql or Q2 is conducting, R2 is connected at point C to provide
a low-impedance path to ground. Thus,

12 = V2 (19)
R2
Overall system design considerations usually determine the voltage swing required
and the impedance level; hence, Ii and RL will probably be predetermined. If
arbitrary supply voltages are used, 12 is determined by the values of (X and h while
resistors Rl and R2 can be obtained from Eqs. (18) and (19).
Consider the following design example for a current mode switch. The circuit
will be identical with that of Fig. 29.24. The collector voltage of Q2 is to be -5.5
volts when the input is negative and - 6.5 volts when the input is positive, i.e., a
voltage swing of 1.0 volt. Since the collector voltage is 6.0 + 0.5 volts, - Vee is
chosen to be -6 volts. Values of - Vi and V2 are chosen to be -45 and +45
volts, respectively. If RL is 50 ohms, then It is 10 rna. Assuming (X = 0.98,12 must
then be approximately 2 X Ii = 20 rna. Rl is calculated from Eq. (18) and is
3,900 ohms. R2 is calculated from Eq. (19) and is 2,200 ohms.
To show that the currents are substantially at their design values, the magnitude
of all currents will be calculated for the condition in which Ql is conducting and
Q2 is cut off. The circuits in Fig. 29.25a and b are simplified equivalents of the

V2
Fig. 29.24. Circuit approximating Fig. 29.22.
Logic Circuits 401

Vee -6v

(a) Equivalent of Fig. 29.24 (b) Equivalent of Fig. 29.24


active section passive section

Figure 29.25

circuit of Fig. 29.22 under these operating conditions. VBE and a are assumed to
be 0.2 volt and 0.98, respectively. From Fig. 29.25b,

(20)

If V(in) = 0.5 volt,


I - 45 - 0.2 + 0.5 - 20 5 (21)
2- 2200
, - .ma

The reverse current of the emitter-base junction of Q2 has been neglected since it
is much smaller than 12 • The collector current of Ql is approximately alE. Using
Fig. 29.25a and neglecting the reverse currents, the collector voltage of Ql is

v:Ol = aI 2
RIRL
+ V 1RL VeeR l
+ -=-....::..::.-=- (22)
Rl + RL Rl + RL Rl + RL

V1 R L
VOl = aI2R L + ~ + Vee (23)

Using the values given in Fig. 29.25a,


VOl ~ -5.58 11 ~ -10.1 rna h ~ 8.3 rna
The voltage at the collector of Q2 is
VI - Vee -
Ve2 = R R RL
1 + L
+ JI ee (24)

V 1R L
VC2=~+ Vee (25)

Using the values given in Fig. 29.25b,


Ve2 = -6.58 volts and 11 = 9.9 rna
402 Switching-mode Designs

These calculations show that the output voltage swing is 1.0 volt, which is suffi-
cient to drive an NPN current mode switch.
Transient Analysis. The analysis of switching times proceeds in the following
manner: the transistors together with the external elements are replaced by an
equivalent network, which is an approximate high-frequency equivalent circuit,
representing the current mode switch when the output current is a function of the
input current. This network is then modified to represent the transistor circuit
during the interval when an input signal has been applied, but before the output
current has begun to change.
Figure 29.26 shows typical input- and output-current waveforms for a transistor
switch. The delay, rise, storage, and fall times are shown.
The output-current rise time is calculated. Figure 29.27 shows the current mode
switch of Fig. 29.24 with the resistors and voltage sources in the collector circuit
replaced by their Thevenin equivalents, and the constant-current generator in the
emitter circuit neglected because of its large internal resistance. In the following
analysis, it is assumed that the internal impedance of both transistors is identical.
Looking to the right of A in Fig. 29.27, the input impedance of the grounded-
base transistor can be shown to be
(26)
where Ze is the emitter impedance, rb is the base resistance, and IX is short-circuit
current gain in the grounded-base configuration. The input impedance of Ql is

Z (in) Ze Z(ea:t)
= rb + -1--
- IX + -1--
- IX
(27)

where Z(ea:t) is the impedance in the emitter circuit of Ql, and is equal to Z(in) of
Eq. (26). Substitution of Eq. (26) into Eq. (27) for Z(ea:t) gives

Z(in) = 2 ~b + 1 :'e IX) (28)

Input
waveform

10%
~----------------------~----~------~

90%~-------~~~~~~1~~~
I
I
I

10%tt==~~====t========i:====J=====~ __
~ td --L trl ~
1 ~ td 2 1- tr2 ~
Fig. 29.26. Typical input and output waveforms for a transistor switch.
Logic Circuits 403

Fig. 29.27. Current mode switch of Fig. 29.24


using Thevenin equivalents. Fig. 29.28. Composite equivalent circuit.

A composite equivalent circuit can be drawn as in Fig. 29.28. The base current is

.
lb =- - = 2[rb + E(in)
E(in)

Z(in)
-::-:----=~':-:--__:_:_
Ze/(l - a)]
(29)

That portion of the circuit to the right of BB' can be presented as shown in Fig.
29.29. Because RL is small compared to the reactance of Cc/(l - a), even at high
frequencies the current through RL is
. iba
10 =-- (30)
I-a
where ib is the base current. Substitution of Eq. (29) into Eq. (30) yields

.
10 = E(in)a
----~-"----,----- (31)
2[rb + Z/(l - a)](l - a)
The parameter a is frequency-dependent and can be approximated by
ao
a = -:----=-;:-:-;;- (32)
1 + jf/ja
where a o = low-frequency small-signal current gain
j = frequency at which a is to be calculated
ja = alpha cutoff frequency
The impedance Ze is also a function of frequency and is, to a close approximation,
Z _ re (33)
e - 1 + jj/ja

Fig. 29.29. Portion of


-ibCX
I-cx
t
Fig. 29.28 equivalent cir-
cuit to right of BB' can
be represented thus.
404 Switching-mode Designs

logJioJ

Fig. 29.30. Load current vs. frequency,


for equivalent circuit of Fig. 29.29.

where re is the emitter junction resistance. Substitution of Eqs. (32) and (33) into
Eq. (31) gives, after rearrangement of terms,
. (XoE(in)
10 = -::---:-:----:---''---'=::-:'--""""7"----:;:-;"7"
2rb (1 - (Xo) + 2re + j 2rb//f",
(34)

Figure 29.30 shows a plot of io vs. frequency. The current gain of the circuit is
down 3 db at the frequency /c. This frequency can be determined by equating the
real and imaginary terms of the denominator ofEq. (34) and solving for frequency.
Thus,
f=/C =fa [(1 - (Xo) + ~:J (35)

The following measurements were made on a Texas Instruments 2N1305 transis-


tor: fa = 6.6 mc, (xo = 0.994, and rb = 105 ohms. From the relation
_ kT
re = - -
qIE
where k = Boltzmann's constant
T = absolute temperature
q = electronic charge
IE = emitter current
re is calculated to be 2.6 ohms, using an average IE of 10 rna. Substitution of these
values into Eq. (35) gives /c = 0.204 mc.
From Eq. (34), the d-c or maximum value of io is calculated to be 77 rna
for E(in) = 0.5 volt. The RL circuit of Fig. 29.31 can be selected so that its fre-
quency response is the same as that shown in Fig. 29.30. If the maximum value
of input current to this circuit is adjusted to be 77 rna, an expression for current
through the RL circuit may be written:
io = 77(1 - e-tlT ) (36)

Fig. 29.31. RL circuit to give curve


shown in Fig. 29.30.
Logic Circuits 405

io, rna
.,,' ... ------
,/'

,
,, ,
/

,
Fig. 29.32. Curve resulting from Eq. (36).

where 'T = L/R and is the circuit time constant. The impedance of this circuit is
Z = R + jwL (37)
and to have a frequency cutoff at /c = 0.204 mc, the real and imaginary terms of
Eq. (37) must be equal at this frequency. Solving for L/ R under this condition
yields
L
R
= 'T = 1w = 7.81 X 10- 7 sec

The output-current rise time of the current mode switch may now be calculated.
Although the collector current rises toward 77 ma, it is limited to a maximum value
of 20 ma because of the constant-current generator in the emitter circuit. Equa-
tion (36) gives the magnitude of io after the output current has begun to flow. This
equation is used to calculate t1 and t2 (Fig. 29.32), which correspond to collector
currents of 2 and 18 ma, respectively. These times are found to be t1 = 20.8
ill/Lsec and t2 = 208 m/Lsec. Thus, tr = t2 - t1 = 187 m/Lsec.
The current mode switch of Fig. 29.24 was breadboarded, using the resistor and
voltage values selected in the example. A square-wave voltage, with a rise time
of 20 m/Lsec, varying above and below zero volts by 0.5 volt, was applied to the
input of Q1. With Q1 and Q2 having the parameters given for the 2N1305 tran-
sistor, the rise time of the output current was measured to be 180 m/Lsec.
Delay time is divided into two parts. Figure 29.33 shows the input circuit of a
transistor when it is biased in the reverse direction. C TE is a depletion-layer capaci-
tance between the emitter and base. When the transistor is reverse-biased, this
capacitor is charged to a reverse polarity. Sufficient charge must be supplied by
thc input current to discharge the capacitor. The time required to discharge this
capacitor, after the input has risen to its 10% value, is the first portion of the delay
time.

Fig. 29.33. Input circuit


of transistor when biased
in reverse direction.
406 Switching-mode Designs

+
-3v
3V
l C
0.001
p.f
Fig. 29.34. Complemen-
tary emitter-follower cir-
cuit.

The remaining portion of the delay time is the time required for the output cur-
rent to change from its initial value to 10% of its final value. This time has
previously been calculated at t1 and is 20.8 m/Lsec. The measured delay time of
the circuit of Fig. 29.24 was 40 m/Lsec.
The second delay time td2 and fall time t1"2 are calculated, using the same equiva-
lent circuit of Fig. 29.28. For this reason, td2 and tr2 have the same values as td1
and tr1, respectively.
Complementary Emitter-Follower. A complementary emitter-follower is
shown in Fig. 29.34. Q1 and Q2 are PNP and NPN transistors, respectively, and
have nearly identical electrical characteristics. The advantage of a complementary
emitter-follower over the conventional type can be seen with the aid of Fig. 29.35.
This shows an emitter-follower driving a capacitive load.
A negative input to the base of Q1 causes conduction, and C is charged with the
polarity as shown. The charging path of C is through the forward resistance of
the base-emitter diode of Q1. This resistance is of the order of only a few ohms,
and C will charge rapidly. Removal of the negative drive at the base causes Ql
to stop conducting, and C must then discharge through R. If R is larger than the
resistance in the charging path, the output-voltage waveform of Q2 will have a
longer fall time than rise time.
Figure 29.36 shows how the output waveform is distorted. To reduce the fall
time of the output waveform, a circuit is required which will present a low-
impedance path for the discharge of C. The complementary emitter-follower of
Fig. 29.34 provides this low-impedance path. Q1 of Fig. 29.34 is the same as in
Fig. 29.35.

c
Fig. 29.35. Emitter-follower driving
a capacitive load.
Logic Circuits 407

o--u o~
Input Output
Fig. 29.36. Waveforms for circuit of Fig. 29.35. Note distortion in output waveform.

A negative input at the base connection causes Ql to conduct, and C is charged


to a voltage which is almost equal to the input voltage. When the input goes
positive, the emitter of Ql is negative with respect to its base. Q2 conducts, and
C discharges through the base-emitter diode of Q2. This reduces the fall time of
the output waveform and gives a symmetrical waveshape.
The biasing arrangement for the complementary emitter-follower of Fig. 29.34
is easily determined. For the output-voltage swing to have approximately the
same magnitude as the input-voltage swing, the collector voltages for the PNP and
NPN transistors will be chosen as -3 and +3 volts, respectively.
Transient Analysis. The complementary emitter-follower shown in Fig. 29.34
can be analyzed to ascertain the transient response in the following manner. If it
is assumed that both NPN and PNP units have identical characteristics, then only
one of the two transistors need be considered. When an ordinary emitter-follower
is changed from the ON to the OFF condition, any capacitive load must discharge
through the resistance of the biasing network, and hence produce a relatively long
transition time. As an example, the circuit of Fig. 29.34 has a rise time of 80
mp.sec and a fall time of 2.5 p.sec when the NPN transistor is removed. If the NPN
unit is included, the fall time is the same as the rise time.
It is obvious that one of the transistors is responsible for the rise and the other
for the fall; hence, the transient analysis will consider a single transistor driving
the load as shown in Fig. 29.35. If the equivalent circuit of Fig. 29.37 is used, cur-
rent i2 can be written as
(38)

and the voltage gain is

(39)

Since Zc = l/jwCc at high frequencies and in the frequency range of interest,


wrbCc ~ 1

+ +
rb= base resistance
Ze= emitter junction
impedance
Zc = collector junction
impedance
ZL=load impedance

Fig. 29.37. Equivalent circuit for transient analysis.


408 Switching-mode Designs

where w is radian frequency. Equation (39) may now be written as


eo ~L
(40)
e(in) ~e + rb(1 - a) + ~L

The terms ofEq. (40) as a function of frequency are as follows:


~ _ re ao
+ p/w", a = -:----:-- (41)
e- I 1 + p/w"
where re --- kT/qIE
P = complex frequency
w" = alpha cutoff frequency expressed in radians
RL = load resistance
CL = load capacitance
a o = low-frequency value of a
Substituting Eq. (41) into Eq. (40) yields
eo RL
e(in) RL + re + rb(1 - ao)
x (l + p/w,,)
I + {RLCdre + rb(1 - a o)] + (RL + rb)/w",}P + rbRLCLp2
RL + re + rb(1 - a o) w,,[RL + re + rb(1 - a o)]
(42)
If RL ~ re + rb(1 -ao), Eq. (42) can be written
~ (l + p/w,,) (43)
e(in) - I + {[re + rb(1 - ao)]CL + (RL + rb)/RLw,,}p + rb CLp2/w"
Complementary transistors having the following characteristics were used in the
circuit of Fig. 29.34: w" = 2 X 6 X 106 radians/sec; a o = 0.99; rb = 60 ohms;
re = 10 ohms.
These transistor parameters were measured at an average bias condition of
RL = 1,000 ohms, CL = 0.001 pi.
By using the measured parameters given above, the rise time can be calculated
as 75 mJ.tsec. The value determined experimentally was 80 mJ.tsec, which shows
good agreement with the calculated value.
30
Transistorized Timers

Timing can be accomplished by a variety of methods-mechanical, thermal,


chemical, electronic, or a combination of these. Regardless of the method, a timer
depends upon a time base either generated internally or applied from an external
source. The spring-driven clock, for example, generates its own time base, whereas
the ordinary electric clock uses an external time base-the period of the a-c line
voltage. The first consideration in the design of transistorized timers is the gen-
eration of a suitable time base.

30.1. RC TIME-BASE GENERATORS

Analysis of a Theoretical Circuit. The time base for a simple low-cost circuit
may be established by the use of a resistor, a capacitor, and a sensing network as
shown in Fig. 30.1. Ignoring the loading of the sensing network, the time, t, for
capacitor C to charge to voltage V G in the simple timing circuit is

t = RC In VB V. (1)
VB - G

The accuracy of a time base derived from the circuit is dependent on the sta-
bility of the RC product, of VB, and of the sensing network. The change in the
time base produced by an incremental change in the RC product with all other
variables held constant is
VB
flt = flRC In VB- V.
G
(2)

0-----,
I
Voltage
senSing
network

0------1
Fig. 30.1. Theoretical RC timing circuit.

409
410 Switching-mode Designs

where I:lt = incremental change in t, and I:lRC = incremental change in the RC


product.
The equation shows that a percentage change in the RC product will produce an
equal percentage change in the time base.
The error in the time base produced by an incremental change in the source
voltage VB while all other parameters are held constant is

I:lt = -I:lVB VcRC (3)


VB(VB - Ve)
where I:lVB = incremental change in VB. The error in the time base produced by
an incremental change in Ve with all other parameters held constant is

I:lt = I:lVe RC (4)


VB - Ve
where I:lVe = incremental change in capacitor voltage. Mathematically, the per-
centage error resulting from an incremental change in Ve is a minimum when
Ve = 63% of VB.
The accuracy of a practical RC timing circuit will depend on well-regulated
source voltages, small tolerances on resistors and capacitors or proper compensa-
tion for changes in these components, and a stable sensing circuit.
Analysis of a Transistorized Circuit. A practical timing circuit is shown in
Fig. 30.2. The sensing circuit is designed to supply current to RL when
Ve = Vz + VBE(on) (5)
where Ve = voltage across the capacitor
Vz = zener voltage of Dl
VBE(on) = base-emitter ON voltage of transistor Q1
The time t' for the RC circuit to charge to the voltage which operates Q1 is

t' = R'Cln VB - leBoR' (6)


VB - leBoR' - Vz - VBE(on)

where R' = RRs V( -


B-
V, Rs
BR+Rs
R +Rs
and leBO = collector-base reverse current of Q1 with the emitter open-circuited,
and VBE(on) = base-emitter ON voltage of Q1. All variables in Eq. (6) are depend-
ent on temperature; therefore, an exact equation for t' is not practical because of
its complexity. A better approach to the problem is to design the circuit to be as
stable as possible with existing components, then compensate for variations in
specific parameters over the operating temperature range.
In this circuit, as in all circuits where a transistor is to be operated as a saturated
switch, two cases must be considered: the ON case and the OFF case. The circuit
should be so designed that the transistor will saturate at the lowest operating tem-
perature, and to ensure that the transistor will be held OFF at the highest
temperature.
Transistorized Timers 411
r---------,
I I
I I
I
Rl I
I
R I
I
I
I
I
I
I
I
L- _ _ _ _ _ _ _ _ ..J
I
Sensing circuit

Fig. 30.2. Transistorized RC timing circuit.

A technique which will meet these requirements requires a d-c analysis of the
equivalent circuit for both the ON and the OFF states of the transistor. The fol-
lowing considerations should be made in the design of the sensing network.
For the ON case, the collector current of Ql is
Ic = VB - VCE(sat) - Vz
(7)
RL

where VCE(sat) = collector-emitter saturation voltage. The maximum base current


required to saturate the device is
Ic VB - VCE(sat) - Vz
I B(max) = --=h--=---
FE(min) hFE(min.,RL
(8)

where hFE(min) = minimum current gain of the device. The available base current is
IB = VBRs - (Vz + VBE(on»(R + Rs)
(9)
RRs
Thus, hFE(min) must be chosen so that
IB > IB(max) (10)

Collector power dissipation during the ON time is


P C(on) = I CV CE(sat) (11)

This equation may be used to determine the collector dissipation rating when
TON ~ (hcCJ_c ~ Tsw (12)
where TON = ON time
Tsw = time to switch the transistor from OFF to ON states
OJ_cCJ_C = junction thermal time constant

F or large values of Rand C, the time required to switch the transistor may be long
412 Switching-mode Designs

compared to the thermal time constant of the transistor. Thus, the collector dissi-
pation rating for this case should be determined from the equation

(13)

During the OFF time, the collector-emitter and emitter-base voltage-breakdown


ratings must not be exceeded. The collector reverse current lOBO should be small
compared to the capacitor-charging current.
The zener diode Dl should be selected with the following characteristics:
1. Voltage rating large compared to VBE(on)'
2. Low dynamic impedance.
3. Adequate power rating when Ql is saturated.
4. Temperature coefficient which cancels that of the base-emitter junction
(approximately 2 mv/CO).
If the timer circuit is to be operated over a wide temperature range, the tem-
perature coefficients of all components should be considered. As noted in Eq. (6),
components in the RC network will affect the stability of the time base. Resistor
R has a temperature coefficient which causes the time base to vary with tempera-
ture. Fixed-composition resistors change with voltage as well as with temperature;
the total change can be as much as -+ 35 % from 25 to 105 C. Some 1% carbon
0

resistors change 5% for a 100 CO temperature change.


Both capacitance and shunt resistance of capacitor C must be considered. For
temperatures approaching 200°C, Teflon* capacitors at present are the most suita-
ble. Since the shunt resistance is very high (1 X 109 megohm-pi product), these
capacitors allow a wider range of charging currents for varying time delays. The
Teflon temperature curve shows a negative coefficient of 100 ppm/Co. A typical
Mylar* capacitor has a high shunt resistance (6 X 104 megohm-p.f product), and
is operational up to 125°C. The capacitance-vs.-temperature curve flattens near
25°C, then increases rapidly with temperature above 65°C.
Very often in analyzing a transistorized timer, the sensing network is automat-
ically considered to be the major cause of instability. The above considerations,
however, indicate that the major source of error may often be attributed to other
factors; however, parameter variations of the transistor in the sensing network
should not be ignored when considering the factors which might affect the stability
of the time base.
The circuit of Fig. 30.2 may be temperature-compensated if desired. To obtain
the required accuracy, it may be necessary to compensate for both the change in
the RC product and the change in lOBO. As a rule, the capacitor-charging current
is made much larger than the leakage current lOBO, making the effect of lOBO
negligible. Opposite temperature coefficients of Vz and VBE(on) may eliminate the
need for compensation in the emitter of Q1. However, if the turn-on voltage
Vz + VBE(on) varies with temperature, compensation may be effected by using a
thermistor or sensistort resistor.
* Trademark of Du Pont.
t Trademark of Texas Instruments.
Transistorized Timers 413

The temperature coefficient of each component in the timing circuit has a defi-
nite thermal time constant. Even though the circuit may be perfectly compen-
sated for gradual temperature changes, the time base may vary with fast changes
in temperature. Good heat-sinking techniques will minimize this problem.

30.2. DESIGN EXAMPLES

One-shot Multivibrator Timer. Considering economy, simplicity, and ease of


assembly, a simple two-transistor monos table multivibrator makes a very good
timer. For example, the timer circuit in Fig. 30.3, having an accuracy of -+-10%
from -20 to +60°C, is designed to switch a 4-ma load with a 12-volt supply.
The output is - 12 volts for periods of 1 to 5 sec, and is adjustable between these
values. The circuit operates as follows: When power is applied, Ql is normally
OFF and Q2 normally ON. Cl will charge with polarity as shown. Operating
PB l causes Ql to conduct. Q2 turns off since Dl is reverse-biased, owing to the
charge on C1. Base drive for Ql now flows through R4 from the collector of Q2,
which is at approximately - 12 volts. The output voltage appearing at the col-
lector of Q2 remains until the charge on Cl reverses, owing to the charging path
through R2 and R 3 • Q2 will turn ON, removing the base drive from Qb and the
circuit will remain in this state until PBl is operated again.
Free-running, Dual-output Timer. The circuit of Fig. 30.4 has dual outputs,
each of which may be controlled separately. The operation may be described as

-12v

Output

Ql
2N1305
R5 Q2
12 K 2N1305

Note: All resistors are ±5%. % watt

Fig. 30.3. One-shot multivibrator timer.


414 Switching-mode Designs

+ 15v

Note: (1) All resistors are ± 10%, 1/~ watt


unless otherwise specified
(2) SW1 is shown in OFF position
(3) RLl or RL2 can be replaced with a 500 n
relay coil and IN2069 diode in parallel
Fig. 30.4. Free-running, dual-output timer.

follows: When Vee is applied with SW1 (emitter leg) open, C1 will charge, raising
the potential at A above the potential at B, causing conduction in Q3 and Q4.
This will tum Ql ON when SW1 is closed. Closing SW1 opens the direct V cc sup-
ply to C 1 • Ql now conducts, dropping the potential at point C to nearly ground
level, and removes the charging source from C 1 . When Ql turns ON, Q2 turns
OFF, raising the potential of point D from nearly ground to approximately Vee.
Hence C2 commences to charge, and when point E rises to a greater potential than
point F, transistors Q5 and Q6 conduct. This turns Q2 ON and Ql OFF, and
commences the charging cycle on C1 . If SW1 is opened (emitter leg opened and
V cc supply to C1 closed), C1 will charge almost instantaneously, enabling the circuit
to start a new cycle. The OFF time of Ql and Q2 may be varied by adjusting Rl and
R 2 , respectively.
A temperature check of this circuit showed an error of 3% over a range of 25 to
55 C, and a lO% error from - 20 to + 25 C. Most of this error was due to the
0 0

difference in the firing point of the PNP-NPN "hook" combination. This type of
repeating timer will give excellent results with a stable power-supply voltage and a
constant ambient temperature. A typical accuracy of 0.1 % may be expected with
these conditions.
Bootstrap Timer. A bootstrap timer is shown in Fig. 30.5. Transistors Ql and
Q2 comprise a one-shot multivibrator with Ql normally ON and Q2 normally OFF.
Transistorized Timers 415

C1 will charge through Rl and Dl toward 24 volts. The voltage on C1 will be


"followed" by the Darlington circuit, composed of Q3 and Q4. The voltage across
the 4.7-kilohm resistor in the emitter of Q4 will approximate that of C1 and change
at the same rate. This change will be coupled to the junction of Rl and Dl through
a 10-[1'[ capacitor. This type of feedback allows Rl and C1 to see almost the same
charging voltage during the timing cycle. The result is a nearly linear output-
voltage rise across the emitter resistor of Q4. The length of the time cycle is set
by controlling the emitter voltage of Q5. This voltage must always be some value
less than Vee. When the sawtooth voltage applied to the base of Q5 exceeds the
emitter voltage, Q5 will saturate. A negative pulse will be generated by the network
connected to the collector of Q5, and will be applied to the base of Ql. When Ql
turns OFF, Q2 will turn ON and discharge C1 . When the one-shot multivibrator
returns to its original stage, the timing cycle will begin again.
Overall accuracy of this circuit, from - 50 to + 50° C, is 3%. Counter circuits to
give longer time cycles can easily be utilized for production-line control, acid-bath
timers, photographic timers, and many other monotonous jobs which are repeated
sequentially day after day.

+24v

Sensistor® resistor
680n

Output

+20V
A
o h---l

Note: (1) All resistors are ± 5%, V2 watt unless otherwise specified
(2) C 1 is a Teflon® dielectric capacitor
(3) The temperature coefficient of Rl is ± 2 ppm/"C
(4) R2 sets the value of t
(5) All diodes IN2069
Fig. 30.5. Bootstrap timer.
416 Switching-mode Designs

Sawtooth
outPut~
J r------0
Q

~~===I=------I------I~'~
Note: Blocks 1, 2, 3, and 4
are voltage sensing
amplifiers that control
loads or other timers

Fig. 30.6. Sequential bootstrap timer.

Sequential Timer. The block diagram of a sequential bootstrap timer is shown


in Fig. 30.6. Four sequential events can be set to occur in order until all four are
completed. All four will turn OFF together, and the cycle will be repeated. The
order in which each event will occur is determined by the voltage level of the saw-
tooth waveform. Blocks 1,2,3, and 4 may also represent timers whose outputs
will perform functions of different time lengths, a feature often required for repeat-
job operations.
Decade Timer. Figure 30.7 shows a timer using digital methods, with a selection
capability of 0.1 to 99.9 sec in O.l-sec increments. This timer makes use of the 60-cps
line frequency for a time base. The three decade counters, A, B, and C, have selec-
tive outputs which provide for operation of a relay or other devices when the three
decades reach the time preset by the three switches, SW2 , SW3 , and SW4 • The
principal advantage of this timer over other types is that the accuracy depends on
the stability of the 60-cps line frequency instead of on the circuit parameters.
An oven-controlled tuning-fork oscillator, running at 60 cps, could supply the
input to this type of counter and afford the same accuracy. Addition of more decade
counters will provide extended time ranges with the same accuracy throughout the
entire range.
SW1
60 cps / o-------J Pulse s~aping I ' .. I 10 cps
amplifier

Note: (1) The zero position of


SW2 , SWa and SW4
corresponds to a
fixed bias voltage
(2) The switches are shown for
a setting of 76.3 sec

SWa 0·9.0 sec

---
Output

"'"
" SW4 0·90 sec

Fig. 30.7. Decade timer.


31
High-level Switching

Because of their efficiency and reliability, transistor switches are ideally suited
to the manipulation and control of large amounts of power.

31.1. POWER DISSIPATION

In a practical switching circuit, the average power dissipated in the transistor is


much less than the peak dissipation. Consequently, relatively large currents and
voltages can be handled without exceeding the rated dissipation of the transistor.
However, the voltages should be limited to a safe value below the breakdown
voltage, and the current should stay within the maximum current specified for the
transistor. At all times, the average power dissipation must be below the rated
dissipation at the maximum ambient temperature.
An expression for the average power dissipated in a transistor switch can be
derived from the idealized current and voltage waveforms of Fig. 31.1. The
assumptions made are:
1. Power dissipated in the base is negligible.
2. Rise time and fall time are equa1.
3. Storage time and delay times are negligible; i.e., the ON and OFF times
are equal.
Even using these simplifying assumptions, the resulting equation is helpful in
illustrating which of the transistor electrical quantities are most important for
power-dissipation considerations.

P (average dissipation) =ljTON


r 0
VcE(sat)Ipdt 1
+ TON + Tsw
TON
(Ip - Ip /
SW
) (Vp /
SW
)dt

+ f7 - Tsw

TON+Tsw
Vplco dt + f r
r-Tsw
(vp - Vp +-) +-
SW
(Ip
SW
dt) (1)

(2)

ON OFF Switching

418
High-level Switching 419

c:
o
:;::;
'"
Q.
"u;
/ Peak dissipation
"~
"0
'-
Q)
~Average

Fig. 31. 1. Power dissi- ~ L dissipation

pation.

This equation illustrates the importance of fast switching and low saturation
voltage for efficient switching.

31.2. LOAD-LINE ANALYSIS

An important consideration in achieving maximum reliability in a high-level


switch is the transistor's load line. The load line, or VI curve as it is sometimes
called, is the locus of the transistor's operating points. A simple method of
observing a load line is shown in Fig. 31.2. The vertical plates of an oscilloscope
are connected across a small resistor inserted in the collector circuit. It should be
noninductive, and its resistance should be much smaller than any other impedance
in series with the transistor. The horizontal plates are connected to the collector
and emitter terminals. The resulting trace shows the current and voltage that the
transistor is handling as it functions in the circuit. The peak power dissipated by
the transistor during switching can be determined by taking the peak product of
the currents and voltages which occur simultaneously. If a determination of the
average power dissipated is desired, the necessary time relationship can be obtained
by modulating the trace with a time-mark generator.
In many high-level switching applications the load is inductive or transformer-
coupled, and, consequently, problems inherent in inductive switching are en-
420 Switching-mode Designs

+ Vee

Current sensing To vertical plates


resistor of oscilloscope

To horizontal plates
of oscilloscope

Fig. 31.2. Measurement


of load line.

countered. A load line for a single-ended switch with an inductive load is shown
in Fig. 31.3. The voltage induced in the inductance at tum-off adds to the supply
voltage to form a collector-to-emitter voltage spike. This voltage could exceed the
applicable collector-to-emitter voltage breakdown of the transistor, BVCEX•
Another equally-important possibility is that the transistor would experience a
secondary voltage breakdown, because of the large current and voltage appearing
simultaneously during tum-off. That is, the maximum allowable collector-to-
emitter voltage is determined by the load line as well as by the rated BVCEX• From
voltage considerations alone, the maximum collector-emitter voltage could safely
approach BVOEX• But consideration of the load line (i.e., simultaneous current and
voltage variations) often reveals that the maximum voltage must be restricted to
something less than BVCEX, especially if the load is inductive. Limiting the maxi-
mum collector-to-emitter voltage to the BVOES rating (rather than to BVCEX) often
affords a safety factor for resistive and slightly inductive loads. However, even
this may not be conservative enough for a high-level switching circuit with an
inductive load line similar to that shown in Fig. 31.3. In every instance, it is

-
Load line

Turn OFF)

o Vee
Collector to emitter voltage

Fig. 31.3. Switch with inductive load.


High-level Switching 421

...
<:
~
:::l
- Load line

Turn OFF
J
u
5
tl
~
a
() -

o Vee
Collector to emitter voltage

Fig. 31.4. Switch with inductive load shunted by a diode.

advisable to switch the transistor operating point through the region of high dissi-
pation as rapidly as possible.
The most common method of protecting the transistor from the energy stored in
the inductance of an inductively loaded single-ended switch is shown in Fig. 31.4.
The diode limits the voltage across the transistor during turn-off to the supply
voltage.
Further improvement in shaping of the load line can be achieved in many
instances by shunting the diode with a small capacitor, as shown in Fig. 31.5. The
capacitor voltage opposes the supply voltage during turn-off, thus allowing the
current through the transistor to drop without a sudden voltage rise across the
transistor. For some designs, the diode may become unnecessary.
Double-ended (push-pull) switches with inductive loads can also have their load
lines shaped. A small capacitor connected from collector to collector, as shown in
Fig. 31.6, is usually very effective in suppressing collector-to-emitter voltage spikes.

o Vee
Collector to emitter voltage

Fig. 31.5. Switch with inductive load shunted by a diode and capacitor.
422 Switching-mode Designs

-Vee

Fig. 31.6. Capacitor spike suppression. Fig. 31.7. Breakdown-diode spike sup-
pression.

If the voltage spikes are exceptionally severe or fast switching time is of prime
importance, it is best to replace the capacitor with a double-anode breakdown diode
as shown in Fig. 31.7.
The sections following are representative of high-level switching applications.

BIBLIOGRAPHY

Newell, A. F.: An Introduction to the Use of Transistors in Inductive Circuits, Mullard Tech.
Communs., vol. 4, no. 35, pp. 157-160, November, 1958.
32
Light Flashers

Transistor-operated flashers are now replacing flare pots and mechanically


operated flashers for reasons of reliability, safety, compactness, and efficiency.
Figure 32.1 shows a multivibrator flasher which drives two lamps alternately.
Such a flasher has been used in aircraft applications. The design of the astable
multivibrator is discussed in Sec. 28.2.
The construction barricade flasher is the most common flasher application at
present. Some transistorized flashers run as long as 60 days on a single battery,
whereas a flare pot must be refilled every few days. The barricade flasher must be
inexpensive and efficient, usually driving a single lamp at 1 cps at a 15% duty cycle.
A typical design of this type is shown in Fig. 32.2. To explain its operation, assume
that the switch Sl has just closed. Base current then flows through R2 into Ql.
The collector current of Ql is the base current of Q2. The resulting collector
current in Q2 divides between the lamp and the feedback path (Rl C1 ). The feed-
back current adds to the base current of Ql, and the resulting regeneration saturates
Q2, causing the lamp to burn at full brilliance. The feedback current decays
exponentially, owing to the Rl C1 time constant. The flasher begins to turn offwhen
this current decays to a value that will not sustain saturation of Q2. As Q2 comes
out of saturation, the voltage change is fed back to the base of Ql through the (R1,C1)
path. Regeneration occurs again, causing both transistors to turn off rapidly.

Fig. 32.1. Astable multivibrator


light flasher.

423
424 Switching-mode Designs

r
-=- Vee

Fig. 32.2. Low-current flasher.

The charge on C1 is such that the base of Ql is made negative. C1 begins to charge
toward Vee through Rl and R 2 • When the base voltage of Ql reaches VBE(on)l, Ql
begins to turn ON, starting a new cycle.
The base current IBl in Ql comprises two components: a static component, 10 ,
and a dynamic component, ia, as shown in Fig. 32.3. 10 and ia are given by

(I)

and (2)

Therefore,
(3)

The operation of this flasher is very dependent upon the hFE of both Ql and Q2.
To ensure starting and to prevent lockup in the ON state, both transistors should
be in the active region when the feedback path (R1,C1) is open, and the closed-loop
gain must be greater than unity. An open-loop lamp current between 20 and 80%
of the full-load lamp current, h, has been found to be satisfactory for a typica15-volt
90-ma flasher lamp such as the GE 1850. Then the static base current in Ql must be

10 > O.2h (4)


- hFElhFE2

and (5)

The loop gain is

AL - hFElhFE2RL >I (6)


hiel + Rl + RL

where RL = lamp resistance measured at 0.2h, and hiel = input resistance of Ql


measured with iBl = 10 . The flasher turns OFF when iBl decays to a value (1(off)
which will not sustain saturation of Q2, that is, when
Light Flashers 425

10
a t(on)

Fig. 32.3. Base current in Ql.

h
I(of{) = h h
FEl FE2
(7)

Since (8)

Vee
then tON~ RlClln R (I I ) (9)
1 (of{) - 0

Assuming R2 ~ R l , the OFF time is


tOFF ~ 0.7R 2 Cl (10)

This condition is illustrated in Fig. 32.3. When t = tON, iBl has decayed to l(of{)'
varies with hFEl and h FE2 . 1Bl should decay to l(of{) within two time constants
l(of{)

for reasonable ON time stability.


R3 is chosen small enough to allow Q2 to saturate when Ql is saturated,

R3 < (Vee - VBE(on)2 - V eE(sat)1)h{e (11)


h

r~6v
Note: (1) QI - 2N1302 inverted
configuration; Q2 -2N1374
(2) hFEI x hFE2 selected to be
between 500 and 1,000
(3) Typical ON time 0.2 sec
(4) Typical OFF time 0.8 sec

Fig. 32.4. Low-current flasher.


426 Switching-mode Designs

and R3 must be large enough to prevent excessive collector currents in Ql and Q2.
Figure 32.4 illustrates a typical flasher design. Ql is operated in the inverted
configuration for lower h pE and lower leakage current. Inverted h pE of the 2N1302
can be expected to be between 5 and 20. Normal hpE of the 2N1374 is specified
to be between 50 and 150. Ql and Q2 must be selected such that the hpElhpE2
product satisfies Eqs. (4) to (6). An hpElhpE2 product between 500 and 1,000 works
well in this flasher.
The switch 8 1 can be replaced with a solar-cell switch to turn off the flasher
automatically in daytime; such an arrangement will roughly double battery life in
unattended locations.
33
Blocking Oscillators

The blocking oscillator is a common type of relaxation oscillator. There are two
major modes of operation: the astable or free-running mode, and the monostable
or triggered mode. In computer circuitry, the blocking oscillator is often used as
a pulse generator.

33.1. COMMON EMITTER

The circuit shown in Fig. 33.1 is a basic blocking oscillator in the common-
emitter configuration. Upon application of a negative trigger pulse to the base,
the collector current will start to rise. The collector voltage will rise toward
V CE(sat), and a pulse will be coupled to the feedback winding. Since the feedback
voltage is 180 out of phase with the primary voltage, a negative-going pulse will
0

be coupled to the base, thereby turning the transistor ON and driving it into
saturation. When the current in the transformer builds up to the point where the
transistor cannot remain saturated, the feedback voltage will decrease, and the
transistor will turn OFF. The back voltage that will be present at the collector when
the field of the primary winding starts to collapse may exceed the BVCBO rating of
the transistor; consequently, a diode is connected across the primary winding to
prevent voltage breakdown of the transistor.

Output

Vee
Fig. 33.1. Common-emitter triggered blocking oscillator.
427
428 Switching-mode Designs

Ignoring the load current and the current through R 1 , the collector and base
currents as a function of time are given by the following equations:

(1)

and (2)

where r = rl + rz
rl = d-c resistance of the transformer primary plus Res (collector saturation
resistance)
r2 = re (saturated emitter resistance) plus RE (external emitter resistance)
rb = base resistance
n = Nl/N2 = turns ratio
Lm = magnetizing inductance
When the collector current is approximately hpEiB , the transistor will turn OFF.
Using Eqs. (1) and (2), the pulse width, t w , is

tw - Lm In 1 - r/ n2rb + (h pEr2/ rb) (1 + r/ nr2) (3)


r 1 + hpEr2/rb

tw - Lm In
r
(1 + ~)
nr2
(4)

Thus, the effect of circuit parameters on pulse width can easily be determined from
Eq. (4). Conversely, the magnetizing inductance necessary for a given pulse width
can easily be computed. For example, assume
tw = 1 Ilsec
rl = 2 ohms
rz = 2.7 ohms
n=¥I
Therefore,
L (1 X 10-6)(4.7) = 15.7 h
m = In [1 + 4.7/(5)(2.7)] Il

The maximum collector current can be determined by substituting Eq. (3) into
Eq. (1), thus:

(5)

Assuming hpE is large,


Vee (6)
i e(ma:c) = ---=--='-----
nr2 + r
Blocking Oscillators 429

33.2. COMMON BASE

The saturated common-base-type blocking oscillator is similar in operation to


the saturated common-emitter type; therefore, the following discussion covers the
common-base nonsaturating-type blocking oscillator. This is often used when fast
response is desired.
Figure 33.2 illustrates the common-base nonsaturating blocking oscillator.
When the transistor is triggered by a negative pulse, current will start to rise in
the collector. The pulse coupled to the emitter will be in phase with the pulse at
the collector. The negative pulse fed back to the emitter will aid the turn-on cur-
rent, causing the transistor to be driven toward VCE(sat). However, the collector
voltage will not reach VCE(sat) but will be clamped to a voltage level, VI, which is
above VCE(sat)' thereby achieving nonsaturated operation of the blocking oscillator.
There will be a constant voltage, V2 , across the magnetizing inductance, Lm.
Since the current through the inductance builds up linearly, the current through
Dl will decrease at a linear rate. When the current through the diode ceases, the
voltage V2 will start to decrease, owing to the rising current required by Lm. Dl
will become reverse-biased, and the collector voltage will start to rise, causing the
transistor to start turning OFF.
The magnetizing inductance Lm will discharge through D 2 • The capacitor, be-
ing charged during the pulse, will cause the emitter-base junction to be reverse-
biased. The transistor will not conduct until a new triggering pulse is applied.
Immediately after the transistor has turned ON, V2 is present across the primary
of the transformer, and very little current flows through the magnetizing induct-
ance. The emitter current is
. -V2
le = --,:---,.-:=-----,--.,,- (7)
n[re + rb(l - ao)]
The current through the primary of the transformer is

II = aoie + iDI = - n~2 [


re + rb (11 - ao
) + _l_J
RL
(8)

From Eqs. (7) and (8),


(9)

Input

Fig. 33.2. Common-base nonsaturating triggered blocking oscillator.


430 Switching-mode Designs

O~----I~-----1---+~ Pulse transformer:


Aladdin 90-722
Trigger
Nl:N2:N3=5:1:1
input

Fig. 33.3. Common-base blocking oscillator.

40
.el
"0 I\.
> 30
as
IlO
.l9
"0 20 1 I
>
...
....0<.> \ )
-- ---
~ 10
I--""'"
"0
u
\ ~

....
IF>

"0
>
0

-2
, - .
/
cV
IlO /
....--
---
.l9 -4 .".
0
>
....
:§ -6
·E
\ 1-
V
LLI

-8

.el
0
>
oj
IlO
....
ro
0
>
"0
ro
0
6

2
I
.-
-r-- ---- .......

i\
..J

o
J
0.2 0.4 0.6 0.8 1.0 1.2 1.4
\ 1.6 1.8 2.0
Time, J.lsec

Fig. 33.4. Blocking-oscillator waveforms with 1,OOO-ohm load.


Blocking Oscillators 431
40
tl
"0
> 30
eli
00
2
"0 20
1\ I

2
>
5
t)
10
\ )
i-""
\ V
---
"0
u ~
0
2

tl
"0 0
>
eli
00
2 -2
"0
~ I
~
>
'-
Ql

'E
-4 \ /
LLl
\ ~ f..-- /
-6

tl
"0
8

6 I -- r-- --.. i'o...


/ \
>
eli
00
2 4
"0
>
"C
ro
0
-l
2
I \
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Time, [J.sec

Fig. 33.5. Blocking-oscillator waveforms with 100-ohm load.

When the current in the magnetizing inductance builds up to i Dl in Eq. (9), the
diode current will be zero, and the transistor will begin to turn OFF. Since the
current in the magnetizing inductance increases linearly with time, the pulse width is

(10)

The value of Lm necessary for a l-/lsec pulse is calculated in the following exam-
ple; assume:
re = 2.7 ohms
rb = 50 ohms
RL = 100 ohms
n = ¥!
0'0 = 0.98
432 Switching-mode Designs

Then,
(1 X 10-6 )(25)
(5)(0.98) _ 1 1 = 24/-th
2.7 + 50(1 - 0.98) - 100
The circuit in Fig. 33.3 is a second common-base blocking oscillator, using a
2N338. The effect of loading is displayed in Figs. 33.4 and 33.5, which show the
voltage waveforms for 1,000- and 100-ohm loads, respectively.

BIBLIOGRAPHY

Linvill, J. c., and J. F. Gibbons: "Transistors and Active Elements," pp. 492-498, McGraw-
Hill Book Company, Inc., New York, 1961.
34
D-C Converters

Electronic equipment often requires, for its operation, a d-c voltage different
from the available d-c power source. The circuit used to convert direct current
from one level to another efficiently is called a d-c power converter.
The most simple and efficient power converters usually contain two power tran-
sistors and a special transformer, so connected that a regenerative switching action
exists between the two transistors. The transformer, a vital part of the system,
has a core material with a hysteresis curve approaching a square loop. The out-
put is an almost perfect square wave, and, when rectified, the resultant voltage
contains very little ripple.

34.1. THEORY OF OPERATION

The basic circuit for a converter is shown in Fig. 34.la. Its output is magnet-
ically coupled to its input through a square core transformer which has a charac-
teristic hysteresis curve as shown in Fig. 34.1b.
To begin the explanation of its operation, assume that the circuit is oscillating.
If transistor Ql is conducting, the supply voltage is dropped across the transformer
primary, N 1 , and the rate of flux change is linear, as indicated by the equation
dO Vee
(I)
dt Nl X 10-8
where dO/dt = change of flux in core with respect to time, webers/sec
Vee = supply voltage, volts
Nl = one-half the total number of turns on the primary, i.e., from one
end to center tap
[Equation (I) ignores the saturation voltage of the transistor and the resistive drop
in Nl in order to simplify the explanation.] This changing flux in the core will
then induce a voltage in the other coils, with polarity as shown by the dots and
magnitude proportional to the turns ratio. Therefore, transistor Ql is biased ON
with a negative base voltage and transistor Q2 is OFF with a positive voltage.
Curves 2 and 4 of Fig. 34.lc show the collector and base voltages of transistor Ql.
433
434 Switching-mode Designs

(a)

d ~
t
(1)

H
.. (3)
t
Square hysteresis loop

(b)
.. (4)
(c) t

Fig. 34.1. A typical converter.

Curve 3 shows that flux change is linear as indicated by Eq. (1). When the core
approaches saturation, the induced voltages are reduced, and the base drive is
therefore reduced. Since transistor Ql is turning OFF, the induced voltage across
Nl is reversed. This causes a reversal of bias, and transistor Q2 is turned ON as
transistor Ql is turned OFF. The cycle then continues. It should be noted from
Fig. 34.1a that when transistor Ql is conducting, Nl of transistor Q2 has an induced
voltage of such polarity as to add to the supply voltage. Therefore, twice the sup-
ply voltage appears across each transistor during its OFF time.
The current waveform of the inverter can be explained by the transformer equiva-
lent circuit as given in Fig. 34.2. Figure 34.2h is an approximate equivalent of
34.2a as seen from the input terminals, where Rl is the effective primary resistance
and R2 is the effective secondary and load resistance referred to the primary.
Depending on the sum of Rl and R 2 , the current will rise instantly, as shown by
curve 1 of Fig. 34.1c. Then, by the equation
D-C Converters 435

di V (2)
dt L
the current will increase at a constant rate. The current spike at the end of the
waveform is due to core saturation since inductance approaches zero. The current
will tend to rise to a value governed by the current gain of the transistor.

34.2. TRANSFORMER CONSIDERATIONS

The basic equation describing converter operation as derived from Eq. (1) is
V = 4BmjNl SA X 10-8 (3)
where V = peak squa~e-wave voltage impressed across saturation-core primary
winding N l , volts
Bm = maximum flux density of saturating core, gauss
f = frequency of oscillation, cps
Nl = number of primary turns on saturating core carrying load current for
the ON transistor (i.e., from collector end to center tap)
A = cross-sectional area of saturating core, cm2
S = stacking factor of core
Thus, it becomes apparent that in the basic converter, i.e., the single-transformer
configuration, the transformer performs two functions. Not only does it perform
the standard function of transformation of power, but it determines the frequency
of oscillation as well. The function of the transistors is simply to switch the d-c
supply from one-half of the center-tapped primary to the other, thus permitting
the resulting square-wave a-c voltage to be transformed to the secondary.
The design of the transformer involves the same considerations as that of a
standard transformer with respect to amount and type of insulation, wire size, and
window area necessary for windings. Equation (3) is of fundamental importance
in determining the relationship among the core size, frequency, and supply voltage.

=b~
Input L
M

(a)
Rc
RL

(b)
Fig. 34.2. Approximate transformer equivalent circuits.
436 Switching-mode Designs
34.3. TRANSISTOR CONSIDERATIONS

The transistors for a particular converter must satisfy two basic requirements.
They should have a useful hFE at a current level determined by the maximum
value of the primary load current, and they must be capable of withstanding the
maximum voltage applied to the collector-to-emitter terminals. As previously
mentioned, this voltage will be approximately twice the supply voltage (if no volt-
age spikes are present), and will appear across the OFF transistor terminals.
Generally speaking, it is best to limit this maximum collector-emitter voltage to
less than the BVCES rating of the transistor.

34.4. STARTING
The most common type of starting circuit is the resistive voltage-divider type
such as shown in Fig. 34.1. A slight forward bias is applied to both transistors
through the starting resistor Rs. The required magnitude of Rs is primarily a
function of the load and the hFE of the transistors. The worst case for starting will
occur with heavy loads and at low temperatures, where hFE is minimum. A filter
capacitor on the secondary requires a heavy surge of current during starting as it
charges up. Because this initial heavy load can make starting difficult, filter capaci-
tors should be as small as possible.
The value of starting resistance is generally best determined by trial and error,
but an approximate value can be determined from

VI = VCCRB (4)
Rs+RB
where VI ~ 0.3 for germanium transistors, and VI ~ 0.5 for silicon transistors.
To reduce losses, a diode can be used instead of R B , being placed so that base
current can flow in the forward direction. The value of Rs can be increased since
the diode appears as an open circuit until the oscillations begin.

34.5. CIRCUIT CONFIGURATIONS

The most frequently used circuits are the common-emitter configuration shown
in Fig. 34.1 and the common-collector autotransformer configuration shown in
Fig. 34.3.
The common-collector autotransformer configuration has this advantage over
the common-emitter configuration: The cases of the transistors can be mounted
directly on a common heat sink without using insulating washers. A disadvantage
is the need for additional base and starting resistors.
The dual-transformer configuration shown in Fig. 34.4 has many advantages
over the single-transformer configuration. A comparison of the typical collector
currents of both configurations at no load and full load, illustrated in Figs. 34.5
and 34.6, reveals one of them: Since the output transformer of the two-transformer
configuration does not saturate, its magnetizing current is never large.
In the single-transformer converter, once the transformer saturates, the collector
D-C Converters 437

Fig. 34.3. Common-collector autotransformer configuration.

current increases until it tends to exceed hpEIB , i.e., pulls the ON transistor out of
saturation. Conservative design is usually based upon the minimum value of
hpE, i.e.,
(5)
where 1£ = maximum load current reflected to the primary. Since many transis-
tors exhibit a 3 : 1 hpE spread, it would be possible for the actual peak collector cur-
rent to be three times greater than the maximum reflected load current in those
transistors with a high hpE.
The dual-transformer configuration differs from the conventional converter in
that switching is determined by the small saturating tape-wound toroidal trans-
former, while the larger nonsaturating power transformer handles the feedback
and output power transformation. Since the output transformer does not saturate,
switching is not determined by the increasing magnetizing current pulling the ON
transistor out of saturation. Instead, the ON transistor is pulled out of saturation
by the decrease in base current which occurs when the toroidal transformer satu-
rates. As the core reaches saturation, the increasing magnetizing current causes

- Vee •

Fig. 34.4. Basic dual-transformer converter.


438 Switching-mode Designs

Full-load current No-load current


I L---- ------

Time
Fig. 34.5. Dual-transformer converter: typical collector currents.

Full-load current No-load current


hFEIB - - - -----

Time
Fig. 34.6. Single-transformer converter: typical collector currents.

an additional voltage drop across the feedback resistor R p . Thus the primary of
the saturated transformer has less voltage dropped across it, effecting the decrease
in secondary or base-drive voltage.

34.6. PRACTICAL CIRCUITS

Figures 34.7 to 34.9 and Table 34.1 provide circuit diagrams and parts lists for
the following eight converters which are typical, practical circuits:
Converter Voltage Voltage Transistor
output rating, watts input output type
15 12 300 2N1038
30 12 300 2N1042
55 12 100 2N456
100 12 300 2N511
150 12 500 2N512
200 12 300 2N513
250 12 500 2N514
500 28 300 2N'i14A

Performance Characteristics. Figures 34.10 through 34.17 show plots of out-


put voltage, output power, frequency, and efficiency vs. load current for the eight
different converters. The output-voltage regulation is seen to be less than 7%
D-C Converters 439

Fig. 34.7. Type A converter.

Fig. 34.8. Type B converter.

Fig. 34.9. Type C SOO-watt converter.


l>-
I>-
o
Table 34.1. Parts List for Figs. 34.7 to 34.9

N 1, N 2, N 3, Zener Diodes
RB or RB, Rs, Rp , Diodes C, Rating,
Transistors Transformer Transformer turns turns turns diode, D 3 ,D4 ,
Type of circuit ohms ohms ohms D 1, D2 pi watts
Ql, Q2 Tl T2 AWG AWG AWG Dz D5,Ds
A 2N1038 Arnold .... 70 20 1,800 IS 1,200 . ... . ... . ... IN2071 2 IS
5772D2 No. 18 No. 30 No. 30
A 2N1042 Magnetics .... 78 30 2,000 15 1,500 ... . . . .. . ... IN2071 4 30
500172A No. 16 No. 29 No. 29
A 2N456 Magnetics .... 29 6 275 5 180 . ... . ... . ... IN2071 6 55
500352A No. 17 No. 24 No. 24
B 2N511 Magnetics TI 48 ... . 185 2 100 5 INI817 IN2069 IN2071 10 100
500942A 440402-1 No. 24 No. 28
B 2N512 Magnetics TI 48 .... 185 2 75 10 INI817 IN2069 I N207 I 20 150
501812A 440404-1 No. 22 No. 26
B 2N513 Magnetics TI 35 .... 140 I 75 5 INI817 IN2069 IN2071 20 200
500262A 440406-1 No. 20 No. 26
B 2N514 Magnetics TI 35 ... , 140 1 75 5 INI817 IN2069 IN2071 30 250
500262A 440408-1 No. 20 No. 24
C 2N514A Arnold TI 35 .... 140 RB = Y, 75 10 INI825 IN2069 INI126 40 500
5233D2 440413-1 No. 20 No. 24 RB = y, ----
L-_____ -- - --
D-C Converters 441

f %
cps Eff

300 30
J .1
Output voltage
1 600

-
EffiCiency
200 20 ,- ./
400 80

V Frequency /'

100 10 I 1>tI~V
'V0 200 40
If ¥~ V(in) = 12 volts

V
Fig. 34.10. 1 5-watt con-
o 0 l/ 0 o
o 10 20 30 40 50 60 70
verter. Load current, rna

from one-half to rated load. The output power is almost a straight-line function
ofload current, as one would expect. The frequency of the 15-,30-, and 55-watt
converters decreases slightly under load. The frequency of the two-transformer
converters remains almost constant under load.
The efficiency of all the converters is greater than 80% at rated load. The out-
put ripple on all converters is less than 4% at rated load.
All these circuits are conservatively rated. In particular, the 500-watt converter
has attained an output power of 700 watts on an intermittent basis.
Design Information. The step-by-step design for the 200-watt dual-transformer
converter is given; the procedure may be followed in designing similar circuits.

f %
cps Eff

600 30 600
V
V Efficiency

--t-,~~
.!:!::.s..uency
400 20 / 400 80
L / Output voltag;;-
_

200 10 200 40
()~
I I
V (in) = 12 volts

o 0
o
Vl 15 30 45 60 75 90 105 120
0 0

Fig. 34.11. 30-watt converter. Load current, rna


442 Switching-mode Designs

f %
cps Eff

120 60 / 1,200
Output voltage
/
/

80 40
Frequency
V
Efficiency - - 800 80

/ /0- V o;f.

40 20 L '/ ~
1'..~
,::;

V (in) = 12 volts
'I 1
400 40

0 0 0 /
o 100 200 300 400 500 600 700
o
Fig. 34.12. 55-watt con-
Load current, rna verter.

The following information is given:


Output power, Po = 200 watts.
Supply voltage, Vee = 12. volts.
Output voltage, Vo = 300 volts.
Core = Orthonol® toroid.
Frequency = 400 cps.
Circuit configuration = common emitter, i.e., type B converter.
A converter efficiency of 80% is assumed. The necessary input power is
Po
P(in) = --:;;- = 200
0.8 = 250 watts (6)

f %
cps Eff

/
V
600 120 600
V'
/ Frequency
/
~ V
400 80
-. .--t7 EfiCienfY-
400 80

i>""

/
V &/ outPUj vOlti ge-

I opy
200 40 ,::; ~
.... 200 40
1 ,I
V (in) = 12 volts

o 0 /
o 50 100 150 200 250 300 350 400 450
0 0

Load current, rna

Fig. 34.13. l00-waH converter.


D-C Converters 443

f %
cps Eff

600

400
300

200
----
frequency
~y
I
Output voltage

/
600

400 80

./
,,/'
rp
200 100
(I
/Jj
,/'
V
O~'I.~~
~~o

V (in) = 12 volts
I
200 40

o o. / 0 o
o 50 100 150 200 250 300 350 400
Load current, rna

Fig. 34.14. 150-watt converter.

where P(in) = input power


Po = output power
TJ = efficiency

The collector current of each transistor is given by


I - P(in) - 250 - 20 8 (7)
e- Vee - 12 - . amp

where Vee = supply voltage. The 2N513 transistor is selected on the basis of
maximum collector current and maximum collector breakdown voltages. Each

f %
cps Eff

600 300 600

Frequency ~
400 200 400 80
~ency
/' ki
~/ '
ou1ut vTage
/V o~

P
200 100 I I 200 40

I V"
O~....~
'/
V (in) = 12 volts

o o
y 0 o
o 100 200 300 400 500 600 700 800
Load current, rna

Fig. 34.15. 200-watt converter.


444 Switching-mode Designs

f %
cps Eff
600 300 1 .1
600
Output voltage
./

400 200
.1
Frequency
1
.;'
./ 400 80
¥~ ./
~,0 O-.t\0V
/ ~ ~\.<9
200 100
if J'
::P V (in) = 12 volts
200 40

V"
o o V 0 o
o 60 120 180 240 300 360 420 480 540
Load current, rna
Fig. 34.16. 2S0-watt converter.

transistor, during its OFF time, is subjected to approximately twice the supply
voltage. The base current of each transistor is

IB = hp~:in) = 2~08 = l.04 amp (8)

where IB = base current, and hPE(min) = minimum short-circuit current gain at


specified Ie. From the data sheet for the 2N513, the maximum base-to-emitter
voltage is 2 volts. The base-drive voltage is made equal to twice the maximum
base-to-emitter voltage, to reduce the effect of variation in VBE among transistors.

f %
cps Eff

I I
300 600
"' r---. Output voltage
600

Eft"IClency
.I
./
200 400 ./ 400 80

1/ Frequency
./
100 200 I ~o
~~
. /
200 40
V O\).\.~ V (in) = 28 volts

V
o o V 0 o
o 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
Load current, rna

Fig. 34.17. SOO-waH converter.


D-C Converters 445

The power required by the base drive is given by


PD = VD 1B = 4(1.04) = 4.16 watts (9)
where PD = drive power, and VD = drive voltage. A 90% efficiency is assumed
for the drive transformer. Therefore, the power supplied to the primary of the
drive transformer is
PD 4.15
P 2 = 0.9 = G.9 = 4.6 watts (10)

The turns ratio for the drive transformer is chosen as 4: 1. This sets the primary
voltage of the drive transformer at 16 volts. The primary current of the drive
transformer is given by
12 = P 2 = 4.6 = 288 rna (11)
V2 16
N ext, the wire sizes for the primary and secondary turns are chosen, based on
1,000 cir mils/amp:
N2 (primary) A WG No. 26 (320 cir mils).
Nl (secondary) AWG No. 20 (1,197 cir mils).
Selection of the toroidal core for the drive transformer is next. One method is
to determine the necessary W A product from known and estimated factors and.
use this product for core selection. WA is the product of the core window area,
W, and the core cross-sectional area, A. It is frequently listed in the manufactur-
er's catalog of core data.
A necessary step in this procedure is to estimate the ratio of total wire area to
the core window area. This ratio is the K factor, which for this particular design
can be expressed as
K = N~W2 + 2N1Awl = N~W2 + hN~W2 (12)
W W
where K = ratio of total wire area to core window area
A W = area of single strand of wire, cir mils
W = area of core window, cir mils
The K factor is estimated to be 0.2 to assure ease in winding the core. Sepa-
rating the known and unknown quantities in Eq. (12) results in
N2 K
(13)
W AW2 + hAwl
Since the only unknowns in the basic transformer expression of Eq. (3) are the
number of primary turns N2 and the area of the core A, Eqs. (3) and (13) can be
solved simultaneously for the product of Wand A:
WA = V(AW2 + 1f2A W1 ) (16)(919)
(14)
K4B m fx 10- 8 (0.2)(4)(14,000)(400) X 10-3
WA = 328,000
446 Switching-mode Designs

:3
:3 N2

IO-N- - - - o
3

Fig. 34.1 8. Schematic diagram


of transformer. Fig. 34.19. Transformer core.

For the required WA product, a Magnetics 50026-2A core is chosen. The area is
seen to be 0.514 cm2 • N2 is calculated to be 140 turns, using Eq. (3). Nl is found
to be 35 turns. The number of primary and secondary turns and size of the wire
are then determined. The K factor is checked; the actual K factor is slightly less
than 0.2.
The design is completed with the determination of R B , R s , R F , and the power
transformer. The base resistor RB is chosen to drop approximately half of the 4
volts supplied. The starting resistor Rs is made as large as possible to keep losses
to a minimum and still assure reliable starting. The feedback resistor RF is chosen
to give 16 volts across the primary of the drive transformer at rated load.
The core loss in the 200-watt power transformer at rated load is calculated to be
10 watts. The primary and secondary winding losses are approximately 2 watts
each. The input impedance of the transformer is made equal to approximately 40
times the load resistance. Figures 34.18 and 34.19 in conjunction with Table 34.1
give power transformer information.

BIBLIOGRAPHY

Jensen, J. L.: An Improved Square-wave Oscillator Circuit, IRE Trans., vol. CT-4, no. 3,
pp. 276-279, September, 1957.
Nowicki, J. R.: New High Power DC Converter Circuits, Mullard Tech. Pub., vol. 5, no. 43,
pp. 104-114, April, 1961.
35
Inverters

An inverter as defined here provides an a-c output from a d-c supply. In the
simplest transistor inverters, the a-c output is a square wave. Many kinds of equip-
ment will operate satisfactorily on a square-wave voltage, but in some instances
a filter on the secondary is necessary in order to suppress objectionable harmonics.
The fundamental harmonic content of a square wave is the maximum value of the
square wave divided by 1.11. Thus, if a 115-volt rms sine wave is needed, the trans-
former output should be 128 volts plus ruter drops.
In a converter, the exact value of frequency of oscillation and its change with load
and input-voltage variations are not usually important. In an inverter, however,
these considerations may be quite important. The frequency of oscillation of most
common circuits is set by a saturating-core oscillator, and is dependent upon
voltage as shown by the basic converter and inverter equation,
E = 4Bm fN l SA X 10-8 (1)
where E = peak square-wave voltage impressed across one-half the total center-
tapped primary winding, volts
Bm = maximum flux density of the saturating core, gauss
f = frequency of oscillation, cps
Nl = one-half the number of total primary turns on the saturating core
A = cross-sectional area of the saturating core, cm 2
S = stacking factor of the core
Equation (1) shows that frequency is dependent on voltage since all other values
are constant for a particular core. Therefore, the frequency can be controlled by
controlling the input voltage. The transformer equivalent circuit of Fig. 34.2b (d-c
converters) indicates that frequency may be controlled by controlling the induced
voltage, which is given by the equation
E _ EAR2 (2)
t - Rl + R2
where Ei = induced voltage, and EA = applied voltage to the transformer. Ideally,
Rl should be zero or very small with respect to R 2 • One method of minimizing
447
448 Switching-mode Designs

Induced
voltage
sampler

Fig. 35.1. Block diagram of 60-cycle power inverter.

the difference between applied and induced voltage is to use large wire on the
primary so that Ei approaches EA in Eq. (2). But this does not compensate for the
change in transistor saturation voltage with current, which will cause a variation
in frequency with load. If the input voltage is regulated, the frequency can be
controlled to about -+-2% by using extra-large wire in the primary of the saturating-
core transformer.

35.1. FREQUENCY STABILITY

If closer frequency control is required, it is evident that a method of measuring


the induced-voltage variation must be used, so that compensation can be obtained
by adjusting the oscillator supply voltage. Figure 35.1 shows a block diagram of
the frequency-stable power inverter. The frequency of operation of the saturating-
core oscillator is dependent on the induced voltage of the oscillator transformer.
This induced voltage is detected by a sensing circuit which varies the output voltage
of the regulator to keep the transformer-induced voltage constant, and therefore
stabilizes the frequency. The oscillator is transformer-coupled to the power ampli-
fier, which supplies power to the load. Only the oscillator requires regulated
supply voltage; hence, the power amplifier is connected directly to the power supply.
Saturating-core Oscillator. The oscillator is an inverter using a saturating
transformer. Its circuit is identical with the basic converter circuit (without the
rectifiers) shown in Fig. 34.la.
Induced-voltage-sensing Circuit. The sensing circuit is connected (as shown
in Fig. 35.2) to each primary coil of the oscillator during the OFF cycle. The

Nl
t----o Regulated O--~f----t-----o
+ supply _ +
Induced voltage
output

Fig. 35.2. Induced-voltage-sensing circuit.


Inverters 449

---#,~~-.~-------------------o+

+ 0----+----..,.,(

Regulated
output
Battery Induced
supply feedback
sensing
input

Fig. 35.3. Inverter regulator.

voltage seen by the sensing circuit is almost identical with the true induced voltage
because of the high-impedance input circuit of the regulator.
Voltage Regulator. The regulator circuit is shown in Fig. 35.3. The induced
voltage is negative with respect to the negative terminal of the supply and drives
the base of Q3. If the induced voltage decreases, the drive to Q3 is increased by
the ratio of the reference voltage at the emitter to the voltage applied at the base.
The series regulator Q5 therefore increases the voltage fed to the saturating-core
oscillator. Consequently, the induced voltage will increase to approximately the
initial value.
The diodes D2 and D3 provide temperature compensation for the avalanche
diode Dl and the transistor Q3. The capacitor C1 decreases the high-frequency
response of the regulator amplifier. R7 provides sufficient regulator output voltage
to initiate oscillations when power is initially applied.

35.2. POWER AMPLIFIER

The power amplifier as shown in Fig. 35.4 is driven by the oscillator and is
supplied with power directly from the power supply. If regulated output voltage
is a requirement, a transistor regulator may be inserted between the supply and
this amplifier.
Power
transformer

Battery
\o--J1./\,rv----+---o+ supply _

Fig. 35.4. Driven power amplifier.


450 Switching-mode Designs

The power transformer is wound with sufficient turns to provide square-wave


output voltage at the frequency concerned. Peak current in the power transistor
will be the peak reflected load current. Magnetizing current should be small since
this transformer core is never saturated.

35.3. DESIGN PROCEDURE FOR 200 WATTS AT 60 CYCLES

A specific example will be used to explain the design procedure for the inverter
circuit as outlined above. Assume the output to be a 60-cps 200-watt 115-volt
square wave. The load is assumed to be resistive with no reactive component (most
tape recorders, television sets, etc., are highly resistive). The input is a 12.6-volt
automobile battery. The complete circuit diagram is shown in Fig. 35.5.
The Driven Power Amplifier. The power transformer must have sufficient core
area to avoid saturation and high transistor currents, as discussed previously. The
usual efficiency of this type of transformer should be in the order of 90%. A trans-
former design for this application is given in Fig. 35.6. If efficiency is 90%, 220
watts will be required at the transformer input.
Allowing for the power-transistor saturation voltage and transformer-primary
resistance drop, the input to the primary of the transformer would be a square wave
having a peak amplitude of approximately 11.5 volts. The transformer turns ratio
is then
(3)

The peak primary current is

I - P(in) - 220 - 191 (4)


p - E1 - 11.5 - . amp

For the transformer load, the voltage across the transistor during its OFF period
is twice the supply voltage. These two requirements necessitate a 20-amp transistor
with a BVCEX rating of over 30 volts. The 2N513A and 2N514A units meet both
requirements, but the 2N514A will be used in this application since it has a higher
minimum h pE• A base current of 1 amp will be required since this unit has a
guaranteed minimum current gain of 20 at 25 amp. Typical VBE is 0.5 to 1.0 volt;
therefore, the induced voltage of N 3 will be 2 volts to take care of possible variations.
RBl should be a I-ohm 5-watt noninductive resistor to assure sufficient overdrive
for low saturation voltage. The efficiency of the whole system is governed almost
entirely by power losses due to saturation, switching time, and the power trans-
former.
The Saturating-core Oscillator. Most important in the oscillator design is the
saturating-core transformer. The core should have: (1) a square BH characteristic
for frequency stability with load variations, (2) a saturation flux density, B M , such
that neither the number of turns nor the cross-sectional area has to be excessive,
and (3) low losses at the frequency used (this is a function of the material and the
lamination thickness, both of which are functions of the area enclosed by the BH
curve). A tape-wound core of 50:50 nickel-iron (saturation flux density - 14,500
lOon
A t 0+

Saturating transformer data:


Core - The Arnold Engineering 1.62 K
CO.3T·7189·D4
Coil 1: 160 turns each of No. 26 wire 50 n pot
Coil 2: 20 turns each of No. 36 wire Fine frequency
Coil 3: 40 turns each of No. 20 wire control 12.6v

Note: (1) Power transformer data 1 K pot


included in Fig. 35.10 Coarse frequency
(2) All resistors are 1f2 watt control
except where indicated
1N2069 4.64K
1N2069
2N1038

1N2069 I •
Nt
2N514A

1N2069

Nt

2N1038

N2
• Power
1>0.
2N514A
.."
N2
• transformer

Fig. 35.5. 200-watt 60-cycle inverter.


452 Switching-mode Designs

0 28V
200w

CT s 2",
SI

r
I
0 \ Pl.2.~ Ip
0 0
\ 0
P2 IICT S2
II
II
II
'1
424359·1 :

1 0 /
PI
1
1

P 2. 1 0 0
S1
I 0

Winding
Specification
Primary Secondary

Tube ................... . Jl7!12 by Jl ~2 in., 04 FK Over primary


Wire size .................... . No. 13 FX No. 20 FX
Turns ........................ . 36 bifilar 468 ± 4
Taps ......................... . Bifilar
Turns/layer ................... . 12 52
Length: winding/coil. ......... . 12¥12-2'112 in. 12~2-2~2 in.
Paper ........................ . 0-1-0,0.007 kraft 0-1-0,0.005 kraft
Wrapper ..................... . I layer, 0.010 kraft 1 layer, 0.005 kraft
Anchor ...................... . 3fs-in. no. 27 '/4-in. no. 27
Saddle ................... . No. 27 tape
Lead ........................ . Self Self
Lead length .................. . 6 in. 6 in.
Lead anchor .................. . 3fs-in. no. 27 'A-in. no. 27
Final wrap ................... . I layer, 0.005 GK
Laminations .................. . EI-l3, 0.014 Silectron®
Stack ........................ . I by 1 by 1V, in.
Secure laminations ............ . Through bolts
Finish ....................... . Varnish-impregnated
Insulation resistance
10,000 megohms minimum at 500 volts doc between windings and from each winding
to core.

D-c resistance
Terminals Resistance (maximum), ohms
PI, P 2 0.12
S1, S2 4.0

Fig. 35.6. Transformer, power output 200 waHs.


Inverters 453

gauss and 0.004-in.-thick laminations) is adequate for the 60-cps frequency. When
using a tape-wound core, the gross core area must be multiplied by a stacking factor
to obtain the actual core area. Core size is a function of the cross-sectional area,
as shown by Eq. (1), and the area necessary to accommodate the windings. The
core size for the 200-watt inverter shown in this chapter was not optimized. The
availability of a usable core dictated this particular choice. The core constants are:
EM = 14,500 gauss.
Gross area = 1.61 cm 2 .
/= 60 cps.
Stacking factor = 0.9.
Window diameter = 1.15 in.
The voltage applied to the saturating-core transformer is assumed to be 8 volts.
This value permits 4 volts to be dropped across the voltage regulator with a supply
voltage of 12 volts, thus assuring reliable regulation.
From Eq. (1), Nl may be determined as
8 (5)
NI = (4)(14,500)(60)(1.61)(0.9)(10- 8) = 159 turns
The voltage induced in the oscillator base-drive windings, N 2 , should be in the order
of 1 volt. Therefore,
N2 = NI E2 = 160 X VB = 20 turns (6)
El
E3 (7)
and, further, N3 = NI El = 160 X % = 40 turns

The maximum current in the base circuit of the power stage will not exceed 2 amp
unless the regulator output exceeds 10 volts. Therefore, the maximum primary
current will be
N3
II = - h = 40/160 X 2 = 0.5 amp (8)
NI
The transistor for this application must be capable of carrying a collector current
of 0.5 amp and should have a BVOEX rating of over 20 volts. The 2N1038 more
than meets these requirements. Since it has a minimum current gain of 20 at
+25°C, a base current of 25 ma is sufficient. (For low-temperature operation this
must be increased to allow for a decrease in current gain.)
Wire size is calculated on the basis of 1,000 cir mils/amp. Since the duty cycle
is 50% for each winding, the minimum wire sizes are as follows:

ANI = 0.5 X 1,~00 = 250 cir mils (9)

AN2 = 0.025 X 1,~00 = 12.5 cir mils (10)

1,000
A N3 = 2 X -2- =,1 000 Clr. mils (11)
454 Switching-mode Designs

The AWG wire sizes are selected as 26, 36, and 20, respectively. Size 36 is larger
than necessary, but is selected for ease of handling. The total area of wire then is
Aw = 2N1A 26 + 2N~36 + 2NsA20 = 200,000 cir mils (12)
The available winding area in circular mils is
AA = (ID)2 = 1,320,000 cir mils (13)

Thus Aw = 0.152 (14)


AA
Equation (14) indicates that the core size is excessive. It could be reduced until
the result of this calculation is about 0.4. These windings should be bifilar-wound
to increase coupling and thereby reduce voltage spikes due to current interruption
in the leakage inductances.
Figure 35.7 shows an equivalent circuit of the emitter-base bias circuit. Before
oscillations start, the induced voltage across N2 is zero; therefore, the I-volt
potentials shown do not exist. The voltage across RB2 is then
8 X 40
ERB = 1,000 + 40 = 0.3 volt
(15)

This bias is enough to cause both transistors to begin conducting. Because of the
strong positive feedback provided by the base-drive windings, any slight disturbance
in the collector currents becomes amplified until one transistor is driven into satu-
ration. This condition persists until the core saturates and the base drive fails.
Then the saturated transistor turns OFF, and the cycle repeats with the opposite
transistor. To calculate base bias current after the circuit is running, Fig. 35.7 is
drawn for one condition of base voltages, i.e., when transistor 1 is ON and tran-
sistor 2 is OFF. If VBE = 0.4 volt for transistor 1, 11 = 8.6 rna, and 12 = -15 rna
to provide the necessary base-drive current, IBl = 23.6 rna. Transistor 2 as shown
has a reverse bias of 1.6 volts, and is therefore turned OFF.
The Voltage Regulator. The direct current to the oscillator will be 0.5 to 0.7
amp; thus, a 2N1038 can be used as the series regulator Q5, as shown in Fig. 35.3.

+
Rs

lK
--
11

RB2
+r ERB Q1
C
Q2
C
40n
Regulated -=:l 1.6v
voltage
E s =8v
~I2
t+

Fig. 35.7. Equivalent oscillator bias circuit.


Inverters 455
60.2
V
60.1 rEJ 131 ~
~
,........,V
./

- --
If)
c.
u ~ V
>; 60.0
E(in) = 12.5v
~
u
c
C1)
::J
~ 59.9
i I
E(in)-1l·5v
.... TA =25°C
59.8 I I

o 50 100 150 200


Power output, watts
Fig. 35.S. Frequency vs. power output with input voltage constant.

Since the 2N1038 has a minimum current gain of 20, the required base current will
be 35 ma, which can be provided by a 2N1372. The minimum current gain of the
2N1372 is 30; therefore, its maximum base current will be 1.2 mao A 2N120
silicon transistor was selected for Q3 to minimize change in regulator output voltage
with temperature. The 2N120 has a minimum current gain of 76; therefore, 16 /La
base current will be required.
The induced voltage from the sensing circuit shown in Fig. 35.2 will be approxi-
mately 7.5 volts when the 0.5-volt drop across the sensing diodes is taken into
account. Dl is a IN75lA avalanche diode, which has a nominal reference voltage
of 5.1 volts, and R5 was selected to provide approximately 4 ma of diode current.
Temperature compensation of the regulator was accomplished by connecting a pair
of IN2069 silicon diodes, D2 and D 3 , in series with D 1 . C1 was found to be unneces-
sary after the 4-p,[ despiking capacitors were connected from base to emitter of the
two 2N514A transistors in Fig. 35.5.
Test Results and Data for the 200-watt 60-cycle Inverter. Figure 35.8
shows experimental data for frequency variation vS. changes in load at different
constant input voltages. The maximum frequency variation for a change of load
from 0 to 200 watts and a voltage change of 11.5 to 13.5 volts is less than 0.5%.
The curves swing upward as the output power is increased, owing to the increase
in base-to-emitter voltage of the 2N514A transistors. Thus, the base current
decreases and results in less load on the saturating-core oscillator. For typical
installations, the input voltage to the inverter will decrease as the load is increased;
therefore, the frequency will vary less with power output than indicated by Fig.
35.10.
The variation of frequency with temperature is shown in Fig. 35.9 for no-load
and full-load conditions. For various transistors used in the inverter circuit, the
per cent frequency deviation was approximately the same as indicated by Fig. 35.9;
however, the shape of the curves in each case was different.
Figure 35.10 shows efficiency plotted against output power. An interesting point
is that the efficiency is about 86% at 200 watts. The efficiency of the transformer
at these powers was around 90%. This means that the power transformer was a
major factor in circuit efficiency. The no-load input power was 8.5 watts.
456 Switching-mode Designs

60.25
V
~
p
'"
a. ~w V
u. 60.00 -p ./
o ~ ~r::::::: ~ V-
~
c:
Q)
::s
~ 59.75
r-- V
u..
E(in) = 12.5v d·c
59.50

-20 o +20 +40 +60


Temperature, °C

Fig. 35.9. Frequency vs. temperature for no-load and full-load conditions.

For a l2-hr period, during which supply voltage may have varied only slightly,
maximum frequency variation was less than 0.1 %.

35.4. ADDITIONAL CIRCUITS

Figure 35.11 shows a circuit for a lOa-watt 60-cps inverter. It was not as
thoroughly tested as the 200-watt circuit. Slightly more frequency change with
temperature may be expected since the sensing-input transistor (2N1302) is
germanium.
Figure 35.12 shows a low-power 60-cycle inverter designed to drive a timer. This
circuit does not include the sensing circuit, but instead makes the primary oscillator
windings large enough to reduce the effect of the primary resistance. The timer
represented an almost constant load except for variations in supply voltage. For
supply-voltage variations between 11.5 and 14.5 volts, the maximum frequency
variation was +1 %.

100

./
,,- -r-.- 1"--0..
80
>,
u
c:
Q)
'u 60 I
V
:E
Q)
.....c:
Q)
u
40 I
~
20 I T=25°C
E(in) =12.5v

0 50 100 150 200


Power output, watts
Fig. 35.10. Efficiency vs. power output.
2.15 K

~ ~, ,9+

1.78 K
Saturating transformer data:
Core -Magnetics, Inc., 50181·4A 5012 pot
Coil 1: 600 turns each of No. 30 wire Fine frequency
control 12.6v
Coil 2: 75 turns each of No. 38 wire
Coil 3: 115 turns each of No. 26 wire 1 K pot
Note: (1) All resistors are % watt
except where indicated
1 N7 5pA Ci4"\ 1\~ ) 1.? Coa rsc~~~~~ency
IN2069 5.62 K

1N2069
2N1372

1N2069 I •
Nl
2N511A

IN2069 Nl

L _ _ I __ ---'I
2N511A Power
~ transformer
.."
'-j

Fig. 35.11. 100-watt 60-cycle inverter.


458 Switching-mode Designs

r-~----------~------------------'------------o+

2N1372 2N1372

----, I
I
I
I
I
I I
IL _ _Motor
_ _ _ JI

Transformer data:
Core - Magnetics, Inc., 50076-4A Coil 2: 130 turns each of No. 36 wire
Coil 1: 1,100 turns each of No. 36wire Coil 3: 200 turns each of No. 36 wire
Note: All resistors are 1f2 watt

Fig. 35.12. 20-watt 60-cycle inverter.

RF~'-------------------~

12v
~~--o O~-r--~~
+

Parts List
Xl-Tape-wound toroid, 5320-D4 Arnold Engineer-
Ql, Q2-2N514 ing Co., or 5000-4A Magnetics, Inc.
D l -IN1823 (27-volt double-anode clipper) N l -316 turns, #24 heavy Formvar
R F -20-ohm 5-watt rheostat N 2, N3-79 turns, #22 heavy Formvar
R l , R2-1 ohm, 5 watts Tl-Texas Instruments transformer #440401 or
R 3 , R 4 -150 ohms, I watt equivalent
Fig. 35.13. 250-waH 60-cycle dual-transformer inverter.
Inverters 459

Parts List
Ql through Qs-2N458A Tl-Texas Instruments transformer #440220 or equivalent
Dl through D s-IN2069 Xl-Tapewound toroidal core, 51425-4A Magnetics Inc., or
D9 through D l2 -IN1825R 5772-D4 Arnold Co.
Rl through Rs-5 ohms, I watt Nl--448 turns, #22 heavy Formvar
R9 through Rl6 -910 ohms, I watt N2 through N9-112 turns, #28 heavy Formvar
Rr-25-ohm 5-watt rheostat
Fig. 35.14. 400-watt 60-cyc/e dual-transformer inverter.
460 Switching-mode Designs

The dual-transformer configuration is an especially useful inverter circuit. Two


power inverters using this configuration are illustrated in Figs. 35.13 and 35.14. The
inverter in Fig. 35.13 operates from a 12-volt d-c supply and provides a 6O-cyc1e
130-volt square-wave output to a 250-watt load. Performance characteristics are
illustrated in Fig. 35.15. An inverter designed to operate from a 120-volt d-c supply
and capable of over 400 watts output is illustrated in Fig. 35.14. Input voltage is
divided equally across the four series primaries, subjecting each transistor to only
60 volts in the OFF condition. Output voltage is a 60-cyc1e 140-volt square wave.
Operating characteristics are illustrated in Fig. 35.16.
The output transformers (Tl in each instance) were designed by the transformer
engineering department of Texas Instruments. * These transformers were designed
for maximum efficiency and minimum sag in the output square wave. To this end,
size and weight considerations were sacrificed, making these transformers larger
than many commercial transformers with similar power ratings. The output trans-
formers of the 250- and 400-watt inverters weigh 22lb each. If size and weight are
of prime importance, almost any 60-cyc1e output transformer should operate satis-
factorily if it does not saturate and if it can handle the required power.
Several advantages of this dual-transformer configuration were discussed in Chap.
34, D-C Converters. Another important advantage when used in an inverter is the
ease with which the frequency of oscillation can be adjusted. The frequency vs.
load-current curves shown in Figs. 35.15 and 35.16 cover one particular value of
R p . Frequency can be adjusted to exactly 60 cps for any value of load current by
varying this resistance. On the other hand, a single-transformer configuration offers
* Information concerning these transformers can be obtained by contacting the transformer
engineering department of Texas Instruments Incorporated, Box 6015, Dallas 22, Tex.

f %
cps Eft
240

200
300

250
y 120

100
120

100
/iI
160 200
t.~~ 1/ 80 80
~
-L. /olutput vJltage
120 150
L /
60 60
/ Frequency

80 100 ~q
>:i
# 0/ Input voltage
I
Full·load
12 v d·c
40 40

~ resistive load
40 50 0/ 20 20
/
o o o o Fig. 35.15. 250-watt in-
o 0.5 1.0 1.5 2.0 2.5 verter operating charac-
Load current, amp teristics.
Inverters 461

~ ~ f %
..r
200
~
500
cps
100
Eff
100
Efficiency I

160 400 ~
i"'"-" I
I V 80 80
V Output voltage A
/ ./ I
120 300 Frequency 60 60
V
I
I

80 200
I ,>-'~
0
~e' V I
I
I
40 40
Full·load

40 100 ~ I
Input voltage 120 v d·c- 20 20
V resistive load

o o
/ I I I o 0
o 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Load current, amp

Fig. 35.16. 400-watt inverter operating characteristics.

no method of frequency adjustment other than varying the d-c supply voltage, and
in most instances this is impractical.
An additional modification will provide a constant-frequency output for a limited
variation of the supply voltage. The addition of a double-anode breakdown diode
across the primary (from point A to point B in Fig. 35.13) of the small saturating
drive transformer will provide the constant voltage necessary for a fixed frequency.
Note that the feedback resistor will act as the series dropping element necessary
for a simple regulator of this type. This particular inverter would require modi-
fication of the toroidal core transformer to permit a large voltage drop across the
series resistor, R p .

BIBLIOGRAPHY

Bright, Pittman, and Royer: Transistors as "On-Off" Switches in Saturable-core Circuits,


Elec. Mfg., December, 1954.
Card, W. H.: Transistor-oscillator Induction-motor Drive, Communs. and Electronics, no. 38,
pp. 531-535, September, 1958.
Feth, G. C.: Core-reset Functions in Magnetic-amplifier Analysis, parts I and II, Communs.
and Electronics, no. 38, pp. 503-519, September, 1958.
Hurley, R. B.: "Junction Transistor Electronics," pp. 189-320, John Wiley & Sons, Inc., New
York,1958.
Jensen, J. L.: An Improved Square-wave Oscillator Circuit, IRE Trans., voL CT-4, pp. 276-
279, September, 1957.
Lohr, J. F.: Transistorized Static Inverter Design, Electronic Design, pp. 58-61, April 16, 1958.
Lowry, H. R.: Transistorized Regulated Power Supplies, parts I and II, Electronic Design,
voL 4, pp. 38-41, February 15, 1956; pp. 32-35, March 1, 1956.
Middlebook, R. D.: Design of Transistor Regulated Power Supplies, Proc. IRE, voL 45,
pp. 1502-1509, November, 1957.
462 Switching-mode Designs

Sherr, S., and P. M. Levey: Design Considerations for Semiconductor-regulated Power


Supplies, Electronic Design, vol. 4, pp. 22-24, July 15, 1956.
Smyth, R. R., and M. G. Shorr: Transistorized Power Sources for D-C to A-C and D-C to
D-C Conversion, Electronic Design, November 15, 1956.
Swartz, Seymour: "Selected Semiconductor Circuits Handbook," part 9, pp. 1-46, John
Wiley & Sons, Inc., New York, 1960.
Thomas, Donald R.: Transistorized Power Converters, Device-Circuit Notes, Semiconductor-
components Division, file A-59-l, Texas Instruments, Inc., Dallas.
Uchrin, G. C., and W. O. Taylor: A New Self-excited Square Wave Oscillator, Proc. IRE,
vol. 43, p. 99, January, 1955.
Wasserman, Reuben: Self-excited Transistor D-C-A-C Converter Design, Electronic Design,
pp. 78-81, April 13, 1960.
36
Switching-mode Voltage Regulators

The primary advantage of a switching regulator over a conventional regulator is


that relatively low power is dissipated in the series regulating transistor. Conse-
quently, the full current capabilities of the transistor can be used with minor
emphasis given to its thermal characteristics.
A comparison of the power dissipation in the series regulating transistor of con-
ventional and switching regulators is given in the following example: A 2Nl907 is
used as the series regulating transistor in both regulators, and the regulated output
is 20 volts d-c at 5 amp with an input of 45 volts d-c. The 2Nl907 collector dissi-
pation is 125 watts in the conventional regulator, but it is only 8 watts (or less) in
the switching regulator. Complete calculations for determining the collector dissi-
pation in the 2Nl907 switching transistor are given in Sec. 36.5.
The advantages of the switching regulator over conventional series regulators
may be summarized as follows:
1. Higher efficiency, hence lower power dissipation and smaller physical size.
2. Use of fewer, more economical transistors.
3. High power-output capabilities.

36.1. CIRCUIT ANALYSIS

A block diagram of a switching regulator is shown in Fig. 36.1. The regulated


output voltage is applied to the d-c controlled multivibrator which generates pulses
whose duty cycle depends upon the difference in voltage between the d-c reference
and the regulated output. The multivibrator pulses are applied to a switching
driver which operates the series transistor switch. A low-pass filter is used to
integrate the pulses at the output of the series switch. Ripple voltage from the
unregulated d-c supply is filtered by modulation of the switching duty cycle; how-
ever, the switching frequency must be much greater than the ripple frequency.

36.2. D-C CONTROLLED MULTIVIBRATOR

One possible circuit for the basic multivibrator is shown in Fig. 36.2. The d-c
reference voltage, V(refh is applied to the base of Q2 through a voltage divider. The
regulated output voltage is applied to the base of Q1. Transistors Q1 and Q2 are
463
464 Switching-mode Designs

Unregulated
d-csupply

doc Gontrolled
asymmetrical
multivibrator

Fig. 36.1. Block diagram of switching regulator.

connected as a differential amplifier, which drives another differential amplifier


composed of Q5 and Q6- The collector currents of Q5 and Q6 provide the charging
currents for C1 and C 2, respectively. The duty cycle depends upon 105 and 106 ,
and will change when the voltage at the base of Ql is changed. Degeneration is
provided in the emitter circuits of Q5 and Q6 to make 105 and 106 less dependent
on the hFE of each transistor.
The waveforms for the case in which the collector currents of Q5 and Q6 are equal
are shown in Fig. 36.3_ The period is
(1)

Fig. 36.2. D-c controlled asymmetrical multivibrator.


Switching-mode Voltage Regulators 465

veet,..---...,

Or---------------~~------------~

Fig. 36.3. Multivibrator


voltage waveform. - Vee t ' - - - - -

Neglecting the rise and fall times of V OE4 , the duty cycle is
11
'7" =----- (2)
11 + t2
The relationship between charging current and capacitance of the timing circuit
may be determined from the equation

(3)

where Vc = voltage across the capacitor, and ic = charging current. The collector
currents of both Q5 and Q6 are assumed to be reasonably constant during the
positive charging periods of C1 and C2 • Therefore, Eq. (3) may be written for these
periods as follows:
11 = V OOC1 (4)
105

and 12 = VOOC2 (5)


106
where 105 and 106 are the collector currents of Q5 and Q6, respectively, and Voo =
supply voltage. When a load, R L, is connected to the collector of Q4, Voo in Eq.
(5) must be replaced by Voo[Rd(R6 + RL)]. The equation which shows how a
466 Switching-mode Designs

change in T is related to the difference between regulated output voltage, V(out),


and reference voltage, ~ret), is derived as follows:
VEl = V(out)K1 (6)
and V B2 = V(ref) K2 (7)
where K1 and K2 are the voltage-divider ratios in the base circuits of Q1 and Q2>
respectively. Since Q1 and Q2 are connected as a differential amplifier,
(8)
whereA = voltage gain of the differential amplifier. For a symmetrical differential
amplifier,
~V9 = -~V8 (9)

~V9 _ ~(VEl - V B2 )A
Thus, - 2 (10)

and ~V8 - -~(VEl - V B2 )A (11)


- 2
If R 10 and Rn are equal, and the change in voltage across each is large compared
to ~VBE5 and ~VBE6, then
(12)
where 10 is a constant. Thus,
M _ ~(VB1 - VB2 )A
05 - 2Rll (13)

and ~106 = -~(VEl - V B2 )A (14)


2RlO

106 106
T- -- (15)
- 105 + 106 - 10

Thus, ~T = ~106 = -~(V(out)K1 - V(ref)K2 )A


(16)
10 210RlO

The equations which show how frequency varies with duty cycle are given as
follows:

T = t1 + t2 = V OOC1 (1~5 + 1~6) (17)

and / = 1.. = 1051 06 (18)


T VOOC1 (I05 + 106 )
Substituting Eqs. (12) and (15) into (18),
(T - T2)10
/= --O-..._~ (19)
VOOC1
Switching-mode Voltage Regulators 467

'V\J\,
R7R p
R7+ R p 1
(a) Charging circuits during ON time of Q4
f'

(b) Charging circuits during OFF time of Q4

....--------
IcsRp
-----------
....... ......
O~------_7~------~~--------~

tl =OFF time of Q4
t z = OFF time of Qa

(c) VoltageacrossCp

Fig. 36.4. Approximate equivalent charging circuits of Cpo

As an example of the change injfor a given change in duty cycle, assume that the
frequency at which T = 0.5 is /0. If T is changed to 0.15 or 0.85, then
j = 0.51/0
To decrease the change in frequency when low or high duty cycles are approached,
C1 can be replaced by a parallel combination of a resistor, R p, and a capacitor, Cpo
The value of Rp is arbitrary; however, good frequency stability has been obtained
by choosing Rp such that the sum of R7 and Rp can saturate Q4 when both IC5
and IC6 are zero. The value of Cp can be obtained by referring to the equivalent
circuits in Fig. 36.4.

36.3. DRIVER CIRCUIT

The driver circuit may be analyzed by referring to Fig. 36.5. The driver transis-
tors Q7 and Q8 are operated as switches, and are saturated when driven with the
positive pulses from the multivibrator. The value of R18 must be chosen such that
Q9 will be saturated when E(in) is minimum. The maximum collector current of
r--------,
r--D-----------------------l
I I
I
I
Series switch I
I
Filter
----,:
r- Load
---,
I

I "A" D4 Q9 I I I I
I II I I I
a-c
~~··~~I-
I II
: 'op"' II i I
I
I
I
I
I I I
I I I I I I :
IL __________ , I
JI IL ____ _ J
~
IL I
_ _ _ _ _ _ _ ...l
r--------, I I
~
c- ~_~~~ateds~pl~ _____ ~
Ol
i ["A" "B" : r------~-- --"1
I R 20 R21 : I
I ~ I I I
iI SW1 I
I
I I
I I
I i I I
I I
I
Multivibrator
L_~~t ____ J
~ : I I
I I
Qs

I
II _ Da

I IL _Driver
_____ ~
- ___ __
I

::~-:
I
I ,
I
I II B D
1
I
I I
I I ~ I
IL _ _ _ _ _ _ _ doc
__ _ _ _ _ _ _ _ _~
_ _ _multivibrator
controlled _______________ _ IL~ference
_ _ _ -II

Parts List
Resistors* Kilohms Resistors* Kilohms Resistors* Kilohms Transistors CapaCitors It! Diodes and rectifiers
Rp 4.7 Rs, R9 10 R17 270 ohms Ql, Q2, Q3, Q4 2N1304 Cp 0.02 Dl IN751
Rl 1.8 R 10, Rll 2.2 R 18 110 ohms, 20 watts Q5, Q6 2N1305 C2 0.001 D2 IN2499
R2, R3 3.3 R12 4.7 R 19 33 ohms Q7 2N1302 C3 1,000 D3 IN2069
R4 :.0 R 1a 47 R20 200 ohms, 10 watts Qs 2NI720 D4 INlS81
R5 1.0 R14 680 ohms R21 82 ohms, 2 watts Q9 2N1907 D5 XR-78
Rs 470 ohms R 15 2.0 Inductor
R7 2.2 R 16 680 ohms Ll 10 mh
* All resistors ±5%, 'h watt, unless otherwise specified.
Fig. 36.5. lOO-watt switching regulator.
Switching-mode Voltage Regulators 469

Qs occurs when E(in) is maximum; therefore, the collector current rating of Qs must
be determined for this condition. The value of R 15 must be chosen such that Q7
and Qs are saturated when the collector current of Qs is maximum. The collector-
to-emitter voltage rating of Qs must be greater than the maximum value of E(in).
The approximate equation for the collector power dissipation in the! driver tran-
sistor Qs can be determined by assuming the current and voltage waveforms are
as shown in Fig. 36.6. When the transistor is OFF, the energy, f, dissipated is
(20)
During the ON time,
(21)

Neglecting IC(off), the collector current and collector-to-emitter voltage during the
switching interval may be written as follows:
. I c t- (22)
1C= rsw
t
and V CE = V CE(off) - [VCE(off) - V CE(.at)] -r
SW
(23)

The energy dissipated during one switching interval is

fC3 =J(Tow
o iCVCE dt (24)

Mter integration and grouping of terms, Eq. (24) becomes

fC3 = -Tsw1c
6 - (VCE(off) + 2VCE(.at») (25)

V CE(off)

I
I
VCE(sat) I
o I I

~Tswl--- TON ----jTsw/---- TOFF ~


Fig. 36.6. Idealized switching waveforms for Qs.
470 Switching-mode Designs

Thus, the total collector power dissipation is


Tsw Ic
PC8 = -r
TOFF TON
VCE(ofn/C(otn + T VCE(satlC + T 3 (VCE(off) + 2VCE(sat») (26)

where T = period of waveform


TON = ON time of transistor
TOFF = OFF time of transistor
Tsw = switching interval
VCE(sat) = collector-to-emitter saturation voltage
VCE(off) = collector-to-emitter voltage during OFF time
Ic = collector current during ON time
IC(off) = collector current during OFF time

36.4. SERIES SWITCHING CIRCUIT

Assuming that the power dissipation in Q9 (Fig. 36.5) is low, the maximum col-
lector current rating may be utilized by choosing Ll such that the collector current
is reasonably constant during the conduction time of Q9. The voltage across Ll
during this time is
(27)

where E(in) = d-c input voltage


V(out) = regulated output voltage
100 = collector current of Q9 during ON time

The ripple voltage across C3 is much less than VL1 , assuming


1
C3 ~2"-L
W 1
(28)

where w = switching frequency in radians per second. Thus,


dIoo =K (29)
dt
during the ON time of Q9, and
L _ ilt(E(in) - V(out»)
1 - ilIoo (30)

where ilt = TON = ON time of Q9. Equation (30) may be used to determine Ll
such that MC9 ~ 100 during the ON time. Therefore,
(31)
where h is the direct load current. Thus, the maximum load current a switching
regulator can deliver is approximately equal to the maximum collector current
rating of the series switching transistor.
The equation that relates duty cycle to ~e input and output voltages of the
Switching-mode Voltage Regulators 471

regulator is derived as follows: Assume that Eq. (30) is satisfied such that /)J09 ~
109 during TON. Neglecting the circuit losses, the average power, P, transferred
from the doc supply to the load is
P = E(inV097" (32)
where 7" = switching duty cycle. The load power may also be expressed by the
equation
J5 = h~out) (33)
Substituting Eqs. (31) and (33) into (32) yields
7" = V(out) (34)
E(in)

where E(in) > V(out)

The collector dissipation for the series switching transistor Q9 can be determined
by referring to the waveforms shown in Fig. 36.7.
Dissipations during the OFF and ON times are given by Eqs. (20) and (21),
respectively. During the switching interval, D5 and Ll will cause the collector
voltage to switch much faster than the collector current. Thus, the approximate
equation for VCE during this interval is
V CE - V CE(off) (35)
Neglecting IC(off), the collector current during the switching interval is
.
lc= c
I t (36)
T- sw
The energy dissipated during the switching interval is
(Tsw
fC3 = Jo iCVCE dt (37)

IC(off)
o~F=========~-L-----------+----~

I I
I I I I
I I I I
VCE(off)
I I I I
I I I I
I I I I
I I I I
I
I
I
I
~ V CE(sat) I

Fig. 36.7. Idealized switching waveforms for Q9.


472 Switching-mode Designs

After integration, Eq. (37) becomes

(38)

Thus, the total collector power dissipation is


ToF'F' TON Tsw
Peg = -----;y- VOE(of{,IO(off) + T VOE(sat,Io + T VOE(off)Io (39)

During the OFF time of Q9, D4 and R 19 minimize the collector leakage current.
The diode D5 transfers the stored energy in Ll to the load during this time, and
must have a peak current rating equal to the maximum collector current of Q9.
Since D5 conducts when Q9 is OFF, the collector-to-emitter voltage rating of Q9
must be greater than the maximum value of input voltage, E(in)'
Other Design Considerations. Temperature Compensation. Since differential
amplifiers are used to control the multivibrator, the regulator will exhibit good
temperature stability if the avalanche diode Dl has a temperature coefficient near
zero, and the resistors R 1 , R 2 , R 4 , and R5 have temperature coefficients that are
nearly equal. The value of Dl and the corresponding current necessary to ap-
proach a zero temperature coefficient can be determined by referring to the data
sheets for Texas Instruments voltage-regulator diodes.
Short-circuit Protection. The regulator will exhibit short-circuit protection if
Q9 is turned OFF immediately after a short, and remains OFF until the short is
removed. This may be accomplished by removing the multivibrator supply volt-
age during the short-circuit condition. The starting resistor R 20 is connected to
point A through a start button SW1 so that it is normally disconnected from the
circuit except during starting of the regulator. When a short occurs, the multi-
vibrator supply voltage will go to zero, and remain there until the short is removed
and the start button is pushed.
Transient Suppression. A positive-voltage transient will appear at the output of
the regulator when the load current is suddenly decreased, and will be maximum
when the load current is switched from full to no load. Neglecting the losses in
the output filter and the current in R 21 , the maximum voltage that will appear at
the output is

VO(max) = V:2
(out)
+ L1I't,max)
C (40)
3

Thus, the LtlC3 ratio should be minimized within practical limits to reduce the
output-voltage transient.
A low inductance-to-capacitance ratio should also be chosen for the filter of the
unregulated supply in Fig. 36.5 to reduce the supply-voltage transient resulting
from a sudden change in load current. If the ratio is not low enough, the output
of the unregulated supply can momentarily drop below the regulated voltage when
the load current is suddenly increased, and the regulator may begin oscillating
with the unregulated supply.
To prevent an output-voltage transient from occurring when starting the regu-
lator, SW1 should be closed before the a-c input voltage is applied to the rectifying
Switching-mode Voltage Regulators 473

20.02
TA=25°C
I L =5 amp
20.01

19.99

19.98 L..-_ _ _ _"'--_ _ _ _...J-_ _ _ _--'-_ _ _ _--'


30 35 40 45 50
E(in)' volts

Fig. 36.S. Output voltage vs. d-c input voltage.

circuit. Assuming that the response time of the regulator is short compared to
the unregulated supply filter, regulation will begin before the output of the unregu-
lated supply is appreciably larger than the regulated voltage.

36.5. DESIGN EXAMPLE

A 100-watt switching regulator has been built, using the circuit and list of
recommended components in Fig. 36.5, to meet the following specifications:
V(out) = 20 volts.
h = 0 to 5 amp.
E(in) = 40 + 10 volts.
Input frequency to the unregulated supply = 60 cps.
Operating temperature = -25 to 50°C.
Ro < 0.02 ohms.
Overall voltage regulation < +0.2 volt.
Circuit Performance. Series-switch Power Dissipation. The maximum collec-
tor dissipation in the series switching transistor Q9 in Fig. 36.5 occurs when the

20.02

E(in) =40 volts


20.01
TA 25°C
£]
"0
>
20.00
~

';:;.~
19.99

19.98
0 2 3 4 5
Load cu'rrent, amp

Fig. 36.9. Output voltage vs. load current.


474 Switching-mode Designs
20.20

IL =5 amp
20.10 ~ E(in)=40 volts
.l!l
g
~ 20.00
;:..~
------------------
19.90

19.80 L--_....L.-_ _L......_...L._---'_ _....L-_---l._ _...l...-_--1


-30 -20 -10 o 10 20 30 40 50
Temperature, °C
Fig. 36.10. Output voltage vs. temperature.

load current and a-c input voltage to the rectifying circuit are maximum. The
values used in Eq. (39) for these conditions are as follows:
T = 100 p,sec TON = 44 p,sec TOFF = 52 p,sec Tsw = 2 p,sec
VOE(sat) = 1 volt VOE(of{) = 45 volts
IO(of{) = lOBO = 50 ma 10= 5 amp
Thus, Pog = 1.17 + 2.20 + 4.50 = 7.87 watts
The lO-kc switching frequency will result in more power dissipation than a lower
frequency, as indicated by the third term of Eq. (39). This frequency was chosen,
however, to minimize the size of the output filter.
Regulation Characteristics. Typical regulation curves for the switching regu-
lator are shown in Figs. 36.8 to 36.10.
The average values for regulation factor F, output resistance R o, and regulation
temperature coefficient KT are 0.0007,0.002 ohm, and 0.0011 volt/CO, respectively.
From these values, the regulator performance can be determined from the regula-
tion equation:
~ V(out) = F !J..E(in) + Ro ~h + KT ~T
The values of ~E(in), ~h, and ~T are specified as 20 volts, 5 amp, and 75
Co, respectively. Thus,
~ V(out) = 0.11 volt
37
Switching-mode Motor Control

37.1. ADVANTAGES OF SWITCHING-MODE CONTROL

A series d-c motor is used in applications where variable-speed operation and


high starting torque are required; various techniques are available for speed con-
trol of a d-c motor in such applications. Each of these techniques is based on a
common principle: regulating the speed of the motor by controlling the input
power to the motor.
The most common method of controlling the speed of a series motor is to use
a variable resistor inserted in series with the motor. This method is particularly
applicable when the available power supply consists of a constant-voltage source,
such as a storage battery. The power supplied is divided between the motor and
the series resistor, with the resulting disadvantage that the system is inefficient
when the power loss in the rheostat is high. Another disadvantage is that the po-
tential drop across the resistance will cause poor speed regulation with respect to
varying loads.
A more desirable method of speed control involves the use of a periodically
operated switch, inserted in place of the series rheostat. The continual opening
and closing of the switch regulates the input to the motor; variation of the time
duration of the ON and OFF positions of the switch provides a control of the speed
of the motor. Figure 37.1 shows the time relationship between the OFF and ON
positions of such a switch for various settings of motor speed. One of the main
advantages of this system is an efficient utilization of the available power; the
switch has very high impedance when open and very low impedance when closed.
The speed regulation of a system using a switch as a speed-control element is
an improvement over that of a system using a series resistance control, since po-
tential drop across the switch varies negligibly with load current.

37.2. CIRCUIT EXAMPLE


Figure 37.2 is a block diagram of a transistorized switching circuit. This sys-
tem was designed to control the speed of a 20-amp 24-volt d-c series motor with
peak starting currents up to 100 amp. The power-switch stage of the circuit con-
475
476 Switching-mode Designs
Power ON . - - - - - r - - r - - r - -
I Maximum
I
I speed
powerOFF~--~:--~--~----~~
I I I Time

ON Hririr High
speed
OFFULU

ONHririr
I I I
I I I

Medium

OFF~ I I I
speed

I I I

ON~ Slow

OFF~ speed

-1 r- 1/100 sec

Figure 37.1

troIs the power delivered to the motor, while the driver stage serves as a current
amplifier, furnishing sufficient current to drive the power switch. The automatic
drive-control stage controls the power level of the driver stage under varying load
conditions, so that a high system efficiency can be maintained. The required ON-
OFF cycling operation of the driver stage and the duty cycle of the power switch
are controlled by a variable resistor in the multivibrator. The multivibrator also
establishes the period of the switching cycle.
Figure 37.3 is a complete schematic diagram of the speed-control system. A
rectifier and a capacitor are placed in parallel across the motor, to minimize the
possibility of damage to the power transistors when they switch off the heavily in-
ductive motor load. Without the rectifier and the capacitor a high voltage would

Automatic
drive
control

Fig. 37.2. Block diagram.


I--------------~ r - - - - - - - . r-------,
I I
r-------------------,
+24v
d·c
5w 1K
50Q
I
I
Qll
2N1373
Ql0
2N1038
Q
2N1h3
IiI

I
I
I
I
...I
I
Ir_...J I
I : L_£o~~~~~ _________ I __ __l
I
50 K I L--------------l
I 1K 478Q
Speed I
control I
element I
I
I
I
I
..,
I I
I + 16 Mf I
:::100vl

500Q 270Q 30Q


I
I 20Q ;X;
L!)
1- d·c I
I
5w I 20w ..... I
I z
.....
J>. I I
:::: I I I
I I
L Oscillator and speed control
_ _ _ _ _ _ _ _ _ _ _ _ _ --.J ! IL _Driver
___ !
~
Automatic
IL _ _ _ _ _ _ _ ____ drive
__ control
_ _ _ _ _ _ _ _ ...1 IL _1_ _Motor
_ _ _ __ ...I

Fig. 37.3. Complete schematic diagram of speed-control system.


478 Switching-mode Designs
r--------------, r-----------
1 +Mv I
Variable r----,I doc I
pulse I I 1 I
width
input I ~,I~I----_4~--_+------~I~~--~~--~--~
I 1
1 I 1
lflrl Q I I
i2N5511 1
I I Q9
I : 2N511
I 1

:
I
1
1
------,
I I I
I RI I 1
12012 I I
I I I
I I I
I I I
I 1 I
I I I
1 I
I I _ IL _________
Load I
L.. _ _ _ .J L ____________ ---' J
Driver Automatic drive control Motor

Fig. 37.4. Automatic drive-control circuit.

appear across the power-switch stage during turn-off, because of the reverse volt-
age induced in the motor windings when the current is interrupted_
The power-switch stage of the circuit consists of four parallel 2N 514 transistors.
Four transistors were necessary because the current required by the motor in a
starting or stalled condition approaches 100 amp; 2N514 transistors can carry an
absolute maximum collector current of 25 amp_ Special precautions must be
taken to assure an equal division of current among the four power-switch transis-
tors. Emitter resistors provide compensation for variations in VOE(sat)' h pE, and
forward transfer admittance (YPE)- The resistor values are a compromise between
efficiency and current distribution of the paralleled transistors. Increasing these
values reduces the circuit efficiency, but provides better equalization of collector
currents.
A factor to be considered when transistors are used in switching circuits is that
the transistors must remain in a saturated state while handling large currents, in
order to keep the transistor power dissipation to a minimum. If a saturated con-
dition is to be maintained over a wide range of collector current variations, the
base current must be sufficiently large to accommodate the largest anticipated
value of 10 in conjunction with the lowest value of hpE- If IB is too small to keep
the transistor in a saturated state, the resulting increase in power dissipation could
exceed the transistor's power rating. However, if IB is maintained at a value cor-
responding to the largest anticipated value of IO(ma:c/hPE(min), the driver stage is
inefficient when only moderate values of 10 are required (normal operation of the
motor).
Switching-mode Motor Control 479

Slow speed
20 amp
Collector current
10 amp

o
v V
Collector-to-emitter
voltage 20 volts

o
Sweep, 2 msec/dlv -

Medium speed
20 amp
Collector current

Collector -to-em itter


10 amp

o
/ ' i-"""" ~ -
voltage 20 volts

o
Sweep,2msec/dlv -

High speed
20 amp
Collector current

Collector-to-emitter
voltage
10 amp

o
20 volts -
- -
o
Sweep, 2 msec/dlv -

Figure 37.5

Provision should be made for automatic variation in IB when Ic is varied. This


is accomplished in the speed-control system by an automatic drive-control circuit
(see Fig. 37.4). The automatic drive-control stage, represented by Q6, Q7, Qs, and
Qg, senses any difference in VCE of Q6 and the power-switch transistors. If the
paralleled 2N5l4 transistors in the power-switch stage are not in saturation during
any portion of the ON cycle of operation, the base voltage of Q7 will become
negative with respect to its emitter voltage, and the transistors Qs and Qg will be-
gin to conduct. This conduction will cause more base current to flow into the
power-switch stage of the circuit, driving that stage back into saturation.

Motor stalled
20 amp
Collector current
10 amp / V
o
Collector-to-emitter
voltage 20 volts

o
Sweep, 2msec/dlv _ _

Figure 37.6
480 Switching-mode Designs

600

~
- Transistor switch
500 l"-
--- Rheostat f:)' ~~~-
e§' ~ ~
. . .' . .rr-/,'&
. _/s
~I I
1.....'?1/~
~
400
' / I' rr'-
/ .....

"
VI
::::OJ A I ,- I

,,~
I
~
...: // I ,<~~-
I.r/ ,', ,,,<0
::s 300
....<Il0
/00
~

~~~ / , /
0
a.
200
..4 ~C5
f:)'
,"
/',,/

100
// /
/ ;'
/;

Fig. 37.7. Control ele-


ment: power out VS.
a 100 200 300 400 500 600 700 power in (speed = con-
Power in, watts stant).

Figure 37.5 shows oscilloscope waveforms of the collector voltage and current
for the power-switch stage of the circuit under various conditions of motor speed
at an intermediate load. Figure 37.6 represents the collector current and voltage
waveforms of a single transistor in the power switch under a stalled condition of
motor operation, with the automatic drive-control stage removed. The waveforms
shown in Fig. 37.6 indicate that the instantaneous power dissipated in the transis-
tor at the end of the ON cycle is 240 watts. Automatic drive control is a necessity
if this high dissipation is to be avoided.
Switching action of the system is provided by a multivibrator (Ql0 and Qll),
which holds the driver stage either in full saturation or completely OFF. Thus,
the driver stage of the system is operated at a low power-dissipation level.
The circuit component which controls the ratio of OFF and ON time for the
power switch is the 50-kilohm variable resistor in the multivibrator. The extreme
settings of the variable resistor will cause the switching action to cease, and the
power switch will be either full ON or OFF. Intermediate settings will establish
the pulse width and, therefore, the percentage of ON time for the power switch.
Operating frequency of the multivibrator is approximately 100 cps.
Figure 37.7 is a comparison of power out vs. power in for three different speed
settings of the control element. These curves indicate that the transistorized
switch is much more efficient than the series rheostat for speed control.
The circuit was designed to function at 24 volts, and to supply a current which
approached 100 amp. With minor modifications, it is flexible enough to work in
applications requiring lower or higher power. Current-switching capacity of the
circuit is limited only by the number of transistors paralleled in the power-switch
stage and the maximum current-carrying capacity of each of the transistors.
38
Switching-mode Servo Amplifier

A common servo amplifier consists of a number of cascaded linear amplifier


stages with a class B push-pull output stage supplying power to the control wind-
ing of a two-phase servo motor. Better efficiency can be achieved by replacing
such an amplifier with one which operates in a switching mode.
One approach to a switching amplifier is to employ pulse-duration modulation
(PDM). With this method, the input signal is used to control the pulse duration
of a relatively constant repetition-rate pulse signal. The repetition rate of the
pulse signal is much higher than the signal frequency, permitting the PDM signal
to be ffitered at the output, and thereby recovering the amplifier signal frequency.
The amount of output power is a function of the power-switching capabilities of
the output transistors and the duty cycle of the modulated pulse train.
A practical switching servo amplifier is shown in block form in Fig. 38.1, with
waveshapes shown in Fig. 38.2. The actual circuit is shown in Fig. 38.3. The in-
put signal controls the current sources in the free-running multivibrator, thus
Power
supply

Modulated pulse
waveshape Fig. 38.2 (c»

Error
Astable
signal
(free-running) I
input
multivibrator I
I
'V Variable duty
Refer~ce §_
V0
400 cps cycle
phase
'" Servo
motor

Figure 38.1

481
482 Switching-mode Designs

(a) Unmodulated pulse train (10 kc)

(b) Modulating signal (400 cps)

(c) Modulated pulse train (not to scale)

Figure 38.2

achieving PDM. The driver and power complementary transistor switches com-
plete the circuit.
This method, while particularly useful for single-frequency applications, can also
be used for varying-frequency input signals. However, this approach makes the
pulse repetition rate somewhat dependent on the duty cycle. It may therefore be
difficult to achieve a large separation between the pulse-train repetition rate and a
varying-frequency signal.
The pulse repetition rate for this circuit is approximately lO kc; this was a com-
promise between the desirable high frequency dictated by filter considerations and
the low frequency required by switching considerations.
+30v d-c

D~
1N759A

I
I
I
I

+ Referen~__ O_
slgnab,..3
Ml

C7
0.15 J.tf

For operation above 30° C, QI, Q8, Qu, QI2 and QJ5
Parts List Tl must be placed in heat sinks.

~
R J should be adjusted to bring the collector of QJ to + 15 volts.
Resistors Kilohms
Rl 130 ohms 400cps
Capacitors pI Inductor
1>- R 2, R, 2 error signal
0> C\ 16 Ll 3.2 mh
W
R 4, R5, RIO, Rll I C2, C:l 0.003
R 6, Rg 3 Miscellaneous
Diodes C4 0.1
1.5 MI John Oster Manufacturing
R 7 , R8 IN751 Cs, C 7 0.15
DI Co. type 11-5101-03
R 12, R 13 , RI4 270 ohms C6 5
D2 G130
R I5 5
D 3 , Dg IN645
Transistors D4 IN759A
QI, Qs, Q15 2N 1131 D 5 , D 7, Ds, D IO IN914
Q2, Q4, Qs, Q7 2N929 D6 IN747 Transformer
Q3, Q6, QI0, Q13 2N24 II D ll , D 12 , D 13 , DI4 IN916 TI Step-down 117-12.6-volt
Q9, Q14 2N743
Q11, Q12 2N24 10 Figure 38.3
39
Digital Servo System

The digital servo system described here demonstrates the application of transis-
torized circuitry to machine tool control, air-navigation computing systems, and
radar. A simple and highly accurate method of positioning a mechanical object,
using numerical input information, is to employ a digital servomechanism. Digital
systems (often referred to as sampled data control systems) are gaining wide
acceptance.

39.1. ANALOG VS. DIGITAL SERVOMECHANISMS

A digital servo employs digital means to compare input and output. The
difference between the two numbers is a number which must be converted to a form
suitable for driving the mechanical element until the digital error is reduced to zero.
The digital information pertaining to the output position is obtained from some
form of encoder.
In an analog system, a voltage proportional to the desired input quantity is com-
pared with a voltage obtained from the output transducer, which is typically a
potentiometer or a synchro. Thus, if the input information is obtained from a
punched card or tape reader, intermediate conversion is required to change the input
signal to analog form.
A good linearity for a servo potentiometer is 0.01 %; in other words, the shaft can
be positioned to an accuracy of 2 minutes of arc. A synchro can position a shaft
to an accuracy of better than 1 minute of arc. A 19-bit shaft encoder can position
a shaft within 2 seconds of the desired position. Thus, the accuracy of a digital
system is potentially much greater than that of an analog system.
Of course, when dealing with this magnitude of error, noise becomes of paramount
importance because of the low level of the error signal. In an analog system the
error signal, being so small, usually picks up some 60-cps noise as well as noise due
to the transducer, making it difficult to differentiate the error signal from the noise.
The standard technique for overcoming this is to shape the frequency response
suitably at the expense of transient response. In the digital system, only two levels
of error signal can occur-one or zero (or typically, 20 or 0 volts).
484
Digital Servo System 485
39.2. DESCRIPTION OF SYSTEM

A block diagram of the system is shown in Fig. 39.1. The binary input consists
of a series of switches, each switch representing a particular significant digit. The
digital shaft encoder is a Datex C711 type, coded in Gray code. The output from
the encoder is converted into natural binary code and compared with the binary
input. The difference between input and output numbers results in the digital error
signal, which is converted into an analog signal. This is chopped by the modulator
into a phase-sensitive 60-cps voltage, the phase depending on which way the motor
has to turn in order to reduce the digital error. The modulator output is amplified
to drive a two-phase 3-watt Diehl motor (type FPE-25L-107-13). The tachometer
is mounted integrally with the motor and is used to damp the system. The speed
reducer is a 25: 1 precision gear train made by Motion Control Incorporated.

39.3. SHAFT-POSITION ENCODER

The shaft encoder is of the disk type, shown pictorially in Fig. 39.2. The dark
areas shown are connected through the disk to a face plate on the back of the disk.
A voltage is applied to the back face by a brush, and the digital output is obtained
from the fixed brushes Bo to B 3 • The disk is mounted on a shaft so that a digital
output ranging from 0000 to 1111, corresponding to the shaft position, is obtained.
The disk shown is coded in binary code, but most practical disks are coded in a
reflected binary code such as Gray code. The reason for this is the large angular

Binary input

Digital Digital·to·analog
Modulator
comparator converter

Gray-binary
converter
~ Tachometer j Servo
amplifier

t
Coded disk digital
shaft encoder
I Speed I Motor
reducer
L J
Fig. 39.1. Block diagram of digital servo system.
486 Switching-mode Designs

Fixed brushes

Coded disk Conducting surfaces


cou pled to a shaft connected to a face
plate on back of disk

Fig. 39.2. Binary-coded disk.

error that can occur if there is any brush misalignment. Consider the shaft in
position 1111, and assume that brush B3 is advanced one sector. It will then read
0111, which corresponds to a position 180 or eight sectors, away. The reason
0
,

such a large error can occur, using binary code, is that between successive numbers
more than one digit can change.
In the Gray code, only one digit changes between successive numbers. A com-
parison of binary and Gray codes is shown in Fig. 39.3. Considering a Gray-coded
disk in position 15, and brush B3 advanced one sector, the output is now 0000, which
corresponds to position 0, or just one sector error.
The encoder used had 10 bits resolution; thus the servo was capable of positioning
the shaft to an accuracy of 360 /2 10 = 0.352
0
Only 8 bits were used for this
0

demonstration because backlash in the gear train made the stabilization of the
system difficult using 10 bits.
Digital Servo System 487

39.4. GRAY-TO-BINARY CONVERTER

Figure 39.4 gives the rules for converting Gray code to binary code, and the form
of the conversion logic. The truth table was derived from the rules, and the
Boolean expression for the logic obtained from it. NOR logic was used because
this promised the simplest and cheapest system. Consequently, the Boolean expres-
sion was converted from a sum of products to a product of sums in order to obtain
the least number of NOR elements to perform the logic. The basic NOR element
used, and the resultant NOR logic circuit for one digit, is shown in Fig. 39.5.

39.5. BINARY COMPARATOR

The binary comparator compares the binary input with the binary number
corresponding to the output position. It consists of a number of modules, one for
each digit to be compared. Each module compares an input digit with the corre-
sponding digit from the Gray-to-binary converter.
When the input digits are the same, the two outputs from each module are "one."
In cases of inequality, one output will be a "one" and the other "zero," depending
on which way the motor has to turn. This is illustrated in Fig. 39.6 by the truth
table from which the binary comparator module is derived. The number of NOR
elements used could be reduced if the output were zero when equality of inputs
existed. However, this corresponds to the output transistors being in the saturated
condition, and therefore the output voltages to the DA converter would vary con-
siderably from device to device, causing an error output voltage from the modulator
at null. If the outputs are "one" when equality exists, the output transistors are

Decimal Binary Gray

0 0000 0000
1 0001 0001
2 0010 o0 1 1
3 0011 0010
4 0100 o1 1 0
5 0101 o1 1 1
6 o1 1 0 o1 0 1
7 0111 0100
8 1000 1100
9 1 001 11 01
10 1010 11 11
11 101 1 1 110
12 1 100 1010
Fig. 39.3. Comparison
13 11 0 1 101 1
of Gray and binary code
representations of deci- 14 1110 1001
mal digits 0 to 15. 15 11 11 1000
488 Switching. mode Designs

Gray code number - - - " ~ 1 A

Converted binarYJ,number
.. ~ 0 B

Rules:
(1) Most significant digit
remains unchanged
(2) Gray digit complemented
if preceding converted
binary digit isa " 1 " - - - - '
(3) Binary digit is the same as
Gray digit if preceding
binary digit is a "0" _ _---J

Form of conversion logic:


Gray code input

Binary code output

Truth table
for logic:
o o o
o 1 1
1 o 1
1 1 o

Fig. 39.4. Conversion of Gray code to binary.

cutoff, and the input voltages to the DA converter are equal, regardless of device
characteristics.

39.6. DIGITAL·TO·ANALOG CONVERTER AND MODULATOR

The digital-to-analog converter converts the digital output of the binary com-
parator into two analog currents, the magnitude of each depending on which way
the motor has to turn. The modulator subtracts these two currents, giving a phase-
sensitive 60-cps square-wave output signal. The circuit is shown in Fig. 39.7. The
DA converter consists of weighted resistors connected from each output of the
binary comparator to the modulator, the weight of the resistor depending on the
Digital Servo System 489

+20v
Basic NOR
element 3.92 K

::>.-1------0 C=A' B'


AO--JV'lv--~-r~

120 K

-20v

Gray
input Binary
An_mO---~~--~ output
11---OB n _ m

Fig. 39.5. Gray-to-binary converter module.

C n-m= Binary output

D n- m
Truth table:
Cn- m B n- m Dn- m E n- m
0 0 1 1
0 1 0 1
1 0 1 0
1 1 1 1
Dn-m= C n_m+ B~-m
En-m=C~-m+Bn_m E n _m

Fig. 39.6. Binary comparator module.


490 Switching-mode Designs
Least
0 10M
significant
digit
1 5M

2 2.49 M
D n _ m output
I
from binary I
comparators I
7 76.8K

8 39.2K

Most 19.6K
9
significant

digit

Most 9 19.6K
i out~ut
significant
digit
8 39.2 K
I
I

E n - m output
from binary
comparators
7

2
76.8K

I
I
2.49 MI
60,Ej
Digit Resistance value
1 5M 3 1.24M
4 619K n=9
Least
0 10M 5 309K 9~m~O
significant
6 154K
digit

Fig. 39.7. Digilal-to-analog converter.

significance of the digit. For example, if the only difference between input and
output occurs in comparing the least significant digit (LSD), the digitizer will have
to travel only one increment equal to 360 /2 8 • Consequently, the input voltage to
0

the motor must be just sufficient to cause it to move one increment. However, if
the difference between input and output occurs in comparing the most significant
digit (MSD), the digitizer will have to rotate 180 and the input voltage to the motor
0
,

must be sufficient to drive it at full speed until the error is zero. The resistance
values are such, therefore, that for an LSD error, one unit of current will be driven
into the modulator; for the next LSD error, two units of current; for the next, four;
and so on up to the eighth digit or the MSD, in which 28 units of current will be
driven into the modulator. The process of demodulation is illustrated in Fig. 39.8,
for a five-bit linear digitizer. The desired position corresponds to the binary input,
and this is compared with each increment as the error is reduced, using the truth
table in Fig. 39.6. The modulator output is proportional to the difference (Dn_m -
E n _m ); the error reduces in steplike fashion, one unit of current at a time, until it
is zero.
The actual circuit diagram of the modulator is shown in Fig. 39.9. The input
swing to the modulator is 20 volts, and since the transistors are used in the reversed
Digital Servo System 491

connection to reduce the offset voltage, it is necessary that the transistors have a
B VEBO rating greater than 20 volts. This requirement is fulffiled by the Texas
Instruments Limited alloy junction 2S302. Potentiometers between the transistors
are used to compensate for the variation of offset voltage between transistors. The
modulator had to be driven from the II5-volt 60-cps supply in order to maintain a
precise phase relationship with the two-phase motor. Two zener diodes back to
back are used as shown, to produce an approximate square-wave drive to switch
the transistors ON and OFF.

Dn·m (Dn·m-En-m)
E n·m
Units of current Input to Proportional to
Input to
into modulator modulator modulator
modulator
24 22 21 output
23 2°


I •• Original position

• 16+8+1=25
16+8 =24
2
2
=2
=2
23
22


16+4+1=21 =0 21
16+4 =20 =0 20

••
16+4+ 1=21 2 =2 19
16+4 =20 2 =2 18

I: •
16+ 1 =17 =0 17
16 =16 =0 16
16 + 1 =17 2 =2 15
16 = 16 2 =2 14

••
8+4+2 =14 =1 13
8+4 =12 =0 12
8+4+1 =13 2 =2 11
8+4 =12 2 =2 10

I: •••
8+1 =9 =0 9
8 =8 =0 8
8+1 =9 2 =2 7
8 =8 2 =2 6
4+1 =5 =0 5
4 =4 =0 4

••
4+1 =5 2 =2 3
4 =4 2 =2 2

I: •
1 =1 0 =0 1
Desired position
0 0 0

Fig. 39.8. Operation of demodulator.


492 Switching-mode Designs

Input 1

3K
lOw
12
4

115v 9 IT::tload
60 cps 10
~K
1
6 7 7 UTC Type
UTCType HA-108X
HA-108X

Input2 10 n
2S302 2S302

Fig. 39.9. Modulator.

Although high-quality transformers are used, some differentiation of the output


waveform occurs. This is due to the direct current flowing in the primary of the
transformer, causing a reduction in the primary inductance, to the high source
impedance, and to the low operating frequency. The switching transients are
damped by means of a I-pi capacitor across the output.
The modulator gives a 2.4-mv peak-to-peak output signal for a 2-p,a input signal
on one side, and 1.1 volts peak to peak for l-ma input signal on one side. The first
corresponds to an LSD error, and the latter to an MSD error.

39.7. SERVO AMPLIFIERS

The preamplifier is shown in Fig. 39.10; it is a conventional operational type.


It is used to sum the modulator and tachometer outputs. It has adjustable overall
d-c feedback to ensure that when the amplifier is overloaded, equal clipping will
occur, and the squared output will have equal mark-space ratio. This is to ensure
that for a large error full torque will be obtained from the motor.
The power amplifier of Fig. 39.11 is used to drive the 3-watt split-phase motor.
The motor is tuned with a 4-p,f capacitor to make the load appear more resistive.
Feedback is used to lower the output impedance, principally to improve the tran-
sient response of the motor.

39.8. SYSTEM STABILIZATION

The chief factors affecting the stability of the system are the frequency response
of the motor and amplifier combination, the mechanical response of the motor,
tachometer and digitizer, and backlash in the gear reducer. Backlash has the same
effect as introducing a lag into the system, and its presence is generally observed
Digital Servo System 493

From

1K

To
power
amplifier

50K 250 K 100p.f


Fig. 39.10. Preamplifier.
2 p.f
From
pn,amplifier Two-phase
60cps motor
0 ~ )~15V
60 cps
+36v

+20v
r-____r-__-+-,4p.f

Transformer:
Primary 1630 T #35
Secondary 1020 T #29 Bifilar wound
Laminations EI 75 SL14 5 x 5 interleaved
Fig. 39.11. Power amplifier.
494 Switching-mode Designs

as a low-amplitude high-frequency oscillation. It is, of course, imperative that the


magnitude of the backlash be much less than the resolution of the servo.
The error signal from the modulator is a staircase function; consequently, the
damping of the system must be such that the system is able to come to a standstill
within one increment of digitizer movement. The stability of the system is adjusted
by means of gain adjustment and tachometer feedback. The gain of the amplifier
must be such that when there is error in the LSD only, there will be sufficient out-
put to overcome the friction in the motor and cause motion in the output shaft.
Tachometer feedback has the same effect as friction damping, without the power
loss and steady-state error associated with friction damping. The gain over and
above that previously mentioned was adjusted for optimum transien t response of
the system.

CONCLUSIONS

A simple digital servomechanism has been discussed which is capable of being


adapted to an actual machine system. The digital-computer section of the system
consists of NOR logic, which is flexible enough to enable use of the least expensive

~
W

B6

To D input To E input
of modulator of modulator
Fig. 39.12. Short-route detector.
Digital Servo System 495

silicon transistors. The present system has a resolution capability of 1% o. The


system is capable of positioning the shaft to a resolution of Y:l however, by utilizing
0 ,

al1lO bits, which is possible with a better gear train.


The output shaft position is indicated by a pointer on a binary-coded 90 quadrant
0

scale. Because of the output-position indication system used, the output shaft
cannot rotate more than 360 Therefore, if the shaft is positioned 1 from refer-
0

0

ence, it will take the long route to get to 359 0


•This may be overcome by the
addition of two NAND gates as shown in Fig. 39.12.
When the output shaft is in sector 00 and the desired position is in sector 11, then
the input to the modulator from the NAND gate must be sufficient to overcome
the actual signal and force the motor in the opposite direction. This can be achieved
by making the weighted resistor equal to half the MSD weighted resistor. Thus,
if the actual position is 1 and the desired position is 359 the error signal that
0
,
0
,

would make the motor tum in the long-route direction will be just under twice the
MSD input current. The output from the appropriate NAND circuit will be twice
the MSD current, making the motor tum in the short-route direction.
APPENDIX

Field-effect Transistors

A.l INTRODUCTION

Conventional transistors exhibit inherently low (but not zero) input impedances
except when operating at very small currents. In the early years of transistor
circuit design this characteristic, plus the current-oriented amplification require-
ments, appeared as major restrictions to the engineers who had originally worked
with vacuum tubes. Time has proved that many of these objections existed only in
the designer's mind, and they vanished as he learned to work with the device.
Nonetheless, there are applications where nothing but a high input impedance
will do. In these cases, conventional transistor circuitry is often awkward or im-
possible to design. The development of the field-effect transistor (FET) was
prompted by this need. However, the FET offers additional advantages which
may encourage wide acceptance:
1. FETs do not depend upon minority carriers, thus their radiation resistance
is good.
2. FETs are free from certain sources of noise that occur in common transistor
action. At least one type of FET now in production exhibits a 3-db spot
noise figure at 10 cps.
3. The power gain of the FET far exceeds that of common transistors at
audio frequencies.
4. The power gain of the FET tends to increase with the current capability,
so that power FETs show considerable promise.

A.2 THEORY OF OPERATION

A unipolar FET can be regarded as a structure containing a semiconductor cur-


rent path whose resistance is modulated by the application of a transverse electric
field.
For the sake of simplicity, consider a bar of semiconductor silicon crystal having
length L, width W, thickness T, excess impurity concentration P, and ohmic (non-
rectifying) contacts at each end, as shown in Fig. A.I.
497
498 Appendix

Figure A.I

The approximate bar resistance Ro between terminals Sand D is

Ro~ L (1)
(qf-L)PWT
where q = electron charge
f-L = majority carrier mobility
The factor qf-LP in the denominator of Eq. (1) is the conductivity a of the semi-
conductor material. A more complete expression for conductivity is
(2)
where a = conductivity
n = electron density
fln = mobility of electrons
p = hole density
f-Lp = mobility of holes
In this discussion we will assume that P ~ N for a P-type crystal. It will be more
convenient to talk about conductance Go rather than resistance Ro:
G = _1 = a WT ~ (qf-L)PWT (3)
o Ro L L
If we assume that the width and length of the bar in Fig. A.I are fixed, Eq.
(3) shows that the conductance can be decreased by removing some of the current
carriers from the crystal or by decreasing the effective thickness T. The FET uses
the depletion regions of back-biased PN junctions to control this conductive
thickness.

Figure A.2
Field-effect Transistors 499

Pchannel

r'ff~i"l
Q)
0.. channel
~
z thickness

o
Q)
0..
~
0.. ~
Space-
~
Space-
charge charge
Figure A.3 region region

Figure A.2 shows a P-type bar of silicon which has had N-type impurities in-
troduced into opposite sides, creating PN junctions. We are interested in conduc-
tance of the P-type channel between the two N-type gate regions. Assume that
any current flow between the source and drain contacts is restricted to the P-type
channel. The conductance of this channel (at very low currents) is given by Eq. (3).
Consider what happens to this conductance when the gate is made positive with
respect to the source; that is, when a reverse bias is applied to the gate-to~channel
PN junction.
Figure A.3 shows a representative plot of the net impurity concentration through
a cross section of the bar at a given junction bias voltage. Since the charges stored
on each side of the junction must be the same, the space charge will be extended
farther in the purer region. It is assumed that the concentration in the N regions is
uniform, the concentration in the P region is uniform, and the junction transitions
are abrupt. As indicated in Fig. A.3, there will exist at each gate-channel junction
a space-charge region, from which all free charge carriers have been removed,
leaving only the nuclei and bound electrons. The width of these space-charge re-
gions is a function of the junction potential and the impurity concentration.
Applying a reverse voltage to the gate-channel junction will cause the conduc-
tance of the channel to decrease because of a widening of the space-charge regions.
Thus the conductance of the channel is an inverse function of the gate-to-channel
voltage. In other words, the transverse electric field introduced into the channel
by the gate has an effect on the channel conductance; hence the term field effect.
Now let us see what happens as the drain-to-source voltage is increased.
Referring to Fig. A.4, assume that the source and gate contacts are grounded .
. Also assume that all parts of the gate are at ground potential (this is a reasonable
assumption, since the gate current is normally very small). Now, when we apply
a negative voltage Vn to the drain, a current will flow from the source through the
channel to the drain. Space-charge regions will be set up as indicated by the
shaded area in Fig. A.4. The current will then be confined to the neutral P-type
channel between the space-charge regions.
Because of the IR drop along the channel, the reverse bias on the gate-channel
junction will not be uniform along the length of the channel. The greater the dis-
tance from the source, the stronger the reverse bias on the junction; this causes the
space charges to assume a wedge shape. N ow we may explore in some detail the
behavior of such a structure.
500 Appendix

VDS
Drain
~===:/-:v.~G-S ---+....JI/r-_---
_ 11"1+,--_ _
Source Drain Gate·

+
Bias

\. space~Charge:; region Source


or depletion layer
(·opposing N·regions are
internally connected)

(a) Structure (b) Device symbol


Figure A.4

A.3 DEVICE CHARACTERISTICS

Static Characteristics. Gate Cutoff Current. By connecting the drain to the


source and reverse-biasing the gate-channel diode, a measure of the d-c input imped-
ance and an indication of the quality of the diode can be obtained. A circuit for
the measurement of this gate cutoff current IGSS is shown in Fig. A.S. The volt-
age used in this measurement is 10 volts, the gate being positive with respect to
the channel for a P-channel device. If this voltage were increased in magnitude,
a voltage would be reached at which the gate-channel diode would break down.
Figure A.6 shows the typical exponential variation of IGSS with temperature for a
silicon device. It can be seen that d-c vaiues of short-circuit input impedance are
in the thousands of megohms near O°C.
Breakdown Voltages. In order to better understand the breakdown-voltage
terminology, consider the typical drain characteristics presented in Fig. A.7 for the
2N2499. These are curves of drain current ID as a function of drain voltage VDS for
the common-source configuration with gate-to-source voltage V GS as a parameter:
. It will be noted that the gate bias voltage is of polarity opposite to that of
the drain supply voltage*; hence, for ordinary bias conditions, a greater potential
difference exists across the gate-drain diode than exists across the gate-source
* These devices can be operated with a few tenths of a volt forward bias, provided the gate-
source. diode is not turned on.

IOv
+
Figure A.5
Field-effect Transistors 501

10
Vas = lOv
ro VDS=O /
/
:I. 1.0
~
....<:
~:l 0.1
/
,/

~
(j

0.01 V
:l
(j V
2ro 0.001 V
OIl
,;, ./
,/
fJ)

......\!l 0.0001

0.00001
-75 -50 -25 0 25 50 75 100 125 150 175
TA , free·air temperature, °C

Figure A.6

diode. This implies that gate-drain diode breakdown will occur before gate-source
diode breakdown. By disconnecting the source from the drain in Fig. A.S and
applying a current source of -10 /La to the drain, the drain-gate breakdown volt-
age BVnGo can be determined under the conditions stated on the specification
sheet. The smallest voltage specified for the three types of units mentioned above
is - 20 volts.
Since the point at which the source is connected to the channel is physically re-
moved from the drain connection, the source can be connected to the gate in the
above measurement without appreciably changing the value of the breakdown
voltage. This connection yields B Vnss breakdown voltage from drain to source
with the gate shorted to the source. A typical value of B Vnss may be seen at the
break on the VGS = 0 curve.

-12
Vas- 0.5v W 2N2499

-10 ~ 01
TA=25°C

ro
E -8
( ~ .I
O.5v

J/; ".,-
~ ,I
<: l.Ov
~ .... ,I
:l -6

vt
u l.5v
<:
.~
"0 2.0v
-4

~
I-"'"'
~ 2.5v

-2 3.0v

~ 1
3.5v
4.0v
a -5 -10 -15 -20 -25 -30 -35
VDS , drain source voltage, volts

Figure A.7
502 Appendix

The break in the drain characteristic curves may be seen to occur at lower drain
voltages as the gate voltage is increased; that is, the drain-gate breakdown voltage
is almost constant and independent of drain-source current. Equation (4) states
the relationship suggested above.
BVnG = BVnsx + VGS ~ constant (4)
where the subscript X denotes the value of BVns for a particular value of VGs. Sub-
stituting BVnGo for the constant, Eq. (4) becomes
BVnsx = BVnGo - VGS (5)
Using the specified minimum B VnGo and values of gate voltage, a curve can
be plotted on the drain characteristic as suggested in Fig. A.8. In the area to the
right of this curve, breakdown is likely to occur. The useful area on the drain charac-
teristic is therefore between this curve and one of the characteristic curves for
slightly forward gate bias. Signals on the gate which cause the gate-source diode
to go into forward conduction are clipped because of the sudden drop in input im-
pedance, but the drain current is not severely affected. If the signal causes
the drain-gate diode to break down, the signal is again clipped by conduction be-
tween the drain and the gate.
Channel Pinch-off. As the magnitude of the drain voltage is increased from zero,
the drain current is at first strongly dependent on drain voltage. However, as the
voltage is increased further, the increasing size of the depletion layer pinches off

,
,'
-,""--
,,,
/ID(on)
vas=o f_
, BVDSS

III
E ,,

-0.1

o -5 -10 -15 -20


VDS , drain source voltage, volts

Figure A.S
Field-effect Transistors 503

Figure A.9

current flow in the channel, and practically no further increase in drain current
occurs until the breakdown voltage is reached. When a reverse bias is applied to
the gate, the channel IR drop necessary to produce pinch-off will occur at a lower
value of drain current, since the gate bias now supplies a part of this voltage. A
pinch-off voltage may be defined as the drain-source voltage which separates the
triode region from the pentode region for a given gate bias voltage; but to describe
this point adequately on a smooth curve, the slope of the (drain) output character-
istic line must be defined at the point of measurement.
While pinch-off voltage can adequately be described in this fashion, such a
procedure is cumbersome in a large-scale production testing facility. The pinch-
off parameter may also be described as the gate-source voltage required to reduce
the drain current to a specified value, or it may be described in terms of drain cur-
rent for specified gate and drain voltages. This last definition is used with the
circuit of Fig. A9 to measure ID(off). Location of the point of measurement on the
drain characteristic is indicated in Fig. A8.
Also indicated in Fig. A8 is the point of measurement of the drain current with
zero gate bias. Because of the magnitude of this current, it is called the ON cur-
rent, ID(on)' It is measured in the pinched-off region. By applying a forward bias
to the gate-source diode, higher current than ID(on) can be realized, although the
input impedance drops rapidly as the gate-source diode nears forward conduction.
In the region extending a few tenths of a volt from each side of the VGS = 0 line,
the characteristic in the pinched-off region is symmetrical and linear about zero.
This feature of the silicon FET allows small-signal operation with zero bias.
Variation of ID(on) with temperature is indicated in Fig. AlO for the 2N2499. It
is an inverse function of temperature between - 50 and 125 C. Preliminary in-
0

vestigations indicate that at lower temperatures ID(on) reaches a maximum and then
decreases. With the device submerged in liquid nitrogen, the shapes of the charac-
teristic curves are about the same as at room temperature.
Low-level Operation. Location of the point of measurement of the static drain-
source resistance rDS is shown near the origin on Fig. A8. This parameter is in-
dicative of the low-level switching capabilities of the device. Except for the con-
dition of forward gate bias, rDS represents the lowest drain-source resistance. If
the drain-source voltage is maintained below pinch-off, the device can be used as
a voltage-variable resistor.
Small Signal Characteristics. An important characteristic of the small-signal
input admittance and reverse transfer admittance is their almost linear increase in
504 Appendix

]:
q ~
...., .. 2.0 ~---'----.--r---'----~---'----r-"""
.... <Ii
t: U
~ t:
... ti'"
::l
u 'Ci)
t: ~ 1.5 ~-.d----+--+--l----+-
.~ Q)

"0 ~
!l'n ::l
J9 ~
0> .:: 1.0
.~
2 ""0
'" U
0.0 :;:;
2 ti'"
Q)
0.5 ~--"~-f--_+_--I--+--l-----t----,-----'--I
N ~
a5 .~
.~ ro
ro E 0 L---L_--L_---l..-_....!......_...I..-_L---L_---'-_-'
E 5 -75 -50 -25 0 25 50 75 100 125 150
o z
z TA , free·air temperature, °C Figure A.l 0

magnitude with frequency. Both admittances are reactive from 10 cps to 100 mc.
In Figs. All, A12, A13, and Al4 the typical variations of the input admittance
and the reverse transfer admittance with frequency are shown. Figure All shows
that the magnitude of the input admittance begins to increase at about 1 cps. In
Fig. Al2 the reverse transfer admittance begins to increase at about 50 cps.
Above these frequencies, a comparison of Figs. A.ll and Al2 with Figs. A13 and
A14, respectively, shows the real parts to be very small compared with the magni-
tudes of the admittances. The input admittance and the reverse transfer admit-
tance are shown in Figs. Al5 and A.16 for frequencies up to 100 mc. The real

o 1.0 ~----,-----r----_,_---__,
.s:::
E
:!.
<Ii
<.J
t:
VDS = -lOv
2N2499 TA = 25°C
::::'"
'E 0.1~----+-----l------+----~
"0
....'"
::l
a.
.=
Q)

~
5 0.01~---_+_----l__---~~--__I
II)

C::
o
E
E
o
u
~ 0.001 ~---_+_----,-~f--..o~--_+_---__I
tlO
~
ro
E
II)

.£ 0.0001 L - _ l ._ _:Il.L---1---'-.L..L..I..1.1J.L--L.J.....L.LU.J..LL---1-L.L..L..u..L.L.J
0.1 1.0 10 100 1,000
t, frequency, cps

Figure A.ll
Field-effect Transistors 505

1.0 ,..-----r----...------r-----,

VDS = -lOv
TA =25°C
~2
... E
6 ::t.
'(' 0'- 0.1 I------+-----+------+------.'-I-~
5 ~
E
E .~'" 2N2499
8.§
(ij
c '"
...
.~~
VJ VJ
..!. C
ro ~
~ ~ 0.01~---4----~--J~_+---~
~~
~Ol

~e

0.01 0.1 1.0 10


t, frequency, kc

Figure A.12

10

/
VDS= -IOv
ID/ID(on)= I
2N2499 gis = Re (Yis)
Ol 1.0
l:
:J 0
- /
/
0 ..c
VJ
.::0 E
::t.
E Ol- 0.1

/
E ()
C
0
()

(ij '"
tl
:J
.~ -g
.f 0 am
(ij
E c.
....
()

:J
/
V
~.E
.~
0

0.001 ,/
,,
f- / -

0.0001 ~( I I

om 0.1 1.0 10
t, frequency, me

Figure A.13
506 Appendix

100~----------~----------,-----------~
VDS = -lOv
TA=25°C
grs = Re (Yrs )
10b-----------~----------~----------~

2N2499

0.1~----------_+------------~~~------~

0.01~----------_+---------L~~----------~

0.00 1 L-__L-L....l---LL.U..l..L__....L-'-...L..l....L..l..u.l__---L--l---L~..J..1..Ll
0.01 0.1 1.0 10
(, frequency, mc

Figure A.14

10,000
0
.<:
E /
~
of
'-'
s::::
3,000 17
,/
fl
·E
"0
'"
oj-'
:::l
a.
.!:
1,000
//
/
~/
/
/

I
/
17
Q)
~ /
:::l
0 /
~/
.::'"0 300
E
E
0
'-'
1/"
I
/ 2N2499
VDs=-lOv
ros:::: j
ID=ID(on)
bO 100 -
~
ro
E
'"
?-7 30
,,
I
I
" gis = Re (Yis)
b is = 1m (Yis)
TA =25°C

.'
2 3 5 10 20 30 50 100 200 300 500 1,000
{, frequency, mc

Figure A.15
Field-effect Transistors 507

10,000

3,000
'"
/
Ul
.... 0
"'£
iii E
~ ::t '0,'
(j
....
:::J '"c:
(j
-

1,000
//
o /
~lS
c ."t::::
o E
,/
E"O
E ro
o ....
(j '"
-'t; 300
," /
ro c:
c: ro
bj
, "
tlD __
0(i,j ....
..g; 2N2499
'"tlD 1/'
cJfL
ro VDs=-lOv
E~ ~
ID=ID(on)
Ul 0 100
- > \;::

~
/' " ,11/ - grs = Re (Yrs )
- brs = 1m (YrJ

30 I TA =25°C
*C 2 = 5.4 pf, R4 and R6 = 55 n
J I I I I I
2 3 5 10 20 30 50 100 200 300 500 1,000
t, frequency, mc

Figure A.16

and imaginary parts of these two parameters roughly correspond to the real parts
and the magnitudes of the four preceding figures.
The forward transfer admittance is virtually constant and real from direct cur-
rent to 20 me. Above 50 me the real part drops very rapidly, but the imaginary
part maintains the magnitude. This is shown in Fig. A17. Transit time in the
channel material is a possible cause of the rapid drop in the real part.
The output admittance is resistive up to about 1 me. Between 1 and 5 me the
reactive part grows larger than the real part; between 5 and 100 me the reactive
part is dominant. Figure A18 shows extrapolations into this transition region
from data taken at higher frequencies.
Figure A19 presents an example of the geometry employed in fabricating the
2N2499 silicon FET, which utilizes advanced gaseous diffusion and photolitho-
graphic techniques of the type required to produce superior high-frequency bipolar
transistors. Germanium FETs are made at Texas Instruments Inc. by a modifica-
tion of the same alloy process used to fabricate ultra-reliable computer transistors.
Whatever the process, the functional structure of the FET can be reduced to
that shown in Fig. A20. This figure suggests an equivalent circuit which will rep-
resent the FET. We will develop this circuit for the 2N2499.
Because of the linear nature of the relationship of the terminal and transfer
admittances with frequency, an equivalent circuit can be used· to represent the
2N2499 from direct current to about 100 me. The equivalent circuit is shown in
Fig. A2l. Location of the lumped constants has been taken directly from the rep-
508 Appendix
o
E 10,000
=l
ai

--- --- -- !.t:.. 1/


u
c
~ 1-- ~--
"E 3,000

/ 1\
"C
ro
.....
a.l
'ti
c
~ 1,000
/
"
1:
ro /
~ ~/
.E /
a.l
/
~ 300
o
III V
.::o / 2N2499
E ~/
V DS = -lOv
/
§u 100 ID= ID(on) -
roc grs = Re (Yrs)
OIl
-brs =Im (YrB)
~ TA=25°C
ro I I I
~ 30

2 3 5 10 20 30 50 100 200 300 500 1,000


(, frequency, mc

Figure A.17

10,000
0
.s=
E
=l
ai
u 3,000 /
c
~
ro
E
/
"C
ro
....
:::l 1,000
/
.&
:::l 7
~
0

/
a.l
~
:::l
0
III
.:: 300 ,
0
E /
/ V
l7
-
E
0
u
roc , /'
~ VDS = -lOv _
OIl
100
~;. -- -- ID=ID(on)
~ Ii
ro gos = Re (Yog )
E bos = 1m (Yos)
III

~ 30 I I ",

2 3 5 10 20 30 50 100 200 300 500 1,000


{, frequency, mc

Figure A.18
Field-effect Transistors 509

Source contact
( Gate
( l Orain contact
amn (,Gate

I.::'
Section at A-A
I

Figure A.19

resentation in Fig. A20. It is assumed that the gate current is divided between
two branches at the ohmic contact, each branch current being required to flow
through a bulk resistance in the gate, the space-charge layer, and a bulk resistance
in the drain or source. The space-charge layer is represented by a capacitor
in parallel with a leakage resistance. Joining the drain and source bulk resistances
is a current generator in parallel with the differential channel resistance in the
pinch-off region. The voltage which activates the current generator has been
assumed to be the voltage across the gate-source capacitor. The internal d-c
transconductance is g;'" . Because of internal feedback in the bulk resistance of the
source R5 the external d-c transconductance is

(6)

Large differences in magnitude exist among the resistances of Fig. A21. Their
order is as follows: R 1 , R2 ~ rD ~ R 3 , R 4 , R 5 , R 6 . The approximate magnitudes
are
R 1 , R2 ~ 1010 ohms
R3 + R5 ~ 150 to 200 ohms
R4 + R6 ~ 50 to 60 ohms

In Fig. A22 are shown the real parts of the forward transfer admittance and the
output admittance as functions of drain current. The higher drain currents
provide higher forward transfer admittance but lower output impedance. Figures
A23, A24, and A25 show the effects of bias current and voltage on the capacitive
components of the four admittances. The input capacitance Cis is approximately
equal to the parallel combination of C1 and C2 in the equivalent circuit. The out-
put capacitance Cos and the reverse transfer capacitance C rs are very nearly
equal to C 2 •
Noise Characteristics. Noise figure is defined as the amount of degradation
suffered by the signal-to-noise power ratio in passing through a system. The nature
of noise figure has been discussed in Chap. 21. To recapitulate, for the FET,
510 Appendix

Drain

Gate
- J [r- ....!:...
fr

VaG -.:1--
Source

Figure A.20

F IOI E(on)2 (7)


= og Av2(4 KTBRg)
where Av = Eos/ Eg, the voltage gain measured at signal levels far above the noise
level
K = Boltzmann's constant, 1.38 X 10-23 joule;oK
T = temperature of R in oK = °C + 273
B = equivalent rectangular bandwidth of the system, cps
Rg = resistance of the signal source impedance, ohms
Eg = the signal source equivalent Thevenin voltage generator
Eos = the output voltage of the FET
E(on) is the output noise voltage produced by Rg and system noise when Eg = O.

Go---t

s Figure A.21
Field-effect Transistors Sl1
5,000 r-----r--,...---,---r--,-----r--,--,.---r--. 200
o
..c VDS = -lOv
~ E
Q)

:; ::t. f= 10 ke-5 me C,)


.... 0
oVl • 4,000 TA=25°C 160 ::l.J:::

e e
Q)
C,)
grs = Re (Yrs) ~ E
e ::t.
0
o '"
En gos = Re (Yos) E cU
E ::l 3,000 1----+-+---t-_+_-t:::...""F'---+--t-_+_--; 120 E g
0"0
_C,) e0
-
un
o '"
::l
'"
C,)
e .... ~"O
.~~ 2,000 r--+-.y~--+--t--+----:;;v~--+----t 80 .-
bile
0
Vl Vl ~
e
....!.
tti ~ = ... C,)

E ..... '"
E a. ::l
Vl"O 1,000 r-.~-+---t---:"JfI"-t--+--+--t--+---; 40
. ~
Vl"5
";,0
~;::
Q.o .... 0.0
.E
0
o -2 -4 -6 -8 -10
ID , drain current, ma

Figure A.22

All terms in Eq. (7) can be measured, and noise figure for a system can be com-
puted. If the gain of the first stage of the system is high, noise generated by
succeeding stages will be negligible at the output and the noise figure of the first
stage may be considered the noise figure of the system. Figure A.26 shows the
basic system used and its external equipment.
For the narrow-band noise-figure measurements, it is necessary to measure the
equivalent rectangular bandwidth B, the gain G, and the output noise E(on)' with
Eg = O. When gain measurements are made, the output should be monitored with
an oscilloscope to check for the presence of clipping or pickup, e.g., 60 cycles. The
generator output should be kept low enough to prevent clipping, and the test
circuit should be placed in a well-shielded enclosure to prevent unwanted pickup.
The frequency of the generator must be set at the center frequency of the filter.

20
JDSI=I_lidv
f=lOke-5mc
16 TA=25°C
C. = 1m ,,~
....a. IS
(Yis)
w i-'"
cU
C,)
e
.l9
Ti
'"a.
12

8
- ~
1.,...000' ~

'"
C,)

c5
4

o
0.01 0.1 1.0
Normalized drain current, IDIID(on)

Figure A.23
512 Appendix

12
Vns = -10v

10 -
{= 10 kc-5rnc
TA =25°C /
11. 8 -

Cos = 1m (yos)

Crs = 1m (Yrs)
w

w
/
-
u CV
c: C = 1m (Yrs)
~ rs
u
6 - W
./
/ Cos
ro
Q. C rs
ro
u ./
0" 4

/
V
2 i"""'"

o -2 -4 -6 -8 -10
I D , drain current, rna

Figure A.24

For the Krohn-Rite filter, minimum pass bandwidth is obtained by setting the
high and low cutoff frequencies equal.
According to Fig. A. 27, the break point of the II/region is less than 100 cps.
This is about half an order of magnitude lower than most transistors. The
I-megohm source resistance shown in Fig. A.27 is not optimum at all frequencies.
At lower frequencies the optimum source resistance is higher; e.g., at 10 cps the

20 1

18 L cl {=1 mc

~"I~I
TA=25°C-
16 . lJsO?GS "=1 v) I
s. v _I I
.....Q. 14 ~08(V I.
...... ~10 C _lm(Yis)-
r£ 12 V) is - - w -
u --"1--- -
c:
.l9
'uro 10
Q.
ro
u
8 c
0" 6
4

2
- ~s.f?;

-Crs vi" VGS (Vns - -10 v)


I
lJs O?GS "= 1 v)

1
C rs = 1m (Yr.) -
w

0 2 3 5 6 7
Vas, gate·source voltage, volts

o -2 -4· -6 -8 -10 -12 -14


Vns , drain-source voltage, volts

Figure A.2S
Field-effect Transistors 513

Zelco Krohn-Hite Ballantine


Audio
oscillator Model 108 Model 330-M Model 320
amplifier Filter true rms

r ___ ~W~~lde~ _ _ _ _ _ _ _ _ l

I Test FET I
I I
I I
I I
: I
I I
I I Conditions:
I I VDS= -5.0v
I I I D = -l.Ov
IL _________________
20 JoIf I RG=1.0M
~

Figure A.26

optimum source resistance is about 10 megohms. Figure A.28 shows the optimum
Rg and optimum NF of the 2N2500 vs. frequency. Figure A.29 shows that, con-
trary to operation with other transistors, noise figure is independent of operating
current for the FET. Although noise figure is proportional to voltage, the change
is slight over a normal operating range_

12
JDS~I_lci~ II
ID = -1 ma
10
Ra=l M
.a
'0

i
::l
8
1\ TA =25°C

OJ)

-=
~
'0
6
1\ ,
c
'5
f} 4
\,
u:
z
2 ~
~ ......
o
0.01 0.1 1.0 10
I, frequency, kc

Figure A.27
514 Appendix

5 20

II
V~S~ ~~~
.0 4 VGS=O
-0
TA = 25°C
~.
::l
bD

""~ 3
'0
c
E
~
\
:::J
E
R 2
0
o [\\
.p
°r~
"V..<' ':) (,-s
rc:o • f:'
~

-
<J(,-
ill;S; F i"1:::::
o
om
III0.1 1.0 10
o
t, frequency, kc
Figure A.28

A.4 BIAS DESIGN CONSIDERATIONS

The 2N2497, 8, 9 data sheet gives two sets of curves to assist the designer
in setting the bias operating point. Figure A.30 shows the gate-source voltage re-
quired to bias a field effect with a given ID(on) to the desired drain current. This
curve is most useful in fixed bias design, d-c amplifier design, and other de- .
sign work where the gate bias voltage is needed. The curves in Fig. A.31 are re-

2.0
R~= 1 M
t= 1 kc
.0
TA=25°C
-0 1.5
~.
:::J
bD

""'0
OJ
U)
1.0
c ~ _ l \IIa)

~
'00.

----
~I' \IS·
I,
U)

NffTr)
LL
z 0.5
~

o -2 -4 -6 -8 -10
VDS ' drain-source voltage, volts
I D , drain current, ma

Figure A.29
Field-effect Transistors 515

-14
VDS = -lOv
TA =25°C
-12

-10
co
E
~
c -8
~
:::l
U
c
.~ -6
"C

.....Q
-4

-2

o -2 -4 -6 -8 -10 -12 -14 -16


ID(on). zero-gate-voltage drain current. rna

Figure A_30

lated to the curves in Fig_ A,30 by the equation Rs = VGs/ID • These curves are
given specifically for the purpose of determining the value of source resistance
needed for self-biasing (circuit shown in Fig. A,3l).
To illustrate the use of these curves, a bias example for each FET type has been
worked up and the results are shown in Fig. A,31. Since the procedure used is
not completely obvious, a detailed explanation of the 2N2498 example follows.
The easiest way to stabilize drain current with a three-to-one ID{on) variation for
each device type is to use self-biasing. To achieve tolerable stability, the drain
current ID should be selected about half the minimum ID(on). In this example,
-1.25 rna was selected for I D • The value of source resistance Rs was taken from
the second set of curves at the intersection of ID = - 1.25 rna and ID(on) = -4.0
rna, the center value for the 2N2498. Thus, Rs = 1 kilohm will give a symmetrical
change in ID over the ID(on) range for the 2N2498. To find this change in ID on
Fig. A,31, follow the Rs = 1 kilohm curve to ID(on) = -2 rna and -6 rna; the re-
spective values of ID are -0.75 rna and -1.75 rna. This gives a change of 0.5 rna
in each direction, or a 40 per cent change of design center. This amount of
operating-point stability is usually good enough for the average small-signal stage;
Fig. A,32suggests a method for achieving greater stability where desired.
Considerable increase in stability can be achieved without loss in device dynamic
operating range by fixed-biasing the gate of circuit A and compensating for this
by adding resistance R to Rs as shown in circuit B. Five volts was selected as a
reasonable value to bias the gate. However, any value can be selected from the
device standpoint, since both the gate and source are changed by the same amount
516 Appendix

-14
VDS = -lOv
TA =25°C
-12

-10

'"
E
....c:- -8 -=-VDD
+ ~----~~--~~~
~
::J
U
c:
"(ij -6
-0
~
-4

-2
5,Ooon

o -2 -4 -6 -8 -10 -12 -14 -16


[D(on), zero-gate-voltage drain current, rna

Figure A.31

to keep VGS constant; therefore the device is no closer to breakdown than before.
The value of R is determined by VG/ln, or -5 volts -;- -1.25 rna = 4 kilohms for
the example. This gives a new R; = 5 kilohms. To find the increase in stability,
R; is plotted on Fig. A.30 through the operating point as follows: symmetrical
points are found on the VGS curves (for 0.5 volt and 2.0 volts) by dividing the

Circuit A Circuit B Circuit C

Figure A.32
Field-effect Transistors 517

Table A.1

FET
ID design center, rna Rs, kilohms R's, kilohms
type
2N2497 -0.5 2.00 12.0
2N2498 -1.25 1.00 5.0
2N2499 -4.00 0.53 1.8

differences between these voltages and the operating point VGS (or 1.25 volts) by
5 kilohms.
1.25 - 0.5 2.0 - 1.25 0.75
5 kilohms 5 kilohms = 015'
. ma
5 kilohms
Thus, the point on the 0.5-volt curve is In = - 1.25 + 0.15 = - 1.10 ma, and on
the 2.0-volt curve it is In = -1.25 - 0.15 = -1.4 ma, as shown on Fig. A.30.
Since these points are almost the exact values of the new In for the -2 ma and
-6 ma In(lYfI) devices, the drain current can be considered to change -+-0.15 ma, or
-+-12 per cent from design center. Thus, the stability is considerably improved,
In change being one-third that of the first cas~.
This analysis has shown no effects of temperature, but there are two other
curves on the 2N2497, 2N2498, 2N2499 data sheet that can be used in combina-
tion with the biasing curves to determine the effects of temperature: gate cutoff
current vs. temperature, and normalized In(on) vs. temperature. Comparison of
these curves shows that the temperature coefficient of IGSS is the usual positive-log
type for diode saturation current. They only tend to compensate, since the drop

Table A.2

Per cent variation of In above and


below design center In due
In(on)' rna VGS, volts' In, mat In, ma§ to max and min IlJ(on)

Circuit A Circuit B or C
I 0.5 -0.35 -0.47
2 1.0 -0.50 -0.50 ±30% ± 6%
3 1.5 -0.65 -0.53

2 0.4 -0.75 -1.10


4 1.25 -1.25 -1.25 ±40% ±12%
6 2.00 -1.75 -1.40

5 0.4 -2.15 -3.2


10 2.12 -4.00 -4.0
±45% ±19%
12 2.75 -4.60
15 3.7 -5.80 -4.7

• Value of VGS for design center In in Table A. 1.


t Value of In for Rs in Table A. 1.
§ Value of In forRs in Table A.1.
S 18 Appendix

2N2499

Figure A.33

in the gate resistor biases the unit ON and the iD(on) decreases, turning it OFF for
the same changes in temperature. The temperature effect on iD(on) can be added
to the bias stability determination by adding its variation to the ends of the normal
device irxon) range and then applying it to the biasing curves.

A.S APPLICATIONS

Potential applications for the FET are virtually limitless. The typical applica-
tions presented here were selected merely to suggest its great flexibility.
Voltage-controlled Current Source. Figure A.7 showed the variation of drain
current vs. gate voltage. At any given gate voltage, an increase in drain voltage
beyond pinch-off will cause very little change in drain current. The device is a
constant current source in this region, with drain current depending on gate voltage.
Voltage-variable Resistor. When biased with drain-source voltage below
pinch-off, the FET can act as a voltage-variable resistor. The circuit of Fig. A.33
illustrates this type of application.
Timers. Figure A.34 is a circuit for a linear scale timer. The time cycle
T is described by the equation T = Rl C, if R2 <{ R 1 . The potentiometer R2 com-
pensates for capacitor and transistor transfer tolerances. For extended time cycles,
the capacitor should be a high quality Mylar® or polystyrene type.
The operation of the timer circuit in Fig. A.35 is similar to that of a one-shot
multivibrator. Q3 is normally ON, and C1 is charged to Vee - VDl - VSE(3) -
VGS(2) with polarity as shown. When Sl is pushed, Q2 and Q3 turn OFF. Q3 re-

Figure A.34
Field-effect Transistors 519

Vee
-8v d-c

1.8 K 1.8 K

-a.BV. r
+ -7.3v--- L---..J
f-t~
t t= 1 sec to 3 min
8 1 pushed

All resistors are ± 5% tolerance, t watt.


C 1 is ± 10% tolerance, Mylar@.
D1 Temperature range = - 20 to + 55°C.
15 K IN2069

Figure A.35

mains OFF until the charge on C1 decreases to the point where Q2 is turned ON
sufficiently to cause Q3 to conduct.
A-C Amplifier. The amplifier in Fig. A.36 demonstrates how FETs may be
used to obtain very high input impedance without sacrificing bandwidth or low
noise performance. Input impedance is 30 megohms shunted by 8 pf. Amplifier
voltage gain is 40 db -+-0.5 db from -55 to + 125°C.
The high input impedance is obtained by bootstrapping Ql. Considerable in-
crease in stability is achieved without loss in dynamic operating range by fixed-
biasing the gate of Ql and compensating for this by adding resistance to the source
of Ql. By using this type of bias, a 3-to-l change in ID(on) as guaranteed by the
2N2498 will produce about -+- 12% change in drain current from the design center.
Wide bandwidth is obtained by operating Q2 grounded base to reduce the Miller
capacity of the field effect at high frequencies. By using a field effect for Q3, it is
possible to use a large load resistor for Q2 to obtain a large voltage gain from Q2.
Figure A.37 shows the frequency response of the amplifier.
The low noise characteristics of the amplifier vs. generator resistance are shown
in Fig. A.38. The broadband noise figure of the amplifier is less than 3 db over a
generator resistance range of 50 kilohms to 5 megohms.
Simple D-C Millivoltmeter. FETs are semiconductors and, therefore, their
electrical characteristics are temperature sensitive. Thus, in direct-coupled d-c
amplifiers they perform best in differential connections. However, FETs differ
significantly from transistors in that the input current is only a few nanoamps,
2.0/-,f
01

'"
o

, " " 0 +28v

3.3 K
10/-,f
lOv
L...-_ _'~--II~ Output

Qa Q4
2N2498 2N930

IN756

2.0M

20K

Figure A.36
Field-effect Transistors 521

50
TA =25°C
..0
"0 ~ ",
.~ 40 ';lj

~ ~~ \~......-
t10 Gl
....
Cll
II
~ Q",

~ 30 .;~ ~

'" I
ol~ ____~____~__~____~____~__~____~
0.001 0.01 0.1 1.0 10 100 1,000 10,000
t, frequency, kc

Figure A.37

being all diode saturation current, and it is therefore independent of the drain cur-
rent. This makes possible low-drift amplifier performance for megohm sources.
An example of this performance is given by the simple meter amplifier shown in
Fig. A.39.
The differential amplifier is made up of a pair of simple two-stage feedback
amplifiers with an approximate voltage gain of 3. The operating conditions of the
field effect are VDS = 10 volts and ID = 1 rna. These conditions were selected to
give a forward transconductance of 1,000 to 1,500 pmhos and an output impedance
greater than 50 kilohms. A PNP-transistor constant-current source is used to im-
prove operating conditions stability of FETs with ID(on) ranging from 1 to 6 rna
and to improve the common-mode rejection ratio. When used as a d-c millivolt-
meter, the circuit has an input sensitivity of 20 megohms per volt with a common-
mode rejection ratio of 1,000 to 1.

6
Ban~widtL 1'0 clpslt~ Ib 1k1c
..0
"0
e-
l\ TA =25°C
'\
",
::J
blJ
:;:: 4
Cll
en
·0
C
""0
C
...... ~ '"
'"
..c
""0
1', , /1/
e'"
..0
u:
2
............
""'"- l.--- --
Z

o
om 0.1 1.0 10
R a, generator resistance, megohms

Figure A.38
522 Appendix

+ 0--_----+......
1M
1%

1M
1%
50!}
Zero adjustment

Ql + Q2 are matched 2N2386 -15v

Figure A.39

Reasonably good temperature characteristics are achieved by matching the PETs


as shown in the following table:

Per cent
Parameter Test Conditions Min Max Units match

ID(on) zero-gate-voltage drain current VDS = -10 v -1 -6 rna 10


Vas =0
Vpo pinch-off voltage VDS = -10v 2 6 volts 10
In = 10 Ita

lass gate cutoff current Vas = 10 v 10 na 10


VDS = 0 V
Field-effect Transistors 523

Temperature data from -25 to +50°C were taken for this circuit with matched
FETs and I-megohm gate resistors as shown. The output change was found to be
linear, giving an equivalent input voltage drift of 0.175 mv per CO. This drift is
lower than can reasonably be achieved with very tightly matched dual transistors
under the same conditions, i.e., I-megohm base resistors.
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