Design and Implementation of Viterbi Decoder Using VHDL: IOP Conference Series: Materials Science and Engineering

IOP Conference Series: Materials Science and Engineering
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Design and Implementation of Viterbi Decoder Using VHDL

To cite this article: Akash Thakur and Manju K Chattopadhyay 2018 IOP Conf. Ser.: Mater. Sci. Eng. 331 012009
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3rd International Conference on Communication Systems (ICCS-2017) IOP Publishing
IOP Conf. Series: Materials Science and Engineering 331 (2018) 012009 doi:10.1088/1757-899X/331/1/012009
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Design and Implementation of Viterbi Decoder Using VHDL

Akash Thakur and Manju K Chattopadhyay
VLSI Design and Embedded System Lab, School of Electronics,

Devi Ahilya University, Indore, India
E-mail: [email protected]
Abstract. A digital design conversion of Viterbi decoder for ½ rate convolutional encoder with
constraint length k = 3 is presented in this paper. The design is coded with the help of VHDL,
simulated and synthesized using XILINX ISE 14.7. Synthesis results show a maximum
frequency of operation for the design is 100.725 MHz. The requirement of memory is less as
compared to conventional method.
Index Terms—VD, VHDL, RTL, BMU, PMU, ACSU, SMU.
1. Introduction
Encoders and decoders play an important role in the field of communication and data storage industries.
There is a need of reliable system with least probability of error and high speed of operation. Error
correcting coding [1] has algorithms for expressing a sequence of numbers, so that if any error due to
noise arises, it can be detected and corrected (within certain limitations). These algorithms come into
operation by converting them into digital design. The digital conversion will work at certain frequency.
Recent developments have contributed towards achieving high reliability required by today’s high-speed
digital systems. The use of coding for error control has become an integral part in the design of modern
communication and digital storage systems.
A typical transmission or storage system may be represented by the block diagram shown in figure1.
Efficient error control code in encoder and decode can help in gaining the following advantages:
a. Power gain by coding in power/bit for cellular systems in digital communication.
b. Increase in storage capacity (no. of bits per sq. inch increases)
Figure 1. Simple Communication Model
Even though the concept of Viterbi algorithm is very old, it is still very much researched for its
optimization. Jinjin He et al. [2] presented paper on low power design of Viterbi decoder without degrading
the decoding speed. K. S Arunlal and S. A Hariprasad [3] shows the reduction in computational time and
hardware requirement. The crucial point among the digital design conversion is the operating speed and
the power reduction, which is presented by many researchers with variation in operating frequency and
reduction in digital complexity [4-9]. D Vaithiyanathana et al. [10] proposed a modified pipelined
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architecture for ACS of Viterbi decoder and shows optimization in frequency of operation, up to 165 MHz
with reduced area. The design proposed by us reduce the memory requirement for the trace back of the
trellis.
2. Architecture
Viterbi Algorithm is an efficient way to implement the M L Decoding, for both hard and soft decision. It
is easy to implement for small constraint length for convolutional encoders which is based on the trellis
method. A J Viterbi proposed Viterbi algorithm in 1967 for convolutional codes. The basic architecture of
the Viterbi Decoder (VD) based on Viterbi algorithm is shown in figure 2.
Figure 2. Block Diagram of Viterbi Algorithm
The main components of the VD are Branch Metric Unit (BMU), Path Metric Unit (PMU), Add-
Compare and Select Unit (ACSU) and Survivor Management Unit (SMU). Viterbi Decoder decodes the
convolutional encoded data on the basis of trellis. An intermediate state of the trellis for a Viterbi decoder
of ½ rate convolutional encoder with constraint length k=3 is shown in figure 3.
Figure 3. Intermediate trellis state of the decoder
A Branch Metric Unit-BMU calculates the branch metrics; An Add-compare-Select Unit -ACUS
recursively accumulates the branch metrics. Path metrics (PM), compares the incoming path metrics,
and makes a decision to select the most likely state transitions for each state of the trellis and generates
the corresponding decision bits. Viterbi algorithm is a special case of Bellman Ford shortest distance
algorithm.
3. Hardware Description
The proposed digital design of the Viterbi decoder for ½ rate convolutional encoder of constraint length
of k=3 is shown in the figure 4. In this design, instead of storing the path metric for each stage, the
decision is taken directly. Following are the components used in the decoder:
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3.1 Branch Metric Unit (BMU)

Branch Metric (BM) calculation is the distance between received and estimated output code word. It is
also called the Hamming distance, for e.g. if the received code word is 10 then the hamming distance
with 00, 01, 10 and 11 will be 01, 10, 00, 01 respectively. This function is done by the BMU.
3.2 Add Compare & Select Unit (ACSU)

Path Metric (PM) calculation is done by ACSU in iterative manner. It is repeated for every encoder state.
Previous path metric will be added to the corresponding branch metric, and the output will be sent to the
comparator and select unit. Two paths ending in a given state are compared and the greater metric is
dropped, whereas the smaller one is selected for further calculation, known as survivor path.
3.3 Path Metric Unit (PMU)

Path Metric Unit takes input from the output of the ACSU and store it for the next clock pulse. It gives
input to ACSU for calculation of next PM. For state a, the path metric for time instant n will:
PM(a,n) = min { PM(a,n-1)+BM(00), PM(b,n-1)+BM(11) } ………. (1)
3.4 RAM
Random Access Memory is used in the design, to store the decisions made by the survivor unit.
3.5 Survivor Unit (SU)

Survivor unit takes the path metrics of all states and select the least of the path metrics. A decision will
be made by selecting the least of the path metric of all states for particular time instant and it will be
stored in RAM.
The design is coded in VHDL, figure 5 shows the block view and figure 6 shows the RTL view
generated after successful synthesis of the Viterbi decoder. Simulation results are taken for input code –
11, 10, 10, 00, 01, 11.
Figure 4. Proposed digital design of Viterbi Decoder for K=3
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Figure 5. Block View of Viterbi decoder
Figure 6. RTL View of Viterbi decoder
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Figure 7. Simulation Results of Viterbi decoder
Figure 8. Data stored in RAM after 7 clock pulses
Figure 9. HDL synthesis report of the Viterbi decoder
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Figure 10. Timing summary of the Viterbi decoder
4. Conclusion & Future Work

The proposed digital design of the Viterbi decoder for ½ rate convolutional encoder of constraint length
k = 3 is successfully synthesized in VHDL and simulated using XILINX ISE 14.7. RTL View of the
complete design is shown in figure 6, whereas figure 7 and figure 8 shows the simulation results. Instead
of storing the path metric of all four states for a single time instant, a decision is made by the survivor
unit and reduce the memory requirement for a complete trellis length. The HDL synthesis report and the
timing summary is shown in figure 9 and figure 10.
Future work will be implementing the design and evaluation of speed performance and power
consumption of the decoder on different FPGA boards.
5. References
[1] Lin S & Costello D J Jr 2011 Error Control Coding (Prentice Hall Inc ) 2e
[2] He J, Liu H, Wang Z, Huang X and Zhang K 2012 High-Speed Low-Power Viterbi Decoder
Design for TCM Decoders, IEEE Trans. on Very Large Scale Integration (VLSI) Sys. vol 20 no 4
pp 755-9
[3] Arunlal K S and Hariprasad S A 2012 An Efficient Viterbi Decoder, Inter. Jour. of Comp. Sci.,
Engg. and App. (IJCSEA), vol 2 no 1 pp 95-110
[4] Pujara H and Prajapti P 2013 RTL Implementation of Viterbi Decoder using VHDL, IOSR Jour.
of VLSI and Sig. Pro. (IOSR-JVSP) vol 2 issue 1 pp 65-71
[5] Reddy A S and Krishna P R 2013 High Speed Viterbi Decoder Design With A Rate Of 1/2
Convolution Code For Tcm Systems, Inter. Jour. of Techno. Enhan. and Emerging Engg.
Research vol 1 issue 4 pp 126-30
[6] Soreng B and Kumar S 2013 Efficient implementation of Convolution Encoder and Viterbi
Decoder, Inter. Confer. on Circuits, Power and Computing Techno. (ICCPCT) pp 1270-3
[7] Mahendran R and Sathish T M K 2013 Low Power Adaptive Viterbi Decoder Design For Trellis
Coded Modulation, Inter. Jour. of Innovative Research in Elec., Electron., Inst. and Control
Engg. vol 1 issue 3 pp 123-8
[8] Singh P and Vishvakarma S K 2013 FPGA Implementation of 413.121 MHz and 11.34 mW High
Speed Low Power Viterbi Decoder, International Journal of Modeling and Optimization vol 3 no
1 pp 15-9
[9] Wayal K, Gore K, Waikule S and Wagaj S.C. 2015 Convolution Encoding and Viterbi Decoding
Based on FPGA using VHDL, Inter. Jour. of Advanced Tech. in Engg. and Science vol 03 issue
01 pp 622-6
[10] Vaithiyanathana D, Nargisb J, and Seshasayanana R 2015 High performance ACS for Viterbi
decoder using pipeline T-Algorithm, Alexandria Engineering Journal vol 54 issue 3 pp 447–55

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PAPER • OPEN ACCESS

Design and Implementation of Viterbi Decoder Using VHDL

View the article online for updates and enhancements.

This content was downloaded from IP address 47.9.103.225 on 09/10/2018 at 15:29

Design and Implementation of Viterbi Decoder Using VHDL

VLSI Design and Embedded System Lab, School of Electronics,

Index Terms—VD, VHDL, RTL, BMU, PMU, ACSU, SMU.

Figure 1. Simple Communication Model

Figure 2. Block Diagram of Viterbi Algorithm

Figure 3. Intermediate trellis state of the decoder

3.1 Branch Metric Unit (BMU)

3.2 Add Compare & Select Unit (ACSU)

3.3 Path Metric Unit (PMU)

PM(a,n) = min { PM(a,n-1)+BM(00), PM(b,n-1)+BM(11) } ………. (1)

3.5 Survivor Unit (SU)

Figure 4. Proposed digital design of Viterbi Decoder for K=3

Figure 5. Block View of Viterbi decoder

Figure 6. RTL View of Viterbi decoder

Figure 7. Simulation Results of Viterbi decoder

Figure 8. Data stored in RAM after 7 clock pulses

Figure 9. HDL synthesis report of the Viterbi decoder

Figure 10. Timing summary of the Viterbi decoder

4. Conclusion & Future Work

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