EE/CPRE 465 – Fall 2019

Final Project
Overview

The United States Department of Agriculture (USDA) has discovered that the temperature
of a plant affects the protein level present in the plant. They want to investigate more
about the relationship, hence the need to monitor the temperature of the plants remotely.

They come to see you, "a certified digital circuit engineer". They want you to design a
circuit that takes the temperature readings from a temperature sensor connected to
IoT motes placed on one of the plants and calculate the average and the standard
deviation of the readings.

Problem Statement and Solution

The problem is to find the moving average and the moving standard deviation of
the last 12 temperature readings from the temperature sensor. Suppose that there are 𝑛
temperature readings 𝑇!, 𝑇!, ⋯ , 𝑇! so far. If 𝑛 ≥ 12, then the moving average is
!
1
𝑇!"# = 𝑇! (1)
12
!!!!11

and the moving standard deviation is

! !
1 ! 1
𝜎= 𝑇! − 𝑇!"# = 𝑇! ! − 𝑇!"# ! (2)
12 12
!!!!11 !!!!11

If 𝑛 < 12, then the moving average and standard deviation of all 𝑛 readings should
be computed instead.

Design Specification

Assume the temperature sensor has a sensitivity of (2-5) oF and has a range of 0 oF
to 100 oF. The output of the temperature sensor is represented as a 12-bit
unsigned integer. For example, an output of 011000110100 represents (210 + 29 +
25 + 24 + 22) x 2-5 = 49.625 oF

The inputs and outputs of the circuit are specified in the block diagram below:
The circuit is initialized (i.e., forgetting all previous temperature readings and
starting from scratch) when RESET is set to 1. The circuit reads in one
temperature reading at a time. When the circuit is ready to read in a new
temperature, it will set SAMPLE to 1. The circuit will then read in a new
temperature reading TN and a mode of operation MODE at the next clock edge.
After that, the circuit will spend one or multiple clock cycles to process the
readings. When the processing is done, the circuit will set DONE to 1 and output
either the moving average temperature (if MODE=0) or the moving standard
deviation (if MODE=1) through AVG/SD.

We need to take the square root of the variance to find the standard deviation in
Equation (2). Square root is not easy to implement in hardware. In this project,
we will approximate the square root of variance 𝑉 by one iteration of the
Babylonian method described below:
1 𝑉
𝑉≈ 𝜎+ (3)
2 𝜎
where 𝜎 is a guess of 𝑉. For example, let 𝑉 = 810000. To find 810000, suppose we
!
guess that 810000 ≈ 1000. Therefore, we set 𝜎 = 1000. Then 810000 ≈ 1000 +
!
!"####
= 905, which is quite close to the exact value 810000 = 900. In this project,
!"""
to compute the current moving standard deviation, we set the value of 𝜎 to the
moving standard deviation computed when MODE was last set to 1. At the
beginning before any moving standard deviation is computed, we will use
𝜎 = 010000000000 (i.e., 32 oF).

To reduce the hardware cost, you should minimize the use of division. When
division is performed, the result should be rounded to the nearest integer. To
reduce the error due to rounding, the expressions should be manipulated so that
divisions are performed as late as possible. If divisions are performed too
early, the rounding errors will be propagated to and amplified by later
computation steps.

You have freedom to choose your design style and even to make changes to the
actual design specification (get feedback first on any change you wish to make).
We reserve the right to make adjustments to the project description as necessary.

Team Formation

Students may work in teams of two or three. For a team with more students, the
expectation of the final product will be higher.

Project Requirements

The basic requirement of the project is that the design should function correctly.
However, if a functional but unoptimized design is submitted, a passing but not
high score will be given. Techniques to optimize the timing, area and energy
consumption of the design should be applied in order to get a high score. Each
team should decide how much / which optimization will be performed.

Note that the power consumption by itself is not a good objective to optimize. The
power of a circuit can be reduced easily by breaking down the computations into
more clock cycles or by using a slower clock. However, the circuit does not really
become more efficient as a result. Instead, the energy consumption per
temperature reading, which equals (power consumption) x (# of clock cycles
required per temperature reading) x (clock cycle time), is a much more
appropriate optimization objective. The IoT motes will run on battery. The battery
life is inversely proportional to the energy consumption per temperature reading.
Minimizing the energy consumption per reading can extend the battery life.

All projects should be coded in Verilog, properly verified by ModelSim using the
given testbenches (and perhaps some additional testbenches), synthesized using
RTL Compiler and laid out using Encounter. Reports on timing, area and power of
the final design should be generated and discussed. Please do not change the
default switching activity parameter when performing power consumption analysis.

You are advised to carefully study the testbenches to ensure that you understand
the requirements of the project before you start designing the circuit.

Project Demonstration and Report

A 15-minute project demonstration needs to be performed by each team. The

main purpose of the project demo is to explain the design to the instructor/TA.

Besides, one project report needs to be submitted by each team. A formal final
report is required. The formal report must be typed neatly and hand-writing is not
acceptable. All graphs and figures must be labeled. All references must be properly
cited. The following sections must be included in the report:
1. Cover Page
• Date
• Project title
• Group Member Names
• Contributions of each team member
2. Introduction
• Describe the problem (do not simply take materials from this project
description).
• Briefly summarize what your team has done.
3. Detailed description of the design
• Describe design styles used, how the design works, any special design
features that you may have, etc.
• Include schematics and layouts of the final design.
• Include the timing, area and power reports by both RTL Compiler and
Encounter.
• Add a table summarizing the following of your design both after
synthesis and after layout:
 o clock period (in ns)
o slack (in ns)
o area (in µm2)
o average power consumption (in mW)
o average energy consumption per temperature reading
o latency (i.e., the # of clock cycles it takes to generate AVG/SD
after SAMPLE is asserted)
o throughput (i.e., the maximum # of temperature readings the
circuit can handle in 1 second)
4. Verilog codes of design
• Print the Verilog codes of all modules in your design.
5. Test results
• Include testbenches and results.
6. Conclusions and Discussions
• Report on difficulties and learning experiences
• Provide feedback on the project experience and any suggestions

Grading Criteria ( 200 % )

Grading is based on the following criteria:

1. Completeness – does project meet requirements? (20%)
2. Functionality – has it been tested thoroughly? does the final design work?
(20%)
3. Optimality – does the design achieve the best performance using the
smallest area, energy, time, etc.? (20%)
4. Modularity – was the project designed in small blocks that can be repeatedly
used? (20%)
5. Design methods – were proper design techniques employed? (20%)
6. Project Demonstration and Presentation ( 50% )
7. Report – is the report thorough, organized, and complete? (50%)

The above list is a qualitative description of the grading criteria. Your final project
score will reflect your effort in meeting the above criteria.

Important Dates

Important dates are listed below:

• The team composition must be submitted to one of the TA's

([email protected]) by email on or before Nov 15, 2019.
• The project report (hardcopy) will be due on Dec. 13, 2019 in class.
Please also submit a copy of the project report and all the design files
(Verilog codes, test benches, scripts, constraint files, etc.) to Canvas on this
day.
• The project demonstration will be done around Dec. 13, 2019. The
instructor and TA's will talk about the schedule for demonstration time a few
days in advance.