Ca3130, Ca3130A: 15Mhz, Bimos Operational Amplifier With Mosfet Input/Cmos Output Features
Ca3130, Ca3130A: 15Mhz, Bimos Operational Amplifier With Mosfet Input/Cmos Output Features
Ca3130, Ca3130A: 15Mhz, Bimos Operational Amplifier With Mosfet Input/Cmos Output Features
CA3130, CA3130A
1 AUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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CA3130, CA3130A
NOTES:
1. Short circuit may be applied to ground or to either supply.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
CA3130 CA3130A
TEST
PARAMETER SYMBOL CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Common-Mode CMRR 70 90 - 80 90 - dB
Rejection Ratio
I+ VO = 0V, - 2 3 - 2 3 mA
RL = ∞
2
CA3130, CA3130A
Electrical Specifications Typical Values Intended Only for Design Guidance, VSUPPLY = ±7.5V, TA = 25oC
Unless Otherwise Specified
CA3130,
PARAMETER SYMBOL TEST CONDITIONS CA3130A UNITS
Input Offset Voltage Adjustment Range 10kΩ Across Terminals 4 and 5 or ±22 mV
4 and 1
Slew Rate: SR
NOTE:
3. Although a 1MΩ source is used for this test, the equivalent input noise remains constant for values of RS up to 10MΩ.
Electrical Specifications Typical Values Intended Only for Design Guidance, V+ = 5V, V- = 0V, TA = 25oC
Unless Otherwise Specified (Note 4)
Input Current II 2 2 pA
100 100 dB
NOTE:
4. Operation at 5V is not recommended for temperatures below 25oC.
3
CA3130, CA3130A
Schematic Diagram
Q1 Q2 Q3
D1
Z1 D2
8.3V Q4 Q5
D3
R1 D4
40kΩ R
2
5kΩ SECOND
STAGE
INPUT STAGE
NON-INV. D5 D6 (NOTE 5) D7 D8
INPUT
3 OUTPUT
+ STAGE Q8
INV.-INPUT Q6 Q7 OUTPUT
2
- 6
R3 R4
1kΩ 1kΩ
Q9 Q10
Q12
Q11
R5 R6
1kΩ 1kΩ
NOTE:
5. Diodes D5 through D8 provide gate-oxide protection for MOSFET input stage.
Application Information
Circuit Description the output stage under the strobed “OFF” condition can only
Figure 1 is a block diagram of the CA3130 Series CMOS be achieved when the ohmic load resistance presented to
Operational Amplifiers. The input terminals may be operated the amplifier is very high (e.g.,when the amplifier output is
down to 0.5V below the negative supply rail, and the output used to drive CMOS digital circuits in Comparator
can be swung very close to either supply rail in many applications).
applications. Consequently, the CA3130 Series circuits are Input Stage
ideal for single-supply operation. Three Class A amplifier
The circuit of the CA3130 is shown in the schematic diagram.
stages, having the individual gain capability and current
It consists of a differential-input stage using PMOS field-effect
consumption shown in Figure 1, provide the total gain of the
transistors (Q6, Q7) working into a mirror-pair of bipolar
CA3130. A biasing circuit provides two potentials for
transistors (Q9, Q10) functioning as load resistors together
common use in the first and second stages.
with resistors R3 through R6.
Terminal 8 can be used both for phase compensation and to
The mirror-pair transistors also function as a differential-to-
strobe the output stage into quiescence. When Terminal 8 is
single-ended converter to provide base drive to the second-
tied to the negative supply rail (Terminal 4) by mechanical or
stage bipolar transistor (Q11). Offset nulling, when desired,
electrical means, the output potential at Terminal 6
can be effected by connecting a 100,000Ω potentiometer
essentially rises to the positive supply-rail potential at
across Terminals 1 and 5 and the potentiometer slider arm to
Terminal 7. This condition of essentially zero current drain in
Terminal 4.
4
CA3130, CA3130A
current sources for both the first and second amplifier stages,
V+
CA3130 respectively.
7
200µA 1.35mA 200µA 8mA At total supply voltages somewhat less than 8.3V, zener
(NOTE 5)
BIAS CKT. 0mA diode Z1 becomes nonconductive and the potential,
(NOTE 7)
developed across series-connected R1, D1-D4, and Q1,
+
varies directly with variations in supply voltage.
OUTPUT Consequently, the gate bias for Q4, Q5 and Q2, Q3 varies in
3
AV ≈ AV ≈ accordance with supply-voltage variations. This variation
INPUT AV ≈ 5X 6000X 30X 6
2
results in deterioration of the power-supply-rejection ratio
- V-
(PSRR) at total supply voltages below 8.3V. Operation at
total supply voltages below about 4.5V results in seriously
4
degraded performance.
CC
5 1 8 STROBE Output Stage
COMPENSATION
OFFSET (WHEN REQUIRED) The output stage consists of a drain-loaded inverting
NULL amplifier using CMOS transistors operating in the Class A
NOTES: mode. When operating into very high resistance loads, the
6. Total supply voltage (for indicated voltage gains) = 15V with input output can be swung within millivolts of either supply rail.
terminals biased so that Terminal 6 potential is +7.5V above Because the output stage is a drain-loaded amplifier, its gain
Terminal 4. is dependent upon the load impedance. The transfer
7. Total supply voltage (for indicated voltage gains) = 15V with characteristics of the output stage for a load returned to the
output terminal driven to either supply rail.
negative supply rail are shown in Figure 2. Typical op amp
FIGURE 1. BLOCK DIAGRAM OF THE CA3130 SERIES loads are readily driven by the output stage. Because large-
Cascade-connected PMOS transistors Q2, Q4 are the signal excursions are non-linear, requiring feedback for good
constant-current source for the input stage. The biasing circuit waveform reproduction, transient delays may be
for the constant-current source is subsequently described. encountered. As a voltage follower, the amplifier can
achieve 0.01% accuracy levels, including the negative
The small diodes D5 through D8 provide gate-oxide protection supply rail.
against high-voltage transients, including static electricity
during handling for Q6 and Q7. NOTE:
8. For general information on the characteristics of CMOS
Second-Stage transistor-pairs in linear-circuit applications, see File Number
Most of the voltage gain in the CA3130 is provided by the 619, data sheet on CA3600E “CMOS Transistor Array”.
second amplifier stage, consisting of bipolar transistor Q11
OUTPUT VOLTAGE (TERMINALS 4 AND 8) (V)
5
CA3130, CA3130A
Input Current Variation with Common Mode Input typical variation of input bias current as a function of
Voltage temperature in the CA3130.
As shown in the Table of Electrical Specifications, the input
4000
current for the CA3130 Series Op Amps is typically 5pA at VS = ±7.5V
TA = 25oC when Terminals 2 and 3 are at a common-mode 1000
potential of +7.5V with respect to negative supply Terminal
package also contributes an increment of leakage current, FIGURE 4. INPUT CURRENT vs TEMPERATURE
there are useful compensating factors. Because the gate- In applications requiring the lowest practical input current
protection network functions as if it is connected to Terminal and incremental increases in current because of “warm-up”
4 potential, and the Metal Can case of the CA3130 is also effects, it is suggested that an appropriate heat sink be used
internally tied to Terminal 4, input Terminal 3 is essentially with the CA3130. In addition, when “sinking” or “sourcing”
“guarded” from spurious leakage currents. significant output current the chip temperature increases,
10 causing an increase in the input current. In such cases, heat-
TA = 25oC
sinking can also very markedly reduce and stabilize input
current variations.
15V
7.5
INPUT VOLTAGE (V)
6
CA3130, CA3130A
7
TA = 125oC FOR TO-5 PACKAGES supply) decreases correspondingly. When the gate terminals
OFFSET VOLTAGE SHIFT (mV)
Wideband Noise
Power-Supply Considerations From the standpoint of low-noise performance
Because the CA3130 is very useful in single-supply considerations, the use of the CA3130 is most
applications, it is pertinent to review some considerations advantageous in applications where in the source resistance
relating to power-supply current consumption under both of the input signal is on the order of 1MΩ or more. In this
single-and dual-supply service. Figures 6A and 6B show the case, the total input-referred noise voltage is typically only
CA3130 connected for both dual-and single-supply 23µV when the test-circuit amplifier of Figure 7 is operated at
operation. a total supply voltage of 15V. This value of total input-
referred noise remains essentially constant, even though the
Dual-supply Operation: When the output voltage at Terminal
value of source resistance is raised by an order of
6 is 0V, the currents supplied by the two power supplies are
magnitude. This characteristic is due to the fact that
equal. When the gate terminals of Q8 and Q12 are driven
reactance of the input capacitance becomes a significant
increasingly positive with respect to ground, current flow
factor in shunting the source resistance. It should be noted,
through Q12 (from the negative supply) to the load is
7
CA3130, CA3130A
however, that for values of source resistance very much with CMOS input logic, e.g., 10V logic levels are used in the
greater than 1MΩ, the total noise voltage generated can be circuit of Figure 10.
dominated by the thermal noise contributions of both the
The circuit uses an R/2R voltage-ladder network, with the
feedback and source resistors.
output potential obtained directly by terminating the ladder
+7.5V arms at either the positive or the negative power-supply
terminal. Each CD4007A contains three “inverters”, each
“inverter” functioning as a single-pole double-throw switch to
terminate an arm of the R/2R network at either the positive
0.01µF
Rs 7
or negative power-supply terminal. The resistor ladder is an
3 + NOISE
assembly of 1% tolerance metal-oxide film resistors. The five
1MΩ 6 VOLTAGE arms requiring the highest accuracy are assembled with
2 - OUTPUT
series and parallel combinations of 806,000Ω resistors from
4
the same manufacturing lot.
8 30.1kΩ
1
0.01 A single 15V supply provides a positive bus for the CA3130
µF
follower amplifier and feeds the CA3085 voltage regulator. A
47pF -7.5V
“scale-adjust” function is provided by the regulator output
control, set to a nominal 10V level in this system. The line-
BW (-3dB) = 200kHz 1kΩ
TOTAL NOISE VOLTAGE (REFERRED voltage regulation (approximately 0.2%) permits a 9-bit
TO INPUT) = 23µV (TYP) accuracy to be maintained with variations of several volts in
FIGURE 7. TEST-CIRCUIT AMPLIFIER (30-dB GAIN) USED the supply. The flexibility afforded by the CMOS building
FOR WIDEBAND NOISE MEASUREMENTS blocks simplifies the design of DAC systems tailored to
particular needs.
Typical Applications
Single-Supply, Absolute-Value, Ideal Full-Wave
Voltage Followers
Rectifier
Operational amplifiers with very high input resistances, like
The absolute-value circuit using the CA3130 is shown in
the CA3130, are particularly suited to service as voltage
Figure 11. During positive excursions, the input signal is fed
followers. Figure 8 shows the circuit of a classical voltage
through the feedback network directly to the output.
follower, together with pertinent waveforms using the
Simultaneously, the positive excursion of the input signal
CA3130 in a split-supply configuration.
also drives the output terminal (No. 6) of the inverting
A voltage follower, operated from a single supply, is shown amplifier in a negative-going excursion such that the 1N914
in Figure 9, together with related waveforms. This follower diode effectively disconnects the amplifier from the signal
circuit is linear over a wide dynamic range, as illustrated by path. During a negative-going excursion of the input signal,
the reproduction of the output waveform in Figure 9A with the CA3130 functions as a normal inverting amplifier with a
input-signal ramping. The waveforms in Figure 9B show that gain equal to -R2/R1. When the equality of the two equations
the follower does not lose its input-to-output phase-sense, shown in Figure 11 is satisfied, the full-wave output is
even though the input is being swung 7.5V below ground symmetrical.
potential. This unique characteristic is an important attribute
Peak Detectors
in both operational amplifier and comparator applications.
Figure 9B also shows the manner in which the CMOS output Peak-detector circuits are easily implemented with the
stage permits the output signal to swing down to the CA3130, as illustrated in Figure 12 for both the peak-positive
negative supply-rail potential (i.e., ground in the case and the peak-negative circuit. It should be noted that with
shown). The digital-to-analog converter (DAC) circuit, large-signal inputs, the bandwidth of the peak-negative
described later, illustrates the practical use of the CA3130 in circuit is much less than that of the peak-positive circuit. The
a single-supply voltage-follower application. second stage of the CA3130 limits the bandwidth in this
case. Negative-going output-signal excursion requires a
9-Bit CMOS DAC positive-going signal excursion at the collector of transistor
A typical circuit of a 9-bit Digital-to-Analog Converter (DAC) Q11, which is loaded by the intrinsic capacitance of the
is shown in Figure 10. This system combines the concepts of associated circuitry in this mode. On the other hand, during a
multiple-switch CMOS lCs, a low-cost ladder network of negative-going signal excursion at the collector of Q11, the
discrete metal-oxide-film resistors, a CA3130 op amp transistor functions in an active “pull-down” mode so that the
connected as a follower, and an inexpensive monolithic intrinsic capacitance can be discharged more expeditiously.
regulator in a simple single power-supply arrangement. An
additional feature of the DAC is that it is readily interfaced
8
CA3130, CA3130A
+7.5V +15V
0.01µF 0.01µF
7 7
3 +
3 + 10kΩ
10kΩ 6 6
2 - 2 -
4 2kΩ
4
8
5
1 1
0.01µF 25pF 8 100kΩ
-7.5V
CC = 56pF 56pF OFFSET
2kΩ ADJUST
2kΩ
BW (-3dB) = 4MHz
SR = 10V/µs 0.1µF
0.1µF
9
CA3130, CA3130A
806K 750K
806K 1% 1%
1% PARALLELED
RESISTORS
10K
+15V
VOLTAGE
REGULATOR 62
+15V 7
1 + 3
OUTPUT
2 +10.010V CA3130 VOLTAGE
6 FOLLOWER
CA3085 8
- 2
3 LOAD 4
22.1k 5
6 1% 1
7 8
+ REGULATED
2µF 4 56pF
1K VOLTAGE 100K
- 25V ADJ OFFSET
0.001µF
3.83k NULL 2K
1%
0.1µF
FIGURE 10. 9-BIT DAC USING CMOS DIGITAL SWITCHES AND CA3130
R2
2kΩ +15V
0.01
R1 µF
2 - 7
4kΩ CA3130 6
3 + 1N914 0V
4 5.1kΩ
5
1
8 R3
PEAK
20pF 100kΩ ADJUST
OFFSET 2kΩ
ADJUST
0V
R2 R3
Gain = ------- = X = -------------------------------------
R1 R1 + R2 + R3
2
2KΩ R 2
R 3 = R 1 ------------------
X+X
For X = 0.5: ------------ = -------
1-X 4kΩ R 1 Top Trace: Output Signal; 2V/Div.
Bottom Trace: Input Signal; 10V/Div.
R 3 = 4kΩ ----------- = 6kΩ
0.75 Time base on both traces: 0.2ms/Div.
0.5
20VP-P Input: BW(-3dB) = 230kHz, DC Output (Avg) = 3.2V
1VP-P Input: BW(-3dB) = 130kHz, DC Output (Avg) = 160mV
FIGURE 11. SINGLE SUPPLY, ABSOLUTE VALUE, IDEAL FULL-WAVE RECTIFIER WITH ASSOCIATED WAVEFORMS
10
CA3130, CA3130A
6VP-P INPUT;
6VP-P INPUT; +7.5V
+7.5V BW (-3dB) = 360kHz
BW (-3dB) = 1.3MHz
0.3VP-P INPUT;
0.3VP-P INPUT; 0.01µF
0.01µF BW (-3dB) = 320kHz
BW (-3dB) = 240kHz 7 -DC
7 +DC 3 + OUTPUT
3 + OUTPUT 10kΩ CA3130 6
10kΩ CA3130 6
2 -
2 - 1N914
1N914
4 -
4 + 100 5µF
100 5µF kΩ
kΩ +
- 0.01µF
0.01µF
2kΩ -7.5V
2kΩ -7.5V
FIGURE 12A. PEAK POSITIVE DETECTOR CIRCUIT FIGURE 12B. PEAK NEGATIVE DETECTOR CIRCUIT
FIGURE 12. PEAK-DETECTOR CIRCUITS
CURRENT
LIMIT
ADJ
3Ω
+
R2
1kΩ
IC3 1kΩ
CA3086 Q5 13
10 7 3 12 14
Q4 Q3 Q2 Q1
9 6 2 4
11 8 1 5
+ OUTPUT
20kΩ
0 TO 13V
390Ω 1kΩ AT
56pF
40mA
+
5µF
2.2kΩ 25V
0.01µF -
ERROR
1 AMPLIFIER
+
25µF 8
IC2 - 7
+20V CA3086 10 11 1, 2 - 2
INPUT Q4 Q1 6 CA3130
9 3 +
IC1 3
8, 7 5
Q2 30kΩ
Q3 Q5 14 4
6 4 100kΩ
R1
12 13 50kΩ
VOLTAGE
ADJUST 0.01
62kΩ µF
- -
REGULATION (NO LOAD TO FULL LOAD): <0.01%
INPUT REGULATION: 0.02%/V
HUM AND NOISE OUTPUT: <25µV UP TO 100kHz
11
CA3130, CA3130A
2N3055 Q2 1Ω
+ +
10kΩ
2N2102
1kΩ CURRENT
4.3kΩ Q1 LIMIT
1W ADJUST
Q3
3.3kΩ
1W
2N5294
+
43kΩ
+ 1000pF 100µF
100µF -
- 2.2kΩ
1 ERROR OUTPUT:
+55V + AMPLIFIER
5µF 8 0.1 TO 50V
INPUT IC2 - 7
2N2102 AT 1A
+ 3
CA3086 10, 11 1, 2
10kΩ
6 CA3130
Q4 Q1
9 3 Q5 14 IC1 - 2
Q4
8, 7 5
12 13 4
Q3 Q2 8.2kΩ
6 4
1kΩ 50kΩ
VOLTAGE
62kΩ ADJUST
- -
REGULATION (NO LOAD TO FULL LOAD): <0.005%
INPUT REGULATION: 0.01%/V
HUM AND NOISE OUTPUT: <250µVRMS UP TO 100kHz
12
CA3130, CA3130A
The heart of the frequency-determining system is an The amplifier circuit in Figure 17 employs feedback to
operational-transconductance-amplifier (OTA) (see Note 10), establish a closed-loop gain of 48dB. The typical large-signal
lC1, operated as a voltage-controlled current-source. The bandwidth (-3dB) is 50kHz.
output, IO, is a current applied directly to the integrating
NOTE:
capacitor, C1, in the feedback loop of the integrator lC2, using 9. See file number 619 for technical information.
a CA3130, to provide the triangular-wave output.
+15V
Potentiometer R2 is used to adjust the circuit for slope
symmetry of positive-going and negative-going signal
excursions. 0.01µF
ON-PERIOD OFF-PERIOD
Another CA3130, IC3, is used as a controlled switch to set the R1 ADJUST ADJUST
excursion limits of the triangular output from the integrator 100kΩ 1MΩ 1MΩ
270kΩ INTEGRATOR
VOLTAGE-CONTROLLED C1
CURRENT SOURCE THRESHOLD
+7.5V HIGH - FREQ. DETECTOR
100pF ADJUST
7 +7.5V 3 - 30pF 150kΩ
IC1
IC2 +7.5V
3 + IO 7
C2 IC3
3kΩ - 7
3kΩ 6 2
2 - CA3080A CA3130 6 3 +
4 (NOTE 10) 3 + 39kΩ CA3130 6
+7.5V 5 -7.5V
4
2 -
10MΩ 8 4
+7.5V 1 5
R2 -7.5V 1
100kΩ SLOPE 22kΩ
R3
SYMMETRY 10kΩ 56pF
100kΩ
ADJUST
FREQUENCY
-7.5V VOLTAGE ADJUST AMPLITUDE
R1
CONTROLLED 10kΩ (100kHz MAX) SYMMETRY
INPUT ADJUST
-7.5V
-7.5V
NOTE:
10. See file number 475 and AN6668 for technical information.
FIGURE 16. FUNCTION GENERATOR (FREQUENCY CAN BE VARIED 1,000,000/1 WITH A SINGLE CONTROL)
13
CA3130, CA3130A
+15V
0.01µF 14 2 11
1MΩ
1µF CA3600E
(NOTE 12) QP1 QP2 QP3
7
750kΩ
3 +
CA3130 13 1
2kΩ 6
INPUT 2 -
500µF
1µF
8 6 3 10 12
4 RL = 100Ω
(PO = 150mW
AT THD = 10%)
8 5
AV(CL) = 48dB
LARGE SIGNAL QN1 QN2 QN3
BW (-3 dB) = 50kHz
7 4 9
510kΩ
NOTES:
11. Transistors QP1, QP2, QP3 and QN1, QN2, QN3 are parallel connected with Q8 and Q12, respectively, of the CA3130.
12. See file number 619.
FIGURE 17. CMOS TRANSISTOR ARRAY (CA3600E) CONNECTED AS POWER BOOSTER IN THE OUTPUT STAGE OF THE CA3130
150
140 1 3
80
2
130 2 -200
60 3
120 1
-300
40 4
110
100 20
90 0
101 102 103 104 105 106 107 108
80 FREQUENCY (Hz)
-100 -50 0 50 100
1 - CL = 9pF, CC = 0pF, RL = ∞
TEMPERATURE (oC) 2 - CL = 30pF, CC = 15pF, RL = 2kΩ
3 - CL = 30pF, CC = 47pF, RL = 2kΩ
4 - CL = 30pF, CC = 150pF, RL = 2kΩ
FIGURE 18. OPEN LOOP GAIN vs TEMPERATURE FIGURE 19. OPEN-LOOP RESPONSE
14
CA3130, CA3130A
17.5
∞ 14
QUIESCENT SUPPLY CURRENT (mA)
LOAD RESISTANCE =
TA = 25oC OUTPUT VOLTAGE = V+/2
10
10 25oC
8 125oC
7.5
6
5
OUTPUT VOLTAGE HIGH = V+ 4
OR LOW = V-
2.5
2
0
0
4 6 8 10 12 14 16 18 0 2 4 6 8 10 12 14 16
TOTAL SUPPLY VOLTAGE (V) TOTAL SUPPLY VOLTAGE (V)
FIGURE 20. QUIESCENT SUPPLY CURRENT vs SUPPLY FIGURE 21. QUIESCENT SUPPLY CURRENT vs SUPPLY
VOLTAGE VOLTAGE
50 50
VOLTAGE DROP ACROSS PMOS OUTPUT
1 1
0.1 0.1
0.01 0.01
0.001 0.001
0.001 0.01 0.1 1.0 10 100 0.001 0.01 0.1 1 10 100
MAGNITUDE OF LOAD CURRENT (mA) MAGNITUDE OF LOAD CURRENT (mA)
FIGURE 22. VOLTAGE ACROSS PMOS OUTPUT TRANSISTOR FIGURE 23. VOLTAGE ACROSS NMOS OUTPUT TRANSISTOR
(Q8) vs LOAD CURRENT (Q12) vs LOAD CURRENT
15
CA3130, CA3130A
N
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX INCHES MILLIMETERS
AREA 1 2 3 N/2
SYMBOL MIN MAX MIN MAX NOTES
-B-
A - 0.210 - 5.33 4
-A-
D E A1 0.015 - 0.39 - 4
BASE A2 0.115 0.195 2.93 4.95 -
PLANE A2
-C- A
B 0.014 0.022 0.356 0.558 -
SEATING
PLANE L C B1 0.045 0.070 1.15 1.77 8, 10
L
D1 A1 eA C 0.008 0.014 0.204 0.355 -
D1
B1 e D 0.355 0.400 9.01 10.16 5
eC C
B
eB D1 0.005 - 0.13 - 5
0.010 (0.25) M C A B S
E 0.300 0.325 7.62 8.25 6
NOTES: E1 0.240 0.280 6.10 7.11 5
1. Controlling Dimensions: INCH. In case of conflict between
e 0.100 BSC 2.54 BSC -
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 7.62 BSC 6
3. Symbols are defined in the “MO Series Symbol List” in Section eB - 0.430 - 10.92 7
2.2 of Publication No. 95. L 0.115 0.150 2.93 3.81 4
4. Dimensions A, A1 and L are measured with the package seated
N 8 8 9
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protru- Rev. 0 12/93
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and eA are measured with the leads constrained to be per-
pendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
16
CA3130, CA3130A
N
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
INDEX
AREA H 0.25(0.010) M B M PACKAGE
E
INCHES MILLIMETERS
-B- SYMBOL MIN MAX MIN MAX NOTES
A 0.0532 0.0688 1.35 1.75 -
1 2 3
L A1 0.0040 0.0098 0.10 0.25 -
-C-
E 0.1497 0.1574 3.80 4.00 4
µα e 0.050 BSC 1.27 BSC -
e A1
C H 0.2284 0.2440 5.80 6.20 -
B 0.10(0.004) h 0.0099 0.0196 0.25 0.50 5
0.25(0.010) M C A M B S L 0.016 0.050 0.40 1.27 6
N 8 8 7
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of α 0o 8o 0o 8o -
Publication Number 95. Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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